| commit | b600658e8d293f533640150d81f62add096cbea1 | |
| author | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Tue, 21 Feb 2012 15:38:35 +0000 (21 15:38 +0000) | ||
| committer | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Tue, 21 Feb 2012 15:38:35 +0000 (21 15:38 +0000) | ||
| tree | 48fe59a405330210ecee291dec3ae758c92a7b2c | treesnapshot (tar.gz zip) |
| parent | b65fb916523c33760decb9c771facaaf078853ad | commitdiff |
PR target/52294
* thumb2.md (thumb2_shiftsi3_short): Split register and
immediate shifts. For register shifts tie operands 0 and 1.
(peephole2 for above): Check that register-controlled shifts
have suitably tied operands.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@184442 138bc75d-0d04-0410-961f-82ee72b054a4
* thumb2.md (thumb2_shiftsi3_short): Split register and
immediate shifts. For register shifts tie operands 0 and 1.
(peephole2 for above): Check that register-controlled shifts
have suitably tied operands.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@184442 138bc75d-0d04-0410-961f-82ee72b054a4
| gcc/ChangeLog | diffblobblamehistory | |
| gcc/config/arm/thumb2.md | diffblobblamehistory |