[AArch64] Fix wrong-code bug in right-shift SISD patterns
commitaadc98cba323ded6db12b72efd0caedcbb999cb7
authorktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 20 Feb 2015 14:05:51 +0000 (20 14:05 +0000)
committerktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 20 Feb 2015 14:05:51 +0000 (20 14:05 +0000)
tree4cf8cd26b5ea9500187020a5b5fad34f124e8436
parent382167e867242a237c2b7784de32d7737936ca33
[AArch64] Fix wrong-code bug in right-shift SISD patterns

* config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_<mode>3):
Mark operand 0 as earlyclobber in 2nd alternative.
(1st define_split below *aarch64_lshr_sisd_or_int_<mode>3):
Write negated shift amount into QI lowpart operand 0 and use it
in the shift step.
(2nd define_split below *aarch64_lshr_sisd_or_int_<mode>3): Likewise.

* gcc.target/aarch64/sisd-shft-neg_1.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220860 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/aarch64/aarch64.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/sisd-shft-neg_1.c [new file with mode: 0644]