gcc/ChangeLog:
commita7aebe6129ec96ef58cc5b92a7daa4eadd026495
authorcarll <carll@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 11 Dec 2017 22:47:34 +0000 (11 22:47 +0000)
committercarll <carll@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 11 Dec 2017 22:47:34 +0000 (11 22:47 +0000)
treeae73ea8b31136475fa92588f0693a5592a7fa797
parent28a5212f1ea4fdd24a8d6cabf2a175075ad291fb
gcc/ChangeLog:

2017-12-11  Carl Love  <cel@us.ibm.com>

* config/rs6000/altivec.h (vec_extract_fp32_from_shorth,
vec_extract_fp32_from_shortl]): Add #defines.
* config/rs6000/rs6000-builtin.def (VSLDOI_2DI): Add macro expansion.
* config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_UNPACKH,
ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_AND,
ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SRL,
ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VEC_SLD,
ALTIVEC_BUILTIN_VEC_SLL): Add expansions.
* doc/extend.texi: Add documentation for the added builtins.

gcc/testsuite/ChangeLog:

2017-12-11  Carl Love  <cel@us.ibm.com>
* gcc.target/powerpc/altivec-7.c: Renamed altivec-7.h.
* gcc.target/powerpc/altivec-7.h (main): Add testcases for vec_unpackl.
Add dg-final tests for the instructions generated.
* gcc.target/powerpc/altivec-7-be.c: New file to test on big endian.
* gcc.target/powerpc/altivec-7-le.c: New file to test on little endian.
* gcc.target/powerpc/altivec-13.c (foo): Add vec_sld, vec_srl,
 vec_sro testcases. Add dg-final tests for the instructions generated.
* gcc.target/powerpc/builtins-3-p8.c (test_vsi_packs_vui,
test_vsi_packs_vsi, test_vsi_packs_vssi, test_vsi_packs_vusi,
test_vsi_packsu-vssi, test_vsi_packsu-vusi, test_vsi_packsu-vsll,
test_vsi_packsu-vull, test_vsi_packsu-vsi, test_vsi_packsu-vui): Add
testcases. Add dg-final tests for new instructions.
* gcc.target/powerpc/p8vector-builtin-2.c (vbschar_eq, vbchar_eq,
vuchar_eq, vbint_eq, vsint_eq, viint_eq, vuint_eq, vbool_eq, vbint_ne,
vsint_ne, vuint_ne, vbool_ne, vsign_ne, vuns_ne, vbshort_ne): Add
tests.
Add dg-final instruction tests.
* gcc.target/powerpc/vsx-vector-6.c: Renamed vsx-vector-6.h.
* gcc.target/powerpc/vsx-vector-6.h (vec_andc,vec_nmsub, vec_nmadd,
vec_or, vec_nor, vec_andc, vec_or, vec_andc, vec_msums): Add tests.
Add dg-final tests for the generated instructions.
* gcc.target/powerpc/builtins-3.c (test_sll_vsc_vsc_vsuc,
test_sll_vuc_vuc, test_sll_vsi_vsi_vuc, test_sll_vui_vui_vuc,
test_sll_vbll_vull, test_sll_vbll_vbll_vus, test_sll_vp_vp_vuc,
test_sll_vssi_vssi_vuc, test_sll_vusi_vusi_vuc, test_slo_vsc_vsc_vsc,
test_slo_vuc_vuc_vsc, test_slo_vsi_vsi_vsc, test_slo_vsi_vsi_vuc,
test_slo_vui_vui_vsc, test_slo_vui_vui_vuc, test_slo_vsll_slo_vsll_vsc,
test_slo_vsll_slo_vsll_vuc, test_slo_vull_slo_vull_vsc,
test_slo_vull_slo_vull_vuc, test_slo_vp_vp_vsc, test_slo_vp_vp_vuc,
test_slo_vssi_vssi_vsc, test_slo_vssi_vssi_vuc, test_slo_vusi_vusi_vsc,
test_slo_vusi_vusi_vuc, test_slo_vusi_vusi_vuc, test_slo_vf_vf_vsc,
test_slo_vf_vf_vuc, test_cmpb_float): Add tests.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@255555 138bc75d-0d04-0410-961f-82ee72b054a4
16 files changed:
gcc/ChangeLog
gcc/config/rs6000/altivec.h
gcc/config/rs6000/rs6000-builtin.def
gcc/config/rs6000/rs6000-c.c
gcc/doc/extend.texi
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/altivec-13.c
gcc/testsuite/gcc.target/powerpc/altivec-7-be.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/altivec-7-le.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/altivec-7.h [moved from gcc/testsuite/gcc.target/powerpc/altivec-7.c with 82% similarity]
gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
gcc/testsuite/gcc.target/powerpc/builtins-3.c
gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h [moved from gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c with 50% similarity]