| commit | 9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0 | |
| author | Thomas Schwinge <thomas@codesourcery.com> | |
| Thu, 16 Nov 2023 22:17:36 +0000 (16 23:17 +0100) | ||
| committer | Thomas Schwinge <thomas@codesourcery.com> | |
| Thu, 30 Nov 2023 14:42:57 +0000 (30 15:42 +0100) | ||
| tree | 279ac00a8da15901d41b0600a74b45aede3bd1f3 | treesnapshot (tar.gz zip) |
| parent | 318f5232cfb3e0c9694889565e1f5424d0354463 | commitdiff |
GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases
... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787
"amdgcn: Add Accelerator VGPR registers". This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.
gcc/testsuite/
* gcc.target/gcn/avgpr-mem-double.c: Remove
'dg-skip-if "incompatible ISA" [...]'.
* gcc.target/gcn/avgpr-mem-int.c: Likewise.
* gcc.target/gcn/avgpr-mem-long.c: Likewise.
* gcc.target/gcn/avgpr-mem-short.c: Likewise.
* gcc.target/gcn/avgpr-spill-double.c: Likewise.
* gcc.target/gcn/avgpr-spill-int.c: Likewise.
* gcc.target/gcn/avgpr-spill-long.c: Likewise.
* gcc.target/gcn/avgpr-spill-short.c: Likewise.
... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787
"amdgcn: Add Accelerator VGPR registers". This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.
gcc/testsuite/
* gcc.target/gcn/avgpr-mem-double.c: Remove
'dg-skip-if "incompatible ISA" [...]'.
* gcc.target/gcn/avgpr-mem-int.c: Likewise.
* gcc.target/gcn/avgpr-mem-long.c: Likewise.
* gcc.target/gcn/avgpr-mem-short.c: Likewise.
* gcc.target/gcn/avgpr-spill-double.c: Likewise.
* gcc.target/gcn/avgpr-spill-int.c: Likewise.
* gcc.target/gcn/avgpr-spill-long.c: Likewise.
* gcc.target/gcn/avgpr-spill-short.c: Likewise.