Fix atomic operations on PA-RISC 2.0 processors.

Fix atomic operations on PA-RISC 2.0 processors.

PA-RISC 2.0 supports out-of-order execution for loads and stores.
Thus, we need to synchonize memory accesses.

This change revises the lock releases in __exchange_and_add and
__atomic_add to use an ordered store with release semantics.  We
also use an ordered load in the inner spin loop.

We use the "ldcw,co" instruction instead of "ldcw" when compiled
for PA 2.0.  Most PA 2.0 processors are coherent and can execute
the ldcw instruction in cache for improved performance.

Finally, the inner spin loop is revised to immediately branch to
the ldcw instruction when it detects the lock is free.

2023-01-05  John David Anglin  <danglin@gcc.gnu.org>

libstdc++-v3/ChangeLog:

	* config/cpu/hppa/atomicity.h (_PA_LDCW_INSN): Define.
	(__exchange_and_add): Use _PA_LDCW_INSN.  Use ordered store for
	lock release.  Revise loop.
	(__atomic_add): Likewise.