PR target/48605
commit908f63e8cef8d356ea669f4b85d41abb626db959
authorjakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 14 Apr 2011 21:30:37 +0000 (14 21:30 +0000)
committerjakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 14 Apr 2011 21:30:37 +0000 (14 21:30 +0000)
treed29b70a327471a0ddf109fe2ca38f6fa09cc3315
parenta758bf7d89253cc93d0a0773a138610ea3d2e97d
PR target/48605
* config/i386/sse.md (sse4_1_insertps): If operands[2] is a MEM,
offset it as needed based on top 2 bits in operands[3], change
MEM mode to SFmode and mask those 2 bits away from operands[3].

* gcc.target/i386/sse4_1-insertps-3.c: New test.
* gcc.target/i386/sse4_1-insertps-4.c: New test.
* gcc.target/i386/avx-insertps-3.c: New test.
* gcc.target/i386/avx-insertps-4.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@172458 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/i386/sse.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c [new file with mode: 0644]