| commit | 8da6e78e68cb290a046135f0d8c5b40e28805f5d | |
| author | wilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Thu, 8 Dec 2016 19:18:33 +0000 (8 19:18 +0000) | ||
| committer | wilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Thu, 8 Dec 2016 19:18:33 +0000 (8 19:18 +0000) | ||
| tree | e2fecc79734bfc862c1cce548342eddf0fd76f1f | treesnapshot (tar.gz zip) |
| parent | 64215350809ec3d3ed76ab210223819845b4e0cc | commitdiff |
This patch fixes an issue in aarch64_classify_address. TImode and TFmode
can either use a 64-bit LDP/STP or 128-bit LDR/STR. The addressing mode
must be carefully modelled as the intersection of both. This is done for
the immediate offsets, however load_store_pair_p must be set as well to
avoid LDP with a PC-relative address if aarch64_pcrelative_literal_loads
is true.
gcc/
PR target/78733
* config/aarch64/aarch64.c (aarch64_classify_address):
Set load_store_pair_p for TImode and TFmode.
testsuite/
* gcc.target/aarch64/pr78733.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243456 138bc75d-0d04-0410-961f-82ee72b054a4
can either use a 64-bit LDP/STP or 128-bit LDR/STR. The addressing mode
must be carefully modelled as the intersection of both. This is done for
the immediate offsets, however load_store_pair_p must be set as well to
avoid LDP with a PC-relative address if aarch64_pcrelative_literal_loads
is true.
gcc/
PR target/78733
* config/aarch64/aarch64.c (aarch64_classify_address):
Set load_store_pair_p for TImode and TFmode.
testsuite/
* gcc.target/aarch64/pr78733.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243456 138bc75d-0d04-0410-961f-82ee72b054a4
| gcc/ChangeLog | diffblobblamehistory | |
| gcc/config/aarch64/aarch64.c | diffblobblamehistory | |
| gcc/testsuite/ChangeLog | diffblobblamehistory |