[AArch64] PR target/85512: Tighten SIMD right shift immediate constraints

[AArch64] PR target/85512: Tighten SIMD right shift immediate constraints

In this testcase it is possible to generate an invalid SISD shift of zero:
Error: immediate value out of range 1 to 64 at operand 3 -- `sshr v9.2s,v0.2s,0'

The SSHR and USHR instructions require a shift from 1 up to the element size.
However our constraints on the scalar shifts that generate these patterns
allow a shift amount of zero as well. The pure GP-reg ASR and LSR instructions allow a shift amount of zero.

It is unlikely that a shift of zero will survive till the end of compilation, but it's not impossible, as this PR shows.

The patch tightens up the constraints in the offending patterns by adding two new constraints
that allow shift amounts [1,32] and [1,64] and using them in *aarch64_ashr_sisd_or_int_<mode>3
and *aarch64_lshr_sisd_or_int_<mode>3.
The left-shift SISD instructions SHL and USHL allow a shift amount of zero so don't need adjustment
The vector shift patterns that map down to SSHR and USHR already enforce the correct immediate range.

        PR target/85512
        * config/aarch64/constraints.md (Usg, Usj): New constraints.
        * config/aarch64/iterators.md (cmode_simd): New mode attribute.
        * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3):
        Use the above on operand 2.  Reindent.
        (*aarch64_lshr_sisd_or_int_<mode>3): Likewise.

        * gcc.dg/pr85512.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@259614 138bc75d-0d04-0410-961f-82ee72b054a4