[gcc]

[gcc]
2017-05-05  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/79038
	PR target/79202
	PR target/79203
	* config/rs6000/rs6000.md (u code attribute): Add FIX and
	UNSIGNED_FIX.
	(extendsi<mode>2): Add support for doing sign extension via
	VUPKHSW and XXPERMDI if the value is in Altivec registers and we
	don't have ISA 3.0 instructions.
	(extendsi<mode>2 splitter): Likewise.
	(fix_trunc<mode>si2): If we are at ISA 2.07 (VSX small integer),
	generate the normal insns since SImode can now go in vector
	registers.  Disallow the special UNSPECs needed for previous
	machines to hide SImode being used.  Add new insns
	fctiw{,w}_<mode>_smallint if SImode can go in vector registers.
	(fix_trunc<mode>si2_stfiwx): Likewise.
	(fix_trunc<mode>si2_internal): Likewise.
	(fixuns_trunc<mode>si2): Likewise.
	(fixuns_trunc<mode>si2_stfiwx): Likewise.
	(fctiw<u>z_<mode>_smallint): Likewise.
	(fctiw<u>z_<mode>_mem): New combiner pattern to prevent conversion
	of floating point to 32-bit integer from doing a direct move to
	the GPR registers to do a store.
	(fctiwz_<mode>): Break long line.

[gcc/testsuite]
2017-05-05  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/79038
	PR target/79202
	PR target/79203
	* gcc.target/powerpc/ppc-round3.c: New test.
	* gcc.target/powerpc/ppc-round2.c: Update expected code.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247657 138bc75d-0d04-0410-961f-82ee72b054a4