RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond
commit5ee894130fd0103b3d95fbca19ea1acc4e68d828
authorLehua Ding <lehua.ding@rivai.ai>
Tue, 31 Oct 2023 03:18:28 +0000 (31 11:18 +0800)
committerLehua Ding <lehua.ding@rivai.ai>
Tue, 31 Oct 2023 03:45:46 +0000 (31 11:45 +0800)
tree4c1b6147328d6099dfb6d29a8b2247e2e7603062
parentf5d33d0c790a00cb5240a966dd99df9961bf57a0
RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond

Hi,

This patch let the INT64 to FP16 convert split to two small converts
(INT64 -> FP32 and FP32 -> FP16) when expanding instead of dealy the
split to split1 pass. This change could make it possible to combine
the FP32 to FP16 and vcond patterns and so we don't need to add an
combine pattern for INT64 to FP16 and vcond patterns.

Consider this code:
  void
  foo (_Float16 *__restrict r, int64_t *__restrict a, _FLoat16 *__restrict b,
       int64_t *__restrict pred, int n)
  {
    for (int i = 0; i < n; i += 1)
      {
        r[i] = pred[i] ? (_Float16) a[i] : b[i];
      }
  }

Before this patch:
  ...
  vfncvt.f.f.w    v2,v2
  vmerge.vvm      v1,v1,v2,v0
  vse16.v v1,0(a0)
  ...

After this patch:
  ...
  vfncvt.f.f.w    v1,v2,v0.t
  vse16.v v1,0(a0)
  ...

gcc/ChangeLog:

* config/riscv/autovec.md (<float_cvt><mode><vnnconvert>2):
Change to define_expand.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c:
Add vfncvt.f.f.w assert.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c:
Ditto.
gcc/config/riscv/autovec.md
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c