RISC-V: Adjust FP rint round tests for RV32

RISC-V: Adjust FP rint round tests for RV32

The FP rint test cases for RV32 need some additional adjust
for types and data. This patch would like to fix this which
is missed in FP rint support PATCH for RV32 only by mistake.

Please note the math-llrintf-run-0.c will trigger one ICE in the
vsetvl pass in RV32 only.

./riscv32-unknown-elf-gcc -march=rv32gcv -mabi=ilp32d \
  -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math \
  gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrintf-run-0.c \
  -o test.elf -lm

Then there will have ICE similar as below, and will file bugzilla for it.

config/riscv/riscv-v.cc:4314
   65 | }
      | ^
0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**,
rtx_def*, bool)
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-v.cc:4314
0x1fb1aa2 pre_vsetvl::remove_avl_operand()
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3342
0x1fb18c1 pre_vsetvl::cleaup()
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3308
0x1fb216d pass_vsetvl::lazy_vsetvl()
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3480
0x1fb2214 pass_vsetvl::execute(function*)
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3504

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/math-irint-run-0.c: Adjust
	test cases.
	* gcc.target/riscv/rvv/autovec/unop/math-llrintf-run-0.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-run-0.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>