RISC-V: Make liveness estimation be aware of .vi variant
Consider this following case:
void
f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
{
for (int i = 0; i < n; i++)
{
int tmp = b[i] + 15;
int tmp2 = tmp + b[i];
c[i] = tmp2 + b[i];
d[i] = tmp + tmp2 + b[i];
}
}
Current dynamic LMUL cost model choose LMUL = 4 because we count the "15" as
consuming 1 vector register group which is not accurate.
We teach the dynamic LMUL cost model be aware of the potential vi variant instructions
transformation, so that we can choose LMUL = 8 according to more accurate cost model.
After this patch:
f:
ble a4,zero,.L5
.L3:
vsetvli a5,a4,e32,m8,ta,ma
slli a0,a5,2
vle32.v v16,0(a1)
vadd.vi v24,v16,15
vadd.vv v8,v24,v16
vadd.vv v0,v8,v16
vse32.v v0,0(a2)
vadd.vv v8,v8,v24
vadd.vv v8,v8,v16
vse32.v v8,0(a3)
add a1,a1,a0
add a2,a2,a0
add a3,a3,a0
sub a4,a4,a5
bne a4,zero,.L3
.L5:
ret
Tested on both RV32 and RV64 no regression.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c: New test.