| commit | 2e59eefdcfe2a28157885965ad081a2302843814 | |
| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Fri, 21 Nov 2014 18:03:09 +0000 (21 18:03 +0000) | ||
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Fri, 21 Nov 2014 18:03:09 +0000 (21 18:03 +0000) | ||
| tree | 70b8a30963ad8464a26784df401831fc1adef5bd | treesnapshot (tar.gz zip) |
| parent | d745b4664702b1bdbdeedcd57d397845853e6819 | commitdiff |
2014-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217940 138bc75d-0d04-0410-961f-82ee72b054a4
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217940 138bc75d-0d04-0410-961f-82ee72b054a4
| gcc/ChangeLog | diffblobblamehistory | |
| gcc/config/rs6000/rs6000-cpus.def | diffblobblamehistory | |
| gcc/config/rs6000/rs6000.c | diffblobblamehistory |