| commit | 1f641d6aba284e0c277e6684cd6b2c73591cd14d | |
| author | Wilco Dijkstra <wilco.dijkstra@arm.com> | |
| Fri, 10 Feb 2023 17:41:05 +0000 (10 17:41 +0000) | ||
| committer | Wilco Dijkstra <wilco.dijkstra@arm.com> | |
| Fri, 24 Mar 2023 16:51:26 +0000 (24 16:51 +0000) | ||
| tree | d977709ea8d2607e7465f92ed8b19b9c57776803 | treesnapshot (tar.gz zip) |
| parent | 243fa4883cf6fccaaafddcc82e6b58843c82fb30 | commitdiff |
libatomic: Fix SEQ_CST 128-bit atomic load [PR108891]
The LSE2 ifunc for 16-byte atomic load requires a barrier before the LDP -
without it, it effectively has Load-AcquirePC semantics similar to LDAPR,
which is less restrictive than what __ATOMIC_SEQ_CST requires. This patch
fixes this and adds comments to make it easier to see which sequence is
used for each case. Use a load/store exclusive loop for store to simplify
testing memory ordering is correct (it is slightly faster too).
libatomic/
PR libgcc/108891
* config/linux/aarch64/atomic_16.S: Fix libat_load_16_i1.
Add comments describing the memory order.
The LSE2 ifunc for 16-byte atomic load requires a barrier before the LDP -
without it, it effectively has Load-AcquirePC semantics similar to LDAPR,
which is less restrictive than what __ATOMIC_SEQ_CST requires. This patch
fixes this and adds comments to make it easier to see which sequence is
used for each case. Use a load/store exclusive loop for store to simplify
testing memory ordering is correct (it is slightly faster too).
libatomic/
PR libgcc/108891
* config/linux/aarch64/atomic_16.S: Fix libat_load_16_i1.
Add comments describing the memory order.
| libatomic/config/linux/aarch64/atomic_16.S | diffblobblamehistory |