| commit | 16d5eaa1b5666b1c263ab5869e1d9b28cd7b0a99 | |
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | |
| Mon, 24 Nov 2014 19:27:29 +0000 (24 19:27 +0000) | ||
| committer | Michael Meissner <meissner@gcc.gnu.org> | |
| Mon, 24 Nov 2014 19:27:29 +0000 (24 19:27 +0000) | ||
| tree | 384cef1786a5d77f6b717004f291f36372ad041c | treesnapshot (tar.gz zip) |
| parent | 22186565977181492c37750e44571a54363d2624 | commitdiff |
re PR target/63965 (ICE: in extract_constrain_insn, at recog.c:2230 on ppc64)
2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
From-SVN: r218028
2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
From-SVN: r218028
| gcc/ChangeLog | diffblobblamehistory | |
| gcc/config/rs6000/altivec.md | diffblobblamehistory | |
| gcc/config/rs6000/rs6000.c | diffblobblamehistory |