This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook.
commit12ad66dd3fec6188e6af48ecc2f002692bc6203f
authorwilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 2 Feb 2016 17:03:05 +0000 (2 17:03 +0000)
committerwilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 2 Feb 2016 17:03:05 +0000 (2 17:03 +0000)
tree3d5dbb501c4b6d12b44117ef9562b9e9467698eb
parentf4c1a841848c9c16a95826666f1d5e17d145ab53
This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook.
When the cost of GENERAL_REGS and FP_REGS is identical, the register allocator
always uses ALL_REGS even when it has a much higher cost. The hook changes the
class to either FP_REGS or GENERAL_REGS depending on the mode of the register.
This results in better register allocation overall, fewer spills and reduced
codesize - particularly in SPEC2006 gamess.

2016-02-02  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
* config/aarch64/aarch64.c
(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
(aarch64_ira_change_pseudo_allocno_class): New function.

    gcc/testsuite/
* gcc.target/aarch64/scalar_shift_1.c
(test_corners_sisd_di): Improve force to SIMD register.
(test_corners_sisd_si): Likewise.
* gcc.target/aarch64/vect-ld1r-compile-fp.c:
Remove scan-assembler check for ldr.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233083 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/aarch64/aarch64.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c