| commit | 12829505f233db52f7f552f1a104ecd3cac8de88 | |
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | |
| Fri, 21 Nov 2014 18:03:09 +0000 (21 18:03 +0000) | ||
| committer | Michael Meissner <meissner@gcc.gnu.org> | |
| Fri, 21 Nov 2014 18:03:09 +0000 (21 18:03 +0000) | ||
| tree | 70b8a30963ad8464a26784df401831fc1adef5bd | treesnapshot (tar.gz zip) |
| parent | a871c139f07730f14985620e3c05c4ddc6e2be0c | commitdiff |
re PR target/63965 (ICE: in extract_constrain_insn, at recog.c:2230 on ppc64)
2014-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
From-SVN: r217940
2014-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/63965
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
Altivec & -16 mask if the type is not valid for Altivec registers.
(rs6000_secondary_reload_memory): Add support for ((reg + const) +
reg) that occurs during push_reload processing.
* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
alternative for moving constant vectors which are easy altivec
constants to GPRs. Set the length attribute each of the
alternatives.
From-SVN: r217940
| gcc/ChangeLog | diffblobblamehistory | |
| gcc/config/rs6000/rs6000-cpus.def | diffblobblamehistory | |
| gcc/config/rs6000/rs6000.c | diffblobblamehistory |