[gcc]

[gcc]
2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (const_0_to_12_operand): Rename
	predicate and change test from 0..11 to 0..12 to match the
	semantics of the word extract/insert instructions.  Change all
	callers.
	(const_0_to_11_operand): Likewise.
	* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
	* config/rs6000/vsx.md (vextract4b): Likewise.
	(vextract4b_internal): Likewise.
	(vinsert4b): Likewise.
	(vinsert4b_internal): Likewise.
	(vinsert4b_di): Likewise.
	(vinsert4b_di_internal): Likewise.
	* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
	in xxextractuw to zero extend the word in the vector registers.
	(lfiwzx): Likewise.

[gcc/testsuite]
2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
	being out of bounds instead of 12.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243948 138bc75d-0d04-0410-961f-82ee72b054a4