1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
39 #include "basic-block.h"
43 #include "tree-pass.h"
45 #ifndef STACK_PUSH_CODE
46 #ifdef STACK_GROWS_DOWNWARD
47 #define STACK_PUSH_CODE PRE_DEC
49 #define STACK_PUSH_CODE PRE_INC
53 #ifndef STACK_POP_CODE
54 #ifdef STACK_GROWS_DOWNWARD
55 #define STACK_POP_CODE POST_INC
57 #define STACK_POP_CODE POST_DEC
61 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
);
62 static rtx
*find_single_use_1 (rtx
, rtx
*);
63 static void validate_replace_src_1 (rtx
*, void *);
64 static rtx
split_insn (rtx
);
66 /* Nonzero means allow operands to be volatile.
67 This should be 0 if you are generating rtl, such as if you are calling
68 the functions in optabs.c and expmed.c (most of the time).
69 This should be 1 if all valid insns need to be recognized,
70 such as in regclass.c and final.c and reload.c.
72 init_recog and init_recog_no_volatile are responsible for setting this. */
76 struct recog_data recog_data
;
78 /* Contains a vector of operand_alternative structures for every operand.
79 Set up by preprocess_constraints. */
80 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
82 /* On return from `constrain_operands', indicate which alternative
85 int which_alternative
;
87 /* Nonzero after end of reload pass.
88 Set to 1 or 0 by toplev.c.
89 Controls the significance of (SUBREG (MEM)). */
93 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
94 int epilogue_completed
;
96 /* Initialize data used by the function `recog'.
97 This must be called once in the compilation of a function
98 before any insn recognition may be done in the function. */
101 init_recog_no_volatile (void)
113 /* Check that X is an insn-body for an `asm' with operands
114 and that the operands mentioned in it are legitimate. */
117 check_asm_operands (rtx x
)
121 const char **constraints
;
124 /* Post-reload, be more strict with things. */
125 if (reload_completed
)
127 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
128 extract_insn (make_insn_raw (x
));
129 constrain_operands (1);
130 return which_alternative
>= 0;
133 noperands
= asm_noperands (x
);
139 operands
= alloca (noperands
* sizeof (rtx
));
140 constraints
= alloca (noperands
* sizeof (char *));
142 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
);
144 for (i
= 0; i
< noperands
; i
++)
146 const char *c
= constraints
[i
];
149 if (ISDIGIT ((unsigned char) c
[0]) && c
[1] == '\0')
150 c
= constraints
[c
[0] - '0'];
152 if (! asm_operand_ok (operands
[i
], c
))
159 /* Static data for the next two routines. */
161 typedef struct change_t
169 static change_t
*changes
;
170 static int changes_allocated
;
172 static int num_changes
= 0;
174 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
175 at which NEW will be placed. If OBJECT is zero, no validation is done,
176 the change is simply made.
178 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
179 will be called with the address and mode as parameters. If OBJECT is
180 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
183 IN_GROUP is nonzero if this is part of a group of changes that must be
184 performed as a group. In that case, the changes will be stored. The
185 function `apply_change_group' will validate and apply the changes.
187 If IN_GROUP is zero, this is a single change. Try to recognize the insn
188 or validate the memory reference with the change applied. If the result
189 is not valid for the machine, suppress the change and return zero.
190 Otherwise, perform the change and return 1. */
193 validate_change (rtx object
, rtx
*loc
, rtx
new, int in_group
)
197 if (old
== new || rtx_equal_p (old
, new))
200 gcc_assert (in_group
!= 0 || num_changes
== 0);
204 /* Save the information describing this change. */
205 if (num_changes
>= changes_allocated
)
207 if (changes_allocated
== 0)
208 /* This value allows for repeated substitutions inside complex
209 indexed addresses, or changes in up to 5 insns. */
210 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
212 changes_allocated
*= 2;
214 changes
= xrealloc (changes
, sizeof (change_t
) * changes_allocated
);
217 changes
[num_changes
].object
= object
;
218 changes
[num_changes
].loc
= loc
;
219 changes
[num_changes
].old
= old
;
221 if (object
&& !MEM_P (object
))
223 /* Set INSN_CODE to force rerecognition of insn. Save old code in
225 changes
[num_changes
].old_code
= INSN_CODE (object
);
226 INSN_CODE (object
) = -1;
231 /* If we are making a group of changes, return 1. Otherwise, validate the
232 change group we made. */
237 return apply_change_group ();
241 /* Function to be passed to for_each_rtx to test whether a piece of
242 RTL contains any mem/v. */
244 volatile_mem_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
246 return (MEM_P (*x
) && MEM_VOLATILE_P (*x
));
249 /* Same as validate_change, but doesn't support groups, and it accepts
250 volatile mems if they're already present in the original insn. */
253 validate_change_maybe_volatile (rtx object
, rtx
*loc
, rtx
new)
257 if (validate_change (object
, loc
, new, 0))
261 /* If there isn't a volatile MEM, there's nothing we can do. */
262 || !for_each_rtx (&PATTERN (object
), volatile_mem_p
, 0)
263 /* Make sure we're not adding or removing volatile MEMs. */
264 || for_each_rtx (loc
, volatile_mem_p
, 0)
265 || for_each_rtx (&new, volatile_mem_p
, 0)
266 || !insn_invalid_p (object
))
271 gcc_assert (!insn_invalid_p (object
));
273 result
= validate_change (object
, loc
, new, 0);
280 /* This subroutine of apply_change_group verifies whether the changes to INSN
281 were valid; i.e. whether INSN can still be recognized. */
284 insn_invalid_p (rtx insn
)
286 rtx pat
= PATTERN (insn
);
287 int num_clobbers
= 0;
288 /* If we are before reload and the pattern is a SET, see if we can add
290 int icode
= recog (pat
, insn
,
291 (GET_CODE (pat
) == SET
292 && ! reload_completed
&& ! reload_in_progress
)
293 ? &num_clobbers
: 0);
294 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
297 /* If this is an asm and the operand aren't legal, then fail. Likewise if
298 this is not an asm and the insn wasn't recognized. */
299 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
300 || (!is_asm
&& icode
< 0))
303 /* If we have to add CLOBBERs, fail if we have to add ones that reference
304 hard registers since our callers can't know if they are live or not.
305 Otherwise, add them. */
306 if (num_clobbers
> 0)
310 if (added_clobbers_hard_reg_p (icode
))
313 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
314 XVECEXP (newpat
, 0, 0) = pat
;
315 add_clobbers (newpat
, icode
);
316 PATTERN (insn
) = pat
= newpat
;
319 /* After reload, verify that all constraints are satisfied. */
320 if (reload_completed
)
324 if (! constrain_operands (1))
328 INSN_CODE (insn
) = icode
;
332 /* Return number of changes made and not validated yet. */
334 num_changes_pending (void)
339 /* Tentatively apply the changes numbered NUM and up.
340 Return 1 if all changes are valid, zero otherwise. */
343 verify_changes (int num
)
346 rtx last_validated
= NULL_RTX
;
348 /* The changes have been applied and all INSN_CODEs have been reset to force
351 The changes are valid if we aren't given an object, or if we are
352 given a MEM and it still is a valid address, or if this is in insn
353 and it is recognized. In the latter case, if reload has completed,
354 we also require that the operands meet the constraints for
357 for (i
= num
; i
< num_changes
; i
++)
359 rtx object
= changes
[i
].object
;
361 /* If there is no object to test or if it is the same as the one we
362 already tested, ignore it. */
363 if (object
== 0 || object
== last_validated
)
368 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
371 else if (insn_invalid_p (object
))
373 rtx pat
= PATTERN (object
);
375 /* Perhaps we couldn't recognize the insn because there were
376 extra CLOBBERs at the end. If so, try to re-recognize
377 without the last CLOBBER (later iterations will cause each of
378 them to be eliminated, in turn). But don't do this if we
379 have an ASM_OPERAND. */
380 if (GET_CODE (pat
) == PARALLEL
381 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
382 && asm_noperands (PATTERN (object
)) < 0)
386 if (XVECLEN (pat
, 0) == 2)
387 newpat
= XVECEXP (pat
, 0, 0);
393 = gen_rtx_PARALLEL (VOIDmode
,
394 rtvec_alloc (XVECLEN (pat
, 0) - 1));
395 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
396 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
399 /* Add a new change to this group to replace the pattern
400 with this new pattern. Then consider this change
401 as having succeeded. The change we added will
402 cause the entire call to fail if things remain invalid.
404 Note that this can lose if a later change than the one
405 we are processing specified &XVECEXP (PATTERN (object), 0, X)
406 but this shouldn't occur. */
408 validate_change (object
, &PATTERN (object
), newpat
, 1);
411 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
412 /* If this insn is a CLOBBER or USE, it is always valid, but is
418 last_validated
= object
;
421 return (i
== num_changes
);
424 /* A group of changes has previously been issued with validate_change and
425 verified with verify_changes. Update the BB_DIRTY flags of the affected
426 blocks, and clear num_changes. */
429 confirm_change_group (void)
434 for (i
= 0; i
< num_changes
; i
++)
435 if (changes
[i
].object
436 && INSN_P (changes
[i
].object
)
437 && (bb
= BLOCK_FOR_INSN (changes
[i
].object
)))
438 bb
->flags
|= BB_DIRTY
;
443 /* Apply a group of changes previously issued with `validate_change'.
444 If all changes are valid, call confirm_change_group and return 1,
445 otherwise, call cancel_changes and return 0. */
448 apply_change_group (void)
450 if (verify_changes (0))
452 confirm_change_group ();
463 /* Return the number of changes so far in the current group. */
466 num_validated_changes (void)
471 /* Retract the changes numbered NUM and up. */
474 cancel_changes (int num
)
478 /* Back out all the changes. Do this in the opposite order in which
480 for (i
= num_changes
- 1; i
>= num
; i
--)
482 *changes
[i
].loc
= changes
[i
].old
;
483 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
484 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
489 /* Replace every occurrence of FROM in X with TO. Mark each change with
490 validate_change passing OBJECT. */
493 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
)
499 enum machine_mode op0_mode
= VOIDmode
;
500 int prev_changes
= num_changes
;
507 fmt
= GET_RTX_FORMAT (code
);
509 op0_mode
= GET_MODE (XEXP (x
, 0));
511 /* X matches FROM if it is the same rtx or they are both referring to the
512 same register in the same mode. Avoid calling rtx_equal_p unless the
513 operands look similar. */
516 || (REG_P (x
) && REG_P (from
)
517 && GET_MODE (x
) == GET_MODE (from
)
518 && REGNO (x
) == REGNO (from
))
519 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
520 && rtx_equal_p (x
, from
)))
522 validate_change (object
, loc
, to
, 1);
526 /* Call ourself recursively to perform the replacements.
527 We must not replace inside already replaced expression, otherwise we
528 get infinite recursion for replacements like (reg X)->(subreg (reg X))
529 done by regmove, so we must special case shared ASM_OPERANDS. */
531 if (GET_CODE (x
) == PARALLEL
)
533 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
535 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
536 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
538 /* Verify that operands are really shared. */
539 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
540 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
542 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
546 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
);
550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
553 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
554 else if (fmt
[i
] == 'E')
555 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
556 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
559 /* If we didn't substitute, there is nothing more to do. */
560 if (num_changes
== prev_changes
)
563 /* Allow substituted expression to have different mode. This is used by
564 regmove to change mode of pseudo register. */
565 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
566 op0_mode
= GET_MODE (XEXP (x
, 0));
568 /* Do changes needed to keep rtx consistent. Don't do any other
569 simplifications, as it is not our job. */
571 if (SWAPPABLE_OPERANDS_P (x
)
572 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
574 validate_change (object
, loc
,
575 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
576 : swap_condition (code
),
577 GET_MODE (x
), XEXP (x
, 1),
586 /* If we have a PLUS whose second operand is now a CONST_INT, use
587 simplify_gen_binary to try to simplify it.
588 ??? We may want later to remove this, once simplification is
589 separated from this function. */
590 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
591 validate_change (object
, loc
,
593 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
596 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
597 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
598 validate_change (object
, loc
,
600 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
601 simplify_gen_unary (NEG
,
602 GET_MODE (x
), XEXP (x
, 1),
607 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
609 new = simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
611 /* If any of the above failed, substitute in something that
612 we know won't be recognized. */
614 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
615 validate_change (object
, loc
, new, 1);
619 /* All subregs possible to simplify should be simplified. */
620 new = simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
623 /* Subregs of VOIDmode operands are incorrect. */
624 if (!new && GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
625 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
627 validate_change (object
, loc
, new, 1);
631 /* If we are replacing a register with memory, try to change the memory
632 to be the mode required for memory in extract operations (this isn't
633 likely to be an insertion operation; if it was, nothing bad will
634 happen, we might just fail in some cases). */
636 if (MEM_P (XEXP (x
, 0))
637 && GET_CODE (XEXP (x
, 1)) == CONST_INT
638 && GET_CODE (XEXP (x
, 2)) == CONST_INT
639 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
640 && !MEM_VOLATILE_P (XEXP (x
, 0)))
642 enum machine_mode wanted_mode
= VOIDmode
;
643 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
644 int pos
= INTVAL (XEXP (x
, 2));
646 if (GET_CODE (x
) == ZERO_EXTRACT
)
648 enum machine_mode new_mode
649 = mode_for_extraction (EP_extzv
, 1);
650 if (new_mode
!= MAX_MACHINE_MODE
)
651 wanted_mode
= new_mode
;
653 else if (GET_CODE (x
) == SIGN_EXTRACT
)
655 enum machine_mode new_mode
656 = mode_for_extraction (EP_extv
, 1);
657 if (new_mode
!= MAX_MACHINE_MODE
)
658 wanted_mode
= new_mode
;
661 /* If we have a narrower mode, we can do something. */
662 if (wanted_mode
!= VOIDmode
663 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
665 int offset
= pos
/ BITS_PER_UNIT
;
668 /* If the bytes and bits are counted differently, we
669 must adjust the offset. */
670 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
672 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
675 pos
%= GET_MODE_BITSIZE (wanted_mode
);
677 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
679 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
680 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
691 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
692 with TO. After all changes have been made, validate by seeing
693 if INSN is still valid. */
696 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
698 validate_replace_rtx_1 (loc
, from
, to
, insn
);
699 return apply_change_group ();
702 /* Try replacing every occurrence of FROM in INSN with TO. After all
703 changes have been made, validate by seeing if INSN is still valid. */
706 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
708 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
709 return apply_change_group ();
712 /* Try replacing every occurrence of FROM in INSN with TO. */
715 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
717 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
720 /* Function called by note_uses to replace used subexpressions. */
721 struct validate_replace_src_data
723 rtx from
; /* Old RTX */
724 rtx to
; /* New RTX */
725 rtx insn
; /* Insn in which substitution is occurring. */
729 validate_replace_src_1 (rtx
*x
, void *data
)
731 struct validate_replace_src_data
*d
732 = (struct validate_replace_src_data
*) data
;
734 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
);
737 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
741 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
743 struct validate_replace_src_data d
;
748 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
752 /* Return 1 if the insn using CC0 set by INSN does not contain
753 any ordered tests applied to the condition codes.
754 EQ and NE tests do not count. */
757 next_insn_tests_no_inequality (rtx insn
)
759 rtx next
= next_cc0_user (insn
);
761 /* If there is no next insn, we have to take the conservative choice. */
765 return (INSN_P (next
)
766 && ! inequality_comparisons_p (PATTERN (next
)));
770 /* This is used by find_single_use to locate an rtx that contains exactly one
771 use of DEST, which is typically either a REG or CC0. It returns a
772 pointer to the innermost rtx expression containing DEST. Appearances of
773 DEST that are being used to totally replace it are not counted. */
776 find_single_use_1 (rtx dest
, rtx
*loc
)
779 enum rtx_code code
= GET_CODE (x
);
797 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
798 of a REG that occupies all of the REG, the insn uses DEST if
799 it is mentioned in the destination or the source. Otherwise, we
800 need just check the source. */
801 if (GET_CODE (SET_DEST (x
)) != CC0
802 && GET_CODE (SET_DEST (x
)) != PC
803 && !REG_P (SET_DEST (x
))
804 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
805 && REG_P (SUBREG_REG (SET_DEST (x
)))
806 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
807 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
808 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
809 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
812 return find_single_use_1 (dest
, &SET_SRC (x
));
816 return find_single_use_1 (dest
, &XEXP (x
, 0));
822 /* If it wasn't one of the common cases above, check each expression and
823 vector of this code. Look for a unique usage of DEST. */
825 fmt
= GET_RTX_FORMAT (code
);
826 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
830 if (dest
== XEXP (x
, i
)
831 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
832 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
835 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
838 result
= this_result
;
839 else if (this_result
)
840 /* Duplicate usage. */
843 else if (fmt
[i
] == 'E')
847 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
849 if (XVECEXP (x
, i
, j
) == dest
851 && REG_P (XVECEXP (x
, i
, j
))
852 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
855 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
858 result
= this_result
;
859 else if (this_result
)
868 /* See if DEST, produced in INSN, is used only a single time in the
869 sequel. If so, return a pointer to the innermost rtx expression in which
872 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
874 This routine will return usually zero either before flow is called (because
875 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
876 note can't be trusted).
878 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
879 care about REG_DEAD notes or LOG_LINKS.
881 Otherwise, we find the single use by finding an insn that has a
882 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
883 only referenced once in that insn, we know that it must be the first
884 and last insn referencing DEST. */
887 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
896 next
= NEXT_INSN (insn
);
898 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
901 result
= find_single_use_1 (dest
, &PATTERN (next
));
908 if (reload_completed
|| reload_in_progress
|| !REG_P (dest
))
911 for (next
= next_nonnote_insn (insn
);
912 next
!= 0 && !LABEL_P (next
);
913 next
= next_nonnote_insn (next
))
914 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
916 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
917 if (XEXP (link
, 0) == insn
)
922 result
= find_single_use_1 (dest
, &PATTERN (next
));
932 /* Return 1 if OP is a valid general operand for machine mode MODE.
933 This is either a register reference, a memory reference,
934 or a constant. In the case of a memory reference, the address
935 is checked for general validity for the target machine.
937 Register and memory references must have mode MODE in order to be valid,
938 but some constants have no machine mode and are valid for any mode.
940 If MODE is VOIDmode, OP is checked for validity for whatever mode
943 The main use of this function is as a predicate in match_operand
944 expressions in the machine description.
946 For an explanation of this function's behavior for registers of
947 class NO_REGS, see the comment for `register_operand'. */
950 general_operand (rtx op
, enum machine_mode mode
)
952 enum rtx_code code
= GET_CODE (op
);
954 if (mode
== VOIDmode
)
955 mode
= GET_MODE (op
);
957 /* Don't accept CONST_INT or anything similar
958 if the caller wants something floating. */
959 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
960 && GET_MODE_CLASS (mode
) != MODE_INT
961 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
964 if (GET_CODE (op
) == CONST_INT
966 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
970 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
972 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
973 && LEGITIMATE_CONSTANT_P (op
));
975 /* Except for certain constants with VOIDmode, already checked for,
976 OP's mode must match MODE if MODE specifies a mode. */
978 if (GET_MODE (op
) != mode
)
983 rtx sub
= SUBREG_REG (op
);
985 #ifdef INSN_SCHEDULING
986 /* On machines that have insn scheduling, we want all memory
987 reference to be explicit, so outlaw paradoxical SUBREGs.
988 However, we must allow them after reload so that they can
989 get cleaned up by cleanup_subreg_operands. */
990 if (!reload_completed
&& MEM_P (sub
)
991 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
994 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
995 may result in incorrect reference. We should simplify all valid
996 subregs of MEM anyway. But allow this after reload because we
997 might be called from cleanup_subreg_operands.
999 ??? This is a kludge. */
1000 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1004 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1005 create such rtl, and we must reject it. */
1006 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1007 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1011 code
= GET_CODE (op
);
1015 /* A register whose class is NO_REGS is not a general operand. */
1016 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1017 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
1021 rtx y
= XEXP (op
, 0);
1023 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1026 /* Use the mem's mode, since it will be reloaded thus. */
1027 if (memory_address_p (GET_MODE (op
), y
))
1034 /* Return 1 if OP is a valid memory address for a memory reference
1037 The main use of this function is as a predicate in match_operand
1038 expressions in the machine description. */
1041 address_operand (rtx op
, enum machine_mode mode
)
1043 return memory_address_p (mode
, op
);
1046 /* Return 1 if OP is a register reference of mode MODE.
1047 If MODE is VOIDmode, accept a register in any mode.
1049 The main use of this function is as a predicate in match_operand
1050 expressions in the machine description.
1052 As a special exception, registers whose class is NO_REGS are
1053 not accepted by `register_operand'. The reason for this change
1054 is to allow the representation of special architecture artifacts
1055 (such as a condition code register) without extending the rtl
1056 definitions. Since registers of class NO_REGS cannot be used
1057 as registers in any case where register classes are examined,
1058 it is most consistent to keep this function from accepting them. */
1061 register_operand (rtx op
, enum machine_mode mode
)
1063 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1066 if (GET_CODE (op
) == SUBREG
)
1068 rtx sub
= SUBREG_REG (op
);
1070 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1071 because it is guaranteed to be reloaded into one.
1072 Just make sure the MEM is valid in itself.
1073 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1074 but currently it does result from (SUBREG (REG)...) where the
1075 reg went on the stack.) */
1076 if (! reload_completed
&& MEM_P (sub
))
1077 return general_operand (op
, mode
);
1079 #ifdef CANNOT_CHANGE_MODE_CLASS
1081 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1082 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1083 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1084 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
)
1088 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1089 create such rtl, and we must reject it. */
1090 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1091 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1097 /* We don't consider registers whose class is NO_REGS
1098 to be a register operand. */
1100 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1101 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1104 /* Return 1 for a register in Pmode; ignore the tested mode. */
1107 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1109 return register_operand (op
, Pmode
);
1112 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1113 or a hard register. */
1116 scratch_operand (rtx op
, enum machine_mode mode
)
1118 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1121 return (GET_CODE (op
) == SCRATCH
1123 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1126 /* Return 1 if OP is a valid immediate operand for mode MODE.
1128 The main use of this function is as a predicate in match_operand
1129 expressions in the machine description. */
1132 immediate_operand (rtx op
, enum machine_mode mode
)
1134 /* Don't accept CONST_INT or anything similar
1135 if the caller wants something floating. */
1136 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1137 && GET_MODE_CLASS (mode
) != MODE_INT
1138 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1141 if (GET_CODE (op
) == CONST_INT
1143 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1146 return (CONSTANT_P (op
)
1147 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1148 || GET_MODE (op
) == VOIDmode
)
1149 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1150 && LEGITIMATE_CONSTANT_P (op
));
1153 /* Returns 1 if OP is an operand that is a CONST_INT. */
1156 const_int_operand (rtx op
, enum machine_mode mode
)
1158 if (GET_CODE (op
) != CONST_INT
)
1161 if (mode
!= VOIDmode
1162 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1168 /* Returns 1 if OP is an operand that is a constant integer or constant
1169 floating-point number. */
1172 const_double_operand (rtx op
, enum machine_mode mode
)
1174 /* Don't accept CONST_INT or anything similar
1175 if the caller wants something floating. */
1176 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1177 && GET_MODE_CLASS (mode
) != MODE_INT
1178 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1181 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
1182 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1183 || GET_MODE (op
) == VOIDmode
));
1186 /* Return 1 if OP is a general operand that is not an immediate operand. */
1189 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1191 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1194 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1197 nonmemory_operand (rtx op
, enum machine_mode mode
)
1199 if (CONSTANT_P (op
))
1201 /* Don't accept CONST_INT or anything similar
1202 if the caller wants something floating. */
1203 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1204 && GET_MODE_CLASS (mode
) != MODE_INT
1205 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1208 if (GET_CODE (op
) == CONST_INT
1210 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1213 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1214 || mode
== VOIDmode
)
1215 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1216 && LEGITIMATE_CONSTANT_P (op
));
1219 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1222 if (GET_CODE (op
) == SUBREG
)
1224 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1225 because it is guaranteed to be reloaded into one.
1226 Just make sure the MEM is valid in itself.
1227 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1228 but currently it does result from (SUBREG (REG)...) where the
1229 reg went on the stack.) */
1230 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1231 return general_operand (op
, mode
);
1232 op
= SUBREG_REG (op
);
1235 /* We don't consider registers whose class is NO_REGS
1236 to be a register operand. */
1238 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1239 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1242 /* Return 1 if OP is a valid operand that stands for pushing a
1243 value of mode MODE onto the stack.
1245 The main use of this function is as a predicate in match_operand
1246 expressions in the machine description. */
1249 push_operand (rtx op
, enum machine_mode mode
)
1251 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1253 #ifdef PUSH_ROUNDING
1254 rounded_size
= PUSH_ROUNDING (rounded_size
);
1260 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1265 if (rounded_size
== GET_MODE_SIZE (mode
))
1267 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1272 if (GET_CODE (op
) != PRE_MODIFY
1273 || GET_CODE (XEXP (op
, 1)) != PLUS
1274 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1275 || GET_CODE (XEXP (XEXP (op
, 1), 1)) != CONST_INT
1276 #ifdef STACK_GROWS_DOWNWARD
1277 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1279 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1285 return XEXP (op
, 0) == stack_pointer_rtx
;
1288 /* Return 1 if OP is a valid operand that stands for popping a
1289 value of mode MODE off the stack.
1291 The main use of this function is as a predicate in match_operand
1292 expressions in the machine description. */
1295 pop_operand (rtx op
, enum machine_mode mode
)
1300 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1305 if (GET_CODE (op
) != STACK_POP_CODE
)
1308 return XEXP (op
, 0) == stack_pointer_rtx
;
1311 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1314 memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx addr
)
1316 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1323 /* Return 1 if OP is a valid memory reference with mode MODE,
1324 including a valid address.
1326 The main use of this function is as a predicate in match_operand
1327 expressions in the machine description. */
1330 memory_operand (rtx op
, enum machine_mode mode
)
1334 if (! reload_completed
)
1335 /* Note that no SUBREG is a memory operand before end of reload pass,
1336 because (SUBREG (MEM...)) forces reloading into a register. */
1337 return MEM_P (op
) && general_operand (op
, mode
);
1339 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1343 if (GET_CODE (inner
) == SUBREG
)
1344 inner
= SUBREG_REG (inner
);
1346 return (MEM_P (inner
) && general_operand (op
, mode
));
1349 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1350 that is, a memory reference whose address is a general_operand. */
1353 indirect_operand (rtx op
, enum machine_mode mode
)
1355 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1356 if (! reload_completed
1357 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1359 int offset
= SUBREG_BYTE (op
);
1360 rtx inner
= SUBREG_REG (op
);
1362 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1365 /* The only way that we can have a general_operand as the resulting
1366 address is if OFFSET is zero and the address already is an operand
1367 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1370 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1371 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1372 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1373 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1374 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1378 && memory_operand (op
, mode
)
1379 && general_operand (XEXP (op
, 0), Pmode
));
1382 /* Return 1 if this is a comparison operator. This allows the use of
1383 MATCH_OPERATOR to recognize all the branch insns. */
1386 comparison_operator (rtx op
, enum machine_mode mode
)
1388 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1389 && COMPARISON_P (op
));
1392 /* If BODY is an insn body that uses ASM_OPERANDS,
1393 return the number of operands (both input and output) in the insn.
1394 Otherwise return -1. */
1397 asm_noperands (rtx body
)
1399 switch (GET_CODE (body
))
1402 /* No output operands: return number of input operands. */
1403 return ASM_OPERANDS_INPUT_LENGTH (body
);
1405 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1406 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1407 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1411 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
1412 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1414 /* Multiple output operands, or 1 output plus some clobbers:
1415 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1419 /* Count backwards through CLOBBERs to determine number of SETs. */
1420 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1422 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1424 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1428 /* N_SETS is now number of output operands. */
1431 /* Verify that all the SETs we have
1432 came from a single original asm_operands insn
1433 (so that invalid combinations are blocked). */
1434 for (i
= 0; i
< n_sets
; i
++)
1436 rtx elt
= XVECEXP (body
, 0, i
);
1437 if (GET_CODE (elt
) != SET
)
1439 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1441 /* If these ASM_OPERANDS rtx's came from different original insns
1442 then they aren't allowed together. */
1443 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1444 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1447 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1450 else if (GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1452 /* 0 outputs, but some clobbers:
1453 body is [(asm_operands ...) (clobber (reg ...))...]. */
1456 /* Make sure all the other parallel things really are clobbers. */
1457 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1458 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1461 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1470 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1471 copy its operands (both input and output) into the vector OPERANDS,
1472 the locations of the operands within the insn into the vector OPERAND_LOCS,
1473 and the constraints for the operands into CONSTRAINTS.
1474 Write the modes of the operands into MODES.
1475 Return the assembler-template.
1477 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1478 we don't store that info. */
1481 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1482 const char **constraints
, enum machine_mode
*modes
)
1486 const char *template = 0;
1488 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1490 rtx asmop
= SET_SRC (body
);
1491 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1493 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1495 for (i
= 1; i
< noperands
; i
++)
1498 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1500 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1502 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1504 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1507 /* The output is in the SET.
1508 Its constraint is in the ASM_OPERANDS itself. */
1510 operands
[0] = SET_DEST (body
);
1512 operand_locs
[0] = &SET_DEST (body
);
1514 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1516 modes
[0] = GET_MODE (SET_DEST (body
));
1517 template = ASM_OPERANDS_TEMPLATE (asmop
);
1519 else if (GET_CODE (body
) == ASM_OPERANDS
)
1522 /* No output operands: BODY is (asm_operands ....). */
1524 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1526 /* The input operands are found in the 1st element vector. */
1527 /* Constraints for inputs are in the 2nd element vector. */
1528 for (i
= 0; i
< noperands
; i
++)
1531 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1533 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1535 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1537 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1539 template = ASM_OPERANDS_TEMPLATE (asmop
);
1541 else if (GET_CODE (body
) == PARALLEL
1542 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
1543 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1545 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1546 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1547 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1548 int nout
= 0; /* Does not include CLOBBERs. */
1550 /* At least one output, plus some CLOBBERs. */
1552 /* The outputs are in the SETs.
1553 Their constraints are in the ASM_OPERANDS itself. */
1554 for (i
= 0; i
< nparallel
; i
++)
1556 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1557 break; /* Past last SET */
1560 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1562 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1564 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1566 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1570 for (i
= 0; i
< nin
; i
++)
1573 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1575 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1577 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1579 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1582 template = ASM_OPERANDS_TEMPLATE (asmop
);
1584 else if (GET_CODE (body
) == PARALLEL
1585 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1587 /* No outputs, but some CLOBBERs. */
1589 rtx asmop
= XVECEXP (body
, 0, 0);
1590 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1592 for (i
= 0; i
< nin
; i
++)
1595 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1597 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1599 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1601 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1604 template = ASM_OPERANDS_TEMPLATE (asmop
);
1610 /* Check if an asm_operand matches its constraints.
1611 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1614 asm_operand_ok (rtx op
, const char *constraint
)
1618 /* Use constrain_operands after reload. */
1619 gcc_assert (!reload_completed
);
1623 char c
= *constraint
;
1640 case '0': case '1': case '2': case '3': case '4':
1641 case '5': case '6': case '7': case '8': case '9':
1642 /* For best results, our caller should have given us the
1643 proper matching constraint, but we can't actually fail
1644 the check if they didn't. Indicate that results are
1648 while (ISDIGIT (*constraint
));
1654 if (address_operand (op
, VOIDmode
))
1659 case 'V': /* non-offsettable */
1660 if (memory_operand (op
, VOIDmode
))
1664 case 'o': /* offsettable */
1665 if (offsettable_nonstrict_memref_p (op
))
1670 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1671 excepting those that expand_call created. Further, on some
1672 machines which do not have generalized auto inc/dec, an inc/dec
1673 is not a memory_operand.
1675 Match any memory and hope things are resolved after reload. */
1679 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1680 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1687 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1688 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1694 if (GET_CODE (op
) == CONST_DOUBLE
1695 || (GET_CODE (op
) == CONST_VECTOR
1696 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1701 if (GET_CODE (op
) == CONST_DOUBLE
1702 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1706 if (GET_CODE (op
) == CONST_DOUBLE
1707 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1712 if (GET_CODE (op
) == CONST_INT
1713 || (GET_CODE (op
) == CONST_DOUBLE
1714 && GET_MODE (op
) == VOIDmode
))
1719 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1724 if (GET_CODE (op
) == CONST_INT
1725 || (GET_CODE (op
) == CONST_DOUBLE
1726 && GET_MODE (op
) == VOIDmode
))
1731 if (GET_CODE (op
) == CONST_INT
1732 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1736 if (GET_CODE (op
) == CONST_INT
1737 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1741 if (GET_CODE (op
) == CONST_INT
1742 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1746 if (GET_CODE (op
) == CONST_INT
1747 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1751 if (GET_CODE (op
) == CONST_INT
1752 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1756 if (GET_CODE (op
) == CONST_INT
1757 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1761 if (GET_CODE (op
) == CONST_INT
1762 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1766 if (GET_CODE (op
) == CONST_INT
1767 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1776 if (general_operand (op
, VOIDmode
))
1781 /* For all other letters, we first check for a register class,
1782 otherwise it is an EXTRA_CONSTRAINT. */
1783 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1786 if (GET_MODE (op
) == BLKmode
)
1788 if (register_operand (op
, VOIDmode
))
1791 #ifdef EXTRA_CONSTRAINT_STR
1792 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1794 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
1795 /* Every memory operand can be reloaded to fit. */
1796 && memory_operand (op
, VOIDmode
))
1798 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
)
1799 /* Every address operand can be reloaded to fit. */
1800 && address_operand (op
, VOIDmode
))
1805 len
= CONSTRAINT_LEN (c
, constraint
);
1808 while (--len
&& *constraint
);
1816 /* Given an rtx *P, if it is a sum containing an integer constant term,
1817 return the location (type rtx *) of the pointer to that constant term.
1818 Otherwise, return a null pointer. */
1821 find_constant_term_loc (rtx
*p
)
1824 enum rtx_code code
= GET_CODE (*p
);
1826 /* If *P IS such a constant term, P is its location. */
1828 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1832 /* Otherwise, if not a sum, it has no constant term. */
1834 if (GET_CODE (*p
) != PLUS
)
1837 /* If one of the summands is constant, return its location. */
1839 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1840 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1843 /* Otherwise, check each summand for containing a constant term. */
1845 if (XEXP (*p
, 0) != 0)
1847 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1852 if (XEXP (*p
, 1) != 0)
1854 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1862 /* Return 1 if OP is a memory reference
1863 whose address contains no side effects
1864 and remains valid after the addition
1865 of a positive integer less than the
1866 size of the object being referenced.
1868 We assume that the original address is valid and do not check it.
1870 This uses strict_memory_address_p as a subroutine, so
1871 don't use it before reload. */
1874 offsettable_memref_p (rtx op
)
1876 return ((MEM_P (op
))
1877 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1880 /* Similar, but don't require a strictly valid mem ref:
1881 consider pseudo-regs valid as index or base regs. */
1884 offsettable_nonstrict_memref_p (rtx op
)
1886 return ((MEM_P (op
))
1887 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1890 /* Return 1 if Y is a memory address which contains no side effects
1891 and would remain valid after the addition of a positive integer
1892 less than the size of that mode.
1894 We assume that the original address is valid and do not check it.
1895 We do check that it is valid for narrower modes.
1897 If STRICTP is nonzero, we require a strictly valid address,
1898 for the sake of use in reload.c. */
1901 offsettable_address_p (int strictp
, enum machine_mode mode
, rtx y
)
1903 enum rtx_code ycode
= GET_CODE (y
);
1907 int (*addressp
) (enum machine_mode
, rtx
) =
1908 (strictp
? strict_memory_address_p
: memory_address_p
);
1909 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1911 if (CONSTANT_ADDRESS_P (y
))
1914 /* Adjusting an offsettable address involves changing to a narrower mode.
1915 Make sure that's OK. */
1917 if (mode_dependent_address_p (y
))
1920 /* ??? How much offset does an offsettable BLKmode reference need?
1921 Clearly that depends on the situation in which it's being used.
1922 However, the current situation in which we test 0xffffffff is
1923 less than ideal. Caveat user. */
1925 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1927 /* If the expression contains a constant term,
1928 see if it remains valid when max possible offset is added. */
1930 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1935 *y2
= plus_constant (*y2
, mode_sz
- 1);
1936 /* Use QImode because an odd displacement may be automatically invalid
1937 for any wider mode. But it should be valid for a single byte. */
1938 good
= (*addressp
) (QImode
, y
);
1940 /* In any case, restore old contents of memory. */
1945 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1948 /* The offset added here is chosen as the maximum offset that
1949 any instruction could need to add when operating on something
1950 of the specified mode. We assume that if Y and Y+c are
1951 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1952 go inside a LO_SUM here, so we do so as well. */
1953 if (GET_CODE (y
) == LO_SUM
1955 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
1956 z
= gen_rtx_LO_SUM (GET_MODE (y
), XEXP (y
, 0),
1957 plus_constant (XEXP (y
, 1), mode_sz
- 1));
1959 z
= plus_constant (y
, mode_sz
- 1);
1961 /* Use QImode because an odd displacement may be automatically invalid
1962 for any wider mode. But it should be valid for a single byte. */
1963 return (*addressp
) (QImode
, z
);
1966 /* Return 1 if ADDR is an address-expression whose effect depends
1967 on the mode of the memory reference it is used in.
1969 Autoincrement addressing is a typical example of mode-dependence
1970 because the amount of the increment depends on the mode. */
1973 mode_dependent_address_p (rtx addr ATTRIBUTE_UNUSED
/* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */)
1975 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1977 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1978 win
: ATTRIBUTE_UNUSED_LABEL
1982 /* Like extract_insn, but save insn extracted and don't extract again, when
1983 called again for the same insn expecting that recog_data still contain the
1984 valid information. This is used primary by gen_attr infrastructure that
1985 often does extract insn again and again. */
1987 extract_insn_cached (rtx insn
)
1989 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
1991 extract_insn (insn
);
1992 recog_data
.insn
= insn
;
1995 /* Do cached extract_insn, constrain_operands and complain about failures.
1996 Used by insn_attrtab. */
1998 extract_constrain_insn_cached (rtx insn
)
2000 extract_insn_cached (insn
);
2001 if (which_alternative
== -1
2002 && !constrain_operands (reload_completed
))
2003 fatal_insn_not_found (insn
);
2006 /* Do cached constrain_operands and complain about failures. */
2008 constrain_operands_cached (int strict
)
2010 if (which_alternative
== -1)
2011 return constrain_operands (strict
);
2016 /* Analyze INSN and fill in recog_data. */
2019 extract_insn (rtx insn
)
2024 rtx body
= PATTERN (insn
);
2026 recog_data
.insn
= NULL
;
2027 recog_data
.n_operands
= 0;
2028 recog_data
.n_alternatives
= 0;
2029 recog_data
.n_dups
= 0;
2030 which_alternative
= -1;
2032 switch (GET_CODE (body
))
2042 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2047 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2048 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2049 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2055 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2058 /* This insn is an `asm' with operands. */
2060 /* expand_asm_operands makes sure there aren't too many operands. */
2061 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2063 /* Now get the operand values and constraints out of the insn. */
2064 decode_asm_operands (body
, recog_data
.operand
,
2065 recog_data
.operand_loc
,
2066 recog_data
.constraints
,
2067 recog_data
.operand_mode
);
2070 const char *p
= recog_data
.constraints
[0];
2071 recog_data
.n_alternatives
= 1;
2073 recog_data
.n_alternatives
+= (*p
++ == ',');
2077 fatal_insn_not_found (insn
);
2081 /* Ordinary insn: recognize it, get the operands via insn_extract
2082 and get the constraints. */
2084 icode
= recog_memoized (insn
);
2086 fatal_insn_not_found (insn
);
2088 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2089 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2090 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2092 insn_extract (insn
);
2094 for (i
= 0; i
< noperands
; i
++)
2096 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2097 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2098 /* VOIDmode match_operands gets mode from their real operand. */
2099 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2100 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2103 for (i
= 0; i
< noperands
; i
++)
2104 recog_data
.operand_type
[i
]
2105 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2106 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2109 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2112 /* After calling extract_insn, you can use this function to extract some
2113 information from the constraint strings into a more usable form.
2114 The collected data is stored in recog_op_alt. */
2116 preprocess_constraints (void)
2120 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2121 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2122 * sizeof (struct operand_alternative
)));
2124 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2127 struct operand_alternative
*op_alt
;
2128 const char *p
= recog_data
.constraints
[i
];
2130 op_alt
= recog_op_alt
[i
];
2132 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2134 op_alt
[j
].cl
= NO_REGS
;
2135 op_alt
[j
].constraint
= p
;
2136 op_alt
[j
].matches
= -1;
2137 op_alt
[j
].matched
= -1;
2139 if (*p
== '\0' || *p
== ',')
2141 op_alt
[j
].anything_ok
= 1;
2151 while (c
!= ',' && c
!= '\0');
2152 if (c
== ',' || c
== '\0')
2160 case '=': case '+': case '*': case '%':
2161 case 'E': case 'F': case 'G': case 'H':
2162 case 's': case 'i': case 'n':
2163 case 'I': case 'J': case 'K': case 'L':
2164 case 'M': case 'N': case 'O': case 'P':
2165 /* These don't say anything we care about. */
2169 op_alt
[j
].reject
+= 6;
2172 op_alt
[j
].reject
+= 600;
2175 op_alt
[j
].earlyclobber
= 1;
2178 case '0': case '1': case '2': case '3': case '4':
2179 case '5': case '6': case '7': case '8': case '9':
2182 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2183 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2189 op_alt
[j
].memory_ok
= 1;
2192 op_alt
[j
].decmem_ok
= 1;
2195 op_alt
[j
].incmem_ok
= 1;
2198 op_alt
[j
].nonoffmem_ok
= 1;
2201 op_alt
[j
].offmem_ok
= 1;
2204 op_alt
[j
].anything_ok
= 1;
2208 op_alt
[j
].is_address
= 1;
2209 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2210 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
2216 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2220 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2222 op_alt
[j
].memory_ok
= 1;
2225 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2227 op_alt
[j
].is_address
= 1;
2229 = (reg_class_subunion
2230 [(int) op_alt
[j
].cl
]
2231 [(int) MODE_BASE_REG_CLASS (VOIDmode
)]);
2236 = (reg_class_subunion
2237 [(int) op_alt
[j
].cl
]
2238 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2241 p
+= CONSTRAINT_LEN (c
, p
);
2247 /* Check the operands of an insn against the insn's operand constraints
2248 and return 1 if they are valid.
2249 The information about the insn's operands, constraints, operand modes
2250 etc. is obtained from the global variables set up by extract_insn.
2252 WHICH_ALTERNATIVE is set to a number which indicates which
2253 alternative of constraints was matched: 0 for the first alternative,
2254 1 for the next, etc.
2256 In addition, when two operands are required to match
2257 and it happens that the output operand is (reg) while the
2258 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2259 make the output operand look like the input.
2260 This is because the output operand is the one the template will print.
2262 This is used in final, just before printing the assembler code and by
2263 the routines that determine an insn's attribute.
2265 If STRICT is a positive nonzero value, it means that we have been
2266 called after reload has been completed. In that case, we must
2267 do all checks strictly. If it is zero, it means that we have been called
2268 before reload has completed. In that case, we first try to see if we can
2269 find an alternative that matches strictly. If not, we try again, this
2270 time assuming that reload will fix up the insn. This provides a "best
2271 guess" for the alternative and is used to compute attributes of insns prior
2272 to reload. A negative value of STRICT is used for this internal call. */
2280 constrain_operands (int strict
)
2282 const char *constraints
[MAX_RECOG_OPERANDS
];
2283 int matching_operands
[MAX_RECOG_OPERANDS
];
2284 int earlyclobber
[MAX_RECOG_OPERANDS
];
2287 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2288 int funny_match_index
;
2290 which_alternative
= 0;
2291 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2294 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2296 constraints
[c
] = recog_data
.constraints
[c
];
2297 matching_operands
[c
] = -1;
2302 int seen_earlyclobber_at
= -1;
2305 funny_match_index
= 0;
2307 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2309 rtx op
= recog_data
.operand
[opno
];
2310 enum machine_mode mode
= GET_MODE (op
);
2311 const char *p
= constraints
[opno
];
2317 earlyclobber
[opno
] = 0;
2319 /* A unary operator may be accepted by the predicate, but it
2320 is irrelevant for matching constraints. */
2324 if (GET_CODE (op
) == SUBREG
)
2326 if (REG_P (SUBREG_REG (op
))
2327 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2328 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2329 GET_MODE (SUBREG_REG (op
)),
2332 op
= SUBREG_REG (op
);
2335 /* An empty constraint or empty alternative
2336 allows anything which matched the pattern. */
2337 if (*p
== 0 || *p
== ',')
2341 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2350 case '?': case '!': case '*': case '%':
2355 /* Ignore rest of this alternative as far as
2356 constraint checking is concerned. */
2359 while (*p
&& *p
!= ',');
2364 earlyclobber
[opno
] = 1;
2365 if (seen_earlyclobber_at
< 0)
2366 seen_earlyclobber_at
= opno
;
2369 case '0': case '1': case '2': case '3': case '4':
2370 case '5': case '6': case '7': case '8': case '9':
2372 /* This operand must be the same as a previous one.
2373 This kind of constraint is used for instructions such
2374 as add when they take only two operands.
2376 Note that the lower-numbered operand is passed first.
2378 If we are not testing strictly, assume that this
2379 constraint will be satisfied. */
2384 match
= strtoul (p
, &end
, 10);
2391 rtx op1
= recog_data
.operand
[match
];
2392 rtx op2
= recog_data
.operand
[opno
];
2394 /* A unary operator may be accepted by the predicate,
2395 but it is irrelevant for matching constraints. */
2397 op1
= XEXP (op1
, 0);
2399 op2
= XEXP (op2
, 0);
2401 val
= operands_match_p (op1
, op2
);
2404 matching_operands
[opno
] = match
;
2405 matching_operands
[match
] = opno
;
2410 /* If output is *x and input is *--x, arrange later
2411 to change the output to *--x as well, since the
2412 output op is the one that will be printed. */
2413 if (val
== 2 && strict
> 0)
2415 funny_match
[funny_match_index
].this = opno
;
2416 funny_match
[funny_match_index
++].other
= match
;
2423 /* p is used for address_operands. When we are called by
2424 gen_reload, no one will have checked that the address is
2425 strictly valid, i.e., that all pseudos requiring hard regs
2426 have gotten them. */
2428 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2433 /* No need to check general_operand again;
2434 it was done in insn-recog.c. Well, except that reload
2435 doesn't check the validity of its replacements, but
2436 that should only matter when there's a bug. */
2438 /* Anything goes unless it is a REG and really has a hard reg
2439 but the hard reg is not in the class GENERAL_REGS. */
2443 || GENERAL_REGS
== ALL_REGS
2444 || (reload_in_progress
2445 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2446 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2449 else if (strict
< 0 || general_operand (op
, mode
))
2454 /* This is used for a MATCH_SCRATCH in the cases when
2455 we don't actually need anything. So anything goes
2461 /* Memory operands must be valid, to the extent
2462 required by STRICT. */
2466 && !strict_memory_address_p (GET_MODE (op
),
2470 && !memory_address_p (GET_MODE (op
), XEXP (op
, 0)))
2474 /* Before reload, accept what reload can turn into mem. */
2475 else if (strict
< 0 && CONSTANT_P (op
))
2477 /* During reload, accept a pseudo */
2478 else if (reload_in_progress
&& REG_P (op
)
2479 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2485 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2486 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2492 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2493 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2499 if (GET_CODE (op
) == CONST_DOUBLE
2500 || (GET_CODE (op
) == CONST_VECTOR
2501 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2507 if (GET_CODE (op
) == CONST_DOUBLE
2508 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2513 if (GET_CODE (op
) == CONST_INT
2514 || (GET_CODE (op
) == CONST_DOUBLE
2515 && GET_MODE (op
) == VOIDmode
))
2518 if (CONSTANT_P (op
))
2523 if (GET_CODE (op
) == CONST_INT
2524 || (GET_CODE (op
) == CONST_DOUBLE
2525 && GET_MODE (op
) == VOIDmode
))
2537 if (GET_CODE (op
) == CONST_INT
2538 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2544 && ((strict
> 0 && ! offsettable_memref_p (op
))
2546 && !(CONSTANT_P (op
) || MEM_P (op
)))
2547 || (reload_in_progress
2549 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2554 if ((strict
> 0 && offsettable_memref_p (op
))
2555 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2556 /* Before reload, accept what reload can handle. */
2558 && (CONSTANT_P (op
) || MEM_P (op
)))
2559 /* During reload, accept a pseudo */
2560 || (reload_in_progress
&& REG_P (op
)
2561 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2570 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2576 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2577 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2579 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2582 #ifdef EXTRA_CONSTRAINT_STR
2583 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2586 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2587 /* Every memory operand can be reloaded to fit. */
2588 && ((strict
< 0 && MEM_P (op
))
2589 /* Before reload, accept what reload can turn
2591 || (strict
< 0 && CONSTANT_P (op
))
2592 /* During reload, accept a pseudo */
2593 || (reload_in_progress
&& REG_P (op
)
2594 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2596 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2597 /* Every address operand can be reloaded to fit. */
2604 while (p
+= len
, c
);
2606 constraints
[opno
] = p
;
2607 /* If this operand did not win somehow,
2608 this alternative loses. */
2612 /* This alternative won; the operands are ok.
2613 Change whichever operands this alternative says to change. */
2618 /* See if any earlyclobber operand conflicts with some other
2621 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2622 for (eopno
= seen_earlyclobber_at
;
2623 eopno
< recog_data
.n_operands
;
2625 /* Ignore earlyclobber operands now in memory,
2626 because we would often report failure when we have
2627 two memory operands, one of which was formerly a REG. */
2628 if (earlyclobber
[eopno
]
2629 && REG_P (recog_data
.operand
[eopno
]))
2630 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2631 if ((MEM_P (recog_data
.operand
[opno
])
2632 || recog_data
.operand_type
[opno
] != OP_OUT
)
2634 /* Ignore things like match_operator operands. */
2635 && *recog_data
.constraints
[opno
] != 0
2636 && ! (matching_operands
[opno
] == eopno
2637 && operands_match_p (recog_data
.operand
[opno
],
2638 recog_data
.operand
[eopno
]))
2639 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2640 recog_data
.operand
[eopno
]))
2645 while (--funny_match_index
>= 0)
2647 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2648 = recog_data
.operand
[funny_match
[funny_match_index
].this];
2655 which_alternative
++;
2657 while (which_alternative
< recog_data
.n_alternatives
);
2659 which_alternative
= -1;
2660 /* If we are about to reject this, but we are not to test strictly,
2661 try a very loose test. Only return failure if it fails also. */
2663 return constrain_operands (-1);
2668 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2669 is a hard reg in class CLASS when its regno is offset by OFFSET
2670 and changed to mode MODE.
2671 If REG occupies multiple hard regs, all of them must be in CLASS. */
2674 reg_fits_class_p (rtx operand
, enum reg_class cl
, int offset
,
2675 enum machine_mode mode
)
2677 int regno
= REGNO (operand
);
2678 if (regno
< FIRST_PSEUDO_REGISTER
2679 && TEST_HARD_REG_BIT (reg_class_contents
[(int) cl
],
2684 for (sr
= hard_regno_nregs
[regno
][mode
] - 1;
2686 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) cl
],
2695 /* Split single instruction. Helper function for split_all_insns and
2696 split_all_insns_noflow. Return last insn in the sequence if successful,
2697 or NULL if unsuccessful. */
2700 split_insn (rtx insn
)
2702 /* Split insns here to get max fine-grain parallelism. */
2703 rtx first
= PREV_INSN (insn
);
2704 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2709 /* try_split returns the NOTE that INSN became. */
2710 SET_INSN_DELETED (insn
);
2712 /* ??? Coddle to md files that generate subregs in post-reload
2713 splitters instead of computing the proper hard register. */
2714 if (reload_completed
&& first
!= last
)
2716 first
= NEXT_INSN (first
);
2720 cleanup_subreg_operands (first
);
2723 first
= NEXT_INSN (first
);
2729 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2732 split_all_insns (int upd_life
)
2738 blocks
= sbitmap_alloc (last_basic_block
);
2739 sbitmap_zero (blocks
);
2742 FOR_EACH_BB_REVERSE (bb
)
2745 bool finish
= false;
2747 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2749 /* Can't use `next_real_insn' because that might go across
2750 CODE_LABELS and short-out basic blocks. */
2751 next
= NEXT_INSN (insn
);
2752 finish
= (insn
== BB_END (bb
));
2755 rtx set
= single_set (insn
);
2757 /* Don't split no-op move insns. These should silently
2758 disappear later in final. Splitting such insns would
2759 break the code that handles REG_NO_CONFLICT blocks. */
2760 if (set
&& set_noop_p (set
))
2762 /* Nops get in the way while scheduling, so delete them
2763 now if register allocation has already been done. It
2764 is too risky to try to do this before register
2765 allocation, and there are unlikely to be very many
2766 nops then anyways. */
2767 if (reload_completed
)
2769 /* If the no-op set has a REG_UNUSED note, we need
2770 to update liveness information. */
2771 if (find_reg_note (insn
, REG_UNUSED
, NULL_RTX
))
2773 SET_BIT (blocks
, bb
->index
);
2776 /* ??? Is life info affected by deleting edges? */
2777 delete_insn_and_edges (insn
);
2782 rtx last
= split_insn (insn
);
2785 /* The split sequence may include barrier, but the
2786 BB boundary we are interested in will be set to
2789 while (BARRIER_P (last
))
2790 last
= PREV_INSN (last
);
2791 SET_BIT (blocks
, bb
->index
);
2801 int old_last_basic_block
= last_basic_block
;
2803 find_many_sub_basic_blocks (blocks
);
2805 if (old_last_basic_block
!= last_basic_block
&& upd_life
)
2806 blocks
= sbitmap_resize (blocks
, last_basic_block
, 1);
2809 if (changed
&& upd_life
)
2810 update_life_info (blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
2813 #ifdef ENABLE_CHECKING
2814 verify_flow_info ();
2817 sbitmap_free (blocks
);
2820 /* Same as split_all_insns, but do not expect CFG to be available.
2821 Used by machine dependent reorg passes. */
2824 split_all_insns_noflow (void)
2828 for (insn
= get_insns (); insn
; insn
= next
)
2830 next
= NEXT_INSN (insn
);
2833 /* Don't split no-op move insns. These should silently
2834 disappear later in final. Splitting such insns would
2835 break the code that handles REG_NO_CONFLICT blocks. */
2836 rtx set
= single_set (insn
);
2837 if (set
&& set_noop_p (set
))
2839 /* Nops get in the way while scheduling, so delete them
2840 now if register allocation has already been done. It
2841 is too risky to try to do this before register
2842 allocation, and there are unlikely to be very many
2845 ??? Should we use delete_insn when the CFG isn't valid? */
2846 if (reload_completed
)
2847 delete_insn_and_edges (insn
);
2855 #ifdef HAVE_peephole2
2856 struct peep2_insn_data
2862 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2863 static int peep2_current
;
2864 /* The number of instructions available to match a peep2. */
2865 int peep2_current_count
;
2867 /* A non-insn marker indicating the last insn of the block.
2868 The live_before regset for this element is correct, indicating
2869 global_live_at_end for the block. */
2870 #define PEEP2_EOB pc_rtx
2872 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2873 does not exist. Used by the recognizer to find the next insn to match
2874 in a multi-insn pattern. */
2877 peep2_next_insn (int n
)
2879 gcc_assert (n
<= peep2_current_count
);
2882 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2883 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2885 return peep2_insn_data
[n
].insn
;
2888 /* Return true if REGNO is dead before the Nth non-note insn
2892 peep2_regno_dead_p (int ofs
, int regno
)
2894 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
2896 ofs
+= peep2_current
;
2897 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2898 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2900 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
2902 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
2905 /* Similarly for a REG. */
2908 peep2_reg_dead_p (int ofs
, rtx reg
)
2912 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
2914 ofs
+= peep2_current
;
2915 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2916 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2918 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
2920 regno
= REGNO (reg
);
2921 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2923 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
2928 /* Try to find a hard register of mode MODE, matching the register class in
2929 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2930 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2931 in which case the only condition is that the register must be available
2932 before CURRENT_INSN.
2933 Registers that already have bits set in REG_SET will not be considered.
2935 If an appropriate register is available, it will be returned and the
2936 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2940 peep2_find_free_register (int from
, int to
, const char *class_str
,
2941 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
2943 static int search_ofs
;
2948 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
2949 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
2951 from
+= peep2_current
;
2952 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
2953 from
-= MAX_INSNS_PER_PEEP2
+ 1;
2954 to
+= peep2_current
;
2955 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
2956 to
-= MAX_INSNS_PER_PEEP2
+ 1;
2958 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
2959 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
2963 HARD_REG_SET this_live
;
2965 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
2967 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
2968 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
2969 IOR_HARD_REG_SET (live
, this_live
);
2972 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
2973 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
2975 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2977 int raw_regno
, regno
, success
, j
;
2979 /* Distribute the free registers as much as possible. */
2980 raw_regno
= search_ofs
+ i
;
2981 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
2982 raw_regno
-= FIRST_PSEUDO_REGISTER
;
2983 #ifdef REG_ALLOC_ORDER
2984 regno
= reg_alloc_order
[raw_regno
];
2989 /* Don't allocate fixed registers. */
2990 if (fixed_regs
[regno
])
2992 /* Make sure the register is of the right class. */
2993 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
))
2995 /* And can support the mode we need. */
2996 if (! HARD_REGNO_MODE_OK (regno
, mode
))
2998 /* And that we don't create an extra save/restore. */
2999 if (! call_used_regs
[regno
] && ! regs_ever_live
[regno
])
3001 /* And we don't clobber traceback for noreturn functions. */
3002 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
3003 && (! reload_completed
|| frame_pointer_needed
))
3007 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
3009 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3010 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3018 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
3019 SET_HARD_REG_BIT (*reg_set
, regno
+ j
);
3021 /* Start the next search with the next register. */
3022 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3024 search_ofs
= raw_regno
;
3026 return gen_rtx_REG (mode
, regno
);
3034 /* Perform the peephole2 optimization pass. */
3037 peephole2_optimize (FILE *dump_file ATTRIBUTE_UNUSED
)
3043 #ifdef HAVE_conditional_execution
3047 bool do_cleanup_cfg
= false;
3048 bool do_global_life_update
= false;
3049 bool do_rebuild_jump_labels
= false;
3051 /* Initialize the regsets we're going to use. */
3052 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3053 peep2_insn_data
[i
].live_before
= ALLOC_REG_SET (®_obstack
);
3054 live
= ALLOC_REG_SET (®_obstack
);
3056 #ifdef HAVE_conditional_execution
3057 blocks
= sbitmap_alloc (last_basic_block
);
3058 sbitmap_zero (blocks
);
3061 count_or_remove_death_notes (NULL
, 1);
3064 FOR_EACH_BB_REVERSE (bb
)
3066 struct propagate_block_info
*pbi
;
3067 reg_set_iterator rsi
;
3070 /* Indicate that all slots except the last holds invalid data. */
3071 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3072 peep2_insn_data
[i
].insn
= NULL_RTX
;
3073 peep2_current_count
= 0;
3075 /* Indicate that the last slot contains live_after data. */
3076 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3077 peep2_current
= MAX_INSNS_PER_PEEP2
;
3079 /* Start up propagation. */
3080 COPY_REG_SET (live
, bb
->il
.rtl
->global_live_at_end
);
3081 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3083 #ifdef HAVE_conditional_execution
3084 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, 0);
3086 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, PROP_DEATH_NOTES
);
3089 for (insn
= BB_END (bb
); ; insn
= prev
)
3091 prev
= PREV_INSN (insn
);
3094 rtx
try, before_try
, x
;
3097 bool was_call
= false;
3099 /* Record this insn. */
3100 if (--peep2_current
< 0)
3101 peep2_current
= MAX_INSNS_PER_PEEP2
;
3102 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
3103 && peep2_insn_data
[peep2_current
].insn
== NULL_RTX
)
3104 peep2_current_count
++;
3105 peep2_insn_data
[peep2_current
].insn
= insn
;
3106 propagate_one_insn (pbi
, insn
);
3107 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3109 if (RTX_FRAME_RELATED_P (insn
))
3111 /* If an insn has RTX_FRAME_RELATED_P set, peephole
3112 substitution would lose the
3113 REG_FRAME_RELATED_EXPR that is attached. */
3114 peep2_current_count
= 0;
3118 /* Match the peephole. */
3119 try = peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3123 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3124 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3125 cfg-related call notes. */
3126 for (i
= 0; i
<= match_len
; ++i
)
3129 rtx old_insn
, new_insn
, note
;
3131 j
= i
+ peep2_current
;
3132 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3133 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3134 old_insn
= peep2_insn_data
[j
].insn
;
3135 if (!CALL_P (old_insn
))
3140 while (new_insn
!= NULL_RTX
)
3142 if (CALL_P (new_insn
))
3144 new_insn
= NEXT_INSN (new_insn
);
3147 gcc_assert (new_insn
!= NULL_RTX
);
3149 CALL_INSN_FUNCTION_USAGE (new_insn
)
3150 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3152 for (note
= REG_NOTES (old_insn
);
3154 note
= XEXP (note
, 1))
3155 switch (REG_NOTE_KIND (note
))
3159 REG_NOTES (new_insn
)
3160 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note
),
3162 REG_NOTES (new_insn
));
3164 /* Discard all other reg notes. */
3168 /* Croak if there is another call in the sequence. */
3169 while (++i
<= match_len
)
3171 j
= i
+ peep2_current
;
3172 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3173 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3174 old_insn
= peep2_insn_data
[j
].insn
;
3175 gcc_assert (!CALL_P (old_insn
));
3180 i
= match_len
+ peep2_current
;
3181 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3182 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3184 note
= find_reg_note (peep2_insn_data
[i
].insn
,
3185 REG_EH_REGION
, NULL_RTX
);
3187 /* Replace the old sequence with the new. */
3188 try = emit_insn_after_setloc (try, peep2_insn_data
[i
].insn
,
3189 INSN_LOCATOR (peep2_insn_data
[i
].insn
));
3190 before_try
= PREV_INSN (insn
);
3191 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
);
3193 /* Re-insert the EH_REGION notes. */
3194 if (note
|| (was_call
&& nonlocal_goto_handler_labels
))
3199 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3200 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3203 for (x
= try ; x
!= before_try
; x
= PREV_INSN (x
))
3205 || (flag_non_call_exceptions
3206 && may_trap_p (PATTERN (x
))
3207 && !find_reg_note (x
, REG_EH_REGION
, NULL
)))
3211 = gen_rtx_EXPR_LIST (REG_EH_REGION
,
3215 if (x
!= BB_END (bb
) && eh_edge
)
3220 nfte
= split_block (bb
, x
);
3221 flags
= (eh_edge
->flags
3222 & (EDGE_EH
| EDGE_ABNORMAL
));
3224 flags
|= EDGE_ABNORMAL_CALL
;
3225 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3228 nehe
->probability
= eh_edge
->probability
;
3230 = REG_BR_PROB_BASE
- nehe
->probability
;
3232 do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3233 #ifdef HAVE_conditional_execution
3234 SET_BIT (blocks
, nfte
->dest
->index
);
3242 /* Converting possibly trapping insn to non-trapping is
3243 possible. Zap dummy outgoing edges. */
3244 do_cleanup_cfg
|= purge_dead_edges (bb
);
3247 #ifdef HAVE_conditional_execution
3248 /* With conditional execution, we cannot back up the
3249 live information so easily, since the conditional
3250 death data structures are not so self-contained.
3251 So record that we've made a modification to this
3252 block and update life information at the end. */
3253 SET_BIT (blocks
, bb
->index
);
3256 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3257 peep2_insn_data
[i
].insn
= NULL_RTX
;
3258 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3259 peep2_current_count
= 0;
3261 /* Back up lifetime information past the end of the
3262 newly created sequence. */
3263 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3265 COPY_REG_SET (live
, peep2_insn_data
[i
].live_before
);
3267 /* Update life information for the new sequence. */
3274 i
= MAX_INSNS_PER_PEEP2
;
3275 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
3276 && peep2_insn_data
[i
].insn
== NULL_RTX
)
3277 peep2_current_count
++;
3278 peep2_insn_data
[i
].insn
= x
;
3279 propagate_one_insn (pbi
, x
);
3280 COPY_REG_SET (peep2_insn_data
[i
].live_before
, live
);
3286 /* ??? Should verify that LIVE now matches what we
3287 had before the new sequence. */
3292 /* If we generated a jump instruction, it won't have
3293 JUMP_LABEL set. Recompute after we're done. */
3294 for (x
= try; x
!= before_try
; x
= PREV_INSN (x
))
3297 do_rebuild_jump_labels
= true;
3303 if (insn
== BB_HEAD (bb
))
3307 /* Some peepholes can decide the don't need one or more of their
3308 inputs. If this happens, local life update is not enough. */
3309 EXECUTE_IF_AND_COMPL_IN_BITMAP (bb
->il
.rtl
->global_live_at_start
, live
,
3312 do_global_life_update
= true;
3316 free_propagate_block_info (pbi
);
3319 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3320 FREE_REG_SET (peep2_insn_data
[i
].live_before
);
3321 FREE_REG_SET (live
);
3323 if (do_rebuild_jump_labels
)
3324 rebuild_jump_labels (get_insns ());
3326 /* If we eliminated EH edges, we may be able to merge blocks. Further,
3327 we've changed global life since exception handlers are no longer
3332 do_global_life_update
= true;
3334 if (do_global_life_update
)
3335 update_life_info (0, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
3336 #ifdef HAVE_conditional_execution
3339 count_or_remove_death_notes (blocks
, 1);
3340 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
3342 sbitmap_free (blocks
);
3345 #endif /* HAVE_peephole2 */
3347 /* Common predicates for use with define_bypass. */
3349 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3350 data not the address operand(s) of the store. IN_INSN must be
3351 single_set. OUT_INSN must be either a single_set or a PARALLEL with
3355 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3357 rtx out_set
, in_set
;
3359 in_set
= single_set (in_insn
);
3360 gcc_assert (in_set
);
3362 if (!MEM_P (SET_DEST (in_set
)))
3365 out_set
= single_set (out_insn
);
3368 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3376 out_pat
= PATTERN (out_insn
);
3377 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3379 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3381 rtx exp
= XVECEXP (out_pat
, 0, i
);
3383 if (GET_CODE (exp
) == CLOBBER
)
3386 gcc_assert (GET_CODE (exp
) == SET
);
3388 if (reg_mentioned_p (SET_DEST (exp
), SET_DEST (in_set
)))
3396 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3397 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3398 or multiple set; IN_INSN should be single_set for truth, but for convenience
3399 of insn categorization may be any JUMP or CALL insn. */
3402 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3404 rtx out_set
, in_set
;
3406 in_set
= single_set (in_insn
);
3409 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3413 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3415 in_set
= SET_SRC (in_set
);
3417 out_set
= single_set (out_insn
);
3420 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3421 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3429 out_pat
= PATTERN (out_insn
);
3430 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3432 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3434 rtx exp
= XVECEXP (out_pat
, 0, i
);
3436 if (GET_CODE (exp
) == CLOBBER
)
3439 gcc_assert (GET_CODE (exp
) == SET
);
3441 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3442 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3451 gate_handle_peephole2 (void)
3453 return (optimize
> 0 && flag_peephole2
);
3457 rest_of_handle_peephole2 (void)
3459 #ifdef HAVE_peephole2
3460 peephole2_optimize (dump_file
);
3464 struct tree_opt_pass pass_peephole2
=
3466 "peephole2", /* name */
3467 gate_handle_peephole2
, /* gate */
3468 rest_of_handle_peephole2
, /* execute */
3471 0, /* static_pass_number */
3472 TV_PEEPHOLE2
, /* tv_id */
3473 0, /* properties_required */
3474 0, /* properties_provided */
3475 0, /* properties_destroyed */
3476 0, /* todo_flags_start */
3477 TODO_dump_func
, /* todo_flags_finish */
3482 rest_of_handle_split_all_insns (void)
3484 split_all_insns (1);
3487 struct tree_opt_pass pass_split_all_insns
=
3489 "split1", /* name */
3491 rest_of_handle_split_all_insns
, /* execute */
3494 0, /* static_pass_number */
3496 0, /* properties_required */
3497 0, /* properties_provided */
3498 0, /* properties_destroyed */
3499 0, /* todo_flags_start */
3500 TODO_dump_func
, /* todo_flags_finish */
3504 /* The placement of the splitting that we do for shorten_branches
3505 depends on whether regstack is used by the target or not. */
3507 gate_do_final_split (void)
3509 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3516 struct tree_opt_pass pass_split_for_shorten_branches
=
3518 "split3", /* name */
3519 gate_do_final_split
, /* gate */
3520 split_all_insns_noflow
, /* execute */
3523 0, /* static_pass_number */
3524 TV_SHORTEN_BRANCH
, /* tv_id */
3525 0, /* properties_required */
3526 0, /* properties_provided */
3527 0, /* properties_destroyed */
3528 0, /* todo_flags_start */
3529 TODO_dump_func
, /* todo_flags_finish */
3535 gate_handle_split_before_regstack (void)
3537 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3538 /* If flow2 creates new instructions which need splitting
3539 and scheduling after reload is not done, they might not be
3540 split until final which doesn't allow splitting
3541 if HAVE_ATTR_length. */
3542 # ifdef INSN_SCHEDULING
3543 return (optimize
&& !flag_schedule_insns_after_reload
);
3552 struct tree_opt_pass pass_split_before_regstack
=
3554 "split2", /* name */
3555 gate_handle_split_before_regstack
, /* gate */
3556 rest_of_handle_split_all_insns
, /* execute */
3559 0, /* static_pass_number */
3560 TV_SHORTEN_BRANCH
, /* tv_id */
3561 0, /* properties_required */
3562 0, /* properties_provided */
3563 0, /* properties_destroyed */
3564 0, /* todo_flags_start */
3565 TODO_dump_func
, /* todo_flags_finish */