| blob | 54942d52080dc1dd4f9e6eeaedbe270b3cd42646 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
91 #ifndef CHECK_STACK_LIMIT
92 #define CHECK_STACK_LIMIT (-1)
93 #endif
95 /* Return index of given mode in mult and division cost tables. */
96 #define MODE_INDEX(mode) \
97 ((mode) == QImode ? 0 \
98 : (mode) == HImode ? 1 \
99 : (mode) == SImode ? 2 \
100 : (mode) == DImode ? 3 \
101 : 4)
103 /* Processor costs (relative to an add) */
104 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
105 #define COSTS_N_BYTES(N) ((N) * 2)
107 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
116 const
139 in QImode, HImode and SImode.
140 Relative to reg-reg move (2). */
144 in SFmode, DFmode and XFmode */
146 in SFmode, DFmode and XFmode */
149 in SImode and DImode */
151 in SImode and DImode */
154 in SImode, DImode and TImode */
156 in SImode, DImode and TImode */
169 ix86_size_memcpy,
170 ix86_size_memset,
182 };
184 /* Processor costs (relative to an add) */
187 DUMMY_STRINGOP_ALGS};
190 DUMMY_STRINGOP_ALGS};
192 static const
215 in QImode, HImode and SImode.
216 Relative to reg-reg move (2). */
220 in SFmode, DFmode and XFmode */
222 in SFmode, DFmode and XFmode */
225 in SImode and DImode */
227 in SImode and DImode */
230 in SImode, DImode and TImode */
232 in SImode, DImode and TImode */
245 i386_memcpy,
246 i386_memset,
258 };
262 DUMMY_STRINGOP_ALGS};
265 DUMMY_STRINGOP_ALGS};
267 static const
290 in QImode, HImode and SImode.
291 Relative to reg-reg move (2). */
295 in SFmode, DFmode and XFmode */
297 in SFmode, DFmode and XFmode */
300 in SImode and DImode */
302 in SImode and DImode */
305 in SImode, DImode and TImode */
307 in SImode, DImode and TImode */
310 shared for code and data, so 4kB is
311 not really precise. */
322 i486_memcpy,
323 i486_memset,
335 };
339 DUMMY_STRINGOP_ALGS};
342 DUMMY_STRINGOP_ALGS};
344 static const
367 in QImode, HImode and SImode.
368 Relative to reg-reg move (2). */
372 in SFmode, DFmode and XFmode */
374 in SFmode, DFmode and XFmode */
377 in SImode and DImode */
379 in SImode and DImode */
382 in SImode, DImode and TImode */
384 in SImode, DImode and TImode */
397 pentium_memcpy,
398 pentium_memset,
410 };
412 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
413 (we ensure the alignment). For small blocks inline loop is still a
414 noticeable win, for bigger blocks either rep movsl or rep movsb is
415 way to go. Rep movsb has apparently more expensive startup time in CPU,
416 but after 4K the difference is down in the noise. */
421 DUMMY_STRINGOP_ALGS};
426 DUMMY_STRINGOP_ALGS};
427 static const
450 in QImode, HImode and SImode.
451 Relative to reg-reg move (2). */
455 in SFmode, DFmode and XFmode */
457 in SFmode, DFmode and XFmode */
460 in SImode and DImode */
462 in SImode and DImode */
465 in SImode, DImode and TImode */
467 in SImode, DImode and TImode */
480 pentiumpro_memcpy,
481 pentiumpro_memset,
493 };
497 DUMMY_STRINGOP_ALGS};
500 DUMMY_STRINGOP_ALGS};
501 static const
524 in QImode, HImode and SImode.
525 Relative to reg-reg move (2). */
529 in SFmode, DFmode and XFmode */
531 in SFmode, DFmode and XFmode */
535 in SImode and DImode */
537 in SImode and DImode */
540 in SImode, DImode and TImode */
542 in SImode, DImode and TImode */
555 geode_memcpy,
556 geode_memset,
568 };
572 DUMMY_STRINGOP_ALGS};
575 DUMMY_STRINGOP_ALGS};
576 static const
599 in QImode, HImode and SImode.
600 Relative to reg-reg move (2). */
604 in SFmode, DFmode and XFmode */
606 in SFmode, DFmode and XFmode */
609 in SImode and DImode */
611 in SImode and DImode */
614 in SImode, DImode and TImode */
616 in SImode, DImode and TImode */
620 have integrated l2 cache, but
621 optimizing for k6 is not important
622 enough to worry about that. */
632 k6_memcpy,
633 k6_memset,
645 };
647 /* For some reason, Athlon deals better with REP prefix (relative to loops)
648 compared to K8. Alignment becomes important after 8 bytes for memcpy and
649 128 bytes for memset. */
652 DUMMY_STRINGOP_ALGS};
655 DUMMY_STRINGOP_ALGS};
656 static const
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
684 in SFmode, DFmode and XFmode */
686 in SFmode, DFmode and XFmode */
689 in SImode and DImode */
691 in SImode and DImode */
694 in SImode, DImode and TImode */
696 in SImode, DImode and TImode */
709 athlon_memcpy,
710 athlon_memset,
722 };
724 /* K8 has optimized REP instruction for medium sized blocks, but for very
725 small blocks it is better to use loop. For large blocks, libcall can
726 do nontemporary accesses and beat inline considerably. */
737 static const
760 in QImode, HImode and SImode.
761 Relative to reg-reg move (2). */
765 in SFmode, DFmode and XFmode */
767 in SFmode, DFmode and XFmode */
770 in SImode and DImode */
772 in SImode and DImode */
775 in SImode, DImode and TImode */
777 in SImode, DImode and TImode */
782 /* New AMD processors never drop prefetches; if they cannot be performed
783 immediately, they are queued. We set number of simultaneous prefetches
784 to a large constant to reflect this (it probably is not a good idea not
785 to limit number of prefetches at all, as their execution also takes some
786 time). */
796 k8_memcpy,
797 k8_memset,
809 };
811 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
812 very small blocks it is better to use loop. For large blocks, libcall can
813 do nontemporary accesses and beat inline considerably. */
846 in QImode, HImode and SImode.
847 Relative to reg-reg move (2). */
851 in SFmode, DFmode and XFmode */
853 in SFmode, DFmode and XFmode */
856 in SImode and DImode */
858 in SImode and DImode */
861 in SImode, DImode and TImode */
863 in SImode, DImode and TImode */
865 /* On K8:
866 MOVD reg64, xmmreg Double FSTORE 4
867 MOVD reg32, xmmreg Double FSTORE 4
868 On AMDFAM10:
869 MOVD reg64, xmmreg Double FADD 3
870 1/1 1/1
871 MOVD reg32, xmmreg Double FADD 3
872 1/1 1/1 */
876 /* New AMD processors never drop prefetches; if they cannot be performed
877 immediately, they are queued. We set number of simultaneous prefetches
878 to a large constant to reflect this (it probably is not a good idea not
879 to limit number of prefetches at all, as their execution also takes some
880 time). */
890 amdfam10_memcpy,
891 amdfam10_memset,
903 };
905 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
906 very small blocks it is better to use loop. For large blocks, libcall
907 can do nontemporary accesses and beat inline considerably. */
941 in QImode, HImode and SImode.
942 Relative to reg-reg move (2). */
946 in SFmode, DFmode and XFmode */
948 in SFmode, DFmode and XFmode */
951 in SImode and DImode */
953 in SImode and DImode */
956 in SImode, DImode and TImode */
958 in SImode, DImode and TImode */
960 /* On K8:
961 MOVD reg64, xmmreg Double FSTORE 4
962 MOVD reg32, xmmreg Double FSTORE 4
963 On AMDFAM10:
964 MOVD reg64, xmmreg Double FADD 3
965 1/1 1/1
966 MOVD reg32, xmmreg Double FADD 3
967 1/1 1/1 */
971 /* New AMD processors never drop prefetches; if they cannot be performed
972 immediately, they are queued. We set number of simultaneous prefetches
973 to a large constant to reflect this (it probably is not a good idea not
974 to limit number of prefetches at all, as their execution also takes some
975 time). */
985 bdver1_memcpy,
986 bdver1_memset,
998 };
1000 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1001 very small blocks it is better to use loop. For large blocks, libcall
1002 can do nontemporary accesses and beat inline considerably. */
1037 in QImode, HImode and SImode.
1038 Relative to reg-reg move (2). */
1042 in SFmode, DFmode and XFmode */
1044 in SFmode, DFmode and XFmode */
1047 in SImode and DImode */
1049 in SImode and DImode */
1052 in SImode, DImode and TImode */
1054 in SImode, DImode and TImode */
1056 /* On K8:
1057 MOVD reg64, xmmreg Double FSTORE 4
1058 MOVD reg32, xmmreg Double FSTORE 4
1059 On AMDFAM10:
1060 MOVD reg64, xmmreg Double FADD 3
1061 1/1 1/1
1062 MOVD reg32, xmmreg Double FADD 3
1063 1/1 1/1 */
1067 /* New AMD processors never drop prefetches; if they cannot be performed
1068 immediately, they are queued. We set number of simultaneous prefetches
1069 to a large constant to reflect this (it probably is not a good idea not
1070 to limit number of prefetches at all, as their execution also takes some
1071 time). */
1081 bdver2_memcpy,
1082 bdver2_memset,
1094 };
1097 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1098 very small blocks it is better to use loop. For large blocks, libcall
1099 can do nontemporary accesses and beat inline considerably. */
1132 in QImode, HImode and SImode.
1133 Relative to reg-reg move (2). */
1137 in SFmode, DFmode and XFmode */
1139 in SFmode, DFmode and XFmode */
1142 in SImode and DImode */
1144 in SImode and DImode */
1147 in SImode, DImode and TImode */
1149 in SImode, DImode and TImode */
1154 /* New AMD processors never drop prefetches; if they cannot be performed
1155 immediately, they are queued. We set number of simultaneous prefetches
1156 to a large constant to reflect this (it probably is not a good idea not
1157 to limit number of prefetches at all, as their execution also takes some
1158 time). */
1168 bdver3_memcpy,
1169 bdver3_memset,
1181 };
1183 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1184 very small blocks it is better to use loop. For large blocks, libcall
1185 can do nontemporary accesses and beat inline considerably. */
1218 in QImode, HImode and SImode.
1219 Relative to reg-reg move (2). */
1223 in SFmode, DFmode and XFmode */
1225 in SFmode, DFmode and XFmode */
1228 in SImode and DImode */
1230 in SImode and DImode */
1233 in SImode, DImode and TImode */
1235 in SImode, DImode and TImode */
1240 /* New AMD processors never drop prefetches; if they cannot be performed
1241 immediately, they are queued. We set number of simultaneous prefetches
1242 to a large constant to reflect this (it probably is not a good idea not
1243 to limit number of prefetches at all, as their execution also takes some
1244 time). */
1254 bdver4_memcpy,
1255 bdver4_memset,
1267 };
1269 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1270 very small blocks it is better to use loop. For large blocks, libcall can
1271 do nontemporary accesses and beat inline considerably. */
1304 in QImode, HImode and SImode.
1305 Relative to reg-reg move (2). */
1309 in SFmode, DFmode and XFmode */
1311 in SFmode, DFmode and XFmode */
1314 in SImode and DImode */
1316 in SImode and DImode */
1319 in SImode, DImode and TImode */
1321 in SImode, DImode and TImode */
1323 /* On K8:
1324 MOVD reg64, xmmreg Double FSTORE 4
1325 MOVD reg32, xmmreg Double FSTORE 4
1326 On AMDFAM10:
1327 MOVD reg64, xmmreg Double FADD 3
1328 1/1 1/1
1329 MOVD reg32, xmmreg Double FADD 3
1330 1/1 1/1 */
1343 btver1_memcpy,
1344 btver1_memset,
1356 };
1390 in QImode, HImode and SImode.
1391 Relative to reg-reg move (2). */
1395 in SFmode, DFmode and XFmode */
1397 in SFmode, DFmode and XFmode */
1400 in SImode and DImode */
1402 in SImode and DImode */
1405 in SImode, DImode and TImode */
1407 in SImode, DImode and TImode */
1409 /* On K8:
1410 MOVD reg64, xmmreg Double FSTORE 4
1411 MOVD reg32, xmmreg Double FSTORE 4
1412 On AMDFAM10:
1413 MOVD reg64, xmmreg Double FADD 3
1414 1/1 1/1
1415 MOVD reg32, xmmreg Double FADD 3
1416 1/1 1/1 */
1428 btver2_memcpy,
1429 btver2_memset,
1441 };
1445 DUMMY_STRINGOP_ALGS};
1449 DUMMY_STRINGOP_ALGS};
1451 static const
1474 in QImode, HImode and SImode.
1475 Relative to reg-reg move (2). */
1479 in SFmode, DFmode and XFmode */
1481 in SFmode, DFmode and XFmode */
1484 in SImode and DImode */
1486 in SImode and DImode */
1489 in SImode, DImode and TImode */
1491 in SImode, DImode and TImode */
1504 pentium4_memcpy,
1505 pentium4_memset,
1517 };
1530 static const
1553 in QImode, HImode and SImode.
1554 Relative to reg-reg move (2). */
1558 in SFmode, DFmode and XFmode */
1560 in SFmode, DFmode and XFmode */
1563 in SImode and DImode */
1565 in SImode and DImode */
1568 in SImode, DImode and TImode */
1570 in SImode, DImode and TImode */
1583 nocona_memcpy,
1584 nocona_memset,
1596 };
1607 static const
1630 in QImode, HImode and SImode.
1631 Relative to reg-reg move (2). */
1635 in SFmode, DFmode and XFmode */
1637 in SFmode, DFmode and XFmode */
1640 in SImode and DImode */
1642 in SImode and DImode */
1645 in SImode, DImode and TImode */
1647 in SImode, DImode and TImode */
1660 atom_memcpy,
1661 atom_memset,
1673 };
1684 static const
1707 in QImode, HImode and SImode.
1708 Relative to reg-reg move (2). */
1712 in SFmode, DFmode and XFmode */
1714 in SFmode, DFmode and XFmode */
1717 in SImode and DImode */
1719 in SImode and DImode */
1722 in SImode, DImode and TImode */
1724 in SImode, DImode and TImode */
1737 slm_memcpy,
1738 slm_memset,
1750 };
1761 static const
1784 in QImode, HImode and SImode.
1785 Relative to reg-reg move (2). */
1789 in SFmode, DFmode and XFmode */
1791 in SFmode, DFmode and XFmode */
1794 in SImode and DImode */
1796 in SImode and DImode */
1799 in SImode, DImode and TImode */
1801 in SImode, DImode and TImode */
1814 intel_memcpy,
1815 intel_memset,
1827 };
1829 /* Generic should produce code tuned for Core-i7 (and newer chips)
1830 and btver1 (and newer chips). */
1842 static const
1845 /* On all chips taken into consideration lea is 2 cycles and more. With
1846 this cost however our current implementation of synth_mult results in
1847 use of unnecessary temporary registers causing regression on several
1848 SPECfp benchmarks. */
1869 in QImode, HImode and SImode.
1870 Relative to reg-reg move (2). */
1874 in SFmode, DFmode and XFmode */
1876 in SFmode, DFmode and XFmode */
1879 in SImode and DImode */
1881 in SImode and DImode */
1884 in SImode, DImode and TImode */
1886 in SImode, DImode and TImode */
1892 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1893 value is increased to perhaps more appropriate value of 5. */
1901 generic_memcpy,
1902 generic_memset,
1914 };
1916 /* core_cost should produce code tuned for Core familly of CPUs. */
1929 static const
1932 /* On all chips taken into consideration lea is 2 cycles and more. With
1933 this cost however our current implementation of synth_mult results in
1934 use of unnecessary temporary registers causing regression on several
1935 SPECfp benchmarks. */
1956 in QImode, HImode and SImode.
1957 Relative to reg-reg move (2). */
1961 in SFmode, DFmode and XFmode */
1963 in SFmode, DFmode and XFmode */
1966 in SImode and DImode */
1968 in SImode and DImode */
1971 in SImode, DImode and TImode */
1973 in SImode, DImode and TImode */
1979 /* FIXME perhaps more appropriate value is 5. */
1987 core_memcpy,
1988 core_memset,
2000 };
2003 /* Set by -mtune. */
2006 /* Set by -mtune or -Os. */
2009 /* Processor feature/optimization bitmasks. */
2010 #define m_386 (1<<PROCESSOR_I386)
2011 #define m_486 (1<<PROCESSOR_I486)
2012 #define m_PENT (1<<PROCESSOR_PENTIUM)
2013 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2014 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2015 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2016 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2017 #define m_CORE2 (1<<PROCESSOR_CORE2)
2018 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2019 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2020 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2021 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2022 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2023 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2024 #define m_INTEL (1<<PROCESSOR_INTEL)
2026 #define m_GEODE (1<<PROCESSOR_GEODE)
2027 #define m_K6 (1<<PROCESSOR_K6)
2028 #define m_K6_GEODE (m_K6 | m_GEODE)
2029 #define m_K8 (1<<PROCESSOR_K8)
2030 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2031 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2032 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2033 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2034 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2035 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2036 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2037 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2038 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2039 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2040 #define m_BTVER (m_BTVER1 | m_BTVER2)
2041 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2043 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2046 #undef DEF_TUNE
2047 #define DEF_TUNE(tune, name, selector) name,
2049 #undef DEF_TUNE
2050 };
2052 /* Feature tests against the various tunings. */
2055 /* Feature tests against the various tunings used to create ix86_tune_features
2056 based on the processor mask. */
2058 #undef DEF_TUNE
2059 #define DEF_TUNE(tune, name, selector) selector,
2061 #undef DEF_TUNE
2062 };
2064 /* Feature tests against the various architecture variations. */
2067 /* Feature tests against the various architecture variations, used to create
2068 ix86_arch_features based on the processor mask. */
2070 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2073 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2076 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2079 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2082 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2084 };
2086 /* In case the average insn count for single function invocation is
2087 lower than this constant, emit fast (but longer) prologue and
2088 epilogue code. */
2089 #define FAST_PROLOGUE_INSN_COUNT 20
2091 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2096 /* Array of the smallest class containing reg number REGNO, indexed by
2097 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2100 {
2101 /* ax, dx, cx, bx */
2103 /* si, di, bp, sp */
2105 /* FP registers */
2108 /* arg pointer */
2109 NON_Q_REGS,
2110 /* flags, fpsr, fpcr, frame */
2112 /* SSE registers */
2115 /* MMX registers */
2118 /* REX registers */
2121 /* SSE REX registers */
2124 /* AVX-512 SSE registers */
2129 /* Mask registers. */
2132 };
2134 /* The "default" register map used in 32bit mode. */
2137 {
2148 };
2150 /* The "default" register map used in 64bit mode. */
2153 {
2164 };
2166 /* Define the register numbers to be used in Dwarf debugging information.
2167 The SVR4 reference port C compiler uses the following register numbers
2168 in its Dwarf output code:
2169 0 for %eax (gcc regno = 0)
2170 1 for %ecx (gcc regno = 2)
2171 2 for %edx (gcc regno = 1)
2172 3 for %ebx (gcc regno = 3)
2173 4 for %esp (gcc regno = 7)
2174 5 for %ebp (gcc regno = 6)
2175 6 for %esi (gcc regno = 4)
2176 7 for %edi (gcc regno = 5)
2177 The following three DWARF register numbers are never generated by
2178 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2179 believes these numbers have these meanings.
2180 8 for %eip (no gcc equivalent)
2181 9 for %eflags (gcc regno = 17)
2182 10 for %trapno (no gcc equivalent)
2183 It is not at all clear how we should number the FP stack registers
2184 for the x86 architecture. If the version of SDB on x86/svr4 were
2185 a bit less brain dead with respect to floating-point then we would
2186 have a precedent to follow with respect to DWARF register numbers
2187 for x86 FP registers, but the SDB on x86/svr4 is so completely
2188 broken with respect to FP registers that it is hardly worth thinking
2189 of it as something to strive for compatibility with.
2190 The version of x86/svr4 SDB I have at the moment does (partially)
2191 seem to believe that DWARF register number 11 is associated with
2192 the x86 register %st(0), but that's about all. Higher DWARF
2193 register numbers don't seem to be associated with anything in
2194 particular, and even for DWARF regno 11, SDB only seems to under-
2195 stand that it should say that a variable lives in %st(0) (when
2196 asked via an `=' command) if we said it was in DWARF regno 11,
2197 but SDB still prints garbage when asked for the value of the
2198 variable in question (via a `/' command).
2199 (Also note that the labels SDB prints for various FP stack regs
2200 when doing an `x' command are all wrong.)
2201 Note that these problems generally don't affect the native SVR4
2202 C compiler because it doesn't allow the use of -O with -g and
2203 because when it is *not* optimizing, it allocates a memory
2204 location for each floating-point variable, and the memory
2205 location is what gets described in the DWARF AT_location
2206 attribute for the variable in question.
2207 Regardless of the severe mental illness of the x86/svr4 SDB, we
2208 do something sensible here and we use the following DWARF
2209 register numbers. Note that these are all stack-top-relative
2210 numbers.
2211 11 for %st(0) (gcc regno = 8)
2212 12 for %st(1) (gcc regno = 9)
2213 13 for %st(2) (gcc regno = 10)
2214 14 for %st(3) (gcc regno = 11)
2215 15 for %st(4) (gcc regno = 12)
2216 16 for %st(5) (gcc regno = 13)
2217 17 for %st(6) (gcc regno = 14)
2218 18 for %st(7) (gcc regno = 15)
2219 */
2221 {
2232 };
2234 /* Define parameter passing and return registers. */
2237 {
2239 };
2242 {
2244 };
2247 {
2249 };
2251 /* Additional registers that are clobbered by SYSV calls. */
2254 {
2259 };
2261 /* Define the structure for the machine field in struct function. */
2266 rtx rtl;
2268 };
2270 /* Structure describing stack frame layout.
2271 Stack grows downward:
2273 [arguments]
2274 <- ARG_POINTER
2275 saved pc
2277 saved static chain if ix86_static_chain_on_stack
2279 saved frame pointer if frame_pointer_needed
2280 <- HARD_FRAME_POINTER
2281 [saved regs]
2282 <- regs_save_offset
2283 [padding0]
2285 [saved SSE regs]
2286 <- sse_regs_save_offset
2287 [padding1] |
2288 | <- FRAME_POINTER
2289 [va_arg registers] |
2290 |
2291 [frame] |
2292 |
2293 [padding2] | = to_allocate
2294 <- STACK_POINTER
2295 */
2296 struct ix86_frame
2297 {
2304 /* The offsets relative to ARG_POINTER. */
2305 HOST_WIDE_INT frame_pointer_offset;
2306 HOST_WIDE_INT hard_frame_pointer_offset;
2307 HOST_WIDE_INT stack_pointer_offset;
2308 HOST_WIDE_INT hfp_save_offset;
2309 HOST_WIDE_INT reg_save_offset;
2310 HOST_WIDE_INT sse_reg_save_offset;
2312 /* When save_regs_using_mov is set, emit prologue using
2313 move instead of push instructions. */
2315 };
2317 /* Which cpu are we scheduling for. */
2320 /* Which cpu are we optimizing for. */
2323 /* Which instruction set architecture to use. */
2326 /* True if processor has SSE prefetch instruction. */
2329 /* -mstackrealign option */
2346 /* Preferred alignment for stack boundary in bits. */
2349 /* Alignment for incoming stack boundary in bits specified at
2350 command line. */
2353 /* Default alignment for incoming stack boundary in bits. */
2356 /* Alignment for incoming stack boundary in bits. */
2359 /* Calling abi specific va_list type nodes. */
2363 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2367 /* Fence to use after loop using movnt. */
2368 tree x86_mfence;
2370 /* Register class used for passing given 64bit part of the argument.
2371 These represent classes as documented by the PS ABI, with the exception
2372 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2373 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2375 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2376 whenever possible (upper half does contain padding). */
2377 enum x86_64_reg_class
2378 {
2379 X86_64_NO_CLASS,
2380 X86_64_INTEGER_CLASS,
2381 X86_64_INTEGERSI_CLASS,
2382 X86_64_SSE_CLASS,
2383 X86_64_SSESF_CLASS,
2384 X86_64_SSEDF_CLASS,
2385 X86_64_SSEUP_CLASS,
2386 X86_64_X87_CLASS,
2387 X86_64_X87UP_CLASS,
2388 X86_64_COMPLEX_X87_CLASS,
2389 X86_64_MEMORY_CLASS
2390 };
2392 #define MAX_CLASSES 8
2394 /* Table of constants used by fldpi, fldln2, etc.... */
2398 \f
2403 const_tree);
2415 enum ix86_function_specific_strings
2416 {
2417 IX86_FUNCTION_SPECIFIC_ARCH,
2418 IX86_FUNCTION_SPECIFIC_TUNE,
2419 IX86_FUNCTION_SPECIFIC_MAX
2420 };
2441 \f
2442 #ifndef SUBTARGET32_DEFAULT_CPU
2444 #endif
2446 /* Whether -mtune= or -march= were specified */
2450 /* Vectorization library interface and handlers. */
2456 /* Processor target table, indexed by processor number */
2457 struct ptt
2458 {
2466 };
2468 /* This table must be in sync with enum processor_type in i386.h. */
2470 {
2496 };
2497 \f
2498 static bool
2500 {
2502 }
2504 static unsigned int
2506 {
2509 /* vzeroupper instructions are inserted immediately after reload to
2510 account for possible spills from 256bit registers. The pass
2511 reuses mode switching infrastructure by re-running mode insertion
2512 pass, so disable entities that have already been processed. */
2518 /* Call optimize_mode_switching. */
2521 }
2526 {
2538 };
2541 {
2545 {}
2547 /* opt_pass methods: */
2555 rtl_opt_pass *
2557 {
2559 }
2561 /* Return true if a red-zone is in use. */
2565 {
2567 }
2568 \f
2569 /* Return a string that documents the current -m options. The caller is
2570 responsible for freeing the string. */
2576 {
2577 struct ix86_target_opts
2578 {
2581 };
2583 /* This table is ordered so that options like -msse4.2 that imply
2584 preceding options while match those first. */
2586 {
2628 };
2630 /* Flag options. */
2632 {
2661 };
2678 /* Add -march= option. */
2680 {
2683 }
2685 /* Add -mtune= option. */
2687 {
2690 }
2692 /* Add -m32/-m64/-mx32. */
2694 {
2697 else
2699 isa &= ~ (OPTION_MASK_ISA_64BIT
2700 | OPTION_MASK_ABI_64
2702 }
2703 else
2707 /* Pick out the options in isa options. */
2709 {
2711 {
2714 }
2715 }
2718 {
2721 isa);
2722 }
2724 /* Add flag options. */
2726 {
2728 {
2731 }
2732 }
2735 {
2738 }
2740 /* Add -fpmath= option. */
2742 {
2745 {
2760 }
2761 }
2763 /* Any options? */
2769 /* Size the string. */
2773 {
2778 }
2780 /* Build the string. */
2785 {
2792 {
2794 line_len++;
2797 {
2801 }
2802 }
2806 {
2810 }
2811 }
2817 }
2819 /* Return true, if profiling code should be emitted before
2820 prologue. Otherwise it returns false.
2821 Note: For x86 with "hotfix" it is sorried. */
2822 static bool
2824 {
2826 }
2828 /* Function that is callable from the debugger to print the current
2829 options. */
2830 void ATTRIBUTE_UNUSED
2832 {
2838 {
2841 }
2842 else
2846 }
2849 #define DEF_ENUM
2850 #define DEF_ALG(alg, name) #name,
2852 #undef DEF_ENUM
2853 #undef DEF_ALG
2854 };
2856 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2857 The string is of the following form (or comma separated list of it):
2859 strategy_alg:max_size:[align|noalign]
2861 where the full size range for the strategy is either [0, max_size] or
2862 [min_size, max_size], in which min_size is the max_size + 1 of the
2863 preceding range. The last size range must have max_size == -1.
2865 Examples:
2867 1.
2868 -mmemcpy-strategy=libcall:-1:noalign
2870 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2873 2.
2874 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2876 This is to tell the compiler to use the following strategy for memset
2877 1) when the expected size is between [1, 16], use rep_8byte strategy;
2878 2) when the size is between [17, 2048], use vector_loop;
2879 3) when the size is > 2048, use libcall. */
2881 struct stringop_size_range
2882 {
2884 stringop_alg alg;
2886 };
2888 static void
2890 {
2898 else
2903 do
2904 {
2914 {
2918 }
2921 {
2925 }
2932 {
2934 alg_name,
2937 }
2945 else
2946 {
2950 }
2951 n++;
2953 }
2957 {
2962 }
2965 {
2969 }
2971 /* Now override the default algs array. */
2973 {
2979 }
2980 }
2982 \f
2983 /* parse -mtune-ctrl= option. When DUMP is true,
2984 print the features that are explicitly set. */
2986 static void
2988 {
2996 do
2997 {
3004 {
3005 curr_feature_string++;
3007 }
3009 {
3011 {
3017 }
3018 }
3023 }
3026 }
3028 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3029 processor type. */
3031 static void
3033 {
3038 {
3041 else
3043 }
3046 {
3051 }
3054 }
3057 /* Override various settings based on options. If MAIN_ARGS_P, the
3058 options are from the command line, otherwise they are from
3059 attributes. */
3061 static void
3065 {
3073 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3074 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3075 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3076 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3077 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3078 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3079 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3080 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3081 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3082 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3083 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3084 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3085 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3086 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3087 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3088 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3089 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3090 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3091 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3092 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3093 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3094 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3095 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3096 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3097 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3098 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3099 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3100 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3101 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3102 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3103 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3104 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3105 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3106 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3107 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3108 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3109 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3110 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3111 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3112 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3113 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3114 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3115 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3116 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3117 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3118 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3120 #define PTA_CORE2 \
3121 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3122 | PTA_CX16 | PTA_FXSR)
3123 #define PTA_NEHALEM \
3124 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3125 #define PTA_WESTMERE \
3126 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3127 #define PTA_SANDYBRIDGE \
3128 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3129 #define PTA_IVYBRIDGE \
3130 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3131 #define PTA_HASWELL \
3132 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3133 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3134 #define PTA_BROADWELL \
3135 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3136 #define PTA_BONNELL \
3137 (PTA_CORE2 | PTA_MOVBE)
3138 #define PTA_SILVERMONT \
3139 (PTA_WESTMERE | PTA_MOVBE)
3141 /* if this reaches 64, need to widen struct pta flags below */
3143 static struct pta
3144 {
3149 }
3151 {
3185 PTA_SANDYBRIDGE},
3187 PTA_SANDYBRIDGE},
3189 PTA_IVYBRIDGE},
3191 PTA_IVYBRIDGE},
3282 PTA_64BIT
3284 };
3286 /* -mrecip options. */
3287 static struct
3288 {
3291 }
3293 {
3300 };
3304 /* Set up prefix/suffix so the error messages refer to either the command
3305 line argument, or the attribute(target). */
3307 {
3311 }
3312 else
3313 {
3317 }
3319 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3320 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3323 #ifdef TARGET_BI_ARCH
3324 else
3325 {
3326 #if TARGET_BI_ARCH == 1
3327 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3328 is on and OPTION_MASK_ABI_X32 is off. We turn off
3329 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3330 -mx32. */
3333 #else
3334 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3335 on and OPTION_MASK_ABI_64 is off. We turn off
3336 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3337 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3341 #endif
3342 }
3343 #endif
3346 {
3347 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3348 OPTION_MASK_ABI_64 for TARGET_X32. */
3351 }
3354 | OPTION_MASK_ABI_X32
3357 {
3358 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3359 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3362 }
3364 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3365 SUBTARGET_OVERRIDE_OPTIONS;
3366 #endif
3368 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3369 SUBSUBTARGET_OVERRIDE_OPTIONS;
3370 #endif
3372 /* -fPIC is the default for x86_64. */
3376 /* Need to check -mtune=generic first. */
3378 {
3379 /* As special support for cross compilers we read -mtune=native
3380 as -mtune=generic. With native compilers we won't see the
3381 -mtune=native, as it was changed by the driver. */
3383 {
3385 }
3390 }
3391 else
3392 {
3396 {
3397 opts->x_ix86_tune_string
3400 }
3402 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3403 or defaulted. We need to use a sensible tune option. */
3405 {
3407 }
3408 }
3412 {
3413 /* rep; movq isn't available in 32-bit code. */
3416 }
3419 opts->x_ix86_arch_string
3422 else
3426 {
3434 }
3435 else
3442 /* For targets using ms ABI enable ms-extensions, if not
3443 explicit turned off. For non-ms ABI we turn off this
3444 option. */
3449 {
3451 {
3495 {
3498 }
3506 }
3507 }
3508 else
3509 {
3510 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3511 use of rip-relative addressing. This eliminates fixups that
3512 would otherwise be needed if this object is to be placed in a
3513 DLL, and is essentially just as efficient as direct addressing. */
3519 else
3521 }
3523 {
3526 }
3534 {
3537 /* Default cpu tuning to the architecture. */
3682 }
3700 {
3704 {
3706 {
3708 {
3716 }
3717 else
3720 }
3721 }
3722 /* Intel CPUs have always interpreted SSE prefetch instructions as
3723 NOPs; so, we can enable SSE prefetch instructions even when
3724 -mtune (rather than -march) points us to a processor that has them.
3725 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3726 higher processors. */
3731 }
3739 #ifndef USE_IX86_FRAME_POINTER
3740 #define USE_IX86_FRAME_POINTER 0
3741 #endif
3743 #ifndef USE_X86_64_FRAME_POINTER
3744 #define USE_X86_64_FRAME_POINTER 0
3745 #endif
3747 /* Set the default values for switches whose default depends on TARGET_64BIT
3748 in case they weren't overwritten by command line options. */
3750 {
3758 opts->x_flag_unwind_tables
3762 }
3763 else
3764 {
3766 opts->x_flag_omit_frame_pointer
3772 }
3777 else
3780 /* Arrange to set up i386_stack_locals for all functions. */
3783 /* Validate -mregparm= value. */
3785 {
3789 {
3793 }
3794 }
3798 /* Default align_* from the processor table. */
3800 {
3803 }
3805 {
3808 }
3810 {
3812 }
3814 /* Provide default for -mbranch-cost= value. */
3819 {
3820 opts->x_target_flags
3823 /* Enable by default the SSE and MMX builtins. Do allow the user to
3824 explicitly disable any of these. In particular, disabling SSE and
3825 MMX for kernel code is extremely useful. */
3827 opts->x_ix86_isa_flags
3834 }
3835 else
3836 {
3837 opts->x_target_flags
3841 opts->x_ix86_isa_flags
3844 /* i386 ABI does not specify red zone. It still makes sense to use it
3845 when programmer takes care to stack from being destroyed. */
3848 }
3853 /* -fshrink-wrap-frame-pointer is an optimization based on
3854 -fno-omit-frame-pointer mode, so it is only effective when
3855 flag_omit_frame_pointer is false.
3856 Frame pointer shrinkwrap may increase code size, so disable
3857 it when optimize_size is true. */
3863 /* If only no -mno-omit-leaf-frame-pointer is explicitly specified,
3864 -fshrink_wrap_frame_pointer will enable omitting leaf frame
3865 pointer by default. */
3871 /* Keep nonleaf frame pointers. */
3875 /* If we're doing fast math, we don't care about comparison order
3876 wrt NaNs. This lets us use a shorter comparison sequence. */
3880 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3881 since the insns won't need emulation. */
3885 /* Likewise, if the target doesn't have a 387, or we've specified
3886 software floating point, don't use 387 inline intrinsics. */
3890 /* Turn on MMX builtins for -msse. */
3892 opts->x_ix86_isa_flags
3895 /* Enable SSE prefetch. */
3900 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3903 opts->x_ix86_isa_flags
3906 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3909 opts->x_ix86_isa_flags
3912 /* Enable lzcnt instruction for -mabm. */
3914 opts->x_ix86_isa_flags
3917 /* Validate -mpreferred-stack-boundary= value or default it to
3918 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3921 {
3928 {
3932 else
3935 }
3936 else
3937 ix86_preferred_stack_boundary
3939 }
3941 /* Set the default value for -mstackrealign. */
3947 /* Validate -mincoming-stack-boundary= value or default it to
3948 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3951 {
3958 else
3959 {
3960 ix86_user_incoming_stack_boundary
3962 ix86_incoming_stack_boundary
3964 }
3965 }
3967 /* Accept -msseregparm only if at least SSE support is enabled. */
3973 {
3975 {
3977 {
3980 }
3983 {
3986 }
3987 }
3988 }
3989 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3990 fpmath=387. The second is however default at many targets since the
3991 extra 80bit precision of temporaries is considered to be part of ABI.
3992 Overwrite the default at least for -ffast-math.
3993 TODO: -mfpmath=both seems to produce same performing code with bit
3994 smaller binaries. It is however not clear if register allocation is
3995 ready for this setting.
3996 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3997 codegen. We may switch to 387 with -ffast-math for size optimized
3998 functions. */
4002 else
4005 /* If the i387 is disabled, then do not return values in it. */
4009 /* Use external vectorized library in vectorizing intrinsics. */
4012 {
4023 }
4030 /* If stack probes are required, the space used for large function
4031 arguments on the stack must also be probed, so enable
4032 -maccumulate-outgoing-args so this happens in the prologue. */
4035 {
4040 }
4042 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4043 {
4049 }
4051 /* When scheduling description is not available, disable scheduler pass
4052 so it won't slow down the compilation and make x87 code slower. */
4073 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4075 && HAVE_prefetch
4080 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4081 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4086 {
4089 {
4091 ix86_gen_tls_local_dynamic_base_64
4093 }
4094 else
4095 {
4097 ix86_gen_tls_local_dynamic_base_64
4099 }
4100 }
4101 else
4105 {
4115 }
4116 else
4117 {
4127 }
4129 #ifdef USE_IX86_CLD
4130 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4133 #endif
4136 {
4141 }
4143 {
4147 }
4149 {
4150 #if defined(PROFILE_BEFORE_PROLOGUE)
4152 #else
4154 #endif
4155 }
4157 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4158 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4159 AVX unaligned load/store. */
4161 {
4171 /* Enable 128-bit AVX instruction generation
4172 for the auto-vectorizer. */
4176 }
4179 {
4186 {
4189 {
4191 q++;
4192 }
4193 else
4198 else
4199 {
4202 {
4205 }
4208 {
4212 }
4213 }
4218 else
4220 }
4221 }
4228 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4229 for 64-bit Bionic. */
4234 ? MASK_LONG_DOUBLE_128
4237 /* Only one of them can be active. */
4241 /* Save the initial options in case the user does function specific
4242 options. */
4244 target_option_default_node = target_option_current_node
4247 /* Handle stack protector */
4249 opts->x_ix86_stack_protector_guard
4252 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4254 {
4258 }
4261 {
4265 }
4266 }
4268 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4270 static void
4272 {
4274 static struct register_pass_info insert_vzeroupper_info
4277 };
4282 /* This needs to be done at start up. It's convenient to do it here. */
4284 }
4286 /* Update register usage after having seen the compiler flags. */
4288 static void
4290 {
4294 /* The PIC register, if it exists, is fixed. */
4299 /* For 32-bit targets, squash the REX registers. */
4301 {
4308 }
4310 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4318 {
4319 /* Set/reset conditionally defined registers from
4320 CALL_USED_REGISTERS initializer. */
4324 /* Calculate registers of CLOBBERED_REGS register set
4325 as call used registers from GENERAL_REGS register set. */
4329 }
4331 /* If MMX is disabled, squash the registers. */
4337 /* If SSE is disabled, squash the registers. */
4343 /* If the FPU is disabled, squash the registers. */
4349 /* If AVX512F is disabled, squash the registers. */
4351 {
4357 }
4358 }
4360 \f
4361 /* Save the current options */
4363 static void
4366 {
4401 /* The fields are char but the variables are not; make sure the
4402 values fit in the fields. */
4407 }
4409 /* Restore the current options */
4411 static void
4414 {
4420 /* We don't change -fPIC. */
4457 /* Recreate the arch feature tests if the arch changed */
4459 {
4464 }
4466 /* Recreate the tune optimization tests */
4469 }
4471 /* Print the current options */
4473 static void
4476 {
4494 {
4497 }
4498 }
4500 \f
4501 /* Inner function to process the attribute((target(...))), take an argument and
4502 set the current options from the argument. If we have a list, recursively go
4503 over the list. */
4505 static bool
4510 {
4514 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4515 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4516 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4517 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4518 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4520 enum ix86_opt_type
4521 {
4522 ix86_opt_unknown,
4523 ix86_opt_yes,
4524 ix86_opt_no,
4525 ix86_opt_str,
4526 ix86_opt_enum,
4527 ix86_opt_isa
4528 };
4530 static const struct
4531 {
4538 /* isa options */
4581 /* enum options */
4584 /* string options */
4588 /* flag options */
4590 OPT_mcld,
4591 MASK_CLD),
4594 OPT_mfancy_math_387,
4595 MASK_NO_FANCY_MATH_387),
4598 OPT_mieee_fp,
4599 MASK_IEEE_FP),
4602 OPT_minline_all_stringops,
4603 MASK_INLINE_ALL_STRINGOPS),
4606 OPT_minline_stringops_dynamically,
4607 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4610 OPT_mno_align_stringops,
4611 MASK_NO_ALIGN_STRINGOPS),
4614 OPT_mrecip,
4615 MASK_RECIP),
4617 };
4619 /* If this is a list, recurse to get the options. */
4621 {
4628 enum_opts_set))
4632 }
4635 {
4638 }
4640 /* Handle multiple arguments separated by commas. */
4644 {
4658 {
4662 }
4663 else
4664 {
4667 }
4669 /* Recognize no-xxx. */
4671 {
4675 }
4676 else
4679 /* Find the option. */
4683 {
4691 {
4696 }
4697 }
4699 /* Process the option. */
4701 {
4704 }
4707 {
4713 }
4716 {
4722 else
4724 }
4727 {
4729 {
4732 }
4733 else
4735 }
4738 {
4746 global_dc);
4747 else
4748 {
4751 }
4752 }
4754 else
4756 }
4759 }
4761 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4763 tree
4767 {
4782 /* Process each of the options on the chain. */
4787 /* If the changed options are different from the default, rerun
4788 ix86_option_override_internal, and then save the options away.
4789 The string options are are attribute options, and will be undone
4790 when we copy the save structure. */
4796 {
4797 /* If we are using the default tune= or arch=, undo the string assigned,
4798 and use the default. */
4809 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4814 {
4817 }
4819 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4822 /* Add any builtin functions with the new isa if any. */
4825 /* Save the current options unless we are validating options for
4826 #pragma. */
4833 /* Free up memory allocated to hold the strings */
4836 }
4839 }
4841 /* Hook to validate attribute((target("string"))). */
4843 static bool
4846 tree args,
4848 {
4853 /* attribute((target("default"))) does nothing, beyond
4854 affecting multi-versioning. */
4863 /* Get the optimization options of the current function. */
4869 /* Init func_options. */
4877 /* Initialize func_options to the default before its target options can
4878 be set. */
4891 {
4896 }
4899 }
4901 \f
4902 /* Hook to determine if one function can safely inline another. */
4904 static bool
4906 {
4911 /* If callee has no option attributes, then it is ok to inline. */
4915 /* If caller has no option attributes, but callee does then it is not ok to
4916 inline. */
4920 else
4921 {
4925 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4926 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4927 function. */
4932 /* See if we have the same non-isa options. */
4936 /* See if arch, tune, etc. are the same. */
4949 else
4951 }
4954 }
4956 \f
4957 /* Remember the last target of ix86_set_current_function. */
4960 /* Invalidate ix86_previous_fndecl cache. */
4961 void
4963 {
4965 }
4967 /* Establish appropriate back-end context for processing the function
4968 FNDECL. The argument might be NULL to indicate processing at top
4969 level, outside of any function scope. */
4970 static void
4972 {
4973 /* Only change the context if the function changes. This hook is called
4974 several times in the course of compiling a function, and we don't want to
4975 slow things down too much or call target_reinit when it isn't safe. */
4977 {
4978 tree old_tree = (ix86_previous_fndecl
4982 tree new_tree = (fndecl
4988 ;
4991 {
4996 else
4999 }
5002 {
5010 else
5013 }
5014 }
5015 }
5017 \f
5018 /* Return true if this goes in large data/bss. */
5020 static bool
5022 {
5026 /* Functions are never large data. */
5030 /* Automatic variables are never large data. */
5035 {
5041 }
5042 else
5043 {
5046 /* If this is an incomplete type with size 0, then we can't put it
5047 in data because it might be too big when completed. Also,
5048 int_size_in_bytes returns -1 if size can vary or is larger than
5049 an integer in which case also it is safer to assume that it goes in
5050 large data. */
5053 }
5056 }
5058 /* Switch to the appropriate section for output of DECL.
5059 DECL is either a `VAR_DECL' node or a constant of some sort.
5060 RELOC indicates whether forming the initial value of DECL requires
5061 link-time relocations. */
5066 {
5068 {
5072 {
5106 /* We don't split these for medium model. Place them into
5107 default sections and hope for best. */
5109 }
5111 {
5112 /* We might get called with string constants, but get_named_section
5113 doesn't like them as they are not DECLs. Also, we need to set
5114 flags in that case. */
5118 }
5119 }
5121 }
5123 /* Select a set of attributes for section NAME based on the properties
5124 of DECL and whether or not RELOC indicates that DECL's initializer
5125 might contain runtime relocations. */
5127 static unsigned int ATTRIBUTE_UNUSED
5129 {
5143 }
5145 /* Build up a unique section name, expressed as a
5146 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5147 RELOC indicates whether the initial value of EXP requires
5148 link-time relocations. */
5150 static void ATTRIBUTE_UNUSED
5152 {
5154 {
5156 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5160 {
5184 /* We don't split these for medium model. Place them into
5185 default sections and hope for best. */
5187 }
5189 {
5196 /* If we're using one_only, then there needs to be a .gnu.linkonce
5197 prefix to the section name. */
5204 }
5205 }
5207 }
5209 #ifdef COMMON_ASM_OP
5210 /* This says how to output assembler code to declare an
5211 uninitialized external linkage data object.
5213 For medium model x86-64 we need to use .largecomm opcode for
5214 large objects. */
5215 void
5219 {
5223 else
5228 }
5229 #endif
5231 /* Utility function for targets to use in implementing
5232 ASM_OUTPUT_ALIGNED_BSS. */
5234 void
5238 {
5242 else
5245 #ifdef ASM_DECLARE_OBJECT_NAME
5248 #else
5249 /* Standard thing is just output label for the object. */
5253 }
5254 \f
5255 /* Decide whether we must probe the stack before any space allocation
5256 on this target. It's essentially TARGET_STACK_PROBE except when
5257 -fstack-check causes the stack to be already probed differently. */
5259 bool
5261 {
5262 /* Do not probe the stack twice if static stack checking is enabled. */
5267 }
5268 \f
5269 /* Decide whether we can make a sibling call to a function. DECL is the
5270 declaration of the function being targeted by the call and EXP is the
5271 CALL_EXPR representing the call. */
5273 static bool
5275 {
5279 /* If we are generating position-independent code, we cannot sibcall
5280 optimize any indirect call, or a direct call to a global function,
5281 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5283 && !TARGET_64BIT
5284 && flag_pic
5288 /* If we need to align the outgoing stack, then sibcalling would
5289 unalign the stack, which may break the called function. */
5295 {
5298 }
5299 else
5300 {
5301 /* We're looking at the CALL_EXPR, we need the type of the function. */
5306 }
5308 /* Check that the return value locations are the same. Like
5309 if we are returning floats on the 80387 register stack, we cannot
5310 make a sibcall from a function that doesn't return a float to a
5311 function that does or, conversely, from a function that does return
5312 a float to a function that doesn't; the necessary stack adjustment
5313 would not be executed. This is also the place we notice
5314 differences in the return value ABI. Note that it is ok for one
5315 of the functions to have void return type as long as the return
5316 value of the other is passed in a register. */
5321 {
5324 }
5326 ;
5331 {
5332 /* The SYSV ABI has more call-clobbered registers;
5333 disallow sibcalls from MS to SYSV. */
5337 }
5338 else
5339 {
5340 /* If this call is indirect, we'll need to be able to use a
5341 call-clobbered register for the address of the target function.
5342 Make sure that all such registers are not used for passing
5343 parameters. Note that DLLIMPORT functions are indirect. */
5346 {
5348 {
5349 /* ??? Need to count the actual number of registers to be used,
5350 not the possible number of registers. Fix later. */
5352 }
5353 }
5354 }
5356 /* Otherwise okay. That also includes certain types of indirect calls. */
5358 }
5360 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5361 and "sseregparm" calling convention attributes;
5362 arguments as in struct attribute_spec.handler. */
5364 static tree
5366 tree args,
5369 {
5374 {
5376 name);
5379 }
5381 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5383 {
5384 tree cst;
5387 {
5389 }
5392 {
5394 }
5398 {
5401 name);
5403 }
5405 {
5409 }
5412 }
5415 {
5416 /* Do not warn when emulating the MS ABI. */
5421 name);
5424 }
5426 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5428 {
5430 {
5432 }
5434 {
5436 }
5438 {
5440 }
5442 {
5444 }
5445 }
5447 /* Can combine stdcall with fastcall (redundant), regparm and
5448 sseregparm. */
5450 {
5452 {
5454 }
5456 {
5458 }
5460 {
5462 }
5463 }
5465 /* Can combine cdecl with regparm and sseregparm. */
5467 {
5469 {
5471 }
5473 {
5475 }
5477 {
5479 }
5480 }
5482 {
5485 name);
5487 {
5489 }
5491 {
5493 }
5495 {
5497 }
5498 }
5500 /* Can combine sseregparm with all attributes. */
5503 }
5505 /* The transactional memory builtins are implicitly regparm or fastcall
5506 depending on the ABI. Override the generic do-nothing attribute that
5507 these builtins were declared with, and replace it with one of the two
5508 attributes that we expect elsewhere. */
5510 static tree
5512 tree args ATTRIBUTE_UNUSED,
5514 {
5515 tree alt;
5517 /* In no case do we want to add the placeholder attribute. */
5520 /* The 64-bit ABI is unchanged for transactional memory. */
5524 /* ??? Is there a better way to validate 32-bit windows? We have
5525 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5528 else
5529 {
5532 }
5536 }
5538 /* This function determines from TYPE the calling-convention. */
5540 unsigned int
5542 {
5545 tree attrs;
5552 {
5562 /* Regparam isn't allowed for thiscall and fastcall. */
5564 {
5569 }
5573 }
5580 || is_stdarg
5586 }
5588 /* Return 0 if the attributes for two types are incompatible, 1 if they
5589 are compatible, and 2 if they are nearly compatible (which causes a
5590 warning to be generated). */
5592 static int
5594 {
5610 }
5611 \f
5612 /* Return the regparm value for a function with the indicated TYPE and DECL.
5613 DECL may be NULL when calling function indirectly
5614 or considering a libcall. */
5616 static int
5618 {
5619 tree attr;
5630 {
5633 {
5636 }
5637 }
5643 /* Use register calling convention for local functions when possible. */
5646 /* Caller and callee must agree on the calling convention, so
5647 checking here just optimize means that with
5648 __attribute__((optimize (...))) caller could use regparm convention
5649 and callee not, or vice versa. Instead look at whether the callee
5650 is optimized or not. */
5653 {
5654 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5657 {
5660 /* Make sure no regparm register is taken by a
5661 fixed register variable. */
5666 /* We don't want to use regparm(3) for nested functions as
5667 these use a static chain pointer in the third argument. */
5671 /* In 32-bit mode save a register for the split stack. */
5675 /* Each fixed register usage increases register pressure,
5676 so less registers should be used for argument passing.
5677 This functionality can be overriden by an explicit
5678 regparm value. */
5681 globals++;
5683 local_regparm
5688 }
5689 }
5692 }
5694 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5695 DFmode (2) arguments in SSE registers for a function with the
5696 indicated TYPE and DECL. DECL may be NULL when calling function
5697 indirectly or considering a libcall. Otherwise return 0. */
5699 static int
5701 {
5704 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5705 by the sseregparm attribute. */
5708 {
5710 {
5712 {
5716 else
5719 }
5721 }
5724 }
5726 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5727 (and DFmode for SSE2) arguments in SSE registers. */
5730 {
5731 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5735 }
5738 }
5740 /* Return true if EAX is live at the start of the function. Used by
5741 ix86_expand_prologue to determine if we need special help before
5742 calling allocate_stack_worker. */
5744 static bool
5746 {
5747 /* Cheat. Don't bother working forward from ix86_function_regparm
5748 to the function type to whether an actual argument is located in
5749 eax. Instead just look at cfg info, which is still close enough
5750 to correct at this point. This gives false positives for broken
5751 functions that might use uninitialized data that happens to be
5752 allocated in eax, but who cares? */
5754 }
5756 static bool
5758 {
5759 tree attr;
5762 {
5768 /* For 32-bit MS-ABI the default is to keep aggregate
5769 return pointer. */
5772 }
5774 }
5776 /* Value is the number of bytes of arguments automatically
5777 popped when returning from a subroutine call.
5778 FUNDECL is the declaration node of the function (as a tree),
5779 FUNTYPE is the data type of the function (as a tree),
5780 or for a library call it is an identifier node for the subroutine name.
5781 SIZE is the number of bytes of arguments passed on the stack.
5783 On the 80386, the RTD insn may be used to pop them if the number
5784 of args is fixed, but if the number is variable then the caller
5785 must pop them all. RTD can't be used for library calls now
5786 because the library is compiled with the Unix compiler.
5787 Use of RTD is a selectable option, since it is incompatible with
5788 standard Unix calling sequences. If the option is not selected,
5789 the caller must always pop the args.
5791 The attribute stdcall is equivalent to RTD on a per module basis. */
5793 static int
5795 {
5798 /* None of the 64-bit ABIs pop arguments. */
5809 /* Lose any fake structure return argument if it is passed on the stack. */
5812 {
5816 }
5819 }
5821 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5823 static bool
5825 {
5826 /* Check operand constraints in case hard registers were propagated
5827 into insn pattern. This check prevents combine pass from
5828 generating insn patterns with invalid hard register operands.
5829 These invalid insns can eventually confuse reload to error out
5830 with a spill failure. See also PRs 46829 and 46843. */
5832 {
5839 {
5847 /* For pre-AVX disallow unaligned loads/stores where the
5848 instructions don't support it. */
5852 {
5856 }
5858 /* A unary operator may be accepted by the predicate, but it
5859 is irrelevant for matching constraints. */
5864 {
5872 }
5879 /* Operand has no constraints, anything is OK. */
5883 {
5886 && operands_match_p
5890 {
5893 }
5894 }
5898 }
5899 }
5902 }
5903 \f
5904 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5906 static unsigned HOST_WIDE_INT
5908 {
5912 }
5913 \f
5914 /* Argument support functions. */
5916 /* Return true when register may be used to pass function parameters. */
5917 bool
5919 {
5924 {
5928 else
5934 }
5940 /* TODO: The function should depend on current function ABI but
5941 builtins.c would need updating then. Therefore we use the
5942 default ABI. */
5944 /* RAX is used as hidden argument to va_arg functions. */
5950 else
5957 }
5959 /* Return if we do not know how to pass TYPE solely in registers. */
5961 static bool
5963 {
5967 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5968 The layout_type routine is crafty and tries to trick us into passing
5969 currently unsupported vector types on the stack by using TImode. */
5972 }
5974 /* It returns the size, in bytes, of the area reserved for arguments passed
5975 in registers for the function represented by fndecl dependent to the used
5976 abi format. */
5977 int
5979 {
5983 else
5988 }
5990 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5991 call abi used. */
5992 enum calling_abi
5994 {
5996 {
5999 {
6001 {
6003 {
6006 {
6009 }
6010 }
6012 }
6013 }
6017 }
6019 }
6021 /* We add this as a workaround in order to use libc_has_function
6022 hook in i386.md. */
6023 bool
6025 {
6027 }
6029 static bool
6031 {
6033 {
6037 else
6039 }
6041 }
6043 static enum calling_abi
6045 {
6049 }
6051 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6052 call abi used. */
6053 enum calling_abi
6055 {
6059 }
6061 /* Write the extra assembler code needed to declare a function properly. */
6063 void
6065 tree decl)
6066 {
6070 {
6076 }
6078 #ifdef SUBTARGET_ASM_UNWIND_INIT
6080 #endif
6084 /* Output magic byte marker, if hot-patch attribute is set. */
6086 {
6088 {
6089 /* leaq [%rsp + 0], %rsp */
6092 }
6093 else
6094 {
6095 /* movl.s %edi, %edi
6096 push %ebp
6097 movl.s %esp, %ebp */
6100 }
6101 }
6102 }
6104 /* regclass.c */
6107 /* Implementation of call abi switching target hook. Specific to FNDECL
6108 the specific call register sets are set. See also
6109 ix86_conditional_register_usage for more details. */
6110 void
6112 {
6115 else
6117 }
6119 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6120 expensive re-initialization of init_regs each time we switch function context
6121 since this is needed only during RTL expansion. */
6122 static void
6124 {
6128 }
6130 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6131 for a call to a function whose data type is FNTYPE.
6132 For a library call, FNTYPE is 0. */
6134 void
6138 tree fndecl,
6140 {
6146 {
6149 }
6150 else
6151 {
6154 }
6158 /* Set up the number of registers to use for passing arguments. */
6161 {
6163 ? X86_64_REGPARM_MAX
6165 }
6167 {
6170 {
6172 ? X86_64_SSE_REGPARM_MAX
6174 }
6175 }
6183 /* Because type might mismatch in between caller and callee, we need to
6184 use actual type of function for local calls.
6185 FIXME: cgraph_analyze can be told to actually record if function uses
6186 va_start so for local functions maybe_vaarg can be made aggressive
6187 helping K&R code.
6188 FIXME: once typesytem is fixed, we won't need this code anymore. */
6196 {
6197 /* If there are variable arguments, then we won't pass anything
6198 in registers in 32-bit mode. */
6200 {
6209 }
6211 /* Use ecx and edx registers if function has fastcall attribute,
6212 else look for regparm information. */
6214 {
6217 {
6220 }
6222 {
6225 }
6226 else
6228 }
6230 /* Set up the number of SSE registers used for passing SFmode
6231 and DFmode arguments. Warn for mismatching ABI. */
6233 }
6234 }
6236 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6237 But in the case of vector types, it is some vector mode.
6239 When we have only some of our vector isa extensions enabled, then there
6240 are some modes for which vector_mode_supported_p is false. For these
6241 modes, the generic vector support in gcc will choose some non-vector mode
6242 in order to implement the type. By computing the natural mode, we'll
6243 select the proper ABI location for the operand and not depend on whatever
6244 the middle-end decides to do with these vector types.
6246 The midde-end can't deal with the vector types > 16 bytes. In this
6247 case, we return the original mode and warn ABI change if CUM isn't
6248 NULL.
6250 If INT_RETURN is true, warn ABI change if the vector mode isn't
6251 available for function return value. */
6253 static enum machine_mode
6256 {
6260 {
6263 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6265 {
6270 else
6273 /* Get the mode which has this inner mode and number of units. */
6277 {
6279 {
6284 {
6288 }
6290 {
6294 }
6297 }
6299 {
6304 {
6308 }
6310 {
6314 }
6317 }
6320 {
6325 {
6329 }
6331 {
6335 }
6336 }
6338 {
6343 {
6347 }
6349 {
6353 }
6354 }
6356 }
6359 }
6360 }
6363 }
6365 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6366 this may not agree with the mode that the type system has chosen for the
6367 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6368 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6370 static rtx
6373 {
6374 rtx tmp;
6378 else
6379 {
6383 }
6386 }
6388 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6389 of this code is to classify each 8bytes of incoming argument by the register
6390 class and assign registers accordingly. */
6392 /* Return the union class of CLASS1 and CLASS2.
6393 See the x86-64 PS ABI for details. */
6395 static enum x86_64_reg_class
6397 {
6398 /* Rule #1: If both classes are equal, this is the resulting class. */
6402 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6403 the other class. */
6409 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6413 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6421 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6422 MEMORY is used. */
6431 /* Rule #6: Otherwise class SSE is used. */
6433 }
6435 /* Classify the argument of type TYPE and mode MODE.
6436 CLASSES will be filled by the register class used to pass each word
6437 of the operand. The number of words is returned. In case the parameter
6438 should be passed in memory, 0 is returned. As a special case for zero
6439 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6441 BIT_OFFSET is used internally for handling records and specifies offset
6442 of the offset in bits modulo 512 to avoid overflow cases.
6444 See the x86-64 PS ABI for details.
6445 */
6447 static int
6450 {
6451 HOST_WIDE_INT bytes =
6453 int words
6456 /* Variable sized entities are always passed/returned in memory. */
6465 {
6467 tree field;
6470 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6477 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6478 signalize memory class, so handle it as special case. */
6480 {
6483 }
6485 /* Classify each field of record and merge classes. */
6487 {
6489 /* And now merge the fields of structure. */
6491 {
6493 {
6499 /* Bitfields are always classified as integer. Handle them
6500 early, since later code would consider them to be
6501 misaligned integers. */
6503 {
6512 }
6513 else
6514 {
6519 /* Flexible array member is ignored. */
6526 {
6530 {
6533 "the ABI of passing struct with"
6534 " a flexible array member has"
6536 }
6538 }
6540 subclasses,
6550 }
6551 }
6552 }
6556 /* Arrays are handled as small records. */
6557 {
6564 /* The partial classes are now full classes. */
6575 }
6578 /* Unions are similar to RECORD_TYPE but offset is always 0.
6579 */
6581 {
6583 {
6591 bit_offset);
6596 }
6597 }
6602 }
6605 {
6606 /* When size > 16 bytes, if the first one isn't
6607 X86_64_SSE_CLASS or any other ones aren't
6608 X86_64_SSEUP_CLASS, everything should be passed in
6609 memory. */
6616 }
6618 /* Final merger cleanup. */
6620 {
6621 /* If one class is MEMORY, everything should be passed in
6622 memory. */
6626 /* The X86_64_SSEUP_CLASS should be always preceded by
6627 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6631 {
6632 /* The first one should never be X86_64_SSEUP_CLASS. */
6635 }
6637 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6638 everything should be passed in memory. */
6641 {
6644 /* The first one should never be X86_64_X87UP_CLASS. */
6647 {
6650 "the ABI of passing union with long double"
6652 }
6654 }
6655 }
6657 }
6659 /* Compute alignment needed. We align all types to natural boundaries with
6660 exception of XFmode that is aligned to 64bits. */
6662 {
6671 /* Misaligned fields are always returned in memory. */
6674 }
6676 /* for V1xx modes, just use the base mode */
6681 /* Classification of atomic types. */
6683 {
6699 {
6702 /* Analyze last 128 bits only. */
6706 {
6709 }
6711 {
6714 }
6716 {
6720 }
6722 {
6725 }
6726 else
6728 }
6735 /* OImode shouldn't be used directly. */
6742 else
6760 else
6761 {
6765 {
6768 "the ABI of passing structure with complex float"
6770 }
6773 }
6782 /* This modes is larger than 16 bytes. */
6840 else
6844 }
6845 }
6847 /* Examine the argument and return set number of register required in each
6848 class. Return 0 iff parameter should be passed in memory. */
6849 static int
6852 {
6862 {
6884 }
6886 }
6888 /* Construct container for the argument used by GCC interface. See
6889 FUNCTION_ARG for the detailed description. */
6891 static rtx
6895 {
6896 /* The following variables hold the static issued_error state. */
6910 rtx ret;
6921 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6922 some less clueful developer tries to use floating-point anyway. */
6924 {
6926 {
6928 {
6931 }
6932 }
6934 {
6937 }
6939 }
6941 /* Likewise, error if the ABI requires us to return values in the
6942 x87 registers and the user specified -mno-80387. */
6948 {
6950 {
6953 }
6955 }
6957 /* First construct simple cases. Avoid SCmode, since we want to use
6958 single register to pass this type. */
6961 {
6976 /* Zero sized array, struct or class. */
6980 }
7019 /* Otherwise figure out the entries of the PARALLEL. */
7021 {
7025 {
7030 /* Merge TImodes on aligned occasions here too. */
7032 tmpmode
7036 else
7038 /* We've requested 24 bytes we
7039 don't have mode for. Use DImode. */
7046 intreg++;
7054 sse_regno++;
7062 sse_regno++;
7067 {
7073 {
7075 i++;
7076 }
7077 else
7102 }
7108 sse_regno++;
7112 }
7113 }
7115 /* Empty aligned struct, union or class. */
7123 }
7125 /* Update the data in CUM to advance over an argument of mode MODE
7126 and data type TYPE. (TYPE is null for libcalls where that information
7127 may not be available.) */
7129 static void
7132 HOST_WIDE_INT words)
7133 {
7135 {
7142 /* FALLTHRU */
7153 {
7156 }
7160 /* OImode shouldn't be used directly. */
7169 /* FALLTHRU */
7191 {
7196 {
7199 }
7200 }
7210 {
7215 {
7218 }
7219 }
7221 }
7222 }
7224 static void
7227 {
7230 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7237 {
7242 }
7243 else
7244 {
7248 }
7249 }
7251 static void
7253 HOST_WIDE_INT words)
7254 {
7255 /* Otherwise, this should be passed indirect. */
7260 {
7263 }
7264 }
7266 /* Update the data in CUM to advance over an argument of mode MODE and
7267 data type TYPE. (TYPE is null for libcalls where that information
7268 may not be available.) */
7270 static void
7273 {
7279 else
7290 else
7292 }
7294 /* Define where to put the arguments to a function.
7295 Value is zero to push the argument on the stack,
7296 or a hard register in which to store the argument.
7298 MODE is the argument's machine mode.
7299 TYPE is the data type of the argument (as a tree).
7300 This is null for libcalls where that information may
7301 not be available.
7302 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7303 the preceding args and about the function being called.
7304 NAMED is nonzero if this argument is a named parameter
7305 (otherwise it is an extra parameter matching an ellipsis). */
7307 static rtx
7311 {
7312 /* Avoid the AL settings for the Unix64 ABI. */
7317 {
7324 /* FALLTHRU */
7330 {
7333 /* Fastcall allocates the first two DWORD (SImode) or
7334 smaller arguments to ECX and EDX if it isn't an
7335 aggregate type . */
7337 {
7343 /* ECX not EAX is the first allocated register. */
7346 }
7348 }
7357 /* FALLTHRU */
7359 /* In 32bit, we pass TImode in xmm registers. */
7367 {
7371 }
7376 /* OImode and XImode shouldn't be used directly. */
7392 {
7396 }
7406 {
7410 }
7412 }
7415 }
7417 static rtx
7420 {
7421 /* Handle a hidden AL argument containing number of registers
7422 for varargs x86-64 functions. */
7426 ? X86_64_SSE_REGPARM_MAX
7431 {
7447 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7451 }
7457 }
7459 static rtx
7462 HOST_WIDE_INT bytes)
7463 {
7466 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7467 We use value of -2 to specify that current function call is MSABI. */
7471 /* If we've run out of registers, it goes on the stack. */
7477 /* Only floating point modes are passed in anything but integer regs. */
7479 {
7482 else
7483 {
7486 /* Unnamed floating parameters are passed in both the
7487 SSE and integer registers. */
7493 }
7494 }
7495 /* Handle aggregated types passed in register. */
7497 {
7502 }
7505 }
7507 /* Return where to put the arguments to a function.
7508 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7510 MODE is the argument's machine mode. TYPE is the data type of the
7511 argument. It is null for libcalls where that information may not be
7512 available. CUM gives information about the preceding args and about
7513 the function being called. NAMED is nonzero if this argument is a
7514 named parameter (otherwise it is an extra parameter matching an
7515 ellipsis). */
7517 static rtx
7520 {
7524 rtx arg;
7528 else
7532 /* To simplify the code below, represent vector types with a vector mode
7533 even if MMX/SSE are not active. */
7541 else
7545 }
7547 /* A C expression that indicates when an argument must be passed by
7548 reference. If nonzero for an argument, a copy of that argument is
7549 made in memory and a pointer to the argument is passed instead of
7550 the argument itself. The pointer is passed in whatever way is
7551 appropriate for passing a pointer to that type. */
7553 static bool
7556 {
7559 /* See Windows x64 Software Convention. */
7561 {
7564 {
7565 /* Arrays are passed by reference. */
7570 {
7571 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7572 are passed by reference. */
7574 }
7575 }
7577 /* __m128 is passed by reference. */
7583 }
7584 }
7589 }
7591 /* Return true when TYPE should be 128bit aligned for 32bit argument
7592 passing ABI. XXX: This function is obsolete and is only used for
7593 checking psABI compatibility with previous versions of GCC. */
7595 static bool
7597 {
7609 {
7610 /* Walk the aggregates recursively. */
7612 {
7616 {
7617 tree field;
7619 /* Walk all the structure fields. */
7621 {
7625 }
7627 }
7630 /* Just for use if some languages passes arrays by value. */
7637 }
7638 }
7640 }
7642 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7643 XXX: This function is obsolete and is only used for checking psABI
7644 compatibility with previous versions of GCC. */
7646 static unsigned int
7649 {
7650 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7651 natural boundaries. */
7653 {
7654 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7655 make an exception for SSE modes since these require 128bit
7656 alignment.
7658 The handling here differs from field_alignment. ICC aligns MMX
7659 arguments to 4 byte boundaries, while structure fields are aligned
7660 to 8 byte boundaries. */
7662 {
7665 }
7666 else
7667 {
7670 }
7671 }
7675 }
7677 /* Return true when TYPE should be 128bit aligned for 32bit argument
7678 passing ABI. */
7680 static bool
7682 {
7692 {
7693 /* Walk the aggregates recursively. */
7695 {
7699 {
7700 tree field;
7702 /* Walk all the structure fields. */
7704 field;
7706 {
7710 }
7712 }
7715 /* Just for use if some languages passes arrays by value. */
7722 }
7723 }
7724 else
7728 }
7730 /* Gives the alignment boundary, in bits, of an argument with the
7731 specified mode and type. */
7733 static unsigned int
7735 {
7738 {
7739 /* Since the main variant type is used for call, we convert it to
7740 the main variant type. */
7743 }
7744 else
7748 else
7749 {
7754 {
7755 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7757 {
7760 }
7766 }
7769 && !warned
7771 saved_align))
7772 {
7775 "The ABI for passing parameters with %d-byte"
7778 }
7779 }
7782 }
7784 /* Return true if N is a possible register number of function value. */
7786 static bool
7788 {
7790 {
7798 /* Complex values are returned in %st(0)/%st(1) pair. */
7801 /* TODO: The function should depend on current function ABI but
7802 builtins.c would need updating then. Therefore we use the
7803 default ABI. */
7808 /* Complex values are returned in %xmm0/%xmm1 pair. */
7817 }
7820 }
7822 /* Define how to find the value returned by a function.
7823 VALTYPE is the data type of the value (as a tree).
7824 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7825 otherwise, FUNC is 0. */
7827 static rtx
7830 {
7833 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7834 we normally prevent this case when mmx is not available. However
7835 some ABIs may require the result to be returned like DImode. */
7839 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7840 we prevent this case when sse is not available. However some ABIs
7841 may require the result to be returned like integer TImode. */
7846 /* 32-byte vector modes in %ymm0. */
7850 /* 64-byte vector modes in %zmm0. */
7854 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7857 else
7858 /* Most things go in %eax. */
7861 /* Override FP return register with %xmm0 for local functions when
7862 SSE math is enabled or for functions with sseregparm attribute. */
7864 {
7869 }
7871 /* OImode shouldn't be used directly. */
7875 }
7877 static rtx
7879 const_tree valtype)
7880 {
7881 rtx ret;
7883 /* Handle libcalls, which don't provide a type node. */
7885 {
7889 {
7908 }
7911 }
7913 {
7914 /* Pointers are always returned in word_mode. */
7916 }
7922 /* For zero sized structures, construct_container returns NULL, but we
7923 need to keep rest of compiler happy by returning meaningful value. */
7928 }
7930 static rtx
7932 const_tree valtype)
7933 {
7937 {
7939 {
7958 }
7959 }
7961 }
7963 static rtx
7966 {
7978 else
7980 }
7982 static rtx
7985 {
7991 }
7993 /* Pointer function arguments and return values are promoted to
7994 word_mode. */
7996 static enum machine_mode
8000 {
8002 {
8005 }
8007 for_return);
8008 }
8010 /* Return true if a structure, union or array with MODE containing FIELD
8011 should be accessed using BLKmode. */
8013 static bool
8015 {
8016 /* Union with XFmode must be in BLKmode. */
8020 }
8022 rtx
8024 {
8026 }
8028 /* Return true iff type is returned in memory. */
8030 static bool ATTRIBUTE_UNUSED
8032 {
8033 HOST_WIDE_INT size;
8044 {
8045 /* User-created vectors small enough to fit in EAX. */
8049 /* MMX/3dNow values are returned in MM0,
8050 except when it doesn't exits or the ABI prescribes otherwise. */
8054 /* SSE values are returned in XMM0, except when it doesn't exist. */
8058 /* AVX values are returned in YMM0, except when it doesn't exist. */
8062 /* AVX512F values are returned in ZMM0, except when it doesn't exist. */
8065 }
8073 /* OImode shouldn't be used directly. */
8077 }
8079 static bool ATTRIBUTE_UNUSED
8081 {
8084 }
8086 static bool ATTRIBUTE_UNUSED
8088 {
8091 /* __m128 is returned in xmm0. */
8098 /* Otherwise, the size must be exactly in [1248]. */
8100 }
8102 static bool
8104 {
8105 #ifdef SUBTARGET_RETURN_IN_MEMORY
8107 #else
8111 {
8114 else
8116 }
8117 else
8119 #endif
8120 }
8122 \f
8123 /* Create the va_list data type. */
8125 /* Returns the calling convention specific va_list date type.
8126 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8128 static tree
8130 {
8133 /* For i386 we use plain pointer to argument area. */
8143 unsigned_type_node);
8146 unsigned_type_node);
8149 ptr_type_node);
8152 ptr_type_node);
8171 /* The correct type is an array type of one element. */
8173 }
8175 /* Setup the builtin va_list data type and for 64-bit the additional
8176 calling convention specific va_list data types. */
8178 static tree
8180 {
8183 /* Initialize abi specific va_list builtin types. */
8185 {
8186 tree t;
8188 {
8193 }
8194 else
8195 {
8200 }
8202 {
8207 }
8208 else
8209 {
8214 }
8215 }
8218 }
8220 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8222 static void
8224 {
8226 alias_set_type set;
8229 /* GPR size of varargs save area. */
8232 else
8235 /* FPR size of varargs save area. We don't need it if we don't pass
8236 anything in SSE registers. */
8239 else
8253 {
8261 }
8264 {
8268 /* Now emit code to save SSE registers. The AX parameter contains number
8269 of SSE parameter registers used to call this function, though all we
8270 actually check here is the zero/non-zero status. */
8275 label));
8277 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8278 we used movdqa (i.e. TImode) instead? Perhaps even better would
8279 be if we could determine the real mode of the data, via a hook
8280 into pass_stdarg. Ignore all that for now. */
8290 {
8299 }
8302 }
8303 }
8305 static void
8307 {
8311 /* Reset to zero, as there might be a sysv vaarg used
8312 before. */
8317 {
8328 }
8329 }
8331 static void
8335 {
8337 CUMULATIVE_ARGS next_cum;
8338 tree fntype;
8340 /* This argument doesn't appear to be used anymore. Which is good,
8341 because the old code here didn't suppress rtl generation. */
8349 /* For varargs, we do not want to skip the dummy va_dcl argument.
8350 For stdargs, we do want to skip the last named argument. */
8358 else
8360 }
8362 /* Checks if TYPE is of kind va_list char *. */
8364 static bool
8366 {
8367 tree canonic;
8369 /* For 32-bit it is always true. */
8375 }
8377 /* Implement va_start. */
8379 static void
8381 {
8385 tree type;
8386 rtx ovf_rtx;
8390 {
8393 /* When we are splitting the stack, we can't refer to the stack
8394 arguments using internal_arg_pointer, because they may be on
8395 the old stack. The split stack prologue will arrange to
8396 leave a pointer to the old stack arguments in a scratch
8397 register, which we here copy to a pseudo-register. The split
8398 stack prologue can't set the pseudo-register directly because
8399 it (the prologue) runs before any registers have been saved. */
8403 {
8417 }
8418 }
8420 /* Only 64bit target needs something special. */
8422 {
8425 else
8426 {
8435 }
8437 }
8446 /* The following should be folded into the MEM_REF offset. */
8456 /* Count number of gp and fp argument registers used. */
8462 {
8468 }
8471 {
8477 }
8479 /* Find the overflow area. */
8483 else
8493 {
8494 /* Find the register save area.
8495 Prologue of the function save it right above stack frame. */
8503 }
8504 }
8506 /* Implement va_arg. */
8508 static tree
8511 {
8518 rtx container;
8520 tree ptrtype;
8524 /* Only 64bit target needs something special. */
8548 {
8561 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8563 {
8566 }
8574 }
8576 /* Pull the value out of the saved registers. */
8581 {
8595 /* In case we are passing structure, verify that it is consecutive block
8596 on the register save area. If not we need to do moves. */
8598 {
8599 /* Verify that all registers are strictly consecutive */
8601 {
8605 {
8610 }
8611 }
8612 else
8613 {
8617 {
8622 }
8623 }
8624 }
8626 {
8629 }
8630 else
8631 {
8634 }
8636 /* First ensure that we fit completely in registers. */
8638 {
8645 }
8647 {
8655 }
8657 /* Compute index to start of area used for integer regs. */
8659 {
8660 /* int_addr = gpr + sav; */
8663 }
8665 {
8666 /* sse_addr = fpr + sav; */
8669 }
8671 {
8675 /* addr = &temp; */
8680 {
8684 tree piece_type;
8685 tree addr_type;
8686 tree daddr_type;
8695 {
8700 }
8704 else
8711 {
8714 }
8715 else
8716 {
8719 }
8726 {
8731 }
8732 else
8733 {
8734 tree copy
8739 }
8741 }
8742 }
8745 {
8749 }
8752 {
8756 }
8761 }
8763 /* ... otherwise out of the overflow area. */
8765 /* When we align parameter on stack for caller, if the parameter
8766 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8767 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8768 here with caller. */
8773 /* Care for on-stack alignment if needed. */
8776 else
8777 {
8782 }
8799 }
8800 \f
8801 /* Return true if OPNUM's MEM should be matched
8802 in movabs* patterns. */
8804 bool
8806 {
8818 }
8819 \f
8820 /* Initialize the table of extra 80387 mathematical constants. */
8822 static void
8824 {
8826 {
8832 };
8836 {
8838 /* Ensure each constant is rounded to XFmode precision. */
8841 }
8844 }
8846 /* Return non-zero if the constant is something that
8847 can be loaded with a special instruction. */
8849 int
8851 {
8854 REAL_VALUE_TYPE r;
8866 /* For XFmode constants, try to find a special 80387 instruction when
8867 optimizing for size or on those CPUs that benefit from them. */
8870 {
8879 }
8881 /* Load of the constant -0.0 or -1.0 will be split as
8882 fldz;fchs or fld1;fchs sequence. */
8889 }
8891 /* Return the opcode of the special instruction to be used to load
8892 the constant X. */
8896 {
8898 {
8918 }
8919 }
8921 /* Return the CONST_DOUBLE representing the 80387 constant that is
8922 loaded by the specified special instruction. The argument IDX
8923 matches the return value from standard_80387_constant_p. */
8925 rtx
8927 {
8934 {
8945 }
8948 XFmode);
8949 }
8951 /* Return 1 if X is all 0s and 2 if x is all 1s
8952 in supported SSE/AVX vector mode. */
8954 int
8956 {
8963 {
8984 }
8987 }
8989 /* Return the opcode of the special instruction to be used to load
8990 the constant X. */
8994 {
8996 {
8999 {
9021 }
9030 else
9035 }
9037 }
9039 /* Returns true if OP contains a symbol reference */
9041 bool
9043 {
9052 {
9054 {
9060 }
9064 }
9067 }
9069 /* Return true if it is appropriate to emit `ret' instructions in the
9070 body of a function. Do this only if the epilogue is simple, needing a
9071 couple of insns. Prior to reloading, we can't tell how many registers
9072 must be saved, so return false then. Return false if there is no frame
9073 marker to de-allocate. */
9075 bool
9077 {
9083 /* Don't allow more than 32k pop, since that's all we can do
9084 with one instruction. */
9091 }
9092 \f
9093 /* Value should be nonzero if functions must have frame pointers.
9094 Zero means the frame pointer need not be set up (and parms may
9095 be accessed via the stack pointer) in functions that seem suitable. */
9097 static bool
9099 {
9100 /* If we accessed previous frames, then the generated code expects
9101 to be able to access the saved ebp value in our frame. */
9105 /* Several x86 os'es need a frame pointer for other reasons,
9106 usually pertaining to setjmp. */
9110 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9114 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9115 allocation is 4GB. */
9123 }
9125 /* Return true if the frame pointer of the function could be omitted. */
9127 static bool
9129 {
9130 return TARGET_OMIT_LEAF_FRAME_POINTER
9133 }
9135 /* Record that the current function accesses previous call frames. */
9137 void
9139 {
9141 }
9142 \f
9143 #ifndef USE_HIDDEN_LINKONCE
9144 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9145 # define USE_HIDDEN_LINKONCE 1
9146 # else
9147 # define USE_HIDDEN_LINKONCE 0
9148 # endif
9149 #endif
9153 /* Fills in the label name that should be used for a pc thunk for
9154 the given register. */
9156 static void
9158 {
9163 else
9165 }
9168 /* This function generates code for -fpic that loads %ebx with
9169 the return address of the caller and then returns. */
9171 static void
9173 {
9178 {
9180 tree decl;
9196 #if TARGET_MACHO
9198 {
9207 }
9208 else
9209 #endif
9211 {
9222 }
9223 else
9224 {
9227 }
9233 /* Make sure unwind info is emitted for the thunk if needed. */
9236 /* Pad stack IP move with 4 instructions (two NOPs count
9237 as one instruction). */
9239 {
9244 }
9255 }
9259 }
9261 /* Emit code for the SET_GOT patterns. */
9265 {
9271 {
9272 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9277 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9278 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9279 an unadorned address. */
9284 }
9289 {
9291 /* We don't need a pic base, we're not producing pic. */
9298 }
9299 else
9300 {
9309 #if TARGET_MACHO
9310 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9311 This is what will be referenced by the Mach-O PIC subsystem. */
9315 /* When we are restoring the pic base at the site of a nonlocal label,
9316 and we decided to emit the pic base above, we will still output a
9317 local label used for calculating the correction offset (even though
9318 the offset will be 0 in that case). */
9322 #endif
9323 }
9329 }
9331 /* Generate an "push" pattern for input ARG. */
9333 static rtx
9335 {
9348 stack_pointer_rtx)),
9349 arg);
9350 }
9352 /* Generate an "pop" pattern for input ARG. */
9354 static rtx
9356 {
9361 arg,
9364 stack_pointer_rtx)));
9365 }
9367 /* Return >= 0 if there is an unused call-clobbered register available
9368 for the entire function. */
9370 static unsigned int
9372 {
9376 {
9378 /* Can't use the same register for both PIC and DRAP. */
9381 else
9386 }
9389 }
9391 /* Return TRUE if we need to save REGNO. */
9393 static bool
9395 {
9406 {
9409 {
9415 }
9416 }
9427 }
9429 /* Return number of saved general prupose registers. */
9431 static int
9433 {
9439 nregs ++;
9441 }
9443 /* Return number of saved SSE registrers. */
9445 static int
9447 {
9455 nregs ++;
9457 }
9459 /* Given FROM and TO register numbers, say whether this elimination is
9460 allowed. If stack alignment is needed, we can only replace argument
9461 pointer with hard frame pointer, or replace frame pointer with stack
9462 pointer. Otherwise, frame pointer elimination is automatically
9463 handled and all other eliminations are valid. */
9465 static bool
9467 {
9473 else
9475 }
9477 /* Return the offset between two registers, one to be eliminated, and the other
9478 its replacement, at the start of a routine. */
9480 HOST_WIDE_INT
9482 {
9491 else
9492 {
9500 }
9501 }
9503 /* In a dynamically-aligned function, we can't know the offset from
9504 stack pointer to frame pointer, so we must ensure that setjmp
9505 eliminates fp against the hard fp (%ebp) rather than trying to
9506 index from %esp up to the top of the frame across a gap that is
9507 of unknown (at compile-time) size. */
9508 static rtx
9510 {
9512 }
9514 /* When using -fsplit-stack, the allocation routines set a field in
9515 the TCB to the bottom of the stack plus this much space, measured
9516 in bytes. */
9518 #define SPLIT_STACK_AVAILABLE 256
9520 /* Fill structure ix86_frame about frame of currently computed function. */
9522 static void
9524 {
9526 HOST_WIDE_INT offset;
9529 HOST_WIDE_INT to_allocate;
9537 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9538 function prologues and leaf. */
9542 {
9547 }
9553 /* For SEH we have to limit the amount of code movement into the prologue.
9554 At present we do this via a BLOCKAGE, at which point there's very little
9555 scheduling that can be done, which means that there's very little point
9556 in doing anything except PUSHs. */
9560 /* During reload iteration the amount of registers saved can change.
9561 Recompute the value as needed. Do not recompute when amount of registers
9562 didn't change as reload does multiple calls to the function and does not
9563 expect the decision to change within single iteration. */
9566 {
9572 /* The fast prologue uses move instead of push to save registers. This
9573 is significantly longer, but also executes faster as modern hardware
9574 can execute the moves in parallel, but can't do that for push/pop.
9576 Be careful about choosing what prologue to emit: When function takes
9577 many instructions to execute we may use slow version as well as in
9578 case function is known to be outside hot spot (this is known with
9579 feedback only). Weight the size of function by number of registers
9580 to save as it is cheap to use one or two push instructions but very
9581 slow to use many of them. */
9585 || (flag_branch_probabilities
9588 else
9591 }
9593 frame->save_regs_using_mov
9595 /* If static stack checking is enabled and done with probes,
9596 the registers need to be saved before allocating the frame. */
9599 /* Skip return address. */
9602 /* Skip pushed static chain. */
9606 /* Skip saved base pointer. */
9611 /* The traditional frame pointer location is at the top of the frame. */
9614 /* Register save area */
9618 /* On SEH target, registers are pushed just before the frame pointer
9619 location. */
9623 /* Align and set SSE register save area. */
9625 {
9626 /* The only ABI that has saved SSE registers (Win64) also has a
9627 16-byte aligned default stack, and thus we don't need to be
9628 within the re-aligned local stack frame to save them. */
9632 }
9635 /* The re-aligned stack starts here. Values before this point are not
9636 directly comparable with values below this point. In order to make
9637 sure that no value happens to be the same before and after, force
9638 the alignment computation below to add a non-zero value. */
9642 /* Va-arg area */
9646 /* Align start of frame for local function. */
9655 /* Frame pointer points here. */
9660 /* Add outgoing arguments area. Can be skipped if we eliminated
9661 all the function calls as dead code.
9662 Skipping is however impossible when function calls alloca. Alloca
9663 expander assumes that last crtl->outgoing_args_size
9664 of stack frame are unused. */
9668 {
9671 }
9672 else
9675 /* Align stack boundary. Only needed if we're calling another function
9676 or using alloca. */
9681 /* We've reached end of stack frame. */
9684 /* Size prologue needs to allocate. */
9695 {
9701 }
9702 else
9706 /* The SEH frame pointer location is near the bottom of the frame.
9707 This is enforced by the fact that the difference between the
9708 stack pointer and the frame pointer is limited to 240 bytes in
9709 the unwind data structure. */
9711 {
9712 HOST_WIDE_INT diff;
9714 /* If we can leave the frame pointer where it is, do so. Also, returns
9715 the establisher frame for __builtin_frame_address (0). */
9720 {
9721 /* Ideally we'd determine what portion of the local stack frame
9722 (within the constraint of the lowest 240) is most heavily used.
9723 But without that complication, simply bias the frame pointer
9724 by 128 bytes so as to maximize the amount of the local stack
9725 frame that is addressable with 8-bit offsets. */
9727 }
9728 }
9729 }
9731 /* This is semi-inlined memory_address_length, but simplified
9732 since we know that we're always dealing with reg+offset, and
9733 to avoid having to create and discard all that rtl. */
9737 {
9741 {
9742 /* EBP and R13 cannot be encoded without an offset. */
9744 }
9748 /* ESP and R12 must be encoded with a SIB byte. */
9750 len++;
9753 }
9755 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9756 The valid base registers are taken from CFUN->MACHINE->FS. */
9758 static rtx
9760 {
9766 {
9767 /* Choose the base register most likely to allow the most scheduling
9768 opportunities. Generally FP is valid throughout the function,
9769 while DRAP must be reloaded within the epilogue. But choose either
9770 over the SP due to increased encoding size. */
9773 {
9776 }
9778 {
9781 }
9783 {
9786 }
9787 }
9788 else
9789 {
9790 HOST_WIDE_INT toffset;
9793 /* Choose the base register with the smallest address encoding.
9794 With a tie, choose FP > DRAP > SP. */
9796 {
9800 }
9802 {
9806 {
9810 }
9811 }
9813 {
9817 {
9821 }
9822 }
9823 }
9827 }
9829 /* Emit code to save registers in the prologue. */
9831 static void
9833 {
9835 rtx insn;
9839 {
9842 }
9843 }
9845 /* Emit a single register save at CFA - CFA_OFFSET. */
9847 static void
9849 HOST_WIDE_INT cfa_offset)
9850 {
9858 /* For SSE saves, we need to indicate the 128-bit alignment. */
9869 /* When saving registers into a re-aligned local stack frame, avoid
9870 any tricky guessing by dwarf2out. */
9872 {
9876 {
9877 /* A bit of a hack. We force the DRAP register to be saved in
9878 the re-aligned stack frame, which provides us with a copy
9879 of the CFA that will last past the prologue. Install it. */
9885 }
9886 else
9887 {
9888 /* The frame pointer is a stable reference within the
9889 aligned frame. Use it. */
9896 }
9897 }
9899 /* The memory may not be relative to the current CFA register,
9900 which means that we may need to generate a new pattern for
9901 use by the unwind info. */
9903 {
9908 }
9909 }
9911 /* Emit code to save registers using MOV insns.
9912 First register is stored at CFA - CFA_OFFSET. */
9913 static void
9915 {
9920 {
9923 }
9924 }
9926 /* Emit code to save SSE registers using MOV insns.
9927 First register is stored at CFA - CFA_OFFSET. */
9928 static void
9930 {
9935 {
9938 }
9939 }
9943 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9944 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9945 Don't add the note if the previously saved value will be left untouched
9946 within stack red-zone till return, as unwinders can find the same value
9947 in the register and on the stack. */
9949 static void
9951 {
9957 {
9960 }
9961 else
9962 queued_cfa_restores
9964 }
9966 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9968 static void
9970 {
9971 rtx last;
9975 ;
9980 }
9982 /* Expand prologue or epilogue stack adjustment.
9983 The pattern exist to put a dependency on all ebp-based memory accesses.
9984 STYLE should be negative if instructions should be marked as frame related,
9985 zero if %r11 register is live and cannot be freely used and positive
9986 otherwise. */
9988 static void
9991 {
9993 rtx insn;
10000 else
10001 {
10002 rtx tmp;
10003 /* r11 is used by indirect sibcall return as well, set before the
10004 epilogue and used after the epilogue. */
10007 else
10008 {
10012 }
10018 }
10025 {
10026 rtx r;
10036 }
10038 {
10041 {
10045 }
10046 }
10049 {
10054 {
10057 }
10059 {
10062 }
10063 else
10064 {
10065 /* Else there are two possibilities: SP itself, which we set
10066 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10067 taken care of this by hand along the eh_return path. */
10070 }
10074 }
10075 }
10077 /* Find an available register to be used as dynamic realign argument
10078 pointer regsiter. Such a register will be written in prologue and
10079 used in begin of body, so it must not be
10080 1. parameter passing register.
10081 2. GOT pointer.
10082 We reuse static-chain register if it is available. Otherwise, we
10083 use DI for i386 and R13 for x86-64. We chose R13 since it has
10084 shorter encoding.
10086 Return: the regno of chosen register. */
10088 static unsigned int
10090 {
10094 {
10095 /* Use R13 for nested function or function need static chain.
10096 Since function with tail call may use any caller-saved
10097 registers in epilogue, DRAP must not use caller-saved
10098 register in such case. */
10103 }
10104 else
10105 {
10106 /* Use DI for nested function or function need static chain.
10107 Since function with tail call may use any caller-saved
10108 registers in epilogue, DRAP must not use caller-saved
10109 register in such case. */
10113 /* Reuse static chain register if it isn't used for parameter
10114 passing. */
10116 {
10120 }
10122 }
10123 }
10125 /* Return minimum incoming stack alignment. */
10127 static unsigned int
10129 {
10132 /* Prefer the one specified at command line. */
10135 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10136 if -mstackrealign is used, it isn't used for sibcall check and
10137 estimated stack alignment is 128bit. */
10139 && !TARGET_64BIT
10140 && ix86_force_align_arg_pointer
10143 else
10146 /* Incoming stack alignment can be changed on individual functions
10147 via force_align_arg_pointer attribute. We use the smallest
10148 incoming stack boundary. */
10154 /* The incoming stack frame has to be aligned at least at
10155 parm_stack_boundary. */
10159 /* Stack at entrance of main is aligned by runtime. We use the
10160 smallest incoming stack boundary. */
10168 }
10170 /* Update incoming stack boundary and estimated stack alignment. */
10172 static void
10174 {
10175 ix86_incoming_stack_boundary
10178 /* x86_64 vararg needs 16byte stack alignment for register save
10179 area. */
10184 }
10186 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10187 needed or an rtx for DRAP otherwise. */
10189 static rtx
10191 {
10196 {
10197 /* Assign DRAP to vDRAP and returns vDRAP */
10199 rtx drap_vreg;
10200 rtx arg_ptr;
10213 {
10216 }
10218 }
10219 else
10221 }
10223 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10225 static rtx
10227 {
10229 }
10232 rtx reg;
10234 };
10236 /* Return a short-lived scratch register for use on function entry.
10237 In 32-bit mode, it is valid only after the registers are saved
10238 in the prologue. This register must be released by means of
10239 release_scratch_register_on_entry once it is dead. */
10241 static void
10243 {
10249 {
10250 /* We always use R11 in 64-bit mode. */
10252 }
10253 else
10254 {
10256 bool fastcall_p
10258 bool thiscall_p
10262 int drap_regno
10265 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10266 for the static chain register. */
10270 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10271 for the static chain register. */
10276 /* ecx is the static chain register. */
10278 && !static_chain_p
10283 /* esi is the static chain register. */
10289 else
10290 {
10293 }
10294 }
10298 {
10301 }
10302 }
10304 /* Release a scratch register obtained from the preceding function. */
10306 static void
10308 {
10310 {
10314 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10320 }
10321 }
10323 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10325 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10327 static void
10329 {
10330 /* We skip the probe for the first interval + a small dope of 4 words and
10331 probe that many bytes past the specified size to maintain a protection
10332 area at the botton of the stack. */
10336 /* See if we have a constant small number of probes to generate. If so,
10337 that's the easy case. The run-time loop is made up of 11 insns in the
10338 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10339 for n # of intervals. */
10341 {
10345 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10346 values of N from 1 until it exceeds SIZE. If only one probe is
10347 needed, this will not generate any code. Then adjust and probe
10348 to PROBE_INTERVAL + SIZE. */
10350 {
10352 {
10355 }
10356 else
10363 }
10367 else
10375 /* Adjust back to account for the additional first interval. */
10379 }
10381 /* Otherwise, do the same as above, but in a loop. Note that we must be
10382 extra careful with variables wrapping around because we might be at
10383 the very top (or the very bottom) of the address space and we have
10384 to be able to handle this case properly; in particular, we use an
10385 equality test for the loop condition. */
10386 else
10387 {
10388 HOST_WIDE_INT rounded_size;
10394 /* Step 1: round SIZE to the previous multiple of the interval. */
10399 /* Step 2: compute initial and final value of the loop counter. */
10401 /* SP = SP_0 + PROBE_INTERVAL. */
10406 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10410 stack_pointer_rtx)));
10413 /* Step 3: the loop
10415 while (SP != LAST_ADDR)
10416 {
10417 SP = SP + PROBE_INTERVAL
10418 probe at SP
10419 }
10421 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10422 values of N from 1 until it is equal to ROUNDED_SIZE. */
10427 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10428 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10431 {
10436 }
10438 /* Adjust back to account for the additional first interval. */
10444 }
10448 /* Even if the stack pointer isn't the CFA register, we need to correctly
10449 describe the adjustments made to it, in particular differentiate the
10450 frame-related ones from the frame-unrelated ones. */
10452 {
10465 }
10467 /* Make sure nothing is scheduled before we are done. */
10469 }
10471 /* Adjust the stack pointer up to REG while probing it. */
10475 {
10485 /* Jump to END_LAB if SP == LAST_ADDR. */
10493 /* SP = SP + PROBE_INTERVAL. */
10497 /* Probe at SP. */
10508 }
10510 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10511 inclusive. These are offsets from the current stack pointer. */
10513 static void
10515 {
10516 /* See if we have a constant small number of probes to generate. If so,
10517 that's the easy case. The run-time loop is made up of 7 insns in the
10518 generic case while the compile-time loop is made up of n insns for n #
10519 of intervals. */
10521 {
10522 HOST_WIDE_INT i;
10524 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10525 it exceeds SIZE. If only one probe is needed, this will not
10526 generate any code. Then probe at FIRST + SIZE. */
10533 }
10535 /* Otherwise, do the same as above, but in a loop. Note that we must be
10536 extra careful with variables wrapping around because we might be at
10537 the very top (or the very bottom) of the address space and we have
10538 to be able to handle this case properly; in particular, we use an
10539 equality test for the loop condition. */
10540 else
10541 {
10548 /* Step 1: round SIZE to the previous multiple of the interval. */
10553 /* Step 2: compute initial and final value of the loop counter. */
10555 /* TEST_OFFSET = FIRST. */
10558 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10562 /* Step 3: the loop
10564 while (TEST_ADDR != LAST_ADDR)
10565 {
10566 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10567 probe at TEST_ADDR
10568 }
10570 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10571 until it is equal to ROUNDED_SIZE. */
10576 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10577 that SIZE is equal to ROUNDED_SIZE. */
10582 stack_pointer_rtx,
10587 }
10589 /* Make sure nothing is scheduled before we are done. */
10591 }
10593 /* Probe a range of stack addresses from REG to END, inclusive. These are
10594 offsets from the current stack pointer. */
10598 {
10608 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10616 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10620 /* Probe at TEST_ADDR. */
10633 }
10635 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10636 to be generated in correct form. */
10637 static void
10639 {
10640 /* Check if stack realign is really needed after reload, and
10641 stores result in cfun */
10642 unsigned int incoming_stack_boundary
10651 {
10652 /* After stack_realign_needed is finalized, we can't no longer
10653 change it. */
10656 }
10658 /* If the only reason for frame_pointer_needed is that we conservatively
10659 assumed stack realignment might be needed, but in the end nothing that
10660 needed the stack alignment had been spilled, clear frame_pointer_needed
10661 and say we don't need stack realignment. */
10663 && frame_pointer_needed
10665 && flag_omit_frame_pointer
10667 && !ix86_current_function_calls_tls_descriptor
10676 {
10678 basic_block bb;
10685 HARD_FRAME_POINTER_REGNUM);
10687 {
10688 rtx insn;
10692 set_up_by_prologue))
10693 {
10697 }
10698 }
10700 /* If drap has been set, but it actually isn't live at the start
10701 of the function, there is no reason to set it up. */
10703 {
10706 {
10709 }
10710 }
10711 else
10726 }
10730 }
10732 /* Expand the prologue into a bunch of separate insns. */
10734 void
10736 {
10741 HOST_WIDE_INT allocate;
10747 /* DRAP should not coexist with stack_realign_fp */
10752 /* Initialize CFA state for before the prologue. */
10756 /* Track SP offset to the CFA. We continue tracking this after we've
10757 swapped the CFA register away from SP. In the case of re-alignment
10758 this is fudged; we're interested to offsets within the local frame. */
10765 {
10766 /* We should have already generated an error for any use of
10767 ms_hook on a nested function. */
10770 /* Check if profiling is active and we shall use profiling before
10771 prologue variant. If so sorry. */
10776 /* In ix86_asm_output_function_label we emitted:
10777 8b ff movl.s %edi,%edi
10778 55 push %ebp
10779 8b ec movl.s %esp,%ebp
10781 This matches the hookable function prologue in Win32 API
10782 functions in Microsoft Windows XP Service Pack 2 and newer.
10783 Wine uses this to enable Windows apps to hook the Win32 API
10784 functions provided by Wine.
10786 What that means is that we've already set up the frame pointer. */
10790 {
10793 /* We've decided to use the frame pointer already set up.
10794 Describe this to the unwinder by pretending that both
10795 push and mov insns happen right here.
10797 Putting the unwind info here at the end of the ms_hook
10798 is done so that we can make absolutely certain we get
10799 the required byte sequence at the start of the function,
10800 rather than relying on an assembler that can produce
10801 the exact encoding required.
10803 However it does mean (in the unpatched case) that we have
10804 a 1 insn window where the asynchronous unwind info is
10805 incorrect. However, if we placed the unwind info at
10806 its correct location we would have incorrect unwind info
10807 in the patched case. Which is probably all moot since
10808 I don't expect Wine generates dwarf2 unwind info for the
10809 system libraries that use this feature. */
10815 stack_pointer_rtx);
10823 /* Note that gen_push incremented m->fs.cfa_offset, even
10824 though we didn't emit the push insn here. */
10828 }
10829 else
10830 {
10831 /* The frame pointer is not needed so pop %ebp again.
10832 This leaves us with a pristine state. */
10834 }
10835 }
10837 /* The first insn of a function that accepts its static chain on the
10838 stack is to push the register that would be filled in by a direct
10839 call. This insn will be skipped by the trampoline. */
10841 {
10845 /* We don't want to interpret this push insn as a register save,
10846 only as a stack adjustment. The real copy of the register as
10847 a save will be done later, if needed. */
10852 }
10854 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10855 of DRAP is needed and stack realignment is really needed after reload */
10857 {
10860 /* Only need to push parameter pointer reg if it is caller saved. */
10862 {
10863 /* Push arg pointer reg */
10866 }
10868 /* Grab the argument pointer. */
10875 /* Align the stack. */
10877 stack_pointer_rtx,
10881 /* Replicate the return address on the stack so that return
10882 address can be reached via (argp - 1) slot. This is needed
10883 to implement macro RETURN_ADDR_RTX and intrinsic function
10884 expand_builtin_return_addr etc. */
10890 /* For the purposes of frame and register save area addressing,
10891 we've started over with a new frame. */
10894 }
10900 {
10901 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10902 slower on all targets. Also sdb doesn't like it. */
10906 /* Push registers now, before setting the frame pointer
10907 on SEH target. */
10909 && TARGET_SEH
10911 {
10915 }
10918 {
10926 }
10927 }
10929 {
10933 {
10935 /* Using sp as cfa_reg will involve more .cfi_def_cfa_offset for
10936 pushes in prologue, so use fp as cfa_reg to reduce .eh_frame
10937 size when possible. */
10939 {
10945 }
10946 }
10947 }
10950 {
10951 /* If saving registers via PUSH, do so now. */
10953 {
10957 }
10959 /* When using red zone we may start register saving before allocating
10960 the stack frame saving one cycle of the prologue. However, avoid
10961 doing this if we have to probe the stack; at least on x86_64 the
10962 stack probe can turn into a call that clobbers a red zone location. */
10964 && (! TARGET_STACK_PROBE
10966 {
10969 }
10970 }
10973 {
10977 /* The computation of the size of the re-aligned stack frame means
10978 that we must allocate the size of the register save area before
10979 performing the actual alignment. Otherwise we cannot guarantee
10980 that there's enough storage above the realignment point. */
10987 /* Align the stack. */
10989 stack_pointer_rtx,
10992 /* For the purposes of register save area addressing, the stack
10993 pointer is no longer valid. As for the value of sp_offset,
10994 see ix86_compute_frame_layout, which we need to match in order
10995 to pass verification of stack_pointer_offset at the end. */
10998 }
11003 {
11004 /* We start to count from ARG_POINTER. */
11007 /* If it was realigned, take into account the fake frame. */
11009 {
11016 /* This over-estimates by 1 minimal-stack-alignment-unit but
11017 mitigates that by counting in the new return address slot. */
11018 current_function_dynamic_stack_size
11020 }
11023 }
11025 /* On SEH target with very large frame size, allocate an area to save
11026 SSE registers (as the very large allocation won't be described). */
11030 {
11031 HOST_WIDE_INT sse_size =
11036 /* No need to do stack checking as the area will be immediately
11037 written. */
11044 }
11046 /* The stack has already been decremented by the instruction calling us
11047 so probe if the size is non-negative to preserve the protection area. */
11049 {
11050 /* We expect the registers to be saved when probes are used. */
11054 {
11057 {
11060 }
11061 }
11062 else
11063 {
11070 {
11072 {
11075 }
11076 else
11078 }
11079 else
11080 {
11082 {
11086 }
11087 else
11089 }
11090 }
11091 }
11094 ;
11097 {
11101 }
11102 else
11103 {
11115 {
11118 /* Note that SEH directives need to continue tracking the stack
11119 pointer even after the frame pointer has been set up. */
11121 {
11129 }
11130 }
11133 {
11138 {
11146 }
11147 }
11152 /* Use the fact that AX still contains ALLOCATE. */
11154 ? gen_pro_epilogue_adjust_stack_di_sub
11161 {
11169 }
11172 /* Use stack_pointer_rtx for relative addressing so that code
11173 works for realigned stack, too. */
11175 {
11182 }
11184 {
11189 }
11190 }
11193 /* If we havn't already set up the frame pointer, do so now. */
11195 {
11207 }
11215 /* We don't use pic-register for pe-coff target. */
11217 && !TARGET_PECOFF
11220 {
11227 }
11230 {
11232 {
11234 {
11244 label));
11248 }
11249 else
11251 }
11252 else
11253 {
11257 }
11258 }
11260 /* In the pic_reg_used case, make sure that the got load isn't deleted
11261 when mcount needs it. Blockage to avoid call movement across mcount
11262 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11263 note. */
11268 {
11269 /* vDRAP is setup but after reload it turns out stack realign
11270 isn't necessary, here we will emit prologue to setup DRAP
11271 without stack realign adjustment */
11274 }
11276 /* Prevent instructions from being scheduled into register save push
11277 sequence when access to the redzone area is done through frame pointer.
11278 The offset between the frame pointer and the stack pointer is calculated
11279 relative to the value of the stack pointer at the end of the function
11280 prologue, and moving instructions that access redzone area via frame
11281 pointer inside push sequence violates this assumption. */
11285 /* Emit cld instruction if stringops are used in the function. */
11289 /* SEH requires that the prologue end within 256 bytes of the start of
11290 the function. Prevent instruction schedules that would extend that.
11291 Further, prevent alloca modifications to the stack pointer from being
11292 combined with prologue modifications. */
11295 }
11297 /* Get frame pointer setting insn based on frame state. */
11298 static rtx
11300 {
11303 HOST_WIDE_INT offset;
11310 {
11315 }
11316 else
11317 {
11320 }
11323 }
11325 /* Emit code to restore REG using a POP insn. */
11327 static void
11329 {
11338 {
11339 /* Previously we'd represented the CFA as an expression
11340 like *(%ebp - 8). We've just popped that value from
11341 the stack, which means we need to reset the CFA to
11342 the drap register. This will remain until we restore
11343 the stack pointer. */
11347 /* This means that the DRAP register is valid for addressing too. */
11350 }
11353 {
11360 }
11362 /* When the frame pointer is the CFA, and we pop it, we are
11363 swapping back to the stack pointer as the CFA. This happens
11364 for stack frames that don't allocate other data, so we assume
11365 the stack pointer is now pointing at the return address, i.e.
11366 the function entry state, which makes the offset be 1 word. */
11368 {
11371 {
11379 }
11380 }
11381 }
11383 /* Emit code to restore saved registers using POP insns. */
11385 static void
11387 {
11393 }
11395 /* Emit code and notes for the LEAVE instruction. */
11397 static void
11399 {
11411 {
11419 }
11422 }
11424 /* Emit code to restore saved registers using MOV insns.
11425 First register is restored from CFA - CFA_OFFSET. */
11426 static void
11429 {
11435 {
11444 {
11445 /* Previously we'd represented the CFA as an expression
11446 like *(%ebp - 8). We've just popped that value from
11447 the stack, which means we need to reset the CFA to
11448 the drap register. This will remain until we restore
11449 the stack pointer. */
11453 /* This means that the DRAP register is valid for addressing. */
11455 }
11456 else
11460 }
11461 }
11463 /* Emit code to restore saved registers using MOV insns.
11464 First register is restored from CFA - CFA_OFFSET. */
11465 static void
11468 {
11473 {
11475 rtx mem;
11485 }
11486 }
11488 /* Restore function stack, frame, and registers. */
11490 void
11492 {
11508 /* The FP must be valid if the frame pointer is present. */
11511 else
11517 /* We must have *some* valid pointer to the stack frame. */
11520 /* The DRAP is never valid at this point. */
11523 /* See the comment about red zone and frame
11524 pointer usage in ix86_expand_prologue. */
11531 /* Determine the CFA offset of the end of the red-zone. */
11534 {
11535 /* The red-zone begins below the return address. */
11538 /* When the register save area is in the aligned portion of
11539 the stack, determine the maximum runtime displacement that
11540 matches up with the aligned frame. */
11544 }
11546 /* Special care must be taken for the normal return case of a function
11547 using eh_return: the eax and edx registers are marked as saved, but
11548 not restored along this path. Adjust the save location to match. */
11552 /* EH_RETURN requires the use of moves to function properly. */
11555 /* SEH requires the use of pops to identify the epilogue. */
11558 /* If we're only restoring one register and sp is not valid then
11559 using a move instruction to restore the register since it's
11560 less work than reloading sp and popping the register. */
11573 && TARGET_USE_LEAVE
11577 else
11581 {
11582 /* Ensure that the entire register save area is addressable via
11583 the stack pointer, if we will restore via sp. */
11588 {
11592 style,
11594 }
11595 }
11597 /* If there are any SSE registers to restore, then we have to do it
11598 via moves, since there's obviously no pop for SSE regs. */
11604 {
11605 rtx t;
11610 /* eh_return epilogues need %ecx added to the stack pointer. */
11612 {
11615 /* Stack align doesn't work with eh_return. */
11617 /* Neither does regparm nested functions. */
11621 {
11629 /* Note that we use SA as a temporary CFA, as the return
11630 address is at the proper place relative to it. We
11631 pretend this happens at the FP restore insn because
11632 prior to this insn the FP would be stored at the wrong
11633 offset relative to SA, and after this insn we have no
11634 other reasonable register to use for the CFA. We don't
11635 bother resetting the CFA to the SP for the duration of
11636 the return insn. */
11649 }
11650 else
11651 {
11659 {
11663 UNITS_PER_WORD));
11665 }
11666 }
11669 }
11670 }
11671 else
11672 {
11673 /* SEH requires that the function end with (1) a stack adjustment
11674 if necessary, (2) a sequence of pops, and (3) a return or
11675 jump instruction. Prevent insns from the function body from
11676 being scheduled into this sequence. */
11678 {
11679 /* Prevent a catch region from being adjacent to the standard
11680 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11681 several other flags that would be interesting to test are
11682 not yet set up. */
11685 else
11687 }
11689 /* First step is to deallocate the stack frame so that we can
11690 pop the registers. Also do it on SEH target for very large
11691 frame as the emitted instructions aren't allowed by the ABI in
11692 epilogues. */
11694 || (TARGET_SEH
11697 {
11702 }
11704 {
11708 style,
11710 }
11713 }
11715 /* If we used a stack pointer and haven't already got rid of it,
11716 then do so now. */
11718 {
11719 /* If the stack pointer is valid and pointing at the frame
11720 pointer store address, then we only need a pop. */
11723 /* Leave results in shorter dependency chains on CPUs that are
11724 able to grok it fast. */
11726 && (TARGET_USE_LEAVE
11730 else
11731 {
11737 dest,
11740 }
11741 }
11744 {
11746 rtx insn;
11772 }
11774 /* At this point the stack pointer must be valid, and we must have
11775 restored all of the registers. We may not have deallocated the
11776 entire stack frame. We've delayed this until now because it may
11777 be possible to merge the local stack deallocation with the
11778 deallocation forced by ix86_static_chain_on_stack. */
11783 {
11787 }
11788 else
11791 /* Sibcall epilogues don't want a return instruction. */
11793 {
11796 }
11799 {
11802 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11803 address, do explicit add, and jump indirectly to the caller. */
11806 {
11808 rtx insn;
11810 /* There is no "pascal" calling convention in any 64bit ABI. */
11827 }
11828 else
11830 }
11831 else
11834 /* Restore the state back to the state from the prologue,
11835 so that it's correct for the next epilogue. */
11837 }
11840 /* True if the current function should be patched with nops at prologue and
11841 returns. */
11846 {
11849 }
11851 /* Return true if we patch the current function. By default a function
11852 is patched if it has loops or if the number of insns is greater than
11853 patch_functions_min_instructions (number of insns roughly translates
11854 to number of instructions). */
11856 static bool
11858 {
11860 rtx insn;
11866 /* If a function has an attribute forcing patching on or off, do as it
11867 indicates. */
11873 /* Patch the function if it has at least a loop. */
11875 {
11877 {
11880 /* FIXME - Deallocating the loop causes a seg-fault. */
11881 #if 0
11883 #endif
11884 /* We are not concerned with the function body as a loop. */
11887 }
11888 }
11890 /* Else, check if function has more than patch_functions_min_instrctions. */
11892 /* Borrowed this code from rest_of_handle_final() in final.c. */
11895 func_name &&
11899 min_functions_instructions =
11902 {
11903 /* Calculate the number of instructions in this function and only emit
11904 function patch for instrumentation if it is greater than
11905 patch_functions_min_instructions. */
11907 {
11910 }
11913 }
11916 }
11918 /* Emit the 11-byte patch space for the function prologue for functions that
11919 qualify. */
11921 static void
11923 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11924 {
11925 /* Only for 64-bit target. */
11927 {
11929 /* Emit the instruction 'jmp 09' followed by 9 bytes to make it 11-bytes
11930 of nop. */
11932 file,
11933 FUNCTION_PATCH_PROLOGUE_SECTION,
11936 }
11937 }
11939 /* Emit the nop bytes at function prologue or return (including tail call
11940 jumps). The number of nop bytes generated is at least 8.
11941 Also emits a section named SECTION_NAME, which is a backpointer section
11942 holding the addresses of the nop bytes in the text section.
11943 SECTION_NAME is either '_function_patch_prologue' or
11944 '_function_patch_epilogue'. The backpointer section can be used to navigate
11945 through all the function entry and exit points which are patched with nops.
11946 PRE_INSTRUCTIONS are the instructions, if any, at the start of the nop byte
11947 sequence. NUM_REMAINING_NOPS are the number of nop bytes to fill,
11948 excluding the number of bytes in PRE_INSTRUCTIONS.
11949 Returns true if the function was patched, false otherwise. */
11951 bool
11956 {
11976 /* Align the start of nops to 2-byte boundary so that the 2-byte jump
11977 instruction can be patched atomically at run time. */
11980 /* Emit nop bytes. They look like the following:
11981 $LFPEL0:
11982 <pre_instruction>
11983 0x90 (repeated num_actual_nops times)
11984 .quad $LFPESL0 - .
11985 followed by section 'section_name' which contains the address
11986 of instruction at 'label'.
11987 */
11996 /* Output "section_label - ." for the relative address of the entry in
11997 the section 'section_name'. */
12002 /* Emit the backpointer section. For functions belonging to comdat group,
12003 we emit a different section named '<section_name>.foo' where 'foo' is
12004 the name of the comdat section. This section is later renamed to
12005 '<section_name>' by ix86_elf_asm_named_section().
12006 We emit a unique section name for the back pointer section for comdat
12007 functions because otherwise the 'get_section' call may return an existing
12008 non-comdat section with the same name, leading to references from
12009 non-comdat section to comdat functions.
12010 */
12013 HAVE_COMDAT_GROUP)
12014 {
12015 decl_section_name =
12022 }
12024 {
12027 {
12031 func_name);
12033 }
12034 }
12037 /* Align the section to 8-byte boundary. */
12040 /* Emit address of the start of nop bytes in the section:
12041 $LFPESP0:
12042 .quad $LFPEL0
12043 */
12049 /* Switching back to text section. */
12052 }
12054 /* Strips the characters after '_function_patch_prologue' or
12055 '_function_patch_epilogue' and emits the section. */
12057 static void
12059 tree decl)
12060 {
12063 {
12075 }
12077 }
12079 /* Reset from the function's potential modifications. */
12081 static void
12083 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12084 {
12087 #if TARGET_MACHO
12088 /* Mach-O doesn't support labels at the end of objects, so if
12089 it looks like we might want one, insert a NOP. */
12090 {
12096 {
12097 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12098 notes only, instead set their CODE_LABEL_NUMBER to -1,
12099 otherwise there would be code generation differences
12100 in between -g and -g0. */
12104 }
12114 }
12115 #endif
12117 }
12119 /* Return a scratch register to use in the split stack prologue. The
12120 split stack prologue is used for -fsplit-stack. It is the first
12121 instructions in the function, even before the regular prologue.
12122 The scratch register can be any caller-saved register which is not
12123 used for parameters or for the static chain. */
12125 static unsigned int
12127 {
12130 else
12131 {
12144 {
12146 {
12150 }
12152 }
12154 {
12158 }
12160 {
12163 else
12164 {
12166 {
12170 }
12172 }
12173 }
12174 else
12175 {
12176 /* FIXME: We could make this work by pushing a register
12177 around the addition and comparison. */
12180 }
12181 }
12182 }
12184 /* A SYMBOL_REF for the function which allocates new stackspace for
12185 -fsplit-stack. */
12189 /* A SYMBOL_REF for the more stack function when using the large
12190 model. */
12194 /* Handle -fsplit-stack. These are the first instructions in the
12195 function, even before the regular prologue. */
12197 void
12199 {
12201 HOST_WIDE_INT allocate;
12206 rtx fn;
12214 /* This is the label we will branch to if we have enough stack
12215 space. We expect the basic block reordering pass to reverse this
12216 branch if optimizing, so that we branch in the unlikely case. */
12219 /* We need to compare the stack pointer minus the frame size with
12220 the stack boundary in the TCB. The stack boundary always gives
12221 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12222 can compare directly. Otherwise we need to do an addition. */
12225 UNSPEC_STACK_CHECK);
12230 else
12231 {
12233 rtx offset;
12235 /* We need a scratch register to hold the stack pointer minus
12236 the required frame size. Since this is the very start of the
12237 function, the scratch register can be any caller-saved
12238 register which is not used for parameters. */
12245 {
12246 /* We don't use ix86_gen_add3 in this case because it will
12247 want to split to lea, but when not optimizing the insn
12248 will not be split after this point. */
12251 offset)));
12252 }
12253 else
12254 {
12257 stack_pointer_rtx));
12258 }
12260 }
12266 /* Mark the jump as very likely to be taken. */
12274 /* Get more stack space. We pass in the desired stack space and the
12275 size of the arguments to copy to the new stack. In 32-bit mode
12276 we push the parameters; __morestack will return on a new stack
12277 anyhow. In 64-bit mode we pass the parameters in r10 and
12278 r11. */
12283 {
12289 /* If this function uses a static chain, it will be in %r10.
12290 Preserve it across the call to __morestack. */
12292 {
12293 rtx rax;
12298 }
12302 {
12303 HOST_WIDE_INT argval;
12306 /* When using the large model we need to load the address
12307 into a register, and we've run out of registers. So we
12308 switch to a different calling convention, and we call a
12309 different function: __morestack_large. We pass the
12310 argument size in the upper 32 bits of r10 and pass the
12311 frame size in the lower 32 bits. */
12316 split_stack_fn_large =
12320 {
12330 UNSPEC_GOT);
12336 }
12337 else
12344 }
12345 else
12346 {
12350 }
12353 }
12354 else
12355 {
12358 }
12364 /* In order to make call/return prediction work right, we now need
12365 to execute a return instruction. See
12366 libgcc/config/i386/morestack.S for the details on how this works.
12368 For flow purposes gcc must not see this as a return
12369 instruction--we need control flow to continue at the subsequent
12370 label. Therefore, we use an unspec. */
12374 /* If we are in 64-bit mode and this function uses a static chain,
12375 we saved %r10 in %rax before calling _morestack. */
12380 /* If this function calls va_start, we need to store a pointer to
12381 the arguments on the old stack, because they may not have been
12382 all copied to the new stack. At this point the old stack can be
12383 found at the frame pointer value used by __morestack, because
12384 __morestack has set that up before calling back to us. Here we
12385 store that pointer in a scratch register, and in
12386 ix86_expand_prologue we store the scratch register in a stack
12387 slot. */
12389 {
12391 rtx frame_reg;
12398 /* 64-bit:
12399 fp -> old fp value
12400 return address within this function
12401 return address of caller of this function
12402 stack arguments
12403 So we add three words to get to the stack arguments.
12405 32-bit:
12406 fp -> old fp value
12407 return address within this function
12408 first argument to __morestack
12409 second argument to __morestack
12410 return address of caller of this function
12411 stack arguments
12412 So we add five words to get to the stack arguments.
12413 */
12424 }
12429 /* If this function calls va_start, we now have to set the scratch
12430 register for the case where we do not call __morestack. In this
12431 case we need to set it based on the stack pointer. */
12433 {
12440 }
12441 }
12443 /* We may have to tell the dataflow pass that the split stack prologue
12444 is initializing a scratch register. */
12446 static void
12448 {
12450 {
12453 }
12454 }
12455 \f
12456 /* Extract the parts of an RTL expression that is a valid memory address
12457 for an instruction. Return 0 if the structure of the address is
12458 grossly off. Return -1 if the address contains ASHIFT, so it is not
12459 strictly valid, but still used for computing length of lea instruction. */
12461 int
12463 {
12468 rtx tmp;
12472 /* Allow zero-extended SImode addresses,
12473 they will be emitted with addr32 prefix. */
12475 {
12478 {
12482 }
12485 {
12492 }
12493 }
12495 /* Allow SImode subregs of DImode addresses,
12496 they will be emitted with addr32 prefix. */
12498 {
12501 {
12505 }
12506 }
12511 {
12514 else
12516 }
12518 {
12523 do
12524 {
12529 }
12536 {
12539 {
12564 /* FALLTHRU */
12568 && TARGET_TLS_DIRECT_SEG_REFS
12571 else
12578 /* FALLTHRU */
12585 else
12600 }
12601 }
12602 }
12604 {
12607 }
12609 {
12610 /* We're called for lea too, which implements ashift on occasion. */
12620 }
12621 else
12625 {
12627 ;
12630 ;
12631 else
12633 }
12635 /* Extract the integral value of scale. */
12637 {
12641 }
12646 /* Avoid useless 0 displacement. */
12650 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12655 {
12656 rtx tmp;
12659 }
12661 /* Special case: %ebp cannot be encoded as a base without a displacement.
12662 Similarly %r13. */
12664 && base_reg
12673 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12674 Avoid this by transforming to [%esi+0].
12675 Reload calls address legitimization without cfun defined, so we need
12676 to test cfun for being non-NULL. */
12682 /* Special case: encode reg+reg instead of reg*2. */
12686 /* Special case: scaling cannot be encoded without base or displacement. */
12697 }
12698 \f
12699 /* Return cost of the memory address x.
12700 For i386, it is better to use a complex address than let gcc copy
12701 the address into a reg and make a new pseudo. But not if the address
12702 requires to two regs - that would mean more pseudos with longer
12703 lifetimes. */
12704 static int
12706 addr_space_t as ATTRIBUTE_UNUSED,
12708 {
12720 /* Attempt to minimize number of registers in the address. */
12726 cost++;
12733 cost++;
12735 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12736 since it's predecode logic can't detect the length of instructions
12737 and it degenerates to vector decoded. Increase cost of such
12738 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12739 to split such addresses or even refuse such addresses at all.
12741 Following addressing modes are affected:
12742 [base+scale*index]
12743 [scale*index+disp]
12744 [base+index]
12746 The first and last case may be avoidable by explicitly coding the zero in
12747 memory address, but I don't have AMD-K6 machine handy to check this
12748 theory. */
12757 }
12758 \f
12759 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12760 this is used for to form addresses to local data when -fPIC is in
12761 use. */
12763 static bool
12765 {
12768 }
12770 /* Determine if a given RTX is a valid constant. We already know this
12771 satisfies CONSTANT_P. */
12773 static bool
12775 {
12777 {
12782 {
12786 }
12791 /* Only some unspecs are valid as "constants". */
12794 {
12810 }
12812 /* We must have drilled down to a symbol. */
12817 /* FALLTHRU */
12820 /* TLS symbols are never valid. */
12824 /* DLLIMPORT symbols are never valid. */
12829 #if TARGET_MACHO
12830 /* mdynamic-no-pic */
12833 #endif
12849 }
12851 /* Otherwise we handle everything else in the move patterns. */
12853 }
12855 /* Determine if it's legal to put X into the constant pool. This
12856 is not possible for the address of thread-local symbols, which
12857 is checked above. */
12859 static bool
12861 {
12862 /* We can always put integral constants and vectors in memory. */
12864 {
12872 }
12874 }
12876 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12877 otherwise zero. */
12879 static bool
12881 {
12887 }
12890 /* Nonzero if the constant value X is a legitimate general operand
12891 when generating PIC code. It is given that flag_pic is on and
12892 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12894 bool
12896 {
12897 rtx inner;
12900 {
12907 /* Only some unspecs are valid as "constants". */
12910 {
12923 }
12924 /* FALLTHRU */
12932 }
12933 }
12935 /* Determine if a given CONST RTX is a valid memory displacement
12936 in PIC mode. */
12938 bool
12940 {
12943 /* In 64bit mode we can allow direct addresses of symbols and labels
12944 when they are not dynamic symbols. */
12946 {
12950 {
12974 /* FALLTHRU */
12977 /* TLS references should always be enclosed in UNSPEC.
12978 The dllimported symbol needs always to be resolved. */
12984 {
12992 /* Function-symbols need to be resolved only for
12993 large-model.
12994 For the small-model we don't need to resolve anything
12995 here. */
13000 /* Non-external symbols don't need to be resolved for
13001 large, and medium-model. */
13006 }
13009 || (HAVE_LD_PIE_COPYRELOC
13010 && flag_pie
13012 /* TODO:Temporary fix for weak defined symbols. Weak defined
13013 symbols in an executable cannot be overridden even with
13014 a non-weak symbol in a shared library.
13015 Revert after fix is checked in here:
13016 http://gcc.gnu.org/ml/gcc-patches/2015-02/msg00366.html*/
13025 }
13026 }
13032 {
13033 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13034 of GOT tables. We should not need these anyway. */
13046 }
13050 {
13055 }
13064 {
13068 /* We need to check for both symbols and labels because VxWorks loads
13069 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13070 details. */
13074 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13075 While ABI specify also 32bit relocation but we don't produce it in
13076 small PIC model at all. */
13098 }
13101 }
13103 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13104 replace the input X, or the original X if no replacement is called for.
13105 The output parameter *WIN is 1 if the calling macro should goto WIN,
13106 0 if it should not. */
13108 bool
13113 {
13114 /* Reload can generate:
13116 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13117 (reg:DI 97))
13118 (reg:DI 2 cx))
13120 This RTX is rejected from ix86_legitimate_address_p due to
13121 non-strictness of base register 97. Following this rejection,
13122 reload pushes all three components into separate registers,
13123 creating invalid memory address RTX.
13125 Following code reloads only the invalid part of the
13126 memory address RTX. */
13132 {
13138 {
13143 }
13147 {
13152 }
13156 }
13159 }
13161 /* Determine if op is suitable RTX for an address register.
13162 Return naked register if a register or a register subreg is
13163 found, otherwise return NULL_RTX. */
13165 static rtx
13167 {
13170 /* Only SImode or DImode registers can form the address. */
13177 {
13185 /* Don't allow SUBREGs that span more than a word. It can
13186 lead to spill failures when the register is one word out
13187 of a two word structure. */
13191 /* Allow only SUBREGs of non-eliminable hard registers. */
13194 }
13196 /* Op is not a register. */
13198 }
13200 /* Recognizes RTL expressions that are valid memory addresses for an
13201 instruction. The MODE argument is the machine mode for the MEM
13202 expression that wants to use this address.
13204 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13205 convert common non-canonical forms to canonical form so that they will
13206 be recognized. */
13208 static bool
13211 {
13214 HOST_WIDE_INT scale;
13218 /* Decomposition failed. */
13227 /* Validate base register. */
13229 {
13237 /* Base is not valid. */
13239 }
13241 /* Validate index register. */
13243 {
13251 /* Index is not valid. */
13253 }
13255 /* Index and base should have the same mode. */
13260 /* Address override works only on the (%reg) part of %fs:(%reg). */
13266 /* Validate scale factor. */
13268 {
13270 /* Scale without index. */
13274 /* Scale is not a valid multiplier. */
13276 }
13278 /* Validate displacement. */
13280 {
13285 {
13286 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13287 used. While ABI specify also 32bit relocations, we don't produce
13288 them at all and use IP relative instead. */
13295 /* 64bit address unspec. */
13315 /* Invalid address unspec. */
13317 }
13320 && (flag_pic
13321 || (TARGET_MACHO
13322 #if TARGET_MACHO
13323 && MACHOPIC_INDIRECT
13325 #endif
13326 )))
13327 {
13329 is_legitimate_pic:
13331 {
13332 /* foo@dtpoff(%rX) is ok. */
13339 /* Non-constant pic memory reference. */
13341 }
13344 /* Displacement is an invalid pic construct. */
13346 #if TARGET_MACHO
13349 /* displacment must be referenced via non_lazy_pointer */
13351 #endif
13353 /* This code used to verify that a symbolic pic displacement
13354 includes the pic_offset_table_rtx register.
13356 While this is good idea, unfortunately these constructs may
13357 be created by "adds using lea" optimization for incorrect
13358 code like:
13360 int a;
13361 int foo(int i)
13362 {
13363 return *(&a+i);
13364 }
13366 This code is nonsensical, but results in addressing
13367 GOT table with pic_offset_table_rtx base. We can't
13368 just refuse it easily, since it gets matched by
13369 "addsi3" pattern, that later gets split to lea in the
13370 case output register differs from input. While this
13371 can be handled by separate addsi pattern for this case
13372 that never results in lea, this seems to be easier and
13373 correct fix for crash to disable this test. */
13374 }
13381 /* Displacement is not constant. */
13385 /* Displacement is out of range. */
13387 /* In x32 mode, constant addresses are sign extended to 64bit, so
13388 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13393 }
13395 /* Everything looks valid. */
13397 }
13399 /* Determine if a given RTX is a valid constant address. */
13401 bool
13403 {
13405 }
13406 \f
13407 /* Return a unique alias set for the GOT. */
13409 static alias_set_type
13411 {
13416 }
13418 /* Return a legitimate reference for ORIG (an address) using the
13419 register REG. If REG is 0, a new pseudo is generated.
13421 There are two types of references that must be handled:
13423 1. Global data references must load the address from the GOT, via
13424 the PIC reg. An insn is emitted to do this load, and the reg is
13425 returned.
13427 2. Static data references, constant pool addresses, and code labels
13428 compute the address as an offset from the GOT, whose base is in
13429 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13430 differentiate them from global data objects. The returned
13431 address is the PIC reg + an unspec constant.
13433 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13434 reg also appears in the address. */
13436 static rtx
13438 {
13442 #if TARGET_MACHO
13444 {
13447 /* Use the generic Mach-O PIC machinery. */
13449 }
13450 #endif
13453 {
13457 }
13463 {
13464 rtx tmpreg;
13465 /* This symbol may be referenced via a displacement from the PIC
13466 base address (@GOTOFF). */
13473 {
13475 UNSPEC_GOTOFF);
13477 }
13478 else
13483 else
13488 {
13492 }
13493 else
13495 }
13497 {
13498 /* This symbol may be referenced via a displacement from the PIC
13499 base address (@GOTOFF). */
13506 {
13508 UNSPEC_GOTOFF);
13510 }
13511 else
13517 {
13520 }
13521 }
13523 /* We can't use @GOTOFF for text labels on VxWorks;
13524 see gotoff_operand. */
13526 {
13531 /* For x64 PE-COFF there is no GOT table. So we use address
13532 directly. */
13534 {
13542 }
13544 {
13552 /* Use directly gen_movsi, otherwise the address is loaded
13553 into register for CSE. We don't want to CSE this addresses,
13554 instead we CSE addresses from the GOT table, so skip this. */
13557 }
13558 else
13559 {
13560 /* This symbol must be referenced via a load from the
13561 Global Offset Table (@GOT). */
13577 }
13578 }
13579 else
13580 {
13583 {
13585 {
13588 }
13589 else
13591 }
13593 {
13596 /* We must match stuff we generate before. Assume the only
13597 unspecs that can get here are ours. Not that we could do
13598 anything with them anyway.... */
13604 }
13606 {
13609 /* Check first to see if this is a constant offset from a @GOTOFF
13610 symbol reference. */
13613 {
13615 {
13619 UNSPEC_GOTOFF);
13625 {
13628 }
13629 }
13630 else
13631 {
13634 {
13638 }
13639 }
13640 }
13641 else
13642 {
13645 new_rtx
13649 {
13652 {
13655 new_rtx
13657 }
13658 else
13660 }
13661 else
13662 {
13665 {
13668 }
13670 }
13671 }
13672 }
13673 }
13675 }
13676 \f
13677 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13679 static rtx
13681 {
13685 {
13690 }
13696 }
13698 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13702 static rtx
13704 {
13706 {
13712 }
13715 {
13717 UNSPEC_PLTOFF);
13720 }
13723 }
13725 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13729 rtx
13731 {
13733 {
13734 ix86_tls_module_base_symbol
13739 }
13742 }
13744 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13745 false if we expect this to be used for a memory address and true if
13746 we expect to load the address into a register. */
13748 static rtx
13750 {
13756 /* Fall back to global dynamic model if tool chain cannot support local
13757 dynamic. */
13764 {
13769 {
13772 else
13773 {
13776 }
13777 }
13780 {
13783 else
13793 }
13794 else
13795 {
13799 {
13801 rtx insns;
13804 emit_call_insn
13814 }
13815 else
13817 }
13824 {
13827 else
13828 {
13831 }
13832 }
13835 {
13840 else
13846 }
13847 else
13848 {
13852 {
13857 emit_call_insn
13862 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13863 share the LD_BASE result with other LD model accesses. */
13865 UNSPEC_TLS_LD_BASE);
13869 }
13870 else
13872 }
13880 {
13887 }
13892 {
13894 {
13895 /* The Sun linker took the AMD64 TLS spec literally
13896 and can only handle %rax as destination of the
13897 initial executable code sequence. */
13902 }
13904 /* Generate DImode references to avoid %fs:(%reg32)
13905 problems and linker IE->LE relaxation bug. */
13909 }
13911 {
13916 }
13918 {
13922 }
13923 else
13924 {
13927 }
13937 {
13942 }
13943 else
13944 {
13948 }
13958 {
13962 }
13963 else
13964 {
13968 }
13973 }
13976 }
13978 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13979 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13980 unique refptr-DECL symbol corresponding to symbol DECL. */
13983 htab_t dllimport_map;
13985 static tree
13987 {
13994 tree to;
13995 rtx rtl;
14022 else
14035 {
14037 #ifdef SUB_TARGET_RECORD_STUB
14039 #endif
14040 }
14049 }
14051 /* Expand SYMBOL into its corresponding far-addresse symbol.
14052 WANT_REG is true if we require the result be a register. */
14054 static rtx
14056 {
14057 tree imp_decl;
14058 rtx x;
14067 }
14069 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14070 true if we require the result be a register. */
14072 static rtx
14074 {
14075 tree imp_decl;
14076 rtx x;
14085 }
14087 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14088 is true if we require the result be a register. */
14090 static rtx
14092 {
14097 {
14104 {
14107 }
14108 }
14124 {
14127 }
14129 }
14131 /* Try machine-dependent ways of modifying an illegitimate address
14132 to be legitimate. If we find one, return the new, valid address.
14133 This macro is used in only one place: `memory_address' in explow.c.
14135 OLDX is the address as it was before break_out_memory_refs was called.
14136 In some cases it is useful to look at this to decide what needs to be done.
14138 It is always safe for this macro to do nothing. It exists to recognize
14139 opportunities to optimize the output.
14141 For the 80386, we handle X+REG by loading X into a register R and
14142 using R+REG. R will go in a general reg and indexing will be used.
14143 However, if REG is a broken-out memory address or multiplication,
14144 nothing needs to be done because REG can certainly go in a general reg.
14146 When -fpic is used, special handling is needed for symbolic references.
14147 See comments by legitimize_pic_address in i386.c for details. */
14149 static rtx
14152 {
14163 {
14167 }
14170 {
14174 }
14179 #if TARGET_MACHO
14182 #endif
14184 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14188 {
14193 }
14196 {
14197 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14202 {
14208 }
14213 {
14219 }
14221 /* Put multiply first if it isn't already. */
14223 {
14228 }
14230 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14231 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14232 created by virtual register instantiation, register elimination, and
14233 similar optimizations. */
14235 {
14241 }
14243 /* Canonicalize
14244 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14245 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14250 {
14251 rtx constant;
14255 {
14258 }
14260 {
14263 }
14264 else
14268 {
14275 }
14276 }
14282 {
14285 }
14288 {
14291 }
14299 {
14302 }
14308 {
14312 {
14315 }
14319 }
14322 {
14326 {
14329 }
14333 }
14334 }
14337 }
14338 \f
14339 /* Print an integer constant expression in assembler syntax. Addition
14340 and subtraction are the only arithmetic that may appear in these
14341 expressions. FILE is the stdio stream to write to, X is the rtx, and
14342 CODE is the operand print code from the output string. */
14344 static void
14346 {
14350 {
14359 else
14360 {
14363 /* Mark the decl as referenced so that cgraph will
14364 output the function. */
14368 #if TARGET_MACHO
14372 #endif
14374 }
14382 /* FALLTHRU */
14393 /* This used to output parentheses around the expression,
14394 but that does not work on the 386 (either ATT or BSD assembler). */
14400 {
14401 /* We can use %d if the number is <32 bits and positive. */
14406 else
14408 }
14409 else
14410 /* We can't handle floating point constants;
14411 TARGET_PRINT_OPERAND must handle them. */
14416 /* Some assemblers need integer constants to appear first. */
14418 {
14422 }
14423 else
14424 {
14429 }
14444 {
14448 }
14453 {
14472 /* FIXME: This might be @TPOFF in Sun ld too. */
14481 else
14491 else
14497 #if TARGET_MACHO
14502 #endif
14506 }
14511 }
14512 }
14514 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14515 We need to emit DTP-relative relocations. */
14517 static void ATTRIBUTE_UNUSED
14519 {
14524 {
14532 }
14533 }
14535 /* Return true if X is a representation of the PIC register. This copes
14536 with calls from ix86_find_base_term, where the register might have
14537 been replaced by a cselib value. */
14539 static bool
14541 {
14545 else
14547 }
14549 /* Helper function for ix86_delegitimize_address.
14550 Attempt to delegitimize TLS local-exec accesses. */
14552 static rtx
14554 {
14579 {
14584 }
14590 }
14592 /* In the name of slightly smaller debug output, and to cater to
14593 general assembler lossage, recognize PIC+GOTOFF and turn it back
14594 into a direct symbol reference.
14596 On Darwin, this is necessary to avoid a crash, because Darwin
14597 has a different PIC label for each routine but the DWARF debugging
14598 information is not associated with any particular routine, so it's
14599 necessary to remove references to the PIC label from RTL stored by
14600 the DWARF output code. */
14602 static rtx
14604 {
14606 /* addend is NULL or some rtx if x is something+GOTOFF where
14607 something doesn't include the PIC register. */
14609 /* reg_addend is NULL or a multiple of some register. */
14611 /* const_addend is NULL or a const_int. */
14613 /* This is the result, or NULL. */
14622 {
14629 {
14635 }
14642 {
14645 {
14650 }
14652 }
14657 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14658 and -mcmodel=medium -fpic. */
14659 }
14666 /* %ebx + GOT/GOTOFF */
14667 ;
14669 {
14670 /* %ebx + %reg * scale + GOT/GOTOFF */
14676 else
14677 {
14680 }
14681 }
14682 else
14688 {
14691 }
14712 {
14713 /* If the rest of original X doesn't involve the PIC register, add
14714 addend and subtract pic_offset_table_rtx. This can happen e.g.
14715 for code like:
14716 leal (%ebx, %ecx, 4), %ecx
14717 ...
14718 movl foo@GOTOFF(%ecx), %edx
14719 in which case we return (%ecx - %ebx) + foo. */
14722 pic_offset_table_rtx),
14723 result);
14724 else
14726 }
14728 {
14732 }
14734 }
14736 /* If X is a machine specific address (i.e. a symbol or label being
14737 referenced as a displacement from the GOT implemented using an
14738 UNSPEC), then return the base term. Otherwise return X. */
14740 rtx
14742 {
14743 rtx term;
14746 {
14760 }
14763 }
14764 \f
14765 static void
14768 {
14772 {
14775 }
14780 {
14783 {
14802 }
14806 {
14825 }
14832 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14833 Those same assemblers have the same but opposite lossage on cmov. */
14836 else
14841 {
14854 }
14861 else
14866 {
14879 }
14886 else
14896 else
14907 }
14909 }
14911 /* Print the name of register X to FILE based on its machine mode and number.
14912 If CODE is 'w', pretend the mode is HImode.
14913 If CODE is 'b', pretend the mode is QImode.
14914 If CODE is 'k', pretend the mode is SImode.
14915 If CODE is 'q', pretend the mode is DImode.
14916 If CODE is 'x', pretend the mode is V4SFmode.
14917 If CODE is 't', pretend the mode is V8SFmode.
14918 If CODE is 'g', pretend the mode is V16SFmode.
14919 If CODE is 'h', pretend the reg is the 'high' byte register.
14920 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14921 If CODE is 'd', duplicate the operand for AVX instruction.
14922 */
14924 void
14926 {
14935 {
14939 }
14966 else
14969 /* Irritatingly, AMD extended registers use different naming convention
14970 from the normal registers: "r%d[bwd]" */
14972 {
14977 {
14991 /* no suffix */
14996 }
14998 }
15002 {
15005 {
15008 }
15009 /* FALLTHRU */
15015 /* FALLTHRU */
15018 normal:
15033 {
15038 }
15041 {
15046 }
15050 }
15054 {
15057 else
15059 }
15060 }
15062 /* Locate some local-dynamic symbol still in use by this function
15063 so that we can print its name in some tls_local_dynamic_base
15064 pattern. */
15066 static int
15068 {
15073 {
15076 }
15079 }
15083 {
15084 rtx insn;
15095 }
15097 /* Meaning of CODE:
15098 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15099 C -- print opcode suffix for set/cmov insn.
15100 c -- like C, but print reversed condition
15101 F,f -- likewise, but for floating-point.
15102 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15103 otherwise nothing
15104 R -- print embeded rounding and sae.
15105 r -- print only sae.
15106 z -- print the opcode suffix for the size of the current operand.
15107 Z -- likewise, with special suffixes for x87 instructions.
15108 * -- print a star (in certain assembler syntax)
15109 A -- print an absolute memory reference.
15110 E -- print address with DImode register names if TARGET_64BIT.
15111 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15112 s -- print a shift double count, followed by the assemblers argument
15113 delimiter.
15114 b -- print the QImode name of the register for the indicated operand.
15115 %b0 would print %al if operands[0] is reg 0.
15116 w -- likewise, print the HImode name of the register.
15117 k -- likewise, print the SImode name of the register.
15118 q -- likewise, print the DImode name of the register.
15119 x -- likewise, print the V4SFmode name of the register.
15120 t -- likewise, print the V8SFmode name of the register.
15121 g -- likewise, print the V16SFmode name of the register.
15122 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15123 y -- print "st(0)" instead of "st" as a register.
15124 d -- print duplicated register operand for AVX instruction.
15125 D -- print condition for SSE cmp instruction.
15126 P -- if PIC, print an @PLT suffix.
15127 p -- print raw symbol name.
15128 X -- don't print any sort of PIC '@' suffix for a symbol.
15129 & -- print some in-use local-dynamic symbol name.
15130 H -- print a memory address offset by 8; used for sse high-parts
15131 Y -- print condition for XOP pcom* instruction.
15132 + -- print a branch hint as 'cs' or 'ds' prefix
15133 ; -- print a semicolon (after prefixes due to bug in older gas).
15134 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15135 @ -- print a segment register of thread base pointer load
15136 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15137 */
15139 void
15141 {
15143 {
15145 {
15148 {
15154 /* Intel syntax. For absolute addresses, registers should not
15155 be surrounded by braces. */
15157 {
15162 }
15167 }
15173 /* Wrap address in an UNSPEC to declare special handling. */
15211 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15216 {
15230 output_operand_lossage
15233 }
15236 #endif
15241 {
15242 /* Opcodes don't get size suffixes if using Intel opcodes. */
15247 {
15265 output_operand_lossage
15268 }
15269 }
15272 warning
15274 /* FALLTHRU */
15277 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15282 {
15284 {
15286 #ifdef HAVE_AS_IX86_FILDS
15288 #endif
15296 #ifdef HAVE_AS_IX86_FILDQ
15298 #else
15300 #endif
15305 }
15306 }
15308 {
15309 /* 387 opcodes don't get size suffixes
15310 if the operands are registers. */
15315 {
15331 }
15332 }
15333 else
15334 {
15335 output_operand_lossage
15338 }
15340 output_operand_lossage
15361 {
15364 }
15369 {
15420 }
15424 /* Little bit of braindamage here. The SSE compare instructions
15425 does use completely different names for the comparisons that the
15426 fp conditional moves. */
15428 {
15431 {
15434 }
15440 {
15443 }
15449 {
15452 }
15461 {
15464 }
15470 {
15473 }
15479 {
15482 }
15493 }
15498 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15501 #endif
15506 {
15510 }
15514 file);
15519 {
15523 }
15524 /* It doesn't actually matter what mode we use here, as we're
15525 only going to use this for printing. */
15527 /* Output 'qword ptr' for intel assembler dialect. */
15536 #ifdef HAVE_AS_IX86_HLE
15538 #else
15540 #endif
15542 #ifdef HAVE_AS_IX86_HLE
15544 #else
15546 #endif
15547 /* We do not want to print value of the operand. */
15576 {
15591 }
15604 {
15609 else
15612 }
15615 {
15616 rtx x;
15625 {
15630 {
15632 bool cputaken
15635 /* Emit hints only in the case default branch prediction
15636 heuristics would fail. */
15638 {
15639 /* We use 3e (DS) prefix for taken branches and
15640 2e (CS) prefix for not taken branches. */
15643 else
15645 }
15646 }
15647 }
15649 }
15652 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15654 #endif
15661 /* The kernel uses a different segment register for performance
15662 reasons; a system call would not have to trash the userspace
15663 segment register, which would be expensive. */
15666 else
15681 }
15682 }
15688 {
15689 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15692 {
15695 {
15704 else
15711 }
15713 /* Check for explicit size override (codes 'b', 'w', 'k',
15714 'q' and 'x') */
15728 }
15731 /* Avoid (%rip) for call operands. */
15737 else
15739 }
15742 {
15743 REAL_VALUE_TYPE r;
15751 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15755 else
15757 }
15760 {
15761 REAL_VALUE_TYPE r;
15770 }
15772 /* These float cases don't actually occur as immediate operands. */
15774 {
15779 }
15781 else
15782 {
15783 /* We have patterns that allow zero sets of memory, for instance.
15784 In 64-bit mode, we should probably support all 8-byte vectors,
15785 since we can in fact encode that into an immediate. */
15787 {
15790 }
15793 {
15795 {
15798 }
15801 {
15804 else
15806 }
15807 }
15812 else
15814 }
15815 }
15817 static bool
15819 {
15822 }
15823 \f
15824 /* Print a memory operand whose address is ADDR. */
15826 static void
15828 {
15837 {
15844 }
15846 {
15850 }
15851 else
15862 {
15873 }
15875 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15877 {
15889 }
15891 {
15892 /* Displacement only requires special attention. */
15895 {
15899 }
15902 else
15904 }
15905 else
15906 {
15907 /* Print SImode register names to force addr32 prefix. */
15909 {
15910 #ifdef ENABLE_CHECKING
15913 {
15924 }
15925 #endif
15928 }
15930 && TARGET_X32
15931 && disp
15934 {
15935 /* X32 runs in 64-bit mode, where displacement, DISP, in
15936 address DISP(%r64), is encoded as 32-bit immediate sign-
15937 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15938 address is %r64 + 0xffffffffbffffd00. When %r64 <
15939 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15940 which is invalid for x32. The correct address is %r64
15941 - 0x40000300 == 0xf7ffdd64. To properly encode
15942 -0x40000300(%r64) for x32, we zero-extend negative
15943 displacement by forcing addr32 prefix which truncates
15944 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15945 zero-extend all negative displacements, including -1(%rsp).
15946 However, for small negative displacements, sign-extension
15947 won't cause overflow. We only zero-extend negative
15948 displacements if they < -16*1024*1024, which is also used
15949 to check legitimate address displacements for PIC. */
15951 }
15954 {
15956 {
15961 else
15963 }
15969 {
15974 }
15976 }
15977 else
15978 {
15982 {
15983 /* Pull out the offset of a symbol; print any symbol itself. */
15987 {
15991 }
15999 else
16001 }
16005 {
16008 {
16012 }
16013 }
16016 else
16020 {
16025 }
16027 }
16028 }
16029 }
16031 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16033 static bool
16035 {
16036 rtx op;
16043 {
16046 /* FIXME: This might be @TPOFF in Sun ld. */
16057 else
16069 else
16076 #if TARGET_MACHO
16082 #endif
16085 {
16090 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16092 #else
16094 #endif
16097 }
16102 }
16105 }
16106 \f
16107 /* Split one or more double-mode RTL references into pairs of half-mode
16108 references. The RTL can be REG, offsettable MEM, integer constant, or
16109 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16110 split and "num" is its length. lo_half and hi_half are output arrays
16111 that parallel "operands". */
16113 void
16116 {
16121 {
16130 }
16135 {
16138 /* simplify_subreg refuse to split volatile memory addresses,
16139 but we still have to handle it. */
16141 {
16144 }
16145 else
16146 {
16153 }
16154 }
16155 }
16156 \f
16157 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16158 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16159 is the expression of the binary operation. The output may either be
16160 emitted here, or returned to the caller, like all output_* functions.
16162 There is no guarantee that the operands are the same mode, as they
16163 might be within FLOAT or FLOAT_EXTEND expressions. */
16165 #ifndef SYSV386_COMPAT
16166 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16167 wants to fix the assemblers because that causes incompatibility
16168 with gcc. No-one wants to fix gcc because that causes
16169 incompatibility with assemblers... You can use the option of
16170 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16171 #define SYSV386_COMPAT 1
16172 #endif
16176 {
16182 #ifdef ENABLE_CHECKING
16183 /* Even if we do not want to check the inputs, this documents input
16184 constraints. Which helps in understanding the following code. */
16194 else
16196 #endif
16199 {
16204 else
16213 else
16222 else
16231 else
16238 }
16241 {
16243 {
16247 else
16249 }
16250 else
16251 {
16255 else
16257 }
16259 }
16263 {
16267 {
16271 }
16273 /* know operands[0] == operands[1]. */
16276 {
16279 }
16282 {
16284 /* How is it that we are storing to a dead operand[2]?
16285 Well, presumably operands[1] is dead too. We can't
16286 store the result to st(0) as st(0) gets popped on this
16287 instruction. Instead store to operands[2] (which I
16288 think has to be st(1)). st(1) will be popped later.
16289 gcc <= 2.8.1 didn't have this check and generated
16290 assembly code that the Unixware assembler rejected. */
16292 else
16295 }
16299 else
16306 {
16309 }
16312 {
16315 }
16318 {
16319 #if SYSV386_COMPAT
16320 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16321 derived assemblers, confusingly reverse the direction of
16322 the operation for fsub{r} and fdiv{r} when the
16323 destination register is not st(0). The Intel assembler
16324 doesn't have this brain damage. Read !SYSV386_COMPAT to
16325 figure out what the hardware really does. */
16328 else
16330 #else
16332 /* As above for fmul/fadd, we can't store to st(0). */
16334 else
16336 #endif
16338 }
16341 {
16342 #if SYSV386_COMPAT
16345 else
16347 #else
16350 else
16352 #endif
16354 }
16357 {
16360 else
16363 }
16365 {
16366 #if SYSV386_COMPAT
16368 #else
16370 #endif
16371 }
16372 else
16373 {
16374 #if SYSV386_COMPAT
16376 #else
16378 #endif
16379 }
16384 }
16388 }
16390 /* Check if a 256bit AVX register is referenced inside of EXP. */
16392 static int
16394 {
16405 }
16407 /* Return needed mode for entity in optimize_mode_switching pass. */
16409 static int
16411 {
16413 {
16414 rtx link;
16416 /* Needed mode is set to AVX_U128_CLEAN if there are
16417 no 256bit modes used in function arguments. */
16419 link;
16421 {
16423 {
16428 }
16429 }
16432 }
16434 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16435 changes state only when a 256bit register is written to, but we need
16436 to prevent the compiler from moving optimal insertion point above
16437 eventual read from 256bit register. */
16442 }
16444 /* Return mode that i387 must be switched into
16445 prior to the execution of insn. */
16447 static int
16449 {
16452 /* The mode UNINITIALIZED is used to store control word after a
16453 function call or ASM pattern. The mode ANY specify that function
16454 has no requirements on the control word and make no changes in the
16455 bits we are interested in. */
16469 {
16492 }
16495 }
16497 /* Return mode that entity must be switched into
16498 prior to the execution of insn. */
16500 int
16502 {
16504 {
16514 }
16516 }
16518 /* Check if a 256bit AVX register is referenced in stores. */
16520 static void
16522 {
16524 {
16527 }
16528 }
16530 /* Calculate mode of upper 128bit AVX registers after the insn. */
16532 static int
16534 {
16541 /* We know that state is clean after CALL insn if there are no
16542 256bit registers used in the function return register. */
16544 {
16549 }
16551 /* Otherwise, return current mode. Remember that if insn
16552 references AVX 256bit registers, the mode was already changed
16553 to DIRTY from MODE_NEEDED. */
16555 }
16557 /* Return the mode that an insn results in. */
16559 int
16561 {
16563 {
16573 }
16574 }
16576 static int
16578 {
16579 tree arg;
16581 /* Entry mode is set to AVX_U128_DIRTY if there are
16582 256bit modes used in function arguments. */
16585 {
16590 }
16593 }
16595 /* Return a mode that ENTITY is assumed to be
16596 switched to at function entry. */
16598 int
16600 {
16602 {
16612 }
16613 }
16615 static int
16617 {
16620 /* Exit mode is set to AVX_U128_DIRTY if there are
16621 256bit modes used in the function return register. */
16626 }
16628 /* Return a mode that ENTITY is assumed to be
16629 switched to at function exit. */
16631 int
16633 {
16635 {
16645 }
16646 }
16648 /* Output code to initialize control word copies used by trunc?f?i and
16649 rounding patterns. CURRENT_MODE is set to current control word,
16650 while NEW_MODE is set to new control word. */
16652 static void
16654 {
16656 rtx new_mode;
16667 {
16669 {
16671 /* round toward zero (truncate) */
16677 /* round down toward -oo */
16684 /* round up toward +oo */
16691 /* mask precision exception for nearbyint() */
16698 }
16699 }
16700 else
16701 {
16703 {
16705 /* round toward zero (truncate) */
16711 /* round down toward -oo */
16717 /* round up toward +oo */
16723 /* mask precision exception for nearbyint() */
16730 }
16731 }
16737 }
16739 /* Emit vzeroupper. */
16741 void
16743 {
16746 /* Cancel automatic vzeroupper insertion if there are
16747 live call-saved SSE registers at the insertion point. */
16759 }
16761 /* Generate one or more insns to set ENTITY to MODE. */
16763 void
16765 {
16767 {
16782 }
16783 }
16785 /* Output code for INSN to convert a float to a signed int. OPERANDS
16786 are the insn operands. The output may be [HSD]Imode and the input
16787 operand may be [SDX]Fmode. */
16791 {
16796 /* Jump through a hoop or two for DImode, since the hardware has no
16797 non-popping instruction. We used to do this a different way, but
16798 that was somewhat fragile and broke with post-reload splitters. */
16808 else
16809 {
16814 else
16818 }
16821 }
16823 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16824 have the values zero or one, indicates the ffreep insn's operand
16825 from the OPERANDS array. */
16829 {
16831 #ifdef HAVE_AS_IX86_FFREEP
16833 #else
16834 {
16844 }
16845 #endif
16848 }
16851 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16852 should be used. UNORDERED_P is true when fucom should be used. */
16856 {
16862 {
16865 }
16866 else
16867 {
16870 }
16873 {
16877 else
16879 else
16882 else
16884 }
16891 {
16893 {
16896 }
16897 else
16899 }
16902 && stack_top_dies
16905 {
16906 /* If both the top of the 387 stack dies, and the other operand
16907 is also a stack register that dies, then this must be a
16908 `fcompp' float compare */
16911 {
16912 /* There is no double popping fcomi variant. Fortunately,
16913 eflags is immune from the fstp's cc clobbering. */
16916 else
16919 }
16920 else
16921 {
16924 else
16926 }
16927 }
16928 else
16929 {
16930 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16933 {
16941 NULL,
16942 NULL,
16949 NULL,
16950 NULL,
16951 NULL,
16952 NULL
16953 };
16968 }
16969 }
16971 void
16973 {
16976 #ifdef ASM_QUAD
16979 #else
16981 #endif
16984 }
16986 void
16988 {
16991 #ifdef ASM_QUAD
16994 #else
16996 #endif
16997 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17003 #if TARGET_MACHO
17005 {
17009 }
17010 #endif
17011 else
17014 }
17015 \f
17016 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17017 for the target. */
17019 void
17021 {
17022 rtx tmp;
17024 /* We play register width games, which are only valid after reload. */
17027 /* Avoid HImode and its attendant prefix byte. */
17032 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
17034 {
17037 }
17040 }
17042 /* X is an unchanging MEM. If it is a constant pool reference, return
17043 the constant pool rtx, else NULL. */
17045 rtx
17047 {
17054 }
17056 void
17058 {
17066 {
17067 rtx tmp;
17071 {
17077 }
17080 }
17084 {
17087 rtx tmp;
17092 else
17096 {
17103 }
17104 }
17108 {
17110 {
17111 #if TARGET_MACHO
17112 /* dynamic-no-pic */
17114 {
17115 rtx temp = ((reload_in_progress
17123 }
17125 {
17129 }
17132 else
17133 {
17141 }
17142 /* dynamic-no-pic */
17143 #endif
17144 }
17145 else
17146 {
17150 {
17156 }
17157 }
17158 }
17159 else
17160 {
17171 /* Force large constants in 64bit compilation into register
17172 to get them CSEed. */
17184 {
17185 /* If we are loading a floating point constant to a register,
17186 force the value to memory now, since we'll get better code
17187 out the back end. */
17191 {
17196 }
17197 }
17198 }
17201 }
17203 void
17205 {
17212 /* Force constants other than zero into memory. We do not know how
17213 the instructions used to build constants modify the upper 64 bits
17214 of the register, once we have that information we may be able
17215 to handle some of them more efficiently. */
17224 /* We need to check memory alignment for SSE mode since attribute
17225 can make operands unaligned. */
17230 {
17233 /* ix86_expand_vector_move_misalign() does not like constants ... */
17239 /* ... nor both arguments in memory. */
17247 }
17249 /* Make operand1 a register if it isn't already. */
17253 {
17256 }
17259 }
17261 /* Split 32-byte AVX unaligned load and store if needed. */
17263 static void
17265 {
17266 rtx m;
17273 {
17294 }
17297 {
17299 {
17306 }
17307 /* Normal *mov<mode>_internal pattern will handle
17308 unaligned loads just fine if misaligned_operand
17309 is true, and without the UNSPEC it can be combined
17310 with arithmetic instructions. */
17313 else
17315 }
17317 {
17319 {
17324 }
17325 else
17327 }
17328 else
17330 }
17332 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17333 straight to ix86_expand_vector_move. */
17334 /* Code generation for scalar reg-reg moves of single and double precision data:
17335 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17336 movaps reg, reg
17337 else
17338 movss reg, reg
17339 if (x86_sse_partial_reg_dependency == true)
17340 movapd reg, reg
17341 else
17342 movsd reg, reg
17344 Code generation for scalar loads of double precision data:
17345 if (x86_sse_split_regs == true)
17346 movlpd mem, reg (gas syntax)
17347 else
17348 movsd mem, reg
17350 Code generation for unaligned packed loads of single precision data
17351 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17352 if (x86_sse_unaligned_move_optimal)
17353 movups mem, reg
17355 if (x86_sse_partial_reg_dependency == true)
17356 {
17357 xorps reg, reg
17358 movlps mem, reg
17359 movhps mem+8, reg
17360 }
17361 else
17362 {
17363 movlps mem, reg
17364 movhps mem+8, reg
17365 }
17367 Code generation for unaligned packed loads of double precision data
17368 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17369 if (x86_sse_unaligned_move_optimal)
17370 movupd mem, reg
17372 if (x86_sse_split_regs == true)
17373 {
17374 movlpd mem, reg
17375 movhpd mem+8, reg
17376 }
17377 else
17378 {
17379 movsd mem, reg
17380 movhpd mem+8, reg
17381 }
17382 */
17384 void
17386 {
17395 {
17397 {
17401 {
17403 {
17406 }
17407 else
17409 }
17411 /* FALLTHRU */
17415 {
17430 }
17436 else
17444 }
17447 }
17451 {
17453 {
17457 {
17459 {
17462 }
17463 else
17465 }
17467 /* FALLTHRU */
17477 }
17480 }
17483 {
17484 /* Normal *mov<mode>_internal pattern will handle
17485 unaligned loads just fine if misaligned_operand
17486 is true, and without the UNSPEC it can be combined
17487 with arithmetic instructions. */
17493 /* ??? If we have typed data, then it would appear that using
17494 movdqu is the only way to get unaligned data loaded with
17495 integer type. */
17497 {
17499 {
17502 }
17504 /* We will eventually emit movups based on insn attributes. */
17508 }
17510 {
17511 rtx zero;
17514 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17515 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17517 {
17518 /* We will eventually emit movups based on insn attributes. */
17521 }
17523 /* When SSE registers are split into halves, we can avoid
17524 writing to the top half twice. */
17526 {
17529 }
17530 else
17531 {
17532 /* ??? Not sure about the best option for the Intel chips.
17533 The following would seem to satisfy; the register is
17534 entirely cleared, breaking the dependency chain. We
17535 then store to the upper half, with a dependency depth
17536 of one. A rumor has it that Intel recommends two movsd
17537 followed by an unpacklpd, but this is unconfirmed. And
17538 given that the dependency depth of the unpacklpd would
17539 still be one, I'm not sure why this would be better. */
17541 }
17547 }
17548 else
17549 {
17550 rtx t;
17553 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17554 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17556 {
17558 {
17561 }
17568 }
17572 else
17577 else
17586 }
17587 }
17589 {
17591 {
17594 /* We will eventually emit movups based on insn attributes. */
17596 }
17598 {
17600 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17601 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17603 /* We will eventually emit movups based on insn attributes. */
17605 else
17606 {
17611 }
17612 }
17613 else
17614 {
17619 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17620 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17622 {
17625 }
17626 else
17627 {
17632 }
17633 }
17634 }
17635 else
17637 }
17639 /* Helper function of ix86_fixup_binary_operands to canonicalize
17640 operand order. Returns true if the operands should be swapped. */
17642 static bool
17644 rtx operands[])
17645 {
17650 /* If the operation is not commutative, we can't do anything. */
17654 /* Highest priority is that src1 should match dst. */
17660 /* Next highest priority is that immediate constants come second. */
17666 /* Lowest priority is that memory references should come second. */
17673 }
17676 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17677 destination to use for the operation. If different from the true
17678 destination in operands[0], a copy operation will be required. */
17680 rtx
17682 rtx operands[])
17683 {
17688 /* Canonicalize operand order. */
17690 {
17691 rtx temp;
17693 /* It is invalid to swap operands of different modes. */
17699 }
17701 /* Both source operands cannot be in memory. */
17703 {
17704 /* Optimization: Only read from memory once. */
17706 {
17709 }
17712 else
17714 }
17716 /* If the destination is memory, and we do not have matching source
17717 operands, do things in registers. */
17721 /* Source 1 cannot be a constant. */
17725 /* Source 1 cannot be a non-matching memory. */
17729 /* Improve address combine. */
17738 }
17740 /* Similarly, but assume that the destination has already been
17741 set up properly. */
17743 void
17746 {
17749 }
17751 /* Attempt to expand a binary operator. Make the expansion closer to the
17752 actual machine, then just general_operand, which will allow 3 separate
17753 memory references (one output, two input) in a single insn. */
17755 void
17757 rtx operands[])
17758 {
17765 /* Emit the instruction. */
17769 {
17770 /* Reload doesn't know about the flags register, and doesn't know that
17771 it doesn't want to clobber it. We can only do this with PLUS. */
17774 }
17778 {
17779 /* This is going to be an LEA; avoid splitting it later. */
17781 }
17782 else
17783 {
17786 }
17788 /* Fix up the destination if needed. */
17791 }
17793 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17794 the given OPERANDS. */
17796 void
17798 rtx operands[])
17799 {
17802 {
17805 }
17807 {
17810 }
17811 /* Optimize (__m128i) d | (__m128i) e and similar code
17812 when d and e are float vectors into float vector logical
17813 insn. In C/C++ without using intrinsics there is no other way
17814 to express vector logical operation on float vectors than
17815 to cast them temporarily to integer vectors. */
17817 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17826 {
17827 rtx dst;
17829 {
17836 {
17839 }
17840 else
17841 {
17846 }
17857 }
17858 }
17867 }
17869 /* Return TRUE or FALSE depending on whether the binary operator meets the
17870 appropriate constraints. */
17872 bool
17875 {
17880 /* Both source operands cannot be in memory. */
17884 /* Canonicalize operand order for commutative operators. */
17886 {
17890 }
17892 /* If the destination is memory, we must have a matching source operand. */
17896 /* Source 1 cannot be a constant. */
17900 /* Source 1 cannot be a non-matching memory. */
17902 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17910 }
17912 /* Attempt to expand a unary operator. Make the expansion closer to the
17913 actual machine, then just general_operand, which will allow 2 separate
17914 memory references (one output, one input) in a single insn. */
17916 void
17918 rtx operands[])
17919 {
17926 /* If the destination is memory, and we do not have matching source
17927 operands, do things in registers. */
17930 {
17933 else
17935 }
17937 /* When source operand is memory, destination must match. */
17941 /* Emit the instruction. */
17945 {
17946 /* Reload doesn't know about the flags register, and doesn't know that
17947 it doesn't want to clobber it. */
17950 }
17951 else
17952 {
17955 }
17957 /* Fix up the destination if needed. */
17960 }
17962 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17963 divisor are within the range [0-255]. */
17965 void
17968 {
17977 {
17990 }
17997 /* Use 8bit unsigned divimod if dividend and divisor are within
17998 the range [0-255]. */
18007 pc_rtx);
18012 /* Generate original signed/unsigned divimod. */
18017 /* Branch to the end. */
18021 /* Generate 8bit unsigned divide. */
18023 /* Don't use operands[0] for result of 8bit divide since not all
18024 registers support QImode ZERO_EXTRACT. */
18031 {
18034 }
18035 else
18036 {
18039 }
18041 /* Extract remainder from AH. */
18045 else
18046 {
18047 /* Need a new scratch register since the old one has result
18048 of 8bit divide. */
18052 }
18055 /* Zero extend quotient from AL. */
18061 }
18063 /* Whether it is OK to emit CFI directives when emitting asm code. */
18065 bool
18067 {
18069 }
18071 #define LEA_MAX_STALL (3)
18072 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18074 /* Increase given DISTANCE in half-cycles according to
18075 dependencies between PREV and NEXT instructions.
18076 Add 1 half-cycle if there is no dependency and
18077 go to next cycle if there is some dependecy. */
18079 static unsigned int
18081 {
18098 }
18100 /* Function checks if instruction INSN defines register number
18101 REGNO1 or REGNO2. */
18103 static bool
18105 rtx insn)
18106 {
18114 {
18116 }
18119 }
18121 /* Function checks if instruction INSN uses register number
18122 REGNO as a part of address expression. */
18124 static bool
18126 {
18134 }
18136 /* Search backward for non-agu definition of register number REGNO1
18137 or register number REGNO2 in basic block starting from instruction
18138 START up to head of basic block or instruction INSN.
18140 Function puts true value into *FOUND var if definition was found
18141 and false otherwise.
18143 Distance in half-cycles between START and found instruction or head
18144 of BB is added to DISTANCE and returned. */
18146 static int
18150 {
18160 {
18162 {
18165 {
18168 {
18171 }
18172 }
18175 }
18180 }
18183 }
18185 /* Search backward for non-agu definition of register number REGNO1
18186 or register number REGNO2 in INSN's basic block until
18187 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18188 2. Reach neighbour BBs boundary, or
18189 3. Reach agu definition.
18190 Returns the distance between the non-agu definition point and INSN.
18191 If no definition point, returns -1. */
18193 static int
18195 rtx insn)
18196 {
18207 {
18208 edge e;
18209 edge_iterator ei;
18214 {
18217 }
18223 else
18224 {
18229 {
18230 int bb_dist
18236 {
18243 }
18244 }
18247 }
18248 }
18250 /* get_attr_type may modify recog data. We want to make sure
18251 that recog data is valid for instruction INSN, on which
18252 distance_non_agu_define is called. INSN is unchanged here. */
18259 }
18261 /* Return the distance in half-cycles between INSN and the next
18262 insn that uses register number REGNO in memory address added
18263 to DISTANCE. Return -1 if REGNO0 is set.
18265 Put true value into *FOUND if register usage was found and
18266 false otherwise.
18267 Put true value into *REDEFINED if register redefinition was
18268 found and false otherwise. */
18270 static int
18274 {
18283 {
18286 /* If insn and start belong to the same bb, set prev to insn,
18287 so the call to increase_distance will increase the distance
18288 between insns by 1. */
18290 }
18295 {
18297 {
18300 {
18301 /* Return DISTANCE if OP0 is used in memory
18302 address in NEXT. */
18305 }
18308 {
18309 /* Return -1 if OP0 is set in NEXT. */
18312 }
18315 }
18321 }
18324 }
18326 /* Return the distance between INSN and the next insn that uses
18327 register number REGNO0 in memory address. Return -1 if no such
18328 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18330 static int
18332 {
18344 {
18345 edge e;
18346 edge_iterator ei;
18351 {
18354 }
18360 else
18361 {
18367 {
18368 int bb_dist
18373 {
18380 }
18381 }
18384 }
18385 }
18391 }
18393 /* Define this macro to tune LEA priority vs ADD, it take effect when
18394 there is a dilemma of choicing LEA or ADD
18395 Negative value: ADD is more preferred than LEA
18396 Zero: Netrual
18397 Positive value: LEA is more preferred than ADD*/
18398 #define IX86_LEA_PRIORITY 0
18400 /* Return true if usage of lea INSN has performance advantage
18401 over a sequence of instructions. Instructions sequence has
18402 SPLIT_COST cycles higher latency than lea latency. */
18404 static bool
18407 {
18410 /* For Silvermont if using a 2-source or 3-source LEA for
18411 non-destructive destination purposes, or due to wanting
18412 ability to use SCALE, the use of LEA is justified. */
18414 {
18422 }
18428 {
18429 /* If there is no non AGU operand definition, no AGU
18430 operand usage and split cost is 0 then both lea
18431 and non lea variants have same priority. Currently
18432 we prefer lea for 64 bit code and non lea on 32 bit
18433 code. */
18436 else
18438 }
18440 /* With longer definitions distance lea is more preferable.
18441 Here we change it to take into account splitting cost and
18442 lea priority. */
18445 /* If there is no use in memory addess then we just check
18446 that split cost exceeds AGU stall. */
18450 /* If this insn has both backward non-agu dependence and forward
18451 agu dependence, the one with short distance takes effect. */
18453 }
18455 /* Return true if it is legal to clobber flags by INSN and
18456 false otherwise. */
18458 static bool
18460 {
18463 bitmap live;
18466 {
18468 {
18475 }
18481 }
18485 }
18487 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18488 move and add to avoid AGU stalls. */
18490 bool
18492 {
18495 /* Check if we need to optimize. */
18499 /* Check it is correct to split here. */
18507 /* We need to split only adds with non destructive
18508 destination operand. */
18511 else
18513 }
18515 /* Return true if we should emit lea instruction instead of mov
18516 instruction. */
18518 bool
18520 {
18523 /* Check if we need to optimize. */
18527 /* Use lea for reg to reg moves only. */
18535 }
18537 /* Return true if we need to split lea into a sequence of
18538 instructions to avoid AGU stalls. */
18540 bool
18542 {
18548 /* Check we need to optimize. */
18552 /* The "at least two components" test below might not catch simple
18553 move or zero extension insns if parts.base is non-NULL and parts.disp
18554 is const0_rtx as the only components in the address, e.g. if the
18555 register is %rbp or %r13. As this test is much cheaper and moves or
18556 zero extensions are the common case, do this check first. */
18562 /* Check if it is OK to split here. */
18569 /* There should be at least two components in the address. */
18574 /* We should not split into add if non legitimate pic
18575 operand is used as displacement. */
18590 /* Compute how many cycles we will add to execution time
18591 if split lea into a sequence of instructions. */
18593 {
18594 /* Have to use mov instruction if non desctructive
18595 destination form is used. */
18599 /* Have to add index to base if both exist. */
18603 /* Have to use shift and adds if scale is 2 or greater. */
18605 {
18610 else
18612 }
18614 /* Have to use add instruction with immediate if
18615 disp is non zero. */
18619 /* Subtract the price of lea. */
18621 }
18625 }
18627 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18628 matches destination. RTX includes clobber of FLAGS_REG. */
18630 static void
18633 {
18640 }
18642 /* Return true if regno1 def is nearest to the insn. */
18644 static bool
18646 {
18653 {
18655 {
18658 }
18664 }
18666 /* None of the regs is defined in the bb. */
18668 }
18670 /* Split lea instructions into a sequence of instructions
18671 which are executed on ALU to avoid AGU stalls.
18672 It is assumed that it is allowed to clobber flags register
18673 at lea position. */
18675 void
18677 {
18693 {
18696 }
18699 {
18702 }
18708 {
18709 /* Case r1 = r1 + ... */
18711 {
18712 /* If we have a case r1 = r1 + C * r2 then we
18713 should use multiplication which is very
18714 expensive. Assume cost model is wrong if we
18715 have such case here. */
18720 }
18721 else
18722 {
18723 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18727 /* Use shift for scaling. */
18736 }
18737 }
18739 {
18742 }
18743 else
18744 {
18746 {
18749 }
18751 {
18754 }
18755 else
18756 {
18761 else
18762 {
18763 rtx tmp1;
18765 /* Find better operand for SET instruction, depending
18766 on which definition is farther from the insn. */
18769 else
18779 }
18782 }
18786 }
18787 }
18789 /* Return true if it is ok to optimize an ADD operation to LEA
18790 operation to avoid flag register consumation. For most processors,
18791 ADD is faster than LEA. For the processors like BONNELL, if the
18792 destination register of LEA holds an actual address which will be
18793 used soon, LEA is better and otherwise ADD is better. */
18795 bool
18797 {
18802 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18810 }
18812 /* Return true if destination reg of SET_BODY is shift count of
18813 USE_BODY. */
18815 static bool
18817 {
18818 rtx set_dest;
18819 rtx shift_rtx;
18822 /* Retrieve destination of SET_BODY. */
18824 {
18833 use_body))
18838 }
18840 /* Retrieve shift count of USE_BODY. */
18842 {
18854 }
18862 {
18865 /* Return true if shift count is dest of SET_BODY. */
18867 {
18868 /* Add check since it can be invoked before register
18869 allocation in pre-reload schedule. */
18875 }
18876 }
18879 }
18881 /* Return true if destination reg of SET_INSN is shift count of
18882 USE_INSN. */
18884 bool
18886 {
18889 }
18891 /* Return TRUE or FALSE depending on whether the unary operator meets the
18892 appropriate constraints. */
18894 bool
18898 {
18899 /* If one of operands is memory, source and destination must match. */
18905 }
18907 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18908 are ok, keeping in mind the possible movddup alternative. */
18910 bool
18912 {
18918 }
18920 /* Post-reload splitter for converting an SF or DFmode value in an
18921 SSE register into an unsigned SImode. */
18923 void
18925 {
18936 /* Load up the value into the low element. We must ensure that the other
18937 elements are valid floats -- zero is the easiest such value. */
18939 {
18942 else
18944 }
18945 else
18946 {
18951 else
18953 }
18973 else
18978 }
18980 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18981 Expects the 64-bit DImode to be supplied in a pair of integral
18982 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18983 -mfpmath=sse, !optimize_size only. */
18985 void
18987 {
18991 rtx x;
18997 {
19000 }
19001 else
19002 {
19006 }
19014 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19017 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19018 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19019 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19020 (0x1.0p84 + double(fp_value_hi_xmm)).
19021 Note these exponents differ by 32. */
19025 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19026 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19035 /* Add the upper and lower DFmode values together. */
19038 else
19039 {
19043 }
19046 }
19048 /* Not used, but eases macroization of patterns. */
19049 void
19051 rtx input ATTRIBUTE_UNUSED)
19052 {
19054 }
19056 /* Convert an unsigned SImode value into a DFmode. Only currently used
19057 for SSE, but applicable anywhere. */
19059 void
19061 {
19062 REAL_VALUE_TYPE TWO31r;
19077 }
19079 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19080 32-bit mode; otherwise we have a direct convert instruction. */
19082 void
19084 {
19085 REAL_VALUE_TYPE TWO32r;
19103 }
19105 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19106 For x86_32, -mfpmath=sse, !optimize_size only. */
19107 void
19109 {
19110 REAL_VALUE_TYPE ONE16r;
19129 }
19131 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19132 a vector of unsigned ints VAL to vector of floats TARGET. */
19134 void
19136 {
19138 REAL_VALUE_TYPE TWO16r;
19145 else
19150 OPTAB_DIRECT);
19161 OPTAB_DIRECT);
19163 OPTAB_DIRECT);
19166 }
19168 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19169 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19170 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19171 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19173 rtx
19175 {
19176 REAL_VALUE_TYPE TWO31r;
19191 {
19197 }
19206 OPTAB_DIRECT);
19207 else
19208 {
19214 OPTAB_DIRECT);
19215 }
19218 }
19220 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19221 then replicate the value for all elements of the vector
19222 register. */
19224 rtx
19226 {
19228 rtvec v;
19232 {
19265 }
19266 }
19268 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19269 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19270 for an SSE register. If VECT is true, then replicate the mask for
19271 all elements of the vector register. If INVERT is true, then create
19272 a mask excluding the sign bit. */
19274 rtx
19276 {
19280 rtx v;
19281 rtx mask;
19283 /* Find the sign bit, sign extended to 2*HWI. */
19285 {
19309 else
19317 {
19320 }
19321 else
19322 {
19323 rtvec vec;
19329 {
19332 }
19333 else
19343 }
19348 }
19353 /* Force this value into the low part of a fp vector constant. */
19362 }
19364 /* Generate code for floating point ABS or NEG. */
19366 void
19368 rtx operands[])
19369 {
19380 {
19386 }
19388 /* NEG and ABS performed with SSE use bitwise mask operations.
19389 Create the appropriate mask now. */
19392 else
19402 {
19404 rtvec par;
19409 else
19410 {
19413 }
19415 }
19416 else
19418 }
19420 /* Expand a copysign operation. Special case operand 0 being a constant. */
19422 void
19424 {
19438 else
19442 {
19449 {
19452 else
19453 {
19457 }
19458 }
19468 else
19472 }
19473 else
19474 {
19484 else
19488 }
19489 }
19491 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19492 be a constant, and so has already been expanded into a vector constant. */
19494 void
19496 {
19512 {
19515 }
19516 }
19518 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19519 so we have to do two masks. */
19521 void
19523 {
19538 {
19539 /* Shouldn't happen often (it's useless, obviously), but when it does
19540 we'd generate incorrect code if we continue below. */
19543 }
19546 {
19557 }
19558 else
19559 {
19561 {
19563 }
19565 {
19569 }
19573 {
19576 }
19578 {
19583 }
19585 }
19589 }
19591 /* Return TRUE or FALSE depending on whether the first SET in INSN
19592 has source and destination with matching CC modes, and that the
19593 CC mode is at least as constrained as REQ_MODE. */
19595 bool
19597 {
19598 rtx set;
19609 {
19619 /* FALLTHRU */
19623 /* FALLTHRU */
19627 /* FALLTHRU */
19641 }
19644 }
19646 /* Generate insn patterns to do an integer compare of OPERANDS. */
19648 static rtx
19650 {
19657 /* This is very simple, but making the interface the same as in the
19658 FP case makes the rest of the code easier. */
19662 /* Return the test that should be put into the flags user, i.e.
19663 the bcc, scc, or cmov instruction. */
19665 }
19667 /* Figure out whether to use ordered or unordered fp comparisons.
19668 Return the appropriate mode to use. */
19670 enum machine_mode
19672 {
19673 /* ??? In order to make all comparisons reversible, we do all comparisons
19674 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19675 all forms trapping and nontrapping comparisons, we can make inequality
19676 comparisons trapping again, since it results in better code when using
19677 FCOM based compares. */
19679 }
19681 enum machine_mode
19683 {
19687 {
19690 }
19693 {
19694 /* Only zero flag is needed. */
19698 /* Codes needing carry flag. */
19701 /* Detect overflow checks. They need just the carry flag. */
19705 else
19710 /* Codes possibly doable only with sign flag when
19711 comparing against zero. */
19716 else
19717 /* For other cases Carry flag is not required. */
19719 /* Codes doable only with sign flag when comparing
19720 against zero, but we miss jump instruction for it
19721 so we need to use relational tests against overflow
19722 that thus needs to be zero. */
19727 else
19729 /* strcmp pattern do (use flags) and combine may ask us for proper
19730 mode. */
19735 }
19736 }
19738 /* Return the fixed registers used for condition codes. */
19740 static bool
19742 {
19746 }
19748 /* If two condition code modes are compatible, return a condition code
19749 mode which is compatible with both. Otherwise, return
19750 VOIDmode. */
19752 static enum machine_mode
19754 {
19771 {
19785 {
19799 }
19803 /* These are only compatible with themselves, which we already
19804 checked above. */
19806 }
19807 }
19810 /* Return a comparison we can do and that it is equivalent to
19811 swap_condition (code) apart possibly from orderedness.
19812 But, never change orderedness if TARGET_IEEE_FP, returning
19813 UNKNOWN in that case if necessary. */
19815 static enum rtx_code
19817 {
19819 {
19830 }
19831 }
19833 /* Return cost of comparison CODE using the best strategy for performance.
19834 All following functions do use number of instructions as a cost metrics.
19835 In future this should be tweaked to compute bytes for optimize_size and
19836 take into account performance of various instructions on various CPUs. */
19838 static int
19840 {
19843 /* The cost of code using bit-twiddling on %ah. */
19845 {
19868 }
19871 {
19878 }
19879 }
19881 /* Return strategy to use for floating-point. We assume that fcomi is always
19882 preferrable where available, since that is also true when looking at size
19883 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19885 enum ix86_fpcmp_strategy
19887 {
19888 /* Do fcomi/sahf based test when profitable. */
19897 }
19899 /* Swap, force into registers, or otherwise massage the two operands
19900 to a fp comparison. The operands are updated in place; the new
19901 comparison code is returned. */
19903 static enum rtx_code
19905 {
19911 /* All of the unordered compare instructions only work on registers.
19912 The same is true of the fcomi compare instructions. The XFmode
19913 compare instructions require registers except when comparing
19914 against zero or when converting operand 1 from fixed point to
19915 floating point. */
19924 {
19927 }
19928 else
19929 {
19930 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19931 things around if they appear profitable, otherwise force op0
19932 into a register. */
19938 {
19941 {
19942 rtx tmp;
19945 }
19946 }
19952 {
19957 {
19960 }
19961 else
19963 }
19964 }
19966 /* Try to rearrange the comparison to make it cheaper. */
19970 {
19971 rtx tmp;
19976 }
19981 }
19983 /* Convert comparison codes we use to represent FP comparison to integer
19984 code that will result in proper branch. Return UNKNOWN if no such code
19985 is available. */
19987 enum rtx_code
19989 {
19991 {
20014 }
20015 }
20017 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20019 static rtx
20021 {
20028 /* Do fcomi/sahf based test when profitable. */
20030 {
20035 tmp);
20043 tmp);
20052 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20059 /* In the unordered case, we have to check C2 for NaN's, which
20060 doesn't happen to work out to anything nice combination-wise.
20061 So do some bit twiddling on the value we've got in AH to come
20062 up with an appropriate set of condition codes. */
20066 {
20070 {
20073 }
20074 else
20075 {
20081 }
20086 {
20091 }
20092 else
20093 {
20096 }
20101 {
20104 }
20105 else
20106 {
20110 }
20115 {
20121 }
20122 else
20123 {
20126 }
20131 {
20136 }
20137 else
20138 {
20141 }
20146 {
20151 }
20152 else
20153 {
20156 }
20170 }
20175 }
20177 /* Return the test that should be put into the flags user, i.e.
20178 the bcc, scc, or cmov instruction. */
20181 const0_rtx);
20182 }
20184 static rtx
20186 {
20187 rtx ret;
20193 {
20196 }
20197 else
20201 }
20203 void
20205 {
20207 rtx tmp;
20210 {
20217 simple:
20221 pc_rtx);
20229 /* Expand DImode branch into multiple compare+branch. */
20230 {
20236 {
20239 }
20246 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20247 avoid two branches. This costs one extra insn, so disable when
20248 optimizing for size. */
20253 {
20271 }
20273 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20274 op1 is a constant and the low word is zero, then we can just
20275 examine the high word. Similarly for low word -1 and
20276 less-or-equal-than or greater-than. */
20280 {
20283 {
20286 }
20290 {
20293 }
20297 }
20299 /* Otherwise, we need two or three jumps. */
20308 {
20322 }
20324 /*
20325 * a < b =>
20326 * if (hi(a) < hi(b)) goto true;
20327 * if (hi(a) > hi(b)) goto false;
20328 * if (lo(a) < lo(b)) goto true;
20329 * false:
20330 */
20342 }
20347 }
20348 }
20350 /* Split branch based on floating point condition. */
20351 void
20354 {
20355 rtx condition;
20356 rtx i;
20359 {
20364 }
20367 tmp);
20375 }
20377 void
20379 {
20380 rtx ret;
20387 }
20389 /* Expand comparison setting or clearing carry flag. Return true when
20390 successful and set pop for the operation. */
20391 static bool
20393 {
20397 /* Do not handle double-mode compares that go through special path. */
20402 {
20407 /* Shortcut: following common codes never translate
20408 into carry flag compares. */
20413 /* These comparisons require zero flag; swap operands so they won't. */
20416 {
20421 }
20423 /* Try to expand the comparison and verify that we end up with
20424 carry flag based comparison. This fails to be true only when
20425 we decide to expand comparison using arithmetic that is not
20426 too common scenario. */
20435 else
20444 }
20450 {
20455 /* Convert a==0 into (unsigned)a<1. */
20464 /* Convert a>b into b<a or a>=b-1. */
20468 {
20470 /* Bail out on overflow. We still can swap operands but that
20471 would force loading of the constant into register. */
20476 }
20477 else
20478 {
20483 }
20486 /* Convert a>=0 into (unsigned)a<0x80000000. */
20504 }
20505 /* Swapping operands may cause constant to appear as first operand. */
20507 {
20511 }
20515 }
20517 bool
20519 {
20543 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20544 HImode insns, we'd be swallowed in word prefix ops. */
20550 {
20554 HOST_WIDE_INT diff;
20557 /* Sign bit compares are better done using shifts than we do by using
20558 sbb. */
20561 {
20562 /* Detect overlap between destination and compare sources. */
20566 {
20567 rtx flags;
20576 {
20578 compare_code
20580 }
20582 /* To simplify rest of code, restrict to the GEU case. */
20584 {
20590 }
20591 else
20592 {
20595 reverse_condition_maybe_unordered
20597 else
20600 }
20609 else
20612 }
20613 else
20614 {
20617 else
20618 {
20623 }
20625 }
20628 {
20629 /*
20630 * cmpl op0,op1
20631 * sbbl dest,dest
20632 * [addl dest, ct]
20633 *
20634 * Size 5 - 8.
20635 */
20640 }
20642 {
20643 /*
20644 * cmpl op0,op1
20645 * sbbl dest,dest
20646 * orl $ct, dest
20647 *
20648 * Size 8.
20649 */
20653 }
20655 {
20656 /*
20657 * cmpl op0,op1
20658 * sbbl dest,dest
20659 * notl dest
20660 * [addl dest, cf]
20661 *
20662 * Size 8 - 11.
20663 */
20669 }
20670 else
20671 {
20672 /*
20673 * cmpl op0,op1
20674 * sbbl dest,dest
20675 * [notl dest]
20676 * andl cf - ct, dest
20677 * [addl dest, ct]
20678 *
20679 * Size 8 - 11.
20680 */
20683 {
20687 }
20697 }
20703 }
20706 {
20709 HOST_WIDE_INT tmp;
20714 {
20717 /* We may be reversing unordered compare to normal compare, that
20718 is not valid in general (we may convert non-trapping condition
20719 to trapping one), however on i386 we currently emit all
20720 comparisons unordered. */
20723 }
20724 else
20725 {
20728 }
20729 }
20734 {
20739 {
20744 }
20745 }
20747 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20751 {
20752 /* If lea code below could be used, only optimize
20753 if it results in a 2 insn sequence. */
20759 {
20760 /*
20761 * notl op1 (if necessary)
20762 * sarl $31, op1
20763 * orl cf, op1
20764 */
20766 {
20770 }
20781 }
20782 }
20790 {
20791 /*
20792 * xorl dest,dest
20793 * cmpl op1,op2
20794 * setcc dest
20795 * lea cf(dest*(ct-cf)),dest
20796 *
20797 * Size 14.
20798 *
20799 * This also catches the degenerate setcc-only case.
20800 */
20802 rtx tmp;
20808 /* On x86_64 the lea instruction operates on Pmode, so we need
20809 to get arithmetics done in proper mode to match. */
20812 else
20813 {
20814 rtx out1;
20817 nops++;
20819 {
20821 nops++;
20822 }
20823 }
20825 {
20827 nops++;
20828 }
20830 {
20833 else
20835 }
20840 }
20842 /*
20843 * General case: Jumpful:
20844 * xorl dest,dest cmpl op1, op2
20845 * cmpl op1, op2 movl ct, dest
20846 * setcc dest jcc 1f
20847 * decl dest movl cf, dest
20848 * andl (cf-ct),dest 1:
20849 * addl ct,dest
20850 *
20851 * Size 20. Size 14.
20852 *
20853 * This is reasonably steep, but branch mispredict costs are
20854 * high on modern cpus, so consider failing only if optimizing
20855 * for space.
20856 */
20861 {
20863 {
20870 {
20873 /* We may be reversing unordered compare to normal compare,
20874 that is not valid in general (we may convert non-trapping
20875 condition to trapping one), however on i386 we currently
20876 emit all comparisons unordered. */
20878 }
20879 else
20880 {
20884 }
20885 }
20888 {
20889 /* notl op1 (if needed)
20890 sarl $31, op1
20891 andl (cf-ct), op1
20892 addl ct, op1
20894 For x < 0 (resp. x <= -1) there will be no notl,
20895 so if possible swap the constants to get rid of the
20896 complement.
20897 True/false will be -1/0 while code below (store flag
20898 followed by decrement) is 0/-1, so the constants need
20899 to be exchanged once more. */
20902 {
20905 }
20906 else
20907 {
20911 }
20914 }
20915 else
20916 {
20920 constm1_rtx,
20922 }
20934 }
20935 }
20938 {
20939 /* Try a few things more with specific constants and a variable. */
20941 optab op;
20947 /* If one of the two operands is an interesting constant, load a
20948 constant with the above and mask it in with a logical operation. */
20951 {
20957 else
20959 }
20961 {
20967 else
20969 }
20970 else
20977 /* Recurse to get the constant loaded. */
20981 /* Mask in the interesting variable. */
20983 OPTAB_WIDEN);
20988 }
20990 /*
20991 * For comparison with above,
20992 *
20993 * movl cf,dest
20994 * movl ct,tmp
20995 * cmpl op1,op2
20996 * cmovcc tmp,dest
20997 *
20998 * Size 15.
20999 */
21021 }
21023 /* Swap, force into registers, or otherwise massage the two operands
21024 to an sse comparison with a mask result. Thus we differ a bit from
21025 ix86_prepare_fp_compare_args which expects to produce a flags result.
21027 The DEST operand exists to help determine whether to commute commutative
21028 operators. The POP0/POP1 operands are updated in place. The new
21029 comparison code is returned, or UNKNOWN if not implementable. */
21031 static enum rtx_code
21034 {
21035 rtx tmp;
21038 {
21041 /* AVX supports all the needed comparisons. */
21044 /* We have no LTGT as an operator. We could implement it with
21045 NE & ORDERED, but this requires an extra temporary. It's
21046 not clear that it's worth it. */
21053 /* These are supported directly. */
21060 /* AVX has 3 operand comparisons, no need to swap anything. */
21063 /* For commutative operators, try to canonicalize the destination
21064 operand to be first in the comparison - this helps reload to
21065 avoid extra moves. */
21068 /* FALLTHRU */
21074 /* These are not supported directly before AVX, and furthermore
21075 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21076 comparison operands to transform into something that is
21077 supported. */
21086 }
21089 }
21091 /* Detect conditional moves that exactly match min/max operational
21092 semantics. Note that this is IEEE safe, as long as we don't
21093 interchange the operands.
21095 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21096 and TRUE if the operation is successful and instructions are emitted. */
21098 static bool
21101 {
21104 rtx tmp;
21107 ;
21109 {
21113 }
21114 else
21121 else
21126 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21127 but MODE may be a vector mode and thus not appropriate. */
21129 {
21131 rtvec v;
21136 }
21137 else
21138 {
21141 }
21145 }
21147 /* Expand an sse vector comparison. Return the register with the result. */
21149 static rtx
21152 {
21156 /* In general case result of comparison can differ from operands' type. */
21159 /* In AVX512F the result of comparison is an integer mask. */
21161 rtx x;
21164 {
21169 }
21170 else
21183 /* Compare patterns for int modes are unspec in AVX512F only. */
21185 {
21189 {
21198 }
21201 {
21204 }
21205 }
21209 {
21212 }
21213 else
21217 }
21219 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21220 operations. This is used for both scalar and vector conditional moves. */
21222 static void
21224 {
21228 /* In AVX512F the result of comparison is an integer mask. */
21236 {
21238 }
21241 {
21245 }
21248 {
21253 }
21256 {
21260 }
21263 {
21271 op_true,
21272 op_false)));
21273 }
21274 else
21275 {
21285 {
21299 {
21306 }
21321 {
21328 }
21346 }
21349 {
21353 }
21354 else
21355 {
21361 else
21373 }
21374 }
21375 }
21377 /* Expand a floating-point conditional move. Return true if successful. */
21379 bool
21381 {
21389 {
21392 /* Since we've no cmove for sse registers, don't force bad register
21393 allocation just to gain access to it. Deny movcc when the
21394 comparison mode doesn't match the move mode. */
21413 }
21420 /* The floating point conditional move instructions don't directly
21421 support conditions resulting from a signed integer comparison. */
21425 {
21430 }
21437 }
21439 /* Expand a floating-point vector conditional move; a vcond operation
21440 rather than a movcc operation. */
21442 bool
21444 {
21446 rtx cmp;
21451 {
21452 rtx temp;
21454 {
21471 }
21473 OPTAB_DIRECT);
21476 }
21486 }
21488 /* Expand a signed/unsigned integral vector conditional move. */
21490 bool
21492 {
21502 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21503 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21512 {
21516 {
21522 }
21525 {
21531 }
21532 }
21541 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21545 ;
21546 else
21547 {
21548 /* Canonicalize the comparison to EQ, GT, GTU. */
21550 {
21567 /* FALLTHRU */
21577 }
21579 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21581 {
21583 {
21585 /* SSE4.1 supports EQ. */
21592 /* SSE4.2 supports GT/GTU. */
21599 }
21600 }
21602 /* Unsigned parallel compare is not supported by the hardware.
21603 Play some tricks to turn this into a signed comparison
21604 against 0. */
21606 {
21610 {
21617 {
21622 {
21631 }
21632 /* Subtract (-(INT MAX) - 1) from both operands to make
21633 them signed. */
21644 }
21651 /* Perform a parallel unsigned saturating subtraction. */
21664 }
21665 }
21666 }
21668 /* Allow the comparison to be done in one mode, but the movcc to
21669 happen in another mode. */
21671 {
21674 }
21675 else
21676 {
21682 }
21687 }
21689 static bool
21691 {
21694 {
21698 op1));
21703 op1));
21715 }
21716 }
21718 /* Expand a variable vector permutation. */
21720 void
21722 {
21733 /* Number of elements in the vector. */
21742 {
21744 {
21745 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21746 an constant shuffle operand. With a tiny bit of effort we can
21747 use VPERMD instead. A re-interpretation stall for V4DFmode is
21748 unfortunate but there's no avoiding it.
21749 Similarly for V16HImode we don't have instructions for variable
21750 shuffling, while for V32QImode we can use after preparing suitable
21751 masks vpshufb; vpshufb; vpermq; vpor. */
21754 {
21758 }
21759 else
21760 {
21764 }
21767 /* Replicate the low bits of the V4DImode mask into V8SImode:
21768 mask = { A B C D }
21769 t1 = { A A B B C C D D }. */
21777 else
21780 /* Multiply the shuffle indicies by two. */
21782 OPTAB_DIRECT);
21784 /* Add one to the odd shuffle indicies:
21785 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21787 {
21790 }
21794 OPTAB_DIRECT);
21796 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21801 }
21804 {
21806 /* The VPERMD and VPERMPS instructions already properly ignore
21807 the high bits of the shuffle elements. No need for us to
21808 perform an AND ourselves. */
21810 {
21815 }
21816 else
21817 {
21823 }
21830 else
21831 {
21837 }
21841 /* By combining the two 128-bit input vectors into one 256-bit
21842 input vector, we can use VPERMD and VPERMPS for the full
21843 two-operand shuffle. */
21875 /* From mask create two adjusted masks, which contain the same
21876 bits as mask in the low 7 bits of each vector element.
21877 The first mask will have the most significant bit clear
21878 if it requests element from the same 128-bit lane
21879 and MSB set if it requests element from the other 128-bit lane.
21880 The second mask will have the opposite values of the MSB,
21881 and additionally will have its 128-bit lanes swapped.
21882 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21883 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21884 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21885 stands for other 12 bytes. */
21886 /* The bit whether element is from the same lane or the other
21887 lane is bit 4, so shift it up by 3 to the MSB position. */
21891 /* Clear MSB bits from the mask just in case it had them set. */
21893 /* After this t1 will have MSB set for elements from other lane. */
21895 /* Clear bits other than MSB. */
21897 /* Or in the lower bits from mask into t3. */
21899 /* And invert MSB bits in t1, so MSB is set for elements from the same
21900 lane. */
21902 /* Swap 128-bit lanes in t3. */
21907 /* And or in the lower bits from mask into t1. */
21910 {
21911 /* Each of these shuffles will put 0s in places where
21912 element from the other 128-bit lane is needed, otherwise
21913 will shuffle in the requested value. */
21917 /* For t3 the 128-bit lanes are swapped again. */
21922 /* And oring both together leads to the result. */
21929 }
21932 /* Similarly to the above one_operand_shuffle code,
21933 just for repeated twice for each operand. merge_two:
21934 code will merge the two results together. */
21958 }
21959 }
21962 {
21963 /* The XOP VPPERM insn supports three inputs. By ignoring the
21964 one_operand_shuffle special case, we avoid creating another
21965 set of constant vectors in memory. */
21968 /* mask = mask & {2*w-1, ...} */
21970 }
21971 else
21972 {
21973 /* mask = mask & {w-1, ...} */
21975 }
21983 /* For non-QImode operations, convert the word permutation control
21984 into a byte permutation control. */
21986 {
21991 /* Convert mask to vector of chars. */
21994 /* Replicate each of the input bytes into byte positions:
21995 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21996 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21997 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22004 else
22007 /* Convert it into the byte positions by doing
22008 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22014 }
22016 /* The actual shuffle operations all operate on V16QImode. */
22021 {
22028 }
22030 {
22037 }
22038 else
22039 {
22043 /* Shuffle the two input vectors independently. */
22049 merge_two:
22050 /* Then merge them together. The key is whether any given control
22051 element contained a bit set that indicates the second word. */
22055 {
22056 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22057 more shuffle to convert the V2DI input mask into a V4SI
22058 input mask. At which point the masking that expand_int_vcond
22059 will work as desired. */
22067 }
22089 }
22090 }
22092 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22093 true if we should do zero extension, else sign extension. HIGH_P is
22094 true if we want the N/2 high elements, else the low elements. */
22096 void
22098 {
22100 rtx tmp;
22103 {
22109 {
22113 else
22116 extract
22122 else
22125 extract
22131 else
22134 extract
22140 else
22143 extract
22149 else
22152 extract
22158 else
22164 else
22170 else
22175 }
22178 {
22181 }
22183 {
22184 /* Shift higher 8 bytes to lower 8 bytes. */
22189 }
22190 else
22194 }
22195 else
22196 {
22200 {
22204 else
22210 else
22216 else
22221 }
22225 else
22232 }
22233 }
22235 /* Expand conditional increment or decrement using adb/sbb instructions.
22236 The default case using setcc followed by the conditional move can be
22237 done by generic code. */
22238 bool
22240 {
22242 rtx flags;
22244 rtx compare_op;
22262 {
22265 }
22268 {
22272 reverse_condition_maybe_unordered
22274 else
22276 }
22280 /* Construct either adc or sbb insn. */
22282 {
22284 {
22299 }
22300 }
22301 else
22302 {
22304 {
22319 }
22320 }
22324 }
22327 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22328 but works for floating pointer parameters and nonoffsetable memories.
22329 For pushes, it returns just stack offsets; the values will be saved
22330 in the right order. Maximally three parts are generated. */
22332 static int
22334 {
22339 else
22345 /* Optimize constant pool reference to immediates. This is used by fp
22346 moves, that force all constants to memory to allow combining. */
22348 {
22352 }
22355 {
22356 /* The only non-offsetable memories we handle are pushes. */
22365 }
22368 {
22370 /* Caution: if we looked through a constant pool memory above,
22371 the operand may actually have a different mode now. That's
22372 ok, since we want to pun this all the way back to an integer. */
22376 }
22379 {
22382 else
22383 {
22387 {
22391 }
22393 {
22398 }
22400 {
22401 REAL_VALUE_TYPE r;
22406 {
22413 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22414 long double may not be 80-bit. */
22423 }
22426 }
22427 else
22429 }
22430 }
22431 else
22432 {
22436 {
22439 {
22443 }
22445 {
22449 }
22451 {
22452 REAL_VALUE_TYPE r;
22458 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22461 = gen_int_mode
22464 DImode);
22465 else
22472 = gen_int_mode
22475 DImode);
22476 else
22478 }
22479 else
22481 }
22482 }
22485 }
22487 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22488 Return false when normal moves are needed; true when all required
22489 insns have been emitted. Operands 2-4 contain the input values
22490 int the correct order; operands 5-7 contain the output values. */
22492 void
22494 {
22502 /* The DFmode expanders may ask us to move double.
22503 For 64bit target this is single move. By hiding the fact
22504 here we simplify i386.md splitters. */
22506 {
22507 /* Optimize constant pool reference to immediates. This is used by
22508 fp moves, that force all constants to memory to allow combining. */
22515 {
22518 }
22519 else
22524 }
22526 /* The only non-offsettable memory we handle is push. */
22529 else
22536 /* When emitting push, take care for source operands on the stack. */
22539 {
22542 /* Compensate for the stack decrement by 4. */
22547 /* src_base refers to the stack pointer and is
22548 automatically decreased by emitted push. */
22552 }
22554 /* We need to do copy in the right order in case an address register
22555 of the source overlaps the destination. */
22557 {
22558 rtx tmp;
22561 {
22565 collisions++;
22566 }
22568 /* Collision in the middle part can be handled by reordering. */
22570 {
22573 }
22577 {
22579 {
22582 }
22583 else
22584 {
22587 }
22588 }
22590 /* If there are more collisions, we can't handle it by reordering.
22591 Do an lea to the last part and use only one colliding move. */
22593 {
22594 rtx base;
22600 /* Handle the case when the last part isn't valid for lea.
22601 Happens in 64-bit mode storing the 12-byte XFmode. */
22608 {
22611 }
22612 }
22613 }
22616 {
22618 {
22620 {
22625 }
22627 {
22630 }
22631 }
22632 else
22633 {
22634 /* In 64bit mode we don't have 32bit push available. In case this is
22635 register, it is OK - we will just use larger counterpart. We also
22636 retype memory - these comes from attempt to avoid REX prefix on
22637 moving of second half of TFmode value. */
22639 {
22641 {
22652 }
22656 }
22657 }
22661 }
22663 /* Choose correct order to not overwrite the source before it is copied. */
22673 {
22675 {
22678 }
22679 }
22680 else
22681 {
22683 {
22686 }
22687 }
22689 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22691 {
22700 }
22706 }
22708 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22709 left shift by a constant, either using a single shift or
22710 a sequence of add instructions. */
22712 static void
22714 {
22720 {
22724 }
22725 else
22726 {
22729 }
22730 }
22732 void
22734 {
22743 {
22748 {
22754 }
22755 else
22756 {
22764 }
22766 }
22773 {
22774 /* Assuming we've chosen a QImode capable registers, then 1 << N
22775 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22777 {
22793 }
22795 /* Otherwise, we can get the same results by manually performing
22796 a bit extract operation on bit 5/6, and then performing the two
22797 shifts. The two methods of getting 0/1 into low/high are exactly
22798 the same size. Avoiding the shift in the bit extract case helps
22799 pentium4 a bit; no one else seems to care much either way. */
22800 else
22801 {
22806 HOST_WIDE_INT bits;
22807 rtx x;
22810 {
22816 }
22817 else
22818 {
22824 }
22828 else
22836 }
22841 }
22844 {
22845 /* For -1 << N, we can avoid the shld instruction, because we
22846 know that we're shifting 0...31/63 ones into a -1. */
22850 else
22852 }
22853 else
22854 {
22862 }
22867 {
22873 }
22874 else
22875 {
22880 }
22881 }
22883 void
22885 {
22895 {
22900 {
22906 }
22908 {
22917 }
22918 else
22919 {
22927 }
22928 }
22929 else
22930 {
22942 {
22950 scratch));
22951 }
22952 else
22953 {
22958 }
22959 }
22960 }
22962 void
22964 {
22974 {
22979 {
22986 }
22987 else
22988 {
22996 }
22997 }
22998 else
22999 {
23011 {
23017 scratch));
23018 }
23019 else
23020 {
23025 }
23026 }
23027 }
23029 /* Predict just emitted jump instruction to be taken with probability PROB. */
23030 static void
23032 {
23036 }
23038 /* Helper function for the string operations below. Dest VARIABLE whether
23039 it is aligned to VALUE bytes. If true, jump to the label. */
23040 static rtx
23042 {
23047 else
23053 else
23056 }
23058 /* Adjust COUNTER by the VALUE. */
23059 static void
23061 {
23066 }
23068 /* Zero extend possibly SImode EXP to Pmode register. */
23069 rtx
23071 {
23073 }
23075 /* Divide COUNTREG by SCALE. */
23076 static rtx
23078 {
23079 rtx sc;
23091 }
23093 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23094 DImode for constant loop counts. */
23096 static enum machine_mode
23098 {
23106 }
23108 /* Copy the address to a Pmode register. This is used for x32 to
23109 truncate DImode TLS address to a SImode register. */
23111 static rtx
23113 {
23116 else
23117 {
23120 }
23121 }
23123 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23124 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23125 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23126 memory by VALUE (supposed to be in MODE).
23128 The size is rounded down to whole number of chunk size moved at once.
23129 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23132 static void
23137 {
23143 rtx size;
23152 /* Those two should combine. */
23154 {
23158 }
23165 /* This assert could be relaxed - in this case we'll need to compute
23166 smallest power of two, containing in PIECE_SIZE_N and pass it to
23167 offset_address. */
23173 {
23177 /* When unrolling for chips that reorder memory reads and writes,
23178 we can save registers by using single temporary.
23179 Also using 4 temporaries is overkill in 32bit mode. */
23181 {
23183 {
23185 {
23186 destmem =
23188 srcmem =
23190 }
23192 }
23193 }
23194 else
23195 {
23199 {
23202 {
23203 srcmem =
23205 }
23207 }
23209 {
23211 {
23212 destmem =
23214 }
23216 }
23217 }
23218 }
23219 else
23221 {
23223 destmem =
23226 }
23236 {
23242 else
23244 }
23245 else
23253 {
23258 }
23260 }
23262 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23263 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23264 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23265 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23266 ORIG_VALUE is the original value passed to memset to fill the memory with.
23267 Other arguments have same meaning as for previous function. */
23269 static void
23272 rtx count,
23274 {
23275 rtx destexp;
23276 rtx srcexp;
23277 rtx countreg;
23278 HOST_WIDE_INT rounded_count;
23280 /* If possible, it is shorter to use rep movs.
23281 TODO: Maybe it is better to move this logic to decide_alg. */
23292 {
23296 }
23297 else
23300 {
23305 }
23310 {
23313 }
23314 else
23315 {
23319 {
23323 }
23324 else
23327 {
23332 }
23333 else
23334 {
23337 }
23340 }
23341 }
23343 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23344 DESTMEM.
23345 SRC is passed by pointer to be updated on return.
23346 Return value is updated DST. */
23347 static rtx
23349 HOST_WIDE_INT size_to_move)
23350 {
23356 /* Find the widest mode in which we could perform moves.
23357 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23358 it until move of such size is supported. */
23363 {
23367 }
23369 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23370 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23372 {
23377 {
23381 }
23382 }
23388 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23392 {
23393 /* We move from memory to memory, so we'll need to do it via
23394 a temporary register. */
23405 piece_size);
23407 piece_size);
23408 }
23410 /* Update DST and SRC rtx. */
23413 }
23415 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23416 static void
23419 {
23422 {
23427 /* For now MAX_SIZE should be a power of 2. This assert could be
23428 relaxed, but it'll require a bit more complicated epilogue
23429 expanding. */
23432 {
23435 }
23437 }
23439 {
23445 }
23447 /* When there are stringops, we can cheaply increase dest and src pointers.
23448 Otherwise we save code size by maintaining offset (zero is readily
23449 available from preceding rep operation) and using x86 addressing modes.
23450 */
23452 {
23454 {
23461 }
23463 {
23470 }
23472 {
23479 }
23480 }
23481 else
23482 {
23484 rtx tmp;
23487 {
23498 }
23500 {
23513 }
23515 {
23524 }
23525 }
23526 }
23528 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23529 with value PROMOTED_VAL.
23530 SRC is passed by pointer to be updated on return.
23531 Return value is updated DST. */
23532 static rtx
23534 HOST_WIDE_INT size_to_move)
23535 {
23541 /* Find the widest mode in which we could perform moves.
23542 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23543 it until move of such size is supported. */
23548 {
23551 }
23558 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23562 {
23564 {
23567 piece_size);
23569 }
23577 piece_size);
23578 }
23580 /* Update DST rtx. */
23582 }
23583 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23584 static void
23587 {
23588 count =
23594 }
23596 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23597 static void
23600 {
23601 rtx dest;
23604 {
23609 /* For now MAX_SIZE should be a power of 2. This assert could be
23610 relaxed, but it'll require a bit more complicated epilogue
23611 expanding. */
23614 {
23616 {
23619 else
23621 }
23622 }
23624 }
23626 {
23629 }
23631 {
23634 {
23639 }
23640 else
23641 {
23650 }
23653 }
23655 {
23658 {
23661 }
23662 else
23663 {
23668 }
23671 }
23673 {
23679 }
23681 {
23687 }
23689 {
23695 }
23696 }
23698 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23699 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23700 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23701 ignored.
23702 Return value is updated DESTMEM. */
23703 static rtx
23708 {
23711 {
23713 {
23716 {
23719 else
23721 }
23722 else
23728 }
23729 }
23731 }
23733 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23734 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23735 and jump to DONE_LABEL. */
23736 static void
23742 {
23745 rtx modesize;
23748 /* If we do not have vector value to copy, we must reduce size. */
23750 {
23752 {
23757 }
23758 else
23760 }
23761 else
23762 {
23763 /* Choose appropriate vector mode. */
23769 }
23774 {
23777 else
23778 {
23781 }
23783 }
23789 {
23793 }
23795 {
23798 else
23799 {
23802 }
23804 }
23810 }
23812 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23813 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23814 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23815 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23816 DONE_LABEL is a label after the whole copying sequence. The label is created
23817 on demand if *DONE_LABEL is NULL.
23818 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23819 bounds after the initial copies.
23821 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23822 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23823 we will dispatch to a library call for large blocks.
23825 In pseudocode we do:
23827 if (COUNT < SIZE)
23828 {
23829 Assume that SIZE is 4. Bigger sizes are handled analogously
23830 if (COUNT & 4)
23831 {
23832 copy 4 bytes from SRCPTR to DESTPTR
23833 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23834 goto done_label
23835 }
23836 if (!COUNT)
23837 goto done_label;
23838 copy 1 byte from SRCPTR to DESTPTR
23839 if (COUNT & 2)
23840 {
23841 copy 2 bytes from SRCPTR to DESTPTR
23842 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23843 }
23844 }
23845 else
23846 {
23847 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23848 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23850 OLD_DESPTR = DESTPTR;
23851 Align DESTPTR up to DESIRED_ALIGN
23852 SRCPTR += DESTPTR - OLD_DESTPTR
23853 COUNT -= DEST_PTR - OLD_DESTPTR
23854 if (DYNAMIC_CHECK)
23855 Round COUNT down to multiple of SIZE
23856 << optional caller supplied zero size guard is here >>
23857 << optional caller suppplied dynamic check is here >>
23858 << caller supplied main copy loop is here >>
23859 }
23860 done_label:
23861 */
23862 static void
23875 {
23878 rtx modesize;
23880 rtx mode_value;
23882 /* Chose proper value to copy. */
23885 else
23889 /* See if block is big or small, handle small blocks. */
23891 {
23902 /* Handle sizes > 3. */
23909 /* Nothing to copy? Jump to DONE_LABEL if so */
23913 /* Do a byte copy. */
23917 else
23918 {
23921 }
23923 /* Handle sizes 2 and 3. */
23930 else
23931 {
23936 }
23942 }
23943 else
23947 /* Start memcpy for COUNT >= SIZE. */
23949 {
23952 }
23954 /* Copy first desired_align bytes. */
23960 {
23963 else
23964 {
23967 }
23970 }
23973 /* Copy last SIZE bytes. */
23980 else
23981 {
23987 }
23989 {
23993 else
23994 {
23997 }
23998 }
24000 /* Align destination. */
24002 {
24006 /* Align destptr up, place it to new register. */
24013 /* See how many bytes we skipped. */
24017 /* Adjust srcptr and count. */
24023 /* We copied at most size + prolog_size. */
24026 else
24029 /* Our loops always round down the bock size, but for dispatch to library
24030 we need precise value. */
24034 }
24035 else
24036 {
24038 /* Decrease count, so we won't end up copying last word twice. */
24042 else
24046 }
24047 }
24050 /* This function is like the previous one, except here we know how many bytes
24051 need to be copied. That allows us to update alignment not only of DST, which
24052 is returned, but also of SRC, which is passed as a pointer for that
24053 reason. */
24054 static rtx
24059 {
24067 {
24071 }
24076 {
24078 {
24080 {
24083 else
24085 }
24086 else
24089 }
24090 }
24097 {
24103 {
24106 {
24110 }
24115 }
24119 }
24122 }
24124 /* Return true if ALG can be used in current context.
24125 Assume we expand memset if MEMSET is true. */
24126 static bool
24128 {
24133 /* Algorithms using the rep prefix want at least edi and ecx;
24134 additionally, memset wants eax and memcpy wants esi. Don't
24135 consider such algorithms if the user has appropriated those
24136 registers for their own purposes. */
24143 }
24145 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24146 static enum stringop_alg
24150 {
24161 /* Even if the string operation call is cold, we still might spend a lot
24162 of time processing large blocks. */
24168 else
24174 else
24177 /* See maximal size for user defined algorithm. */
24179 {
24186 }
24188 /* If expected size is not known but max size is small enough
24189 so inline version is a win, set expected size into
24190 the range. */
24195 /* If user specified the algorithm, honnor it if possible. */
24199 /* rep; movq or rep; movl is the smallest variant. */
24201 {
24206 else
24209 }
24210 /* Very tiny blocks are best handled via the loop, REP is expensive to
24211 setup. */
24215 {
24219 {
24220 /* We get here if the algorithms that were not libcall-based
24221 were rep-prefix based and we are unable to use rep prefixes
24222 based on global register usage. Break out of the loop and
24223 use the heuristic below. */
24227 {
24231 {
24234 }
24235 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24236 last non-libcall inline algorithm. */
24238 {
24239 /* When the current size is best to be copied by a libcall,
24240 but we are still forced to inline, run the heuristic below
24241 that will pick code for medium sized blocks. */
24243 {
24246 }
24249 }
24251 {
24254 }
24255 }
24256 }
24257 }
24258 /* When asked to inline the call anyway, try to pick meaningful choice.
24259 We look for maximal size of block that is faster to copy by hand and
24260 take blocks of at most of that size guessing that average size will
24261 be roughly half of the block.
24263 If this turns out to be bad, we might simply specify the preferred
24264 choice in ix86_costs. */
24268 {
24271 /* If there aren't any usable algorithms, then recursing on
24272 smaller sizes isn't going to find anything. Just return the
24273 simple byte-at-a-time copy loop. */
24275 {
24276 /* Pick something reasonable. */
24280 }
24288 else
24291 }
24294 }
24296 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24297 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24298 static int
24303 {
24314 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24315 copying whole cacheline at once. */
24328 }
24331 /* Helper function for memcpy. For QImode value 0xXY produce
24332 0xXYXYXYXY of wide specified by MODE. This is essentially
24333 a * 0x10101010, but we can do slightly better than
24334 synth_mult by unwinding the sequence by hand on CPUs with
24335 slow multiply. */
24336 static rtx
24338 {
24340 rtx tmp;
24347 {
24355 }
24364 nops--;
24369 {
24373 OPTAB_DIRECT);
24374 }
24375 else
24376 {
24382 else
24384 else
24385 {
24388 reg =
24390 }
24400 }
24401 }
24403 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24404 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24405 alignment from ALIGN to DESIRED_ALIGN. */
24406 static rtx
24409 {
24410 rtx promoted_val;
24419 else
24423 }
24425 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24426 operations when profitable. The code depends upon architecture, block size
24427 and alignment, but always has one of the following overall structures:
24429 Aligned move sequence:
24431 1) Prologue guard: Conditional that jumps up to epilogues for small
24432 blocks that can be handled by epilogue alone. This is faster
24433 but also needed for correctness, since prologue assume the block
24434 is larger than the desired alignment.
24436 Optional dynamic check for size and libcall for large
24437 blocks is emitted here too, with -minline-stringops-dynamically.
24439 2) Prologue: copy first few bytes in order to get destination
24440 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24441 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24442 copied. We emit either a jump tree on power of two sized
24443 blocks, or a byte loop.
24445 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24446 with specified algorithm.
24448 4) Epilogue: code copying tail of the block that is too small to be
24449 handled by main body (or up to size guarded by prologue guard).
24451 Misaligned move sequence
24453 1) missaligned move prologue/epilogue containing:
24454 a) Prologue handling small memory blocks and jumping to done_label
24455 (skipped if blocks are known to be large enough)
24456 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24457 needed by single possibly misaligned move
24458 (skipped if alignment is not needed)
24459 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24461 2) Zero size guard dispatching to done_label, if needed
24463 3) dispatch to library call, if needed,
24465 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24466 with specified algorithm. */
24467 bool
24473 {
24474 rtx destreg;
24477 rtx tmp;
24493 /* TODO: Once value ranges are available, fill in proper data. */
24501 /* i386 can do misaligned access on reasonably increased cost. */
24505 /* ALIGN is the minimum of destination and source alignment, but we care here
24506 just about destination alignment. */
24512 {
24515 /* When COUNT is 0, there is nothing to do. */
24518 }
24519 else
24520 {
24529 }
24531 /* Make sure we don't need to care about overflow later on. */
24535 /* Step 0: Decide on preferred algorithm, desired alignment and
24536 size of chunks to be copied by main loop. */
24538 issetmem,
24545 /* For now vector-version of memset is generated only for memory zeroing, as
24546 creating of promoted vector value is very cheap in this case. */
24559 {
24578 /* Find the widest supported mode. */
24584 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24585 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24587 {
24592 }
24604 }
24612 /* Step 1: Prologue guard. */
24614 /* Alignment code needs count to be in register. */
24616 {
24619 {
24620 align_bytes
24624 else
24626 }
24629 }
24632 /* Misaligned move sequences handle both prologue and epilogue at once.
24633 Default code generation results in a smaller code for large alignments
24634 and also avoids redundant job when sizes are known precisely. */
24635 misaligned_prologue_used
24636 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24642 /* Do the cheap promotion to allow better CSE across the
24643 main loop and epilogue (ie one load of the big constant in the
24644 front of all code.
24645 For now the misaligned move sequences do not have fast path
24646 without broadcasting. */
24648 {
24650 {
24656 }
24657 else
24658 {
24661 }
24662 }
24663 /* Misaligned move sequences handles both prologues and epilogues at once.
24664 Default code generation results in smaller code for large alignments and
24665 also avoids redundant job when sizes are known precisely. */
24667 {
24668 /* Misaligned move prologue handled small blocks by itself. */
24669 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24674 desired_align < align
24683 {
24684 /* It is possible that we copied enough so the main loop will not
24685 execute. */
24695 else
24697 }
24698 }
24699 /* Ensure that alignment prologue won't copy past end of block. */
24701 {
24703 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24704 Make sure it is power of 2. */
24707 /* To improve performance of small blocks, we jump around the VAL
24708 promoting mode. This mean that if the promoted VAL is not constant,
24709 we might not use it in the epilogue and have to use byte
24710 loop variant. */
24715 {
24716 /* If main algorithm works on QImode, no epilogue is needed.
24717 For small sizes just don't align anything. */
24720 else
24722 }
24725 {
24732 else
24734 }
24735 }
24737 /* Emit code to decide on runtime whether library call or inline should be
24738 used. */
24740 {
24742 {
24744 {
24748 }
24749 }
24750 else
24751 {
24761 else
24765 }
24766 }
24768 /* Step 2: Alignment prologue. */
24769 /* Do the expensive promotion once we branched off the small blocks. */
24775 {
24777 {
24778 /* Except for the first move in prologue, we no longer know
24779 constant offset in aliasing info. It don't seems to worth
24780 the pain to maintain it for the first move, so throw away
24781 the info early. */
24788 issetmem);
24789 /* At most desired_align - align bytes are copied. */
24792 else
24794 }
24795 else
24796 {
24797 /* If we know how many bytes need to be stored before dst is
24798 sufficiently aligned, maintain aliasing info accurately. */
24800 srcreg,
24801 promoted_val,
24802 vec_promoted_val,
24803 desired_align,
24804 align_bytes,
24805 issetmem);
24812 }
24814 && !min_size
24819 {
24820 /* It is possible that we copied enough so the main loop will not
24821 execute. */
24831 else
24833 }
24834 }
24836 {
24843 }
24847 /* Step 3: Main loop. */
24850 {
24873 }
24874 /* Adjust properly the offset of src and dest memory for aliasing. */
24876 {
24882 }
24883 else
24884 {
24888 }
24890 /* Step 4: Epilogue to copy the remaining bytes. */
24891 epilogue:
24893 {
24894 /* When the main loop is done, COUNT_EXP might hold original count,
24895 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24896 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24897 bytes. Compensate if needed. */
24900 {
24901 tmp =
24904 OPTAB_DIRECT);
24907 }
24910 }
24913 {
24916 epilogue_size_needed);
24917 else
24918 {
24922 epilogue_size_needed);
24923 else
24925 epilogue_size_needed);
24926 }
24927 }
24931 }
24934 /* Expand the appropriate insns for doing strlen if not just doing
24935 repnz; scasb
24937 out = result, initialized with the start address
24938 align_rtx = alignment of the address.
24939 scratch = scratch register, initialized with the startaddress when
24940 not aligned, otherwise undefined
24942 This is just the body. It needs the initializations mentioned above and
24943 some address computing at the end. These things are done in i386.md. */
24945 static void
24947 {
24949 rtx tmp;
24954 rtx mem;
24957 rtx cmp;
24963 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24965 /* Is there a known alignment and is it less than 4? */
24967 {
24970 /* Is there a known alignment and is it not 2? */
24972 {
24976 /* Leave just the 3 lower bits. */
24986 }
24987 else
24988 {
24989 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24990 check if is aligned to 4 - byte. */
24997 }
25001 /* Now compare the bytes. */
25003 /* Compare the first n unaligned byte on a byte per byte basis. */
25007 /* Increment the address. */
25010 /* Not needed with an alignment of 2 */
25012 {
25016 end_0_label);
25021 }
25024 end_0_label);
25027 }
25029 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25030 align this loop. It gives only huge programs, but does not help to
25031 speed up. */
25038 /* This formula yields a nonzero result iff one of the bytes is zero.
25039 This saves three branches inside loop and many cycles. */
25047 align_4_label);
25050 {
25056 /* If zero is not in the first two bytes, move two bytes forward. */
25062 reg,
25063 tmpreg)));
25064 /* Emit lea manually to avoid clobbering of flags. */
25072 reg2,
25073 out)));
25074 }
25075 else
25076 {
25078 /* Is zero in the first two bytes? */
25085 pc_rtx);
25089 /* Not in the first two. Move two bytes forward. */
25095 }
25097 /* Avoid branch in fixing the byte. */
25105 }
25107 /* Expand strlen. */
25109 bool
25111 {
25114 /* The generic case of strlen expander is long. Avoid it's
25115 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25118 && !TARGET_INLINE_ALL_STRINGOPS
25128 {
25129 /* Well it seems that some optimizer does not combine a call like
25130 foo(strlen(bar), strlen(bar));
25131 when the move and the subtraction is done here. It does calculate
25132 the length just once when these instructions are done inside of
25133 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25134 often used and I use one fewer register for the lifetime of
25135 output_strlen_unroll() this is better. */
25141 /* strlensi_unroll_1 returns the address of the zero at the end of
25142 the string, like memchr(), so compute the length by subtracting
25143 the start address. */
25145 }
25146 else
25147 {
25148 rtx unspec;
25150 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25163 /* If .md starts supporting :P, this can be done in .md. */
25169 }
25171 }
25173 /* For given symbol (function) construct code to compute address of it's PLT
25174 entry in large x86-64 PIC model. */
25175 static rtx
25177 {
25190 }
25192 rtx
25194 rtx callarg2,
25196 {
25197 unsigned int const cregs_size
25208 {
25209 #if TARGET_MACHO
25212 #endif
25213 }
25214 else
25215 {
25216 /* Static functions and indirect calls don't need the pic register. Also,
25217 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25218 it an indirect call. */
25220 && (!TARGET_64BIT
25225 && flag_plt
25230 }
25233 {
25237 }
25240 && !TARGET_PECOFF
25248 {
25251 }
25259 {
25263 }
25267 {
25271 UNSPEC_MS_TO_SYSV_CALL);
25274 {
25280 }
25281 }
25290 }
25292 /* Return true if the function being called was marked with attribute "noplt"
25293 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25294 handle the non-PIC case in the backend because there is no easy interface
25295 for the front-end to force non-PLT calls to use the GOT. This is currently
25296 used only with 64-bit ELF targets to call the function marked "noplt"
25297 indirectly. */
25299 static bool
25301 {
25315 }
25317 /* Output the assembly for a call instruction. */
25321 {
25327 {
25332 /* SEH epilogue detection requires the indirect branch case
25333 to include REX.W. */
25336 else
25339 /* Just before the sibling call, add 11-bytes of nops to patch function
25340 exit: 2 bytes for 'jmp 09' and remaining 9 bytes. */
25343 asm_out_file,
25344 FUNCTION_PATCH_EPILOGUE_SECTION,
25350 }
25352 /* SEH unwinding can require an extra nop to be emitted in several
25353 circumstances. Determine if we have one of those. */
25355 {
25356 rtx i;
25359 {
25360 /* If we get to another real insn, we don't need the nop. */
25364 /* If we get to the epilogue note, prevent a catch region from
25365 being adjacent to the standard epilogue sequence. If non-
25366 call-exceptions, we'll have done this during epilogue emission. */
25368 && !flag_non_call_exceptions
25370 {
25373 }
25374 }
25376 /* If we didn't find a real insn following the call, prevent the
25377 unwinder from looking into the next function. */
25380 }
25386 else
25395 }
25396 \f
25397 /* Clear stack slot assignments remembered from previous functions.
25398 This is called from INIT_EXPANDERS once before RTL is emitted for each
25399 function. */
25403 {
25411 }
25413 /* Return a MEM corresponding to a stack slot with mode MODE.
25414 Allocate a new slot if necessary.
25416 The RTL for a function can have several slots available: N is
25417 which slot to use. */
25419 rtx
25421 {
25438 }
25440 static void
25442 {
25448 }
25449 \f
25450 /* Check whether x86 address PARTS is a pc-relative address. */
25452 static bool
25454 {
25462 {
25464 {
25481 }
25482 }
25484 }
25486 /* Calculate the length of the memory address in the instruction encoding.
25487 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25488 or other prefixes. We never generate addr32 prefix for LEA insn. */
25490 int
25492 {
25509 /* If this is not LEA instruction, add the length of addr32 prefix. */
25514 len++;
25528 /* Rule of thumb:
25529 - esp as the base always wants an index,
25530 - ebp as the base always wants a displacement,
25531 - r12 as the base always wants an index,
25532 - r13 as the base always wants a displacement. */
25534 /* Register Indirect. */
25536 {
25537 /* esp (for its index) and ebp (for its displacement) need
25538 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25539 code. */
25546 len++;
25547 }
25549 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25550 is not disp32, but disp32(%rip), so for disp32
25551 SIB byte is needed, unless print_operand_address
25552 optimizes it into disp32(%rip) or (%rip) is implied
25553 by UNSPEC. */
25555 {
25558 len++;
25559 }
25560 else
25561 {
25562 /* Find the length of the displacement constant. */
25564 {
25567 else
25569 }
25570 /* ebp always wants a displacement. Similarly r13. */
25572 len++;
25574 /* An index requires the two-byte modrm form.... */
25576 /* ...like esp (or r12), which always wants an index. */
25580 len++;
25581 }
25584 }
25586 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25587 is set, expect that insn have 8bit immediate alternative. */
25588 int
25590 {
25596 {
25601 {
25604 {
25616 }
25618 {
25621 }
25622 }
25624 {
25634 /* Immediates for DImode instructions are encoded
25635 as 32bit sign extended values. */
25641 }
25642 }
25644 }
25646 /* Compute default value for "length_address" attribute. */
25647 int
25649 {
25653 {
25664 }
25669 {
25672 {
25677 constraints++;
25680 ;
25681 /* Skip ignored operands. */
25684 }
25686 }
25688 }
25690 /* Compute default value for "length_vex" attribute. It includes
25691 2 or 3 byte VEX prefix and 1 opcode byte. */
25693 int
25695 {
25698 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25699 byte VEX prefix. */
25703 /* We can always use 2 byte VEX prefix in 32bit. */
25711 {
25712 /* REX.W bit uses 3 byte VEX prefix. */
25716 }
25717 else
25718 {
25719 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25723 }
25726 }
25727 \f
25728 /* Return the maximum number of instructions a cpu can issue. */
25730 static int
25732 {
25734 {
25765 }
25766 }
25768 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25769 by DEP_INSN and nothing set by DEP_INSN. */
25771 static bool
25773 {
25776 /* Simplify the test for uninteresting insns. */
25784 {
25787 }
25792 {
25795 }
25796 else
25802 /* This test is true if the dependent insn reads the flags but
25803 not any other potentially set register. */
25811 }
25813 /* Return true iff USE_INSN has a memory address with operands set by
25814 SET_INSN. */
25816 bool
25818 {
25823 {
25826 }
25828 }
25830 /* Helper function for exact_store_load_dependency.
25831 Return true if addr is found in insn. */
25832 static bool
25834 {
25841 {
25847 CASE_CONST_ANY:
25856 }
25860 {
25862 {
25872 }
25873 }
25875 }
25877 /* Return true if there exists exact dependency for store & load, i.e.
25878 the same memory address is used in them. */
25879 static bool
25881 {
25895 }
25897 static int
25899 {
25905 /* Anti and output dependencies have zero cost on all CPUs. */
25911 /* If we can't recognize the insns, we can't really do anything. */
25919 {
25921 /* Address Generation Interlock adds a cycle of latency. */
25923 {
25934 }
25938 /* ??? Compares pair with jump/setcc. */
25942 /* Floating point stores require value to be ready one cycle earlier. */
25950 /* INT->FP conversion is expensive. */
25954 /* There is one cycle extra latency between an FP op and a store. */
25964 /* Show ability of reorder buffer to hide latency of load by executing
25965 in parallel with previous instruction in case
25966 previous instruction is not needed to compute the address. */
25969 {
25970 /* Claim moves to take one cycle, as core can issue one load
25971 at time and the next load can start cycle later. */
25976 cost--;
25977 }
25981 /* The esp dependency is resolved before
25982 the instruction is really finished. */
25987 /* INT->FP conversion is expensive. */
25993 /* Show ability of reorder buffer to hide latency of load by executing
25994 in parallel with previous instruction in case
25995 previous instruction is not needed to compute the address. */
25998 {
25999 /* Claim moves to take one cycle, as core can issue one load
26000 at time and the next load can start cycle later. */
26006 else
26008 }
26019 /* Stack engine allows to execute push&pop instructions in parall. */
26023 /* FALLTHRU */
26029 /* Show ability of reorder buffer to hide latency of load by executing
26030 in parallel with previous instruction in case
26031 previous instruction is not needed to compute the address. */
26034 {
26038 /* Because of the difference between the length of integer and
26039 floating unit pipeline preparation stages, the memory operands
26040 for floating point are cheaper.
26042 ??? For Athlon it the difference is most probably 2. */
26045 else
26050 else
26052 }
26059 /* Stack engine allows to execute push&pop instructions in parall. */
26066 /* Show ability of reorder buffer to hide latency of load by executing
26067 in parallel with previous instruction in case
26068 previous instruction is not needed to compute the address. */
26071 {
26074 else
26076 }
26084 /* Increase cost of integer loads. */
26087 {
26090 {
26093 else
26094 {
26095 /* Increase cost of ld/st for short int types only
26096 because of store forwarding issue. */
26100 {
26101 /* Increase cost of store/load insn if exact
26102 dependence exists and it is load insn. */
26107 }
26108 }
26109 }
26110 }
26114 }
26117 }
26119 /* How many alternative schedules to try. This should be as wide as the
26120 scheduling freedom in the DFA, but no wider. Making this value too
26121 large results extra work for the scheduler. */
26123 static int
26125 {
26127 {
26139 /* We use lookahead value 4 for BD both before and after reload
26140 schedules. Plan is to have value 8 included for O3. */
26150 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26151 as many instructions can be executed on a cycle, i.e.,
26152 issue_rate. I wonder why tuning for many CPUs does not do this. */
26155 /* Don't use lookahead for pre-reload schedule to save compile time. */
26160 }
26161 }
26163 /* Return true if target platform supports macro-fusion. */
26165 static bool
26167 {
26169 }
26171 /* Check whether current microarchitecture support macro fusion
26172 for insn pair "CONDGEN + CONDJMP". Refer to
26173 "Intel Architectures Optimization Reference Manual". */
26175 static bool
26177 {
26196 else
26197 {
26202 {
26206 else
26208 }
26209 }
26216 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26217 supported. */
26224 /* No fusion for RIP-relative address. */
26231 ix86_address parts;
26237 }
26242 /* Check whether conditional jump use Sign or Overflow Flags. */
26250 /* Return true for TYPE_TEST and TYPE_ICMP. */
26255 /* The following is the case that macro-fusion for alu + jmp. */
26259 /* No fusion for alu op with memory destination operand. */
26264 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26265 supported. */
26274 }
26276 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26277 execution. It is applied if
26278 (1) IMUL instruction is on the top of list;
26279 (2) There exists the only producer of independent IMUL instruction in
26280 ready list.
26281 Return index of IMUL producer if it was found and -1 otherwise. */
26282 static int
26284 {
26286 sd_iterator_def sd_it;
26287 dep_t dep;
26294 /* Check that IMUL instruction is on the top of ready list. */
26303 /* Search for producer of independent IMUL instruction. */
26305 {
26309 /* Skip IMUL instruction. */
26319 {
26320 rtx con;
26331 {
26332 sd_iterator_def sd_it1;
26333 dep_t dep1;
26334 /* Check if there is no other dependee for IMUL. */
26337 {
26338 rtx pro;
26344 }
26347 }
26348 }
26351 }
26353 }
26355 /* Try to find the best candidate on the top of ready list if two insns
26356 have the same priority - candidate is best if its dependees were
26357 scheduled earlier. Applied for Silvermont only.
26358 Return true if top 2 insns must be interchanged. */
26359 static bool
26361 {
26364 rtx set;
26365 sd_iterator_def sd_it;
26366 dep_t dep;
26369 #define INSN_TICK(INSN) (HID (INSN)->tick)
26390 {
26393 /* Determine winner more precise. */
26395 {
26396 rtx pro;
26402 }
26404 {
26405 rtx pro;
26411 }
26414 {
26415 /* Determine winner - load must win. */
26421 }
26423 }
26425 #undef INSN_TICK
26426 }
26428 /* Perform possible reodering of ready list for Atom/Silvermont only.
26429 Return issue rate. */
26430 static int
26433 {
26437 rtx insn;
26440 /* Set up issue rate. */
26443 /* Do reodering for BONNELL/SILVERMONT only. */
26447 /* Nothing to do if ready list contains only 1 instruction. */
26451 /* Do reodering for post-reload scheduler only. */
26456 {
26461 /* Put IMUL producer (ready[index]) at the top of ready list. */
26467 }
26469 {
26473 /* Swap 2 top elements of ready list. */
26477 }
26479 }
26481 static bool
26484 /* Returns true if lhs of insn is HW function argument register and set up
26485 is_spilled to true if it is likely spilled HW register. */
26486 static bool
26488 {
26489 rtx dst;
26493 /* Call instructions are not movable, ignore it. */
26504 {
26505 /* Is it likely spilled HW register? */
26510 }
26512 }
26514 /* Add output dependencies for chain of function adjacent arguments if only
26515 there is a move to likely spilled HW register. Return first argument
26516 if at least one dependence was added or NULL otherwise. */
26517 static rtx
26519 {
26520 rtx insn;
26527 /* Find nearest to call argument passing instruction. */
26529 {
26538 }
26542 {
26549 {
26552 }
26554 {
26555 /* Add output depdendence between two function arguments if chain
26556 of output arguments contains likely spilled HW registers. */
26560 }
26561 else
26563 }
26567 }
26569 /* Add output or anti dependency from insn to first_arg to restrict its code
26570 motion. */
26571 static void
26573 {
26574 rtx set;
26575 rtx tmp;
26582 {
26583 /* Add output dependency to the first function argument. */
26586 }
26587 /* Add anti dependency. */
26589 }
26591 /* Avoid cross block motion of function argument through adding dependency
26592 from the first non-jump instruction in bb. */
26593 static void
26595 {
26599 {
26601 {
26604 {
26607 }
26608 }
26612 }
26613 }
26615 /* Hook for pre-reload schedule - avoid motion of function arguments
26616 passed in likely spilled HW registers. */
26617 static void
26619 {
26620 rtx insn;
26628 {
26631 {
26632 /* Add dependee for first argument to predecessors if only
26633 region contains more than one block. */
26637 /* Skip trivial regions and region head blocks that can have
26638 predecessors outside of region. */
26640 {
26641 edge e;
26642 edge_iterator ei;
26644 /* Regions are SCCs with the exception of selective
26645 scheduling with pipelining of outer blocks enabled.
26646 So also check that immediate predecessors of a non-head
26647 block are in the same region. */
26649 {
26650 /* Avoid creating of loop-carried dependencies through
26651 using topological ordering in the region. */
26655 }
26656 }
26660 }
26661 }
26664 }
26666 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26667 HW registers to maximum, to schedule them at soon as possible. These are
26668 moves from function argument registers at the top of the function entry
26669 and moves from function return value registers after call. */
26670 static int
26672 {
26673 rtx set;
26683 {
26690 }
26693 }
26695 /* Model decoder of Core 2/i7.
26696 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26697 track the instruction fetch block boundaries and make sure that long
26698 (9+ bytes) instructions are assigned to D0. */
26700 /* Maximum length of an insn that can be handled by
26701 a secondary decoder unit. '8' for Core 2/i7. */
26704 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26705 '16' for Core 2/i7. */
26708 /* Maximum number of instructions decoder can handle per cycle.
26709 '6' for Core 2/i7. */
26713 ix86_first_cycle_multipass_data_t;
26715 const_ix86_first_cycle_multipass_data_t;
26717 /* A variable to store target state across calls to max_issue within
26718 one cycle. */
26722 /* Initialize DATA. */
26723 static void
26725 {
26726 ix86_first_cycle_multipass_data_t data
26733 }
26735 /* Advancing the cycle; reset ifetch block counts. */
26736 static void
26738 {
26745 }
26749 /* Filter out insns from ready_try that the core will not be able to issue
26750 on current cycle due to decoder. */
26751 static void
26752 core2i7_first_cycle_multipass_filter_ready_try
26755 {
26757 {
26758 rtx insn;
26768 (!first_cycle_insn_p
26770 /* ... or it would not fit into the ifetch block ... */
26772 /* ... or the decoder is full already ... */
26774 /* ... mask the insn out. */
26775 {
26780 }
26781 }
26782 }
26784 /* Prepare for a new round of multipass lookahead scheduling. */
26785 static void
26788 {
26789 ix86_first_cycle_multipass_data_t data
26791 const_ix86_first_cycle_multipass_data_t prev_data
26794 /* Restore the state from the end of the previous round. */
26798 /* Filter instructions that cannot be issued on current cycle due to
26799 decoder restrictions. */
26801 first_cycle_insn_p);
26802 }
26804 /* INSN is being issued in current solution. Account for its impact on
26805 the decoder model. */
26806 static void
26809 {
26810 ix86_first_cycle_multipass_data_t data
26812 const_ix86_first_cycle_multipass_data_t prev_data
26822 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26824 {
26827 }
26829 {
26833 }
26836 /* Filter out insns from ready_try that the core will not be able to issue
26837 on current cycle due to decoder. */
26840 }
26842 /* Revert the effect on ready_try. */
26843 static void
26847 {
26848 const_ix86_first_cycle_multipass_data_t data
26851 sbitmap_iterator sbi;
26855 {
26857 }
26858 }
26860 /* Save the result of multipass lookahead scheduling for the next round. */
26861 static void
26863 {
26864 const_ix86_first_cycle_multipass_data_t data
26866 ix86_first_cycle_multipass_data_t next_data
26870 {
26873 }
26874 }
26876 /* Deallocate target data. */
26877 static void
26879 {
26880 ix86_first_cycle_multipass_data_t data
26884 {
26888 }
26889 }
26891 /* Prepare for scheduling pass. */
26892 static void
26896 {
26897 /* Install scheduling hooks for current CPU. Some of these hooks are used
26898 in time-critical parts of the scheduler, so we only set them up when
26899 they are actually used. */
26901 {
26906 /* Do not perform multipass scheduling for pre-reload schedule
26907 to save compile time. */
26909 {
26925 /* Set decoder parameters. */
26930 }
26931 /* ... Fall through ... */
26941 }
26942 }
26944 \f
26945 /* Compute the alignment given to a constant that is being placed in memory.
26946 EXP is the constant and ALIGN is the alignment that the object would
26947 ordinarily have.
26948 The value of this function is used instead of that alignment to align
26949 the object. */
26951 int
26953 {
26956 {
26961 }
26967 }
26969 /* Compute the alignment for a static variable.
26970 TYPE is the data type, and ALIGN is the alignment that
26971 the object would ordinarily have. The value of this function is used
26972 instead of that alignment to align the object. */
26974 int
26976 {
26977 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26978 for symbols from other compilation units or symbols that don't need
26979 to bind locally. In order to preserve some ABI compatibility with
26980 those compilers, ensure we don't decrease alignment from what we
26981 used to assume. */
26983 int max_align_compat
26986 /* A data structure, equal or greater than the size of a cache line
26987 (64 bytes in the Pentium 4 and other recent Intel processors, including
26988 processors based on Intel Core microarchitecture) should be aligned
26989 so that its base address is a multiple of a cache line size. */
26991 int max_align
27001 {
27010 }
27012 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27013 to 16byte boundary. */
27015 {
27022 }
27028 {
27033 }
27035 {
27042 }
27047 {
27052 }
27055 {
27060 }
27063 }
27065 /* Compute the alignment for a local variable or a stack slot. EXP is
27066 the data type or decl itself, MODE is the widest mode available and
27067 ALIGN is the alignment that the object would ordinarily have. The
27068 value of this macro is used instead of that alignment to align the
27069 object. */
27071 unsigned int
27074 {
27078 {
27081 }
27082 else
27083 {
27086 }
27088 /* Don't do dynamic stack realignment for long long objects with
27089 -mpreferred-stack-boundary=2. */
27098 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27099 register in MODE. We will return the largest alignment of XF
27100 and DF. */
27102 {
27106 }
27108 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27109 to 16byte boundary. Exact wording is:
27111 An array uses the same alignment as its elements, except that a local or
27112 global array variable of length at least 16 bytes or
27113 a C99 variable-length array variable always has alignment of at least 16 bytes.
27115 This was added to allow use of aligned SSE instructions at arrays. This
27116 rule is meant for static storage (where compiler can not do the analysis
27117 by itself). We follow it for automatic variables only when convenient.
27118 We fully control everything in the function compiled and functions from
27119 other unit can not rely on the alignment.
27121 Exclude va_list type. It is the common case of local array where
27122 we can not benefit from the alignment.
27124 TODO: Probably one should optimize for size only when var is not escaping. */
27127 {
27137 }
27139 {
27144 }
27146 {
27152 }
27157 {
27162 }
27165 {
27171 }
27173 }
27175 /* Compute the minimum required alignment for dynamic stack realignment
27176 purposes for a local variable, parameter or a stack slot. EXP is
27177 the data type or decl itself, MODE is its mode and ALIGN is the
27178 alignment that the object would ordinarily have. */
27180 unsigned int
27183 {
27187 {
27190 }
27191 else
27192 {
27195 }
27200 /* Don't do dynamic stack realignment for long long objects with
27201 -mpreferred-stack-boundary=2. */
27208 }
27209 \f
27210 /* Find a location for the static chain incoming to a nested function.
27211 This is a register, unless all free registers are used by arguments. */
27213 static rtx
27215 {
27222 {
27223 /* We always use R10 in 64-bit mode. */
27225 }
27226 else
27227 {
27228 tree fntype;
27231 /* By default in 32-bit mode we use ECX to pass the static chain. */
27237 {
27238 /* Fastcall functions use ecx/edx for arguments, which leaves
27239 us with EAX for the static chain.
27240 Thiscall functions use ecx for arguments, which also
27241 leaves us with EAX for the static chain. */
27243 }
27245 {
27246 /* Thiscall functions use ecx for arguments, which leaves
27247 us with EAX and EDX for the static chain.
27248 We are using for abi-compatibility EAX. */
27250 }
27252 {
27253 /* For regparm 3, we have no free call-clobbered registers in
27254 which to store the static chain. In order to implement this,
27255 we have the trampoline push the static chain to the stack.
27256 However, we can't push a value below the return address when
27257 we call the nested function directly, so we have to use an
27258 alternate entry point. For this we use ESI, and have the
27259 alternate entry point push ESI, so that things appear the
27260 same once we're executing the nested function. */
27262 {
27268 }
27270 }
27271 }
27274 }
27276 /* Emit RTL insns to initialize the variable parts of a trampoline.
27277 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27278 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27279 to be passed to the target function. */
27281 static void
27283 {
27291 {
27294 /* Load the function address to r11. Try to load address using
27295 the shorter movl instead of movabs. We may want to support
27296 movq for kernel mode, but kernel does not use trampolines at
27297 the moment. FNADDR is a 32bit address and may not be in
27298 DImode when ptr_mode == SImode. Always use movl in this
27299 case. */
27302 {
27311 }
27312 else
27313 {
27320 }
27322 /* Load static chain using movabs to r10. Use the shorter movl
27323 instead of movabs when ptr_mode == SImode. */
27325 {
27328 }
27329 else
27330 {
27333 }
27342 /* Jump to r11; the last (unused) byte is a nop, only there to
27343 pad the write out to a single 32-bit store. */
27347 }
27348 else
27349 {
27352 /* Depending on the static chain location, either load a register
27353 with a constant, or push the constant to the stack. All of the
27354 instructions are the same size. */
27357 {
27359 {
27366 }
27367 }
27368 else
27383 /* Compute offset from the end of the jmp to the target function.
27384 In the case in which the trampoline stores the static chain on
27385 the stack, we need to skip the first insn which pushes the
27386 (call-saved) register static chain; this push is 1 byte. */
27393 }
27397 #ifdef HAVE_ENABLE_EXECUTE_STACK
27398 #ifdef CHECK_EXECUTE_STACK_ENABLED
27400 #endif
27403 #endif
27404 }
27405 \f
27406 /* The following file contains several enumerations and data structures
27407 built from the definitions in i386-builtin-types.def. */
27411 /* Table for the ix86 builtin non-function types. */
27414 /* Retrieve an element from the above table, building some of
27415 the types lazily. */
27417 static tree
27419 {
27431 {
27439 }
27440 else
27441 {
27447 else
27455 }
27459 }
27461 /* Table for the ix86 builtin function types. */
27464 /* Retrieve an element from the above table, building some of
27465 the types lazily. */
27467 static tree
27469 {
27470 tree type;
27479 {
27487 {
27490 }
27493 }
27494 else
27495 {
27501 }
27505 }
27508 /* Codes for all the SSE/MMX builtins. */
27509 enum ix86_builtins
27510 {
27511 IX86_BUILTIN_ADDPS,
27512 IX86_BUILTIN_ADDSS,
27513 IX86_BUILTIN_DIVPS,
27514 IX86_BUILTIN_DIVSS,
27515 IX86_BUILTIN_MULPS,
27516 IX86_BUILTIN_MULSS,
27517 IX86_BUILTIN_SUBPS,
27518 IX86_BUILTIN_SUBSS,
27520 IX86_BUILTIN_CMPEQPS,
27521 IX86_BUILTIN_CMPLTPS,
27522 IX86_BUILTIN_CMPLEPS,
27523 IX86_BUILTIN_CMPGTPS,
27524 IX86_BUILTIN_CMPGEPS,
27525 IX86_BUILTIN_CMPNEQPS,
27526 IX86_BUILTIN_CMPNLTPS,
27527 IX86_BUILTIN_CMPNLEPS,
27528 IX86_BUILTIN_CMPNGTPS,
27529 IX86_BUILTIN_CMPNGEPS,
27530 IX86_BUILTIN_CMPORDPS,
27531 IX86_BUILTIN_CMPUNORDPS,
27532 IX86_BUILTIN_CMPEQSS,
27533 IX86_BUILTIN_CMPLTSS,
27534 IX86_BUILTIN_CMPLESS,
27535 IX86_BUILTIN_CMPNEQSS,
27536 IX86_BUILTIN_CMPNLTSS,
27537 IX86_BUILTIN_CMPNLESS,
27538 IX86_BUILTIN_CMPORDSS,
27539 IX86_BUILTIN_CMPUNORDSS,
27541 IX86_BUILTIN_COMIEQSS,
27542 IX86_BUILTIN_COMILTSS,
27543 IX86_BUILTIN_COMILESS,
27544 IX86_BUILTIN_COMIGTSS,
27545 IX86_BUILTIN_COMIGESS,
27546 IX86_BUILTIN_COMINEQSS,
27547 IX86_BUILTIN_UCOMIEQSS,
27548 IX86_BUILTIN_UCOMILTSS,
27549 IX86_BUILTIN_UCOMILESS,
27550 IX86_BUILTIN_UCOMIGTSS,
27551 IX86_BUILTIN_UCOMIGESS,
27552 IX86_BUILTIN_UCOMINEQSS,
27554 IX86_BUILTIN_CVTPI2PS,
27555 IX86_BUILTIN_CVTPS2PI,
27556 IX86_BUILTIN_CVTSI2SS,
27557 IX86_BUILTIN_CVTSI642SS,
27558 IX86_BUILTIN_CVTSS2SI,
27559 IX86_BUILTIN_CVTSS2SI64,
27560 IX86_BUILTIN_CVTTPS2PI,
27561 IX86_BUILTIN_CVTTSS2SI,
27562 IX86_BUILTIN_CVTTSS2SI64,
27564 IX86_BUILTIN_MAXPS,
27565 IX86_BUILTIN_MAXSS,
27566 IX86_BUILTIN_MINPS,
27567 IX86_BUILTIN_MINSS,
27569 IX86_BUILTIN_LOADUPS,
27570 IX86_BUILTIN_STOREUPS,
27571 IX86_BUILTIN_MOVSS,
27573 IX86_BUILTIN_MOVHLPS,
27574 IX86_BUILTIN_MOVLHPS,
27575 IX86_BUILTIN_LOADHPS,
27576 IX86_BUILTIN_LOADLPS,
27577 IX86_BUILTIN_STOREHPS,
27578 IX86_BUILTIN_STORELPS,
27580 IX86_BUILTIN_MASKMOVQ,
27581 IX86_BUILTIN_MOVMSKPS,
27582 IX86_BUILTIN_PMOVMSKB,
27584 IX86_BUILTIN_MOVNTPS,
27585 IX86_BUILTIN_MOVNTQ,
27587 IX86_BUILTIN_LOADDQU,
27588 IX86_BUILTIN_STOREDQU,
27590 IX86_BUILTIN_PACKSSWB,
27591 IX86_BUILTIN_PACKSSDW,
27592 IX86_BUILTIN_PACKUSWB,
27594 IX86_BUILTIN_PADDB,
27595 IX86_BUILTIN_PADDW,
27596 IX86_BUILTIN_PADDD,
27597 IX86_BUILTIN_PADDQ,
27598 IX86_BUILTIN_PADDSB,
27599 IX86_BUILTIN_PADDSW,
27600 IX86_BUILTIN_PADDUSB,
27601 IX86_BUILTIN_PADDUSW,
27602 IX86_BUILTIN_PSUBB,
27603 IX86_BUILTIN_PSUBW,
27604 IX86_BUILTIN_PSUBD,
27605 IX86_BUILTIN_PSUBQ,
27606 IX86_BUILTIN_PSUBSB,
27607 IX86_BUILTIN_PSUBSW,
27608 IX86_BUILTIN_PSUBUSB,
27609 IX86_BUILTIN_PSUBUSW,
27611 IX86_BUILTIN_PAND,
27612 IX86_BUILTIN_PANDN,
27613 IX86_BUILTIN_POR,
27614 IX86_BUILTIN_PXOR,
27616 IX86_BUILTIN_PAVGB,
27617 IX86_BUILTIN_PAVGW,
27619 IX86_BUILTIN_PCMPEQB,
27620 IX86_BUILTIN_PCMPEQW,
27621 IX86_BUILTIN_PCMPEQD,
27622 IX86_BUILTIN_PCMPGTB,
27623 IX86_BUILTIN_PCMPGTW,
27624 IX86_BUILTIN_PCMPGTD,
27626 IX86_BUILTIN_PMADDWD,
27628 IX86_BUILTIN_PMAXSW,
27629 IX86_BUILTIN_PMAXUB,
27630 IX86_BUILTIN_PMINSW,
27631 IX86_BUILTIN_PMINUB,
27633 IX86_BUILTIN_PMULHUW,
27634 IX86_BUILTIN_PMULHW,
27635 IX86_BUILTIN_PMULLW,
27637 IX86_BUILTIN_PSADBW,
27638 IX86_BUILTIN_PSHUFW,
27640 IX86_BUILTIN_PSLLW,
27641 IX86_BUILTIN_PSLLD,
27642 IX86_BUILTIN_PSLLQ,
27643 IX86_BUILTIN_PSRAW,
27644 IX86_BUILTIN_PSRAD,
27645 IX86_BUILTIN_PSRLW,
27646 IX86_BUILTIN_PSRLD,
27647 IX86_BUILTIN_PSRLQ,
27648 IX86_BUILTIN_PSLLWI,
27649 IX86_BUILTIN_PSLLDI,
27650 IX86_BUILTIN_PSLLQI,
27651 IX86_BUILTIN_PSRAWI,
27652 IX86_BUILTIN_PSRADI,
27653 IX86_BUILTIN_PSRLWI,
27654 IX86_BUILTIN_PSRLDI,
27655 IX86_BUILTIN_PSRLQI,
27657 IX86_BUILTIN_PUNPCKHBW,
27658 IX86_BUILTIN_PUNPCKHWD,
27659 IX86_BUILTIN_PUNPCKHDQ,
27660 IX86_BUILTIN_PUNPCKLBW,
27661 IX86_BUILTIN_PUNPCKLWD,
27662 IX86_BUILTIN_PUNPCKLDQ,
27664 IX86_BUILTIN_SHUFPS,
27666 IX86_BUILTIN_RCPPS,
27667 IX86_BUILTIN_RCPSS,
27668 IX86_BUILTIN_RSQRTPS,
27669 IX86_BUILTIN_RSQRTPS_NR,
27670 IX86_BUILTIN_RSQRTSS,
27671 IX86_BUILTIN_RSQRTF,
27672 IX86_BUILTIN_SQRTPS,
27673 IX86_BUILTIN_SQRTPS_NR,
27674 IX86_BUILTIN_SQRTSS,
27676 IX86_BUILTIN_UNPCKHPS,
27677 IX86_BUILTIN_UNPCKLPS,
27679 IX86_BUILTIN_ANDPS,
27680 IX86_BUILTIN_ANDNPS,
27681 IX86_BUILTIN_ORPS,
27682 IX86_BUILTIN_XORPS,
27684 IX86_BUILTIN_EMMS,
27685 IX86_BUILTIN_LDMXCSR,
27686 IX86_BUILTIN_STMXCSR,
27687 IX86_BUILTIN_SFENCE,
27689 IX86_BUILTIN_FXSAVE,
27690 IX86_BUILTIN_FXRSTOR,
27691 IX86_BUILTIN_FXSAVE64,
27692 IX86_BUILTIN_FXRSTOR64,
27694 IX86_BUILTIN_XSAVE,
27695 IX86_BUILTIN_XRSTOR,
27696 IX86_BUILTIN_XSAVE64,
27697 IX86_BUILTIN_XRSTOR64,
27699 IX86_BUILTIN_XSAVEOPT,
27700 IX86_BUILTIN_XSAVEOPT64,
27702 /* 3DNow! Original */
27703 IX86_BUILTIN_FEMMS,
27704 IX86_BUILTIN_PAVGUSB,
27705 IX86_BUILTIN_PF2ID,
27706 IX86_BUILTIN_PFACC,
27707 IX86_BUILTIN_PFADD,
27708 IX86_BUILTIN_PFCMPEQ,
27709 IX86_BUILTIN_PFCMPGE,
27710 IX86_BUILTIN_PFCMPGT,
27711 IX86_BUILTIN_PFMAX,
27712 IX86_BUILTIN_PFMIN,
27713 IX86_BUILTIN_PFMUL,
27714 IX86_BUILTIN_PFRCP,
27715 IX86_BUILTIN_PFRCPIT1,
27716 IX86_BUILTIN_PFRCPIT2,
27717 IX86_BUILTIN_PFRSQIT1,
27718 IX86_BUILTIN_PFRSQRT,
27719 IX86_BUILTIN_PFSUB,
27720 IX86_BUILTIN_PFSUBR,
27721 IX86_BUILTIN_PI2FD,
27722 IX86_BUILTIN_PMULHRW,
27724 /* 3DNow! Athlon Extensions */
27725 IX86_BUILTIN_PF2IW,
27726 IX86_BUILTIN_PFNACC,
27727 IX86_BUILTIN_PFPNACC,
27728 IX86_BUILTIN_PI2FW,
27729 IX86_BUILTIN_PSWAPDSI,
27730 IX86_BUILTIN_PSWAPDSF,
27732 /* SSE2 */
27733 IX86_BUILTIN_ADDPD,
27734 IX86_BUILTIN_ADDSD,
27735 IX86_BUILTIN_DIVPD,
27736 IX86_BUILTIN_DIVSD,
27737 IX86_BUILTIN_MULPD,
27738 IX86_BUILTIN_MULSD,
27739 IX86_BUILTIN_SUBPD,
27740 IX86_BUILTIN_SUBSD,
27742 IX86_BUILTIN_CMPEQPD,
27743 IX86_BUILTIN_CMPLTPD,
27744 IX86_BUILTIN_CMPLEPD,
27745 IX86_BUILTIN_CMPGTPD,
27746 IX86_BUILTIN_CMPGEPD,
27747 IX86_BUILTIN_CMPNEQPD,
27748 IX86_BUILTIN_CMPNLTPD,
27749 IX86_BUILTIN_CMPNLEPD,
27750 IX86_BUILTIN_CMPNGTPD,
27751 IX86_BUILTIN_CMPNGEPD,
27752 IX86_BUILTIN_CMPORDPD,
27753 IX86_BUILTIN_CMPUNORDPD,
27754 IX86_BUILTIN_CMPEQSD,
27755 IX86_BUILTIN_CMPLTSD,
27756 IX86_BUILTIN_CMPLESD,
27757 IX86_BUILTIN_CMPNEQSD,
27758 IX86_BUILTIN_CMPNLTSD,
27759 IX86_BUILTIN_CMPNLESD,
27760 IX86_BUILTIN_CMPORDSD,
27761 IX86_BUILTIN_CMPUNORDSD,
27763 IX86_BUILTIN_COMIEQSD,
27764 IX86_BUILTIN_COMILTSD,
27765 IX86_BUILTIN_COMILESD,
27766 IX86_BUILTIN_COMIGTSD,
27767 IX86_BUILTIN_COMIGESD,
27768 IX86_BUILTIN_COMINEQSD,
27769 IX86_BUILTIN_UCOMIEQSD,
27770 IX86_BUILTIN_UCOMILTSD,
27771 IX86_BUILTIN_UCOMILESD,
27772 IX86_BUILTIN_UCOMIGTSD,
27773 IX86_BUILTIN_UCOMIGESD,
27774 IX86_BUILTIN_UCOMINEQSD,
27776 IX86_BUILTIN_MAXPD,
27777 IX86_BUILTIN_MAXSD,
27778 IX86_BUILTIN_MINPD,
27779 IX86_BUILTIN_MINSD,
27781 IX86_BUILTIN_ANDPD,
27782 IX86_BUILTIN_ANDNPD,
27783 IX86_BUILTIN_ORPD,
27784 IX86_BUILTIN_XORPD,
27786 IX86_BUILTIN_SQRTPD,
27787 IX86_BUILTIN_SQRTSD,
27789 IX86_BUILTIN_UNPCKHPD,
27790 IX86_BUILTIN_UNPCKLPD,
27792 IX86_BUILTIN_SHUFPD,
27794 IX86_BUILTIN_LOADUPD,
27795 IX86_BUILTIN_STOREUPD,
27796 IX86_BUILTIN_MOVSD,
27798 IX86_BUILTIN_LOADHPD,
27799 IX86_BUILTIN_LOADLPD,
27801 IX86_BUILTIN_CVTDQ2PD,
27802 IX86_BUILTIN_CVTDQ2PS,
27804 IX86_BUILTIN_CVTPD2DQ,
27805 IX86_BUILTIN_CVTPD2PI,
27806 IX86_BUILTIN_CVTPD2PS,
27807 IX86_BUILTIN_CVTTPD2DQ,
27808 IX86_BUILTIN_CVTTPD2PI,
27810 IX86_BUILTIN_CVTPI2PD,
27811 IX86_BUILTIN_CVTSI2SD,
27812 IX86_BUILTIN_CVTSI642SD,
27814 IX86_BUILTIN_CVTSD2SI,
27815 IX86_BUILTIN_CVTSD2SI64,
27816 IX86_BUILTIN_CVTSD2SS,
27817 IX86_BUILTIN_CVTSS2SD,
27818 IX86_BUILTIN_CVTTSD2SI,
27819 IX86_BUILTIN_CVTTSD2SI64,
27821 IX86_BUILTIN_CVTPS2DQ,
27822 IX86_BUILTIN_CVTPS2PD,
27823 IX86_BUILTIN_CVTTPS2DQ,
27825 IX86_BUILTIN_MOVNTI,
27826 IX86_BUILTIN_MOVNTI64,
27827 IX86_BUILTIN_MOVNTPD,
27828 IX86_BUILTIN_MOVNTDQ,
27830 IX86_BUILTIN_MOVQ128,
27832 /* SSE2 MMX */
27833 IX86_BUILTIN_MASKMOVDQU,
27834 IX86_BUILTIN_MOVMSKPD,
27835 IX86_BUILTIN_PMOVMSKB128,
27837 IX86_BUILTIN_PACKSSWB128,
27838 IX86_BUILTIN_PACKSSDW128,
27839 IX86_BUILTIN_PACKUSWB128,
27841 IX86_BUILTIN_PADDB128,
27842 IX86_BUILTIN_PADDW128,
27843 IX86_BUILTIN_PADDD128,
27844 IX86_BUILTIN_PADDQ128,
27845 IX86_BUILTIN_PADDSB128,
27846 IX86_BUILTIN_PADDSW128,
27847 IX86_BUILTIN_PADDUSB128,
27848 IX86_BUILTIN_PADDUSW128,
27849 IX86_BUILTIN_PSUBB128,
27850 IX86_BUILTIN_PSUBW128,
27851 IX86_BUILTIN_PSUBD128,
27852 IX86_BUILTIN_PSUBQ128,
27853 IX86_BUILTIN_PSUBSB128,
27854 IX86_BUILTIN_PSUBSW128,
27855 IX86_BUILTIN_PSUBUSB128,
27856 IX86_BUILTIN_PSUBUSW128,
27858 IX86_BUILTIN_PAND128,
27859 IX86_BUILTIN_PANDN128,
27860 IX86_BUILTIN_POR128,
27861 IX86_BUILTIN_PXOR128,
27863 IX86_BUILTIN_PAVGB128,
27864 IX86_BUILTIN_PAVGW128,
27866 IX86_BUILTIN_PCMPEQB128,
27867 IX86_BUILTIN_PCMPEQW128,
27868 IX86_BUILTIN_PCMPEQD128,
27869 IX86_BUILTIN_PCMPGTB128,
27870 IX86_BUILTIN_PCMPGTW128,
27871 IX86_BUILTIN_PCMPGTD128,
27873 IX86_BUILTIN_PMADDWD128,
27875 IX86_BUILTIN_PMAXSW128,
27876 IX86_BUILTIN_PMAXUB128,
27877 IX86_BUILTIN_PMINSW128,
27878 IX86_BUILTIN_PMINUB128,
27880 IX86_BUILTIN_PMULUDQ,
27881 IX86_BUILTIN_PMULUDQ128,
27882 IX86_BUILTIN_PMULHUW128,
27883 IX86_BUILTIN_PMULHW128,
27884 IX86_BUILTIN_PMULLW128,
27886 IX86_BUILTIN_PSADBW128,
27887 IX86_BUILTIN_PSHUFHW,
27888 IX86_BUILTIN_PSHUFLW,
27889 IX86_BUILTIN_PSHUFD,
27891 IX86_BUILTIN_PSLLDQI128,
27892 IX86_BUILTIN_PSLLWI128,
27893 IX86_BUILTIN_PSLLDI128,
27894 IX86_BUILTIN_PSLLQI128,
27895 IX86_BUILTIN_PSRAWI128,
27896 IX86_BUILTIN_PSRADI128,
27897 IX86_BUILTIN_PSRLDQI128,
27898 IX86_BUILTIN_PSRLWI128,
27899 IX86_BUILTIN_PSRLDI128,
27900 IX86_BUILTIN_PSRLQI128,
27902 IX86_BUILTIN_PSLLDQ128,
27903 IX86_BUILTIN_PSLLW128,
27904 IX86_BUILTIN_PSLLD128,
27905 IX86_BUILTIN_PSLLQ128,
27906 IX86_BUILTIN_PSRAW128,
27907 IX86_BUILTIN_PSRAD128,
27908 IX86_BUILTIN_PSRLW128,
27909 IX86_BUILTIN_PSRLD128,
27910 IX86_BUILTIN_PSRLQ128,
27912 IX86_BUILTIN_PUNPCKHBW128,
27913 IX86_BUILTIN_PUNPCKHWD128,
27914 IX86_BUILTIN_PUNPCKHDQ128,
27915 IX86_BUILTIN_PUNPCKHQDQ128,
27916 IX86_BUILTIN_PUNPCKLBW128,
27917 IX86_BUILTIN_PUNPCKLWD128,
27918 IX86_BUILTIN_PUNPCKLDQ128,
27919 IX86_BUILTIN_PUNPCKLQDQ128,
27921 IX86_BUILTIN_CLFLUSH,
27922 IX86_BUILTIN_MFENCE,
27923 IX86_BUILTIN_LFENCE,
27924 IX86_BUILTIN_PAUSE,
27926 IX86_BUILTIN_FNSTENV,
27927 IX86_BUILTIN_FLDENV,
27928 IX86_BUILTIN_FNSTSW,
27929 IX86_BUILTIN_FNCLEX,
27931 IX86_BUILTIN_BSRSI,
27932 IX86_BUILTIN_BSRDI,
27933 IX86_BUILTIN_RDPMC,
27934 IX86_BUILTIN_RDTSC,
27935 IX86_BUILTIN_RDTSCP,
27936 IX86_BUILTIN_ROLQI,
27937 IX86_BUILTIN_ROLHI,
27938 IX86_BUILTIN_RORQI,
27939 IX86_BUILTIN_RORHI,
27941 /* SSE3. */
27942 IX86_BUILTIN_ADDSUBPS,
27943 IX86_BUILTIN_HADDPS,
27944 IX86_BUILTIN_HSUBPS,
27945 IX86_BUILTIN_MOVSHDUP,
27946 IX86_BUILTIN_MOVSLDUP,
27947 IX86_BUILTIN_ADDSUBPD,
27948 IX86_BUILTIN_HADDPD,
27949 IX86_BUILTIN_HSUBPD,
27950 IX86_BUILTIN_LDDQU,
27952 IX86_BUILTIN_MONITOR,
27953 IX86_BUILTIN_MWAIT,
27955 /* SSSE3. */
27956 IX86_BUILTIN_PHADDW,
27957 IX86_BUILTIN_PHADDD,
27958 IX86_BUILTIN_PHADDSW,
27959 IX86_BUILTIN_PHSUBW,
27960 IX86_BUILTIN_PHSUBD,
27961 IX86_BUILTIN_PHSUBSW,
27962 IX86_BUILTIN_PMADDUBSW,
27963 IX86_BUILTIN_PMULHRSW,
27964 IX86_BUILTIN_PSHUFB,
27965 IX86_BUILTIN_PSIGNB,
27966 IX86_BUILTIN_PSIGNW,
27967 IX86_BUILTIN_PSIGND,
27968 IX86_BUILTIN_PALIGNR,
27969 IX86_BUILTIN_PABSB,
27970 IX86_BUILTIN_PABSW,
27971 IX86_BUILTIN_PABSD,
27973 IX86_BUILTIN_PHADDW128,
27974 IX86_BUILTIN_PHADDD128,
27975 IX86_BUILTIN_PHADDSW128,
27976 IX86_BUILTIN_PHSUBW128,
27977 IX86_BUILTIN_PHSUBD128,
27978 IX86_BUILTIN_PHSUBSW128,
27979 IX86_BUILTIN_PMADDUBSW128,
27980 IX86_BUILTIN_PMULHRSW128,
27981 IX86_BUILTIN_PSHUFB128,
27982 IX86_BUILTIN_PSIGNB128,
27983 IX86_BUILTIN_PSIGNW128,
27984 IX86_BUILTIN_PSIGND128,
27985 IX86_BUILTIN_PALIGNR128,
27986 IX86_BUILTIN_PABSB128,
27987 IX86_BUILTIN_PABSW128,
27988 IX86_BUILTIN_PABSD128,
27990 /* AMDFAM10 - SSE4A New Instructions. */
27991 IX86_BUILTIN_MOVNTSD,
27992 IX86_BUILTIN_MOVNTSS,
27993 IX86_BUILTIN_EXTRQI,
27994 IX86_BUILTIN_EXTRQ,
27995 IX86_BUILTIN_INSERTQI,
27996 IX86_BUILTIN_INSERTQ,
27998 /* SSE4.1. */
27999 IX86_BUILTIN_BLENDPD,
28000 IX86_BUILTIN_BLENDPS,
28001 IX86_BUILTIN_BLENDVPD,
28002 IX86_BUILTIN_BLENDVPS,
28003 IX86_BUILTIN_PBLENDVB128,
28004 IX86_BUILTIN_PBLENDW128,
28006 IX86_BUILTIN_DPPD,
28007 IX86_BUILTIN_DPPS,
28009 IX86_BUILTIN_INSERTPS128,
28011 IX86_BUILTIN_MOVNTDQA,
28012 IX86_BUILTIN_MPSADBW128,
28013 IX86_BUILTIN_PACKUSDW128,
28014 IX86_BUILTIN_PCMPEQQ,
28015 IX86_BUILTIN_PHMINPOSUW128,
28017 IX86_BUILTIN_PMAXSB128,
28018 IX86_BUILTIN_PMAXSD128,
28019 IX86_BUILTIN_PMAXUD128,
28020 IX86_BUILTIN_PMAXUW128,
28022 IX86_BUILTIN_PMINSB128,
28023 IX86_BUILTIN_PMINSD128,
28024 IX86_BUILTIN_PMINUD128,
28025 IX86_BUILTIN_PMINUW128,
28027 IX86_BUILTIN_PMOVSXBW128,
28028 IX86_BUILTIN_PMOVSXBD128,
28029 IX86_BUILTIN_PMOVSXBQ128,
28030 IX86_BUILTIN_PMOVSXWD128,
28031 IX86_BUILTIN_PMOVSXWQ128,
28032 IX86_BUILTIN_PMOVSXDQ128,
28034 IX86_BUILTIN_PMOVZXBW128,
28035 IX86_BUILTIN_PMOVZXBD128,
28036 IX86_BUILTIN_PMOVZXBQ128,
28037 IX86_BUILTIN_PMOVZXWD128,
28038 IX86_BUILTIN_PMOVZXWQ128,
28039 IX86_BUILTIN_PMOVZXDQ128,
28041 IX86_BUILTIN_PMULDQ128,
28042 IX86_BUILTIN_PMULLD128,
28044 IX86_BUILTIN_ROUNDSD,
28045 IX86_BUILTIN_ROUNDSS,
28047 IX86_BUILTIN_ROUNDPD,
28048 IX86_BUILTIN_ROUNDPS,
28050 IX86_BUILTIN_FLOORPD,
28051 IX86_BUILTIN_CEILPD,
28052 IX86_BUILTIN_TRUNCPD,
28053 IX86_BUILTIN_RINTPD,
28054 IX86_BUILTIN_ROUNDPD_AZ,
28056 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28057 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28058 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28060 IX86_BUILTIN_FLOORPS,
28061 IX86_BUILTIN_CEILPS,
28062 IX86_BUILTIN_TRUNCPS,
28063 IX86_BUILTIN_RINTPS,
28064 IX86_BUILTIN_ROUNDPS_AZ,
28066 IX86_BUILTIN_FLOORPS_SFIX,
28067 IX86_BUILTIN_CEILPS_SFIX,
28068 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28070 IX86_BUILTIN_PTESTZ,
28071 IX86_BUILTIN_PTESTC,
28072 IX86_BUILTIN_PTESTNZC,
28074 IX86_BUILTIN_VEC_INIT_V2SI,
28075 IX86_BUILTIN_VEC_INIT_V4HI,
28076 IX86_BUILTIN_VEC_INIT_V8QI,
28077 IX86_BUILTIN_VEC_EXT_V2DF,
28078 IX86_BUILTIN_VEC_EXT_V2DI,
28079 IX86_BUILTIN_VEC_EXT_V4SF,
28080 IX86_BUILTIN_VEC_EXT_V4SI,
28081 IX86_BUILTIN_VEC_EXT_V8HI,
28082 IX86_BUILTIN_VEC_EXT_V2SI,
28083 IX86_BUILTIN_VEC_EXT_V4HI,
28084 IX86_BUILTIN_VEC_EXT_V16QI,
28085 IX86_BUILTIN_VEC_SET_V2DI,
28086 IX86_BUILTIN_VEC_SET_V4SF,
28087 IX86_BUILTIN_VEC_SET_V4SI,
28088 IX86_BUILTIN_VEC_SET_V8HI,
28089 IX86_BUILTIN_VEC_SET_V4HI,
28090 IX86_BUILTIN_VEC_SET_V16QI,
28092 IX86_BUILTIN_VEC_PACK_SFIX,
28093 IX86_BUILTIN_VEC_PACK_SFIX256,
28095 /* SSE4.2. */
28096 IX86_BUILTIN_CRC32QI,
28097 IX86_BUILTIN_CRC32HI,
28098 IX86_BUILTIN_CRC32SI,
28099 IX86_BUILTIN_CRC32DI,
28101 IX86_BUILTIN_PCMPESTRI128,
28102 IX86_BUILTIN_PCMPESTRM128,
28103 IX86_BUILTIN_PCMPESTRA128,
28104 IX86_BUILTIN_PCMPESTRC128,
28105 IX86_BUILTIN_PCMPESTRO128,
28106 IX86_BUILTIN_PCMPESTRS128,
28107 IX86_BUILTIN_PCMPESTRZ128,
28108 IX86_BUILTIN_PCMPISTRI128,
28109 IX86_BUILTIN_PCMPISTRM128,
28110 IX86_BUILTIN_PCMPISTRA128,
28111 IX86_BUILTIN_PCMPISTRC128,
28112 IX86_BUILTIN_PCMPISTRO128,
28113 IX86_BUILTIN_PCMPISTRS128,
28114 IX86_BUILTIN_PCMPISTRZ128,
28116 IX86_BUILTIN_PCMPGTQ,
28118 /* AES instructions */
28119 IX86_BUILTIN_AESENC128,
28120 IX86_BUILTIN_AESENCLAST128,
28121 IX86_BUILTIN_AESDEC128,
28122 IX86_BUILTIN_AESDECLAST128,
28123 IX86_BUILTIN_AESIMC128,
28124 IX86_BUILTIN_AESKEYGENASSIST128,
28126 /* PCLMUL instruction */
28127 IX86_BUILTIN_PCLMULQDQ128,
28129 /* AVX */
28130 IX86_BUILTIN_ADDPD256,
28131 IX86_BUILTIN_ADDPS256,
28132 IX86_BUILTIN_ADDSUBPD256,
28133 IX86_BUILTIN_ADDSUBPS256,
28134 IX86_BUILTIN_ANDPD256,
28135 IX86_BUILTIN_ANDPS256,
28136 IX86_BUILTIN_ANDNPD256,
28137 IX86_BUILTIN_ANDNPS256,
28138 IX86_BUILTIN_BLENDPD256,
28139 IX86_BUILTIN_BLENDPS256,
28140 IX86_BUILTIN_BLENDVPD256,
28141 IX86_BUILTIN_BLENDVPS256,
28142 IX86_BUILTIN_DIVPD256,
28143 IX86_BUILTIN_DIVPS256,
28144 IX86_BUILTIN_DPPS256,
28145 IX86_BUILTIN_HADDPD256,
28146 IX86_BUILTIN_HADDPS256,
28147 IX86_BUILTIN_HSUBPD256,
28148 IX86_BUILTIN_HSUBPS256,
28149 IX86_BUILTIN_MAXPD256,
28150 IX86_BUILTIN_MAXPS256,
28151 IX86_BUILTIN_MINPD256,
28152 IX86_BUILTIN_MINPS256,
28153 IX86_BUILTIN_MULPD256,
28154 IX86_BUILTIN_MULPS256,
28155 IX86_BUILTIN_ORPD256,
28156 IX86_BUILTIN_ORPS256,
28157 IX86_BUILTIN_SHUFPD256,
28158 IX86_BUILTIN_SHUFPS256,
28159 IX86_BUILTIN_SUBPD256,
28160 IX86_BUILTIN_SUBPS256,
28161 IX86_BUILTIN_XORPD256,
28162 IX86_BUILTIN_XORPS256,
28163 IX86_BUILTIN_CMPSD,
28164 IX86_BUILTIN_CMPSS,
28165 IX86_BUILTIN_CMPPD,
28166 IX86_BUILTIN_CMPPS,
28167 IX86_BUILTIN_CMPPD256,
28168 IX86_BUILTIN_CMPPS256,
28169 IX86_BUILTIN_CVTDQ2PD256,
28170 IX86_BUILTIN_CVTDQ2PS256,
28171 IX86_BUILTIN_CVTPD2PS256,
28172 IX86_BUILTIN_CVTPS2DQ256,
28173 IX86_BUILTIN_CVTPS2PD256,
28174 IX86_BUILTIN_CVTTPD2DQ256,
28175 IX86_BUILTIN_CVTPD2DQ256,
28176 IX86_BUILTIN_CVTTPS2DQ256,
28177 IX86_BUILTIN_EXTRACTF128PD256,
28178 IX86_BUILTIN_EXTRACTF128PS256,
28179 IX86_BUILTIN_EXTRACTF128SI256,
28180 IX86_BUILTIN_VZEROALL,
28181 IX86_BUILTIN_VZEROUPPER,
28182 IX86_BUILTIN_VPERMILVARPD,
28183 IX86_BUILTIN_VPERMILVARPS,
28184 IX86_BUILTIN_VPERMILVARPD256,
28185 IX86_BUILTIN_VPERMILVARPS256,
28186 IX86_BUILTIN_VPERMILPD,
28187 IX86_BUILTIN_VPERMILPS,
28188 IX86_BUILTIN_VPERMILPD256,
28189 IX86_BUILTIN_VPERMILPS256,
28190 IX86_BUILTIN_VPERMIL2PD,
28191 IX86_BUILTIN_VPERMIL2PS,
28192 IX86_BUILTIN_VPERMIL2PD256,
28193 IX86_BUILTIN_VPERMIL2PS256,
28194 IX86_BUILTIN_VPERM2F128PD256,
28195 IX86_BUILTIN_VPERM2F128PS256,
28196 IX86_BUILTIN_VPERM2F128SI256,
28197 IX86_BUILTIN_VBROADCASTSS,
28198 IX86_BUILTIN_VBROADCASTSD256,
28199 IX86_BUILTIN_VBROADCASTSS256,
28200 IX86_BUILTIN_VBROADCASTPD256,
28201 IX86_BUILTIN_VBROADCASTPS256,
28202 IX86_BUILTIN_VINSERTF128PD256,
28203 IX86_BUILTIN_VINSERTF128PS256,
28204 IX86_BUILTIN_VINSERTF128SI256,
28205 IX86_BUILTIN_LOADUPD256,
28206 IX86_BUILTIN_LOADUPS256,
28207 IX86_BUILTIN_STOREUPD256,
28208 IX86_BUILTIN_STOREUPS256,
28209 IX86_BUILTIN_LDDQU256,
28210 IX86_BUILTIN_MOVNTDQ256,
28211 IX86_BUILTIN_MOVNTPD256,
28212 IX86_BUILTIN_MOVNTPS256,
28213 IX86_BUILTIN_LOADDQU256,
28214 IX86_BUILTIN_STOREDQU256,
28215 IX86_BUILTIN_MASKLOADPD,
28216 IX86_BUILTIN_MASKLOADPS,
28217 IX86_BUILTIN_MASKSTOREPD,
28218 IX86_BUILTIN_MASKSTOREPS,
28219 IX86_BUILTIN_MASKLOADPD256,
28220 IX86_BUILTIN_MASKLOADPS256,
28221 IX86_BUILTIN_MASKSTOREPD256,
28222 IX86_BUILTIN_MASKSTOREPS256,
28223 IX86_BUILTIN_MOVSHDUP256,
28224 IX86_BUILTIN_MOVSLDUP256,
28225 IX86_BUILTIN_MOVDDUP256,
28227 IX86_BUILTIN_SQRTPD256,
28228 IX86_BUILTIN_SQRTPS256,
28229 IX86_BUILTIN_SQRTPS_NR256,
28230 IX86_BUILTIN_RSQRTPS256,
28231 IX86_BUILTIN_RSQRTPS_NR256,
28233 IX86_BUILTIN_RCPPS256,
28235 IX86_BUILTIN_ROUNDPD256,
28236 IX86_BUILTIN_ROUNDPS256,
28238 IX86_BUILTIN_FLOORPD256,
28239 IX86_BUILTIN_CEILPD256,
28240 IX86_BUILTIN_TRUNCPD256,
28241 IX86_BUILTIN_RINTPD256,
28242 IX86_BUILTIN_ROUNDPD_AZ256,
28244 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28245 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28246 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28248 IX86_BUILTIN_FLOORPS256,
28249 IX86_BUILTIN_CEILPS256,
28250 IX86_BUILTIN_TRUNCPS256,
28251 IX86_BUILTIN_RINTPS256,
28252 IX86_BUILTIN_ROUNDPS_AZ256,
28254 IX86_BUILTIN_FLOORPS_SFIX256,
28255 IX86_BUILTIN_CEILPS_SFIX256,
28256 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28258 IX86_BUILTIN_UNPCKHPD256,
28259 IX86_BUILTIN_UNPCKLPD256,
28260 IX86_BUILTIN_UNPCKHPS256,
28261 IX86_BUILTIN_UNPCKLPS256,
28263 IX86_BUILTIN_SI256_SI,
28264 IX86_BUILTIN_PS256_PS,
28265 IX86_BUILTIN_PD256_PD,
28266 IX86_BUILTIN_SI_SI256,
28267 IX86_BUILTIN_PS_PS256,
28268 IX86_BUILTIN_PD_PD256,
28270 IX86_BUILTIN_VTESTZPD,
28271 IX86_BUILTIN_VTESTCPD,
28272 IX86_BUILTIN_VTESTNZCPD,
28273 IX86_BUILTIN_VTESTZPS,
28274 IX86_BUILTIN_VTESTCPS,
28275 IX86_BUILTIN_VTESTNZCPS,
28276 IX86_BUILTIN_VTESTZPD256,
28277 IX86_BUILTIN_VTESTCPD256,
28278 IX86_BUILTIN_VTESTNZCPD256,
28279 IX86_BUILTIN_VTESTZPS256,
28280 IX86_BUILTIN_VTESTCPS256,
28281 IX86_BUILTIN_VTESTNZCPS256,
28282 IX86_BUILTIN_PTESTZ256,
28283 IX86_BUILTIN_PTESTC256,
28284 IX86_BUILTIN_PTESTNZC256,
28286 IX86_BUILTIN_MOVMSKPD256,
28287 IX86_BUILTIN_MOVMSKPS256,
28289 /* AVX2 */
28290 IX86_BUILTIN_MPSADBW256,
28291 IX86_BUILTIN_PABSB256,
28292 IX86_BUILTIN_PABSW256,
28293 IX86_BUILTIN_PABSD256,
28294 IX86_BUILTIN_PACKSSDW256,
28295 IX86_BUILTIN_PACKSSWB256,
28296 IX86_BUILTIN_PACKUSDW256,
28297 IX86_BUILTIN_PACKUSWB256,
28298 IX86_BUILTIN_PADDB256,
28299 IX86_BUILTIN_PADDW256,
28300 IX86_BUILTIN_PADDD256,
28301 IX86_BUILTIN_PADDQ256,
28302 IX86_BUILTIN_PADDSB256,
28303 IX86_BUILTIN_PADDSW256,
28304 IX86_BUILTIN_PADDUSB256,
28305 IX86_BUILTIN_PADDUSW256,
28306 IX86_BUILTIN_PALIGNR256,
28307 IX86_BUILTIN_AND256I,
28308 IX86_BUILTIN_ANDNOT256I,
28309 IX86_BUILTIN_PAVGB256,
28310 IX86_BUILTIN_PAVGW256,
28311 IX86_BUILTIN_PBLENDVB256,
28312 IX86_BUILTIN_PBLENDVW256,
28313 IX86_BUILTIN_PCMPEQB256,
28314 IX86_BUILTIN_PCMPEQW256,
28315 IX86_BUILTIN_PCMPEQD256,
28316 IX86_BUILTIN_PCMPEQQ256,
28317 IX86_BUILTIN_PCMPGTB256,
28318 IX86_BUILTIN_PCMPGTW256,
28319 IX86_BUILTIN_PCMPGTD256,
28320 IX86_BUILTIN_PCMPGTQ256,
28321 IX86_BUILTIN_PHADDW256,
28322 IX86_BUILTIN_PHADDD256,
28323 IX86_BUILTIN_PHADDSW256,
28324 IX86_BUILTIN_PHSUBW256,
28325 IX86_BUILTIN_PHSUBD256,
28326 IX86_BUILTIN_PHSUBSW256,
28327 IX86_BUILTIN_PMADDUBSW256,
28328 IX86_BUILTIN_PMADDWD256,
28329 IX86_BUILTIN_PMAXSB256,
28330 IX86_BUILTIN_PMAXSW256,
28331 IX86_BUILTIN_PMAXSD256,
28332 IX86_BUILTIN_PMAXUB256,
28333 IX86_BUILTIN_PMAXUW256,
28334 IX86_BUILTIN_PMAXUD256,
28335 IX86_BUILTIN_PMINSB256,
28336 IX86_BUILTIN_PMINSW256,
28337 IX86_BUILTIN_PMINSD256,
28338 IX86_BUILTIN_PMINUB256,
28339 IX86_BUILTIN_PMINUW256,
28340 IX86_BUILTIN_PMINUD256,
28341 IX86_BUILTIN_PMOVMSKB256,
28342 IX86_BUILTIN_PMOVSXBW256,
28343 IX86_BUILTIN_PMOVSXBD256,
28344 IX86_BUILTIN_PMOVSXBQ256,
28345 IX86_BUILTIN_PMOVSXWD256,
28346 IX86_BUILTIN_PMOVSXWQ256,
28347 IX86_BUILTIN_PMOVSXDQ256,
28348 IX86_BUILTIN_PMOVZXBW256,
28349 IX86_BUILTIN_PMOVZXBD256,
28350 IX86_BUILTIN_PMOVZXBQ256,
28351 IX86_BUILTIN_PMOVZXWD256,
28352 IX86_BUILTIN_PMOVZXWQ256,
28353 IX86_BUILTIN_PMOVZXDQ256,
28354 IX86_BUILTIN_PMULDQ256,
28355 IX86_BUILTIN_PMULHRSW256,
28356 IX86_BUILTIN_PMULHUW256,
28357 IX86_BUILTIN_PMULHW256,
28358 IX86_BUILTIN_PMULLW256,
28359 IX86_BUILTIN_PMULLD256,
28360 IX86_BUILTIN_PMULUDQ256,
28361 IX86_BUILTIN_POR256,
28362 IX86_BUILTIN_PSADBW256,
28363 IX86_BUILTIN_PSHUFB256,
28364 IX86_BUILTIN_PSHUFD256,
28365 IX86_BUILTIN_PSHUFHW256,
28366 IX86_BUILTIN_PSHUFLW256,
28367 IX86_BUILTIN_PSIGNB256,
28368 IX86_BUILTIN_PSIGNW256,
28369 IX86_BUILTIN_PSIGND256,
28370 IX86_BUILTIN_PSLLDQI256,
28371 IX86_BUILTIN_PSLLWI256,
28372 IX86_BUILTIN_PSLLW256,
28373 IX86_BUILTIN_PSLLDI256,
28374 IX86_BUILTIN_PSLLD256,
28375 IX86_BUILTIN_PSLLQI256,
28376 IX86_BUILTIN_PSLLQ256,
28377 IX86_BUILTIN_PSRAWI256,
28378 IX86_BUILTIN_PSRAW256,
28379 IX86_BUILTIN_PSRADI256,
28380 IX86_BUILTIN_PSRAD256,
28381 IX86_BUILTIN_PSRLDQI256,
28382 IX86_BUILTIN_PSRLWI256,
28383 IX86_BUILTIN_PSRLW256,
28384 IX86_BUILTIN_PSRLDI256,
28385 IX86_BUILTIN_PSRLD256,
28386 IX86_BUILTIN_PSRLQI256,
28387 IX86_BUILTIN_PSRLQ256,
28388 IX86_BUILTIN_PSUBB256,
28389 IX86_BUILTIN_PSUBW256,
28390 IX86_BUILTIN_PSUBD256,
28391 IX86_BUILTIN_PSUBQ256,
28392 IX86_BUILTIN_PSUBSB256,
28393 IX86_BUILTIN_PSUBSW256,
28394 IX86_BUILTIN_PSUBUSB256,
28395 IX86_BUILTIN_PSUBUSW256,
28396 IX86_BUILTIN_PUNPCKHBW256,
28397 IX86_BUILTIN_PUNPCKHWD256,
28398 IX86_BUILTIN_PUNPCKHDQ256,
28399 IX86_BUILTIN_PUNPCKHQDQ256,
28400 IX86_BUILTIN_PUNPCKLBW256,
28401 IX86_BUILTIN_PUNPCKLWD256,
28402 IX86_BUILTIN_PUNPCKLDQ256,
28403 IX86_BUILTIN_PUNPCKLQDQ256,
28404 IX86_BUILTIN_PXOR256,
28405 IX86_BUILTIN_MOVNTDQA256,
28406 IX86_BUILTIN_VBROADCASTSS_PS,
28407 IX86_BUILTIN_VBROADCASTSS_PS256,
28408 IX86_BUILTIN_VBROADCASTSD_PD256,
28409 IX86_BUILTIN_VBROADCASTSI256,
28410 IX86_BUILTIN_PBLENDD256,
28411 IX86_BUILTIN_PBLENDD128,
28412 IX86_BUILTIN_PBROADCASTB256,
28413 IX86_BUILTIN_PBROADCASTW256,
28414 IX86_BUILTIN_PBROADCASTD256,
28415 IX86_BUILTIN_PBROADCASTQ256,
28416 IX86_BUILTIN_PBROADCASTB128,
28417 IX86_BUILTIN_PBROADCASTW128,
28418 IX86_BUILTIN_PBROADCASTD128,
28419 IX86_BUILTIN_PBROADCASTQ128,
28420 IX86_BUILTIN_VPERMVARSI256,
28421 IX86_BUILTIN_VPERMDF256,
28422 IX86_BUILTIN_VPERMVARSF256,
28423 IX86_BUILTIN_VPERMDI256,
28424 IX86_BUILTIN_VPERMTI256,
28425 IX86_BUILTIN_VEXTRACT128I256,
28426 IX86_BUILTIN_VINSERT128I256,
28427 IX86_BUILTIN_MASKLOADD,
28428 IX86_BUILTIN_MASKLOADQ,
28429 IX86_BUILTIN_MASKLOADD256,
28430 IX86_BUILTIN_MASKLOADQ256,
28431 IX86_BUILTIN_MASKSTORED,
28432 IX86_BUILTIN_MASKSTOREQ,
28433 IX86_BUILTIN_MASKSTORED256,
28434 IX86_BUILTIN_MASKSTOREQ256,
28435 IX86_BUILTIN_PSLLVV4DI,
28436 IX86_BUILTIN_PSLLVV2DI,
28437 IX86_BUILTIN_PSLLVV8SI,
28438 IX86_BUILTIN_PSLLVV4SI,
28439 IX86_BUILTIN_PSRAVV8SI,
28440 IX86_BUILTIN_PSRAVV4SI,
28441 IX86_BUILTIN_PSRLVV4DI,
28442 IX86_BUILTIN_PSRLVV2DI,
28443 IX86_BUILTIN_PSRLVV8SI,
28444 IX86_BUILTIN_PSRLVV4SI,
28446 IX86_BUILTIN_GATHERSIV2DF,
28447 IX86_BUILTIN_GATHERSIV4DF,
28448 IX86_BUILTIN_GATHERDIV2DF,
28449 IX86_BUILTIN_GATHERDIV4DF,
28450 IX86_BUILTIN_GATHERSIV4SF,
28451 IX86_BUILTIN_GATHERSIV8SF,
28452 IX86_BUILTIN_GATHERDIV4SF,
28453 IX86_BUILTIN_GATHERDIV8SF,
28454 IX86_BUILTIN_GATHERSIV2DI,
28455 IX86_BUILTIN_GATHERSIV4DI,
28456 IX86_BUILTIN_GATHERDIV2DI,
28457 IX86_BUILTIN_GATHERDIV4DI,
28458 IX86_BUILTIN_GATHERSIV4SI,
28459 IX86_BUILTIN_GATHERSIV8SI,
28460 IX86_BUILTIN_GATHERDIV4SI,
28461 IX86_BUILTIN_GATHERDIV8SI,
28463 /* AVX512F */
28464 IX86_BUILTIN_ADDPD512,
28465 IX86_BUILTIN_ADDPS512,
28466 IX86_BUILTIN_ADDSD_ROUND,
28467 IX86_BUILTIN_ADDSS_ROUND,
28468 IX86_BUILTIN_ALIGND512,
28469 IX86_BUILTIN_ALIGNQ512,
28470 IX86_BUILTIN_BLENDMD512,
28471 IX86_BUILTIN_BLENDMPD512,
28472 IX86_BUILTIN_BLENDMPS512,
28473 IX86_BUILTIN_BLENDMQ512,
28474 IX86_BUILTIN_BROADCASTF32X4_512,
28475 IX86_BUILTIN_BROADCASTF64X4_512,
28476 IX86_BUILTIN_BROADCASTI32X4_512,
28477 IX86_BUILTIN_BROADCASTI64X4_512,
28478 IX86_BUILTIN_BROADCASTSD512,
28479 IX86_BUILTIN_BROADCASTSS512,
28480 IX86_BUILTIN_CMPD512,
28481 IX86_BUILTIN_CMPPD512,
28482 IX86_BUILTIN_CMPPS512,
28483 IX86_BUILTIN_CMPQ512,
28484 IX86_BUILTIN_CMPSD_MASK,
28485 IX86_BUILTIN_CMPSS_MASK,
28486 IX86_BUILTIN_COMIDF,
28487 IX86_BUILTIN_COMISF,
28488 IX86_BUILTIN_COMPRESSPD512,
28489 IX86_BUILTIN_COMPRESSPDSTORE512,
28490 IX86_BUILTIN_COMPRESSPS512,
28491 IX86_BUILTIN_COMPRESSPSSTORE512,
28492 IX86_BUILTIN_CVTDQ2PD512,
28493 IX86_BUILTIN_CVTDQ2PS512,
28494 IX86_BUILTIN_CVTPD2DQ512,
28495 IX86_BUILTIN_CVTPD2PS512,
28496 IX86_BUILTIN_CVTPD2UDQ512,
28497 IX86_BUILTIN_CVTPH2PS512,
28498 IX86_BUILTIN_CVTPS2DQ512,
28499 IX86_BUILTIN_CVTPS2PD512,
28500 IX86_BUILTIN_CVTPS2PH512,
28501 IX86_BUILTIN_CVTPS2UDQ512,
28502 IX86_BUILTIN_CVTSD2SS_ROUND,
28503 IX86_BUILTIN_CVTSI2SD64,
28504 IX86_BUILTIN_CVTSI2SS32,
28505 IX86_BUILTIN_CVTSI2SS64,
28506 IX86_BUILTIN_CVTSS2SD_ROUND,
28507 IX86_BUILTIN_CVTTPD2DQ512,
28508 IX86_BUILTIN_CVTTPD2UDQ512,
28509 IX86_BUILTIN_CVTTPS2DQ512,
28510 IX86_BUILTIN_CVTTPS2UDQ512,
28511 IX86_BUILTIN_CVTUDQ2PD512,
28512 IX86_BUILTIN_CVTUDQ2PS512,
28513 IX86_BUILTIN_CVTUSI2SD32,
28514 IX86_BUILTIN_CVTUSI2SD64,
28515 IX86_BUILTIN_CVTUSI2SS32,
28516 IX86_BUILTIN_CVTUSI2SS64,
28517 IX86_BUILTIN_DIVPD512,
28518 IX86_BUILTIN_DIVPS512,
28519 IX86_BUILTIN_DIVSD_ROUND,
28520 IX86_BUILTIN_DIVSS_ROUND,
28521 IX86_BUILTIN_EXPANDPD512,
28522 IX86_BUILTIN_EXPANDPD512Z,
28523 IX86_BUILTIN_EXPANDPDLOAD512,
28524 IX86_BUILTIN_EXPANDPDLOAD512Z,
28525 IX86_BUILTIN_EXPANDPS512,
28526 IX86_BUILTIN_EXPANDPS512Z,
28527 IX86_BUILTIN_EXPANDPSLOAD512,
28528 IX86_BUILTIN_EXPANDPSLOAD512Z,
28529 IX86_BUILTIN_EXTRACTF32X4,
28530 IX86_BUILTIN_EXTRACTF64X4,
28531 IX86_BUILTIN_EXTRACTI32X4,
28532 IX86_BUILTIN_EXTRACTI64X4,
28533 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28534 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28535 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28536 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28537 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28538 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28539 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28540 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28541 IX86_BUILTIN_GETEXPPD512,
28542 IX86_BUILTIN_GETEXPPS512,
28543 IX86_BUILTIN_GETEXPSD128,
28544 IX86_BUILTIN_GETEXPSS128,
28545 IX86_BUILTIN_GETMANTPD512,
28546 IX86_BUILTIN_GETMANTPS512,
28547 IX86_BUILTIN_GETMANTSD128,
28548 IX86_BUILTIN_GETMANTSS128,
28549 IX86_BUILTIN_INSERTF32X4,
28550 IX86_BUILTIN_INSERTF64X4,
28551 IX86_BUILTIN_INSERTI32X4,
28552 IX86_BUILTIN_INSERTI64X4,
28553 IX86_BUILTIN_LOADAPD512,
28554 IX86_BUILTIN_LOADAPS512,
28555 IX86_BUILTIN_LOADDQUDI512,
28556 IX86_BUILTIN_LOADDQUSI512,
28557 IX86_BUILTIN_LOADUPD512,
28558 IX86_BUILTIN_LOADUPS512,
28559 IX86_BUILTIN_MAXPD512,
28560 IX86_BUILTIN_MAXPS512,
28561 IX86_BUILTIN_MAXSD_ROUND,
28562 IX86_BUILTIN_MAXSS_ROUND,
28563 IX86_BUILTIN_MINPD512,
28564 IX86_BUILTIN_MINPS512,
28565 IX86_BUILTIN_MINSD_ROUND,
28566 IX86_BUILTIN_MINSS_ROUND,
28567 IX86_BUILTIN_MOVAPD512,
28568 IX86_BUILTIN_MOVAPS512,
28569 IX86_BUILTIN_MOVDDUP512,
28570 IX86_BUILTIN_MOVDQA32LOAD512,
28571 IX86_BUILTIN_MOVDQA32STORE512,
28572 IX86_BUILTIN_MOVDQA32_512,
28573 IX86_BUILTIN_MOVDQA64LOAD512,
28574 IX86_BUILTIN_MOVDQA64STORE512,
28575 IX86_BUILTIN_MOVDQA64_512,
28576 IX86_BUILTIN_MOVNTDQ512,
28577 IX86_BUILTIN_MOVNTDQA512,
28578 IX86_BUILTIN_MOVNTPD512,
28579 IX86_BUILTIN_MOVNTPS512,
28580 IX86_BUILTIN_MOVSHDUP512,
28581 IX86_BUILTIN_MOVSLDUP512,
28582 IX86_BUILTIN_MULPD512,
28583 IX86_BUILTIN_MULPS512,
28584 IX86_BUILTIN_MULSD_ROUND,
28585 IX86_BUILTIN_MULSS_ROUND,
28586 IX86_BUILTIN_PABSD512,
28587 IX86_BUILTIN_PABSQ512,
28588 IX86_BUILTIN_PADDD512,
28589 IX86_BUILTIN_PADDQ512,
28590 IX86_BUILTIN_PANDD512,
28591 IX86_BUILTIN_PANDND512,
28592 IX86_BUILTIN_PANDNQ512,
28593 IX86_BUILTIN_PANDQ512,
28594 IX86_BUILTIN_PBROADCASTD512,
28595 IX86_BUILTIN_PBROADCASTD512_GPR,
28596 IX86_BUILTIN_PBROADCASTMB512,
28597 IX86_BUILTIN_PBROADCASTMW512,
28598 IX86_BUILTIN_PBROADCASTQ512,
28599 IX86_BUILTIN_PBROADCASTQ512_GPR,
28600 IX86_BUILTIN_PBROADCASTQ512_MEM,
28601 IX86_BUILTIN_PCMPEQD512_MASK,
28602 IX86_BUILTIN_PCMPEQQ512_MASK,
28603 IX86_BUILTIN_PCMPGTD512_MASK,
28604 IX86_BUILTIN_PCMPGTQ512_MASK,
28605 IX86_BUILTIN_PCOMPRESSD512,
28606 IX86_BUILTIN_PCOMPRESSDSTORE512,
28607 IX86_BUILTIN_PCOMPRESSQ512,
28608 IX86_BUILTIN_PCOMPRESSQSTORE512,
28609 IX86_BUILTIN_PEXPANDD512,
28610 IX86_BUILTIN_PEXPANDD512Z,
28611 IX86_BUILTIN_PEXPANDDLOAD512,
28612 IX86_BUILTIN_PEXPANDDLOAD512Z,
28613 IX86_BUILTIN_PEXPANDQ512,
28614 IX86_BUILTIN_PEXPANDQ512Z,
28615 IX86_BUILTIN_PEXPANDQLOAD512,
28616 IX86_BUILTIN_PEXPANDQLOAD512Z,
28617 IX86_BUILTIN_PMAXSD512,
28618 IX86_BUILTIN_PMAXSQ512,
28619 IX86_BUILTIN_PMAXUD512,
28620 IX86_BUILTIN_PMAXUQ512,
28621 IX86_BUILTIN_PMINSD512,
28622 IX86_BUILTIN_PMINSQ512,
28623 IX86_BUILTIN_PMINUD512,
28624 IX86_BUILTIN_PMINUQ512,
28625 IX86_BUILTIN_PMOVDB512,
28626 IX86_BUILTIN_PMOVDB512_MEM,
28627 IX86_BUILTIN_PMOVDW512,
28628 IX86_BUILTIN_PMOVDW512_MEM,
28629 IX86_BUILTIN_PMOVQB512,
28630 IX86_BUILTIN_PMOVQB512_MEM,
28631 IX86_BUILTIN_PMOVQD512,
28632 IX86_BUILTIN_PMOVQD512_MEM,
28633 IX86_BUILTIN_PMOVQW512,
28634 IX86_BUILTIN_PMOVQW512_MEM,
28635 IX86_BUILTIN_PMOVSDB512,
28636 IX86_BUILTIN_PMOVSDB512_MEM,
28637 IX86_BUILTIN_PMOVSDW512,
28638 IX86_BUILTIN_PMOVSDW512_MEM,
28639 IX86_BUILTIN_PMOVSQB512,
28640 IX86_BUILTIN_PMOVSQB512_MEM,
28641 IX86_BUILTIN_PMOVSQD512,
28642 IX86_BUILTIN_PMOVSQD512_MEM,
28643 IX86_BUILTIN_PMOVSQW512,
28644 IX86_BUILTIN_PMOVSQW512_MEM,
28645 IX86_BUILTIN_PMOVSXBD512,
28646 IX86_BUILTIN_PMOVSXBQ512,
28647 IX86_BUILTIN_PMOVSXDQ512,
28648 IX86_BUILTIN_PMOVSXWD512,
28649 IX86_BUILTIN_PMOVSXWQ512,
28650 IX86_BUILTIN_PMOVUSDB512,
28651 IX86_BUILTIN_PMOVUSDB512_MEM,
28652 IX86_BUILTIN_PMOVUSDW512,
28653 IX86_BUILTIN_PMOVUSDW512_MEM,
28654 IX86_BUILTIN_PMOVUSQB512,
28655 IX86_BUILTIN_PMOVUSQB512_MEM,
28656 IX86_BUILTIN_PMOVUSQD512,
28657 IX86_BUILTIN_PMOVUSQD512_MEM,
28658 IX86_BUILTIN_PMOVUSQW512,
28659 IX86_BUILTIN_PMOVUSQW512_MEM,
28660 IX86_BUILTIN_PMOVZXBD512,
28661 IX86_BUILTIN_PMOVZXBQ512,
28662 IX86_BUILTIN_PMOVZXDQ512,
28663 IX86_BUILTIN_PMOVZXWD512,
28664 IX86_BUILTIN_PMOVZXWQ512,
28665 IX86_BUILTIN_PMULDQ512,
28666 IX86_BUILTIN_PMULLD512,
28667 IX86_BUILTIN_PMULUDQ512,
28668 IX86_BUILTIN_PORD512,
28669 IX86_BUILTIN_PORQ512,
28670 IX86_BUILTIN_PROLD512,
28671 IX86_BUILTIN_PROLQ512,
28672 IX86_BUILTIN_PROLVD512,
28673 IX86_BUILTIN_PROLVQ512,
28674 IX86_BUILTIN_PRORD512,
28675 IX86_BUILTIN_PRORQ512,
28676 IX86_BUILTIN_PRORVD512,
28677 IX86_BUILTIN_PRORVQ512,
28678 IX86_BUILTIN_PSHUFD512,
28679 IX86_BUILTIN_PSLLD512,
28680 IX86_BUILTIN_PSLLDI512,
28681 IX86_BUILTIN_PSLLQ512,
28682 IX86_BUILTIN_PSLLQI512,
28683 IX86_BUILTIN_PSLLVV16SI,
28684 IX86_BUILTIN_PSLLVV8DI,
28685 IX86_BUILTIN_PSRAD512,
28686 IX86_BUILTIN_PSRADI512,
28687 IX86_BUILTIN_PSRAQ512,
28688 IX86_BUILTIN_PSRAQI512,
28689 IX86_BUILTIN_PSRAVV16SI,
28690 IX86_BUILTIN_PSRAVV8DI,
28691 IX86_BUILTIN_PSRLD512,
28692 IX86_BUILTIN_PSRLDI512,
28693 IX86_BUILTIN_PSRLQ512,
28694 IX86_BUILTIN_PSRLQI512,
28695 IX86_BUILTIN_PSRLVV16SI,
28696 IX86_BUILTIN_PSRLVV8DI,
28697 IX86_BUILTIN_PSUBD512,
28698 IX86_BUILTIN_PSUBQ512,
28699 IX86_BUILTIN_PTESTMD512,
28700 IX86_BUILTIN_PTESTMQ512,
28701 IX86_BUILTIN_PTESTNMD512,
28702 IX86_BUILTIN_PTESTNMQ512,
28703 IX86_BUILTIN_PUNPCKHDQ512,
28704 IX86_BUILTIN_PUNPCKHQDQ512,
28705 IX86_BUILTIN_PUNPCKLDQ512,
28706 IX86_BUILTIN_PUNPCKLQDQ512,
28707 IX86_BUILTIN_PXORD512,
28708 IX86_BUILTIN_PXORQ512,
28709 IX86_BUILTIN_RCP14PD512,
28710 IX86_BUILTIN_RCP14PS512,
28711 IX86_BUILTIN_RCP14SD,
28712 IX86_BUILTIN_RCP14SS,
28713 IX86_BUILTIN_RNDSCALEPD,
28714 IX86_BUILTIN_RNDSCALEPS,
28715 IX86_BUILTIN_RNDSCALESD,
28716 IX86_BUILTIN_RNDSCALESS,
28717 IX86_BUILTIN_RSQRT14PD512,
28718 IX86_BUILTIN_RSQRT14PS512,
28719 IX86_BUILTIN_RSQRT14SD,
28720 IX86_BUILTIN_RSQRT14SS,
28721 IX86_BUILTIN_SCALEFPD512,
28722 IX86_BUILTIN_SCALEFPS512,
28723 IX86_BUILTIN_SCALEFSD,
28724 IX86_BUILTIN_SCALEFSS,
28725 IX86_BUILTIN_SHUFPD512,
28726 IX86_BUILTIN_SHUFPS512,
28727 IX86_BUILTIN_SHUF_F32x4,
28728 IX86_BUILTIN_SHUF_F64x2,
28729 IX86_BUILTIN_SHUF_I32x4,
28730 IX86_BUILTIN_SHUF_I64x2,
28731 IX86_BUILTIN_SQRTPD512,
28732 IX86_BUILTIN_SQRTPD512_MASK,
28733 IX86_BUILTIN_SQRTPS512_MASK,
28734 IX86_BUILTIN_SQRTPS_NR512,
28735 IX86_BUILTIN_SQRTSD_ROUND,
28736 IX86_BUILTIN_SQRTSS_ROUND,
28737 IX86_BUILTIN_STOREAPD512,
28738 IX86_BUILTIN_STOREAPS512,
28739 IX86_BUILTIN_STOREDQUDI512,
28740 IX86_BUILTIN_STOREDQUSI512,
28741 IX86_BUILTIN_STOREUPD512,
28742 IX86_BUILTIN_STOREUPS512,
28743 IX86_BUILTIN_SUBPD512,
28744 IX86_BUILTIN_SUBPS512,
28745 IX86_BUILTIN_SUBSD_ROUND,
28746 IX86_BUILTIN_SUBSS_ROUND,
28747 IX86_BUILTIN_UCMPD512,
28748 IX86_BUILTIN_UCMPQ512,
28749 IX86_BUILTIN_UNPCKHPD512,
28750 IX86_BUILTIN_UNPCKHPS512,
28751 IX86_BUILTIN_UNPCKLPD512,
28752 IX86_BUILTIN_UNPCKLPS512,
28753 IX86_BUILTIN_VCVTSD2SI32,
28754 IX86_BUILTIN_VCVTSD2SI64,
28755 IX86_BUILTIN_VCVTSD2USI32,
28756 IX86_BUILTIN_VCVTSD2USI64,
28757 IX86_BUILTIN_VCVTSS2SI32,
28758 IX86_BUILTIN_VCVTSS2SI64,
28759 IX86_BUILTIN_VCVTSS2USI32,
28760 IX86_BUILTIN_VCVTSS2USI64,
28761 IX86_BUILTIN_VCVTTSD2SI32,
28762 IX86_BUILTIN_VCVTTSD2SI64,
28763 IX86_BUILTIN_VCVTTSD2USI32,
28764 IX86_BUILTIN_VCVTTSD2USI64,
28765 IX86_BUILTIN_VCVTTSS2SI32,
28766 IX86_BUILTIN_VCVTTSS2SI64,
28767 IX86_BUILTIN_VCVTTSS2USI32,
28768 IX86_BUILTIN_VCVTTSS2USI64,
28769 IX86_BUILTIN_VFMADDPD512_MASK,
28770 IX86_BUILTIN_VFMADDPD512_MASK3,
28771 IX86_BUILTIN_VFMADDPD512_MASKZ,
28772 IX86_BUILTIN_VFMADDPS512_MASK,
28773 IX86_BUILTIN_VFMADDPS512_MASK3,
28774 IX86_BUILTIN_VFMADDPS512_MASKZ,
28775 IX86_BUILTIN_VFMADDSD3_ROUND,
28776 IX86_BUILTIN_VFMADDSS3_ROUND,
28777 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28778 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28779 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28780 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28781 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28782 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28783 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28784 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28785 IX86_BUILTIN_VFMSUBPD512_MASK3,
28786 IX86_BUILTIN_VFMSUBPS512_MASK3,
28787 IX86_BUILTIN_VFMSUBSD3_MASK3,
28788 IX86_BUILTIN_VFMSUBSS3_MASK3,
28789 IX86_BUILTIN_VFNMADDPD512_MASK,
28790 IX86_BUILTIN_VFNMADDPS512_MASK,
28791 IX86_BUILTIN_VFNMSUBPD512_MASK,
28792 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28793 IX86_BUILTIN_VFNMSUBPS512_MASK,
28794 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28795 IX86_BUILTIN_VPCLZCNTD512,
28796 IX86_BUILTIN_VPCLZCNTQ512,
28797 IX86_BUILTIN_VPCONFLICTD512,
28798 IX86_BUILTIN_VPCONFLICTQ512,
28799 IX86_BUILTIN_VPERMDF512,
28800 IX86_BUILTIN_VPERMDI512,
28801 IX86_BUILTIN_VPERMI2VARD512,
28802 IX86_BUILTIN_VPERMI2VARPD512,
28803 IX86_BUILTIN_VPERMI2VARPS512,
28804 IX86_BUILTIN_VPERMI2VARQ512,
28805 IX86_BUILTIN_VPERMILPD512,
28806 IX86_BUILTIN_VPERMILPS512,
28807 IX86_BUILTIN_VPERMILVARPD512,
28808 IX86_BUILTIN_VPERMILVARPS512,
28809 IX86_BUILTIN_VPERMT2VARD512,
28810 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28811 IX86_BUILTIN_VPERMT2VARPD512,
28812 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28813 IX86_BUILTIN_VPERMT2VARPS512,
28814 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28815 IX86_BUILTIN_VPERMT2VARQ512,
28816 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28817 IX86_BUILTIN_VPERMVARDF512,
28818 IX86_BUILTIN_VPERMVARDI512,
28819 IX86_BUILTIN_VPERMVARSF512,
28820 IX86_BUILTIN_VPERMVARSI512,
28821 IX86_BUILTIN_VTERNLOGD512_MASK,
28822 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28823 IX86_BUILTIN_VTERNLOGQ512_MASK,
28824 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28826 /* Mask arithmetic operations */
28827 IX86_BUILTIN_KAND16,
28828 IX86_BUILTIN_KANDN16,
28829 IX86_BUILTIN_KNOT16,
28830 IX86_BUILTIN_KOR16,
28831 IX86_BUILTIN_KORTESTC16,
28832 IX86_BUILTIN_KORTESTZ16,
28833 IX86_BUILTIN_KUNPCKBW,
28834 IX86_BUILTIN_KXNOR16,
28835 IX86_BUILTIN_KXOR16,
28836 IX86_BUILTIN_KMOV16,
28838 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28839 where all operands are 32-byte or 64-byte wide respectively. */
28840 IX86_BUILTIN_GATHERALTSIV4DF,
28841 IX86_BUILTIN_GATHERALTDIV8SF,
28842 IX86_BUILTIN_GATHERALTSIV4DI,
28843 IX86_BUILTIN_GATHERALTDIV8SI,
28844 IX86_BUILTIN_GATHER3ALTDIV16SF,
28845 IX86_BUILTIN_GATHER3ALTDIV16SI,
28846 IX86_BUILTIN_GATHER3ALTSIV8DF,
28847 IX86_BUILTIN_GATHER3ALTSIV8DI,
28848 IX86_BUILTIN_GATHER3DIV16SF,
28849 IX86_BUILTIN_GATHER3DIV16SI,
28850 IX86_BUILTIN_GATHER3DIV8DF,
28851 IX86_BUILTIN_GATHER3DIV8DI,
28852 IX86_BUILTIN_GATHER3SIV16SF,
28853 IX86_BUILTIN_GATHER3SIV16SI,
28854 IX86_BUILTIN_GATHER3SIV8DF,
28855 IX86_BUILTIN_GATHER3SIV8DI,
28856 IX86_BUILTIN_SCATTERDIV16SF,
28857 IX86_BUILTIN_SCATTERDIV16SI,
28858 IX86_BUILTIN_SCATTERDIV8DF,
28859 IX86_BUILTIN_SCATTERDIV8DI,
28860 IX86_BUILTIN_SCATTERSIV16SF,
28861 IX86_BUILTIN_SCATTERSIV16SI,
28862 IX86_BUILTIN_SCATTERSIV8DF,
28863 IX86_BUILTIN_SCATTERSIV8DI,
28865 /* AVX512PF */
28866 IX86_BUILTIN_GATHERPFQPD,
28867 IX86_BUILTIN_GATHERPFDPS,
28868 IX86_BUILTIN_GATHERPFDPD,
28869 IX86_BUILTIN_GATHERPFQPS,
28870 IX86_BUILTIN_SCATTERPFDPD,
28871 IX86_BUILTIN_SCATTERPFDPS,
28872 IX86_BUILTIN_SCATTERPFQPD,
28873 IX86_BUILTIN_SCATTERPFQPS,
28875 /* AVX-512ER */
28876 IX86_BUILTIN_EXP2PD_MASK,
28877 IX86_BUILTIN_EXP2PS_MASK,
28878 IX86_BUILTIN_EXP2PS,
28879 IX86_BUILTIN_RCP28PD,
28880 IX86_BUILTIN_RCP28PS,
28881 IX86_BUILTIN_RCP28SD,
28882 IX86_BUILTIN_RCP28SS,
28883 IX86_BUILTIN_RSQRT28PD,
28884 IX86_BUILTIN_RSQRT28PS,
28885 IX86_BUILTIN_RSQRT28SD,
28886 IX86_BUILTIN_RSQRT28SS,
28888 /* SHA builtins. */
28889 IX86_BUILTIN_SHA1MSG1,
28890 IX86_BUILTIN_SHA1MSG2,
28891 IX86_BUILTIN_SHA1NEXTE,
28892 IX86_BUILTIN_SHA1RNDS4,
28893 IX86_BUILTIN_SHA256MSG1,
28894 IX86_BUILTIN_SHA256MSG2,
28895 IX86_BUILTIN_SHA256RNDS2,
28897 /* TFmode support builtins. */
28898 IX86_BUILTIN_INFQ,
28899 IX86_BUILTIN_HUGE_VALQ,
28900 IX86_BUILTIN_FABSQ,
28901 IX86_BUILTIN_COPYSIGNQ,
28903 /* Vectorizer support builtins. */
28904 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28905 IX86_BUILTIN_CPYSGNPS,
28906 IX86_BUILTIN_CPYSGNPD,
28907 IX86_BUILTIN_CPYSGNPS256,
28908 IX86_BUILTIN_CPYSGNPS512,
28909 IX86_BUILTIN_CPYSGNPD256,
28910 IX86_BUILTIN_CPYSGNPD512,
28911 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28912 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28915 /* FMA4 instructions. */
28916 IX86_BUILTIN_VFMADDSS,
28917 IX86_BUILTIN_VFMADDSD,
28918 IX86_BUILTIN_VFMADDPS,
28919 IX86_BUILTIN_VFMADDPD,
28920 IX86_BUILTIN_VFMADDPS256,
28921 IX86_BUILTIN_VFMADDPD256,
28922 IX86_BUILTIN_VFMADDSUBPS,
28923 IX86_BUILTIN_VFMADDSUBPD,
28924 IX86_BUILTIN_VFMADDSUBPS256,
28925 IX86_BUILTIN_VFMADDSUBPD256,
28927 /* FMA3 instructions. */
28928 IX86_BUILTIN_VFMADDSS3,
28929 IX86_BUILTIN_VFMADDSD3,
28931 /* XOP instructions. */
28932 IX86_BUILTIN_VPCMOV,
28933 IX86_BUILTIN_VPCMOV_V2DI,
28934 IX86_BUILTIN_VPCMOV_V4SI,
28935 IX86_BUILTIN_VPCMOV_V8HI,
28936 IX86_BUILTIN_VPCMOV_V16QI,
28937 IX86_BUILTIN_VPCMOV_V4SF,
28938 IX86_BUILTIN_VPCMOV_V2DF,
28939 IX86_BUILTIN_VPCMOV256,
28940 IX86_BUILTIN_VPCMOV_V4DI256,
28941 IX86_BUILTIN_VPCMOV_V8SI256,
28942 IX86_BUILTIN_VPCMOV_V16HI256,
28943 IX86_BUILTIN_VPCMOV_V32QI256,
28944 IX86_BUILTIN_VPCMOV_V8SF256,
28945 IX86_BUILTIN_VPCMOV_V4DF256,
28947 IX86_BUILTIN_VPPERM,
28949 IX86_BUILTIN_VPMACSSWW,
28950 IX86_BUILTIN_VPMACSWW,
28951 IX86_BUILTIN_VPMACSSWD,
28952 IX86_BUILTIN_VPMACSWD,
28953 IX86_BUILTIN_VPMACSSDD,
28954 IX86_BUILTIN_VPMACSDD,
28955 IX86_BUILTIN_VPMACSSDQL,
28956 IX86_BUILTIN_VPMACSSDQH,
28957 IX86_BUILTIN_VPMACSDQL,
28958 IX86_BUILTIN_VPMACSDQH,
28959 IX86_BUILTIN_VPMADCSSWD,
28960 IX86_BUILTIN_VPMADCSWD,
28962 IX86_BUILTIN_VPHADDBW,
28963 IX86_BUILTIN_VPHADDBD,
28964 IX86_BUILTIN_VPHADDBQ,
28965 IX86_BUILTIN_VPHADDWD,
28966 IX86_BUILTIN_VPHADDWQ,
28967 IX86_BUILTIN_VPHADDDQ,
28968 IX86_BUILTIN_VPHADDUBW,
28969 IX86_BUILTIN_VPHADDUBD,
28970 IX86_BUILTIN_VPHADDUBQ,
28971 IX86_BUILTIN_VPHADDUWD,
28972 IX86_BUILTIN_VPHADDUWQ,
28973 IX86_BUILTIN_VPHADDUDQ,
28974 IX86_BUILTIN_VPHSUBBW,
28975 IX86_BUILTIN_VPHSUBWD,
28976 IX86_BUILTIN_VPHSUBDQ,
28978 IX86_BUILTIN_VPROTB,
28979 IX86_BUILTIN_VPROTW,
28980 IX86_BUILTIN_VPROTD,
28981 IX86_BUILTIN_VPROTQ,
28982 IX86_BUILTIN_VPROTB_IMM,
28983 IX86_BUILTIN_VPROTW_IMM,
28984 IX86_BUILTIN_VPROTD_IMM,
28985 IX86_BUILTIN_VPROTQ_IMM,
28987 IX86_BUILTIN_VPSHLB,
28988 IX86_BUILTIN_VPSHLW,
28989 IX86_BUILTIN_VPSHLD,
28990 IX86_BUILTIN_VPSHLQ,
28991 IX86_BUILTIN_VPSHAB,
28992 IX86_BUILTIN_VPSHAW,
28993 IX86_BUILTIN_VPSHAD,
28994 IX86_BUILTIN_VPSHAQ,
28996 IX86_BUILTIN_VFRCZSS,
28997 IX86_BUILTIN_VFRCZSD,
28998 IX86_BUILTIN_VFRCZPS,
28999 IX86_BUILTIN_VFRCZPD,
29000 IX86_BUILTIN_VFRCZPS256,
29001 IX86_BUILTIN_VFRCZPD256,
29003 IX86_BUILTIN_VPCOMEQUB,
29004 IX86_BUILTIN_VPCOMNEUB,
29005 IX86_BUILTIN_VPCOMLTUB,
29006 IX86_BUILTIN_VPCOMLEUB,
29007 IX86_BUILTIN_VPCOMGTUB,
29008 IX86_BUILTIN_VPCOMGEUB,
29009 IX86_BUILTIN_VPCOMFALSEUB,
29010 IX86_BUILTIN_VPCOMTRUEUB,
29012 IX86_BUILTIN_VPCOMEQUW,
29013 IX86_BUILTIN_VPCOMNEUW,
29014 IX86_BUILTIN_VPCOMLTUW,
29015 IX86_BUILTIN_VPCOMLEUW,
29016 IX86_BUILTIN_VPCOMGTUW,
29017 IX86_BUILTIN_VPCOMGEUW,
29018 IX86_BUILTIN_VPCOMFALSEUW,
29019 IX86_BUILTIN_VPCOMTRUEUW,
29021 IX86_BUILTIN_VPCOMEQUD,
29022 IX86_BUILTIN_VPCOMNEUD,
29023 IX86_BUILTIN_VPCOMLTUD,
29024 IX86_BUILTIN_VPCOMLEUD,
29025 IX86_BUILTIN_VPCOMGTUD,
29026 IX86_BUILTIN_VPCOMGEUD,
29027 IX86_BUILTIN_VPCOMFALSEUD,
29028 IX86_BUILTIN_VPCOMTRUEUD,
29030 IX86_BUILTIN_VPCOMEQUQ,
29031 IX86_BUILTIN_VPCOMNEUQ,
29032 IX86_BUILTIN_VPCOMLTUQ,
29033 IX86_BUILTIN_VPCOMLEUQ,
29034 IX86_BUILTIN_VPCOMGTUQ,
29035 IX86_BUILTIN_VPCOMGEUQ,
29036 IX86_BUILTIN_VPCOMFALSEUQ,
29037 IX86_BUILTIN_VPCOMTRUEUQ,
29039 IX86_BUILTIN_VPCOMEQB,
29040 IX86_BUILTIN_VPCOMNEB,
29041 IX86_BUILTIN_VPCOMLTB,
29042 IX86_BUILTIN_VPCOMLEB,
29043 IX86_BUILTIN_VPCOMGTB,
29044 IX86_BUILTIN_VPCOMGEB,
29045 IX86_BUILTIN_VPCOMFALSEB,
29046 IX86_BUILTIN_VPCOMTRUEB,
29048 IX86_BUILTIN_VPCOMEQW,
29049 IX86_BUILTIN_VPCOMNEW,
29050 IX86_BUILTIN_VPCOMLTW,
29051 IX86_BUILTIN_VPCOMLEW,
29052 IX86_BUILTIN_VPCOMGTW,
29053 IX86_BUILTIN_VPCOMGEW,
29054 IX86_BUILTIN_VPCOMFALSEW,
29055 IX86_BUILTIN_VPCOMTRUEW,
29057 IX86_BUILTIN_VPCOMEQD,
29058 IX86_BUILTIN_VPCOMNED,
29059 IX86_BUILTIN_VPCOMLTD,
29060 IX86_BUILTIN_VPCOMLED,
29061 IX86_BUILTIN_VPCOMGTD,
29062 IX86_BUILTIN_VPCOMGED,
29063 IX86_BUILTIN_VPCOMFALSED,
29064 IX86_BUILTIN_VPCOMTRUED,
29066 IX86_BUILTIN_VPCOMEQQ,
29067 IX86_BUILTIN_VPCOMNEQ,
29068 IX86_BUILTIN_VPCOMLTQ,
29069 IX86_BUILTIN_VPCOMLEQ,
29070 IX86_BUILTIN_VPCOMGTQ,
29071 IX86_BUILTIN_VPCOMGEQ,
29072 IX86_BUILTIN_VPCOMFALSEQ,
29073 IX86_BUILTIN_VPCOMTRUEQ,
29075 /* LWP instructions. */
29076 IX86_BUILTIN_LLWPCB,
29077 IX86_BUILTIN_SLWPCB,
29078 IX86_BUILTIN_LWPVAL32,
29079 IX86_BUILTIN_LWPVAL64,
29080 IX86_BUILTIN_LWPINS32,
29081 IX86_BUILTIN_LWPINS64,
29083 IX86_BUILTIN_CLZS,
29085 /* RTM */
29086 IX86_BUILTIN_XBEGIN,
29087 IX86_BUILTIN_XEND,
29088 IX86_BUILTIN_XABORT,
29089 IX86_BUILTIN_XTEST,
29091 /* BMI instructions. */
29092 IX86_BUILTIN_BEXTR32,
29093 IX86_BUILTIN_BEXTR64,
29094 IX86_BUILTIN_CTZS,
29096 /* TBM instructions. */
29097 IX86_BUILTIN_BEXTRI32,
29098 IX86_BUILTIN_BEXTRI64,
29100 /* BMI2 instructions. */
29101 IX86_BUILTIN_BZHI32,
29102 IX86_BUILTIN_BZHI64,
29103 IX86_BUILTIN_PDEP32,
29104 IX86_BUILTIN_PDEP64,
29105 IX86_BUILTIN_PEXT32,
29106 IX86_BUILTIN_PEXT64,
29108 /* ADX instructions. */
29109 IX86_BUILTIN_ADDCARRYX32,
29110 IX86_BUILTIN_ADDCARRYX64,
29112 /* FSGSBASE instructions. */
29113 IX86_BUILTIN_RDFSBASE32,
29114 IX86_BUILTIN_RDFSBASE64,
29115 IX86_BUILTIN_RDGSBASE32,
29116 IX86_BUILTIN_RDGSBASE64,
29117 IX86_BUILTIN_WRFSBASE32,
29118 IX86_BUILTIN_WRFSBASE64,
29119 IX86_BUILTIN_WRGSBASE32,
29120 IX86_BUILTIN_WRGSBASE64,
29122 /* RDRND instructions. */
29123 IX86_BUILTIN_RDRAND16_STEP,
29124 IX86_BUILTIN_RDRAND32_STEP,
29125 IX86_BUILTIN_RDRAND64_STEP,
29127 /* RDSEED instructions. */
29128 IX86_BUILTIN_RDSEED16_STEP,
29129 IX86_BUILTIN_RDSEED32_STEP,
29130 IX86_BUILTIN_RDSEED64_STEP,
29132 /* F16C instructions. */
29133 IX86_BUILTIN_CVTPH2PS,
29134 IX86_BUILTIN_CVTPH2PS256,
29135 IX86_BUILTIN_CVTPS2PH,
29136 IX86_BUILTIN_CVTPS2PH256,
29138 /* CFString built-in for darwin */
29139 IX86_BUILTIN_CFSTRING,
29141 /* Builtins to get CPU type and supported features. */
29142 IX86_BUILTIN_CPU_INIT,
29143 IX86_BUILTIN_CPU_IS,
29144 IX86_BUILTIN_CPU_SUPPORTS,
29146 /* Read/write FLAGS register built-ins. */
29147 IX86_BUILTIN_READ_FLAGS,
29148 IX86_BUILTIN_WRITE_FLAGS,
29150 IX86_BUILTIN_MAX
29151 };
29153 /* Table for the ix86 builtin decls. */
29156 /* Table of all of the builtin functions that are possible with different ISA's
29157 but are waiting to be built until a function is declared to use that
29158 ISA. */
29165 };
29170 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
29171 of which isa_flags to use in the ix86_builtins_isa array. Stores the
29172 function decl in the ix86_builtins array. Returns the function decl or
29173 NULL_TREE, if the builtin was not added.
29175 If the front end has a special hook for builtin functions, delay adding
29176 builtin functions that aren't in the current ISA until the ISA is changed
29177 with function specific optimization. Doing so, can save about 300K for the
29178 default compiler. When the builtin is expanded, check at that time whether
29179 it is valid.
29181 If the front end doesn't have a special hook, record all builtins, even if
29182 it isn't an instruction set in the current ISA in case the user uses
29183 function specific options for a different ISA, so that we don't get scope
29184 errors if a builtin is added in the middle of a function scope. */
29190 {
29194 {
29204 {
29210 }
29211 else
29212 {
29218 }
29219 }
29222 }
29224 /* Like def_builtin, but also marks the function decl "const". */
29229 {
29233 else
29237 }
29239 /* Add any new builtin functions for a given ISA that may not have been
29240 declared. This saves a bit of space compared to adding all of the
29241 declarations to the tree, even if we didn't use them. */
29243 static void
29245 {
29249 {
29252 {
29255 /* Don't define the builtin again. */
29261 NULL_TREE);
29266 }
29267 }
29268 }
29270 /* Bits for builtin_description.flag. */
29272 /* Set when we don't support the comparison natively, and should
29273 swap_comparison in order to support it. */
29274 #define BUILTIN_DESC_SWAP_OPERANDS 1
29276 struct builtin_description
29277 {
29284 };
29287 {
29288 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
29289 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
29290 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
29291 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
29292 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
29293 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
29294 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
29295 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
29296 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
29297 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
29298 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
29299 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
29300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
29301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
29302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
29303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
29304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
29305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
29306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
29307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
29308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
29309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
29310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
29311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
29312 };
29315 {
29316 /* SSE4.2 */
29317 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
29318 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
29319 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
29320 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
29321 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
29322 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
29323 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
29324 };
29327 {
29328 /* SSE4.2 */
29329 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
29330 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
29331 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
29332 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
29333 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
29334 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
29335 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
29336 };
29338 /* Special builtins with variable number of arguments. */
29340 {
29341 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
29342 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
29343 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
29345 /* 80387 (for use internally for atomic compound assignment). */
29346 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
29347 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
29348 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
29349 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
29351 /* MMX */
29352 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29354 /* 3DNow! */
29355 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29357 /* FXSR, XSAVE and XSAVEOPT */
29358 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
29359 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
29360 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29361 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29362 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29364 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29365 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29366 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29367 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29368 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29370 /* SSE */
29371 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29372 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29373 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29375 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29376 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29378 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29380 /* SSE or 3DNow!A */
29381 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29382 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
29384 /* SSE2 */
29385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
29389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
29391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
29392 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
29393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
29394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29399 /* SSE3 */
29400 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29402 /* SSE4.1 */
29403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29405 /* SSE4A */
29406 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29407 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29409 /* AVX */
29410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29413 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29414 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29415 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29440 /* AVX2 */
29441 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29442 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29443 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29444 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29445 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29446 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29447 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29448 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29449 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29451 /* AVX512F */
29452 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29453 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29454 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29455 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29456 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29457 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29458 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29459 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29460 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29461 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29462 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29463 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29464 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29465 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29466 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29467 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29468 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29469 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29470 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29471 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29472 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29473 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29474 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29475 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29476 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29477 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29478 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29479 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29480 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29481 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29482 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29483 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29484 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29485 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29486 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29487 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29488 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29489 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29490 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29491 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29492 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29493 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29494 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29495 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29496 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29497 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29498 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29500 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29501 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29502 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29503 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29504 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29505 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29507 /* FSGSBASE */
29508 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29509 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29510 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29511 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29512 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29513 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29514 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29515 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29517 /* RTM */
29518 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29519 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29520 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29521 };
29523 /* Builtins with variable number of arguments. */
29525 {
29526 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29527 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29528 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29529 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29530 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29531 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29532 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29534 /* MMX */
29535 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29536 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29537 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29538 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29539 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29540 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29542 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29543 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29544 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29545 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29546 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29547 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29548 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29549 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29551 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29552 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29554 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29555 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29556 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29557 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29559 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29560 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29561 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29562 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29563 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29564 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29566 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29567 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29568 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29569 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29570 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29571 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29573 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29574 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29575 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29577 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29579 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29580 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29581 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29582 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29583 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29584 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29586 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29587 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29588 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29589 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29590 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29591 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29593 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29594 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29595 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29596 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29598 /* 3DNow! */
29599 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29600 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29601 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29602 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29604 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29605 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29606 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29607 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29608 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29609 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29610 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29611 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29612 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29613 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29614 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29615 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29616 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29617 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29618 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29620 /* 3DNow!A */
29621 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29622 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29623 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29624 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29625 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29626 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29628 /* SSE */
29629 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29630 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29631 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29632 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29633 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29634 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29635 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29636 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29637 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29638 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29639 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29640 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29642 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29644 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29645 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29646 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29647 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29648 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29649 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29650 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29651 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29653 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29654 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29655 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29656 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29657 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29658 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29659 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29660 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29661 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29662 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29663 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29664 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29665 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29666 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29667 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29668 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29669 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29670 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29671 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29672 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29674 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29675 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29676 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29677 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29679 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29680 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29681 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29682 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29684 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29686 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29687 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29688 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29689 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29690 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29692 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29693 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29694 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29696 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29698 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29699 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29700 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29702 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29703 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29705 /* SSE MMX or 3Dnow!A */
29706 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29707 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29708 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29710 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29711 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29712 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29713 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29715 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29716 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29718 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29720 /* SSE2 */
29721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29725 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29726 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29727 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29731 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29732 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29733 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29737 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29739 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29740 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29742 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29743 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29744 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29746 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29747 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29748 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29749 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29750 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29751 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29753 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29755 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29756 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29757 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29758 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29759 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29773 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29777 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29781 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29782 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29783 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29784 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29786 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29789 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29790 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29792 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29794 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29795 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29796 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29797 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29798 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29799 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29800 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29801 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29803 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29812 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29813 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29815 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29817 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29818 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29830 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29831 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29832 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29835 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29836 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29837 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29838 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29839 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29840 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29841 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29842 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29848 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29852 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29857 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29858 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29859 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29862 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29863 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29864 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29865 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29866 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29867 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29870 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29871 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29872 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29873 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29874 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29875 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29877 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29878 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29879 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29880 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29888 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29890 /* SSE2 MMX */
29891 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29892 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29894 /* SSE3 */
29895 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29896 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29898 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29899 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29900 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29901 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29902 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29903 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29905 /* SSSE3 */
29906 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29907 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29908 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29909 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29910 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29911 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29913 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29914 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29915 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29916 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29917 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29918 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29919 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29920 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29921 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29922 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29923 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29924 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29925 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29926 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29927 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29928 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29929 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29930 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29931 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29932 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29933 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29934 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29935 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29936 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29938 /* SSSE3. */
29939 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29940 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29942 /* SSE4.1 */
29943 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29944 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29945 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29946 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29947 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29948 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29949 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29950 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29951 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29952 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29954 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29955 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29956 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29957 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29958 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29959 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29960 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29961 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29962 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29963 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29964 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29965 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29966 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29968 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29969 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29970 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29971 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29972 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29973 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29974 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29975 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29976 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29977 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29978 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29979 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29981 /* SSE4.1 */
29982 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29983 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29984 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29985 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29987 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29988 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29989 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29990 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29992 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29993 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29995 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29996 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29998 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29999 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
30000 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
30001 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
30003 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
30004 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
30006 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30007 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
30009 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
30010 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
30011 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
30013 /* SSE4.2 */
30014 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30015 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
30016 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
30017 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30018 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30020 /* SSE4A */
30021 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
30022 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
30023 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
30024 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30026 /* AES */
30027 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
30028 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
30030 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30031 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30032 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30033 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30035 /* PCLMUL */
30036 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
30038 /* AVX */
30039 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30040 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30043 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30044 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30047 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30053 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30054 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30055 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30056 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30057 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30058 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30059 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30060 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30061 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30062 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30063 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30064 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
30067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
30068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
30069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
30071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
30074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
30075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30084 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
30085 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
30086 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
30087 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
30088 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
30089 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
30090 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
30091 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
30092 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
30093 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
30094 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
30095 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30096 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30097 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
30098 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
30099 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
30100 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
30101 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
30102 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
30103 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
30104 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
30106 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30107 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30108 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
30110 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
30111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30112 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30113 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30114 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30116 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30118 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
30119 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
30121 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
30122 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
30123 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
30124 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
30126 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
30127 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
30129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
30130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
30132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
30133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
30134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
30135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
30137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
30138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
30140 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30141 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
30143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30148 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
30149 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
30150 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
30151 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
30152 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
30153 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
30155 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
30156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
30157 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
30158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
30159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
30160 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
30161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
30162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
30163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
30164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
30165 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
30166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
30167 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
30168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
30169 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
30171 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
30172 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
30174 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30175 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30177 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
30179 /* AVX2 */
30180 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
30181 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
30182 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
30183 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
30184 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
30185 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
30186 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
30187 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
30188 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30189 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30190 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30191 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30192 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30193 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30194 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30195 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30196 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
30197 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30198 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30199 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30200 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30201 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
30202 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
30203 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30204 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30205 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30206 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30207 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30208 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30209 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30210 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30211 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30212 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30213 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30214 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30215 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30216 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30217 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
30218 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
30219 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30220 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30221 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30222 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30223 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30224 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30225 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30226 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30227 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30228 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30229 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30230 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30231 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
30232 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
30233 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
30234 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
30235 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
30236 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
30237 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
30238 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
30239 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
30240 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
30241 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
30242 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
30243 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
30244 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
30245 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30246 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30247 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30248 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30249 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30250 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
30251 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30252 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
30253 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30254 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
30255 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
30256 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
30257 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30258 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30259 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30260 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
30261 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
30262 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
30263 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
30264 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
30265 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
30266 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
30267 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
30268 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
30269 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
30270 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
30271 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
30272 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
30273 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
30274 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
30275 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
30276 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
30277 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
30278 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30279 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30280 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30281 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30282 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30283 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30284 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30285 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30286 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30287 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30288 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30289 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30290 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30291 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30292 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30293 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30294 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30295 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30296 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
30297 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
30298 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
30299 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30300 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
30301 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
30302 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
30303 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
30304 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
30305 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
30306 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
30307 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
30308 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
30309 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30310 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
30311 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
30312 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
30313 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
30314 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
30315 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
30316 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30317 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30318 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30319 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30320 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30321 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30322 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30323 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30324 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30325 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30327 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30329 /* BMI */
30330 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30331 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30332 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30334 /* TBM */
30335 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30336 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30338 /* F16C */
30339 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
30340 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
30341 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
30342 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
30344 /* BMI2 */
30345 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30346 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30347 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30348 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30349 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30350 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30352 /* AVX512F */
30353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30354 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30356 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30357 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30358 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30359 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30360 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
30361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30362 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
30363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
30364 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30366 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30368 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30370 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
30371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30372 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
30373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30374 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30376 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
30378 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
30379 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
30380 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
30381 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
30382 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
30383 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
30384 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
30385 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30386 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30387 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30388 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30389 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30390 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30391 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30392 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30393 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30394 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30395 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30396 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30397 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30398 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30399 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30400 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30401 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30402 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30403 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30404 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30405 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30406 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30407 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30408 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30409 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30410 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30411 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30412 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30413 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30414 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30415 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30416 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30417 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30418 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30419 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30420 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30421 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30422 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30423 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30424 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30425 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30426 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30427 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30428 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30429 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30430 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30431 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30432 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30433 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30434 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30435 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30436 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30437 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30438 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30439 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30440 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30441 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30442 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30443 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30444 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30445 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30446 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30447 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30448 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30449 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30450 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30451 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30452 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30453 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30454 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30455 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30456 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30457 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30458 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30459 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30460 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30461 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30462 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30463 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30464 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30465 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30466 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30467 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30468 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30469 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30470 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30471 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30472 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30473 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30474 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30475 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30476 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30477 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30478 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30479 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30480 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30481 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30482 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30483 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30484 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30485 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30486 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30487 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30488 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30489 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30490 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30491 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30492 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30493 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30494 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30495 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30496 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30497 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30498 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30499 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30500 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30501 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30502 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30503 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30504 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30505 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30506 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30507 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30508 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30509 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30510 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30511 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30512 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30513 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30514 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30515 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30516 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30517 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30518 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30519 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30520 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30521 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30522 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30523 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30524 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30525 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30526 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30527 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30528 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30529 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30530 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30531 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30532 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30533 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30534 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30535 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30536 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30537 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30538 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30539 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30540 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30541 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30542 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30543 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30545 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30546 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30547 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30548 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30549 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30550 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30551 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30552 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30554 /* Mask arithmetic operations */
30555 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30556 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30557 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30558 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30559 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30560 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30561 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30562 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30563 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30564 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30566 /* SHA */
30567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30569 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30574 };
30576 /* Builtins with rounding support. */
30578 {
30579 /* AVX512F */
30580 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30581 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30582 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30583 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30584 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30585 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30586 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30587 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30588 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30589 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30590 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30591 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30592 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30593 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30594 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30595 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30596 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30597 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30598 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30599 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30600 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30601 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30602 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30603 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30604 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30605 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30606 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30607 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30608 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30609 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30610 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30611 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30612 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30613 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30614 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30615 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30616 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30617 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30618 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30619 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30620 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30621 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30622 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30623 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30624 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30625 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30626 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30627 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30628 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30629 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30630 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30631 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30632 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30633 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30634 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30635 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30636 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30637 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30638 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30639 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30640 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30641 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30642 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30643 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30644 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30645 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30646 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30647 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30648 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30649 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30650 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30651 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30652 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30653 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30654 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30655 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30656 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30657 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30658 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30659 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30660 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30661 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30662 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30663 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30664 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30665 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30666 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30667 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30668 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30669 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30670 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30671 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30672 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30673 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30674 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30675 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30676 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30677 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30678 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30679 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30680 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30681 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30682 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30683 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30684 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30685 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30686 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30687 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30688 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30689 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30690 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30691 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30692 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30693 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30694 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30695 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30696 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30697 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30698 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30700 /* AVX512ER */
30701 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30702 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30703 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30704 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30705 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30706 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30707 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30708 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30709 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30710 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30711 };
30713 /* FMA4 and XOP. */
30714 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30715 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30716 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30717 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30718 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30719 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30720 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30721 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30722 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30723 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30724 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30725 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30726 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30727 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30728 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30729 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30730 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30731 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30732 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30733 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30734 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30735 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30736 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30737 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30738 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30739 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30740 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30741 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30742 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30743 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30744 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30745 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30746 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30747 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30748 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30749 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30750 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30751 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30752 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30753 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30754 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30755 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30756 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30757 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30758 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30759 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30760 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30761 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30762 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30763 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30764 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30765 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30768 {
30809 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30810 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30811 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30812 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30813 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30814 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30815 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30817 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30818 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30819 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30820 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30821 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30822 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30823 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30825 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30827 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30828 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30829 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30830 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30831 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30832 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30833 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30834 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30835 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30836 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30837 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30838 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30840 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30841 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30842 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30843 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30844 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30845 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30846 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30847 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30848 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30849 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30850 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30851 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30852 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30853 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30854 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30855 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30857 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30858 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30859 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30860 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30861 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30862 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30864 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30865 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30866 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30867 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30868 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30869 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30870 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30871 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30872 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30873 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30874 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30875 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30876 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30877 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30878 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30880 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30881 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30882 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30883 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30884 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30885 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30886 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30888 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30889 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30890 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30891 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30892 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30893 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30894 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30896 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30897 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30898 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30899 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30900 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30901 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30902 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30905 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30913 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30915 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30967 };
30968 \f
30969 /* TM vector builtins. */
30971 /* Reuse the existing x86-specific `struct builtin_description' cause
30972 we're lazy. Add casts to make them fit. */
30974 {
30975 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30976 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30977 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30978 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30979 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30980 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30981 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30983 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30984 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30985 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30986 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30987 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30988 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30989 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30991 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30992 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30993 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30994 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30995 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30996 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30997 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30999 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
31000 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
31001 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
31002 };
31004 /* TM callbacks. */
31006 /* Return the builtin decl needed to load a vector of TYPE. */
31008 static tree
31010 {
31012 {
31014 {
31021 }
31022 }
31024 }
31026 /* Return the builtin decl needed to store a vector of TYPE. */
31028 static tree
31030 {
31032 {
31034 {
31041 }
31042 }
31044 }
31045 \f
31046 /* Initialize the transactional memory vector load/store builtins. */
31048 static void
31050 {
31054 tree decl;
31061 /* If there are no builtins defined, we must be compiling in a
31062 language without trans-mem support. */
31066 /* Use whatever attributes a normal TM load has. */
31070 /* Use whatever attributes a normal TM store has. */
31074 /* Use whatever attributes a normal TM log has. */
31082 {
31086 {
31094 {
31097 }
31099 {
31102 }
31103 else
31104 {
31107 }
31109 /* The builtin without the prefix for
31110 calling it directly. */
31112 attrs);
31113 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
31114 set the TYPE_ATTRIBUTES. */
31118 }
31119 }
31120 }
31122 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
31123 in the current target ISA to allow the user to compile particular modules
31124 with different target specific options that differ from the command line
31125 options. */
31126 static void
31128 {
31133 /* Add all special builtins with variable number of operands. */
31137 {
31143 }
31145 /* Add all builtins with variable number of operands. */
31149 {
31155 }
31157 /* Add all builtins with rounding. */
31161 {
31167 }
31169 /* pcmpestr[im] insns. */
31173 {
31176 else
31179 }
31181 /* pcmpistr[im] insns. */
31185 {
31188 else
31191 }
31193 /* comi/ucomi insns. */
31195 {
31198 else
31201 }
31203 /* SSE */
31209 /* SSE or 3DNow!A */
31212 IX86_BUILTIN_MASKMOVQ);
31214 /* SSE2 */
31223 /* SSE3. */
31229 /* AES */
31243 /* PCLMUL */
31247 /* RDRND */
31254 IX86_BUILTIN_RDRAND64_STEP);
31256 /* AVX2 */
31258 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
31259 IX86_BUILTIN_GATHERSIV2DF);
31262 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
31263 IX86_BUILTIN_GATHERSIV4DF);
31266 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
31267 IX86_BUILTIN_GATHERDIV2DF);
31270 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
31271 IX86_BUILTIN_GATHERDIV4DF);
31274 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
31275 IX86_BUILTIN_GATHERSIV4SF);
31278 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
31279 IX86_BUILTIN_GATHERSIV8SF);
31282 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
31283 IX86_BUILTIN_GATHERDIV4SF);
31286 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
31287 IX86_BUILTIN_GATHERDIV8SF);
31290 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
31291 IX86_BUILTIN_GATHERSIV2DI);
31294 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
31295 IX86_BUILTIN_GATHERSIV4DI);
31298 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
31299 IX86_BUILTIN_GATHERDIV2DI);
31302 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
31303 IX86_BUILTIN_GATHERDIV4DI);
31306 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
31307 IX86_BUILTIN_GATHERSIV4SI);
31310 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
31311 IX86_BUILTIN_GATHERSIV8SI);
31314 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
31315 IX86_BUILTIN_GATHERDIV4SI);
31318 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
31319 IX86_BUILTIN_GATHERDIV8SI);
31322 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
31323 IX86_BUILTIN_GATHERALTSIV4DF);
31326 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
31327 IX86_BUILTIN_GATHERALTDIV8SF);
31330 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
31331 IX86_BUILTIN_GATHERALTSIV4DI);
31334 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
31335 IX86_BUILTIN_GATHERALTDIV8SI);
31337 /* AVX512F */
31339 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
31340 IX86_BUILTIN_GATHER3SIV16SF);
31343 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
31344 IX86_BUILTIN_GATHER3SIV8DF);
31347 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
31348 IX86_BUILTIN_GATHER3DIV16SF);
31351 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
31352 IX86_BUILTIN_GATHER3DIV8DF);
31355 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
31356 IX86_BUILTIN_GATHER3SIV16SI);
31359 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
31360 IX86_BUILTIN_GATHER3SIV8DI);
31363 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
31364 IX86_BUILTIN_GATHER3DIV16SI);
31367 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
31368 IX86_BUILTIN_GATHER3DIV8DI);
31371 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
31372 IX86_BUILTIN_GATHER3ALTSIV8DF);
31375 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
31376 IX86_BUILTIN_GATHER3ALTDIV16SF);
31379 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
31380 IX86_BUILTIN_GATHER3ALTSIV8DI);
31383 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
31384 IX86_BUILTIN_GATHER3ALTDIV16SI);
31387 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
31388 IX86_BUILTIN_SCATTERSIV16SF);
31391 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
31392 IX86_BUILTIN_SCATTERSIV8DF);
31395 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31396 IX86_BUILTIN_SCATTERDIV16SF);
31399 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31400 IX86_BUILTIN_SCATTERDIV8DF);
31403 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31404 IX86_BUILTIN_SCATTERSIV16SI);
31407 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31408 IX86_BUILTIN_SCATTERSIV8DI);
31411 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31412 IX86_BUILTIN_SCATTERDIV16SI);
31415 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31416 IX86_BUILTIN_SCATTERDIV8DI);
31418 /* AVX512PF */
31420 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31421 IX86_BUILTIN_GATHERPFDPD);
31423 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31424 IX86_BUILTIN_GATHERPFDPS);
31426 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31427 IX86_BUILTIN_GATHERPFQPD);
31429 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31430 IX86_BUILTIN_GATHERPFQPS);
31432 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31433 IX86_BUILTIN_SCATTERPFDPD);
31435 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31436 IX86_BUILTIN_SCATTERPFDPS);
31438 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31439 IX86_BUILTIN_SCATTERPFQPD);
31441 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31442 IX86_BUILTIN_SCATTERPFQPS);
31444 /* SHA */
31460 /* RTM. */
31464 /* MMX access to the vec_init patterns. */
31469 V4HI_FTYPE_HI_HI_HI_HI,
31470 IX86_BUILTIN_VEC_INIT_V4HI);
31473 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31474 IX86_BUILTIN_VEC_INIT_V8QI);
31476 /* Access to the vec_extract patterns. */
31498 /* Access to the vec_set patterns. */
31519 /* RDSEED */
31528 /* ADCX */
31533 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31534 IX86_BUILTIN_ADDCARRYX64);
31536 /* Read/write FLAGS. */
31547 /* Add FMA4 multi-arg argument instructions */
31549 {
31555 }
31556 }
31558 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31559 to return a pointer to VERSION_DECL if the outcome of the expression
31560 formed by PREDICATE_CHAIN is true. This function will be called during
31561 version dispatch to decide which function version to execute. It returns
31562 the basic block at the end, to which more conditions can be added. */
31564 static basic_block
31567 {
31568 gimple return_stmt;
31570 gimple convert_stmt;
31571 gimple call_cond_stmt;
31572 gimple if_else_stmt;
31578 gimple_seq gseq;
31595 {
31603 }
31606 {
31621 else
31622 {
31623 gimple assign_stmt;
31624 /* Use MIN_EXPR to check if any integer is zero?.
31625 and_expr_var = min_expr <cond_var, and_expr_var> */
31633 }
31634 }
31637 integer_zero_node,
31667 }
31669 /* This parses the attribute arguments to target in DECL and determines
31670 the right builtin to use to match the platform specification.
31671 It returns the priority value for this version decl. If PREDICATE_LIST
31672 is not NULL, it stores the list of cpu features that need to be checked
31673 before dispatching this function. */
31675 static unsigned int
31677 {
31678 tree attrs;
31680 tree target_node;
31687 /* Priority of i386 features, greater value is higher priority. This is
31688 used to decide the order in which function dispatch must happen. For
31689 instance, a version specialized for SSE4.2 should be checked for dispatch
31690 before a version for SSE3, as SSE4.2 implies SSE3. */
31691 enum feature_priority
31692 {
31694 P_MMX,
31695 P_SSE,
31696 P_SSE2,
31697 P_SSE3,
31698 P_SSSE3,
31699 P_PROC_SSSE3,
31700 P_SSE4_A,
31701 P_PROC_SSE4_A,
31702 P_SSE4_1,
31703 P_SSE4_2,
31704 P_PROC_SSE4_2,
31705 P_POPCNT,
31706 P_AVX,
31707 P_PROC_AVX,
31708 P_FMA4,
31709 P_XOP,
31710 P_PROC_XOP,
31711 P_FMA,
31712 P_PROC_FMA,
31713 P_AVX2,
31714 P_PROC_AVX2
31715 };
31719 /* These are the target attribute strings for which a dispatcher is
31720 available, from fold_builtin_cpu. */
31722 static struct _feature_list
31723 {
31726 }
31728 {
31743 };
31746 static unsigned int NUM_FEATURES
31762 /* Return priority zero for default function. */
31766 /* Handle arch= if specified. For priority, set it to be 1 more than
31767 the best instruction set the processor can handle. For instance, if
31768 there is a version for atom and a version for ssse3 (the highest ISA
31769 priority for atom), the atom version must be checked for dispatch
31770 before the ssse3 version. */
31772 {
31782 {
31784 {
31792 else
31793 /* We translate "arch=corei7" and "arch=nehalem" to
31794 "corei7" so that it will be mapped to M_INTEL_COREI7
31795 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31802 else
31809 else
31849 }
31850 }
31855 {
31859 }
31862 {
31864 /* For a C string literal the length includes the trailing NULL. */
31867 predicate_chain);
31868 }
31869 }
31871 /* Process feature name. */
31878 {
31879 /* Do not process "arch=" */
31881 {
31884 }
31886 {
31888 {
31890 {
31895 predicate_chain);
31896 }
31897 /* Find the maximum priority feature. */
31902 }
31903 }
31905 {
31909 }
31911 }
31915 {
31918 attrs_str);
31920 }
31922 {
31925 }
31928 }
31930 /* This compares the priority of target features in function DECL1
31931 and DECL2. It returns positive value if DECL1 is higher priority,
31932 negative value if DECL2 is higher priority and 0 if they are the
31933 same. */
31935 static int
31937 {
31942 }
31944 /* V1 and V2 point to function versions with different priorities
31945 based on the target ISA. This function compares their priorities. */
31947 static int
31949 {
31951 {
31952 tree version_decl;
31953 tree predicate_chain;
31960 }
31962 /* This function generates the dispatch function for
31963 multi-versioned functions. DISPATCH_DECL is the function which will
31964 contain the dispatch logic. FNDECLS are the function choices for
31965 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31966 in DISPATCH_DECL in which the dispatch code is generated. */
31968 static int
31972 {
31973 tree default_decl;
31974 gimple ifunc_cpu_init_stmt;
31975 gimple_seq gseq;
31977 tree ele;
31983 struct _function_version_info
31984 {
31985 tree version_decl;
31986 tree predicate_chain;
31994 /*fndecls_p is actually a vector. */
31997 /* At least one more version other than the default. */
32004 /* The first version in the vector is the default decl. */
32010 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
32011 constructors, so explicity call __builtin_cpu_init here. */
32022 {
32026 /* Get attribute string, parse it and find the right predicate decl.
32027 The predicate function could be a lengthy combination of many
32028 features, like arch-type and various isa-variants. */
32039 actual_versions++;
32040 }
32042 /* Sort the versions according to descending order of dispatch priority. The
32043 priority is based on the ISA. This is not a perfect solution. There
32044 could still be ambiguity. If more than one function version is suitable
32045 to execute, which one should be dispatched? In future, allow the user
32046 to specify a dispatch priority next to the version. */
32056 /* dispatch default version at the end. */
32062 }
32064 /* Comparator function to be used in qsort routine to sort attribute
32065 specification strings to "target". */
32067 static int
32069 {
32073 }
32075 /* ARGLIST is the argument to target attribute. This function tokenizes
32076 the comma separated arguments, sorts them and returns a string which
32077 is a unique identifier for the comma separated arguments. It also
32078 replaces non-identifier characters "=,-" with "_". */
32082 {
32083 tree arg;
32092 {
32097 argnum++;
32100 argnum++;
32101 }
32106 {
32112 }
32114 /* Replace "=,-" with "_". */
32127 {
32129 i++;
32131 }
32138 {
32143 }
32148 }
32150 /* This function changes the assembler name for functions that are
32151 versions. If DECL is a function version and has a "target"
32152 attribute, it appends the attribute string to its assembler name. */
32154 static tree
32156 {
32157 tree version_attr;
32165 "Function versions cannot be marked as gnu_inline,"
32174 /* target attribute string cannot be NULL. */
32178 version_string
32189 /* Allow assembler name to be modified if already set. */
32197 }
32199 /* This function returns true if FN1 and FN2 are versions of the same function,
32200 that is, the target strings of the function decls are different. This assumes
32201 that FN1 and FN2 have the same signature. */
32203 static bool
32205 {
32217 /* At least one function decl should have the target attribute specified. */
32221 /* Diagnose missing target attribute if one of the decls is already
32222 multi-versioned. */
32224 {
32226 {
32228 {
32233 }
32236 fn2);
32239 /* Prevent diagnosing of the same error multiple times. */
32244 }
32246 }
32251 /* The sorted target strings must be different for fn1 and fn2
32252 to be versions. */
32255 else
32262 }
32264 static tree
32266 {
32267 /* For function version, add the target suffix to the assembler name. */
32271 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
32273 #endif
32276 }
32278 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
32279 is true, append the full path name of the source file. */
32283 {
32291 /* Get a unique name that can be used globally without any chances
32292 of collision at link time. */
32302 /* Use '.' to concatenate names as it is demangler friendly. */
32305 suffix);
32306 else
32310 }
32312 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32314 /* Make a dispatcher declaration for the multi-versioned function DECL.
32315 Calls to DECL function will be replaced with calls to the dispatcher
32316 by the front-end. Return the decl created. */
32318 static tree
32320 {
32321 tree func_decl;
32341 /* Mark this func as external, the resolver will flip it again if
32342 it gets generated. */
32344 /* This will be of type IFUNCs have to be externally visible. */
32348 }
32350 #endif
32352 /* Returns true if decl is multi-versioned and DECL is the default function,
32353 that is it is not tagged with target specific optimization. */
32355 static bool
32357 {
32366 }
32368 /* Make a dispatcher declaration for the multi-versioned function DECL.
32369 Calls to DECL function will be replaced with calls to the dispatcher
32370 by the front-end. Returns the decl of the dispatcher function. */
32372 static tree
32374 {
32396 /* Find the default version and make it the first node. */
32398 /* Go to the beginning of the chain. */
32403 {
32408 }
32410 /* If there is no default node, just return NULL. */
32414 /* Make default info the first node. */
32416 {
32423 }
32427 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32429 {
32434 /* Right now, the dispatching is done via ifunc. */
32440 dispatcher_version_info
32445 /* Set the dispatcher for all the versions. */
32448 {
32451 }
32452 }
32453 else
32454 #endif
32455 {
32457 "multiversioning needs ifunc which is not supported "
32459 }
32462 }
32464 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32465 it to CHAIN. */
32467 static tree
32469 {
32470 tree attr_name;
32471 tree attr_arg_name;
32472 tree attr_args;
32473 tree attr;
32480 }
32482 /* Make the resolver function decl to dispatch the versions of
32483 a multi-versioned function, DEFAULT_DECL. Create an
32484 empty basic block in the resolver and store the pointer in
32485 EMPTY_BB. Return the decl of the resolver function. */
32487 static tree
32491 {
32496 /* IFUNC's have to be globally visible. So, if the default_decl is
32497 not, then the name of the IFUNC should be made unique. */
32501 /* Append the filename to the resolver function if the versions are
32502 not externally visible. This is because the resolver function has
32503 to be externally visible for the loader to find it. So, appending
32504 the filename will prevent conflicts with a resolver function from
32505 another module which is based on the same version name. */
32508 /* The resolver function should return a (void *). */
32519 /* IFUNC resolvers have to be externally visible. */
32523 /* Resolver is not external, body is generated. */
32533 {
32534 /* In this case, each translation unit with a call to this
32535 versioned function will put out a resolver. Ensure it
32536 is comdat to keep just one copy. */
32539 }
32540 /* Build result decl and add to function_decl. */
32556 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32560 /* Create the alias for dispatch to resolver here. */
32561 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32565 }
32567 /* Generate the dispatching code body to dispatch multi-versioned function
32568 DECL. The target hook is called to process the "target" attributes and
32569 provide the code to dispatch the right function at run-time. NODE points
32570 to the dispatcher decl whose body will be created. */
32572 static tree
32574 {
32575 tree resolver_decl;
32576 basic_block empty_bb;
32577 tree default_ver_decl;
32593 /* The first version in the chain corresponds to the default version. */
32596 /* node is going to be an alias, so remove the finalized bit. */
32610 {
32612 /* Check for virtual functions here again, as by this time it should
32613 have been determined if this function needs a vtable index or
32614 not. This happens for methods in derived classes that override
32615 virtual methods in base classes but are not explicitly marked as
32616 virtual. */
32621 }
32627 }
32628 /* This builds the processor_model struct type defined in
32629 libgcc/config/i386/cpuinfo.c */
32631 static tree
32633 {
32640 /* The first 3 fields are unsigned int. */
32642 {
32648 }
32650 /* The last field is an array of unsigned integers of size one. */
32661 }
32663 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32665 static tree
32667 {
32668 tree new_decl;
32671 VAR_DECL,
32673 type);
32686 }
32688 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32689 into an integer defined in libgcc/config/i386/cpuinfo.c */
32691 static tree
32693 {
32699 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32700 enum processor_features
32701 {
32703 F_MMX,
32704 F_POPCNT,
32705 F_SSE,
32706 F_SSE2,
32707 F_SSE3,
32708 F_SSSE3,
32709 F_SSE4_1,
32710 F_SSE4_2,
32711 F_AVX,
32712 F_AVX2,
32713 F_SSE4_A,
32714 F_FMA4,
32715 F_XOP,
32716 F_FMA,
32717 F_MAX
32718 };
32720 /* These are the values for vendor types and cpu types and subtypes
32721 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32722 the corresponding start value. */
32723 enum processor_model
32724 {
32726 M_AMD,
32727 M_CPU_TYPE_START,
32728 M_INTEL_BONNELL,
32729 M_INTEL_CORE2,
32730 M_INTEL_COREI7,
32731 M_AMDFAM10H,
32732 M_AMDFAM15H,
32733 M_INTEL_SILVERMONT,
32734 M_AMD_BTVER1,
32735 M_AMD_BTVER2,
32736 M_CPU_SUBTYPE_START,
32737 M_INTEL_COREI7_NEHALEM,
32738 M_INTEL_COREI7_WESTMERE,
32739 M_INTEL_COREI7_SANDYBRIDGE,
32740 M_AMDFAM10H_BARCELONA,
32741 M_AMDFAM10H_SHANGHAI,
32742 M_AMDFAM10H_ISTANBUL,
32743 M_AMDFAM15H_BDVER1,
32744 M_AMDFAM15H_BDVER2,
32745 M_AMDFAM15H_BDVER3,
32746 M_AMDFAM15H_BDVER4,
32747 M_INTEL_COREI7_IVYBRIDGE,
32748 M_INTEL_COREI7_HASWELL
32749 };
32751 static struct _arch_names_table
32752 {
32755 }
32757 {
32782 };
32784 static struct _isa_names_table
32785 {
32788 }
32790 {
32806 };
32820 {
32821 /* *args must be a expr that can contain other EXPRS leading to a
32822 STRING_CST. */
32824 {
32827 }
32829 }
32834 {
32835 tree ref;
32836 tree field;
32837 tree final;
32840 unsigned int NUM_ARCH_NAMES
32849 {
32853 }
32858 /* CPU types are stored in the next field. */
32861 {
32864 }
32866 /* CPU subtypes are stored in the next field. */
32868 {
32871 }
32873 /* Get the appropriate field in __cpu_model. */
32877 /* Check the value. */
32881 }
32883 {
32884 tree ref;
32885 tree array_elt;
32886 tree field;
32887 tree final;
32890 unsigned int NUM_ISA_NAMES
32899 {
32903 }
32906 /* Get the last field, which is __cpu_features. */
32910 /* Get the appropriate field: __cpu_model.__cpu_features */
32914 /* Access the 0th element of __cpu_features array. */
32919 /* Return __cpu_model.__cpu_features[0] & field_val */
32923 }
32925 }
32927 static tree
32930 {
32932 {
32937 {
32940 }
32941 }
32943 #ifdef SUBTARGET_FOLD_BUILTIN
32945 #endif
32948 }
32950 /* Make builtins to detect cpu type and features supported. NAME is
32951 the builtin name, CODE is the builtin code, and FTYPE is the function
32952 type of the builtin. */
32954 static void
32957 {
32958 tree decl;
32959 tree type;
32967 }
32969 /* Make builtins to get CPU type and features supported. The created
32970 builtins are :
32972 __builtin_cpu_init (), to detect cpu type and features,
32973 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32974 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32975 */
32977 static void
32979 {
32986 }
32988 /* Internal method for ix86_init_builtins. */
32990 static void
32992 {
33004 sysv_va_ref =
33007 fnvoid_va_end_ms =
33009 fnvoid_va_start_ms =
33011 fnvoid_va_end_sysv =
33013 fnvoid_va_start_sysv =
33015 NULL_TREE);
33016 fnvoid_va_copy_ms =
33018 NULL_TREE);
33019 fnvoid_va_copy_sysv =
33035 }
33037 static void
33039 {
33042 /* The __float80 type. */
33045 {
33046 /* The __float80 type. */
33051 }
33054 /* The __float128 type. */
33060 /* This macro is built by i386-builtin-types.awk. */
33061 DEFINE_BUILTIN_PRIMITIVE_TYPES;
33062 }
33064 static void
33066 {
33067 tree t;
33071 /* Builtins to get CPU type and features. */
33074 /* TFmode support builtins. */
33080 /* We will expand them to normal call if SSE isn't available since
33081 they are used by libgcc. */
33100 #ifdef SUBTARGET_INIT_BUILTINS
33101 SUBTARGET_INIT_BUILTINS;
33102 #endif
33103 }
33105 /* Return the ix86 builtin for CODE. */
33107 static tree
33109 {
33114 }
33116 /* Errors in the source file can cause expand_expr to return const0_rtx
33117 where we expect a vector. To avoid crashing, use one of the vector
33118 clear instructions. */
33119 static rtx
33121 {
33125 }
33127 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
33129 static rtx
33131 {
33132 rtx pat;
33152 {
33156 }
33170 }
33172 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
33174 static rtx
33178 {
33179 rtx pat;
33187 rtx op;
33194 {
33274 }
33284 {
33291 {
33293 {
33296 {
33314 xop_rotl:
33316 {
33319 gcc_checking_assert
33321 }
33322 else
33323 {
33324 gcc_checking_assert
33335 }
33339 }
33340 }
33341 }
33342 else
33343 {
33344 non_constant:
33348 /* If we aren't optimizing, only allow one memory operand to be
33349 generated. */
33351 num_memory++;
33359 }
33363 }
33366 {
33377 else
33378 {
33384 }
33397 }
33404 }
33406 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33407 insns with vec_merge. */
33409 static rtx
33411 rtx target)
33412 {
33413 rtx pat;
33440 }
33442 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33444 static rtx
33447 {
33448 rtx pat;
33453 rtx op2;
33464 /* Swap operands if we have a comparison that isn't available in
33465 hardware. */
33467 {
33472 }
33492 }
33494 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33496 static rtx
33498 rtx target)
33499 {
33500 rtx pat;
33514 /* Swap operands if we have a comparison that isn't available in
33515 hardware. */
33517 {
33521 }
33542 const0_rtx)));
33545 }
33547 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33549 static rtx
33551 rtx target)
33552 {
33553 rtx pat;
33578 }
33580 static rtx
33583 {
33584 rtx pat;
33589 rtx op2;
33616 }
33618 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33620 static rtx
33622 rtx target)
33623 {
33624 rtx pat;
33657 const0_rtx)));
33660 }
33662 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33664 static rtx
33667 {
33668 rtx pat;
33706 {
33709 }
33712 {
33721 }
33723 {
33732 }
33733 else
33734 {
33741 }
33749 {
33754 emit_insn
33758 FLAGS_REG),
33759 const0_rtx)));
33761 }
33762 else
33764 }
33767 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33769 static rtx
33772 {
33773 rtx pat;
33801 {
33804 }
33807 {
33816 }
33818 {
33827 }
33828 else
33829 {
33836 }
33844 {
33849 emit_insn
33853 FLAGS_REG),
33854 const0_rtx)));
33856 }
33857 else
33859 }
33861 /* Subroutine of ix86_expand_builtin to take care of insns with
33862 variable number of operands. */
33864 static rtx
33867 {
33873 struct
33874 {
33875 rtx op;
33887 {
34335 }
34340 {
34343 }
34346 {
34353 }
34354 else
34355 {
34358 }
34361 {
34368 {
34369 /* SIMD shift insns take either an 8-bit immediate or
34370 register as count. But builtin functions take int as
34371 count. If count doesn't match, we put it in register. */
34373 {
34377 }
34378 }
34381 {
34384 {
34460 {
34464 {
34467 }
34473 }
34475 }
34476 }
34477 else
34478 {
34482 /* If we aren't optimizing, only allow one memory operand to
34483 be generated. */
34485 num_memory++;
34488 {
34491 }
34492 else
34493 {
34496 }
34497 }
34501 }
34504 {
34529 }
34536 }
34538 /* Transform pattern of following layout:
34539 (parallel [
34540 set (A B)
34541 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34542 ])
34543 into:
34544 (set (A B))
34546 Or:
34547 (parallel [ A B
34548 ...
34549 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34550 ...
34551 ])
34552 into:
34553 (parallel [ A B ... ]) */
34555 static rtx
34557 {
34564 {
34573 }
34574 else
34575 {
34581 {
34586 }
34588 /* No more than 1 occurence was removed. */
34592 }
34593 }
34595 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34596 with rounding. */
34597 static rtx
34600 {
34617 /* See avxintrin.h for values. */
34619 {
34623 };
34625 {
34630 };
34633 {
34636 }
34638 {
34641 }
34644 {
34647 }
34670 ? CODE_FOR_sse_ucomi_round
34677 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34679 {
34685 }
34686 else
34687 {
34690 }
34696 set_dst,
34697 const0_rtx)));
34700 }
34702 static rtx
34705 {
34706 rtx pat;
34708 struct
34709 {
34710 rtx op;
34720 {
34797 }
34807 {
34814 {
34816 {
34818 {
34834 }
34835 }
34836 }
34838 {
34840 {
34843 }
34845 /* If there is no rounding use normal version of the pattern. */
34848 }
34849 else
34850 {
34855 {
34858 }
34859 else
34860 {
34863 }
34864 }
34868 }
34871 {
34896 }
34906 }
34908 /* Subroutine of ix86_expand_builtin to take care of special insns
34909 with variable number of operands. */
34911 static rtx
34914 {
34915 tree arg;
34919 struct
34920 {
34921 rtx op;
34931 {
34970 {
34978 }
34997 /* Reserve memory operand for target. */
35000 {
35001 /* These builtins and instructions require the memory
35002 to be properly aligned. */
35021 }
35046 {
35047 /* These builtins and instructions require the memory
35048 to be properly aligned. */
35057 }
35058 /* FALLTHRU */
35076 /* Reserve memory operand for target. */
35089 {
35090 /* These builtins and instructions require the memory
35091 to be properly aligned. */
35100 }
35113 }
35118 {
35123 {
35126 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
35127 on it. Try to improve it using get_pointer_alignment,
35128 and if the special builtin is one that requires strict
35129 mode alignment, also from it's GET_MODE_ALIGNMENT.
35130 Failure to do so could lead to ix86_legitimate_combined_insn
35131 rejecting all changes to such insns. */
35137 }
35138 else
35141 }
35142 else
35143 {
35150 }
35153 {
35162 {
35164 {
35170 else
35173 }
35174 }
35175 else
35176 {
35178 {
35179 /* This must be the memory operand. */
35182 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
35183 on it. Try to improve it using get_pointer_alignment,
35184 and if the special builtin is one that requires strict
35185 mode alignment, also from it's GET_MODE_ALIGNMENT.
35186 Failure to do so could lead to ix86_legitimate_combined_insn
35187 rejecting all changes to such insns. */
35193 }
35194 else
35195 {
35196 /* This must be register. */
35202 else
35203 {
35206 }
35207 }
35208 }
35212 }
35215 {
35230 }
35236 }
35238 /* Return the integer constant in ARG. Constrain it to be in the range
35239 of the subparts of VEC_TYPE; issue an error if not. */
35241 static int
35243 {
35248 {
35251 }
35254 }
35256 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35257 ix86_expand_vector_init. We DO have language-level syntax for this, in
35258 the form of (type){ init-list }. Except that since we can't place emms
35259 instructions from inside the compiler, we can't allow the use of MMX
35260 registers unless the user explicitly asks for it. So we do *not* define
35261 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
35262 we have builtins invoked by mmintrin.h that gives us license to emit
35263 these sorts of instructions. */
35265 static rtx
35267 {
35277 {
35280 }
35287 }
35289 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35290 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
35291 had a language-level syntax for referencing vector elements. */
35293 static rtx
35295 {
35299 rtx op0;
35319 }
35321 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35322 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
35323 a language-level syntax for referencing vector elements. */
35325 static rtx
35327 {
35351 /* OP0 is the source of these builtin functions and shouldn't be
35352 modified. Create a copy, use it and return it as target. */
35358 }
35360 /* Expand an expression EXP that calls a built-in function,
35361 with result going to TARGET if that's convenient
35362 (and in mode MODE if that's convenient).
35363 SUBTARGET may be used as the target for computing one of EXP's operands.
35364 IGNORE is nonzero if the value is to be ignored. */
35366 static rtx
35369 {
35379 /* For CPU builtins that can be folded, fold first and expand the fold. */
35381 {
35383 {
35384 /* Make it call __cpu_indicator_init in libgcc. */
35390 }
35393 {
35398 }
35399 }
35401 /* Determine whether the builtin function is available under the current ISA.
35402 Originally the builtin was not created if it wasn't applicable to the
35403 current ISA based on the command line switches. With function specific
35404 options, we need to check in the context of the function making the call
35405 whether it is supported. */
35408 {
35414 else
35415 {
35419 }
35421 }
35424 {
35428 ? CODE_FOR_mmx_maskmovq
35430 /* Note the arg order is different from the operand order. */
35531 {
35532 REAL_VALUE_TYPE inf;
35533 rtx tmp;
35545 }
35555 {
35561 insn = (TARGET_64BIT
35565 }
35567 {
35568 insn = (TARGET_64BIT
35572 }
35573 else
35574 {
35577 insn = (TARGET_64BIT
35585 {
35588 }
35590 }
35593 {
35594 /* mode is VOIDmode if __builtin_rd* has been called
35595 without lhs. */
35599 }
35602 {
35607 }
35621 {
35646 }
35652 {
35655 }
35675 {
35678 }
35684 {
35688 {
35709 }
35714 }
35715 else
35716 {
35718 {
35730 }
35732 }
35762 ? CODE_FOR_tbm_bextri_si
35765 {
35768 }
35769 else
35770 {
35779 }
35795 rdrand_step:
35802 {
35805 }
35811 /* Emit SImode conditional move. */
35813 {
35816 }
35819 else
35827 const0_rtx);
35846 rdseed_step:
35853 {
35856 }
35862 const0_rtx);
35881 addcarryx:
35889 /* Generate CF from input operand. */
35894 /* Gen ADCX instruction to compute X+Y+CF. */
35909 /* Store the result. */
35912 {
35915 }
35918 /* Return current CF value. */
35960 kortest:
35974 /* Emit kortest. */
35976 /* And use setcc to return result from flags. */
36127 gather_gen:
36128 rtx half;
36141 /* Note the arg order is different from the operand order. */
36152 else
36156 {
36178 else
36185 {
36190 }
36197 else
36204 {
36209 }
36213 }
36215 /* Force memory operand only with base register here. But we
36216 don't want to do it on memory operand for other builtin
36217 functions. */
36227 {
36230 }
36231 else
36232 {
36235 }
36237 {
36240 }
36242 /* Optimize. If mask is known to have all high bits set,
36243 replace op0 with pc_rtx to signal that the instruction
36244 overwrites the whole destination and doesn't use its
36245 previous contents. */
36247 {
36249 {
36252 }
36254 {
36257 {
36261 negative++;
36264 negative++;
36265 }
36268 }
36271 {
36272 /* Recognize also when mask is like:
36273 __v2df src = _mm_setzero_pd ();
36274 __v2df mask = _mm_cmpeq_pd (src, src);
36275 or
36276 __v8sf src = _mm256_setzero_ps ();
36277 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
36278 as that is a cheaper way to load all ones into
36279 a register than having to load a constant from
36280 memory. */
36283 {
36288 {
36295 /* FALLTHRU */
36305 }
36306 }
36307 }
36308 }
36316 {
36340 }
36343 scatter_gen:
36359 /* Force memory operand only with base register here. But we
36360 don't want to do it on memory operand for other builtin
36361 functions. */
36368 {
36371 }
36372 else
36373 {
36376 }
36385 {
36388 }
36397 vec_prefetch_gen:
36415 {
36418 }
36420 {
36423 }
36428 /* Force memory operand only with base register here. But we
36429 don't want to do it on memory operand for other builtin
36430 functions. */
36437 {
36440 }
36443 {
36446 }
36462 {
36465 }
36471 }
36484 {
36488 /* Emit a normal call if SSE isn't available. */
36492 }
36521 }
36523 /* This returns the target-specific builtin with code CODE if
36524 current_function_decl has visibility on this builtin, which is checked
36525 using isa flags. Returns NULL_TREE otherwise. */
36528 {
36532 /* Determine the isa flags of current_function_decl. */
36544 else
36546 }
36548 /* Returns a function decl for a vectorized version of the builtin function
36549 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36550 if it is not available. */
36552 static tree
36554 tree type_in)
36555 {
36571 {
36574 {
36581 }
36586 {
36589 }
36594 {
36601 }
36607 /* The round insn does not trap on denormals. */
36612 {
36619 }
36625 /* The round insn does not trap on denormals. */
36630 {
36635 }
36641 /* The round insn does not trap on denormals. */
36646 {
36653 }
36659 /* The round insn does not trap on denormals. */
36664 {
36669 }
36676 {
36681 }
36688 {
36693 }
36699 /* The round insn does not trap on denormals. */
36704 {
36711 }
36717 /* The round insn does not trap on denormals. */
36722 {
36727 }
36732 {
36739 }
36744 {
36751 }
36755 /* The round insn does not trap on denormals. */
36760 {
36765 }
36769 /* The round insn does not trap on denormals. */
36774 {
36779 }
36783 /* The round insn does not trap on denormals. */
36788 {
36793 }
36797 /* The round insn does not trap on denormals. */
36802 {
36807 }
36811 /* The round insn does not trap on denormals. */
36816 {
36821 }
36825 /* The round insn does not trap on denormals. */
36830 {
36835 }
36839 /* The round insn does not trap on denormals. */
36844 {
36849 }
36853 /* The round insn does not trap on denormals. */
36858 {
36863 }
36867 /* The round insn does not trap on denormals. */
36872 {
36877 }
36881 /* The round insn does not trap on denormals. */
36886 {
36891 }
36896 {
36901 }
36906 {
36911 }
36916 }
36918 /* Dispatch to a handler for a vectorization library. */
36921 type_in);
36924 }
36926 /* Handler for an SVML-style interface to
36927 a library with vectorized intrinsics. */
36929 static tree
36931 {
36939 /* The SVML is suitable for unsafe math only. */
36952 {
36999 }
37008 {
37011 }
37012 else
37015 /* Convert to uppercase. */
37020 args;
37022 arity++;
37026 else
37029 /* Build a function declaration for the vectorized function. */
37038 }
37040 /* Handler for an ACML-style interface to
37041 a library with vectorized intrinsics. */
37043 static tree
37045 {
37053 /* The ACML is 64bits only and suitable for unsafe math only as
37054 it does not correctly support parts of IEEE with the required
37055 precision such as denormals. */
37069 {
37099 }
37106 args;
37108 arity++;
37112 else
37115 /* Build a function declaration for the vectorized function. */
37124 }
37126 /* Returns a decl of a function that implements gather load with
37127 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
37128 Return NULL_TREE if it is not available. */
37130 static tree
37133 {
37149 /* v*gather* insn sign extends index to pointer mode. */
37161 {
37189 else
37195 else
37201 else
37207 else
37212 }
37215 }
37217 /* Returns a code for a target-specific builtin that implements
37218 reciprocal of the function, or NULL_TREE if not available. */
37220 static tree
37223 {
37230 /* Machine dependent builtins. */
37232 {
37233 /* Vectorized version of sqrt to rsqrt conversion. */
37242 }
37243 else
37244 /* Normal builtins. */
37246 {
37247 /* Sqrt to rsqrt conversion. */
37253 }
37254 }
37255 \f
37256 /* Helper for avx_vpermilps256_operand et al. This is also used by
37257 the expansion functions to turn the parallel back into a mask.
37258 The return value is 0 for no match and the imm8+1 for a match. */
37260 int
37262 {
37270 /* Validate that all of the elements are constants, and not totally
37271 out of range. Copy the data into an integral array to make the
37272 subsequent checks easier. */
37274 {
37284 }
37287 {
37289 /* In the 512-bit DFmode case, we can only move elements within
37290 a 128-bit lane. First fill the second part of the mask,
37291 then fallthru. */
37293 {
37297 }
37299 {
37303 }
37304 /* FALLTHRU */
37307 /* In the 256-bit DFmode case, we can only move elements within
37308 a 128-bit lane. */
37310 {
37314 }
37316 {
37320 }
37324 /* In 512 bit SFmode case, permutation in the upper 256 bits
37325 must mirror the permutation in the lower 256-bits. */
37329 /* FALLTHRU */
37332 /* In 256 bit SFmode case, we have full freedom of
37333 movement within the low 128-bit lane, but the high 128-bit
37334 lane must mirror the exact same pattern. */
37339 /* FALLTHRU */
37343 /* In the 128-bit case, we've full freedom in the placement of
37344 the elements from the source operand. */
37351 }
37353 /* Make sure success has a non-zero value by adding one. */
37355 }
37357 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
37358 the expansion functions to turn the parallel back into a mask.
37359 The return value is 0 for no match and the imm8+1 for a match. */
37361 int
37363 {
37371 /* Validate that all of the elements are constants, and not totally
37372 out of range. Copy the data into an integral array to make the
37373 subsequent checks easier. */
37375 {
37385 }
37387 /* Validate that the halves of the permute are halves. */
37395 /* Reconstruct the mask. */
37397 {
37403 }
37405 /* Make sure success has a non-zero value by adding one. */
37407 }
37408 \f
37409 /* Return a register priority for hard reg REGNO. */
37410 static int
37412 {
37413 /* ebp and r13 as the base always wants a displacement, r12 as the
37414 base always wants an index. So discourage their usage in an
37415 address. */
37420 /* New x86-64 int registers result in bigger code size. Discourage
37421 them. */
37424 /* New x86-64 SSE registers result in bigger code size. Discourage
37425 them. */
37428 /* Usage of AX register results in smaller code. Prefer it. */
37432 }
37434 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37436 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37437 QImode must go into class Q_REGS.
37438 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37439 movdf to do mem-to-mem moves through integer regs. */
37441 static reg_class_t
37443 {
37446 /* We're only allowed to return a subclass of CLASS. Many of the
37447 following checks fail for NO_REGS, so eliminate that early. */
37451 /* All classes can load zeros. */
37455 /* Force constants into memory if we are loading a (nonzero) constant into
37456 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37457 instructions to load from a constant. */
37464 /* Prefer SSE regs only, if we can use them for math. */
37468 /* Floating-point constants need more complex checks. */
37470 {
37471 /* General regs can load everything. */
37475 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37476 zero above. We only want to wind up preferring 80387 registers if
37477 we plan on doing computation with them. */
37480 {
37481 /* Limit class to non-sse. */
37490 }
37493 }
37495 /* Generally when we see PLUS here, it's the function invariant
37496 (plus soft-fp const_int). Which can only be computed into general
37497 regs. */
37501 /* QImode constants are easy to load, but non-constant QImode data
37502 must go into Q_REGS. */
37504 {
37510 }
37513 }
37515 /* Discourage putting floating-point values in SSE registers unless
37516 SSE math is being used, and likewise for the 387 registers. */
37517 static reg_class_t
37519 {
37522 /* Restrict the output reload class to the register bank that we are doing
37523 math on. If we would like not to return a subset of CLASS, reject this
37524 alternative: if reload cannot do this, it will still use its choice. */
37530 {
37535 else
37537 }
37540 }
37542 static reg_class_t
37545 {
37546 /* Double-word spills from general registers to non-offsettable memory
37547 references (zero-extended addresses) require special handling. */
37553 {
37555 ? CODE_FOR_reload_noff_load
37557 /* Add the cost of moving address to a temporary. */
37561 }
37563 /* QImode spills from non-QI registers require
37564 intermediate register on 32bit targets. */
37570 {
37575 else
37581 /* Return Q_REGS if the operand is in memory. */
37584 }
37586 /* This condition handles corner case where an expression involving
37587 pointers gets vectorized. We're trying to use the address of a
37588 stack slot as a vector initializer.
37590 (set (reg:V2DI 74 [ vect_cst_.2 ])
37591 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37593 Eventually frame gets turned into sp+offset like this:
37595 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37596 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37597 (const_int 392 [0x188]))))
37599 That later gets turned into:
37601 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37602 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37603 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37605 We'll have the following reload recorded:
37607 Reload 0: reload_in (DI) =
37608 (plus:DI (reg/f:DI 7 sp)
37609 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37610 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37611 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37612 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37613 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37614 reload_reg_rtx: (reg:V2DI 22 xmm1)
37616 Which isn't going to work since SSE instructions can't handle scalar
37617 additions. Returning GENERAL_REGS forces the addition into integer
37618 register and reload can handle subsequent reloads without problems. */
37626 }
37628 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37630 static bool
37632 {
37634 {
37649 }
37652 }
37654 /* If we are copying between general and FP registers, we need a memory
37655 location. The same is true for SSE and MMX registers.
37657 To optimize register_move_cost performance, allow inline variant.
37659 The macro can't work reliably when one of the CLASSES is class containing
37660 registers from multiple units (SSE, MMX, integer). We avoid this by never
37661 combining those units in single alternative in the machine description.
37662 Ensure that this constraint holds to avoid unexpected surprises.
37664 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37665 enforce these sanity checks. */
37670 {
37679 {
37682 }
37687 /* ??? This is a lie. We do have moves between mmx/general, and for
37688 mmx/sse2. But by saying we need secondary memory we discourage the
37689 register allocator from using the mmx registers unless needed. */
37694 {
37695 /* SSE1 doesn't have any direct moves from other classes. */
37699 /* If the target says that inter-unit moves are more expensive
37700 than moving through memory, then don't generate them. */
37705 /* Between SSE and general, we have moves no larger than word size. */
37708 }
37711 }
37713 bool
37716 {
37718 }
37720 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37722 On the 80386, this is the size of MODE in words,
37723 except in the FP regs, where a single reg is always enough. */
37725 static unsigned char
37727 {
37729 {
37734 else
37736 }
37737 else
37738 {
37741 else
37743 }
37744 }
37746 /* Return true if the registers in CLASS cannot represent the change from
37747 modes FROM to TO. */
37749 bool
37752 {
37756 /* x87 registers can't do subreg at all, as all values are reformatted
37757 to extended precision. */
37762 {
37763 /* Vector registers do not support QI or HImode loads. If we don't
37764 disallow a change to these modes, reload will assume it's ok to
37765 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37766 the vec_dupv4hi pattern. */
37770 /* Vector registers do not support subreg with nonzero offsets, which
37771 are otherwise valid for integer registers. Since we can't see
37772 whether we have a nonzero offset from here, prohibit all
37773 nonparadoxical subregs changing size. */
37776 }
37779 }
37781 /* Return the cost of moving data of mode M between a
37782 register and memory. A value of 2 is the default; this cost is
37783 relative to those in `REGISTER_MOVE_COST'.
37785 This function is used extensively by register_move_cost that is used to
37786 build tables at startup. Make it inline in this case.
37787 When IN is 2, return maximum of in and out move cost.
37789 If moving between registers and memory is more expensive than
37790 between two registers, you should define this macro to express the
37791 relative cost.
37793 Model also increased moving costs of QImode registers in non
37794 Q_REGS classes.
37795 */
37799 {
37802 {
37805 {
37817 }
37821 }
37823 {
37826 {
37838 }
37842 }
37844 {
37847 {
37856 }
37860 }
37862 {
37865 {
37871 else
37876 }
37877 else
37878 {
37883 else
37885 }
37892 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37899 else
37903 }
37904 }
37906 static int
37909 {
37911 }
37914 /* Return the cost of moving data from a register in class CLASS1 to
37915 one in class CLASS2.
37917 It is not required that the cost always equal 2 when FROM is the same as TO;
37918 on some machines it is expensive to move between registers if they are not
37919 general registers. */
37921 static int
37923 reg_class_t class2_i)
37924 {
37928 /* In case we require secondary memory, compute cost of the store followed
37929 by load. In order to avoid bad register allocation choices, we need
37930 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37933 {
37939 /* In case of copying from general_purpose_register we may emit multiple
37940 stores followed by single load causing memory size mismatch stall.
37941 Count this as arbitrarily high cost of 20. */
37946 /* In the case of FP/MMX moves, the registers actually overlap, and we
37947 have to switch modes in order to treat them differently. */
37953 }
37955 /* Moves between SSE/MMX and integer unit are expensive. */
37959 /* ??? By keeping returned value relatively high, we limit the number
37960 of moves between integer and MMX/SSE registers for all targets.
37961 Additionally, high value prevents problem with x86_modes_tieable_p(),
37962 where integer modes in MMX/SSE registers are not tieable
37963 because of missing QImode and HImode moves to, from or between
37964 MMX/SSE registers. */
37974 }
37976 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37977 MODE. */
37979 bool
37981 {
37982 /* Flags and only flags can only hold CCmode values. */
37994 {
37995 /* We implement the move patterns for all vector modes into and
37996 out of SSE registers, even when no operation instructions
37997 are available. */
37999 /* For AVX-512 we allow, regardless of regno:
38000 - XI mode
38001 - any of 512-bit wide vector mode
38002 - any scalar mode. */
38009 /* xmm16-xmm31 are only available for AVX-512. */
38013 /* OImode and AVX modes are available only when AVX is enabled. */
38020 }
38022 {
38023 /* We implement the move patterns for 3DNOW modes even in MMX mode,
38024 so if the register is available at all, then we can move data of
38025 the given mode into or out of it. */
38028 }
38031 {
38032 /* Take care for QImode values - they can be in non-QI regs,
38033 but then they do cause partial register stalls. */
38038 /* LRA checks if the hard register is OK for the given mode.
38039 QImode values can live in non-QI regs, so we allow all
38040 registers here. */
38044 }
38045 /* We handle both integer and floats in the general purpose registers. */
38052 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
38053 on to use that value in smaller contexts, this can easily force a
38054 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
38055 supporting DImode, allow it. */
38060 }
38062 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
38063 tieable integer mode. */
38065 static bool
38067 {
38069 {
38082 }
38083 }
38085 /* Return true if MODE1 is accessible in a register that can hold MODE2
38086 without copying. That is, all register classes that can hold MODE2
38087 can also hold MODE1. */
38089 bool
38091 {
38099 /* MODE2 being XFmode implies fp stack or general regs, which means we
38100 can tie any smaller floating point modes to it. Note that we do not
38101 tie this with TFmode. */
38105 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
38106 that we can tie it with SFmode. */
38110 /* If MODE2 is only appropriate for an SSE register, then tie with
38111 any other mode acceptable to SSE registers. */
38121 /* If MODE2 is appropriate for an MMX register, then tie
38122 with any other mode acceptable to MMX registers. */
38129 }
38131 /* Return the cost of moving between two registers of mode MODE. */
38133 static int
38135 {
38139 {
38171 }
38173 /* Return the cost of moving between two registers of mode MODE,
38174 assuming that the move will be in pieces of at most UNITS bytes. */
38176 }
38178 /* Compute a (partial) cost for rtx X. Return true if the complete
38179 cost has been computed, and false if subexpressions should be
38180 scanned. In either case, *TOTAL contains the cost result. */
38182 static bool
38185 {
38186 rtx mask;
38193 {
38197 {
38200 }
38212 && !(TARGET_64BIT
38217 else
38223 {
38226 }
38228 {
38238 }
38240 {
38243 {
38252 }
38253 }
38254 /* Fall back to (MEM (SYMBOL_REF)), since that's where
38255 it'll probably end up. Add a penalty for size. */
38262 /* The zero extensions is often completely free on x86_64, so make
38263 it as cheap as possible. */
38269 else
38281 {
38284 {
38287 }
38290 {
38293 }
38294 }
38295 /* FALLTHRU */
38302 {
38303 /* ??? Should be SSE vector operation cost. */
38304 /* At least for published AMD latencies, this really is the same
38305 as the latency for a simple fpu operation like fabs. */
38306 /* V*QImode is emulated with 1-11 insns. */
38308 {
38311 {
38312 /* For XOP we use vpshab, which requires a broadcast of the
38313 value to the variable shift insn. For constants this
38314 means a V16Q const in mem; even when we can perform the
38315 shift with one insn set the cost to prefer paddb. */
38317 {
38322 }
38324 }
38328 }
38329 else
38331 }
38333 {
38335 {
38338 else
38340 }
38341 else
38342 {
38345 else
38347 }
38348 }
38349 else
38350 {
38355 {
38356 /* Return the cost after shift-and truncation. */
38359 }
38360 else
38362 }
38366 {
38367 rtx sub;
38372 /* ??? SSE scalar/vector cost should be used here. */
38373 /* ??? Bald assumption that fma has the same cost as fmul. */
38377 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38388 }
38392 {
38393 /* ??? SSE scalar cost should be used here. */
38396 }
38398 {
38401 }
38403 {
38404 /* ??? SSE vector cost should be used here. */
38407 }
38409 {
38410 /* V*QImode is emulated with 7-13 insns. */
38412 {
38419 }
38420 /* V*DImode is emulated with 5-8 insns. */
38422 {
38425 else
38427 }
38428 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38429 insns, including two PMULUDQ. */
38432 else
38435 }
38436 else
38437 {
38442 {
38445 nbits++;
38446 }
38447 else
38448 /* This is arbitrary. */
38451 /* Compute costs correctly for widening multiplication. */
38455 {
38462 {
38466 else
38468 }
38472 }
38480 }
38487 /* ??? SSE cost should be used here. */
38492 /* ??? SSE vector cost should be used here. */
38494 else
38501 {
38506 {
38509 {
38517 }
38518 }
38521 {
38524 {
38530 }
38531 }
38533 {
38541 }
38542 }
38543 /* FALLTHRU */
38547 {
38548 /* ??? SSE cost should be used here. */
38551 }
38553 {
38556 }
38558 {
38559 /* ??? SSE vector cost should be used here. */
38562 }
38563 /* FALLTHRU */
38570 {
38577 }
38578 /* FALLTHRU */
38582 {
38583 /* ??? SSE cost should be used here. */
38586 }
38588 {
38591 }
38593 {
38594 /* ??? SSE vector cost should be used here. */
38597 }
38598 /* FALLTHRU */
38602 {
38603 /* ??? Should be SSE vector operation cost. */
38604 /* At least for published AMD latencies, this really is the same
38605 as the latency for a simple fpu operation like fabs. */
38607 }
38610 else
38619 {
38620 /* This kind of construct is implemented using test[bwl].
38621 Treat it as if we had an AND. */
38626 }
38636 /* ??? SSE cost should be used here. */
38641 /* ??? SSE vector cost should be used here. */
38647 /* ??? SSE cost should be used here. */
38652 /* ??? SSE vector cost should be used here. */
38664 /* ??? Assume all of these vector manipulation patterns are
38665 recognizable. In which case they all pretty much have the
38666 same cost. */
38671 /* This is masked instruction, assume the same cost,
38672 as nonmasked variant. */
38675 else
38681 }
38682 }
38684 #if TARGET_MACHO
38688 /* Given a symbol name and its associated stub, write out the
38689 definition of the stub. */
38691 void
38693 {
38698 /* For 64-bit we shouldn't get here. */
38701 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38718 else
38725 {
38727 }
38729 {
38730 /* PIC stub. */
38731 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38737 }
38738 else
38741 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38742 it needs no stub-binding-helper. */
38749 {
38752 }
38753 else
38758 /* N.B. Keep the correspondence of these
38759 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38760 old-pic/new-pic/non-pic stubs; altering this will break
38761 compatibility with existing dylibs. */
38763 {
38764 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38766 }
38767 else
38768 /* 16-byte -mdynamic-no-pic stub. */
38774 }
38777 /* Order the registers for register allocator. */
38779 void
38781 {
38785 /* First allocate the local general purpose registers. */
38790 /* Global general purpose registers. */
38795 /* x87 registers come first in case we are doing FP math
38796 using them. */
38801 /* SSE registers. */
38807 /* Extended REX SSE registers. */
38811 /* Mask register. */
38815 /* x87 registers. */
38823 /* Initialize the rest of array as we do not allocate some registers
38824 at all. */
38827 }
38829 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38830 in struct attribute_spec handler. */
38831 static tree
38833 tree args,
38836 {
38841 {
38843 name);
38846 }
38848 {
38850 name);
38853 }
38855 {
38856 tree cst;
38860 {
38863 name);
38865 }
38868 {
38871 name);
38873 }
38876 }
38879 }
38881 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38882 struct attribute_spec.handler. */
38883 static tree
38885 tree args ATTRIBUTE_UNUSED,
38887 {
38892 {
38894 name);
38897 }
38899 /* Can combine regparm with all attributes but fastcall. */
38901 {
38903 {
38905 }
38908 }
38910 {
38912 {
38914 }
38917 }
38920 }
38922 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38923 struct attribute_spec.handler. */
38924 static tree
38926 tree args ATTRIBUTE_UNUSED,
38928 {
38931 {
38934 }
38935 else
38939 {
38941 name);
38943 }
38949 {
38951 name);
38953 }
38956 }
38958 static tree
38960 tree args ATTRIBUTE_UNUSED,
38962 {
38964 {
38966 name);
38968 }
38970 }
38972 static bool
38974 {
38978 }
38980 /* Returns an expression indicating where the this parameter is
38981 located on entry to the FUNCTION. */
38983 static rtx
38985 {
38991 {
38996 else
38999 }
39004 {
39011 {
39016 }
39017 else
39018 {
39021 {
39027 }
39028 }
39030 }
39034 }
39036 /* Determine whether x86_output_mi_thunk can succeed. */
39038 static bool
39040 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
39042 {
39043 /* 64-bit can handle anything. */
39047 /* For 32-bit, everything's fine if we have one free register. */
39051 /* Need a free register for vcall_offset. */
39055 /* Need a free register for GOT references. */
39059 /* Otherwise ok. */
39061 }
39063 /* Output the assembler code for a thunk function. THUNK_DECL is the
39064 declaration for the thunk function itself, FUNCTION is the decl for
39065 the target function. DELTA is an immediate constant offset to be
39066 added to THIS. If VCALL_OFFSET is nonzero, the word at
39067 *(*this + vcall_offset) should be added to THIS. */
39069 static void
39073 {
39080 else
39081 {
39087 else
39089 }
39093 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
39094 pull it in now and let DELTA benefit. */
39098 {
39099 /* Put the this parameter into %eax. */
39102 }
39103 else
39106 /* Adjust the this parameter by a fixed constant. */
39108 {
39113 {
39115 {
39119 }
39120 }
39123 }
39125 /* Adjust the this parameter by a value stored in the vtable. */
39127 {
39137 /* Adjust the this parameter. */
39141 {
39145 }
39152 vcall_mem));
39153 else
39155 }
39157 /* If necessary, drop THIS back to its stack slot. */
39163 {
39166 ;
39167 else
39168 {
39172 }
39173 }
39174 else
39175 {
39177 ;
39178 #if TARGET_MACHO
39180 {
39183 }
39185 else
39186 {
39194 }
39195 }
39197 /* Our sibling call patterns do not allow memories, because we have no
39198 predicate that can distinguish between frame and non-frame memory.
39199 For our purposes here, we can get away with (ab)using a jump pattern,
39200 because we're going to do no optimization. */
39203 else
39204 {
39210 {
39216 }
39222 }
39225 /* Emit just enough of rest_of_compilation to get the insns emitted.
39226 Note that use_thunk calls assemble_start_function et al. */
39232 }
39234 static void
39236 {
39240 #if TARGET_MACHO
39242 #endif
39249 }
39251 int
39253 {
39265 }
39267 /* Output assembler code to FILE to increment profiler label # LABELNO
39268 for profiling a function entry. */
39269 void
39271 {
39276 {
39277 #ifndef NO_PROFILE_COUNTERS
39279 #endif
39283 else
39285 }
39287 {
39288 #ifndef NO_PROFILE_COUNTERS
39291 #endif
39293 }
39294 else
39295 {
39296 #ifndef NO_PROFILE_COUNTERS
39299 #endif
39301 }
39302 }
39304 /* We don't have exact information about the insn sizes, but we may assume
39305 quite safely that we are informed about all 1 byte insns and memory
39306 address sizes. This is enough to eliminate unnecessary padding in
39307 99% of cases. */
39309 static int
39311 {
39317 /* Discard alignments we've emit and jump instructions. */
39322 /* Important case - calls are always 5 bytes.
39323 It is common to have many calls in the row. */
39332 /* For normal instructions we rely on get_attr_length being exact,
39333 with a few exceptions. */
39335 {
39339 {
39349 /* Otherwise trust get_attr_length. */
39351 }
39356 }
39359 else
39361 }
39363 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39365 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39366 window. */
39368 static void
39370 {
39375 /* Look for all minimal intervals of instructions containing 4 jumps.
39376 The intervals are bounded by START and INSN. NBYTES is the total
39377 size of instructions in the interval including INSN and not including
39378 START. When the NBYTES is smaller than 16 bytes, it is possible
39379 that the end of START and INSN ends up in the same 16byte page.
39381 The smallest offset in the page INSN can start is the case where START
39382 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39383 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39385 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39386 have to, control transfer to label(s) can be performed through other
39387 means, and also we estimate minimum length of all asm stmts as 0. */
39389 {
39393 {
39399 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39400 already in the current 16 byte page, because otherwise
39401 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39402 bytes to reach 16 byte boundary. */
39410 {
39412 {
39417 else
39420 }
39421 }
39423 }
39432 njumps++;
39433 else
39437 {
39442 else
39445 }
39452 {
39459 }
39460 }
39461 }
39462 #endif
39464 /* AMD Athlon works faster
39465 when RET is not destination of conditional jump or directly preceded
39466 by other jump instruction. We avoid the penalty by inserting NOP just
39467 before the RET instructions in such cases. */
39468 static void
39470 {
39471 edge e;
39472 edge_iterator ei;
39475 {
39478 rtx prev;
39488 {
39489 edge e;
39490 edge_iterator ei;
39495 {
39498 }
39499 }
39501 {
39507 /* Empty functions get branch mispredict even when
39508 the jump destination is not visible to us. */
39511 }
39513 {
39516 }
39517 }
39518 }
39520 /* Count the minimum number of instructions in BB. Return 4 if the
39521 number of instructions >= 4. */
39523 static int
39525 {
39526 rtx insn;
39529 /* Count number of instructions in this block. Return 4 if the number
39530 of instructions >= 4. */
39532 {
39533 /* Only happen in exit blocks. */
39541 {
39542 insn_count++;
39545 }
39546 }
39549 }
39552 /* Count the minimum number of instructions in code path in BB.
39553 Return 4 if the number of instructions >= 4. */
39555 static int
39557 {
39558 edge e;
39559 edge_iterator ei;
39562 /* Only bother counting instructions along paths with no
39563 more than 2 basic blocks between entry and exit. Given
39564 that BB has an edge to exit, determine if a predecessor
39565 of BB has an edge from entry. If so, compute the number
39566 of instructions in the predecessor block. If there
39567 happen to be multiple such blocks, compute the minimum. */
39570 {
39571 edge prev_e;
39572 edge_iterator prev_ei;
39575 {
39578 }
39580 {
39582 {
39587 }
39588 }
39589 }
39595 }
39597 /* Pad short function to 4 instructions. */
39599 static void
39601 {
39602 edge e;
39603 edge_iterator ei;
39606 {
39609 {
39612 /* Pad short function. */
39614 {
39617 /* Find epilogue. */
39626 /* Two NOPs count as one instruction. */
39629 }
39630 }
39631 }
39632 }
39634 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39635 the epilogue, the Windows system unwinder will apply epilogue logic and
39636 produce incorrect offsets. This can be avoided by adding a nop between
39637 the last insn that can throw and the first insn of the epilogue. */
39639 static void
39641 {
39642 edge e;
39643 edge_iterator ei;
39646 {
39649 /* Find the beginning of the epilogue. */
39656 /* We only care about preceding insns that can throw. */
39661 /* Do not separate calls from their debug information. */
39667 else
39671 }
39672 }
39674 /* Implement machine specific optimizations. We implement padding of returns
39675 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39676 static void
39678 {
39679 /* We are freeing block_for_insn in the toplev to keep compatibility
39680 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39687 {
39692 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39695 #endif
39696 }
39697 }
39699 /* Return nonzero when QImode register that must be represented via REX prefix
39700 is used. */
39701 bool
39703 {
39711 }
39713 /* Return nonzero when P points to register encoded via REX prefix.
39714 Called via for_each_rtx. */
39715 static int
39717 {
39723 }
39725 /* Return true when INSN mentions register that must be encoded using REX
39726 prefix. */
39727 bool
39729 {
39732 }
39734 /* If profitable, negate (without causing overflow) integer constant
39735 of mode MODE at location LOC. Return true in this case. */
39736 bool
39738 {
39739 HOST_WIDE_INT val;
39745 {
39747 /* DImode x86_64 constants must fit in 32 bits. */
39760 }
39762 /* Avoid overflows. */
39768 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39769 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39772 {
39775 }
39778 }
39780 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39781 optabs would emit if we didn't have TFmode patterns. */
39783 void
39785 {
39819 }
39820 \f
39821 /* AVX512F does support 64-byte integer vector operations,
39822 thus the longest vector we are faced with is V64QImode. */
39823 #define MAX_VECT_LEN 64
39825 struct expand_vec_perm_d
39826 {
39833 };
39839 /* Get a vector mode of the same size as the original but with elements
39840 twice as wide. This is only guaranteed to apply to integral vectors. */
39844 {
39845 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39850 }
39852 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39853 fill target with val via vec_duplicate. */
39855 static bool
39857 {
39861 /* First attempt to recognize VAL as-is. */
39865 {
39866 rtx seq;
39867 /* If that fails, force VAL into a register. */
39878 }
39880 }
39882 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39883 with all elements equal to VAR. Return true if successful. */
39885 static bool
39888 {
39892 {
39897 /* FALLTHRU */
39917 {
39918 rtx x;
39925 }
39935 {
39939 permute:
39947 /* Extend to SImode using a paradoxical SUBREG. */
39951 /* Insert the SImode value as low element of a V4SImode vector. */
39960 }
39968 widen:
39969 /* Replicate the value once into the next wider mode and recurse. */
39970 {
39972 rtx x;
39989 }
39993 {
40002 }
40007 }
40008 }
40010 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
40011 whose ONE_VAR element is VAR, and other elements are zero. Return true
40012 if successful. */
40014 static bool
40017 {
40019 rtx new_target;
40024 {
40026 /* For SSE4.1, we normally use vector set. But if the second
40027 element is zero and inter-unit moves are OK, we use movq
40028 instead. */
40030 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
40052 /* Use ix86_expand_vector_set in 64bit mode only. */
40057 }
40060 {
40065 }
40068 {
40073 /* FALLTHRU */
40088 else
40095 {
40096 /* We need to shuffle the value to the correct position, so
40097 create a new pseudo to store the intermediate result. */
40099 /* With SSE2, we can use the integer shuffle insns. */
40101 {
40103 const1_rtx,
40110 }
40112 /* Otherwise convert the intermediate result to V4SFmode and
40113 use the SSE1 shuffle instructions. */
40115 {
40118 }
40119 else
40123 const1_rtx,
40132 }
40147 widen:
40151 /* Zero extend the variable element to SImode and recurse. */
40164 }
40165 }
40167 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
40168 consisting of the values in VALS. It is known that all elements
40169 except ONE_VAR are constants. Return true if successful. */
40171 static bool
40174 {
40184 {
40189 /* For the two element vectors, it's just as easy to use
40190 the general case. */
40194 /* Use ix86_expand_vector_set in 64bit mode only. */
40216 widen:
40217 /* There's no way to set one QImode entry easily. Combine
40218 the variable value with its adjacent constant value, and
40219 promote to an HImode set. */
40222 {
40227 }
40228 else
40229 {
40232 }
40246 }
40251 }
40253 /* A subroutine of ix86_expand_vector_init_general. Use vector
40254 concatenate to handle the most general case: all values variable,
40255 and none identical. */
40257 static void
40260 {
40263 rtvec v;
40267 {
40270 {
40315 }
40328 {
40343 }
40348 {
40367 }
40372 {
40385 }
40388 half:
40389 /* FIXME: We process inputs backward to help RA. PR 36222. */
40393 {
40398 }
40402 {
40406 {
40410 }
40413 {
40417 }
40420 }
40422 {
40425 {
40429 }
40432 }
40433 else
40439 }
40440 }
40442 /* A subroutine of ix86_expand_vector_init_general. Use vector
40443 interleave to handle the most general case: all values variable,
40444 and none identical. */
40446 static void
40449 {
40458 {
40479 }
40482 {
40483 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40487 /* Insert the SImode value as low element of V4SImode vector. */
40491 op0),
40493 const1_rtx);
40496 /* Cast the V4SImode vector back to a vector in orignal mode. */
40500 /* Load even elements into the second position. */
40504 const1_rtx));
40506 /* Cast vector to FIRST_IMODE vector. */
40509 }
40511 /* Interleave low FIRST_IMODE vectors. */
40513 {
40517 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40520 }
40522 /* Interleave low SECOND_IMODE vectors. */
40524 {
40527 {
40532 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40533 vector. */
40536 }
40539 /* FALLTHRU */
40546 /* Cast the SECOND_IMODE vector back to a vector on original
40547 mode. */
40554 }
40555 }
40557 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40558 all values variable, and none identical. */
40560 static void
40563 {
40569 {
40574 /* FALLTHRU */
40602 half:
40619 /* FALLTHRU */
40625 /* Don't use ix86_expand_vector_init_interleave if we can't
40626 move from GPR to SSE register directly. */
40642 }
40644 {
40656 {
40660 {
40666 else
40667 {
40672 }
40673 }
40676 }
40681 {
40687 }
40689 {
40695 }
40696 else
40698 }
40699 }
40701 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40702 instructions unless MMX_OK is true. */
40704 void
40706 {
40713 rtx x;
40716 {
40726 }
40728 /* Constants are best loaded from the constant pool. */
40730 {
40733 }
40735 /* If all values are identical, broadcast the value. */
40741 /* Values where only one field is non-constant are best loaded from
40742 the pool and overwritten via move later. */
40744 {
40748 one_var))
40753 }
40756 }
40758 void
40760 {
40765 rtx tmp;
40767 = {
40774 };
40776 = {
40783 };
40787 {
40791 {
40796 else
40800 }
40812 else
40818 {
40821 /* For the two element vectors, we implement a VEC_CONCAT with
40822 the extraction of the other element. */
40829 else
40834 }
40843 {
40849 /* tmp = target = A B C D */
40851 /* target = A A B B */
40853 /* target = X A B B */
40855 /* target = A X C D */
40862 /* tmp = target = A B C D */
40864 /* tmp = X B C D */
40866 /* target = A B X D */
40873 /* tmp = target = A B C D */
40875 /* tmp = X B C D */
40877 /* target = A B X D */
40885 }
40893 /* Element 0 handled by vec_merge below. */
40895 {
40898 }
40901 {
40902 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40903 store into element 0, then shuffle them back. */
40920 }
40921 else
40922 {
40923 /* For SSE1, we have to reuse the V4SF code. */
40927 }
40980 half:
40981 /* Compute offset. */
40987 /* Extract the half. */
40991 /* Put val in tmp at elt. */
40994 /* Put it back. */
41000 }
41003 {
41007 }
41008 else
41009 {
41018 }
41019 }
41021 void
41023 {
41027 rtx tmp;
41030 {
41035 /* FALLTHRU */
41048 {
41068 }
41080 {
41082 {
41102 }
41106 }
41107 else
41108 {
41109 /* For SSE1, we have to reuse the V4SF code. */
41113 }
41129 {
41133 else
41137 }
41142 {
41146 else
41150 }
41155 {
41159 else
41163 }
41168 {
41172 else
41176 }
41181 {
41185 else
41189 }
41194 {
41198 else
41202 }
41209 else
41218 else
41227 else
41236 else
41242 /* ??? Could extract the appropriate HImode element and shift. */
41245 }
41248 {
41252 /* Let the rtl optimizers know about the zero extension performed. */
41254 {
41257 }
41260 }
41261 else
41262 {
41269 }
41270 }
41272 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
41273 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
41274 The upper bits of DEST are undefined, though they shouldn't cause
41275 exceptions (some bits from src or all zeros are ok). */
41277 static void
41279 {
41282 {
41286 else
41304 else
41311 else
41319 {
41324 const1_rtx);
41325 }
41326 else
41327 {
41331 }
41351 else
41373 }
41377 }
41379 /* Expand a vector reduction. FN is the binary pattern to reduce;
41380 DEST is the destination; IN is the input vector. */
41382 void
41384 {
41389 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41393 {
41396 }
41401 {
41406 else
41410 }
41411 }
41412 \f
41413 /* Target hook for scalar_mode_supported_p. */
41414 static bool
41416 {
41421 else
41423 }
41425 /* Implements target hook vector_mode_supported_p. */
41426 static bool
41428 {
41442 }
41444 /* Target hook for c_mode_for_suffix. */
41445 static enum machine_mode
41447 {
41454 }
41456 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41458 We do this in the new i386 backend to maintain source compatibility
41459 with the old cc0-based compiler. */
41461 static tree
41463 tree inputs ATTRIBUTE_UNUSED,
41464 tree clobbers)
41465 {
41467 clobbers);
41469 clobbers);
41471 }
41473 /* Implements target vector targetm.asm.encode_section_info. */
41475 static void ATTRIBUTE_UNUSED
41477 {
41484 }
41486 /* Worker function for REVERSE_CONDITION. */
41488 enum rtx_code
41490 {
41494 }
41496 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41497 to OPERANDS[0]. */
41501 {
41503 {
41506 {
41510 }
41514 }
41516 {
41520 else
41521 {
41522 /* There is no non-popping store to memory for XFmode.
41523 So if we need one, follow the store with a load. */
41526 else
41528 }
41529 }
41530 else
41532 }
41534 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41535 FP status register is set. */
41537 void
41539 {
41541 rtx temp;
41546 {
41551 }
41552 else
41553 {
41558 }
41562 pc_rtx);
41567 }
41569 /* Output code to perform a log1p XFmode calculation. */
41572 {
41578 rtx test;
41584 XFmode));
41598 }
41600 /* Emit code for round calculation. */
41602 {
41609 rtx insn;
41614 {
41626 }
41629 {
41650 }
41658 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41660 /* scratch = fxam(op1) */
41663 UNSPEC_FXAM)));
41664 /* e1 = fabs(op1) */
41667 /* e2 = e1 + 0.5 */
41672 /* res = floor(e2) */
41674 {
41679 }
41680 else
41684 {
41687 {
41694 UNSPEC_TRUNC_NOOP)));
41695 }
41711 }
41713 /* flags = signbit(a) */
41716 /* if (flags) then res = -res */
41720 pc_rtx);
41731 }
41733 /* Output code to perform a Newton-Rhapson approximation of a single precision
41734 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41737 {
41745 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41749 /* x0 = rcp(b) estimate */
41753 UNSPEC_RCP14)));
41754 else
41757 UNSPEC_RCP)));
41759 /* e0 = x0 * b */
41763 /* e0 = x0 * e0 */
41767 /* e1 = x0 + x0 */
41771 /* x1 = e1 - e0 */
41775 /* res = a * x1 */
41778 }
41780 /* Output code to perform a Newton-Rhapson approximation of a
41781 single precision floating point [reciprocal] square root. */
41785 {
41787 REAL_VALUE_TYPE r;
41804 {
41807 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41810 }
41812 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41813 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41817 /* x0 = rsqrt(a) estimate */
41820 unspec)));
41822 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41824 {
41832 /* Handle masked compare. */
41834 {
41836 /* Imm value 0x4 corresponds to not-equal comparison. */
41839 }
41840 else
41841 {
41847 }
41848 }
41850 /* e0 = x0 * a */
41853 /* e1 = e0 * x0 */
41857 /* e2 = e1 - 3. */
41864 /* e3 = -.5 * x0 */
41867 else
41868 /* e3 = -.5 * e0 */
41871 /* ret = e2 * e3 */
41874 }
41876 #ifdef TARGET_SOLARIS
41877 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41879 static void
41881 tree decl)
41882 {
41883 /* With Binutils 2.15, the "@unwind" marker must be specified on
41884 every occurrence of the ".eh_frame" section, not just the first
41885 one. */
41888 {
41892 }
41894 #ifndef USE_GAS
41896 {
41899 }
41900 #endif
41903 }
41906 /* Return the mangling of TYPE if it is an extended fundamental type. */
41910 {
41918 {
41920 /* __float128 is "g". */
41923 /* "long double" or __float80 is "e". */
41927 }
41928 }
41930 /* For 32-bit code we can save PIC register setup by using
41931 __stack_chk_fail_local hidden function instead of calling
41932 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41933 register, so it is better to call __stack_chk_fail directly. */
41935 static tree ATTRIBUTE_UNUSED
41937 {
41938 return TARGET_64BIT
41941 }
41943 /* Select a format to encode pointers in exception handling data. CODE
41944 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41945 true if the symbol may be affected by dynamic relocations.
41947 ??? All x86 object file formats are capable of representing this.
41948 After all, the relocation needed is the same as for the call insn.
41949 Whether or not a particular assembler allows us to enter such, I
41950 guess we'll have to see. */
41951 int
41953 {
41955 {
41962 }
41967 }
41968 \f
41969 /* Expand copysign from SIGN to the positive value ABS_VALUE
41970 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41971 the sign-bit. */
41972 static void
41974 {
41978 {
41985 else
41990 {
41991 /* We need to generate a scalar mode mask in this case. */
41996 }
41997 }
41998 else
42004 }
42006 /* Expand fabs (OP0) and return a new rtx that holds the result. The
42007 mask for masking out the sign-bit is stored in *SMASK, if that is
42008 non-null. */
42009 static rtx
42011 {
42020 else
42024 {
42025 /* We need to generate a scalar mode mask in this case. */
42030 }
42038 }
42040 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
42041 swapping the operands if SWAP_OPERANDS is true. The expanded
42042 code is a forward jump to a newly created label in case the
42043 comparison is true. The generated label rtx is returned. */
42044 static rtx
42047 {
42052 {
42056 }
42069 }
42071 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
42072 using comparison code CODE. Operands are swapped for the comparison if
42073 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
42074 static rtx
42077 {
42083 {
42087 }
42094 }
42096 /* Generate and return a rtx of mode MODE for 2**n where n is the number
42097 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
42098 static rtx
42100 {
42101 REAL_VALUE_TYPE TWO52r;
42102 rtx TWO52;
42109 }
42111 /* Expand SSE sequence for computing lround from OP1 storing
42112 into OP0. */
42113 void
42115 {
42116 /* C code for the stuff we're doing below:
42117 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
42118 return (long)tmp;
42119 */
42123 rtx adj;
42125 /* load nextafter (0.5, 0.0) */
42130 /* adj = copysign (0.5, op1) */
42134 /* adj = op1 + adj */
42137 /* op0 = (imode)adj */
42139 }
42141 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
42142 into OPERAND0. */
42143 void
42145 {
42146 /* C code for the stuff we're doing below (for do_floor):
42147 xi = (long)op1;
42148 xi -= (double)xi > op1 ? 1 : 0;
42149 return xi;
42150 */
42155 /* reg = (long)op1 */
42159 /* freg = (double)reg */
42163 /* ireg = (freg > op1) ? ireg - 1 : ireg */
42174 }
42176 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
42177 result in OPERAND0. */
42178 void
42180 {
42181 /* C code for the stuff we're doing below:
42182 xa = fabs (operand1);
42183 if (!isless (xa, 2**52))
42184 return operand1;
42185 xa = xa + 2**52 - 2**52;
42186 return copysign (xa, operand1);
42187 */
42194 /* xa = abs (operand1) */
42197 /* if (!isless (xa, TWO52)) goto label; */
42210 }
42212 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
42213 into OPERAND0. */
42214 void
42216 {
42217 /* C code for the stuff we expand below.
42218 double xa = fabs (x), x2;
42219 if (!isless (xa, TWO52))
42220 return x;
42221 xa = xa + TWO52 - TWO52;
42222 x2 = copysign (xa, x);
42223 Compensate. Floor:
42224 if (x2 > x)
42225 x2 -= 1;
42226 Compensate. Ceil:
42227 if (x2 < x)
42228 x2 -= -1;
42229 return x2;
42230 */
42236 /* Temporary for holding the result, initialized to the input
42237 operand to ease control flow. */
42241 /* xa = abs (operand1) */
42244 /* if (!isless (xa, TWO52)) goto label; */
42247 /* xa = xa + TWO52 - TWO52; */
42251 /* xa = copysign (xa, operand1) */
42254 /* generate 1.0 or -1.0 */
42259 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42263 /* We always need to subtract here to preserve signed zero. */
42272 }
42274 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
42275 into OPERAND0. */
42276 void
42278 {
42279 /* C code for the stuff we expand below.
42280 double xa = fabs (x), x2;
42281 if (!isless (xa, TWO52))
42282 return x;
42283 x2 = (double)(long)x;
42284 Compensate. Floor:
42285 if (x2 > x)
42286 x2 -= 1;
42287 Compensate. Ceil:
42288 if (x2 < x)
42289 x2 += 1;
42290 if (HONOR_SIGNED_ZEROS (mode))
42291 return copysign (x2, x);
42292 return x2;
42293 */
42299 /* Temporary for holding the result, initialized to the input
42300 operand to ease control flow. */
42304 /* xa = abs (operand1) */
42307 /* if (!isless (xa, TWO52)) goto label; */
42310 /* xa = (double)(long)x */
42315 /* generate 1.0 */
42318 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42333 }
42335 /* Expand SSE sequence for computing round from OPERAND1 storing
42336 into OPERAND0. Sequence that works without relying on DImode truncation
42337 via cvttsd2siq that is only available on 64bit targets. */
42338 void
42340 {
42341 /* C code for the stuff we expand below.
42342 double xa = fabs (x), xa2, x2;
42343 if (!isless (xa, TWO52))
42344 return x;
42345 Using the absolute value and copying back sign makes
42346 -0.0 -> -0.0 correct.
42347 xa2 = xa + TWO52 - TWO52;
42348 Compensate.
42349 dxa = xa2 - xa;
42350 if (dxa <= -0.5)
42351 xa2 += 1;
42352 else if (dxa > 0.5)
42353 xa2 -= 1;
42354 x2 = copysign (xa2, x);
42355 return x2;
42356 */
42362 /* Temporary for holding the result, initialized to the input
42363 operand to ease control flow. */
42367 /* xa = abs (operand1) */
42370 /* if (!isless (xa, TWO52)) goto label; */
42373 /* xa2 = xa + TWO52 - TWO52; */
42377 /* dxa = xa2 - xa; */
42380 /* generate 0.5, 1.0 and -0.5 */
42386 /* Compensate. */
42388 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42393 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42399 /* res = copysign (xa2, operand1) */
42406 }
42408 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42409 into OPERAND0. */
42410 void
42412 {
42413 /* C code for SSE variant we expand below.
42414 double xa = fabs (x), x2;
42415 if (!isless (xa, TWO52))
42416 return x;
42417 x2 = (double)(long)x;
42418 if (HONOR_SIGNED_ZEROS (mode))
42419 return copysign (x2, x);
42420 return x2;
42421 */
42427 /* Temporary for holding the result, initialized to the input
42428 operand to ease control flow. */
42432 /* xa = abs (operand1) */
42435 /* if (!isless (xa, TWO52)) goto label; */
42438 /* x = (double)(long)x */
42450 }
42452 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42453 into OPERAND0. */
42454 void
42456 {
42460 /* C code for SSE variant we expand below.
42461 double xa = fabs (x), x2;
42462 if (!isless (xa, TWO52))
42463 return x;
42464 xa2 = xa + TWO52 - TWO52;
42465 Compensate:
42466 if (xa2 > xa)
42467 xa2 -= 1.0;
42468 x2 = copysign (xa2, x);
42469 return x2;
42470 */
42474 /* Temporary for holding the result, initialized to the input
42475 operand to ease control flow. */
42479 /* xa = abs (operand1) */
42482 /* if (!isless (xa, TWO52)) goto label; */
42485 /* res = xa + TWO52 - TWO52; */
42490 /* generate 1.0 */
42493 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42501 /* res = copysign (res, operand1) */
42508 }
42510 /* Expand SSE sequence for computing round from OPERAND1 storing
42511 into OPERAND0. */
42512 void
42514 {
42515 /* C code for the stuff we're doing below:
42516 double xa = fabs (x);
42517 if (!isless (xa, TWO52))
42518 return x;
42519 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42520 return copysign (xa, x);
42521 */
42527 /* Temporary for holding the result, initialized to the input
42528 operand to ease control flow. */
42536 /* load nextafter (0.5, 0.0) */
42541 /* xa = xa + 0.5 */
42545 /* xa = (double)(int64_t)xa */
42550 /* res = copysign (xa, operand1) */
42557 }
42559 /* Expand SSE sequence for computing round
42560 from OP1 storing into OP0 using sse4 round insn. */
42561 void
42563 {
42572 {
42583 }
42585 /* round (a) = trunc (a + copysign (0.5, a)) */
42587 /* load nextafter (0.5, 0.0) */
42593 /* e1 = copysign (0.5, op1) */
42597 /* e2 = op1 + e1 */
42600 /* res = trunc (e2) */
42605 }
42606 \f
42608 /* Table of valid machine attributes. */
42610 {
42611 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42612 affects_type_identity } */
42613 /* Stdcall attribute says callee is responsible for popping arguments
42614 if they are not variable. */
42617 /* Fastcall attribute says callee is responsible for popping arguments
42618 if they are not variable. */
42621 /* Thiscall attribute says callee is responsible for popping arguments
42622 if they are not variable. */
42625 /* Cdecl attribute says the callee is a normal C declaration */
42628 /* Regparm attribute specifies how many integer arguments are to be
42629 passed in registers. */
42632 /* Sseregparm attribute says we are using x86_64 calling conventions
42633 for FP arguments. */
42636 /* The transactional memory builtins are implicitly regparm or fastcall
42637 depending on the ABI. Override the generic do-nothing attribute that
42638 these builtins were declared with. */
42641 /* force_align_arg_pointer says this function realigns the stack at entry. */
42644 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42649 #endif
42654 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42655 SUBTARGET_ATTRIBUTE_TABLE,
42656 #endif
42657 /* ms_abi and sysv_abi calling convention function attributes. */
42664 /* End element. */
42666 };
42668 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42669 static int
42671 tree vectype,
42673 {
42677 {
42722 }
42723 }
42725 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42726 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42727 insn every time. */
42731 /* Initialize vselect_insn. */
42733 static void
42735 {
42737 rtx x;
42748 }
42750 /* Construct (set target (vec_select op0 (parallel perm))) and
42751 return true if that's a valid instruction in the active ISA. */
42753 static bool
42756 {
42782 }
42784 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42786 static bool
42790 {
42792 rtx x;
42807 }
42809 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42810 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42812 static bool
42814 {
42823 ;
42825 ;
42827 ;
42828 else
42831 /* This is a blend, not a permute. Elements must stay in their
42832 respective lanes. */
42834 {
42838 }
42843 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42844 decision should be extracted elsewhere, so that we only try that
42845 sequence once all budget==3 options have been tried. */
42852 {
42876 /* See if bytes move in pairs so we can use pblendw with
42877 an immediate argument, rather than pblendvb with a vector
42878 argument. */
42881 {
42882 use_pblendvb:
42886 finish_pblendvb:
42892 else
42897 }
42902 /* FALLTHRU */
42904 do_subreg:
42911 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42915 /* See if bytes move in quadruplets. If yes, vpblendd
42916 with immediate can be used. */
42921 {
42922 /* See if bytes move the same in both lanes. If yes,
42923 vpblendw with immediate can be used. */
42928 /* Use vpblendw. */
42933 }
42935 /* Use vpblendd. */
42942 /* See if words move in pairs. If yes, vpblendd can be used. */
42947 {
42948 /* See if words move the same in both lanes. If not,
42949 vpblendvb must be used. */
42952 {
42953 /* Use vpblendvb. */
42963 }
42965 /* Use vpblendw. */
42969 }
42971 /* Use vpblendd. */
42978 /* Use vpblendd. */
42986 }
42988 /* This matches five different patterns with the different modes. */
42996 }
42998 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42999 in terms of the variable form of vpermilps.
43001 Note that we will have already failed the immediate input vpermilps,
43002 which requires that the high and low part shuffle be identical; the
43003 variable form doesn't require that. */
43005 static bool
43007 {
43014 /* We can only permute within the 128-bit lane. */
43016 {
43020 }
43026 {
43029 /* Within each 128-bit lane, the elements of op0 are numbered
43030 from 0 and the elements of op1 are numbered from 4. */
43037 }
43044 }
43046 /* Return true if permutation D can be performed as VMODE permutation
43047 instead. */
43049 static bool
43051 {
43066 else
43072 }
43074 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43075 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
43077 static bool
43079 {
43088 {
43090 {
43093 {
43097 /* Use vperm2i128 insn. The pattern uses
43098 V4DImode instead of V2TImode. */
43111 }
43113 }
43114 }
43115 else
43116 {
43118 {
43121 }
43123 {
43127 /* V4DImode should be already handled through
43128 expand_vselect by vpermq instruction. */
43135 {
43136 /* First see if vpermq can be used for
43137 V8SImode/V16HImode/V32QImode. */
43139 {
43147 {
43151 }
43153 }
43155 /* Next see if vpermd can be used. */
43158 }
43159 /* Or if vpermps can be used. */
43164 {
43165 /* vpshufb only works intra lanes, it is not
43166 possible to shuffle bytes in between the lanes. */
43170 }
43171 }
43172 else
43174 }
43182 else
43183 {
43189 else
43193 {
43197 }
43198 }
43209 {
43216 else
43218 }
43219 else
43220 {
43223 }
43228 }
43230 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
43231 in a single instruction. */
43233 static bool
43235 {
43239 /* Check plain VEC_SELECT first, because AVX has instructions that could
43240 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
43241 input where SEL+CONCAT may not. */
43243 {
43249 {
43255 }
43258 {
43262 }
43264 {
43265 /* Use vpbroadcast{b,w,d}. */
43268 {
43287 /* For other modes prefer other shuffles this function creates. */
43289 }
43291 {
43295 }
43296 }
43301 /* There are plenty of patterns in sse.md that are written for
43302 SEL+CONCAT and are not replicated for a single op. Perhaps
43303 that should be changed, to avoid the nastiness here. */
43305 /* Recognize interleave style patterns, which means incrementing
43306 every other permutation operand. */
43308 {
43311 }
43316 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43318 {
43320 {
43325 }
43330 }
43331 }
43333 /* Finally, try the fully general two operand permute. */
43338 /* Recognize interleave style patterns with reversed operands. */
43340 {
43342 {
43346 else
43349 }
43354 }
43356 /* Try the SSE4.1 blend variable merge instructions. */
43360 /* Try one of the AVX vpermil variable permutations. */
43364 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43365 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43369 /* Try the AVX512F vpermi2 instructions. */
43383 }
43385 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43386 in terms of a pair of pshuflw + pshufhw instructions. */
43388 static bool
43390 {
43398 /* The two permutations only operate in 64-bit lanes. */
43409 /* Emit the pshuflw. */
43416 /* Emit the pshufhw. */
43424 }
43426 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43427 the permutation using the SSSE3 palignr instruction. This succeeds
43428 when all of the elements in PERM fit within one vector and we merely
43429 need to shift them down so that a single vector permutation has a
43430 chance to succeed. */
43432 static bool
43434 {
43441 /* Even with AVX, palignr only operates on 128-bit vectors. */
43447 {
43453 }
43457 /* Given that we have SSSE3, we know we'll be able to implement the
43458 single operand permutation after the palignr with pshufb. */
43473 {
43478 }
43480 /* Test for the degenerate case where the alignment by itself
43481 produces the desired permutation. */
43483 {
43486 }
43492 }
43496 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43497 a two vector permutation into a single vector permutation by using
43498 an interleave operation to merge the vectors. */
43500 static bool
43502 {
43507 rtx seq;
43511 {
43514 }
43516 {
43519 /* For 32-byte modes allow even d->one_operand_p.
43520 The lack of cross-lane shuffling in some instructions
43521 might prevent a single insn shuffle. */
43524 /* If expand_vec_perm_interleave3 can expand this into
43525 a 3 insn sequence, give up and let it be expanded as
43526 3 insn sequence. While that is one insn longer,
43527 it doesn't need a memory operand and in the common
43528 case that both interleave low and high permutations
43529 with the same operands are adjacent needs 4 insns
43530 for both after CSE. */
43533 }
43534 else
43537 /* Examine from whence the elements come. */
43546 {
43549 /* Split the two input vectors into 4 halves. */
43555 /* If the elements from the low halves use interleave low, and similarly
43556 for interleave high. If the elements are from mis-matched halves, we
43557 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43559 {
43560 /* punpckl* */
43562 {
43567 }
43570 }
43572 {
43573 /* punpckh* */
43575 {
43580 }
43583 }
43585 {
43586 /* shufps */
43588 {
43593 }
43595 {
43596 /* shufpd */
43601 }
43602 }
43604 {
43605 /* shufps */
43607 {
43612 }
43614 {
43615 /* shufpd */
43620 }
43621 }
43622 else
43624 }
43625 else
43626 {
43631 /* Split the two input vectors into 8 quarters. */
43637 {
43640 }
43643 {
43647 }
43649 {
43652 }
43655 {
43657 {
43658 /* Attempt to increase the likelihood that dfinal
43659 shuffle will be intra-lane. */
43663 }
43665 /* vperm2f128 or vperm2i128. */
43667 {
43672 }
43677 {
43681 {
43684 }
43685 }
43686 }
43691 {
43692 /* vpunpckl* */
43694 {
43703 }
43704 }
43707 {
43708 /* vpunpckh* */
43710 {
43719 }
43720 }
43721 else
43723 }
43725 /* Use the remapping array set up above to move the elements from their
43726 swizzled locations into their final destinations. */
43729 {
43732 /* If same_halves is true, both halves of the remapped vector are the
43733 same. Avoid cross-lane accesses if possible. */
43735 {
43738 }
43739 else
43741 }
43743 {
43746 }
43750 /* Test if the final remap can be done with a single insn. For V4SFmode or
43751 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43764 {
43767 }
43774 }
43776 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43777 a single vector cross-lane permutation into vpermq followed
43778 by any of the single insn permutations. */
43780 static bool
43782 {
43796 {
43799 }
43802 {
43807 }
43820 {
43827 }
43834 {
43839 ;
43842 else
43844 }
43853 }
43855 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43856 a vector permutation using two instructions, vperm2f128 resp.
43857 vperm2i128 followed by any single in-lane permutation. */
43859 static bool
43861 {
43875 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43876 immediate. For perm < 16 the second permutation uses
43877 d->op0 as first operand, for perm >= 16 it uses d->op1
43878 as first operand. The second operand is the result of
43879 vperm2[fi]128. */
43881 {
43882 /* Ignore permutations which do not move anything cross-lane. */
43884 {
43885 /* The second shuffle for e.g. V4DFmode has
43886 0123 and ABCD operands.
43887 Ignore AB23, as 23 is already in the second lane
43888 of the first operand. */
43890 /* And 01CD, as 01 is in the first lane of the first
43891 operand. */
43893 /* And 4567, as then the vperm2[fi]128 doesn't change
43894 anything on the original 4567 second operand. */
43896 }
43897 else
43898 {
43899 /* The second shuffle for e.g. V4DFmode has
43900 4567 and ABCD operands.
43901 Ignore AB67, as 67 is already in the second lane
43902 of the first operand. */
43904 /* And 45CD, as 45 is in the first lane of the first
43905 operand. */
43907 /* And 0123, as then the vperm2[fi]128 doesn't change
43908 anything on the original 0123 first operand. */
43910 }
43913 {
43919 else
43921 }
43924 {
43928 }
43929 else
43933 {
43937 /* Found a usable second shuffle. dfirst will be
43938 vperm2f128 on d->op0 and d->op1. */
43949 /* And dsecond is some single insn shuffle, taking
43950 d->op0 and result of vperm2f128 (if perm < 16) or
43951 d->op1 and result of vperm2f128 (otherwise). */
43960 }
43962 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43965 }
43968 }
43970 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43971 a two vector permutation using 2 intra-lane interleave insns
43972 and cross-lane shuffle for 32-byte vectors. */
43974 static bool
43976 {
43983 ;
43985 ;
43986 else
44001 {
44005 else
44011 else
44017 else
44023 else
44029 else
44035 else
44040 }
44044 }
44046 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
44047 a single vector permutation using a single intra-lane vector
44048 permutation, vperm2f128 swapping the lanes and vblend* insn blending
44049 the non-swapped and swapped vectors together. */
44051 static bool
44053 {
44056 rtx seq;
44061 || TARGET_AVX2
44070 {
44077 }
44112 }
44114 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
44115 permutation using two vperm2f128, followed by a vshufpd insn blending
44116 the two vectors together. */
44118 static bool
44120 {
44163 }
44165 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
44166 permutation with two pshufb insns and an ior. We should have already
44167 failed all two instruction sequences. */
44169 static bool
44171 {
44185 /* Generate two permutation masks. If the required element is within
44186 the given vector it is shuffled into the proper lane. If the required
44187 element is in the other vector, force a zero into the lane by setting
44188 bit 7 in the permutation mask. */
44191 {
44198 {
44201 }
44202 }
44226 }
44228 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
44229 with two vpshufb insns, vpermq and vpor. We should have already failed
44230 all two or three instruction sequences. */
44232 static bool
44234 {
44249 /* Generate two permutation masks. If the required element is within
44250 the same lane, it is shuffled in. If the required element from the
44251 other lane, force a zero by setting bit 7 in the permutation mask.
44252 In the other mask the mask has non-negative elements if element
44253 is requested from the other lane, but also moved to the other lane,
44254 so that the result of vpshufb can have the two V2TImode halves
44255 swapped. */
44258 {
44263 {
44266 }
44267 }
44276 /* Swap the 128-byte lanes of h into hp. */
44280 const1_rtx));
44297 }
44299 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44300 and extract-odd permutations of two V32QImode and V16QImode operand
44301 with two vpshufb insns, vpor and vpermq. We should have already
44302 failed all two or three instruction sequences. */
44304 static bool
44306 {
44325 /* Generate two permutation masks. In the first permutation mask
44326 the first quarter will contain indexes for the first half
44327 of the op0, the second quarter will contain bit 7 set, third quarter
44328 will contain indexes for the second half of the op0 and the
44329 last quarter bit 7 set. In the second permutation mask
44330 the first quarter will contain bit 7 set, the second quarter
44331 indexes for the first half of the op1, the third quarter bit 7 set
44332 and last quarter indexes for the second half of the op1.
44333 I.e. the first mask e.g. for V32QImode extract even will be:
44334 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44335 (all values masked with 0xf except for -128) and second mask
44336 for extract even will be
44337 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44340 {
44346 {
44349 }
44350 }
44369 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44377 }
44379 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44380 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
44381 with two "and" and "pack" or two "shift" and "pack" insns. We should
44382 have already failed all two instruction sequences. */
44384 static bool
44386 {
44390 machine_mode half_mode;
44399 {
44401 /* Required for "pack". */
44412 /* No check as all instructions are SSE2. */
44443 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
44444 general shuffles. */
44446 }
44448 /* Check that permutation is even or odd. */
44463 {
44470 }
44471 else
44472 {
44479 }
44480 /* In AVX2 for 256 bit case we need to permute pack result. */
44482 {
44488 const0_rtx,
44489 const2_rtx,
44490 const1_rtx,
44493 }
44494 else
44498 }
44500 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44501 and extract-odd permutations. */
44503 static bool
44505 {
44509 {
44516 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44520 /* Now an unpck[lh]pd will produce the result required. */
44523 else
44529 {
44538 /* Shuffle within the 128-bit lanes to produce:
44539 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44543 /* Shuffle the lanes around to produce:
44544 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44548 /* Shuffle within the 128-bit lanes to produce:
44549 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44552 /* Shuffle within the 128-bit lanes to produce:
44553 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44556 /* Shuffle the lanes around to produce:
44557 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44560 }
44567 /* These are always directly implementable by expand_vec_perm_1. */
44575 else
44576 {
44579 /* We need 2*log2(N)-1 operations to achieve odd/even
44580 with interleave. */
44589 else
44592 }
44604 {
44609 else
44614 {
44619 }
44621 }
44629 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44633 /* Now an vpunpck[lh]qdq will produce the result required. */
44636 else
44643 {
44648 else
44653 {
44658 }
44660 }
44671 /* Shuffle the lanes around into
44672 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44680 /* Swap the 2nd and 3rd position in each lane into
44681 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44687 /* Now an vpunpck[lh]qdq will produce
44688 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44692 else
44701 }
44704 }
44706 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44707 extract-even and extract-odd permutations. */
44709 static bool
44711 {
44723 }
44725 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44726 permutations. We assume that expand_vec_perm_1 has already failed. */
44728 static bool
44730 {
44738 {
44741 /* These are special-cased in sse.md so that we can optionally
44742 use the vbroadcast instruction. They expand to two insns
44743 if the input happens to be in a register. */
44750 /* These are always implementable using standard shuffle patterns. */
44755 /* These can be implemented via interleave. We save one insn by
44756 stopping once we have promoted to V4SImode and then use pshufd. */
44759 do
44760 {
44761 rtx dest;
44767 {
44771 }
44778 }
44793 /* For AVX2 broadcasts of the first element vpbroadcast* or
44794 vpermq should be used by expand_vec_perm_1. */
44800 }
44801 }
44803 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44804 broadcast permutations. */
44806 static bool
44808 {
44820 }
44822 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44823 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44824 all the shorter instruction sequences. */
44826 static bool
44828 {
44844 /* Generate 4 permutation masks. If the required element is within
44845 the same lane, it is shuffled in. If the required element from the
44846 other lane, force a zero by setting bit 7 in the permutation mask.
44847 In the other mask the mask has non-negative elements if element
44848 is requested from the other lane, but also moved to the other lane,
44849 so that the result of vpshufb can have the two V2TImode halves
44850 swapped. */
44853 {
44858 }
44864 {
44872 }
44875 {
44877 {
44880 }
44887 }
44889 /* Swap the 128-byte lanes of h[X]. */
44891 {
44897 const1_rtx));
44899 }
44902 {
44904 {
44907 }
44913 }
44916 {
44918 {
44922 }
44925 }
44935 }
44937 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44938 With all of the interface bits taken care of, perform the expansion
44939 in D and return true on success. */
44941 static bool
44943 {
44944 /* Try a single instruction expansion. */
44948 /* Try sequences of two instructions. */
44968 /* Try sequences of three instructions. */
44985 /* Try sequences of four instructions. */
44993 /* ??? Look for narrow permutations whose element orderings would
44994 allow the promotion to a wider mode. */
44996 /* ??? Look for sequences of interleave or a wider permute that place
44997 the data into the correct lanes for a half-vector shuffle like
44998 pshuf[lh]w or vpermilps. */
45000 /* ??? Look for sequences of interleave that produce the desired results.
45001 The combinatorics of punpck[lh] get pretty ugly... */
45006 /* Even longer sequences. */
45011 }
45013 /* If a permutation only uses one operand, make it clear. Returns true
45014 if the permutation references both operands. */
45016 static bool
45018 {
45026 {
45032 {
45035 }
45036 /* The elements of PERM do not suggest that only the first operand
45037 is used, but both operands are identical. Allow easier matching
45038 of the permutation by folding the permutation into the single
45039 input vector. */
45040 /* FALLTHRU */
45051 }
45054 }
45056 bool
45058 {
45063 rtx sel;
45080 {
45085 }
45092 /* If the selector says both arguments are needed, but the operands are the
45093 same, the above tried to expand with one_operand_p and flattened selector.
45094 If that didn't work, retry without one_operand_p; we succeeded with that
45095 during testing. */
45097 {
45101 }
45104 }
45106 /* Implement targetm.vectorize.vec_perm_const_ok. */
45108 static bool
45111 {
45120 /* Given sufficient ISA support we can just return true here
45121 for selected vector modes. */
45124 /* All implementable with a single vpermi2 insn. */
45127 {
45128 /* All implementable with a single vpperm insn. */
45131 /* All implementable with 2 pshufb + 1 ior. */
45134 /* All implementable with shufpd or unpck[lh]pd. */
45137 }
45139 /* Extract the values from the vector CST into the permutation
45140 array in D. */
45143 {
45147 }
45149 /* For all elements from second vector, fold the elements to first. */
45154 /* Check whether the mask can be applied to the vector type. */
45157 /* Implementable with shufps or pshufd. */
45161 /* Otherwise we have to go through the motions and see if we can
45162 figure out how to generate the requested permutation. */
45173 }
45175 void
45177 {
45192 /* We'll either be able to implement the permutation directly... */
45196 /* ... or we use the special-case patterns. */
45198 }
45200 static void
45202 {
45217 {
45220 }
45222 /* Note that for AVX this isn't one instruction. */
45225 }
45228 /* Expand a vector operation CODE for a V*QImode in terms of the
45229 same operation on V*HImode. */
45231 void
45233 {
45245 {
45258 }
45262 {
45264 /* Unpack data such that we've got a source byte in each low byte of
45265 each word. We don't care what goes into the high byte of each word.
45266 Rather than trying to get zero in there, most convenient is to let
45267 it be a copy of the low byte. */
45272 /* FALLTHRU */
45284 /* FALLTHRU */
45294 }
45296 /* Perform the operation. */
45303 /* Merge the data back into the right place. */
45313 {
45314 /* For SSE2, we used an full interleave, so the desired
45315 results are in the even elements. */
45318 }
45319 else
45320 {
45321 /* For AVX, the interleave used above was not cross-lane. So the
45322 extraction is evens but with the second and third quarter swapped.
45323 Happily, that is even one insn shorter than even extraction. */
45326 }
45333 }
45335 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
45336 if op is CONST_VECTOR with all odd elements equal to their
45337 preceding element. */
45339 static bool
45341 {
45351 }
45353 void
45356 {
45359 rtx x;
45367 /* We only play even/odd games with vectors of SImode. */
45370 /* If we're looking for the odd results, shift those members down to
45371 the even slots. For some cpus this is faster than a PSHUFD. */
45373 {
45374 /* For XOP use vpmacsdqh, but only for smult, as it is only
45375 signed. */
45377 {
45381 }
45392 }
45395 {
45398 else
45400 }
45402 {
45405 else
45407 }
45412 else
45413 {
45416 /* The easiest way to implement this without PMULDQ is to go through
45417 the motions as if we are performing a full 64-bit multiply. With
45418 the exception that we need to do less shuffling of the elements. */
45420 /* Compute the sign-extension, aka highparts, of the two operands. */
45426 /* Multiply LO(A) * HI(B), and vice-versa. */
45432 /* Multiply LO(A) * LO(B). */
45436 /* Combine and shift the highparts into place. */
45441 /* Combine high and low parts. */
45444 }
45446 }
45448 void
45451 {
45457 {
45462 {
45463 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45464 shuffle the elements once so that all elements are in the right
45465 place for immediate use: { A C B D }. */
45470 }
45471 else
45472 {
45473 /* Put the elements into place for the multiply. */
45477 }
45482 /* Shuffle the elements between the lanes. After this we
45483 have { A B E F | C D G H } for each operand. */
45493 /* Shuffle the elements within the lanes. After this we
45494 have { A A B B | C C D D } or { E E F F | G G H H }. */
45532 }
45533 }
45535 void
45537 {
45547 /* Move the results in element 2 down to element 1; we don't care
45548 what goes in elements 2 and 3. Then we can merge the parts
45549 back together with an interleave.
45551 Note that two other sequences were tried:
45552 (1) Use interleaves at the start instead of psrldq, which allows
45553 us to use a single shufps to merge things back at the end.
45554 (2) Use shufps here to combine the two vectors, then pshufd to
45555 put the elements in the correct order.
45556 In both cases the cost of the reformatting stall was too high
45557 and the overall sequence slower. */
45568 }
45570 void
45572 {
45577 {
45578 /* op1: A,B,C,D, op2: E,F,G,H */
45587 /* t1: B,A,D,C */
45594 /* t2: (B*E),(A*F),(D*G),(C*H) */
45597 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45600 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45603 /* Multiply lower parts and add all */
45605 emit_insn (gen_vec_widen_umult_even_v4si (t5, gen_lowpart (V4SImode, op1), gen_lowpart (V4SImode, op2)));
45607 }
45608 else
45609 {
45614 {
45617 }
45619 {
45622 }
45624 {
45627 }
45628 else
45632 /* Multiply low parts. */
45636 /* Shift input vectors right 32 bits so we can multiply high parts. */
45641 /* Multiply high parts by low parts. */
45647 /* Combine and shift the highparts back. */
45651 /* Combine high and low parts. */
45653 }
45657 }
45659 /* Calculate integer abs() using only SSE2 instructions. */
45661 void
45663 {
45668 {
45669 /* For 32-bit signed integer X, the best way to calculate the absolute
45670 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45682 /* For 16-bit signed integer X, the best way to calculate the absolute
45683 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45691 /* For 8-bit signed integer X, the best way to calculate the absolute
45692 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45693 as SSE2 provides the PMINUB insn. */
45703 }
45707 }
45709 /* Expand an insert into a vector register through pinsr insn.
45710 Return true if successful. */
45712 bool
45714 {
45722 {
45725 }
45731 {
45736 {
45743 {
45775 }
45789 }
45793 }
45794 }
45795 \f
45796 /* This function returns the calling abi specific va_list type node.
45797 It returns the FNDECL specific va_list type. */
45799 static tree
45801 {
45808 else
45810 }
45812 /* Returns the canonical va_list type specified by TYPE. If there
45813 is no valid TYPE provided, it return NULL_TREE. */
45815 static tree
45817 {
45820 /* Resolve references and pointers to va_list type. */
45829 {
45834 {
45835 /* If va_list is an array type, the argument may have decayed
45836 to a pointer type, e.g. by being passed to another function.
45837 In that case, unwrap both types so that we can compare the
45838 underlying records. */
45841 {
45844 }
45845 }
45852 {
45853 /* If va_list is an array type, the argument may have decayed
45854 to a pointer type, e.g. by being passed to another function.
45855 In that case, unwrap both types so that we can compare the
45856 underlying records. */
45859 {
45862 }
45863 }
45870 {
45871 /* If va_list is an array type, the argument may have decayed
45872 to a pointer type, e.g. by being passed to another function.
45873 In that case, unwrap both types so that we can compare the
45874 underlying records. */
45877 {
45880 }
45881 }
45885 }
45887 }
45889 /* Iterate through the target-specific builtin types for va_list.
45890 IDX denotes the iterator, *PTREE is set to the result type of
45891 the va_list builtin, and *PNAME to its internal type.
45892 Returns zero if there is no element for this index, otherwise
45893 IDX should be increased upon the next call.
45894 Note, do not iterate a base builtin's name like __builtin_va_list.
45895 Used from c_common_nodes_and_builtins. */
45897 static int
45899 {
45901 {
45903 {
45916 }
45917 }
45920 }
45922 #undef TARGET_SCHED_DISPATCH
45923 #define TARGET_SCHED_DISPATCH has_dispatch
45924 #undef TARGET_SCHED_DISPATCH_DO
45925 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45926 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45927 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45928 #undef TARGET_SCHED_REORDER
45929 #define TARGET_SCHED_REORDER ix86_sched_reorder
45930 #undef TARGET_SCHED_ADJUST_PRIORITY
45931 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45932 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45933 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45934 ix86_dependencies_evaluation_hook
45936 /* The size of the dispatch window is the total number of bytes of
45937 object code allowed in a window. */
45938 #define DISPATCH_WINDOW_SIZE 16
45940 /* Number of dispatch windows considered for scheduling. */
45941 #define MAX_DISPATCH_WINDOWS 3
45943 /* Maximum number of instructions in a window. */
45944 #define MAX_INSN 4
45946 /* Maximum number of immediate operands in a window. */
45947 #define MAX_IMM 4
45949 /* Maximum number of immediate bits allowed in a window. */
45950 #define MAX_IMM_SIZE 128
45952 /* Maximum number of 32 bit immediates allowed in a window. */
45953 #define MAX_IMM_32 4
45955 /* Maximum number of 64 bit immediates allowed in a window. */
45956 #define MAX_IMM_64 2
45958 /* Maximum total of loads or prefetches allowed in a window. */
45959 #define MAX_LOAD 2
45961 /* Maximum total of stores allowed in a window. */
45962 #define MAX_STORE 1
45964 #undef BIG
45965 #define BIG 100
45968 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45971 disp_load,
45972 disp_store,
45973 disp_load_store,
45974 disp_prefetch,
45975 disp_imm,
45976 disp_imm_32,
45977 disp_imm_64,
45978 disp_branch,
45979 disp_cmp,
45980 disp_jcc,
45981 disp_last
45982 };
45984 /* Number of allowable groups in a dispatch window. It is an array
45985 indexed by dispatch_group enum. 100 is used as a big number,
45986 because the number of these kind of operations does not have any
45987 effect in dispatch window, but we need them for other reasons in
45988 the table. */
45991 };
45997 };
45999 /* Instruction path. */
46005 last_path
46006 };
46008 /* sched_insn_info defines a window to the instructions scheduled in
46009 the basic block. It contains a pointer to the insn_info table and
46010 the instruction scheduled.
46012 Windows are allocated for each basic block and are linked
46013 together. */
46015 rtx insn;
46022 /* Linked list of dispatch windows. This is a two way list of
46023 dispatch windows of a basic block. It contains information about
46024 the number of uops in the window and the total number of
46025 instructions and of bytes in the object code for this dispatch
46026 window. */
46044 /* Immediate valuse used in an insn. */
46046 {
46055 /* Get dispatch group of insn. */
46057 static enum dispatch_group
46059 {
46075 }
46077 /* Return true if insn is a compare instruction. */
46079 static bool
46081 {
46089 }
46091 /* Return true if a dispatch violation encountered. */
46093 static bool
46095 {
46099 }
46101 /* Return true if insn is a branch instruction. */
46103 static bool
46105 {
46107 }
46109 /* Return true if insn is a prefetch instruction. */
46111 static bool
46113 {
46115 }
46117 /* This function initializes a dispatch window and the list container holding a
46118 pointer to the window. */
46120 static void
46122 {
46128 else
46146 {
46152 }
46154 }
46156 /* This function allocates and initializes a dispatch window and the
46157 list container holding a pointer to the window. */
46161 {
46166 }
46168 /* This routine initializes the dispatch scheduling information. It
46169 initiates building dispatch scheduler tables and constructs the
46170 first dispatch window. */
46172 static void
46174 {
46175 /* Allocate a dispatch list and a window. */
46180 }
46182 /* This function returns true if a branch is detected. End of a basic block
46183 does not have to be a branch, but here we assume only branches end a
46184 window. */
46186 static bool
46188 {
46190 }
46192 /* This function is called when the end of a window processing is reached. */
46194 static void
46196 {
46199 {
46204 }
46206 }
46208 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
46209 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
46210 for 48 bytes of instructions. Note that these windows are not dispatch
46211 windows that their sizes are DISPATCH_WINDOW_SIZE. */
46215 {
46217 {
46222 }
46228 }
46230 /* Increment the number of immediate operands of an instruction. */
46232 static int
46234 {
46239 {
46246 else
46257 {
46260 }
46265 }
46268 }
46270 /* Compute number of immediate operands of an instruction. */
46272 static void
46274 {
46277 }
46279 /* Return total size of immediate operands of an instruction along with number
46280 of corresponding immediate-operands. It initializes its parameters to zero
46281 befor calling FIND_CONSTANT.
46282 INSN is the input instruction. IMM is the total of immediates.
46283 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
46284 bit immediates. */
46286 static int
46288 {
46296 }
46298 /* This function indicates if an operand of an instruction is an
46299 immediate. */
46301 static bool
46303 {
46312 }
46314 /* Return single or double path for instructions. */
46316 static enum insn_path
46318 {
46328 }
46330 /* Return insn dispatch group. */
46332 static enum dispatch_group
46334 {
46352 }
46354 /* Count number of GROUP restricted instructions in a dispatch
46355 window WINDOW_LIST. */
46357 static int
46359 {
46370 {
46389 }
46402 }
46404 /* This function returns true if insn satisfies dispatch rules on the
46405 last window scheduled. */
46407 static bool
46409 {
46417 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46418 instructions should be given the lowest priority in the
46419 scheduling process in Haifa scheduler to make sure they will be
46420 scheduled in the same dispatch window as the reference to them. */
46424 /* Check nonrestricted. */
46428 /* Get last dispatch window. */
46433 {
46438 /* Window 1 is full. Go for next window. */
46440 }
46447 /* See if it fits in the first window. */
46449 {
46450 /* The first widow should have only single and double path
46451 uops. */
46457 }
46459 }
46461 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46462 dispatch window WINDOW_LIST. */
46464 static void
46466 {
46484 /* Initialize window with new instruction. */
46505 {
46508 }
46509 }
46511 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46512 If the total bytes of instructions or the number of instructions in
46513 the window exceed allowable, it allocates a new window. */
46515 static void
46517 {
46540 /* Get the last dispatch window. */
46548 else
46551 /* If current window is full, get a new window.
46552 Window number zero is full, if MAX_INSN uops are scheduled in it.
46553 Window number one is full, if window zero's bytes plus window
46554 one's bytes is 32, or if the bytes of the new instruction added
46555 to the total makes it greater than 48, or it has already MAX_INSN
46556 instructions in it. */
46565 {
46568 }
46571 {
46575 {
46578 }
46579 }
46581 {
46586 {
46589 }
46592 }
46593 else
46597 {
46598 /* End of basic block is reached do end-basic-block process. */
46601 }
46602 }
46604 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46606 DEBUG_FUNCTION static void
46608 {
46614 else
46628 {
46631 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46637 }
46638 }
46640 /* Print to stdout a dispatch window. */
46642 DEBUG_FUNCTION void
46644 {
46646 }
46648 /* Print INSN dispatch information to FILE. */
46650 DEBUG_FUNCTION static void
46652 {
46675 }
46677 /* Print to STDERR the status of the ready list with respect to
46678 dispatch windows. */
46680 DEBUG_FUNCTION void
46682 {
46690 }
46692 /* This routine is the driver of the dispatch scheduler. */
46694 static void
46696 {
46701 }
46703 /* Return TRUE if Dispatch Scheduling is supported. */
46705 static bool
46707 {
46711 {
46727 }
46730 }
46732 /* Implementation of reassociation_width target hook used by
46733 reassoc phase to identify parallelism level in reassociated
46734 tree. Statements tree_code is passed in OPC. Arguments type
46735 is passed in MODE.
46737 Currently parallel reassociation is enabled for Atom
46738 processors only and we set reassociation width to be 2
46739 because Atom may issue up to 2 instructions per cycle.
46741 Return value should be fixed if parallel reassociation is
46742 enabled for other processors. */
46744 static int
46747 {
46750 /* Vector part. */
46752 {
46755 else
46757 }
46759 /* Scalar part. */
46766 }
46768 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46769 place emms and femms instructions. */
46771 static enum machine_mode
46773 {
46778 {
46795 else
46807 /* FALLTHRU */
46811 }
46812 }
46814 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46815 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46816 256bit and 128bit vectors. */
46818 static unsigned int
46820 {
46823 }
46825 \f
46827 /* Return class of registers which could be used for pseudo of MODE
46828 and of class RCLASS for spilling instead of memory. Return NO_REGS
46829 if it is not possible or non-profitable. */
46830 static reg_class_t
46832 {
46838 }
46840 /* Implement targetm.vectorize.init_cost. */
46844 {
46848 }
46850 /* Implement targetm.vectorize.add_stmt_cost. */
46852 static unsigned
46856 {
46862 /* Statements in an inner loop relative to the loop being
46863 vectorized are weighted more heavily. The value here is
46864 arbitrary and could potentially be improved with analysis. */
46870 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
46871 for Silvermont as it has out of order integer pipeline and can execute
46872 2 scalar instruction per tick, but has in order SIMD pipeline. */
46875 {
46879 }
46884 }
46886 /* Implement targetm.vectorize.finish_cost. */
46888 static void
46891 {
46896 }
46898 /* Implement targetm.vectorize.destroy_cost_data. */
46900 static void
46902 {
46904 }
46906 /* Validate target specific memory model bits in VAL. */
46908 static unsigned HOST_WIDE_INT
46910 {
46917 {
46921 }
46924 {
46928 }
46930 {
46934 }
46936 }
46938 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46939 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46940 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46941 or number of vecsize_mangle variants that should be emitted. */
46943 static int
46947 {
46954 {
46958 }
46963 {
46970 /* case SCmode: */
46971 /* case DCmode: */
46977 }
46979 tree t;
46983 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46985 {
46992 /* case SCmode: */
46993 /* case DCmode: */
46999 }
47002 {
47003 /* Parse here processor clause. If not present, default to 'b'. */
47005 }
47007 {
47008 /* If the function isn't exported, we can pick up just one ISA
47009 for the clones. */
47014 else
47017 }
47018 else
47019 {
47022 }
47024 {
47037 }
47039 {
47042 else
47047 }
47049 }
47051 /* Add target attribute to SIMD clone NODE if needed. */
47053 static void
47055 {
47059 {
47074 }
47084 }
47086 /* If SIMD clone NODE can't be used in a vectorized loop
47087 in current function, return -1, otherwise return a badness of using it
47088 (0 if it is most desirable from vecsize_mangle point of view, 1
47089 slightly less desirable, etc.). */
47091 static int
47093 {
47095 {
47113 }
47114 }
47116 /* This function gives out the number of memory references.
47117 This value determines the unrolling factor for
47118 bdver3 and bdver4 architectures. */
47120 static int
47122 {
47124 {
47133 else
47135 }
47137 }
47139 /* This function adjusts the unroll factor based on
47140 the hardware capabilities. For ex, bdver3 has
47141 a loop buffer which makes unrolling of smaller
47142 loops less important. This function decides the
47143 unroll factor using number of memory references
47144 (value 32 is used) as a heuristic. */
47146 static unsigned
47148 {
47150 rtx insn;
47157 /* Count the number of memory references within the loop body. */
47160 {
47164 }
47171 }
47174 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
47176 static bool
47178 {
47179 /* For x87 floating point with standard excess precision handling,
47180 there is no adddf3 pattern (since x87 floating point only has
47181 XFmode operations) so the default hook implementation gets this
47182 wrong. */
47184 }
47186 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
47188 static void
47190 {
47195 {
47210 hold_fnclex);
47224 }
47226 {
47235 mxcsr_orig_var,
47245 ldmxcsr_hold_call);
47248 else
47253 ldmxcsr_clear_call);
47254 else
47258 stxmcsr_update_call);
47260 {
47266 exceptions_assign);
47267 }
47268 else
47273 ldmxcsr_update_call);
47274 }
47275 tree atomic_feraiseexcept
47280 atomic_feraiseexcept_call);
47281 }
47283 /* Try to determine BASE/OFFSET/SIZE parts of the given MEM.
47284 Return true if successful, false if all the values couldn't
47285 be determined.
47287 This function only looks for REG/SYMBOL or REG/SYMBOL+CONST
47288 address forms. */
47290 static bool
47293 {
47294 rtx addr_rtx;
47297 else
47302 else
47307 {
47310 }
47313 {
47316 }
47317 else
47321 }
47323 /* If MEM1 is adjacent to MEM2 and MEM1 has lower address,
47324 return true. */
47328 {
47334 {
47343 }
47345 }
47347 /* Initialize the GCC target structure. */
47348 #undef TARGET_RETURN_IN_MEMORY
47349 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
47351 #undef TARGET_LEGITIMIZE_ADDRESS
47352 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
47354 #undef TARGET_ATTRIBUTE_TABLE
47355 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
47356 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
47357 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
47358 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47359 # undef TARGET_MERGE_DECL_ATTRIBUTES
47360 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
47361 #endif
47363 #undef TARGET_COMP_TYPE_ATTRIBUTES
47364 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
47366 #undef TARGET_INIT_BUILTINS
47367 #define TARGET_INIT_BUILTINS ix86_init_builtins
47368 #undef TARGET_BUILTIN_DECL
47369 #define TARGET_BUILTIN_DECL ix86_builtin_decl
47370 #undef TARGET_EXPAND_BUILTIN
47371 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
47373 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
47374 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
47375 ix86_builtin_vectorized_function
47377 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
47378 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
47380 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
47381 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
47383 #undef TARGET_VECTORIZE_BUILTIN_GATHER
47384 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
47386 #undef TARGET_BUILTIN_RECIPROCAL
47387 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
47389 #undef TARGET_ASM_FUNCTION_PROLOGUE
47390 #define TARGET_ASM_FUNCTION_PROLOGUE ix86_output_function_prologue
47392 #undef TARGET_ASM_FUNCTION_EPILOGUE
47393 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
47395 #undef TARGET_ASM_NAMED_SECTION
47396 #define TARGET_ASM_NAMED_SECTION ix86_elf_asm_named_section
47398 #undef TARGET_ENCODE_SECTION_INFO
47399 #ifndef SUBTARGET_ENCODE_SECTION_INFO
47400 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
47401 #else
47402 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
47403 #endif
47405 #undef TARGET_ASM_OPEN_PAREN
47407 #undef TARGET_ASM_CLOSE_PAREN
47410 #undef TARGET_ASM_BYTE_OP
47411 #define TARGET_ASM_BYTE_OP ASM_BYTE
47413 #undef TARGET_ASM_ALIGNED_HI_OP
47414 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
47415 #undef TARGET_ASM_ALIGNED_SI_OP
47416 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
47417 #ifdef ASM_QUAD
47418 #undef TARGET_ASM_ALIGNED_DI_OP
47419 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
47420 #endif
47422 #undef TARGET_PROFILE_BEFORE_PROLOGUE
47423 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
47425 #undef TARGET_SET_FP_INSN
47426 #define TARGET_SET_FP_INSN ix86_set_fp_insn
47428 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
47429 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
47431 #undef TARGET_ASM_UNALIGNED_HI_OP
47432 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
47433 #undef TARGET_ASM_UNALIGNED_SI_OP
47434 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
47435 #undef TARGET_ASM_UNALIGNED_DI_OP
47436 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
47438 #undef TARGET_PRINT_OPERAND
47439 #define TARGET_PRINT_OPERAND ix86_print_operand
47440 #undef TARGET_PRINT_OPERAND_ADDRESS
47441 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
47442 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
47443 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
47444 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
47445 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
47447 #undef TARGET_SCHED_INIT_GLOBAL
47448 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
47449 #undef TARGET_SCHED_ADJUST_COST
47450 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
47451 #undef TARGET_SCHED_ISSUE_RATE
47452 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
47453 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
47454 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
47455 ia32_multipass_dfa_lookahead
47456 #undef TARGET_SCHED_MACRO_FUSION_P
47457 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
47458 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
47459 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
47461 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
47462 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
47464 #undef TARGET_MEMMODEL_CHECK
47465 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
47467 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
47468 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
47470 #ifdef HAVE_AS_TLS
47471 #undef TARGET_HAVE_TLS
47472 #define TARGET_HAVE_TLS true
47473 #endif
47474 #undef TARGET_CANNOT_FORCE_CONST_MEM
47475 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
47476 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
47477 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
47479 #undef TARGET_DELEGITIMIZE_ADDRESS
47480 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
47482 #undef TARGET_MS_BITFIELD_LAYOUT_P
47483 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
47485 #if TARGET_MACHO
47486 #undef TARGET_BINDS_LOCAL_P
47487 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
47488 #endif
47489 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47490 #undef TARGET_BINDS_LOCAL_P
47491 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
47492 #endif
47494 #undef TARGET_ASM_OUTPUT_MI_THUNK
47495 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
47496 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
47497 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
47499 #undef TARGET_ASM_FILE_START
47500 #define TARGET_ASM_FILE_START x86_file_start
47502 #undef TARGET_OPTION_OVERRIDE
47503 #define TARGET_OPTION_OVERRIDE ix86_option_override
47505 #undef TARGET_REGISTER_MOVE_COST
47506 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47507 #undef TARGET_MEMORY_MOVE_COST
47508 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47509 #undef TARGET_RTX_COSTS
47510 #define TARGET_RTX_COSTS ix86_rtx_costs
47511 #undef TARGET_ADDRESS_COST
47512 #define TARGET_ADDRESS_COST ix86_address_cost
47514 #undef TARGET_FIXED_CONDITION_CODE_REGS
47515 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47516 #undef TARGET_CC_MODES_COMPATIBLE
47517 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47519 #undef TARGET_MACHINE_DEPENDENT_REORG
47520 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47522 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47523 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47525 #undef TARGET_BUILD_BUILTIN_VA_LIST
47526 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47528 #undef TARGET_FOLD_BUILTIN
47529 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47531 #undef TARGET_COMPARE_VERSION_PRIORITY
47532 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47534 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47535 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47536 ix86_generate_version_dispatcher_body
47538 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47539 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47540 ix86_get_function_versions_dispatcher
47542 #undef TARGET_ENUM_VA_LIST_P
47543 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47545 #undef TARGET_FN_ABI_VA_LIST
47546 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47548 #undef TARGET_CANONICAL_VA_LIST_TYPE
47549 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47551 #undef TARGET_EXPAND_BUILTIN_VA_START
47552 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47554 #undef TARGET_MD_ASM_CLOBBERS
47555 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47557 #undef TARGET_PROMOTE_PROTOTYPES
47558 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47559 #undef TARGET_SETUP_INCOMING_VARARGS
47560 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47561 #undef TARGET_MUST_PASS_IN_STACK
47562 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47563 #undef TARGET_FUNCTION_ARG_ADVANCE
47564 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47565 #undef TARGET_FUNCTION_ARG
47566 #define TARGET_FUNCTION_ARG ix86_function_arg
47567 #undef TARGET_FUNCTION_ARG_BOUNDARY
47568 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47569 #undef TARGET_PASS_BY_REFERENCE
47570 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47571 #undef TARGET_INTERNAL_ARG_POINTER
47572 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47573 #undef TARGET_UPDATE_STACK_BOUNDARY
47574 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47575 #undef TARGET_GET_DRAP_RTX
47576 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47577 #undef TARGET_STRICT_ARGUMENT_NAMING
47578 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47579 #undef TARGET_STATIC_CHAIN
47580 #define TARGET_STATIC_CHAIN ix86_static_chain
47581 #undef TARGET_TRAMPOLINE_INIT
47582 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47583 #undef TARGET_RETURN_POPS_ARGS
47584 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47586 #undef TARGET_LEGITIMATE_COMBINED_INSN
47587 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47589 #undef TARGET_ASAN_SHADOW_OFFSET
47590 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47592 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47593 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47595 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47596 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47598 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47599 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47601 #undef TARGET_C_MODE_FOR_SUFFIX
47602 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47604 #ifdef HAVE_AS_TLS
47605 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47606 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47607 #endif
47609 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47610 #undef TARGET_INSERT_ATTRIBUTES
47611 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47612 #endif
47614 #undef TARGET_MANGLE_TYPE
47615 #define TARGET_MANGLE_TYPE ix86_mangle_type
47617 #if !TARGET_MACHO
47618 #undef TARGET_STACK_PROTECT_FAIL
47619 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47620 #endif
47622 #undef TARGET_FUNCTION_VALUE
47623 #define TARGET_FUNCTION_VALUE ix86_function_value
47625 #undef TARGET_FUNCTION_VALUE_REGNO_P
47626 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47628 #undef TARGET_PROMOTE_FUNCTION_MODE
47629 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47631 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47632 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47634 #undef TARGET_INSTANTIATE_DECLS
47635 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47637 #undef TARGET_SECONDARY_RELOAD
47638 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47640 #undef TARGET_CLASS_MAX_NREGS
47641 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47643 #undef TARGET_PREFERRED_RELOAD_CLASS
47644 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47645 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47646 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47647 #undef TARGET_CLASS_LIKELY_SPILLED_P
47648 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47650 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47651 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47652 ix86_builtin_vectorization_cost
47653 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47654 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47655 ix86_vectorize_vec_perm_const_ok
47656 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47657 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47658 ix86_preferred_simd_mode
47659 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47660 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47661 ix86_autovectorize_vector_sizes
47662 #undef TARGET_VECTORIZE_INIT_COST
47663 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47664 #undef TARGET_VECTORIZE_ADD_STMT_COST
47665 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47666 #undef TARGET_VECTORIZE_FINISH_COST
47667 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47668 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47669 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47671 #undef TARGET_SET_CURRENT_FUNCTION
47672 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47674 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47675 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47677 #undef TARGET_OPTION_SAVE
47678 #define TARGET_OPTION_SAVE ix86_function_specific_save
47680 #undef TARGET_OPTION_RESTORE
47681 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47683 #undef TARGET_OPTION_PRINT
47684 #define TARGET_OPTION_PRINT ix86_function_specific_print
47686 #undef TARGET_OPTION_FUNCTION_VERSIONS
47687 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47689 #undef TARGET_CAN_INLINE_P
47690 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47692 #undef TARGET_EXPAND_TO_RTL_HOOK
47693 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47695 #undef TARGET_LEGITIMATE_ADDRESS_P
47696 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47698 #undef TARGET_LRA_P
47699 #define TARGET_LRA_P hook_bool_void_true
47701 #undef TARGET_REGISTER_PRIORITY
47702 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47704 #undef TARGET_REGISTER_USAGE_LEVELING_P
47705 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47707 #undef TARGET_LEGITIMATE_CONSTANT_P
47708 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47710 #undef TARGET_FRAME_POINTER_REQUIRED
47711 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47713 #undef TARGET_CAN_OMIT_LEAF_FRAME_POINTER
47714 #define TARGET_CAN_OMIT_LEAF_FRAME_POINTER ix86_can_omit_leaf_frame_pointer
47716 #undef TARGET_CAN_ELIMINATE
47717 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47719 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47720 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47722 #undef TARGET_ASM_CODE_END
47723 #define TARGET_ASM_CODE_END ix86_code_end
47725 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47726 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47728 #if TARGET_MACHO
47729 #undef TARGET_INIT_LIBFUNCS
47730 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47731 #endif
47733 #undef TARGET_LOOP_UNROLL_ADJUST
47734 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47736 #undef TARGET_SPILL_CLASS
47737 #define TARGET_SPILL_CLASS ix86_spill_class
47739 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47740 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47741 ix86_simd_clone_compute_vecsize_and_simdlen
47743 #undef TARGET_SIMD_CLONE_ADJUST
47744 #define TARGET_SIMD_CLONE_ADJUST \
47745 ix86_simd_clone_adjust
47747 #undef TARGET_SIMD_CLONE_USABLE
47748 #define TARGET_SIMD_CLONE_USABLE \
47749 ix86_simd_clone_usable
47751 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47752 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47753 ix86_float_exceptions_rounding_supported_p
47755 #undef TARGET_STRICT_ALIGN
47756 #define TARGET_STRICT_ALIGN true
47758 \f