| blob | 3fb2ac854b0ca89a633a5a8feef2a0e396a30424 |
1 ;; Machine Description for Renesas RX processors
2 ;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20 \f
22 ;; This code iterator is used for sign- and zero- extensions.
23 (define_mode_iterator small_int_modes [(HI "") (QI "")])
25 ;; This code iterator is used for max and min operations.
26 (define_mode_iterator int_modes [(SI "") (HI "") (QI "")])
28 ;; We do not handle DFmode here because it is either
29 ;; the same as SFmode, or if -m64bit-doubles is active
30 ;; then all operations on doubles have to be handled by
31 ;; library functions.
32 (define_mode_iterator register_modes
33 [(SF "") (SI "") (HI "") (QI "")])
35 (define_constants
36 [
37 (SP_REG 0)
38 (CC_REG 16)
40 (UNSPEC_LOW_REG 0)
41 (UNSPEC_HIGH_REG 1)
43 (UNSPEC_RTE 10)
44 (UNSPEC_RTFI 11)
45 (UNSPEC_NAKED 12)
46 (UNSPEC_CONST 13)
48 (UNSPEC_MOVSTR 20)
49 (UNSPEC_MOVMEM 21)
50 (UNSPEC_SETMEM 22)
51 (UNSPEC_STRLEN 23)
52 (UNSPEC_CMPSTRN 24)
54 (UNSPEC_BUILTIN_BRK 30)
55 (UNSPEC_BUILTIN_CLRPSW 31)
56 (UNSPEC_BUILTIN_INT 32)
57 (UNSPEC_BUILTIN_MACHI 33)
58 (UNSPEC_BUILTIN_MACLO 34)
59 (UNSPEC_BUILTIN_MULHI 35)
60 (UNSPEC_BUILTIN_MULLO 36)
61 (UNSPEC_BUILTIN_MVFACHI 37)
62 (UNSPEC_BUILTIN_MVFACMI 38)
63 (UNSPEC_BUILTIN_MVFC 39)
64 (UNSPEC_BUILTIN_MVFCP 40)
65 (UNSPEC_BUILTIN_MVTACHI 41)
66 (UNSPEC_BUILTIN_MVTACLO 42)
67 (UNSPEC_BUILTIN_MVTC 43)
68 (UNSPEC_BUILTIN_MVTIPL 44)
69 (UNSPEC_BUILTIN_RACW 45)
70 (UNSPEC_BUILTIN_REVW 46)
71 (UNSPEC_BUILTIN_RMPA 47)
72 (UNSPEC_BUILTIN_ROUND 48)
73 (UNSPEC_BUILTIN_SAT 49)
74 (UNSPEC_BUILTIN_SETPSW 50)
75 (UNSPEC_BUILTIN_WAIT 51)
77 (UNSPEC_PID_ADDR 52)
79 (CTRLREG_PSW 0)
80 (CTRLREG_USP 2)
81 (CTRLREG_FPSW 3)
82 (CTRLREG_CPEN 4)
83 (CTRLREG_BPSW 8)
84 (CTRLREG_BPC 9)
85 (CTRLREG_ISP 10)
86 (CTRLREG_FINTV 11)
87 (CTRLREG_INTB 12)
88 ]
89 )
91 (define_attr "length" "" (const_int 8))
93 (include "predicates.md")
94 (include "constraints.md")
96 ;; Pipeline description.
98 ;; The RX only has a single pipeline. It has five stages (fetch,
99 ;; decode, execute, memory access, writeback) each of which normally
100 ;; takes a single CPU clock cycle.
102 ;; The timings attribute consists of two numbers, the first is the
103 ;; throughput, which is the number of cycles the instruction takes
104 ;; to execute and generate a result. The second is the latency
105 ;; which is the effective number of cycles the instruction takes to
106 ;; execute if its result is used by the following instruction. The
107 ;; latency is always greater than or equal to the throughput.
108 ;; These values were taken from tables 2.13 and 2.14 in section 2.8
109 ;; of the RX610 Group Hardware Manual v0.11
111 ;; Note - it would be nice to use strings rather than integers for
112 ;; the possible values of this attribute, so that we can have the
113 ;; gcc build mechanism check for values that are not supported by
114 ;; the reservations below. But this will not work because the code
115 ;; in rx_adjust_sched_cost() needs integers not strings.
117 (define_attr "timings" "" (const_int 11))
119 (define_automaton "pipelining")
120 (define_cpu_unit "throughput" "pipelining")
122 (define_insn_reservation "throughput__1_latency__1" 1
123 (eq_attr "timings" "11") "throughput")
124 (define_insn_reservation "throughput__1_latency__2" 2
125 (eq_attr "timings" "12") "throughput,nothing")
126 (define_insn_reservation "throughput__2_latency__2" 1
127 (eq_attr "timings" "22") "throughput*2")
128 (define_insn_reservation "throughput__3_latency__3" 1
129 (eq_attr "timings" "33") "throughput*3")
130 (define_insn_reservation "throughput__3_latency__4" 2
131 (eq_attr "timings" "34") "throughput*3,nothing")
132 (define_insn_reservation "throughput__4_latency__4" 1
133 (eq_attr "timings" "44") "throughput*4")
134 (define_insn_reservation "throughput__4_latency__5" 2
135 (eq_attr "timings" "45") "throughput*4,nothing")
136 (define_insn_reservation "throughput__5_latency__5" 1
137 (eq_attr "timings" "55") "throughput*5")
138 (define_insn_reservation "throughput__5_latency__6" 2
139 (eq_attr "timings" "56") "throughput*5,nothing")
140 (define_insn_reservation "throughput__6_latency__6" 1
141 (eq_attr "timings" "66") "throughput*6")
142 (define_insn_reservation "throughput_10_latency_10" 1
143 (eq_attr "timings" "1010") "throughput*10")
144 (define_insn_reservation "throughput_11_latency_11" 1
145 (eq_attr "timings" "1111") "throughput*11")
146 (define_insn_reservation "throughput_16_latency_16" 1
147 (eq_attr "timings" "1616") "throughput*16")
148 (define_insn_reservation "throughput_18_latency_18" 1
149 (eq_attr "timings" "1818") "throughput*18")
151 ;; ----------------------------------------------------------------------------
153 ;; Comparisons
155 ;; Note - we do not specify the two instructions necessary to perform
156 ;; a compare-and-branch in the cbranchsi4 pattern because that would
157 ;; allow the comparison to be moved away from the jump before the reload
158 ;; pass has completed. That would be problematical because reload can
159 ;; generate ADDSI3 instructions which would corrupt the PSW flags.
161 (define_expand "cbranchsi4"
162 [(set (pc)
163 (if_then_else
164 (match_operator 0 "comparison_operator"
165 [(match_operand:SI 1 "register_operand")
166 (match_operand:SI 2 "rx_source_operand")])
167 (label_ref (match_operand 3 ""))
168 (pc)))]
169 ""
170 )
172 (define_insn_and_split "*cbranchsi4"
173 [(set (pc)
174 (if_then_else
175 (match_operator 3 "comparison_operator"
176 [(match_operand:SI 0 "register_operand" "r")
177 (match_operand:SI 1 "rx_source_operand" "riQ")])
178 (match_operand 2 "label_ref_operand" "")
179 (pc)))]
180 ""
181 "#"
182 "reload_completed"
183 [(const_int 0)]
184 {
185 rx_split_cbranch (CCmode, GET_CODE (operands[3]),
186 operands[0], operands[1], operands[2]);
187 DONE;
188 })
190 (define_insn "*cmpsi"
191 [(set (reg:CC CC_REG)
192 (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r")
193 (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
194 "reload_completed"
195 "cmp\t%Q1, %0"
196 [(set_attr "timings" "11,11,11,11,11,11,33")
197 (set_attr "length" "2,2,3,4,5,6,5")]
198 )
200 ;; Canonical method for representing TST.
201 (define_insn_and_split "*cbranchsi4_tst"
202 [(set (pc)
203 (if_then_else
204 (match_operator 3 "rx_zs_comparison_operator"
205 [(and:SI (match_operand:SI 0 "register_operand" "r")
206 (match_operand:SI 1 "rx_source_operand" "riQ"))
207 (const_int 0)])
208 (match_operand 2 "label_ref_operand" "")
209 (pc)))]
210 ""
211 "#"
212 "reload_completed"
213 [(const_int 0)]
214 {
215 rx_split_cbranch (CC_ZSmode, GET_CODE (operands[3]),
216 XEXP (operands[3], 0), XEXP (operands[3], 1),
217 operands[2]);
218 DONE;
219 })
221 ;; Various other ways that GCC codes "var & const"
222 (define_insn_and_split "*cbranchsi4_tst_ext"
223 [(set (pc)
224 (if_then_else
225 (match_operator 4 "rx_z_comparison_operator"
226 [(zero_extract:SI
227 (match_operand:SI 0 "register_operand" "r")
228 (match_operand:SI 1 "rx_constshift_operand" "")
229 (match_operand:SI 2 "rx_constshift_operand" ""))
230 (const_int 0)])
231 (match_operand 3 "label_ref_operand" "")
232 (pc)))]
233 ""
234 "#"
235 "reload_completed"
236 [(const_int 0)]
237 {
238 HOST_WIDE_INT mask;
239 rtx x;
241 mask = 1;
242 mask <<= INTVAL (operands[1]);
243 mask -= 1;
244 mask <<= INTVAL (operands[2]);
245 x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
247 rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
248 x, const0_rtx, operands[3]);
249 DONE;
250 })
252 (define_insn "*tstsi"
253 [(set (reg:CC_ZS CC_REG)
254 (compare:CC_ZS
255 (and:SI (match_operand:SI 0 "register_operand" "r,r,r")
256 (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
257 (const_int 0)))]
258 "reload_completed"
259 "tst\t%Q1, %0"
260 [(set_attr "timings" "11,11,33")
261 (set_attr "length" "3,7,6")]
262 )
264 (define_expand "cbranchsf4"
265 [(set (pc)
266 (if_then_else
267 (match_operator 0 "rx_fp_comparison_operator"
268 [(match_operand:SF 1 "register_operand")
269 (match_operand:SF 2 "rx_source_operand")])
270 (label_ref (match_operand 3 ""))
271 (pc)))]
272 "ALLOW_RX_FPU_INSNS"
273 )
275 (define_insn_and_split "*cbranchsf4"
276 [(set (pc)
277 (if_then_else
278 (match_operator 3 "rx_fp_comparison_operator"
279 [(match_operand:SF 0 "register_operand" "r")
280 (match_operand:SF 1 "rx_source_operand" "rFQ")])
281 (match_operand 2 "label_ref_operand" "")
282 (pc)))]
283 "ALLOW_RX_FPU_INSNS"
284 "#"
285 "&& reload_completed"
286 [(const_int 0)]
287 {
288 rx_split_cbranch (CC_Fmode, GET_CODE (operands[3]),
289 operands[0], operands[1], operands[2]);
290 DONE;
291 })
293 (define_insn "*cmpsf"
294 [(set (reg:CC_F CC_REG)
295 (compare:CC_F
296 (match_operand:SF 0 "register_operand" "r,r,r")
297 (match_operand:SF 1 "rx_source_operand" "r,F,Q")))]
298 "ALLOW_RX_FPU_INSNS && reload_completed"
299 "fcmp\t%1, %0"
300 [(set_attr "timings" "11,11,33")
301 (set_attr "length" "3,7,5")]
302 )
304 ;; Flow Control Instructions:
306 (define_insn "*conditional_branch"
307 [(set (pc)
308 (if_then_else
309 (match_operator 1 "comparison_operator"
310 [(reg CC_REG) (const_int 0)])
311 (label_ref (match_operand 0 "" ""))
312 (pc)))]
313 "reload_completed"
314 "b%B1\t%0"
315 [(set_attr "length" "8") ;; This length is wrong, but it is
316 ;; too hard to compute statically.
317 (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
318 )
320 ;; ----------------------------------------------------------------------------
322 (define_insn "jump"
323 [(set (pc)
324 (label_ref (match_operand 0 "" "")))]
325 ""
326 "bra\t%0"
327 [(set_attr "length" "4")
328 (set_attr "timings" "33")]
329 )
331 (define_insn "indirect_jump"
332 [(set (pc)
333 (match_operand:SI 0 "register_operand" "r"))]
334 ""
335 "jmp\t%0"
336 [(set_attr "length" "2")
337 (set_attr "timings" "33")]
338 )
340 (define_insn "tablejump"
341 [(set (pc)
342 (match_operand:SI 0 "register_operand" "r"))
343 (use (label_ref (match_operand 1 "" "")))]
344 ""
345 { return TARGET_PID ? (TARGET_AS100_SYNTAX ? "\n?:\tbra\t%0"
346 : "\n1:\tbra\t%0")
347 : "\n1:jmp\t%0";
348 }
349 [(set_attr "timings" "33")
350 (set_attr "length" "2")]
351 )
353 (define_expand "return"
354 [(return)]
355 "rx_can_use_simple_return ()"
356 "rx_expand_epilogue (false); DONE;"
357 )
359 (define_insn "simple_return"
360 [(simple_return)]
361 ""
362 "rts"
363 [(set_attr "length" "1")
364 (set_attr "timings" "55")]
365 )
367 ;; Unspec used so that the constant will not be invalid
368 ;; if -mmax-constant-size has been specified.
369 (define_insn "deallocate_and_return"
370 [(set (reg:SI SP_REG)
371 (plus:SI (reg:SI SP_REG)
372 (const:SI (unspec:SI [(match_operand 0 "const_int_operand" "n")] UNSPEC_CONST))))
373 (return)]
374 ""
375 "rtsd\t%0"
376 [(set_attr "length" "2")
377 (set_attr "timings" "55")]
378 )
380 (define_insn "pop_and_return"
381 [(match_parallel 1 "rx_rtsd_vector"
382 [(set (reg:SI SP_REG)
383 (plus:SI (reg:SI SP_REG)
384 (match_operand:SI 0 "const_int_operand" "n")))])
385 (return)]
386 "reload_completed"
387 {
388 rx_emit_stack_popm (operands, false);
389 return "";
390 }
391 [(set_attr "length" "3")
392 (set_attr "timings" "56")]
393 )
395 (define_insn "fast_interrupt_return"
396 [(unspec_volatile [(return)] UNSPEC_RTFI) ]
397 ""
398 "rtfi"
399 [(set_attr "length" "2")
400 (set_attr "timings" "33")]
401 )
403 (define_insn "exception_return"
404 [(unspec_volatile [(return)] UNSPEC_RTE) ]
405 ""
406 "rte"
407 [(set_attr "length" "2")
408 (set_attr "timings" "66")]
409 )
411 (define_insn "naked_return"
412 [(unspec_volatile [(return)] UNSPEC_NAKED) ]
413 ""
414 "; Naked function: epilogue provided by programmer."
415 )
418 ;; Note - the following set of patterns do not use the "memory_operand"
419 ;; predicate or an "m" constraint because we do not allow symbol_refs
420 ;; or label_refs as legitimate memory addresses. This matches the
421 ;; behavior of most of the RX instructions. Only the call/branch
422 ;; instructions are allowed to refer to symbols/labels directly.
423 ;; The call operands are in QImode because that is the value of
424 ;; FUNCTION_MODE
426 (define_expand "call"
427 [(call (match_operand:QI 0 "general_operand")
428 (match_operand:SI 1 "general_operand"))]
429 ""
430 {
431 rtx dest = XEXP (operands[0], 0);
433 if (! rx_call_operand (dest, Pmode))
434 dest = force_reg (Pmode, dest);
435 emit_call_insn (gen_call_internal (dest));
436 DONE;
437 }
438 )
440 (define_insn "call_internal"
441 [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,CALL_OP_SYMBOL_REF"))
442 (const_int 0))
443 (clobber (reg:CC CC_REG))]
444 ""
445 "@
446 jsr\t%0
447 bsr\t%A0"
448 [(set_attr "length" "2,4")
449 (set_attr "timings" "33")]
450 )
452 (define_expand "call_value"
453 [(set (match_operand 0 "register_operand")
454 (call (match_operand:QI 1 "general_operand")
455 (match_operand:SI 2 "general_operand")))]
456 ""
457 {
458 rtx dest = XEXP (operands[1], 0);
460 if (! rx_call_operand (dest, Pmode))
461 dest = force_reg (Pmode, dest);
462 emit_call_insn (gen_call_value_internal (operands[0], dest));
463 DONE;
464 }
465 )
467 (define_insn "call_value_internal"
468 [(set (match_operand 0 "register_operand" "=r,r")
469 (call (mem:QI (match_operand:SI 1 "rx_call_operand" "r,CALL_OP_SYMBOL_REF"))
470 (const_int 0)))
471 (clobber (reg:CC CC_REG))]
472 ""
473 "@
474 jsr\t%1
475 bsr\t%A1"
476 [(set_attr "length" "2,4")
477 (set_attr "timings" "33")]
478 )
480 ;; Note - we do not allow indirect sibcalls (with the address
481 ;; held in a register) because we cannot guarantee that the register
482 ;; chosen will be a call-used one. If it is a call-saved register,
483 ;; then the epilogue code will corrupt it by popping the saved value
484 ;; off of the stack.
485 (define_expand "sibcall"
486 [(parallel
487 [(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand"))
488 (match_operand:SI 1 "general_operand"))
489 (return)])]
490 ""
491 {
492 if (MEM_P (operands[0]))
493 operands[0] = XEXP (operands[0], 0);
494 emit_call_insn (gen_sibcall_internal (operands[0]));
495 DONE;
496 }
497 )
499 (define_insn "sibcall_internal"
500 [(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand" "Symbol"))
501 (const_int 0))
502 (return)]
503 ""
504 "bra\t%A0"
505 [(set_attr "length" "4")
506 (set_attr "timings" "33")]
507 )
509 (define_expand "sibcall_value"
510 [(parallel
511 [(set (match_operand 0 "register_operand")
512 (call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand"))
513 (match_operand:SI 2 "general_operand")))
514 (return)])]
515 ""
516 {
517 if (MEM_P (operands[1]))
518 operands[1] = XEXP (operands[1], 0);
519 emit_call_insn (gen_sibcall_value_internal (operands[0], operands[1]));
520 DONE;
521 }
522 )
524 (define_insn "sibcall_value_internal"
525 [(set (match_operand 0 "register_operand" "=r")
526 (call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand" "Symbol"))
527 (const_int 0)))
528 (return)]
529 ""
530 "bra\t%A1"
531 [(set_attr "length" "4")
532 (set_attr "timings" "33")]
533 )
535 ;; Function Prologue/Epilogue Instructions
537 (define_expand "prologue"
538 [(const_int 0)]
539 ""
540 "rx_expand_prologue (); DONE;"
541 )
543 (define_expand "epilogue"
544 [(return)]
545 ""
546 "rx_expand_epilogue (false); DONE;"
547 )
549 (define_expand "sibcall_epilogue"
550 [(return)]
551 ""
552 "rx_expand_epilogue (true); DONE;"
553 )
555 ;; Move Instructions
557 ;; Note - we do not allow memory to memory moves, even though the ISA
558 ;; supports them. The reason is that the conditions on such moves are
559 ;; too restrictive, specifically the source addressing mode is limited
560 ;; by the destination addressing mode and vice versa. (For example it
561 ;; is not possible to use indexed register indirect addressing for one
562 ;; of the operands if the other operand is anything other than a register,
563 ;; but it is possible to use register relative addressing when the other
564 ;; operand also uses register relative or register indirect addressing).
565 ;;
566 ;; GCC does not support computing legitimate addresses based on the
567 ;; nature of other operands involved in the instruction, and reload is
568 ;; not smart enough to cope with a whole variety of different memory
569 ;; addressing constraints, so it is simpler and safer to just refuse
570 ;; to support memory to memory moves.
572 (define_expand "mov<register_modes:mode>"
573 [(set (match_operand:register_modes 0 "general_operand")
574 (match_operand:register_modes 1 "general_operand"))]
575 ""
576 {
577 if (MEM_P (operands[0]) && MEM_P (operands[1]))
578 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
579 operands[0] = rx_maybe_pidify_operand (operands[0], 0);
580 operands[1] = rx_maybe_pidify_operand (operands[1], 0);
581 if (GET_CODE (operands[0]) != REG
582 && GET_CODE (operands[1]) == PLUS)
583 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
584 if (GET_CODE (operands[1]) == PLUS && GET_MODE (operands[1]) == SImode)
585 {
586 emit_insn (gen_addsi3 (operands[0], XEXP (operands[1], 0), XEXP (operands[1], 1)));
587 DONE;
588 }
589 if (CONST_INT_P (operand1)
590 && ! rx_is_legitimate_constant (<register_modes:MODE>mode, operand1))
591 FAIL;
592 }
593 )
595 (define_insn "*mov<register_modes:mode>_internal"
596 [(set (match_operand:register_modes
597 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,Q,Q,Q,Q,r")
598 (match_operand:register_modes
599 1 "general_operand" "Int08,Sint16,Sint24,i,r,m,r,Int08,Sint16,Sint24,i,RpdaRpid"))]
600 ""
601 { return rx_gen_move_template (operands, false); }
602 [(set_attr "length" "3,4,5,6,2,4,6,5,6,7,8,8")
603 (set_attr "timings" "11,11,11,11,11,12,11,11,11,11,11,11")]
604 )
606 (define_insn "extend<small_int_modes:mode>si2"
607 [(set (match_operand:SI 0 "register_operand" "=r,r")
608 (sign_extend:SI (match_operand:small_int_modes
609 1 "nonimmediate_operand" "r,m")))]
610 ""
611 { return rx_gen_move_template (operands, false); }
612 [(set_attr "length" "2,6")
613 (set_attr "timings" "11,12")]
614 )
616 (define_insn "zero_extend<small_int_modes:mode>si2"
617 [(set (match_operand:SI 0 "register_operand" "=r,r")
618 (zero_extend:SI (match_operand:small_int_modes
619 1 "nonimmediate_operand" "r,m")))]
620 ""
621 { return rx_gen_move_template (operands, true); }
622 [(set_attr "length" "2,4")
623 (set_attr "timings" "11,12")]
624 )
626 (define_insn "stack_push"
627 [(set (reg:SI SP_REG)
628 (minus:SI (reg:SI SP_REG)
629 (const_int 4)))
630 (set (mem:SI (minus:SI (reg:SI SP_REG) (const_int 4)))
631 (match_operand:SI 0 "register_operand" "r"))]
632 ""
633 "push.l\t%0"
634 [(set_attr "length" "2")]
635 )
637 (define_insn "stack_pushm"
638 [(match_parallel 1 "rx_store_multiple_vector"
639 [(set (reg:SI SP_REG)
640 (minus:SI (reg:SI SP_REG)
641 (match_operand:SI 0 "const_int_operand" "n")))])]
642 "reload_completed"
643 {
644 rx_emit_stack_pushm (operands);
645 return "";
646 }
647 [(set_attr "length" "2")
648 (set_attr "timings" "44")] ;; The timing is a guesstimate average timing.
649 )
651 (define_insn "stack_pop"
652 [(set (match_operand:SI 0 "register_operand" "=r")
653 (mem:SI (reg:SI SP_REG)))
654 (set (reg:SI SP_REG)
655 (plus:SI (reg:SI SP_REG)
656 (const_int 4)))]
657 ""
658 "pop\t%0"
659 [(set_attr "length" "2")
660 (set_attr "timings" "12")]
661 )
663 (define_insn "stack_popm"
664 [(match_parallel 1 "rx_load_multiple_vector"
665 [(set (reg:SI SP_REG)
666 (plus:SI (reg:SI SP_REG)
667 (match_operand:SI 0 "const_int_operand" "n")))])]
668 "reload_completed"
669 {
670 rx_emit_stack_popm (operands, true);
671 return "";
672 }
673 [(set_attr "length" "2")
674 (set_attr "timings" "45")] ;; The timing is a guesstimate average timing.
675 )
677 (define_insn_and_split "cstoresi4"
678 [(set (match_operand:SI 0 "register_operand" "=r")
679 (match_operator:SI 1 "comparison_operator"
680 [(match_operand:SI 2 "register_operand" "r")
681 (match_operand:SI 3 "rx_source_operand" "riQ")]))
682 (clobber (reg:CC CC_REG))]
683 ""
684 "#"
685 "reload_completed"
686 [(const_int 0)]
687 {
688 rtx flags, x;
690 flags = gen_rtx_REG (CCmode, CC_REG);
691 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
692 x = gen_rtx_SET (flags, x);
693 emit_insn (x);
695 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
696 x = gen_rtx_SET (operands[0], x);
697 emit_insn (x);
698 DONE;
699 })
701 (define_insn "*sccc"
702 [(set (match_operand:SI 0 "register_operand" "=r")
703 (match_operator:SI 1 "comparison_operator"
704 [(reg CC_REG) (const_int 0)]))]
705 "reload_completed"
706 "sc%B1.L\t%0"
707 [(set_attr "length" "3")]
708 )
710 (define_insn_and_split "cstoresf4"
711 [(set (match_operand:SI 0 "register_operand" "=r")
712 (match_operator:SI 1 "rx_fp_comparison_operator"
713 [(match_operand:SF 2 "register_operand" "r")
714 (match_operand:SF 3 "rx_source_operand" "rFQ")]))]
715 "ALLOW_RX_FPU_INSNS"
716 "#"
717 "reload_completed"
718 [(const_int 0)]
719 {
720 rtx flags, x;
722 flags = gen_rtx_REG (CC_Fmode, CC_REG);
723 x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]);
724 x = gen_rtx_SET (flags, x);
725 emit_insn (x);
727 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
728 x = gen_rtx_SET (operands[0], x);
729 emit_insn (x);
730 DONE;
731 })
733 (define_expand "movsicc"
734 [(parallel
735 [(set (match_operand:SI 0 "register_operand")
736 (if_then_else:SI (match_operand 1 "comparison_operator")
737 (match_operand:SI 2 "nonmemory_operand")
738 (match_operand:SI 3 "nonmemory_operand")))
739 (clobber (reg:CC CC_REG))])]
740 ""
741 {
742 /* Make sure that we have an integer comparison... */
743 if (GET_MODE (XEXP (operands[1], 0)) != CCmode
744 && GET_MODE (XEXP (operands[1], 0)) != SImode)
745 FAIL;
747 /* One operand must be a constant or a register, the other must be a register. */
748 if ( ! CONSTANT_P (operands[2])
749 && ! CONSTANT_P (operands[3])
750 && ! (REG_P (operands[2]) && REG_P (operands[3])))
751 FAIL;
752 })
754 (define_insn_and_split "*movsicc"
755 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
756 (if_then_else:SI
757 (match_operator 5 "comparison_operator"
758 [(match_operand:SI 3 "register_operand" "r,r,r")
759 (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ")])
760 (match_operand:SI 1 "nonmemory_operand" "i,ri,r")
761 (match_operand:SI 2 "nonmemory_operand" "ri,i,r")))
762 (clobber (reg:CC CC_REG))]
763 "(CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))
764 || (REG_P (operands[1]) && REG_P (operands[2]))"
765 "#"
766 "&& reload_completed"
767 [(const_int 0)]
768 {
769 rtx x, flags, op0, op1, op2;
770 enum rtx_code cmp_code;
772 flags = gen_rtx_REG (CCmode, CC_REG);
773 x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]);
774 emit_insn (gen_rtx_SET (flags, x));
776 cmp_code = GET_CODE (operands[5]);
777 op0 = operands[0];
778 op1 = operands[1];
779 op2 = operands[2];
781 /* If OP2 is the constant, reverse the sense of the move.
782 Likewise if both operands are registers but OP1 == OP0. */
783 if ((! CONSTANT_P (operands[1]) && CONSTANT_P (operands[2]))
784 || (REG_P (operands[1]) && REG_P (operands[2])
785 && rtx_equal_p (op0, op1)))
786 {
787 x = op1, op1 = op2, op2 = x;
788 cmp_code = reverse_condition (cmp_code);
789 }
791 /* If OP2 does not match the output, copy it into place. We have allowed
792 these alternatives so that the destination can legitimately be one of
793 the comparison operands without increasing register pressure. */
794 if (! rtx_equal_p (op0, op2))
795 emit_move_insn (op0, op2);
797 x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
798 x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0);
799 emit_insn (gen_rtx_SET (op0, x));
800 DONE;
801 })
803 (define_insn "*stcc"
804 [(set (match_operand:SI 0 "register_operand" "+r,r,r,r")
805 (if_then_else:SI
806 (match_operator 2 "rx_z_comparison_operator"
807 [(reg CC_REG) (const_int 0)])
808 (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
809 (match_dup 0)))]
810 "reload_completed
811 && ((GET_CODE (operands[2]) == EQ) || (GET_CODE (operands[2]) == NE))"
812 {
813 if (GET_CODE (operands[2]) == EQ)
814 return "stz\t%1, %0";
815 else
816 return "stnz\t%1, %0";
817 }
818 [(set_attr "length" "4,5,6,7")]
819 )
821 (define_insn "*stcc_reg"
822 [(set (match_operand:SI 0 "register_operand" "+r,r,r,r,r,r")
823 (if_then_else:SI
824 (match_operator 2 "comparison_operator"
825 [(reg CC_REG) (const_int 0)])
826 (match_operand:SI 1 "nonmemory_operand"
827 "r,Uint04,Sint08,Sint16,Sint24,i")
828 (match_dup 0)))]
829 "reload_completed"
830 {
831 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
832 return "b%B2 1f\n\tmov %1, %0\n1:";
833 }
834 [(set_attr "length" "3,3,4,5,6,7")]
835 )
837 ;; Arithmetic Instructions
839 (define_insn "abssi2"
840 [(set (match_operand:SI 0 "register_operand" "=r,r")
841 (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
842 (clobber (reg:CC CC_REG))]
843 ""
844 "@
845 abs\t%0
846 abs\t%1, %0"
847 [(set_attr "length" "2,3")]
848 )
850 (define_insn "*abssi2_flags"
851 [(set (reg CC_REG)
852 (compare (abs:SI (match_operand:SI 1 "register_operand" "0,r"))
853 (const_int 0)))
854 (set (match_operand:SI 0 "register_operand" "=r,r")
855 (abs:SI (match_dup 1)))]
856 ;; Note - although the ABS instruction does set the O bit in the processor
857 ;; status word, it does not do so in a way that is comparable with the CMP
858 ;; instruction. Hence we use CC_ZSmode rather than CC_ZSOmode.
859 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
860 "@
861 abs\t%0
862 abs\t%1, %0"
863 [(set_attr "length" "2,3")]
864 )
866 (define_expand "addsi3"
867 [(parallel [(set (match_operand:SI 0 "register_operand" "")
868 (plus:SI (match_operand:SI 1 "register_operand" "")
869 (match_operand:SI 2 "rx_source_operand" "")))
870 (clobber (reg:CC CC_REG))])]
871 ""
872 "
873 operands[0] = rx_maybe_pidify_operand (operands[0], 1);
874 operands[1] = rx_maybe_pidify_operand (operands[1], 1);
875 operands[2] = rx_maybe_pidify_operand (operands[2], 1);
876 "
877 )
879 (define_insn "addsi3_internal"
880 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
881 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
882 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
883 (clobber (reg:CC CC_REG))]
884 ""
885 "@
886 add\t%2, %0
887 add\t%2, %0
888 sub\t%N2, %0
889 add\t%2, %0
890 add\t%2, %0
891 add\t%2, %0
892 add\t%2, %0
893 add\t%1, %0
894 add\t%2, %1, %0
895 add\t%2, %1, %0
896 add\t%2, %1, %0
897 add\t%2, %1, %0
898 add\t%2, %1, %0
899 add\t%Q2, %0"
900 [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
901 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
902 )
904 (define_insn "*addsi3_flags"
905 [(set (reg CC_REG)
906 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
907 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))
908 (const_int 0)))
909 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
910 (plus:SI (match_dup 1) (match_dup 2)))]
911 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
912 "@
913 add\t%2, %0
914 add\t%2, %0
915 sub\t%N2, %0
916 add\t%2, %0
917 add\t%2, %0
918 add\t%2, %0
919 add\t%2, %0
920 add\t%1, %0
921 add\t%2, %1, %0
922 add\t%2, %1, %0
923 add\t%2, %1, %0
924 add\t%2, %1, %0
925 add\t%2, %1, %0
926 add\t%Q2, %0"
927 [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
928 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
929 )
931 ;; A helper to expand the above with the CC_MODE filled in.
932 (define_expand "addsi3_flags"
933 [(parallel [(set (reg:CC_ZSC CC_REG)
934 (compare:CC_ZSC
935 (plus:SI (match_operand:SI 1 "register_operand")
936 (match_operand:SI 2 "rx_source_operand"))
937 (const_int 0)))
938 (set (match_operand:SI 0 "register_operand")
939 (plus:SI (match_dup 1) (match_dup 2)))])]
940 )
942 (define_insn "adc_internal"
943 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
944 (plus:SI
945 (plus:SI
946 (ltu:SI (reg:CC CC_REG) (const_int 0))
947 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
948 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
949 (clobber (reg:CC CC_REG))]
950 "reload_completed"
951 "adc\t%2, %0"
952 [(set_attr "timings" "11,11,11,11,11,33")
953 (set_attr "length" "3,4,5,6,7,6")]
954 )
956 (define_insn "*adc_flags"
957 [(set (reg CC_REG)
958 (compare
959 (plus:SI
960 (plus:SI
961 (ltu:SI (reg:CC CC_REG) (const_int 0))
962 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
963 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))
964 (const_int 0)))
965 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
966 (plus:SI
967 (plus:SI
968 (ltu:SI (reg:CC CC_REG) (const_int 0))
969 (match_dup 1))
970 (match_dup 2)))]
971 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
972 "adc\t%2, %0"
973 [(set_attr "timings" "11,11,11,11,11,33")
974 (set_attr "length" "3,4,5,6,7,6")]
975 )
977 ;; Peepholes to match:
978 ;; (set (reg A) (reg B))
979 ;; (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
980 ;; and replace them with the addsi3_flags pattern, using an add
981 ;; of zero to copy the register and set the condition code bits.
982 (define_peephole2
983 [(set (match_operand:SI 0 "register_operand")
984 (match_operand:SI 1 "register_operand"))
985 (set (reg:CC CC_REG)
986 (compare:CC (match_dup 0)
987 (const_int 0)))]
988 ""
989 [(parallel [(set (reg:CC_ZSC CC_REG)
990 (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
991 (const_int 0)))
992 (set (match_dup 0)
993 (plus:SI (match_dup 1) (const_int 0))) ])]
994 )
996 (define_peephole2
997 [(set (match_operand:SI 0 "register_operand")
998 (match_operand:SI 1 "register_operand"))
999 (set (reg:CC CC_REG)
1000 (compare:CC (match_dup 1)
1001 (const_int 0)))]
1002 ""
1003 [(parallel [(set (reg:CC_ZSC CC_REG)
1004 (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
1005 (const_int 0)))
1006 (set (match_dup 0)
1007 (plus:SI (match_dup 1) (const_int 0)))])]
1008 )
1010 (define_expand "adddi3"
1011 [(set (match_operand:DI 0 "register_operand")
1012 (plus:DI (match_operand:DI 1 "register_operand")
1013 (match_operand:DI 2 "rx_source_operand")))]
1014 ""
1015 {
1016 rtx op0l, op0h, op1l, op1h, op2l, op2h;
1018 op0l = gen_lowpart (SImode, operands[0]);
1019 op1l = gen_lowpart (SImode, operands[1]);
1020 op2l = gen_lowpart (SImode, operands[2]);
1021 op0h = gen_highpart (SImode, operands[0]);
1022 op1h = gen_highpart (SImode, operands[1]);
1023 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1025 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
1026 DONE;
1027 })
1029 (define_insn_and_split "adddi3_internal"
1030 [(set (match_operand:SI 0 "register_operand" "=&r")
1031 (plus:SI (match_operand:SI 2 "register_operand" "r")
1032 (match_operand:SI 3 "rx_source_operand" "riQ")))
1033 (set (match_operand:SI 1 "register_operand" "=r")
1034 (plus:SI
1035 (plus:SI
1036 (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
1037 (match_operand:SI 4 "register_operand" "%1"))
1038 (match_operand:SI 5 "rx_source_operand" "riQ")))
1039 (clobber (match_scratch:SI 6 "=&r"))
1040 (clobber (reg:CC CC_REG))]
1041 ""
1042 "#"
1043 "reload_completed"
1044 [(const_int 0)]
1045 {
1046 rtx op0l = operands[0];
1047 rtx op0h = operands[1];
1048 rtx op1l = operands[2];
1049 rtx op2l = operands[3];
1050 rtx op1h = operands[4];
1051 rtx op2h = operands[5];
1052 rtx scratch = operands[6];
1053 rtx x;
1055 if (reg_overlap_mentioned_p (op0l, op1h))
1056 {
1057 emit_move_insn (scratch, op0l);
1058 op1h = scratch;
1059 if (reg_overlap_mentioned_p (op0l, op2h))
1060 op2h = scratch;
1061 }
1062 else if (reg_overlap_mentioned_p (op0l, op2h))
1063 {
1064 emit_move_insn (scratch, op0l);
1065 op2h = scratch;
1066 }
1068 if (rtx_equal_p (op0l, op1l))
1069 ;
1070 /* It is preferable that op0l == op1l... */
1071 else if (rtx_equal_p (op0l, op2l))
1072 x = op1l, op1l = op2l, op2l = x;
1073 /* ... but it is only a requirement if op2l == MEM. */
1074 else if (MEM_P (op2l))
1075 {
1076 /* Let's hope that we still have a scratch register free. */
1077 gcc_assert (op1h != scratch);
1078 emit_move_insn (scratch, op2l);
1079 op2l = scratch;
1080 }
1082 emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
1084 if (rtx_equal_p (op0h, op1h))
1085 ;
1086 else if (rtx_equal_p (op0h, op2h))
1087 x = op1h, op1h = op2h, op2h = x;
1088 else
1089 {
1090 emit_move_insn (op0h, op1h);
1091 op1h = op0h;
1092 }
1093 emit_insn (gen_adc_internal (op0h, op1h, op2h));
1094 DONE;
1095 })
1097 (define_insn "andsi3"
1098 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1099 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1100 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
1101 (clobber (reg:CC CC_REG))]
1102 ""
1103 "@
1104 and\t%2, %0
1105 and\t%2, %0
1106 and\t%2, %0
1107 and\t%2, %0
1108 and\t%2, %0
1109 and\t%2, %0
1110 and\t%1, %0
1111 and\t%2, %1, %0
1112 and\t%Q2, %0"
1113 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1114 (set_attr "length" "2,2,3,4,5,6,2,5,5")]
1115 )
1117 (define_insn "*andsi3_flags"
1118 [(set (reg CC_REG)
1119 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1120 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
1121 (const_int 0)))
1122 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1123 (and:SI (match_dup 1) (match_dup 2)))]
1124 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1125 "@
1126 and\t%2, %0
1127 and\t%2, %0
1128 and\t%2, %0
1129 and\t%2, %0
1130 and\t%2, %0
1131 and\t%2, %0
1132 and\t%1, %0
1133 and\t%2, %1, %0
1134 and\t%Q2, %0"
1135 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1136 (set_attr "length" "2,2,3,4,5,6,2,5,5")]
1137 )
1139 ;; Byte swap (single 32-bit value).
1140 (define_insn "bswapsi2"
1141 [(set (match_operand:SI 0 "register_operand" "=r")
1142 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
1143 ""
1144 "revl\t%1, %0"
1145 [(set_attr "length" "3")]
1146 )
1148 ;; Byte swap (single 16-bit value). Note - we ignore the swapping of the high 16-bits.
1149 (define_insn "bswaphi2"
1150 [(set (match_operand:HI 0 "register_operand" "=r")
1151 (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
1152 ""
1153 "revw\t%1, %0"
1154 [(set_attr "length" "3")]
1155 )
1157 (define_insn "divsi3"
1158 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1159 (div:SI (match_operand:SI 1 "register_operand" "0,0,0,0,0,0")
1160 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
1161 (clobber (reg:CC CC_REG))]
1162 ""
1163 "div\t%Q2, %0"
1164 [(set_attr "timings" "1111") ;; Strictly speaking the timing should be
1165 ;; 2222, but that is a worst case sceanario.
1166 (set_attr "length" "3,4,5,6,7,6")]
1167 )
1169 (define_insn "udivsi3"
1170 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1171 (udiv:SI (match_operand:SI 1 "register_operand" "0,0,0,0,0,0")
1172 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
1173 (clobber (reg:CC CC_REG))]
1174 ""
1175 "divu\t%Q2, %0"
1176 [(set_attr "timings" "1010") ;; Strictly speaking the timing should be
1177 ;; 2020, but that is a worst case sceanario.
1178 (set_attr "length" "3,4,5,6,7,6")]
1179 )
1181 ;; Note - these patterns are suppressed in big-endian mode because they
1182 ;; generate a little endian result. ie the most significant word of the
1183 ;; result is placed in the higher numbered register of the destination
1184 ;; register pair.
1186 (define_insn "mulsidi3"
1187 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
1188 (mult:DI (sign_extend:DI (match_operand:SI
1189 1 "register_operand" "%0,0,0,0,0,0"))
1190 (sign_extend:DI (match_operand:SI
1191 2 "rx_source_operand"
1192 "r,Sint08,Sint16,Sint24,i,Q"))))]
1193 "! TARGET_BIG_ENDIAN_DATA"
1194 "emul\t%Q2, %0"
1195 [(set_attr "length" "3,4,5,6,7,6")
1196 (set_attr "timings" "22,22,22,22,22,44")]
1197 )
1199 ;; See comment for mulsidi3.
1200 ;; Note - the zero_extends are to distinguish this pattern from the
1201 ;; mulsidi3 pattern. Immediate mode addressing is not supported
1202 ;; because gcc cannot handle the expression: (zero_extend (const_int)).
1203 (define_insn "umulsidi3"
1204 [(set (match_operand:DI 0 "register_operand" "=r,r")
1205 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,0"))
1206 (zero_extend:DI (match_operand:SI 2 "rx_compare_operand" "r,Q"))))]
1207 "! TARGET_BIG_ENDIAN_DATA"
1208 "emulu\t%Q2, %0"
1209 [(set_attr "length" "3,6")
1210 (set_attr "timings" "22,44")]
1211 )
1213 (define_insn "smaxsi3"
1214 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1215 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1216 (match_operand:SI 2 "rx_source_operand"
1217 "r,Sint08,Sint16,Sint24,i,Q")))]
1218 ""
1219 "max\t%Q2, %0"
1220 [(set_attr "length" "3,4,5,6,7,6")
1221 (set_attr "timings" "11,11,11,11,11,33")]
1222 )
1224 (define_insn "sminsi3"
1225 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1226 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1227 (match_operand:SI 2 "rx_source_operand"
1228 "r,Sint08,Sint16,Sint24,i,Q")))]
1229 ""
1230 "min\t%Q2, %0"
1231 [(set_attr "length" "3,4,5,6,7,6")
1232 (set_attr "timings" "11,11,11,11,11,33")]
1233 )
1235 (define_insn "umax<small_int_modes:mode>3_u"
1236 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1237 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1238 (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
1239 "r,Sint08,Sint16,Sint24,i,Q"))))]
1240 ""
1241 "max\t%R2, %0"
1242 [(set_attr "length" "3,4,5,6,7,6")
1243 (set_attr "timings" "11,11,11,11,11,33")]
1244 )
1246 (define_insn "umin<small_int_modes:mode>3_ur"
1247 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1248 (smin:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
1249 "r,Sint08,Sint16,Sint24,i,Q"))
1250 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))]
1251 ""
1252 "min\t%R2, %0"
1253 [(set_attr "length" "3,4,5,6,7,6")
1254 (set_attr "timings" "11,11,11,11,11,33")]
1255 )
1257 (define_insn "umax<small_int_modes:mode>3_ur"
1258 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1259 (smax:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
1260 "r,Sint08,Sint16,Sint24,i,Q"))
1261 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))]
1262 ""
1263 "max\t%R2, %0"
1264 [(set_attr "length" "3,4,5,6,7,6")
1265 (set_attr "timings" "11,11,11,11,11,33")]
1266 )
1268 (define_expand "umax<small_int_modes:mode>3"
1269 [(set (match_dup 4)
1270 (zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0")))
1271 (set (match_dup 3)
1272 (smax:SI (match_dup 4)
1273 (match_operand:small_int_modes 2 "rx_source_operand"
1274 "r,Sint08,Sint16,Sint24,i,Q")))
1275 (set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r")
1276 (match_dup 6))
1277 ]
1278 ""
1279 "operands[3] = gen_reg_rtx (SImode);
1280 operands[4] = gen_reg_rtx (SImode);
1281 operands[5] = gen_reg_rtx (SImode);
1282 operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
1283 TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
1284 if (GET_CODE (operands[2]) != CONST_INT)
1285 {
1286 emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
1287 operands[2] = operands[5];
1288 }
1289 "
1290 )
1292 (define_expand "umin<small_int_modes:mode>3"
1293 [(set (match_dup 4)
1294 (zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0")))
1295 (set (match_dup 3)
1296 (smin:SI (match_dup 4)
1297 (match_operand:small_int_modes 2 "rx_source_operand"
1298 "r,Sint08,Sint16,Sint24,i,Q")))
1299 (set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r")
1300 (match_dup 6))
1301 ]
1302 ""
1303 "operands[3] = gen_reg_rtx (SImode);
1304 operands[4] = gen_reg_rtx (SImode);
1305 operands[5] = gen_reg_rtx (SImode);
1306 operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
1307 TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
1308 if (GET_CODE (operands[2]) != CONST_INT)
1309 {
1310 emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
1311 operands[2] = operands[5];
1312 }
1313 "
1314 )
1316 (define_insn "mulsi3"
1317 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1318 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r")
1319 (match_operand:SI 2 "rx_source_operand"
1320 "r,Uint04,Sint08,Sint16,Sint24,i,Q,0,r")))]
1321 ""
1322 "@
1323 mul\t%2, %0
1324 mul\t%2, %0
1325 mul\t%2, %0
1326 mul\t%2, %0
1327 mul\t%2, %0
1328 mul\t%Q2, %0
1329 mul\t%Q2, %0
1330 mul\t%1, %0
1331 mul\t%2, %1, %0"
1332 [(set_attr "length" "2,2,3,4,5,6,5,2,3")
1333 (set_attr "timings" "11,11,11,11,11,11,33,11,11")]
1334 )
1336 (define_insn "negsi2"
1337 [(set (match_operand:SI 0 "register_operand" "=r,r")
1338 (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
1339 (clobber (reg:CC CC_REG))]
1340 ""
1341 "@
1342 neg\t%0
1343 neg\t%1, %0"
1344 [(set_attr "length" "2,3")]
1345 )
1347 ;; Note that the O and C flags are not set as per a normal compare,
1348 ;; and thus are unusable in that context.
1349 (define_insn "*negsi2_flags"
1350 [(set (reg CC_REG)
1351 (compare (neg:SI (match_operand:SI 1 "register_operand" "0,r"))
1352 (const_int 0)))
1353 (set (match_operand:SI 0 "register_operand" "=r,r")
1354 (neg:SI (match_dup 1)))]
1355 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1356 "@
1357 neg\t%0
1358 neg\t%1, %0"
1359 [(set_attr "length" "2,3")]
1360 )
1362 (define_insn "one_cmplsi2"
1363 [(set (match_operand:SI 0 "register_operand" "=r,r")
1364 (not:SI (match_operand:SI 1 "register_operand" "0,r")))
1365 (clobber (reg:CC CC_REG))]
1366 ""
1367 "@
1368 not\t%0
1369 not\t%1, %0"
1370 [(set_attr "length" "2,3")]
1371 )
1373 (define_insn "*one_cmplsi2_flags"
1374 [(set (reg CC_REG)
1375 (compare (not:SI (match_operand:SI 1 "register_operand" "0,r"))
1376 (const_int 0)))
1377 (set (match_operand:SI 0 "register_operand" "=r,r")
1378 (not:SI (match_dup 1)))]
1379 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1380 "@
1381 not\t%0
1382 not\t%1, %0"
1383 [(set_attr "length" "2,3")]
1384 )
1386 (define_insn "iorsi3"
1387 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1388 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1389 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
1390 (clobber (reg:CC CC_REG))]
1391 ""
1392 "@
1393 or\t%2, %0
1394 or\t%2, %0
1395 or\t%2, %0
1396 or\t%2, %0
1397 or\t%2, %0
1398 or\t%Q2, %0
1399 or\t%1, %0
1400 or\t%2, %1, %0
1401 or\t%Q2, %0"
1402 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1403 (set_attr "length" "2,2,3,4,5,6,2,3,5")]
1404 )
1406 (define_insn "*iorsi3_flags"
1407 [(set (reg CC_REG)
1408 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1409 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
1410 (const_int 0)))
1411 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1412 (ior:SI (match_dup 1) (match_dup 2)))]
1413 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1414 "@
1415 or\t%2, %0
1416 or\t%2, %0
1417 or\t%2, %0
1418 or\t%2, %0
1419 or\t%2, %0
1420 or\t%Q2, %0
1421 or\t%1, %0
1422 or\t%2, %1, %0
1423 or\t%Q2, %0"
1424 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1425 (set_attr "length" "2,2,3,4,5,6,2,3,5")]
1426 )
1428 (define_insn "rotlsi3"
1429 [(set (match_operand:SI 0 "register_operand" "=r")
1430 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1431 (match_operand:SI 2 "rx_shift_operand" "rn")))
1432 (clobber (reg:CC CC_REG))]
1433 ""
1434 "rotl\t%2, %0"
1435 [(set_attr "length" "3")]
1436 )
1438 (define_insn "*rotlsi3_flags"
1439 [(set (reg CC_REG)
1440 (compare (rotate:SI (match_operand:SI 1 "register_operand" "0")
1441 (match_operand:SI 2 "rx_shift_operand" "rn"))
1442 (const_int 0)))
1443 (set (match_operand:SI 0 "register_operand" "=r")
1444 (rotate:SI (match_dup 1) (match_dup 2)))]
1445 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1446 "rotl\t%2, %0"
1447 [(set_attr "length" "3")]
1448 )
1450 (define_insn "rotrsi3"
1451 [(set (match_operand:SI 0 "register_operand" "=r")
1452 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
1453 (match_operand:SI 2 "rx_shift_operand" "rn")))
1454 (clobber (reg:CC CC_REG))]
1455 ""
1456 "rotr\t%2, %0"
1457 [(set_attr "length" "3")]
1458 )
1460 (define_insn "*rotrsi3_flags"
1461 [(set (reg CC_REG)
1462 (compare (rotatert:SI (match_operand:SI 1 "register_operand" "0")
1463 (match_operand:SI 2 "rx_shift_operand" "rn"))
1464 (const_int 0)))
1465 (set (match_operand:SI 0 "register_operand" "=r")
1466 (rotatert:SI (match_dup 1) (match_dup 2)))]
1467 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1468 "rotr\t%2, %0"
1469 [(set_attr "length" "3")]
1470 )
1472 (define_insn "ashrsi3"
1473 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1474 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1475 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
1476 (clobber (reg:CC CC_REG))]
1477 ""
1478 "@
1479 shar\t%2, %0
1480 shar\t%2, %0
1481 shar\t%2, %1, %0"
1482 [(set_attr "length" "3,2,3")]
1483 )
1485 (define_insn "*ashrsi3_flags"
1486 [(set (reg CC_REG)
1487 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1488 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
1489 (const_int 0)))
1490 (set (match_operand:SI 0 "register_operand" "=r,r,r")
1491 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
1492 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1493 "@
1494 shar\t%2, %0
1495 shar\t%2, %0
1496 shar\t%2, %1, %0"
1497 [(set_attr "length" "3,2,3")]
1498 )
1500 (define_insn "lshrsi3"
1501 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1502 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1503 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
1504 (clobber (reg:CC CC_REG))]
1505 ""
1506 "@
1507 shlr\t%2, %0
1508 shlr\t%2, %0
1509 shlr\t%2, %1, %0"
1510 [(set_attr "length" "3,2,3")]
1511 )
1513 (define_insn "*lshrsi3_flags"
1514 [(set (reg CC_REG)
1515 (compare (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1516 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
1517 (const_int 0)))
1518 (set (match_operand:SI 0 "register_operand" "=r,r,r")
1519 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
1520 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1521 "@
1522 shlr\t%2, %0
1523 shlr\t%2, %0
1524 shlr\t%2, %1, %0"
1525 [(set_attr "length" "3,2,3")]
1526 )
1528 (define_insn "ashlsi3"
1529 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1530 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1531 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
1532 (clobber (reg:CC CC_REG))]
1533 ""
1534 "@
1535 shll\t%2, %0
1536 shll\t%2, %0
1537 shll\t%2, %1, %0"
1538 [(set_attr "length" "3,2,3")]
1539 )
1541 (define_insn "*ashlsi3_flags"
1542 [(set (reg CC_REG)
1543 (compare (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1544 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
1545 (const_int 0)))
1546 (set (match_operand:SI 0 "register_operand" "=r,r,r")
1547 (ashift:SI (match_dup 1) (match_dup 2)))]
1548 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1549 "@
1550 shll\t%2, %0
1551 shll\t%2, %0
1552 shll\t%2, %1, %0"
1553 [(set_attr "length" "3,2,3")]
1554 )
1556 ;; Saturate to 32-bits
1557 (define_insn_and_split "ssaddsi3"
1558 [(set (match_operand:SI 0 "register_operand" "=r")
1559 (ss_plus:SI (match_operand:SI 1 "register_operand" "r")
1560 (match_operand:SI 2 "rx_source_operand" "riQ")))
1561 (clobber (reg:CC CC_REG))]
1562 ""
1563 "#"
1564 "reload_completed"
1565 [(parallel [(set (reg:CC_ZSC CC_REG)
1566 (compare:CC_ZSC
1567 (plus:SI (match_dup 1) (match_dup 2))
1568 (const_int 0)))
1569 (set (match_dup 0)
1570 (plus:SI (match_dup 1) (match_dup 2)))])
1571 (set (match_dup 0)
1572 (unspec:SI [(match_dup 0) (reg:CC CC_REG)]
1573 UNSPEC_BUILTIN_SAT))]
1574 ""
1575 )
1577 (define_insn "*sat"
1578 [(set (match_operand:SI 0 "register_operand" "=r")
1579 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
1580 (reg:CC CC_REG)]
1581 UNSPEC_BUILTIN_SAT))]
1582 "reload_completed"
1583 "sat\t%0"
1584 [(set_attr "length" "2")]
1585 )
1587 (define_insn "subsi3"
1588 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1589 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
1590 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
1591 (clobber (reg:CC CC_REG))]
1592 ""
1593 "@
1594 sub\t%2, %0
1595 sub\t%2, %0
1596 add\t%N2, %0
1597 sub\t%2, %1, %0
1598 sub\t%Q2, %0"
1599 [(set_attr "timings" "11,11,11,11,33")
1600 (set_attr "length" "2,2,6,3,5")]
1601 )
1603 ;; Note that the O flag is set as if (compare op1 op2) not for
1604 ;; what is described here, (compare op0 0).
1605 (define_insn "*subsi3_flags"
1606 [(set (reg CC_REG)
1607 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
1608 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))
1609 (const_int 0)))
1610 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1611 (minus:SI (match_dup 1) (match_dup 2)))]
1612 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
1613 "@
1614 sub\t%2, %0
1615 sub\t%2, %0
1616 add\t%N2, %0
1617 sub\t%2, %1, %0
1618 sub\t%Q2, %0"
1619 [(set_attr "timings" "11,11,11,11,33")
1620 (set_attr "length" "2,2,6,3,5")]
1621 )
1623 ;; A helper to expand the above with the CC_MODE filled in.
1624 (define_expand "subsi3_flags"
1625 [(parallel [(set (reg:CC_ZSC CC_REG)
1626 (compare:CC_ZSC
1627 (minus:SI (match_operand:SI 1 "register_operand")
1628 (match_operand:SI 2 "rx_source_operand"))
1629 (const_int 0)))
1630 (set (match_operand:SI 0 "register_operand")
1631 (minus:SI (match_dup 1) (match_dup 2)))])]
1632 )
1634 (define_insn "sbb_internal"
1635 [(set (match_operand:SI 0 "register_operand" "=r,r")
1636 (minus:SI
1637 (minus:SI
1638 (match_operand:SI 1 "register_operand" " 0,0")
1639 (match_operand:SI 2 "rx_compare_operand" " r,Q"))
1640 (geu:SI (reg:CC CC_REG) (const_int 0))))
1641 (clobber (reg:CC CC_REG))]
1642 "reload_completed"
1643 "sbb\t%2, %0"
1644 [(set_attr "timings" "11,33")
1645 (set_attr "length" "3,6")]
1646 )
1648 (define_insn "*sbb_flags"
1649 [(set (reg CC_REG)
1650 (compare
1651 (minus:SI
1652 (minus:SI
1653 (match_operand:SI 1 "register_operand" " 0,0")
1654 (match_operand:SI 2 "rx_compare_operand" " r,Q"))
1655 (geu:SI (reg:CC CC_REG) (const_int 0)))
1656 (const_int 0)))
1657 (set (match_operand:SI 0 "register_operand" "=r,r")
1658 (minus:SI
1659 (minus:SI (match_dup 1) (match_dup 2))
1660 (geu:SI (reg:CC CC_REG) (const_int 0))))]
1661 "reload_completed"
1662 "sbb\t%2, %0"
1663 [(set_attr "timings" "11,33")
1664 (set_attr "length" "3,6")]
1665 )
1667 (define_expand "subdi3"
1668 [(set (match_operand:DI 0 "register_operand")
1669 (minus:DI (match_operand:DI 1 "register_operand")
1670 (match_operand:DI 2 "register_operand")))]
1671 ""
1672 {
1673 rtx op0l, op0h, op1l, op1h, op2l, op2h;
1675 op0l = gen_lowpart (SImode, operands[0]);
1676 op1l = gen_lowpart (SImode, operands[1]);
1677 op2l = gen_lowpart (SImode, operands[2]);
1678 op0h = gen_highpart (SImode, operands[0]);
1679 op1h = gen_highpart (SImode, operands[1]);
1680 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1682 emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
1683 DONE;
1684 })
1686 (define_insn_and_split "subdi3_internal"
1687 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
1688 (minus:SI (match_operand:SI 2 "register_operand" " 0, r")
1689 (match_operand:SI 3 "rx_compare_operand" "rQ, r")))
1690 (set (match_operand:SI 1 "register_operand" "= r, r")
1691 (minus:SI
1692 (minus:SI
1693 (match_operand:SI 4 "register_operand" " 1, 1")
1694 (match_operand:SI 5 "rx_compare_operand" " rQ,rQ"))
1695 (geu:SI (match_dup 2) (match_dup 3))))
1696 (clobber (reg:CC CC_REG))]
1697 ""
1698 "#"
1699 "reload_completed"
1700 [(const_int 0)]
1701 {
1702 emit_insn (gen_subsi3_flags (operands[0], operands[2], operands[3]));
1703 emit_insn (gen_sbb_internal (operands[1], operands[4], operands[5]));
1704 DONE;
1705 })
1707 (define_insn "xorsi3"
1708 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1709 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1710 (match_operand:SI 2 "rx_source_operand"
1711 "r,Sint08,Sint16,Sint24,i,Q")))
1712 (clobber (reg:CC CC_REG))]
1713 ""
1714 "xor\t%Q2, %0"
1715 [(set_attr "timings" "11,11,11,11,11,33")
1716 (set_attr "length" "3,4,5,6,7,6")]
1717 )
1719 (define_insn "*xorsi3_flags"
1720 [(set (reg CC_REG)
1721 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1722 (match_operand:SI 2 "rx_source_operand"
1723 "r,Sint08,Sint16,Sint24,i,Q"))
1724 (const_int 0)))
1725 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1726 (xor:SI (match_dup 1) (match_dup 2)))]
1727 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1728 "xor\t%Q2, %0"
1729 [(set_attr "timings" "11,11,11,11,11,33")
1730 (set_attr "length" "3,4,5,6,7,6")]
1731 )
1732 \f
1733 ;; A set of peepholes to catch extending loads followed by arithmetic operations.
1734 ;; We use iterators where possible to reduce the amount of typing and hence the
1735 ;; possibilities for typos.
1737 (define_code_iterator extend_types [(zero_extend "") (sign_extend "")])
1738 (define_code_attr letter [(zero_extend "R") (sign_extend "Q")])
1740 (define_code_iterator memex_commutative [(plus "") (and "") (ior "") (xor "")])
1741 (define_code_iterator memex_noncomm [(div "") (udiv "") (minus "")])
1742 (define_code_iterator memex_nocc [(smax "") (smin "") (mult "")])
1744 (define_code_attr op [(plus "add") (and "and") (div "div") (udiv "divu") (smax "max") (smin "min") (mult "mul") (ior "or") (minus "sub") (xor "xor")])
1746 (define_peephole2
1747 [(set (match_operand:SI 0 "register_operand")
1748 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1749 (parallel [(set (match_operand:SI 2 "register_operand")
1750 (memex_commutative:SI (match_dup 0)
1751 (match_dup 2)))
1752 (clobber (reg:CC CC_REG))])]
1753 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1754 [(parallel [(set (match_dup 2)
1755 (memex_commutative:SI (match_dup 2)
1756 (extend_types:SI (match_dup 1))))
1757 (clobber (reg:CC CC_REG))])]
1758 )
1760 (define_peephole2
1761 [(set (match_operand:SI 0 "register_operand")
1762 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1763 (parallel [(set (match_operand:SI 2 "register_operand")
1764 (memex_commutative:SI (match_dup 2)
1765 (match_dup 0)))
1766 (clobber (reg:CC CC_REG))])]
1767 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1768 [(parallel [(set (match_dup 2)
1769 (memex_commutative:SI (match_dup 2)
1770 (extend_types:SI (match_dup 1))))
1771 (clobber (reg:CC CC_REG))])]
1772 )
1774 (define_peephole2
1775 [(set (match_operand:SI 0 "register_operand")
1776 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1777 (parallel [(set (match_operand:SI 2 "register_operand")
1778 (memex_noncomm:SI (match_dup 2)
1779 (match_dup 0)))
1780 (clobber (reg:CC CC_REG))])]
1781 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1782 [(parallel [(set (match_dup 2)
1783 (memex_noncomm:SI (match_dup 2)
1784 (extend_types:SI (match_dup 1))))
1785 (clobber (reg:CC CC_REG))])]
1786 )
1788 (define_peephole2
1789 [(set (match_operand:SI 0 "register_operand")
1790 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1791 (set (match_operand:SI 2 "register_operand")
1792 (memex_nocc:SI (match_dup 0)
1793 (match_dup 2)))]
1794 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1795 [(set (match_dup 2)
1796 (memex_nocc:SI (match_dup 2)
1797 (extend_types:SI (match_dup 1))))]
1798 )
1800 (define_peephole2
1801 [(set (match_operand:SI 0 "register_operand")
1802 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1803 (set (match_operand:SI 2 "register_operand")
1804 (memex_nocc:SI (match_dup 2)
1805 (match_dup 0)))]
1806 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1807 [(set (match_dup 2)
1808 (memex_nocc:SI (match_dup 2)
1809 (extend_types:SI (match_dup 1))))]
1810 )
1812 (define_insn "<memex_commutative:code>si3_<extend_types:code><small_int_modes:mode>"
1813 [(set (match_operand:SI 0 "register_operand" "=r")
1814 (memex_commutative:SI (match_operand:SI 1 "register_operand" "%0")
1815 (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
1816 (clobber (reg:CC CC_REG))]
1817 "(optimize < 3 || optimize_size)"
1818 "<memex_commutative:op>\t%<extend_types:letter>2, %0"
1819 [(set_attr "timings" "33")
1820 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1821 )
1823 (define_insn "<memex_noncomm:code>si3_<extend_types:code><small_int_modes:mode>"
1824 [(set (match_operand:SI 0 "register_operand" "=r")
1825 (memex_noncomm:SI (match_operand:SI 1 "register_operand" "0")
1826 (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
1827 (clobber (reg:CC CC_REG))]
1828 "(optimize < 3 || optimize_size)"
1829 "<memex_noncomm:op>\t%<extend_types:letter>2, %0"
1830 [(set_attr "timings" "33")
1831 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1832 )
1834 (define_insn "<memex_nocc:code>si3_<extend_types:code><small_int_modes:mode>"
1835 [(set (match_operand:SI 0 "register_operand" "=r")
1836 (memex_nocc:SI (match_operand:SI 1 "register_operand" "%0")
1837 (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))]
1838 "(optimize < 3 || optimize_size)"
1839 "<memex_nocc:op>\t%<extend_types:letter>2, %0"
1840 [(set_attr "timings" "33")
1841 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1842 )
1844 (define_peephole2
1845 [(set (match_operand:SI 0 "register_operand")
1846 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1847 (set (reg:CC CC_REG)
1848 (compare:CC (match_operand:SI 2 "register_operand")
1849 (match_dup 0)))]
1850 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1851 [(set (reg:CC CC_REG)
1852 (compare:CC (match_dup 2)
1853 (extend_types:SI (match_dup 1))))]
1854 )
1856 ;; Convert:
1857 ;; (set (reg1) (sign_extend (mem))
1858 ;; (set (reg2) (zero_extend (reg1))
1859 ;; into
1860 ;; (set (reg2) (zero_extend (mem)))
1861 (define_peephole2
1862 [(set (match_operand:SI 0 "register_operand")
1863 (sign_extend:SI (match_operand:small_int_modes 1 "memory_operand")))
1864 (set (match_operand:SI 2 "register_operand")
1865 (zero_extend:SI (match_operand:small_int_modes 3 "register_operand")))]
1866 "REGNO (operands[0]) == REGNO (operands[3])
1867 && (REGNO (operands[0]) == REGNO (operands[2])
1868 || peep2_regno_dead_p (2, REGNO (operands[0])))"
1869 [(set (match_dup 2)
1870 (zero_extend:SI (match_dup 1)))]
1871 )
1873 ;; Remove the redundant sign extension from:
1874 ;; (set (reg) (extend (mem)))
1875 ;; (set (reg) (extend (reg)))
1876 (define_peephole2
1877 [(set (match_operand:SI 0 "register_operand")
1878 (extend_types:SI (match_operand:small_int_modes 1 "memory_operand")))
1879 (set (match_dup 0)
1880 (extend_types:SI (match_operand:small_int_modes 2 "register_operand")))]
1881 "REGNO (operands[0]) == REGNO (operands[2])"
1882 [(set (match_dup 0) (extend_types:SI (match_dup 1)))]
1883 )
1885 (define_insn "comparesi3_<extend_types:code><small_int_modes:mode>"
1886 [(set (reg:CC CC_REG)
1887 (compare:CC (match_operand:SI 0 "register_operand" "r")
1888 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand" "Q"))))]
1889 "(optimize < 3 || optimize_size)"
1890 "cmp\t%<extend_types:letter>1, %0"
1891 [(set_attr "timings" "33")
1892 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1893 )
1894 \f
1895 ;; Floating Point Instructions
1897 (define_insn "addsf3"
1898 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1899 (plus:SF (match_operand:SF 1 "register_operand" "%0,0,0")
1900 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1901 (clobber (reg:CC CC_REG))]
1902 "ALLOW_RX_FPU_INSNS"
1903 "fadd\t%2, %0"
1904 [(set_attr "timings" "44,44,66")
1905 (set_attr "length" "3,7,5")]
1906 )
1908 (define_insn "divsf3"
1909 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1910 (div:SF (match_operand:SF 1 "register_operand" "0,0,0")
1911 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1912 (clobber (reg:CC CC_REG))]
1913 "ALLOW_RX_FPU_INSNS"
1914 "fdiv\t%2, %0"
1915 [(set_attr "timings" "1616,1616,1818")
1916 (set_attr "length" "3,7,5")]
1917 )
1919 (define_insn "mulsf3"
1920 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1921 (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
1922 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1923 (clobber (reg:CC CC_REG))]
1924 "ALLOW_RX_FPU_INSNS"
1925 "fmul\t%2, %0"
1926 [(set_attr "timings" "33,33,55")
1927 (set_attr "length" "3,7,5")]
1928 )
1930 (define_insn "subsf3"
1931 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1932 (minus:SF (match_operand:SF 1 "register_operand" "0,0,0")
1933 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1934 (clobber (reg:CC CC_REG))]
1935 "ALLOW_RX_FPU_INSNS"
1936 "fsub\t%Q2, %0"
1937 [(set_attr "timings" "44,44,66")
1938 (set_attr "length" "3,7,5")]
1939 )
1941 (define_insn "fix_truncsfsi2"
1942 [(set (match_operand:SI 0 "register_operand" "=r,r")
1943 (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
1944 (clobber (reg:CC CC_REG))]
1945 "ALLOW_RX_FPU_INSNS"
1946 "ftoi\t%Q1, %0"
1947 [(set_attr "timings" "22,44")
1948 (set_attr "length" "3,5")]
1949 )
1951 (define_insn "floatsisf2"
1952 [(set (match_operand:SF 0 "register_operand" "=r,r")
1953 (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
1954 (clobber (reg:CC CC_REG))]
1955 "ALLOW_RX_FPU_INSNS"
1956 "itof\t%Q1, %0"
1957 [(set_attr "timings" "22,44")
1958 (set_attr "length" "3,6")]
1959 )
1960 \f
1961 ;; Bit manipulation instructions.
1963 ;; ??? The *_in_memory patterns will not be matched without further help.
1964 ;; At one time we had the insv expander generate them, but I suspect that
1965 ;; in general we get better performance by exposing the register load to
1966 ;; the optimizers.
1967 ;;
1968 ;; An alternate solution would be to re-organize these patterns such
1969 ;; that allow both register and memory operands. This would allow the
1970 ;; register allocator to spill and not load the register operand. This
1971 ;; would be possible only for operations for which we have a constant
1972 ;; bit offset, so that we can adjust the address by ofs/8 and replace
1973 ;; the offset in the insn by ofs%8.
1975 (define_insn "*bitset"
1976 [(set (match_operand:SI 0 "register_operand" "=r")
1977 (ior:SI (ashift:SI (const_int 1)
1978 (match_operand:SI 1 "rx_shift_operand" "ri"))
1979 (match_operand:SI 2 "register_operand" "0")))]
1980 ""
1981 "bset\t%1, %0"
1982 [(set_attr "length" "3")]
1983 )
1985 (define_insn "*bitset_in_memory"
1986 [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
1987 (ior:QI (ashift:QI (const_int 1)
1988 (match_operand:QI 1 "nonmemory_operand" "ri"))
1989 (match_dup 0)))]
1990 ""
1991 "bset\t%1, %0.B"
1992 [(set_attr "length" "3")
1993 (set_attr "timings" "33")]
1994 )
1996 (define_insn "*bitinvert"
1997 [(set (match_operand:SI 0 "register_operand" "=r")
1998 (xor:SI (ashift:SI (const_int 1)
1999 (match_operand:SI 1 "rx_shift_operand" "ri"))
2000 (match_operand:SI 2 "register_operand" "0")))]
2001 ""
2002 "bnot\t%1, %0"
2003 [(set_attr "length" "3")]
2004 )
2006 (define_insn "*bitinvert_in_memory"
2007 [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
2008 (xor:QI (ashift:QI (const_int 1)
2009 (match_operand:QI 1 "nonmemory_operand" "ri"))
2010 (match_dup 0)))]
2011 ""
2012 "bnot\t%1, %0.B"
2013 [(set_attr "length" "5")
2014 (set_attr "timings" "33")]
2015 )
2017 (define_insn "*bitclr"
2018 [(set (match_operand:SI 0 "register_operand" "=r")
2019 (and:SI (not:SI
2020 (ashift:SI
2021 (const_int 1)
2022 (match_operand:SI 1 "rx_shift_operand" "ri")))
2023 (match_operand:SI 2 "register_operand" "0")))]
2024 ""
2025 "bclr\t%1, %0"
2026 [(set_attr "length" "3")]
2027 )
2029 (define_insn "*bitclr_in_memory"
2030 [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
2031 (and:QI (not:QI
2032 (ashift:QI
2033 (const_int 1)
2034 (match_operand:QI 1 "nonmemory_operand" "ri")))
2035 (match_dup 0)))]
2036 ""
2037 "bclr\t%1, %0.B"
2038 [(set_attr "length" "3")
2039 (set_attr "timings" "33")]
2040 )
2042 (define_insn "*insv_imm"
2043 [(set (zero_extract:SI
2044 (match_operand:SI 0 "register_operand" "+r")
2045 (const_int 1)
2046 (match_operand:SI 1 "rx_shift_operand" "ri"))
2047 (match_operand:SI 2 "const_int_operand" ""))]
2048 ""
2049 {
2050 if (INTVAL (operands[2]) & 1)
2051 return "bset\t%1, %0";
2052 else
2053 return "bclr\t%1, %0";
2054 }
2055 [(set_attr "length" "3")]
2056 )
2058 (define_insn_and_split "rx_insv_reg"
2059 [(set (zero_extract:SI
2060 (match_operand:SI 0 "register_operand" "+r")
2061 (const_int 1)
2062 (match_operand:SI 1 "const_int_operand" ""))
2063 (match_operand:SI 2 "register_operand" "r"))
2064 (clobber (reg:CC CC_REG))]
2065 ""
2066 "#"
2067 "reload_completed"
2068 [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
2069 (match_dup 3))]
2070 {
2071 rtx flags, x;
2073 /* Emit tst #1, op2. */
2074 flags = gen_rtx_REG (CC_ZSmode, CC_REG);
2075 x = gen_rtx_AND (SImode, operands[2], const1_rtx);
2076 x = gen_rtx_COMPARE (CC_ZSmode, x, const0_rtx);
2077 x = gen_rtx_SET (flags, x);
2078 emit_insn (x);
2080 /* Emit bmne. */
2081 operands[3] = gen_rtx_NE (SImode, flags, const0_rtx);
2082 })
2084 (define_insn_and_split "*insv_cond"
2085 [(set (zero_extract:SI
2086 (match_operand:SI 0 "register_operand" "+r")
2087 (const_int 1)
2088 (match_operand:SI 1 "const_int_operand" ""))
2089 (match_operator:SI 4 "comparison_operator"
2090 [(match_operand:SI 2 "register_operand" "r")
2091 (match_operand:SI 3 "rx_source_operand" "riQ")]))
2092 (clobber (reg:CC CC_REG))]
2093 ""
2094 "#"
2095 "reload_completed"
2096 [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
2097 (match_dup 4))]
2098 {
2099 rtx flags, x;
2101 flags = gen_rtx_REG (CCmode, CC_REG);
2102 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
2103 x = gen_rtx_SET (flags, x);
2104 emit_insn (x);
2106 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
2107 flags, const0_rtx);
2108 })
2110 (define_insn "*bmcc"
2111 [(set (zero_extract:SI
2112 (match_operand:SI 0 "register_operand" "+r")
2113 (const_int 1)
2114 (match_operand:SI 1 "const_int_operand" ""))
2115 (match_operator:SI 2 "comparison_operator"
2116 [(reg CC_REG) (const_int 0)]))]
2117 "reload_completed"
2118 "bm%B2\t%1, %0"
2119 [(set_attr "length" "3")]
2120 )
2122 ;; Work around the fact that X=Y<0 is preferentially expanded as a shift.
2123 (define_insn_and_split "*insv_cond_lt"
2124 [(set (zero_extract:SI
2125 (match_operand:SI 0 "register_operand" "+r")
2126 (const_int 1)
2127 (match_operand:SI 1 "const_int_operand" ""))
2128 (match_operator:SI 3 "rshift_operator"
2129 [(match_operand:SI 2 "register_operand" "r")
2130 (const_int 31)]))
2131 (clobber (reg:CC CC_REG))]
2132 ""
2133 "#"
2134 ""
2135 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
2136 (lt:SI (match_dup 2) (const_int 0)))
2137 (clobber (reg:CC CC_REG))])]
2138 ""
2139 )
2141 (define_expand "insv"
2142 [(set (zero_extract:SI
2143 (match_operand:SI 0 "register_operand") ;; Destination
2144 (match_operand:SI 1 "const_int_operand") ;; # of bits to set
2145 (match_operand:SI 2 "nonmemory_operand")) ;; Starting bit
2146 (match_operand:SI 3 "nonmemory_operand"))] ;; Bits to insert
2147 ""
2148 {
2149 /* We only handle single-bit inserts. */
2150 if (!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 1)
2151 FAIL;
2153 /* Either the bit to insert or the position must be constant. */
2154 if (CONST_INT_P (operands[3]))
2155 operands[3] = GEN_INT (INTVAL (operands[3]) & 1);
2156 else if (CONST_INT_P (operands[2]))
2157 {
2158 emit_insn (gen_rx_insv_reg (operands[0], operands[2], operands[3]));
2159 DONE;
2160 }
2161 else
2162 FAIL;
2163 })
2164 \f
2165 ;; Atomic operations.
2167 (define_code_iterator FETCHOP [plus minus ior xor and])
2168 (define_code_iterator FETCHOP_NO_MINUS [plus ior xor and])
2170 (define_code_attr fetchop_name
2171 [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
2173 (define_code_attr fetchop_name2
2174 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
2176 (define_mode_iterator QIHI [QI HI])
2177 (define_mode_attr BW [(QI "B") (HI "W")])
2179 (define_insn "sync_lock_test_and_setsi"
2180 [(set (match_operand:SI 0 "register_operand" "=r,r")
2181 (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
2182 (set (match_dup 1)
2183 (match_operand:SI 2 "register_operand" "0,0"))]
2184 ""
2185 "xchg\t%1, %0"
2186 [(set_attr "length" "3,6")
2187 (set_attr "timings" "22")]
2188 )
2190 (define_expand "atomic_exchange<mode>"
2191 [(match_operand:QIHI 0 "register_operand") ;; oldval output
2192 (match_operand:QIHI 1 "rx_restricted_mem_operand") ;; memory
2193 (match_operand:QIHI 2 "register_operand") ;; newval input
2194 (match_operand:QIHI 3 "const_int_operand")] ;; memory model
2195 ""
2196 {
2197 emit_insn (gen_xchg_mem<mode> (operands[0], operands[1], operands[2]));
2198 DONE;
2199 })
2201 (define_expand "atomic_exchangesi"
2202 [(match_operand:SI 0 "register_operand") ;; oldval output
2203 (match_operand:SI 1 "rx_restricted_mem_operand") ;; memory
2204 (match_operand:SI 2 "register_operand") ;; newval input
2205 (match_operand:SI 3 "const_int_operand")] ;; memory model
2206 ""
2207 {
2208 emit_insn (gen_sync_lock_test_and_setsi (operands[0], operands[1],
2209 operands[2]));
2210 DONE;
2211 })
2213 (define_insn "xchg_mem<mode>"
2214 [(set (match_operand:QIHI 0 "register_operand" "=r")
2215 (match_operand:QIHI 1 "rx_compare_operand" "=Q"))
2216 (set (match_dup 1)
2217 (match_operand:QIHI 2 "register_operand" "0"))]
2218 ""
2219 "xchg\t%1.<BW>, %0"
2220 [(set_attr "length" "6")
2221 (set_attr "timings" "22")]
2222 )
2224 ;; read - modify - write - return old value
2225 (define_expand "atomic_fetch_<fetchop_name>si"
2226 [(set (match_operand:SI 0 "register_operand")
2227 (match_operand:SI 1 "memory_operand"))
2228 (set (match_dup 1)
2229 (FETCHOP:SI (match_dup 1) (match_operand:SI 2 "rx_source_operand")))
2230 (match_operand:SI 3 "const_int_operand")] ;; memory model
2231 ""
2232 {
2233 {
2234 rx_atomic_sequence seq (current_function_decl);
2236 emit_move_insn (operands[0], operands[1]);
2238 rtx tmp = gen_reg_rtx (SImode);
2239 emit_insn (gen_<fetchop_name2>si3 (tmp, operands[0], operands[2]));
2241 emit_move_insn (operands[1], tmp);
2242 }
2243 DONE;
2244 })
2246 (define_expand "atomic_fetch_nandsi"
2247 [(set (match_operand:SI 0 "register_operand")
2248 (match_operand:SI 1 "memory_operand"))
2249 (set (match_dup 1)
2250 (not:SI (and:SI (match_dup 1)
2251 (match_operand:SI 2 "rx_source_operand"))))
2252 (match_operand:SI 3 "const_int_operand")] ;; memory model
2253 ""
2254 {
2255 {
2256 rx_atomic_sequence seq (current_function_decl);
2258 emit_move_insn (operands[0], operands[1]);
2260 rtx tmp = gen_reg_rtx (SImode);
2261 emit_insn (gen_andsi3 (tmp, operands[0], operands[2]));
2262 emit_insn (gen_one_cmplsi2 (tmp, tmp));
2264 emit_move_insn (operands[1], tmp);
2265 }
2266 DONE;
2267 })
2269 ;; read - modify - write - return new value
2270 ;; Because subtraction is not commutative we need to specify a different
2271 ;; set of patterns for it.
2272 (define_expand "atomic_<fetchop_name>_fetchsi"
2273 [(set (match_operand:SI 0 "register_operand")
2274 (FETCHOP_NO_MINUS:SI (match_operand:SI 1 "rx_restricted_mem_operand")
2275 (match_operand:SI 2 "register_operand")))
2276 (set (match_dup 1)
2277 (FETCHOP_NO_MINUS:SI (match_dup 1) (match_dup 2)))
2278 (match_operand:SI 3 "const_int_operand")] ;; memory model
2279 ""
2280 {
2281 {
2282 rx_atomic_sequence seq (current_function_decl);
2284 emit_move_insn (operands[0], operands[2]);
2285 emit_insn (gen_<fetchop_name2>si3 (operands[0], operands[0], operands[1]));
2286 emit_move_insn (operands[1], operands[0]);
2287 }
2288 DONE;
2289 })
2291 (define_expand "atomic_sub_fetchsi"
2292 [(set (match_operand:SI 0 "register_operand")
2293 (minus:SI (match_operand:SI 1 "rx_restricted_mem_operand")
2294 (match_operand:SI 2 "rx_source_operand")))
2295 (set (match_dup 1)
2296 (minus:SI (match_dup 1) (match_dup 2)))
2297 (match_operand:SI 3 "const_int_operand")] ;; memory model
2298 ""
2299 {
2300 {
2301 rx_atomic_sequence seq (current_function_decl);
2303 emit_move_insn (operands[0], operands[1]);
2304 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
2305 emit_move_insn (operands[1], operands[0]);
2306 }
2307 DONE;
2308 })
2310 (define_expand "atomic_nand_fetchsi"
2311 [(set (match_operand:SI 0 "register_operand")
2312 (not:SI (and:SI (match_operand:SI 1 "rx_restricted_mem_operand")
2313 (match_operand:SI 2 "register_operand"))))
2314 (set (match_dup 1)
2315 (not:SI (and:SI (match_dup 1) (match_dup 2))))
2316 (match_operand:SI 3 "const_int_operand")] ;; memory model
2317 ""
2318 {
2319 {
2320 rx_atomic_sequence seq (current_function_decl);
2322 emit_move_insn (operands[0], operands[2]);
2323 emit_insn (gen_andsi3 (operands[0], operands[0], operands[1]));
2324 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
2325 emit_move_insn (operands[1], operands[0]);
2326 }
2327 DONE;
2328 });
2330 \f
2331 ;; Block move functions.
2333 (define_expand "movstr"
2334 [(set (match_operand:BLK 1 "memory_operand") ;; Dest
2335 (match_operand:BLK 2 "memory_operand")) ;; Source
2336 (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
2337 ]
2338 "rx_allow_string_insns"
2339 {
2340 rtx addr1 = gen_rtx_REG (SImode, 1);
2341 rtx addr2 = gen_rtx_REG (SImode, 2);
2342 rtx len = gen_rtx_REG (SImode, 3);
2343 rtx dest_copy = gen_reg_rtx (SImode);
2345 emit_move_insn (len, GEN_INT (-1));
2346 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2347 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2348 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2349 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2350 emit_move_insn (dest_copy, addr1);
2351 emit_insn (gen_rx_movstr ());
2352 emit_move_insn (len, GEN_INT (-1));
2353 emit_insn (gen_rx_strend (operands[0], dest_copy));
2354 DONE;
2355 }
2356 )
2358 (define_insn "rx_movstr"
2359 [(set (mem:BLK (reg:SI 1))
2360 (mem:BLK (reg:SI 2)))
2361 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR)
2362 (clobber (reg:SI 1))
2363 (clobber (reg:SI 2))
2364 (clobber (reg:SI 3))]
2365 "rx_allow_string_insns"
2366 "smovu"
2367 [(set_attr "length" "2")
2368 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
2369 )
2371 (define_insn "rx_strend"
2372 [(set (match_operand:SI 0 "register_operand" "=r")
2373 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2374 (reg:SI 3)] UNSPEC_STRLEN))
2375 (clobber (reg:SI 1))
2376 (clobber (reg:SI 2))
2377 (clobber (reg:SI 3))
2378 (clobber (reg:CC CC_REG))
2379 ]
2380 "rx_allow_string_insns"
2381 "mov\t%1, r1\n\tmov\t#0, r2\n\tsuntil.b\n\tmov\tr1, %0\n\tsub\t#1, %0"
2382 [(set_attr "length" "10")
2383 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
2384 )
2386 (define_expand "movmemsi"
2387 [(parallel
2388 [(set (match_operand:BLK 0 "memory_operand") ;; Dest
2389 (match_operand:BLK 1 "memory_operand")) ;; Source
2390 (use (match_operand:SI 2 "register_operand")) ;; Length in bytes
2391 (match_operand 3 "immediate_operand") ;; Align
2392 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)]
2393 )]
2394 "rx_allow_string_insns"
2395 {
2396 rtx addr1 = gen_rtx_REG (SImode, 1);
2397 rtx addr2 = gen_rtx_REG (SImode, 2);
2398 rtx len = gen_rtx_REG (SImode, 3);
2400 /* Do not use when the source or destination are volatile - the SMOVF
2401 instruction will read and write in word sized blocks, which may be
2402 outside of the valid address range. */
2403 if (MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2404 FAIL;
2405 if (MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))
2406 FAIL;
2408 if (REG_P (operands[0]) && (REGNO (operands[0]) == 2
2409 || REGNO (operands[0]) == 3))
2410 FAIL;
2411 if (REG_P (operands[1]) && (REGNO (operands[1]) == 1
2412 || REGNO (operands[1]) == 3))
2413 FAIL;
2414 if (REG_P (operands[2]) && (REGNO (operands[2]) == 1
2415 || REGNO (operands[2]) == 2))
2416 FAIL;
2418 emit_move_insn (addr1, force_operand (XEXP (operands[0], 0), NULL_RTX));
2419 emit_move_insn (addr2, force_operand (XEXP (operands[1], 0), NULL_RTX));
2420 emit_move_insn (len, force_operand (operands[2], NULL_RTX));
2421 operands[0] = replace_equiv_address_nv (operands[0], addr1);
2422 operands[1] = replace_equiv_address_nv (operands[1], addr2);
2423 emit_insn (gen_rx_movmem ());
2424 DONE;
2425 }
2426 )
2428 (define_insn "rx_movmem"
2429 [(set (mem:BLK (reg:SI 1))
2430 (mem:BLK (reg:SI 2)))
2431 (use (reg:SI 3))
2432 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)
2433 (clobber (reg:SI 1))
2434 (clobber (reg:SI 2))
2435 (clobber (reg:SI 3))]
2436 "rx_allow_string_insns"
2437 "smovf"
2438 [(set_attr "length" "2")
2439 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
2440 )
2442 (define_expand "setmemsi"
2443 [(set (match_operand:BLK 0 "memory_operand") ;; Dest
2444 (match_operand:QI 2 "nonmemory_operand")) ;; Value
2445 (use (match_operand:SI 1 "nonmemory_operand")) ;; Length
2446 (match_operand 3 "immediate_operand") ;; Align
2447 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM)]
2448 ""
2449 {
2450 rtx addr = gen_rtx_REG (SImode, 1);
2451 rtx val = gen_rtx_REG (QImode, 2);
2452 rtx len = gen_rtx_REG (SImode, 3);
2454 emit_move_insn (addr, force_operand (XEXP (operands[0], 0), NULL_RTX));
2455 emit_move_insn (len, force_operand (operands[1], NULL_RTX));
2456 emit_move_insn (val, operands[2]);
2457 emit_insn (gen_rx_setmem ());
2458 DONE;
2459 }
2460 )
2462 (define_insn "rx_setmem"
2463 [(set (mem:BLK (reg:SI 1))
2464 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM))
2465 (clobber (reg:SI 1))
2466 (clobber (reg:SI 3))]
2467 ""
2468 "sstr.b"
2469 [(set_attr "length" "2")
2470 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
2471 )
2473 (define_expand "cmpstrnsi"
2474 [(set (match_operand:SI 0 "register_operand") ;; Result
2475 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1
2476 (match_operand:BLK 2 "memory_operand")] ;; String2
2477 UNSPEC_CMPSTRN))
2478 (use (match_operand:SI 3 "register_operand")) ;; Max Length
2479 (match_operand:SI 4 "immediate_operand")] ;; Known Align
2480 "rx_allow_string_insns"
2481 {
2482 rtx str1 = gen_rtx_REG (SImode, 1);
2483 rtx str2 = gen_rtx_REG (SImode, 2);
2484 rtx len = gen_rtx_REG (SImode, 3);
2486 emit_move_insn (str1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2487 emit_move_insn (str2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2488 emit_move_insn (len, operands[3]);
2490 emit_insn (gen_rx_cmpstrn (operands[0], operands[1], operands[2]));
2491 DONE;
2492 }
2493 )
2495 (define_expand "cmpstrsi"
2496 [(set (match_operand:SI 0 "register_operand") ;; Result
2497 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1
2498 (match_operand:BLK 2 "memory_operand")] ;; String2
2499 UNSPEC_CMPSTRN))
2500 (match_operand:SI 3 "immediate_operand")] ;; Known Align
2501 "rx_allow_string_insns"
2502 {
2503 rtx str1 = gen_rtx_REG (SImode, 1);
2504 rtx str2 = gen_rtx_REG (SImode, 2);
2505 rtx len = gen_rtx_REG (SImode, 3);
2507 emit_move_insn (str1, force_reg (SImode, XEXP (operands[1], 0)));
2508 emit_move_insn (str2, force_reg (SImode, XEXP (operands[2], 0)));
2509 emit_move_insn (len, GEN_INT (-1));
2511 emit_insn (gen_rx_cmpstrn (operands[0], operands[1], operands[2]));
2512 DONE;
2513 }
2514 )
2516 (define_insn "rx_cmpstrn"
2517 [(set (match_operand:SI 0 "register_operand" "=r")
2518 (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)]
2519 UNSPEC_CMPSTRN))
2520 (use (match_operand:BLK 1 "memory_operand" "m"))
2521 (use (match_operand:BLK 2 "memory_operand" "m"))
2522 (clobber (reg:SI 1))
2523 (clobber (reg:SI 2))
2524 (clobber (reg:SI 3))
2525 (clobber (reg:CC CC_REG))]
2526 "rx_allow_string_insns"
2527 "scmpu ; Perform the string comparison
2528 mov #-1, %0 ; Set up -1 result (which cannot be created
2529 ; by the SC insn)
2530 bnc ?+ ; If Carry is not set skip over
2531 scne.L %0 ; Set result based on Z flag
2532 ?:
2533 "
2534 [(set_attr "length" "9")
2535 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
2536 )
2537 \f
2538 ;; Builtin Functions
2539 ;;
2540 ;; GCC does not have the ability to generate the following instructions
2541 ;; on its own so they are provided as builtins instead. To use them from
2542 ;; a program for example invoke them as __builtin_rx_<insn_name>. For
2543 ;; example:
2544 ;;
2545 ;; int short_byte_swap (int arg) { return __builtin_rx_revw (arg); }
2547 ;;---------- Accumulator Support ------------------------
2549 ;; Multiply & Accumulate (high)
2550 (define_insn "machi"
2551 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2552 (match_operand:SI 1 "register_operand" "r")]
2553 UNSPEC_BUILTIN_MACHI)]
2554 ""
2555 "machi\t%0, %1"
2556 [(set_attr "length" "3")]
2557 )
2559 ;; Multiply & Accumulate (low)
2560 (define_insn "maclo"
2561 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2562 (match_operand:SI 1 "register_operand" "r")]
2563 UNSPEC_BUILTIN_MACLO)]
2564 ""
2565 "maclo\t%0, %1"
2566 [(set_attr "length" "3")]
2567 )
2569 ;; Multiply (high)
2570 (define_insn "mulhi"
2571 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2572 (match_operand:SI 1 "register_operand" "r")]
2573 UNSPEC_BUILTIN_MULHI)]
2574 ""
2575 "mulhi\t%0, %1"
2576 [(set_attr "length" "3")]
2577 )
2579 ;; Multiply (low)
2580 (define_insn "mullo"
2581 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2582 (match_operand:SI 1 "register_operand" "r")]
2583 UNSPEC_BUILTIN_MULLO)]
2584 ""
2585 "mullo\t%0, %1"
2586 [(set_attr "length" "3")]
2587 )
2589 ;; Move from Accumulator (high)
2590 (define_insn "mvfachi"
2591 [(set (match_operand:SI 0 "register_operand" "=r")
2592 (unspec:SI [(const_int 0)]
2593 UNSPEC_BUILTIN_MVFACHI))]
2594 ""
2595 "mvfachi\t%0"
2596 [(set_attr "length" "3")]
2597 )
2599 ;; Move from Accumulator (middle)
2600 (define_insn "mvfacmi"
2601 [(set (match_operand:SI 0 "register_operand" "=r")
2602 (unspec:SI [(const_int 0)]
2603 UNSPEC_BUILTIN_MVFACMI))]
2604 ""
2605 "mvfacmi\t%0"
2606 [(set_attr "length" "3")]
2607 )
2609 ;; Move to Accumulator (high)
2610 (define_insn "mvtachi"
2611 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2612 UNSPEC_BUILTIN_MVTACHI)]
2613 ""
2614 "mvtachi\t%0"
2615 [(set_attr "length" "3")]
2616 )
2618 ;; Move to Accumulator (low)
2619 (define_insn "mvtaclo"
2620 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2621 UNSPEC_BUILTIN_MVTACLO)]
2622 ""
2623 "mvtaclo\t%0"
2624 [(set_attr "length" "3")]
2625 )
2627 ;; Round Accumulator
2628 (define_insn "racw"
2629 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
2630 UNSPEC_BUILTIN_RACW)]
2631 ""
2632 "racw\t%0"
2633 [(set_attr "length" "3")]
2634 )
2636 ;; Repeat multiply and accumulate
2637 (define_insn "rmpa"
2638 [(unspec:SI [(const_int 0) (reg:SI 1) (reg:SI 2) (reg:SI 3)
2639 (reg:SI 4) (reg:SI 5) (reg:SI 6)]
2640 UNSPEC_BUILTIN_RMPA)
2641 (clobber (reg:SI 1))
2642 (clobber (reg:SI 2))
2643 (clobber (reg:SI 3))]
2644 "rx_allow_string_insns"
2645 "rmpa"
2646 [(set_attr "length" "2")
2647 (set_attr "timings" "1010")]
2648 )
2650 ;;---------- Arithmetic ------------------------
2652 ;; Byte swap (two 16-bit values).
2653 (define_insn "revw"
2654 [(set (match_operand:SI 0 "register_operand" "=r")
2655 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
2656 UNSPEC_BUILTIN_REVW))]
2657 ""
2658 "revw\t%1, %0"
2659 [(set_attr "length" "3")]
2660 )
2662 ;; Round to integer.
2663 (define_insn "lrintsf2"
2664 [(set (match_operand:SI 0 "register_operand" "=r,r")
2665 (unspec:SI [(match_operand:SF 1 "rx_compare_operand" "r,Q")]
2666 UNSPEC_BUILTIN_ROUND))
2667 (clobber (reg:CC CC_REG))]
2668 ""
2669 "round\t%1, %0"
2670 [(set_attr "timings" "22,44")
2671 (set_attr "length" "3,5")]
2672 )
2674 ;;---------- Control Registers ------------------------
2676 ;; Clear Processor Status Word
2677 (define_insn "clrpsw"
2678 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
2679 UNSPEC_BUILTIN_CLRPSW)
2680 (clobber (reg:CC CC_REG))]
2681 ""
2682 "clrpsw\t%F0"
2683 [(set_attr "length" "2")]
2684 )
2686 ;; Set Processor Status Word
2687 (define_insn "setpsw"
2688 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
2689 UNSPEC_BUILTIN_SETPSW)
2690 (clobber (reg:CC CC_REG))]
2691 ""
2692 "setpsw\t%F0"
2693 [(set_attr "length" "2")]
2694 )
2696 ;; Move from control register
2697 (define_insn "mvfc"
2698 [(set (match_operand:SI 0 "register_operand" "=r")
2699 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
2700 UNSPEC_BUILTIN_MVFC))]
2701 ""
2702 "mvfc\t%C1, %0"
2703 [(set_attr "length" "3")]
2704 )
2706 ;; Move to control register
2707 ;; This insn can be used in atomic sequences to restore the previous PSW
2708 ;; and re-enable interrupts. Because of that it always clobbers the CC_REG.
2709 (define_insn "mvtc"
2710 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i")
2711 (match_operand:SI 1 "nonmemory_operand" "r,i")]
2712 UNSPEC_BUILTIN_MVTC)
2713 (clobber (reg:CC CC_REG))]
2714 ""
2715 "mvtc\t%1, %C0"
2716 [(set_attr "length" "3,7")]
2717 )
2719 ;; Move to interrupt priority level
2720 (define_insn "mvtipl"
2721 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
2722 UNSPEC_BUILTIN_MVTIPL)]
2723 ""
2724 "mvtipl\t%0"
2725 [(set_attr "length" "3")]
2726 )
2728 ;;---------- Interrupts ------------------------
2730 ;; Break
2731 (define_insn "brk"
2732 [(unspec_volatile [(const_int 0)]
2733 UNSPEC_BUILTIN_BRK)]
2734 ""
2735 "brk"
2736 [(set_attr "length" "1")
2737 (set_attr "timings" "66")]
2738 )
2740 ;; Interrupt
2741 (define_insn "int"
2742 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
2743 UNSPEC_BUILTIN_INT)]
2744 ""
2745 "int\t%0"
2746 [(set_attr "length" "3")]
2747 )
2749 ;; Wait
2750 (define_insn "wait"
2751 [(unspec_volatile [(const_int 0)]
2752 UNSPEC_BUILTIN_WAIT)]
2753 ""
2754 "wait"
2755 [(set_attr "length" "2")]
2756 )
2758 ;;---------- CoProcessor Support ------------------------
2760 ;; FIXME: The instructions are currently commented out because
2761 ;; the bit patterns have not been finalized, so the assembler
2762 ;; does not support them. Once they are decided and the assembler
2763 ;; supports them, enable the instructions here.
2765 ;; Move from co-processor register
2766 (define_insn "mvfcp"
2767 [(set (match_operand:SI 0 "register_operand" "=r")
2768 (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
2769 (match_operand:SI 2 "immediate_operand" "i")]
2770 UNSPEC_BUILTIN_MVFCP))]
2771 ""
2772 "; mvfcp\t%1, %0, %2"
2773 [(set_attr "length" "5")]
2774 )
2776 ;;---------- Misc ------------------------
2778 ;; Required by cfglayout.c...
2779 (define_insn "nop"
2780 [(const_int 0)]
2781 ""
2782 "nop"
2783 [(set_attr "length" "1")]
2784 )
2786 (define_expand "pid_addr"
2787 [(plus:SI (match_operand:SI 0)
2788 (const:SI (unspec:SI [(match_operand:SI 1)] UNSPEC_PID_ADDR)))]
2789 ""
2790 ""
2791 )
2793 (define_insn "movdi"
2794 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
2795 (match_operand:DI 1 "general_operand" "rmi"))]
2796 "TARGET_ENABLE_LRA"
2797 { return rx_gen_move_template (operands, false); }
2798 [(set_attr "length" "16")
2799 (set_attr "timings" "22")]
2800 )
2802 (define_insn "movdf"
2803 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm")
2804 (match_operand:DF 1 "general_operand" "rmi"))]
2805 "TARGET_ENABLE_LRA"
2806 { return rx_gen_move_template (operands, false); }
2807 [(set_attr "length" "16")
2808 (set_attr "timings" "22")]
2809 )