1 ;; Expander definitions for vector support between altivec & vsx. No
2 ;; instructions are in this file, this file provides the generic vector
3 ;; expander, and the actual vector instructions will be in altivec.md and
6 ;; Copyright (C) 2009, 2010, 2011
7 ;; Free Software Foundation, Inc.
8 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify it
13 ;; under the terms of the GNU General Public License as published
14 ;; by the Free Software Foundation; either version 3, or (at your
15 ;; option) any later version.
17 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
18 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 ;; License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
28 (define_mode_iterator VEC_I [V16QI V8HI V4SI])
31 (define_mode_iterator VEC_F [V4SF V2DF])
33 ;; Vector arithmetic modes
34 (define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])
36 ;; Vector modes that need alginment via permutes
37 (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
39 ;; Vector logical modes
40 (define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
42 ;; Vector modes for moves. Don't do TImode here.
43 (define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])
45 ;; Vector modes for types that don't need a realignment under VSX
46 (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])
48 ;; Vector comparison modes
49 (define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])
51 ;; Vector init/extract modes
52 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
54 ;; Vector modes for 64-bit base types
55 (define_mode_iterator VEC_64 [V2DI V2DF])
57 ;; Vector reload iterator
58 (define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
60 ;; Base type from vector mode
61 (define_mode_attr VEC_base [(V16QI "QI")
69 ;; Same size integer type for floating point data
70 (define_mode_attr VEC_int [(V4SF "v4si")
73 (define_mode_attr VEC_INT [(V4SF "V4SI")
76 ;; constants for unspec
77 (define_c_enum "unspec" [UNSPEC_PREDICATE])
80 ;; Vector move instructions.
81 (define_expand "mov<mode>"
82 [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
83 (match_operand:VEC_M 1 "any_operand" ""))]
84 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
86 if (can_create_pseudo_p ())
88 if (CONSTANT_P (operands[1])
89 && !easy_vector_constant (operands[1], <MODE>mode))
90 operands[1] = force_const_mem (<MODE>mode, operands[1]);
92 else if (!vlogical_operand (operands[0], <MODE>mode)
93 && !vlogical_operand (operands[1], <MODE>mode))
94 operands[1] = force_reg (<MODE>mode, operands[1]);
98 ;; Generic vector floating point load/store instructions. These will match
99 ;; insns defined in vsx.md or altivec.md depending on the switches.
100 (define_expand "vector_load_<mode>"
101 [(set (match_operand:VEC_M 0 "vfloat_operand" "")
102 (match_operand:VEC_M 1 "memory_operand" ""))]
103 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
106 (define_expand "vector_store_<mode>"
107 [(set (match_operand:VEC_M 0 "memory_operand" "")
108 (match_operand:VEC_M 1 "vfloat_operand" ""))]
109 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
112 ;; Splits if a GPR register was chosen for the move
114 [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
115 (match_operand:VEC_L 1 "input_operand" ""))]
116 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
118 && gpr_or_gpr_p (operands[0], operands[1])"
121 rs6000_split_multireg_move (operands[0], operands[1]);
125 ;; Vector floating point load/store instructions that uses the Altivec
126 ;; instructions even if we are compiling for VSX, since the Altivec
127 ;; instructions silently ignore the bottom 3 bits of the address, and VSX does
129 (define_expand "vector_altivec_load_<mode>"
130 [(set (match_operand:VEC_M 0 "vfloat_operand" "")
131 (match_operand:VEC_M 1 "memory_operand" ""))]
132 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
135 gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
137 if (VECTOR_MEM_VSX_P (<MODE>mode))
139 operands[1] = rs6000_address_for_altivec (operands[1]);
140 emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
145 (define_expand "vector_altivec_store_<mode>"
146 [(set (match_operand:VEC_M 0 "memory_operand" "")
147 (match_operand:VEC_M 1 "vfloat_operand" ""))]
148 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
151 gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
153 if (VECTOR_MEM_VSX_P (<MODE>mode))
155 operands[0] = rs6000_address_for_altivec (operands[0]);
156 emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1]));
163 ;; Reload patterns for vector operations. We may need an addtional base
164 ;; register to convert the reg+offset addressing to reg+reg for vector
165 ;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
166 ;; register for gpr registers.
167 (define_expand "reload_<VEC_R:mode>_<P:mptrsize>_store"
168 [(parallel [(match_operand:VEC_R 0 "memory_operand" "m")
169 (match_operand:VEC_R 1 "gpc_reg_operand" "r")
170 (match_operand:P 2 "register_operand" "=&b")])]
173 rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
177 (define_expand "reload_<VEC_R:mode>_<P:mptrsize>_load"
178 [(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r")
179 (match_operand:VEC_R 1 "memory_operand" "m")
180 (match_operand:P 2 "register_operand" "=&b")])]
183 rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
187 ;; Reload sometimes tries to move the address to a GPR, and can generate
188 ;; invalid RTL for addresses involving AND -16. Allow addresses involving
189 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
191 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
192 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
193 (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
194 (match_operand:P 2 "reg_or_cint_operand" "rI"))
196 "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
198 "&& reload_completed"
200 (plus:P (match_dup 1)
202 (parallel [(set (match_dup 0)
205 (clobber:CC (scratch:CC))])])
207 ;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16
208 ;; address to a register because there is no clobber of a (scratch), so we add
210 (define_insn_and_split "*vec_reload_and_reg_<mptrsize>"
211 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
212 (and:P (match_operand:P 1 "gpc_reg_operand" "r")
214 "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
216 "&& reload_completed"
217 [(parallel [(set (match_dup 0)
220 (clobber:CC (scratch:CC))])])
222 ;; Generic floating point vector arithmetic support
223 (define_expand "add<mode>3"
224 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
225 (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
226 (match_operand:VEC_F 2 "vfloat_operand" "")))]
227 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
230 (define_expand "sub<mode>3"
231 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
232 (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
233 (match_operand:VEC_F 2 "vfloat_operand" "")))]
234 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
237 (define_expand "mul<mode>3"
238 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
239 (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
240 (match_operand:VEC_F 2 "vfloat_operand" "")))]
241 "VECTOR_UNIT_VSX_P (<MODE>mode) || VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
243 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
245 emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
250 (define_expand "div<mode>3"
251 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
252 (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
253 (match_operand:VEC_F 2 "vfloat_operand" "")))]
254 "VECTOR_UNIT_VSX_P (<MODE>mode)"
257 (define_expand "neg<mode>2"
258 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
259 (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
260 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
263 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
265 emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
270 (define_expand "abs<mode>2"
271 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
272 (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
273 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
276 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
278 emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
283 (define_expand "smin<mode>3"
284 [(set (match_operand:VEC_F 0 "register_operand" "")
285 (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
286 (match_operand:VEC_F 2 "register_operand" "")))]
287 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
290 (define_expand "smax<mode>3"
291 [(set (match_operand:VEC_F 0 "register_operand" "")
292 (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
293 (match_operand:VEC_F 2 "register_operand" "")))]
294 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
298 (define_expand "sqrt<mode>2"
299 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
300 (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
301 "VECTOR_UNIT_VSX_P (<MODE>mode)"
304 (define_expand "rsqrte<mode>2"
305 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
306 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
308 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
311 (define_expand "re<mode>2"
312 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
313 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
315 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
318 (define_expand "ftrunc<mode>2"
319 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
320 (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
321 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
324 (define_expand "vector_ceil<mode>2"
325 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
326 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
328 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
331 (define_expand "vector_floor<mode>2"
332 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
333 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
335 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
338 (define_expand "vector_btrunc<mode>2"
339 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
340 (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
341 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
344 (define_expand "vector_copysign<mode>3"
345 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
346 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
347 (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
348 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
351 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
353 emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
360 ;; Vector comparisons
361 (define_expand "vcond<mode>"
362 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
364 (match_operator 3 "comparison_operator"
365 [(match_operand:VEC_F 4 "vfloat_operand" "")
366 (match_operand:VEC_F 5 "vfloat_operand" "")])
367 (match_operand:VEC_F 1 "vfloat_operand" "")
368 (match_operand:VEC_F 2 "vfloat_operand" "")))]
369 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
372 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
373 operands[3], operands[4], operands[5]))
379 (define_expand "vcond<mode>"
380 [(set (match_operand:VEC_I 0 "vint_operand" "")
382 (match_operator 3 "comparison_operator"
383 [(match_operand:VEC_I 4 "vint_operand" "")
384 (match_operand:VEC_I 5 "vint_operand" "")])
385 (match_operand:VEC_I 1 "vint_operand" "")
386 (match_operand:VEC_I 2 "vint_operand" "")))]
387 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
390 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
391 operands[3], operands[4], operands[5]))
397 (define_expand "vcondu<mode>"
398 [(set (match_operand:VEC_I 0 "vint_operand" "")
400 (match_operator 3 "comparison_operator"
401 [(match_operand:VEC_I 4 "vint_operand" "")
402 (match_operand:VEC_I 5 "vint_operand" "")])
403 (match_operand:VEC_I 1 "vint_operand" "")
404 (match_operand:VEC_I 2 "vint_operand" "")))]
405 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
408 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
409 operands[3], operands[4], operands[5]))
415 (define_expand "vector_eq<mode>"
416 [(set (match_operand:VEC_C 0 "vlogical_operand" "")
417 (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
418 (match_operand:VEC_C 2 "vlogical_operand" "")))]
419 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
422 (define_expand "vector_gt<mode>"
423 [(set (match_operand:VEC_C 0 "vlogical_operand" "")
424 (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
425 (match_operand:VEC_C 2 "vlogical_operand" "")))]
426 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
429 (define_expand "vector_ge<mode>"
430 [(set (match_operand:VEC_C 0 "vlogical_operand" "")
431 (ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
432 (match_operand:VEC_C 2 "vlogical_operand" "")))]
433 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
436 (define_expand "vector_gtu<mode>"
437 [(set (match_operand:VEC_I 0 "vint_operand" "")
438 (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
439 (match_operand:VEC_I 2 "vint_operand" "")))]
440 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
443 (define_expand "vector_geu<mode>"
444 [(set (match_operand:VEC_I 0 "vint_operand" "")
445 (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
446 (match_operand:VEC_I 2 "vint_operand" "")))]
447 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
450 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
451 ;; which is in the reverse order that we want
452 (define_expand "vector_select_<mode>"
453 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
455 (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
457 (match_operand:VEC_L 2 "vlogical_operand" "")
458 (match_operand:VEC_L 1 "vlogical_operand" "")))]
459 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
462 (define_expand "vector_select_<mode>_uns"
463 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
465 (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
467 (match_operand:VEC_L 2 "vlogical_operand" "")
468 (match_operand:VEC_L 1 "vlogical_operand" "")))]
469 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
472 ;; Expansions that compare vectors producing a vector result and a predicate,
473 ;; setting CR6 to indicate a combined status
474 (define_expand "vector_eq_<mode>_p"
477 (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
478 (match_operand:VEC_A 2 "vlogical_operand" ""))]
480 (set (match_operand:VEC_A 0 "vlogical_operand" "")
481 (eq:VEC_A (match_dup 1)
483 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
486 (define_expand "vector_gt_<mode>_p"
489 (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
490 (match_operand:VEC_A 2 "vlogical_operand" ""))]
492 (set (match_operand:VEC_A 0 "vlogical_operand" "")
493 (gt:VEC_A (match_dup 1)
495 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
498 (define_expand "vector_ge_<mode>_p"
501 (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
502 (match_operand:VEC_F 2 "vfloat_operand" ""))]
504 (set (match_operand:VEC_F 0 "vfloat_operand" "")
505 (ge:VEC_F (match_dup 1)
507 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
510 (define_expand "vector_gtu_<mode>_p"
513 (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
514 (match_operand:VEC_I 2 "vint_operand" ""))]
516 (set (match_operand:VEC_I 0 "vlogical_operand" "")
517 (gtu:VEC_I (match_dup 1)
519 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
522 ;; AltiVec/VSX predicates.
524 (define_expand "cr6_test_for_zero"
525 [(set (match_operand:SI 0 "register_operand" "=r")
528 "TARGET_ALTIVEC || TARGET_VSX"
531 (define_expand "cr6_test_for_zero_reverse"
532 [(set (match_operand:SI 0 "register_operand" "=r")
535 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
536 "TARGET_ALTIVEC || TARGET_VSX"
539 (define_expand "cr6_test_for_lt"
540 [(set (match_operand:SI 0 "register_operand" "=r")
543 "TARGET_ALTIVEC || TARGET_VSX"
546 (define_expand "cr6_test_for_lt_reverse"
547 [(set (match_operand:SI 0 "register_operand" "=r")
550 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
551 "TARGET_ALTIVEC || TARGET_VSX"
555 ;; Vector logical instructions
556 (define_expand "xor<mode>3"
557 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
558 (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
559 (match_operand:VEC_L 2 "vlogical_operand" "")))]
560 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
563 (define_expand "ior<mode>3"
564 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
565 (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
566 (match_operand:VEC_L 2 "vlogical_operand" "")))]
567 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
570 (define_expand "and<mode>3"
571 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
572 (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
573 (match_operand:VEC_L 2 "vlogical_operand" "")))]
574 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
577 (define_expand "one_cmpl<mode>2"
578 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
579 (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
580 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
583 (define_expand "nor<mode>3"
584 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
585 (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
586 (match_operand:VEC_L 2 "vlogical_operand" ""))))]
587 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
590 (define_expand "andc<mode>3"
591 [(set (match_operand:VEC_L 0 "vlogical_operand" "")
592 (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))
593 (match_operand:VEC_L 1 "vlogical_operand" "")))]
594 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
597 ;; Same size conversions
598 (define_expand "float<VEC_int><mode>2"
599 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
600 (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
601 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
604 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
606 emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
611 (define_expand "unsigned_float<VEC_int><mode>2"
612 [(set (match_operand:VEC_F 0 "vfloat_operand" "")
613 (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
614 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
617 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
619 emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
624 (define_expand "fix_trunc<mode><VEC_int>2"
625 [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
626 (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
627 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
630 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
632 emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
637 (define_expand "fixuns_trunc<mode><VEC_int>2"
638 [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
639 (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
640 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
643 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
645 emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
651 ;; Vector initialization, set, extract
652 (define_expand "vec_init<mode>"
653 [(match_operand:VEC_E 0 "vlogical_operand" "")
654 (match_operand:VEC_E 1 "" "")]
655 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
657 rs6000_expand_vector_init (operands[0], operands[1]);
661 (define_expand "vec_set<mode>"
662 [(match_operand:VEC_E 0 "vlogical_operand" "")
663 (match_operand:<VEC_base> 1 "register_operand" "")
664 (match_operand 2 "const_int_operand" "")]
665 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
667 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
671 (define_expand "vec_extract<mode>"
672 [(match_operand:<VEC_base> 0 "register_operand" "")
673 (match_operand:VEC_E 1 "vlogical_operand" "")
674 (match_operand 2 "const_int_operand" "")]
675 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
677 rs6000_expand_vector_extract (operands[0], operands[1],
678 INTVAL (operands[2]));
682 ;; Interleave patterns
683 (define_expand "vec_interleave_highv4sf"
684 [(set (match_operand:V4SF 0 "vfloat_operand" "")
686 (vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
687 (parallel [(const_int 0)
691 (vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
692 (parallel [(const_int 2)
697 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
700 (define_expand "vec_interleave_lowv4sf"
701 [(set (match_operand:V4SF 0 "vfloat_operand" "")
703 (vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
704 (parallel [(const_int 2)
708 (vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
709 (parallel [(const_int 0)
714 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
717 (define_expand "vec_interleave_high<mode>"
718 [(set (match_operand:VEC_64 0 "vfloat_operand" "")
720 (vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
721 (parallel [(const_int 0)]))
722 (vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
723 (parallel [(const_int 0)]))))]
724 "VECTOR_UNIT_VSX_P (<MODE>mode)"
727 (define_expand "vec_interleave_low<mode>"
728 [(set (match_operand:VEC_64 0 "vfloat_operand" "")
730 (vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
731 (parallel [(const_int 1)]))
732 (vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
733 (parallel [(const_int 1)]))))]
734 "VECTOR_UNIT_VSX_P (<MODE>mode)"
738 ;; Convert double word types to single word types
739 (define_expand "vec_pack_trunc_v2df"
740 [(match_operand:V4SF 0 "vfloat_operand" "")
741 (match_operand:V2DF 1 "vfloat_operand" "")
742 (match_operand:V2DF 2 "vfloat_operand" "")]
743 "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
745 rtx r1 = gen_reg_rtx (V4SFmode);
746 rtx r2 = gen_reg_rtx (V4SFmode);
748 emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
749 emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
750 emit_insn (gen_vec_extract_evenv4sf (operands[0], r1, r2));
754 (define_expand "vec_pack_sfix_trunc_v2df"
755 [(match_operand:V4SI 0 "vint_operand" "")
756 (match_operand:V2DF 1 "vfloat_operand" "")
757 (match_operand:V2DF 2 "vfloat_operand" "")]
758 "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
760 rtx r1 = gen_reg_rtx (V4SImode);
761 rtx r2 = gen_reg_rtx (V4SImode);
763 emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
764 emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
765 emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
769 (define_expand "vec_pack_ufix_trunc_v2df"
770 [(match_operand:V4SI 0 "vint_operand" "")
771 (match_operand:V2DF 1 "vfloat_operand" "")
772 (match_operand:V2DF 2 "vfloat_operand" "")]
773 "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
775 rtx r1 = gen_reg_rtx (V4SImode);
776 rtx r2 = gen_reg_rtx (V4SImode);
778 emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
779 emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
780 emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
784 ;; Convert single word types to double word
785 (define_expand "vec_unpacks_hi_v4sf"
786 [(match_operand:V2DF 0 "vfloat_operand" "")
787 (match_operand:V4SF 1 "vfloat_operand" "")]
788 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
790 rtx reg = gen_reg_rtx (V4SFmode);
792 emit_insn (gen_vec_interleave_highv4sf (reg, operands[1], operands[1]));
793 emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
797 (define_expand "vec_unpacks_lo_v4sf"
798 [(match_operand:V2DF 0 "vfloat_operand" "")
799 (match_operand:V4SF 1 "vfloat_operand" "")]
800 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
802 rtx reg = gen_reg_rtx (V4SFmode);
804 emit_insn (gen_vec_interleave_lowv4sf (reg, operands[1], operands[1]));
805 emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
809 (define_expand "vec_unpacks_float_hi_v4si"
810 [(match_operand:V2DF 0 "vfloat_operand" "")
811 (match_operand:V4SI 1 "vint_operand" "")]
812 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
814 rtx reg = gen_reg_rtx (V4SImode);
816 emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
817 emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
821 (define_expand "vec_unpacks_float_lo_v4si"
822 [(match_operand:V2DF 0 "vfloat_operand" "")
823 (match_operand:V4SI 1 "vint_operand" "")]
824 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
826 rtx reg = gen_reg_rtx (V4SImode);
828 emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
829 emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
833 (define_expand "vec_unpacku_float_hi_v4si"
834 [(match_operand:V2DF 0 "vfloat_operand" "")
835 (match_operand:V4SI 1 "vint_operand" "")]
836 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
838 rtx reg = gen_reg_rtx (V4SImode);
840 emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
841 emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
845 (define_expand "vec_unpacku_float_lo_v4si"
846 [(match_operand:V2DF 0 "vfloat_operand" "")
847 (match_operand:V4SI 1 "vint_operand" "")]
848 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
850 rtx reg = gen_reg_rtx (V4SImode);
852 emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
853 emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
858 ;; Align vector loads with a permute.
859 (define_expand "vec_realign_load_<mode>"
860 [(match_operand:VEC_K 0 "vlogical_operand" "")
861 (match_operand:VEC_K 1 "vlogical_operand" "")
862 (match_operand:VEC_K 2 "vlogical_operand" "")
863 (match_operand:V16QI 3 "vlogical_operand" "")]
864 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
866 emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2],
871 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
872 ;; since the load already handles it.
873 (define_expand "movmisalign<mode>"
874 [(set (match_operand:VEC_N 0 "vfloat_operand" "")
875 (match_operand:VEC_N 1 "vfloat_operand" ""))]
876 "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
880 ;; Vector shift left in bits. Currently supported ony for shift
881 ;; amounts that can be expressed as byte shifts (divisible by 8).
882 ;; General shift amounts can be supported using vslo + vsl. We're
883 ;; not expecting to see these yet (the vectorizer currently
884 ;; generates only shifts divisible by byte_size).
885 (define_expand "vec_shl_<mode>"
886 [(match_operand:VEC_L 0 "vlogical_operand" "")
887 (match_operand:VEC_L 1 "vlogical_operand" "")
888 (match_operand:QI 2 "reg_or_short_operand" "")]
892 rtx bitshift = operands[2];
895 HOST_WIDE_INT bitshift_val;
896 HOST_WIDE_INT byteshift_val;
898 if (! CONSTANT_P (bitshift))
900 bitshift_val = INTVAL (bitshift);
901 if (bitshift_val & 0x7)
903 byteshift_val = bitshift_val >> 3;
904 if (TARGET_VSX && (byteshift_val & 0x3) == 0)
906 shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
907 insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
912 shift = gen_rtx_CONST_INT (QImode, byteshift_val);
913 insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
921 ;; Vector shift right in bits. Currently supported ony for shift
922 ;; amounts that can be expressed as byte shifts (divisible by 8).
923 ;; General shift amounts can be supported using vsro + vsr. We're
924 ;; not expecting to see these yet (the vectorizer currently
925 ;; generates only shifts divisible by byte_size).
926 (define_expand "vec_shr_<mode>"
927 [(match_operand:VEC_L 0 "vlogical_operand" "")
928 (match_operand:VEC_L 1 "vlogical_operand" "")
929 (match_operand:QI 2 "reg_or_short_operand" "")]
933 rtx bitshift = operands[2];
936 HOST_WIDE_INT bitshift_val;
937 HOST_WIDE_INT byteshift_val;
939 if (! CONSTANT_P (bitshift))
941 bitshift_val = INTVAL (bitshift);
942 if (bitshift_val & 0x7)
944 byteshift_val = 16 - (bitshift_val >> 3);
945 if (TARGET_VSX && (byteshift_val & 0x3) == 0)
947 shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
948 insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
953 shift = gen_rtx_CONST_INT (QImode, byteshift_val);
954 insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
962 ;; Expanders for rotate each element in a vector
963 (define_expand "vrotl<mode>3"
964 [(set (match_operand:VEC_I 0 "vint_operand" "")
965 (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
966 (match_operand:VEC_I 2 "vint_operand" "")))]
970 ;; Expanders for arithmetic shift left on each vector element
971 (define_expand "vashl<mode>3"
972 [(set (match_operand:VEC_I 0 "vint_operand" "")
973 (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
974 (match_operand:VEC_I 2 "vint_operand" "")))]
978 ;; Expanders for logical shift right on each vector element
979 (define_expand "vlshr<mode>3"
980 [(set (match_operand:VEC_I 0 "vint_operand" "")
981 (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
982 (match_operand:VEC_I 2 "vint_operand" "")))]
986 ;; Expanders for arithmetic shift right on each vector element
987 (define_expand "vashr<mode>3"
988 [(set (match_operand:VEC_I 0 "vint_operand" "")
989 (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
990 (match_operand:VEC_I 2 "vint_operand" "")))]
994 ;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
996 (define_expand "absv2sf2"
997 [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
998 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
999 "TARGET_PAIRED_FLOAT || TARGET_SPE"
1002 (define_expand "negv2sf2"
1003 [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1004 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1005 "TARGET_PAIRED_FLOAT || TARGET_SPE"
1008 (define_expand "addv2sf3"
1009 [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1010 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1011 (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1012 "TARGET_PAIRED_FLOAT || TARGET_SPE"
1017 /* We need to make a note that we clobber SPEFSCR. */
1018 rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1020 XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1021 gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
1022 XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1028 (define_expand "subv2sf3"
1029 [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1030 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1031 (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1032 "TARGET_PAIRED_FLOAT || TARGET_SPE"
1037 /* We need to make a note that we clobber SPEFSCR. */
1038 rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1040 XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1041 gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
1042 XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1048 (define_expand "mulv2sf3"
1049 [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1050 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1051 (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1052 "TARGET_PAIRED_FLOAT || TARGET_SPE"
1057 /* We need to make a note that we clobber SPEFSCR. */
1058 rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1060 XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1061 gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
1062 XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1068 (define_expand "divv2sf3"
1069 [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1070 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1071 (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1072 "TARGET_PAIRED_FLOAT || TARGET_SPE"
1077 /* We need to make a note that we clobber SPEFSCR. */
1078 rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1080 XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1081 gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
1082 XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));