1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
29 #include "stor-layout.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "insn-codes.h"
49 #include "diagnostic-core.h"
51 #include "tm-constrs.h"
57 #include "cfgcleanup.h"
63 /* This file should be included last. */
64 #include "target-def.h"
66 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
67 names are not prefixed by underscores, to tell whether to prefix a
68 label with a plus sign or not, so that the assembler can tell
69 symbol names from register names. */
70 int mn10300_protect_label
;
72 /* Selected processor type for tuning. */
73 enum processor_type mn10300_tune_cpu
= PROCESSOR_DEFAULT
;
80 static int cc_flags_for_mode(machine_mode
);
81 static int cc_flags_for_code(enum rtx_code
);
83 /* Implement TARGET_OPTION_OVERRIDE. */
85 mn10300_option_override (void)
88 target_flags
&= ~MASK_MULT_BUG
;
91 /* Disable scheduling for the MN10300 as we do
92 not have timing information available for it. */
93 flag_schedule_insns
= 0;
94 flag_schedule_insns_after_reload
= 0;
96 /* Force enable splitting of wide types, as otherwise it is trivial
97 to run out of registers. Indeed, this works so well that register
98 allocation problems are now more common *without* optimization,
99 when this flag is not enabled by default. */
100 flag_split_wide_types
= 1;
103 if (mn10300_tune_string
)
105 if (strcasecmp (mn10300_tune_string
, "mn10300") == 0)
106 mn10300_tune_cpu
= PROCESSOR_MN10300
;
107 else if (strcasecmp (mn10300_tune_string
, "am33") == 0)
108 mn10300_tune_cpu
= PROCESSOR_AM33
;
109 else if (strcasecmp (mn10300_tune_string
, "am33-2") == 0)
110 mn10300_tune_cpu
= PROCESSOR_AM33_2
;
111 else if (strcasecmp (mn10300_tune_string
, "am34") == 0)
112 mn10300_tune_cpu
= PROCESSOR_AM34
;
114 error ("-mtune= expects mn10300, am33, am33-2, or am34");
119 mn10300_file_start (void)
121 default_file_start ();
124 fprintf (asm_out_file
, "\t.am33_2\n");
125 else if (TARGET_AM33
)
126 fprintf (asm_out_file
, "\t.am33\n");
129 /* Note: This list must match the liw_op attribute in mn10300.md. */
131 static const char *liw_op_names
[] =
133 "add", "cmp", "sub", "mov",
139 /* Print operand X using operand code CODE to assembly language output file
143 mn10300_print_operand (FILE *file
, rtx x
, int code
)
149 unsigned int liw_op
= UINTVAL (x
);
151 gcc_assert (TARGET_ALLOW_LIW
);
152 gcc_assert (liw_op
< LIW_OP_MAX
);
153 fputs (liw_op_names
[liw_op
], file
);
160 enum rtx_code cmp
= GET_CODE (x
);
161 machine_mode mode
= GET_MODE (XEXP (x
, 0));
166 cmp
= reverse_condition (cmp
);
167 have_flags
= cc_flags_for_mode (mode
);
178 /* bge is smaller than bnc. */
179 str
= (have_flags
& CC_FLAG_V
? "ge" : "nc");
182 str
= (have_flags
& CC_FLAG_V
? "lt" : "ns");
230 gcc_checking_assert ((cc_flags_for_code (cmp
) & ~have_flags
) == 0);
236 /* This is used for the operand to a call instruction;
237 if it's a REG, enclose it in parens, else output
238 the operand normally. */
242 mn10300_print_operand (file
, x
, 0);
246 mn10300_print_operand (file
, x
, 0);
250 switch (GET_CODE (x
))
254 output_address (XEXP (x
, 0));
259 fprintf (file
, "fd%d", REGNO (x
) - 18);
267 /* These are the least significant word in a 64bit value. */
269 switch (GET_CODE (x
))
273 output_address (XEXP (x
, 0));
278 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
282 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
290 switch (GET_MODE (x
))
293 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
294 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
295 fprintf (file
, "0x%lx", val
[0]);
298 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
299 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
[0]);
300 fprintf (file
, "0x%lx", val
[0]);
304 mn10300_print_operand_address (file
,
305 GEN_INT (CONST_DOUBLE_LOW (x
)));
316 split_double (x
, &low
, &high
);
317 fprintf (file
, "%ld", (long)INTVAL (low
));
326 /* Similarly, but for the most significant word. */
328 switch (GET_CODE (x
))
332 x
= adjust_address (x
, SImode
, 4);
333 output_address (XEXP (x
, 0));
338 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
342 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
350 switch (GET_MODE (x
))
353 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
354 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
355 fprintf (file
, "0x%lx", val
[1]);
361 mn10300_print_operand_address (file
,
362 GEN_INT (CONST_DOUBLE_HIGH (x
)));
373 split_double (x
, &low
, &high
);
374 fprintf (file
, "%ld", (long)INTVAL (high
));
385 if (REG_P (XEXP (x
, 0)))
386 output_address (gen_rtx_PLUS (SImode
, XEXP (x
, 0), const0_rtx
));
388 output_address (XEXP (x
, 0));
393 gcc_assert (INTVAL (x
) >= -128 && INTVAL (x
) <= 255);
394 fprintf (file
, "%d", (int)((~INTVAL (x
)) & 0xff));
398 gcc_assert (INTVAL (x
) >= -128 && INTVAL (x
) <= 255);
399 fprintf (file
, "%d", (int)(INTVAL (x
) & 0xff));
402 /* For shift counts. The hardware ignores the upper bits of
403 any immediate, but the assembler will flag an out of range
404 shift count as an error. So we mask off the high bits
405 of the immediate here. */
409 fprintf (file
, "%d", (int)(INTVAL (x
) & 0x1f));
415 switch (GET_CODE (x
))
419 output_address (XEXP (x
, 0));
428 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
432 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
435 /* This will only be single precision.... */
441 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
442 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
443 fprintf (file
, "0x%lx", val
);
453 mn10300_print_operand_address (file
, x
);
462 /* Output assembly language output for the address ADDR to FILE. */
465 mn10300_print_operand_address (FILE *file
, rtx addr
)
467 switch (GET_CODE (addr
))
470 mn10300_print_operand (file
, XEXP (addr
, 0), 0);
475 mn10300_print_operand (file
, XEXP (addr
, 0), 0);
478 mn10300_print_operand (file
, XEXP (addr
, 1), 0);
482 mn10300_print_operand (file
, addr
, 0);
486 rtx base
= XEXP (addr
, 0);
487 rtx index
= XEXP (addr
, 1);
489 if (REG_P (index
) && !REG_OK_FOR_INDEX_P (index
))
495 gcc_assert (REG_P (index
) && REG_OK_FOR_INDEX_P (index
));
497 gcc_assert (REG_OK_FOR_BASE_P (base
));
499 mn10300_print_operand (file
, index
, 0);
501 mn10300_print_operand (file
, base
, 0);
505 output_addr_const (file
, addr
);
508 output_addr_const (file
, addr
);
513 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
515 Used for PIC-specific UNSPECs. */
518 mn10300_asm_output_addr_const_extra (FILE *file
, rtx x
)
520 if (GET_CODE (x
) == UNSPEC
)
525 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
526 output_addr_const (file
, XVECEXP (x
, 0, 0));
529 output_addr_const (file
, XVECEXP (x
, 0, 0));
530 fputs ("@GOT", file
);
533 output_addr_const (file
, XVECEXP (x
, 0, 0));
534 fputs ("@GOTOFF", file
);
537 output_addr_const (file
, XVECEXP (x
, 0, 0));
538 fputs ("@PLT", file
);
540 case UNSPEC_GOTSYM_OFF
:
541 assemble_name (file
, GOT_SYMBOL_NAME
);
543 output_addr_const (file
, XVECEXP (x
, 0, 0));
555 /* Count the number of FP registers that have to be saved. */
557 fp_regs_to_save (void)
564 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
565 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
571 /* Print a set of registers in the format required by "movm" and "ret".
572 Register K is saved if bit K of MASK is set. The data and address
573 registers can be stored individually, but the extended registers cannot.
574 We assume that the mask already takes that into account. For instance,
575 bits 14 to 17 must have the same value. */
578 mn10300_print_reg_list (FILE *file
, int mask
)
586 for (i
= 0; i
< FIRST_EXTENDED_REGNUM
; i
++)
587 if ((mask
& (1 << i
)) != 0)
591 fputs (reg_names
[i
], file
);
595 if ((mask
& 0x3c000) != 0)
597 gcc_assert ((mask
& 0x3c000) == 0x3c000);
600 fputs ("exreg1", file
);
607 /* If the MDR register is never clobbered, we can use the RETF instruction
608 which takes the address from the MDR register. This is 3 cycles faster
609 than having to load the address from the stack. */
612 mn10300_can_use_retf_insn (void)
614 /* Don't bother if we're not optimizing. In this case we won't
615 have proper access to df_regs_ever_live_p. */
619 /* EH returns alter the saved return address; MDR is not current. */
620 if (crtl
->calls_eh_return
)
623 /* Obviously not if MDR is ever clobbered. */
624 if (df_regs_ever_live_p (MDR_REG
))
627 /* ??? Careful not to use this during expand_epilogue etc. */
628 gcc_assert (!in_sequence_p ());
629 return leaf_function_p ();
633 mn10300_can_use_rets_insn (void)
635 return !mn10300_initial_offset (ARG_POINTER_REGNUM
, STACK_POINTER_REGNUM
);
638 /* Returns the set of live, callee-saved registers as a bitmask. The
639 callee-saved extended registers cannot be stored individually, so
640 all of them will be included in the mask if any one of them is used.
641 Also returns the number of bytes in the registers in the mask if
642 BYTES_SAVED is not NULL. */
645 mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved
)
652 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
653 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
659 if ((mask
& 0x3c000) != 0)
661 for (i
= 0x04000; i
< 0x40000; i
<<= 1)
669 * bytes_saved
= count
* UNITS_PER_WORD
;
677 RTX_FRAME_RELATED_P (r
) = 1;
681 /* Generate an instruction that pushes several registers onto the stack.
682 Register K will be saved if bit K in MASK is set. The function does
683 nothing if MASK is zero.
685 To be compatible with the "movm" instruction, the lowest-numbered
686 register must be stored in the lowest slot. If MASK is the set
687 { R1,...,RN }, where R1...RN are ordered least first, the generated
688 instruction will have the form:
691 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
692 (set (mem:SI (plus:SI (reg:SI 9)
696 (set (mem:SI (plus:SI (reg:SI 9)
701 mn10300_gen_multiple_store (unsigned int mask
)
703 /* The order in which registers are stored, from SP-4 through SP-N*4. */
704 static const unsigned int store_order
[8] = {
705 /* e2, e3: never saved */
706 FIRST_EXTENDED_REGNUM
+ 4,
707 FIRST_EXTENDED_REGNUM
+ 5,
708 FIRST_EXTENDED_REGNUM
+ 6,
709 FIRST_EXTENDED_REGNUM
+ 7,
710 /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
711 FIRST_DATA_REGNUM
+ 2,
712 FIRST_DATA_REGNUM
+ 3,
713 FIRST_ADDRESS_REGNUM
+ 2,
714 FIRST_ADDRESS_REGNUM
+ 3,
715 /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
725 for (i
= count
= 0; i
< ARRAY_SIZE(store_order
); ++i
)
727 unsigned regno
= store_order
[i
];
729 if (((mask
>> regno
) & 1) == 0)
733 x
= plus_constant (Pmode
, stack_pointer_rtx
, count
* -4);
734 x
= gen_frame_mem (SImode
, x
);
735 x
= gen_rtx_SET (x
, gen_rtx_REG (SImode
, regno
));
738 /* Remove the register from the mask so that... */
739 mask
&= ~(1u << regno
);
742 /* ... we can make sure that we didn't try to use a register
743 not listed in the store order. */
744 gcc_assert (mask
== 0);
746 /* Create the instruction that updates the stack pointer. */
747 x
= plus_constant (Pmode
, stack_pointer_rtx
, count
* -4);
748 x
= gen_rtx_SET (stack_pointer_rtx
, x
);
751 /* We need one PARALLEL element to update the stack pointer and
752 an additional element for each register that is stored. */
753 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (count
+ 1, elts
));
757 static inline unsigned int
758 popcount (unsigned int mask
)
760 unsigned int count
= 0;
765 mask
&= ~ (mask
& - mask
);
771 mn10300_expand_prologue (void)
773 HOST_WIDE_INT size
= mn10300_frame_size ();
776 mask
= mn10300_get_live_callee_saved_regs (NULL
);
777 /* If we use any of the callee-saved registers, save them now. */
778 mn10300_gen_multiple_store (mask
);
780 if (flag_stack_usage_info
)
781 current_function_static_stack_size
= size
+ popcount (mask
) * 4;
783 if (TARGET_AM33_2
&& fp_regs_to_save ())
785 int num_regs_to_save
= fp_regs_to_save (), i
;
791 save_sp_partial_merge
,
795 unsigned int strategy_size
= (unsigned)-1, this_strategy_size
;
798 if (flag_stack_usage_info
)
799 current_function_static_stack_size
+= num_regs_to_save
* 4;
801 /* We have several different strategies to save FP registers.
802 We can store them using SP offsets, which is beneficial if
803 there are just a few registers to save, or we can use `a0' in
804 post-increment mode (`a0' is the only call-clobbered address
805 register that is never used to pass information to a
806 function). Furthermore, if we don't need a frame pointer, we
807 can merge the two SP adds into a single one, but this isn't
808 always beneficial; sometimes we can just split the two adds
809 so that we don't exceed a 16-bit constant size. The code
810 below will select which strategy to use, so as to generate
811 smallest code. Ties are broken in favor or shorter sequences
812 (in terms of number of instructions). */
814 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
815 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
816 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
817 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
819 /* We add 0 * (S) in two places to promote to the type of S,
820 so that all arms of the conditional have the same type. */
821 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
822 (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
823 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
824 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
826 #define SIZE_FMOV_SP_(S,N) \
827 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
828 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
829 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
830 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
832 /* Consider alternative save_sp_merge only if we don't need the
833 frame pointer and size is nonzero. */
834 if (! frame_pointer_needed
&& size
)
836 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
837 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
838 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
839 this_strategy_size
+= SIZE_FMOV_SP (size
, num_regs_to_save
);
841 if (this_strategy_size
< strategy_size
)
843 strategy
= save_sp_merge
;
844 strategy_size
= this_strategy_size
;
848 /* Consider alternative save_sp_no_merge unconditionally. */
849 /* Insn: add -4 * num_regs_to_save, sp. */
850 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
851 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
852 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
855 /* Insn: add -size, sp. */
856 this_strategy_size
+= SIZE_ADD_SP (-size
);
859 if (this_strategy_size
< strategy_size
)
861 strategy
= save_sp_no_merge
;
862 strategy_size
= this_strategy_size
;
865 /* Consider alternative save_sp_partial_merge only if we don't
866 need a frame pointer and size is reasonably large. */
867 if (! frame_pointer_needed
&& size
+ 4 * num_regs_to_save
> 128)
869 /* Insn: add -128, sp. */
870 this_strategy_size
= SIZE_ADD_SP (-128);
871 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
872 this_strategy_size
+= SIZE_FMOV_SP (128 - 4 * num_regs_to_save
,
876 /* Insn: add 128-size, sp. */
877 this_strategy_size
+= SIZE_ADD_SP (128 - size
);
880 if (this_strategy_size
< strategy_size
)
882 strategy
= save_sp_partial_merge
;
883 strategy_size
= this_strategy_size
;
887 /* Consider alternative save_a0_merge only if we don't need a
888 frame pointer, size is nonzero and the user hasn't
889 changed the calling conventions of a0. */
890 if (! frame_pointer_needed
&& size
891 && call_really_used_regs
[FIRST_ADDRESS_REGNUM
]
892 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
894 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
895 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
896 /* Insn: mov sp, a0. */
897 this_strategy_size
++;
900 /* Insn: add size, a0. */
901 this_strategy_size
+= SIZE_ADD_AX (size
);
903 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
904 this_strategy_size
+= 3 * num_regs_to_save
;
906 if (this_strategy_size
< strategy_size
)
908 strategy
= save_a0_merge
;
909 strategy_size
= this_strategy_size
;
913 /* Consider alternative save_a0_no_merge if the user hasn't
914 changed the calling conventions of a0. */
915 if (call_really_used_regs
[FIRST_ADDRESS_REGNUM
]
916 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
918 /* Insn: add -4 * num_regs_to_save, sp. */
919 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
920 /* Insn: mov sp, a0. */
921 this_strategy_size
++;
922 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
923 this_strategy_size
+= 3 * num_regs_to_save
;
926 /* Insn: add -size, sp. */
927 this_strategy_size
+= SIZE_ADD_SP (-size
);
930 if (this_strategy_size
< strategy_size
)
932 strategy
= save_a0_no_merge
;
933 strategy_size
= this_strategy_size
;
937 /* Emit the initial SP add, common to all strategies. */
940 case save_sp_no_merge
:
941 case save_a0_no_merge
:
942 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
944 GEN_INT (-4 * num_regs_to_save
))));
948 case save_sp_partial_merge
:
949 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
952 xsize
= 128 - 4 * num_regs_to_save
;
958 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
960 GEN_INT (-(size
+ 4 * num_regs_to_save
)))));
961 /* We'll have to adjust FP register saves according to the
964 /* Since we've already created the stack frame, don't do it
965 again at the end of the function. */
973 /* Now prepare register a0, if we have decided to use it. */
977 case save_sp_no_merge
:
978 case save_sp_partial_merge
:
983 case save_a0_no_merge
:
984 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
);
985 F (emit_insn (gen_movsi (reg
, stack_pointer_rtx
)));
987 F (emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (xsize
))));
988 reg
= gen_rtx_POST_INC (SImode
, reg
);
995 /* Now actually save the FP registers. */
996 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
997 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
1005 /* If we aren't using `a0', use an SP offset. */
1008 addr
= gen_rtx_PLUS (SImode
,
1013 addr
= stack_pointer_rtx
;
1018 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode
, addr
),
1019 gen_rtx_REG (SFmode
, i
))));
1023 /* Now put the frame pointer into the frame pointer register. */
1024 if (frame_pointer_needed
)
1025 F (emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
));
1027 /* Allocate stack for this frame. */
1029 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1033 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
1034 emit_insn (gen_load_pic ());
1038 mn10300_expand_epilogue (void)
1040 HOST_WIDE_INT size
= mn10300_frame_size ();
1041 unsigned int reg_save_bytes
;
1043 mn10300_get_live_callee_saved_regs (& reg_save_bytes
);
1045 if (TARGET_AM33_2
&& fp_regs_to_save ())
1047 int num_regs_to_save
= fp_regs_to_save (), i
;
1050 /* We have several options to restore FP registers. We could
1051 load them from SP offsets, but, if there are enough FP
1052 registers to restore, we win if we use a post-increment
1055 /* If we have a frame pointer, it's the best option, because we
1056 already know it has the value we want. */
1057 if (frame_pointer_needed
)
1058 reg
= gen_rtx_REG (SImode
, FRAME_POINTER_REGNUM
);
1059 /* Otherwise, we may use `a1', since it's call-clobbered and
1060 it's never used for return values. But only do so if it's
1061 smaller than using SP offsets. */
1064 enum { restore_sp_post_adjust
,
1065 restore_sp_pre_adjust
,
1066 restore_sp_partial_adjust
,
1067 restore_a1
} strategy
;
1068 unsigned int this_strategy_size
, strategy_size
= (unsigned)-1;
1070 /* Consider using sp offsets before adjusting sp. */
1071 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1072 this_strategy_size
= SIZE_FMOV_SP (size
, num_regs_to_save
);
1073 /* If size is too large, we'll have to adjust SP with an
1075 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1077 /* Insn: add size + 4 * num_regs_to_save, sp. */
1078 this_strategy_size
+= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
);
1080 /* If we don't have to restore any non-FP registers,
1081 we'll be able to save one byte by using rets. */
1082 if (! reg_save_bytes
)
1083 this_strategy_size
--;
1085 if (this_strategy_size
< strategy_size
)
1087 strategy
= restore_sp_post_adjust
;
1088 strategy_size
= this_strategy_size
;
1091 /* Consider using sp offsets after adjusting sp. */
1092 /* Insn: add size, sp. */
1093 this_strategy_size
= SIZE_ADD_SP (size
);
1094 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1095 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
1096 /* We're going to use ret to release the FP registers
1097 save area, so, no savings. */
1099 if (this_strategy_size
< strategy_size
)
1101 strategy
= restore_sp_pre_adjust
;
1102 strategy_size
= this_strategy_size
;
1105 /* Consider using sp offsets after partially adjusting sp.
1106 When size is close to 32Kb, we may be able to adjust SP
1107 with an imm16 add instruction while still using fmov
1109 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1111 /* Insn: add size + 4 * num_regs_to_save
1112 + reg_save_bytes - 252,sp. */
1113 this_strategy_size
= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
1114 + (int) reg_save_bytes
- 252);
1115 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1116 this_strategy_size
+= SIZE_FMOV_SP (252 - reg_save_bytes
1117 - 4 * num_regs_to_save
,
1119 /* We're going to use ret to release the FP registers
1120 save area, so, no savings. */
1122 if (this_strategy_size
< strategy_size
)
1124 strategy
= restore_sp_partial_adjust
;
1125 strategy_size
= this_strategy_size
;
1129 /* Consider using a1 in post-increment mode, as long as the
1130 user hasn't changed the calling conventions of a1. */
1131 if (call_really_used_regs
[FIRST_ADDRESS_REGNUM
+ 1]
1132 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
+1])
1134 /* Insn: mov sp,a1. */
1135 this_strategy_size
= 1;
1138 /* Insn: add size,a1. */
1139 this_strategy_size
+= SIZE_ADD_AX (size
);
1141 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1142 this_strategy_size
+= 3 * num_regs_to_save
;
1143 /* If size is large enough, we may be able to save a
1145 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1147 /* Insn: mov a1,sp. */
1148 this_strategy_size
+= 2;
1150 /* If we don't have to restore any non-FP registers,
1151 we'll be able to save one byte by using rets. */
1152 if (! reg_save_bytes
)
1153 this_strategy_size
--;
1155 if (this_strategy_size
< strategy_size
)
1157 strategy
= restore_a1
;
1158 strategy_size
= this_strategy_size
;
1164 case restore_sp_post_adjust
:
1167 case restore_sp_pre_adjust
:
1168 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1174 case restore_sp_partial_adjust
:
1175 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1177 GEN_INT (size
+ 4 * num_regs_to_save
1178 + reg_save_bytes
- 252)));
1179 size
= 252 - reg_save_bytes
- 4 * num_regs_to_save
;
1183 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
+ 1);
1184 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
1186 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
1194 /* Adjust the selected register, if any, for post-increment. */
1196 reg
= gen_rtx_POST_INC (SImode
, reg
);
1198 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
1199 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
1207 /* If we aren't using a post-increment register, use an
1209 addr
= gen_rtx_PLUS (SImode
,
1214 addr
= stack_pointer_rtx
;
1218 emit_insn (gen_movsf (gen_rtx_REG (SFmode
, i
),
1219 gen_rtx_MEM (SFmode
, addr
)));
1222 /* If we were using the restore_a1 strategy and the number of
1223 bytes to be released won't fit in the `ret' byte, copy `a1'
1224 to `sp', to avoid having to use `add' to adjust it. */
1225 if (! frame_pointer_needed
&& reg
&& size
+ reg_save_bytes
> 255)
1227 emit_move_insn (stack_pointer_rtx
, XEXP (reg
, 0));
1232 /* Maybe cut back the stack, except for the register save area.
1234 If the frame pointer exists, then use the frame pointer to
1237 If the stack size + register save area is more than 255 bytes,
1238 then the stack must be cut back here since the size + register
1239 save size is too big for a ret/retf instruction.
1241 Else leave it alone, it will be cut back as part of the
1242 ret/retf instruction, or there wasn't any stack to begin with.
1244 Under no circumstances should the register save area be
1245 deallocated here, that would leave a window where an interrupt
1246 could occur and trash the register save area. */
1247 if (frame_pointer_needed
)
1249 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
1252 else if (size
+ reg_save_bytes
> 255)
1254 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1260 /* Adjust the stack and restore callee-saved registers, if any. */
1261 if (mn10300_can_use_rets_insn ())
1262 emit_jump_insn (ret_rtx
);
1264 emit_jump_insn (gen_return_ret (GEN_INT (size
+ reg_save_bytes
)));
1267 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1268 This function is for MATCH_PARALLEL and so assumes OP is known to be
1269 parallel. If OP is a multiple store, return a mask indicating which
1270 registers it saves. Return 0 otherwise. */
1273 mn10300_store_multiple_regs (rtx op
)
1281 count
= XVECLEN (op
, 0);
1285 /* Check that first instruction has the form (set (sp) (plus A B)) */
1286 elt
= XVECEXP (op
, 0, 0);
1287 if (GET_CODE (elt
) != SET
1288 || (! REG_P (SET_DEST (elt
)))
1289 || REGNO (SET_DEST (elt
)) != STACK_POINTER_REGNUM
1290 || GET_CODE (SET_SRC (elt
)) != PLUS
)
1293 /* Check that A is the stack pointer and B is the expected stack size.
1294 For OP to match, each subsequent instruction should push a word onto
1295 the stack. We therefore expect the first instruction to create
1296 COUNT-1 stack slots. */
1297 elt
= SET_SRC (elt
);
1298 if ((! REG_P (XEXP (elt
, 0)))
1299 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1300 || (! CONST_INT_P (XEXP (elt
, 1)))
1301 || INTVAL (XEXP (elt
, 1)) != -(count
- 1) * 4)
1305 for (i
= 1; i
< count
; i
++)
1307 /* Check that element i is a (set (mem M) R). */
1308 /* ??? Validate the register order a-la mn10300_gen_multiple_store.
1309 Remember: the ordering is *not* monotonic. */
1310 elt
= XVECEXP (op
, 0, i
);
1311 if (GET_CODE (elt
) != SET
1312 || (! MEM_P (SET_DEST (elt
)))
1313 || (! REG_P (SET_SRC (elt
))))
1316 /* Remember which registers are to be saved. */
1317 last
= REGNO (SET_SRC (elt
));
1318 mask
|= (1 << last
);
1320 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1321 elt
= XEXP (SET_DEST (elt
), 0);
1322 if (GET_CODE (elt
) != PLUS
1323 || (! REG_P (XEXP (elt
, 0)))
1324 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1325 || (! CONST_INT_P (XEXP (elt
, 1)))
1326 || INTVAL (XEXP (elt
, 1)) != -i
* 4)
1330 /* All or none of the callee-saved extended registers must be in the set. */
1331 if ((mask
& 0x3c000) != 0
1332 && (mask
& 0x3c000) != 0x3c000)
1338 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
1341 mn10300_preferred_reload_class (rtx x
, reg_class_t rclass
)
1343 if (x
== stack_pointer_rtx
&& rclass
!= SP_REGS
)
1344 return (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
1347 && !HARD_REGISTER_P (x
))
1348 || (GET_CODE (x
) == SUBREG
1349 && REG_P (SUBREG_REG (x
))
1350 && !HARD_REGISTER_P (SUBREG_REG (x
))))
1351 return LIMIT_RELOAD_CLASS (GET_MODE (x
), rclass
);
1356 /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
1359 mn10300_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1361 if (x
== stack_pointer_rtx
&& rclass
!= SP_REGS
)
1362 return (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
1366 /* Implement TARGET_SECONDARY_RELOAD. */
1369 mn10300_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
1370 machine_mode mode
, secondary_reload_info
*sri
)
1372 enum reg_class rclass
= (enum reg_class
) rclass_i
;
1373 enum reg_class xclass
= NO_REGS
;
1374 unsigned int xregno
= INVALID_REGNUM
;
1379 if (xregno
>= FIRST_PSEUDO_REGISTER
)
1380 xregno
= true_regnum (x
);
1381 if (xregno
!= INVALID_REGNUM
)
1382 xclass
= REGNO_REG_CLASS (xregno
);
1387 /* Memory load/stores less than a full word wide can't have an
1388 address or stack pointer destination. They must use a data
1389 register as an intermediate register. */
1390 if (rclass
!= DATA_REGS
1391 && (mode
== QImode
|| mode
== HImode
)
1392 && xclass
== NO_REGS
)
1395 /* We can only move SP to/from an address register. */
1397 && rclass
== SP_REGS
1398 && xclass
!= ADDRESS_REGS
)
1399 return ADDRESS_REGS
;
1401 && xclass
== SP_REGS
1402 && rclass
!= ADDRESS_REGS
1403 && rclass
!= SP_OR_ADDRESS_REGS
)
1404 return ADDRESS_REGS
;
1407 /* We can't directly load sp + const_int into a register;
1408 we must use an address register as an scratch. */
1410 && rclass
!= SP_REGS
1411 && rclass
!= SP_OR_ADDRESS_REGS
1412 && rclass
!= SP_OR_GENERAL_REGS
1413 && GET_CODE (x
) == PLUS
1414 && (XEXP (x
, 0) == stack_pointer_rtx
1415 || XEXP (x
, 1) == stack_pointer_rtx
))
1417 sri
->icode
= CODE_FOR_reload_plus_sp_const
;
1421 /* We can only move MDR to/from a data register. */
1422 if (rclass
== MDR_REGS
&& xclass
!= DATA_REGS
)
1424 if (xclass
== MDR_REGS
&& rclass
!= DATA_REGS
)
1427 /* We can't load/store an FP register from a constant address. */
1429 && (rclass
== FP_REGS
|| xclass
== FP_REGS
)
1430 && (xclass
== NO_REGS
|| rclass
== NO_REGS
))
1434 if (xregno
>= FIRST_PSEUDO_REGISTER
&& xregno
!= INVALID_REGNUM
)
1436 addr
= reg_equiv_mem (xregno
);
1438 addr
= XEXP (addr
, 0);
1443 if (addr
&& CONSTANT_ADDRESS_P (addr
))
1444 return GENERAL_REGS
;
1446 /* Otherwise assume no secondary reloads are needed. */
1451 mn10300_frame_size (void)
1453 /* size includes the fixed stack space needed for function calls. */
1454 int size
= get_frame_size () + crtl
->outgoing_args_size
;
1456 /* And space for the return pointer. */
1457 size
+= crtl
->outgoing_args_size
? 4 : 0;
1463 mn10300_initial_offset (int from
, int to
)
1467 gcc_assert (from
== ARG_POINTER_REGNUM
|| from
== FRAME_POINTER_REGNUM
);
1468 gcc_assert (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
1470 if (to
== STACK_POINTER_REGNUM
)
1471 diff
= mn10300_frame_size ();
1473 /* The difference between the argument pointer and the frame pointer
1474 is the size of the callee register save area. */
1475 if (from
== ARG_POINTER_REGNUM
)
1477 unsigned int reg_save_bytes
;
1479 mn10300_get_live_callee_saved_regs (& reg_save_bytes
);
1480 diff
+= reg_save_bytes
;
1481 diff
+= 4 * fp_regs_to_save ();
1487 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1490 mn10300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1492 /* Return values > 8 bytes in length in memory. */
1493 return (int_size_in_bytes (type
) > 8
1494 || int_size_in_bytes (type
) == 0
1495 || TYPE_MODE (type
) == BLKmode
);
1498 /* Flush the argument registers to the stack for a stdarg function;
1499 return the new argument pointer. */
1501 mn10300_builtin_saveregs (void)
1504 tree fntype
= TREE_TYPE (current_function_decl
);
1505 int argadj
= ((!stdarg_p (fntype
))
1506 ? UNITS_PER_WORD
: 0);
1507 alias_set_type set
= get_varargs_alias_set ();
1510 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, argadj
);
1512 offset
= crtl
->args
.arg_offset_rtx
;
1514 mem
= gen_rtx_MEM (SImode
, crtl
->args
.internal_arg_pointer
);
1515 set_mem_alias_set (mem
, set
);
1516 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
1518 mem
= gen_rtx_MEM (SImode
,
1519 plus_constant (Pmode
,
1520 crtl
->args
.internal_arg_pointer
, 4));
1521 set_mem_alias_set (mem
, set
);
1522 emit_move_insn (mem
, gen_rtx_REG (SImode
, 1));
1524 return copy_to_reg (expand_binop (Pmode
, add_optab
,
1525 crtl
->args
.internal_arg_pointer
,
1526 offset
, 0, 0, OPTAB_LIB_WIDEN
));
1530 mn10300_va_start (tree valist
, rtx nextarg
)
1532 nextarg
= expand_builtin_saveregs ();
1533 std_expand_builtin_va_start (valist
, nextarg
);
1536 /* Return true when a parameter should be passed by reference. */
1539 mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1540 machine_mode mode
, const_tree type
,
1541 bool named ATTRIBUTE_UNUSED
)
1543 unsigned HOST_WIDE_INT size
;
1546 size
= int_size_in_bytes (type
);
1548 size
= GET_MODE_SIZE (mode
);
1550 return (size
> 8 || size
== 0);
1553 /* Return an RTX to represent where a value with mode MODE will be returned
1554 from a function. If the result is NULL_RTX, the argument is pushed. */
1557 mn10300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1558 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1560 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1561 rtx result
= NULL_RTX
;
1564 /* We only support using 2 data registers as argument registers. */
1567 /* Figure out the size of the object to be passed. */
1568 if (mode
== BLKmode
)
1569 size
= int_size_in_bytes (type
);
1571 size
= GET_MODE_SIZE (mode
);
1573 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1575 /* Don't pass this arg via a register if all the argument registers
1577 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1580 /* Don't pass this arg via a register if it would be split between
1581 registers and memory. */
1582 if (type
== NULL_TREE
1583 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1586 switch (cum
->nbytes
/ UNITS_PER_WORD
)
1589 result
= gen_rtx_REG (mode
, FIRST_ARGUMENT_REGNUM
);
1592 result
= gen_rtx_REG (mode
, FIRST_ARGUMENT_REGNUM
+ 1);
1601 /* Update the data in CUM to advance over an argument
1602 of mode MODE and data type TYPE.
1603 (TYPE is null for libcalls where that information may not be available.) */
1606 mn10300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1607 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1609 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1611 cum
->nbytes
+= (mode
!= BLKmode
1612 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1613 : (int_size_in_bytes (type
) + 3) & ~3);
1616 /* Return the number of bytes of registers to use for an argument passed
1617 partially in registers and partially in memory. */
1620 mn10300_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1621 tree type
, bool named ATTRIBUTE_UNUSED
)
1623 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1626 /* We only support using 2 data registers as argument registers. */
1629 /* Figure out the size of the object to be passed. */
1630 if (mode
== BLKmode
)
1631 size
= int_size_in_bytes (type
);
1633 size
= GET_MODE_SIZE (mode
);
1635 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1637 /* Don't pass this arg via a register if all the argument registers
1639 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1642 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1645 /* Don't pass this arg via a register if it would be split between
1646 registers and memory. */
1647 if (type
== NULL_TREE
1648 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1651 return nregs
* UNITS_PER_WORD
- cum
->nbytes
;
1654 /* Return the location of the function's value. This will be either
1655 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1656 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1657 we only return the PARALLEL for outgoing values; we do not want
1658 callers relying on this extra copy. */
1661 mn10300_function_value (const_tree valtype
,
1662 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1666 machine_mode mode
= TYPE_MODE (valtype
);
1668 if (! POINTER_TYPE_P (valtype
))
1669 return gen_rtx_REG (mode
, FIRST_DATA_REGNUM
);
1670 else if (! TARGET_PTR_A0D0
|| ! outgoing
1671 || cfun
->returns_struct
)
1672 return gen_rtx_REG (mode
, FIRST_ADDRESS_REGNUM
);
1674 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (2));
1676 = gen_rtx_EXPR_LIST (VOIDmode
,
1677 gen_rtx_REG (mode
, FIRST_ADDRESS_REGNUM
),
1681 = gen_rtx_EXPR_LIST (VOIDmode
,
1682 gen_rtx_REG (mode
, FIRST_DATA_REGNUM
),
1687 /* Implements TARGET_LIBCALL_VALUE. */
1690 mn10300_libcall_value (machine_mode mode
,
1691 const_rtx fun ATTRIBUTE_UNUSED
)
1693 return gen_rtx_REG (mode
, FIRST_DATA_REGNUM
);
1696 /* Implements FUNCTION_VALUE_REGNO_P. */
1699 mn10300_function_value_regno_p (const unsigned int regno
)
1701 return (regno
== FIRST_DATA_REGNUM
|| regno
== FIRST_ADDRESS_REGNUM
);
1704 /* Output an addition operation. */
1707 mn10300_output_add (rtx operands
[3], bool need_flags
)
1709 rtx dest
, src1
, src2
;
1710 unsigned int dest_regnum
, src1_regnum
, src2_regnum
;
1711 enum reg_class src1_class
, src2_class
, dest_class
;
1717 dest_regnum
= true_regnum (dest
);
1718 src1_regnum
= true_regnum (src1
);
1720 dest_class
= REGNO_REG_CLASS (dest_regnum
);
1721 src1_class
= REGNO_REG_CLASS (src1_regnum
);
1723 if (CONST_INT_P (src2
))
1725 gcc_assert (dest_regnum
== src1_regnum
);
1727 if (src2
== const1_rtx
&& !need_flags
)
1729 if (INTVAL (src2
) == 4 && !need_flags
&& dest_class
!= DATA_REGS
)
1732 gcc_assert (!need_flags
|| dest_class
!= SP_REGS
);
1735 else if (CONSTANT_P (src2
))
1738 src2_regnum
= true_regnum (src2
);
1739 src2_class
= REGNO_REG_CLASS (src2_regnum
);
1741 if (dest_regnum
== src1_regnum
)
1743 if (dest_regnum
== src2_regnum
)
1746 /* The rest of the cases are reg = reg+reg. For AM33, we can implement
1747 this directly, as below, but when optimizing for space we can sometimes
1748 do better by using a mov+add. For MN103, we claimed that we could
1749 implement a three-operand add because the various move and add insns
1750 change sizes across register classes, and we can often do better than
1751 reload in choosing which operand to move. */
1752 if (TARGET_AM33
&& optimize_insn_for_speed_p ())
1753 return "add %2,%1,%0";
1755 /* Catch cases where no extended register was used. */
1756 if (src1_class
!= EXTENDED_REGS
1757 && src2_class
!= EXTENDED_REGS
1758 && dest_class
!= EXTENDED_REGS
)
1760 /* We have to copy one of the sources into the destination, then
1761 add the other source to the destination.
1763 Carefully select which source to copy to the destination; a
1764 naive implementation will waste a byte when the source classes
1765 are different and the destination is an address register.
1766 Selecting the lowest cost register copy will optimize this
1768 if (src1_class
== dest_class
)
1769 return "mov %1,%0\n\tadd %2,%0";
1771 return "mov %2,%0\n\tadd %1,%0";
1774 /* At least one register is an extended register. */
1776 /* The three operand add instruction on the am33 is a win iff the
1777 output register is an extended register, or if both source
1778 registers are extended registers. */
1779 if (dest_class
== EXTENDED_REGS
|| src1_class
== src2_class
)
1780 return "add %2,%1,%0";
1782 /* It is better to copy one of the sources to the destination, then
1783 perform a 2 address add. The destination in this case must be
1784 an address or data register and one of the sources must be an
1785 extended register and the remaining source must not be an extended
1788 The best code for this case is to copy the extended reg to the
1789 destination, then emit a two address add. */
1790 if (src1_class
== EXTENDED_REGS
)
1791 return "mov %1,%0\n\tadd %2,%0";
1793 return "mov %2,%0\n\tadd %1,%0";
1796 /* Return 1 if X contains a symbolic expression. We know these
1797 expressions will have one of a few well defined forms, so
1798 we need only check those forms. */
1801 mn10300_symbolic_operand (rtx op
,
1802 machine_mode mode ATTRIBUTE_UNUSED
)
1804 switch (GET_CODE (op
))
1811 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1812 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1813 && CONST_INT_P (XEXP (op
, 1)));
1819 /* Try machine dependent ways of modifying an illegitimate address
1820 to be legitimate. If we find one, return the new valid address.
1821 This macro is used in only one place: `memory_address' in explow.c.
1823 OLDX is the address as it was before break_out_memory_refs was called.
1824 In some cases it is useful to look at this to decide what needs to be done.
1826 Normally it is always safe for this macro to do nothing. It exists to
1827 recognize opportunities to optimize the output.
1829 But on a few ports with segmented architectures and indexed addressing
1830 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1833 mn10300_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1834 machine_mode mode ATTRIBUTE_UNUSED
)
1836 if (flag_pic
&& ! mn10300_legitimate_pic_operand_p (x
))
1837 x
= mn10300_legitimize_pic_address (oldx
, NULL_RTX
);
1839 /* Uh-oh. We might have an address for x[n-100000]. This needs
1840 special handling to avoid creating an indexed memory address
1841 with x-100000 as the base. */
1842 if (GET_CODE (x
) == PLUS
1843 && mn10300_symbolic_operand (XEXP (x
, 1), VOIDmode
))
1845 /* Ugly. We modify things here so that the address offset specified
1846 by the index expression is computed first, then added to x to form
1847 the entire address. */
1849 rtx regx1
, regy1
, regy2
, y
;
1851 /* Strip off any CONST. */
1853 if (GET_CODE (y
) == CONST
)
1856 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1858 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1859 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1860 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1861 regx1
= force_reg (Pmode
,
1862 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
, regx1
,
1864 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1870 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1871 @GOTOFF in `reg'. */
1874 mn10300_legitimize_pic_address (rtx orig
, rtx reg
)
1878 if (GET_CODE (orig
) == LABEL_REF
1879 || (GET_CODE (orig
) == SYMBOL_REF
1880 && (CONSTANT_POOL_ADDRESS_P (orig
)
1881 || ! MN10300_GLOBAL_P (orig
))))
1884 reg
= gen_reg_rtx (Pmode
);
1886 x
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, orig
), UNSPEC_GOTOFF
);
1887 x
= gen_rtx_CONST (SImode
, x
);
1888 emit_move_insn (reg
, x
);
1890 x
= emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1892 else if (GET_CODE (orig
) == SYMBOL_REF
)
1895 reg
= gen_reg_rtx (Pmode
);
1897 x
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, orig
), UNSPEC_GOT
);
1898 x
= gen_rtx_CONST (SImode
, x
);
1899 x
= gen_rtx_PLUS (SImode
, pic_offset_table_rtx
, x
);
1900 x
= gen_const_mem (SImode
, x
);
1902 x
= emit_move_insn (reg
, x
);
1907 set_unique_reg_note (x
, REG_EQUAL
, orig
);
1911 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1912 isn't protected by a PIC unspec; nonzero otherwise. */
1915 mn10300_legitimate_pic_operand_p (rtx x
)
1920 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1923 if (GET_CODE (x
) == UNSPEC
1924 && (XINT (x
, 1) == UNSPEC_PIC
1925 || XINT (x
, 1) == UNSPEC_GOT
1926 || XINT (x
, 1) == UNSPEC_GOTOFF
1927 || XINT (x
, 1) == UNSPEC_PLT
1928 || XINT (x
, 1) == UNSPEC_GOTSYM_OFF
))
1931 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
1932 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
1938 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1939 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x
, i
, j
)))
1942 else if (fmt
[i
] == 'e'
1943 && ! mn10300_legitimate_pic_operand_p (XEXP (x
, i
)))
1950 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1951 legitimate, and FALSE otherwise.
1953 On the mn10300, the value in the address register must be
1954 in the same memory space/segment as the effective address.
1956 This is problematical for reload since it does not understand
1957 that base+index != index+base in a memory reference.
1959 Note it is still possible to use reg+reg addressing modes,
1960 it's just much more difficult. For a discussion of a possible
1961 workaround and solution, see the comments in pa.c before the
1962 function record_unscaled_index_insn_codes. */
1965 mn10300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1969 if (CONSTANT_ADDRESS_P (x
))
1970 return !flag_pic
|| mn10300_legitimate_pic_operand_p (x
);
1972 if (RTX_OK_FOR_BASE_P (x
, strict
))
1975 if (TARGET_AM33
&& (mode
== SImode
|| mode
== SFmode
|| mode
== HImode
))
1977 if (GET_CODE (x
) == POST_INC
)
1978 return RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
);
1979 if (GET_CODE (x
) == POST_MODIFY
)
1980 return (RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
)
1981 && CONSTANT_ADDRESS_P (XEXP (x
, 1)));
1984 if (GET_CODE (x
) != PLUS
)
1988 index
= XEXP (x
, 1);
1994 /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
1995 addressing is hard to satisfy. */
1999 return (REGNO_GENERAL_P (REGNO (base
), strict
)
2000 && REGNO_GENERAL_P (REGNO (index
), strict
));
2003 if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base
), strict
))
2006 if (CONST_INT_P (index
))
2007 return IN_RANGE (INTVAL (index
), -1 - 0x7fffffff, 0x7fffffff);
2009 if (CONSTANT_ADDRESS_P (index
))
2010 return !flag_pic
|| mn10300_legitimate_pic_operand_p (index
);
2016 mn10300_regno_in_class_p (unsigned regno
, int rclass
, bool strict
)
2018 if (regno
>= FIRST_PSEUDO_REGISTER
)
2024 regno
= reg_renumber
[regno
];
2025 if (regno
== INVALID_REGNUM
)
2028 return TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
);
2032 mn10300_legitimize_reload_address (rtx x
,
2033 machine_mode mode ATTRIBUTE_UNUSED
,
2034 int opnum
, int type
,
2035 int ind_levels ATTRIBUTE_UNUSED
)
2037 bool any_change
= false;
2039 /* See above re disabling reg+reg addressing for MN103. */
2043 if (GET_CODE (x
) != PLUS
)
2046 if (XEXP (x
, 0) == stack_pointer_rtx
)
2048 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2049 GENERAL_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
2050 opnum
, (enum reload_type
) type
);
2053 if (XEXP (x
, 1) == stack_pointer_rtx
)
2055 push_reload (XEXP (x
, 1), NULL_RTX
, &XEXP (x
, 1), NULL
,
2056 GENERAL_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
2057 opnum
, (enum reload_type
) type
);
2061 return any_change
? x
: NULL_RTX
;
2064 /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
2065 constant. Note that some "constants" aren't valid, such as TLS
2066 symbols and unconverted GOT-based references, so we eliminate
2070 mn10300_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2072 switch (GET_CODE (x
))
2077 if (GET_CODE (x
) == PLUS
)
2079 if (! CONST_INT_P (XEXP (x
, 1)))
2084 /* Only some unspecs are valid as "constants". */
2085 if (GET_CODE (x
) == UNSPEC
)
2087 switch (XINT (x
, 1))
2099 /* We must have drilled down to a symbol. */
2100 if (! mn10300_symbolic_operand (x
, Pmode
))
2111 /* Undo pic address legitimization for the benefit of debug info. */
2114 mn10300_delegitimize_address (rtx orig_x
)
2116 rtx x
= orig_x
, ret
, addend
= NULL
;
2121 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
2124 if (XEXP (x
, 0) == pic_offset_table_rtx
)
2126 /* With the REG+REG addressing of AM33, var-tracking can re-assemble
2127 some odd-looking "addresses" that were never valid in the first place.
2128 We need to look harder to avoid warnings being emitted. */
2129 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2131 rtx x0
= XEXP (x
, 0);
2132 rtx x00
= XEXP (x0
, 0);
2133 rtx x01
= XEXP (x0
, 1);
2135 if (x00
== pic_offset_table_rtx
)
2137 else if (x01
== pic_offset_table_rtx
)
2147 if (GET_CODE (x
) != CONST
)
2150 if (GET_CODE (x
) != UNSPEC
)
2153 ret
= XVECEXP (x
, 0, 0);
2154 if (XINT (x
, 1) == UNSPEC_GOTOFF
)
2156 else if (XINT (x
, 1) == UNSPEC_GOT
)
2161 gcc_assert (GET_CODE (ret
) == SYMBOL_REF
);
2162 if (need_mem
!= MEM_P (orig_x
))
2164 if (need_mem
&& addend
)
2167 ret
= gen_rtx_PLUS (Pmode
, addend
, ret
);
2171 /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
2172 the 3-byte fully general instruction; for MN103 this is the 2-byte form
2173 with an address register. */
2176 mn10300_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2177 addr_space_t as ATTRIBUTE_UNUSED
, bool speed
)
2182 switch (GET_CODE (x
))
2187 /* We assume all of these require a 32-bit constant, even though
2188 some symbol and label references can be relaxed. */
2189 return speed
? 1 : 4;
2197 /* Assume any symbolic offset is a 32-bit constant. */
2198 i
= (CONST_INT_P (XEXP (x
, 1)) ? INTVAL (XEXP (x
, 1)) : 0x12345678);
2199 if (IN_RANGE (i
, -128, 127))
2200 return speed
? 0 : 1;
2203 if (IN_RANGE (i
, -0x800000, 0x7fffff))
2209 index
= XEXP (x
, 1);
2210 if (register_operand (index
, SImode
))
2212 /* Attempt to minimize the number of registers in the address.
2213 This is similar to what other ports do. */
2214 if (register_operand (base
, SImode
))
2218 index
= XEXP (x
, 0);
2221 /* Assume any symbolic offset is a 32-bit constant. */
2222 i
= (CONST_INT_P (XEXP (x
, 1)) ? INTVAL (XEXP (x
, 1)) : 0x12345678);
2223 if (IN_RANGE (i
, -128, 127))
2224 return speed
? 0 : 1;
2225 if (IN_RANGE (i
, -32768, 32767))
2226 return speed
? 0 : 2;
2227 return speed
? 2 : 6;
2230 return rtx_cost (x
, MEM
, 0, speed
);
2234 /* Implement the TARGET_REGISTER_MOVE_COST hook.
2236 Recall that the base value of 2 is required by assumptions elsewhere
2237 in the body of the compiler, and that cost 2 is special-cased as an
2238 early exit from reload meaning no work is required. */
2241 mn10300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2242 reg_class_t ifrom
, reg_class_t ito
)
2244 enum reg_class from
= (enum reg_class
) ifrom
;
2245 enum reg_class to
= (enum reg_class
) ito
;
2246 enum reg_class scratch
, test
;
2248 /* Simplify the following code by unifying the fp register classes. */
2249 if (to
== FP_ACC_REGS
)
2251 if (from
== FP_ACC_REGS
)
2254 /* Diagnose invalid moves by costing them as two moves. */
2259 scratch
= (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
2260 else if (to
== MDR_REGS
)
2261 scratch
= DATA_REGS
;
2262 else if (to
== FP_REGS
&& to
!= from
)
2263 scratch
= GENERAL_REGS
;
2267 if (from
== SP_REGS
)
2268 scratch
= (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
2269 else if (from
== MDR_REGS
)
2270 scratch
= DATA_REGS
;
2271 else if (from
== FP_REGS
&& to
!= from
)
2272 scratch
= GENERAL_REGS
;
2274 if (scratch
!= NO_REGS
&& !reg_class_subset_p (test
, scratch
))
2275 return (mn10300_register_move_cost (VOIDmode
, from
, scratch
)
2276 + mn10300_register_move_cost (VOIDmode
, scratch
, to
));
2278 /* From here on, all we need consider are legal combinations. */
2282 /* The scale here is bytes * 2. */
2284 if (from
== to
&& (to
== ADDRESS_REGS
|| to
== DATA_REGS
))
2287 if (from
== SP_REGS
)
2288 return (to
== ADDRESS_REGS
? 2 : 6);
2290 /* For MN103, all remaining legal moves are two bytes. */
2295 return (from
== ADDRESS_REGS
? 4 : 6);
2297 if ((from
== ADDRESS_REGS
|| from
== DATA_REGS
)
2298 && (to
== ADDRESS_REGS
|| to
== DATA_REGS
))
2301 if (to
== EXTENDED_REGS
)
2302 return (to
== from
? 6 : 4);
2304 /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
2309 /* The scale here is cycles * 2. */
2313 if (from
== FP_REGS
)
2316 /* All legal moves between integral registers are single cycle. */
2321 /* Implement the TARGET_MEMORY_MOVE_COST hook.
2323 Given lack of the form of the address, this must be speed-relative,
2324 though we should never be less expensive than a size-relative register
2325 move cost above. This is not a problem. */
2328 mn10300_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2329 reg_class_t iclass
, bool in ATTRIBUTE_UNUSED
)
2331 enum reg_class rclass
= (enum reg_class
) iclass
;
2333 if (rclass
== FP_REGS
)
2338 /* Implement the TARGET_RTX_COSTS hook.
2340 Speed-relative costs are relative to COSTS_N_INSNS, which is intended
2341 to represent cycles. Size-relative costs are in bytes. */
2344 mn10300_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2345 int *ptotal
, bool speed
)
2347 /* This value is used for SYMBOL_REF etc where we want to pretend
2348 we have a full 32-bit constant. */
2349 HOST_WIDE_INT i
= 0x12345678;
2359 if (outer_code
== SET
)
2361 /* 16-bit integer loads have latency 1, 32-bit loads 2. */
2362 if (IN_RANGE (i
, -32768, 32767))
2363 total
= COSTS_N_INSNS (1);
2365 total
= COSTS_N_INSNS (2);
2369 /* 16-bit integer operands don't affect latency;
2370 24-bit and 32-bit operands add a cycle. */
2371 if (IN_RANGE (i
, -32768, 32767))
2374 total
= COSTS_N_INSNS (1);
2379 if (outer_code
== SET
)
2383 else if (IN_RANGE (i
, -128, 127))
2385 else if (IN_RANGE (i
, -32768, 32767))
2392 /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
2393 if (IN_RANGE (i
, -128, 127))
2395 else if (IN_RANGE (i
, -32768, 32767))
2397 else if (TARGET_AM33
&& IN_RANGE (i
, -0x01000000, 0x00ffffff))
2409 /* We assume all of these require a 32-bit constant, even though
2410 some symbol and label references can be relaxed. */
2414 switch (XINT (x
, 1))
2420 case UNSPEC_GOTSYM_OFF
:
2421 /* The PIC unspecs also resolve to a 32-bit constant. */
2425 /* Assume any non-listed unspec is some sort of arithmetic. */
2426 goto do_arith_costs
;
2430 /* Notice the size difference of INC and INC4. */
2431 if (!speed
&& outer_code
== SET
&& CONST_INT_P (XEXP (x
, 1)))
2433 i
= INTVAL (XEXP (x
, 1));
2434 if (i
== 1 || i
== 4)
2436 total
= 1 + rtx_cost (XEXP (x
, 0), PLUS
, 0, speed
);
2440 goto do_arith_costs
;
2454 total
= (speed
? COSTS_N_INSNS (1) : 2);
2458 /* Notice the size difference of ASL2 and variants. */
2459 if (!speed
&& CONST_INT_P (XEXP (x
, 1)))
2460 switch (INTVAL (XEXP (x
, 1)))
2475 total
= (speed
? COSTS_N_INSNS (1) : 3);
2479 total
= (speed
? COSTS_N_INSNS (3) : 2);
2486 total
= (speed
? COSTS_N_INSNS (39)
2487 /* Include space to load+retrieve MDR. */
2488 : code
== MOD
|| code
== UMOD
? 6 : 4);
2492 total
= mn10300_address_cost (XEXP (x
, 0), GET_MODE (x
),
2493 MEM_ADDR_SPACE (x
), speed
);
2495 total
= COSTS_N_INSNS (2 + total
);
2499 /* Probably not implemented. Assume external call. */
2500 total
= (speed
? COSTS_N_INSNS (10) : 7);
2512 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2513 may access it using GOTOFF instead of GOT. */
2516 mn10300_encode_section_info (tree decl
, rtx rtl
, int first
)
2520 default_encode_section_info (decl
, rtl
, first
);
2525 symbol
= XEXP (rtl
, 0);
2526 if (GET_CODE (symbol
) != SYMBOL_REF
)
2530 SYMBOL_REF_FLAG (symbol
) = (*targetm
.binds_local_p
) (decl
);
2533 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2534 and readonly data size. So we crank up the case threshold value to
2535 encourage a series of if/else comparisons to implement many small switch
2536 statements. In theory, this value could be increased much more if we
2537 were solely optimizing for space, but we keep it "reasonable" to avoid
2538 serious code efficiency lossage. */
2541 mn10300_case_values_threshold (void)
2546 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2549 mn10300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2551 rtx mem
, disp
, fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2553 /* This is a strict alignment target, which means that we play
2554 some games to make sure that the locations at which we need
2555 to store <chain> and <disp> wind up at aligned addresses.
2558 0xfc 0xdd mov chain,a1
2560 0xf8 0xed 0x00 btst 0,d1
2564 Note that the two extra insns are effectively nops; they
2565 clobber the flags but do not affect the contents of D0 or D1. */
2567 disp
= expand_binop (SImode
, sub_optab
, fnaddr
,
2568 plus_constant (Pmode
, XEXP (m_tramp
, 0), 11),
2569 NULL_RTX
, 1, OPTAB_DIRECT
);
2571 mem
= adjust_address (m_tramp
, SImode
, 0);
2572 emit_move_insn (mem
, gen_int_mode (0xddfc0028, SImode
));
2573 mem
= adjust_address (m_tramp
, SImode
, 4);
2574 emit_move_insn (mem
, chain_value
);
2575 mem
= adjust_address (m_tramp
, SImode
, 8);
2576 emit_move_insn (mem
, gen_int_mode (0xdc00edf8, SImode
));
2577 mem
= adjust_address (m_tramp
, SImode
, 12);
2578 emit_move_insn (mem
, disp
);
2581 /* Output the assembler code for a C++ thunk function.
2582 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2583 is the decl for the target function. DELTA is an immediate constant
2584 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2585 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2586 additionally added to THIS. Finally jump to the entry point of
2590 mn10300_asm_output_mi_thunk (FILE * file
,
2591 tree thunk_fndecl ATTRIBUTE_UNUSED
,
2592 HOST_WIDE_INT delta
,
2593 HOST_WIDE_INT vcall_offset
,
2598 /* Get the register holding the THIS parameter. Handle the case
2599 where there is a hidden first argument for a returned structure. */
2600 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
2601 _this
= reg_names
[FIRST_ARGUMENT_REGNUM
+ 1];
2603 _this
= reg_names
[FIRST_ARGUMENT_REGNUM
];
2605 fprintf (file
, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START
);
2608 fprintf (file
, "\tadd %d, %s\n", (int) delta
, _this
);
2612 const char * scratch
= reg_names
[FIRST_ADDRESS_REGNUM
+ 1];
2614 fprintf (file
, "\tmov %s, %s\n", _this
, scratch
);
2615 fprintf (file
, "\tmov (%s), %s\n", scratch
, scratch
);
2616 fprintf (file
, "\tadd %d, %s\n", (int) vcall_offset
, scratch
);
2617 fprintf (file
, "\tmov (%s), %s\n", scratch
, scratch
);
2618 fprintf (file
, "\tadd %s, %s\n", scratch
, _this
);
2621 fputs ("\tjmp ", file
);
2622 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2626 /* Return true if mn10300_output_mi_thunk would be able to output the
2627 assembler code for the thunk function specified by the arguments
2628 it is passed, and false otherwise. */
2631 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
2632 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
2633 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2634 const_tree function ATTRIBUTE_UNUSED
)
2640 mn10300_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2642 if (REGNO_REG_CLASS (regno
) == FP_REGS
2643 || REGNO_REG_CLASS (regno
) == FP_ACC_REGS
)
2644 /* Do not store integer values in FP registers. */
2645 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ((regno
& 1) == 0);
2647 if (! TARGET_AM33
&& REGNO_REG_CLASS (regno
) == EXTENDED_REGS
)
2650 if (((regno
) & 1) == 0 || GET_MODE_SIZE (mode
) == 4)
2653 if (REGNO_REG_CLASS (regno
) == DATA_REGS
2654 || (TARGET_AM33
&& REGNO_REG_CLASS (regno
) == ADDRESS_REGS
)
2655 || REGNO_REG_CLASS (regno
) == EXTENDED_REGS
)
2656 return GET_MODE_SIZE (mode
) <= 4;
2662 mn10300_modes_tieable (machine_mode mode1
, machine_mode mode2
)
2664 if (GET_MODE_CLASS (mode1
) == MODE_FLOAT
2665 && GET_MODE_CLASS (mode2
) != MODE_FLOAT
)
2668 if (GET_MODE_CLASS (mode2
) == MODE_FLOAT
2669 && GET_MODE_CLASS (mode1
) != MODE_FLOAT
)
2674 || (GET_MODE_SIZE (mode1
) <= 4 && GET_MODE_SIZE (mode2
) <= 4))
2681 cc_flags_for_mode (machine_mode mode
)
2686 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_C
| CC_FLAG_V
;
2688 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_C
;
2690 return CC_FLAG_Z
| CC_FLAG_N
;
2699 cc_flags_for_code (enum rtx_code code
)
2712 case GT
: /* ~(Z|(N^V)) */
2713 case LE
: /* Z|(N^V) */
2714 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_V
;
2720 case GTU
: /* ~(C | Z) */
2721 case LEU
: /* C | Z */
2722 return CC_FLAG_Z
| CC_FLAG_C
;
2740 mn10300_select_cc_mode (enum rtx_code code
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2744 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2745 return CC_FLOATmode
;
2747 req
= cc_flags_for_code (code
);
2749 if (req
& CC_FLAG_V
)
2751 if (req
& CC_FLAG_C
)
2757 set_is_load_p (rtx set
)
2759 return MEM_P (SET_SRC (set
));
2763 set_is_store_p (rtx set
)
2765 return MEM_P (SET_DEST (set
));
2768 /* Update scheduling costs for situations that cannot be
2769 described using the attributes and DFA machinery.
2770 DEP is the insn being scheduled.
2771 INSN is the previous insn.
2772 COST is the current cycle cost for DEP. */
2775 mn10300_adjust_sched_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep
, int cost
)
2784 /* We are only interested in pairs of SET. */
2785 insn_set
= single_set (insn
);
2789 dep_set
= single_set (dep
);
2793 /* For the AM34 a load instruction that follows a
2794 store instruction incurs an extra cycle of delay. */
2795 if (mn10300_tune_cpu
== PROCESSOR_AM34
2796 && set_is_load_p (dep_set
)
2797 && set_is_store_p (insn_set
))
2800 /* For the AM34 a non-store, non-branch FPU insn that follows
2801 another FPU insn incurs a one cycle throughput increase. */
2802 else if (mn10300_tune_cpu
== PROCESSOR_AM34
2803 && ! set_is_store_p (insn_set
)
2805 && GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set
))) == MODE_FLOAT
2806 && GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set
))) == MODE_FLOAT
)
2809 /* Resolve the conflict described in section 1-7-4 of
2810 Chapter 3 of the MN103E Series Instruction Manual
2813 "When the preceding instruction is a CPU load or
2814 store instruction, a following FPU instruction
2815 cannot be executed until the CPU completes the
2816 latency period even though there are no register
2817 or flag dependencies between them." */
2819 /* Only the AM33-2 (and later) CPUs have FPU instructions. */
2820 if (! TARGET_AM33_2
)
2823 /* If a data dependence already exists then the cost is correct. */
2824 if (REG_NOTE_KIND (link
) == 0)
2827 /* Check that the instruction about to scheduled is an FPU instruction. */
2828 if (GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set
))) != MODE_FLOAT
)
2831 /* Now check to see if the previous instruction is a load or store. */
2832 if (! set_is_load_p (insn_set
) && ! set_is_store_p (insn_set
))
2835 /* XXX: Verify: The text of 1-7-4 implies that the restriction
2836 only applies when an INTEGER load/store precedes an FPU
2837 instruction, but is this true ? For now we assume that it is. */
2838 if (GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set
))) != MODE_INT
)
2841 /* Extract the latency value from the timings attribute. */
2842 timings
= get_attr_timings (insn
);
2843 return timings
< 100 ? (timings
% 10) : (timings
% 100);
2847 mn10300_conditional_register_usage (void)
2853 for (i
= FIRST_EXTENDED_REGNUM
;
2854 i
<= LAST_EXTENDED_REGNUM
; i
++)
2855 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2859 for (i
= FIRST_FP_REGNUM
;
2860 i
<= LAST_FP_REGNUM
; i
++)
2861 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2864 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] =
2865 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2868 /* Worker function for TARGET_MD_ASM_ADJUST.
2869 We do this in the mn10300 backend to maintain source compatibility
2870 with the old cc0-based compiler. */
2873 mn10300_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
2874 vec
<const char *> &/*constraints*/,
2875 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
2877 clobbers
.safe_push (gen_rtx_REG (CCmode
, CC_REG
));
2878 SET_HARD_REG_BIT (clobbered_regs
, CC_REG
);
2882 /* A helper function for splitting cbranch patterns after reload. */
2885 mn10300_split_cbranch (machine_mode cmp_mode
, rtx cmp_op
, rtx label_ref
)
2889 flags
= gen_rtx_REG (cmp_mode
, CC_REG
);
2890 x
= gen_rtx_COMPARE (cmp_mode
, XEXP (cmp_op
, 0), XEXP (cmp_op
, 1));
2891 x
= gen_rtx_SET (flags
, x
);
2894 x
= gen_rtx_fmt_ee (GET_CODE (cmp_op
), VOIDmode
, flags
, const0_rtx
);
2895 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
, label_ref
, pc_rtx
);
2896 x
= gen_rtx_SET (pc_rtx
, x
);
2900 /* A helper function for matching parallels that set the flags. */
2903 mn10300_match_ccmode (rtx insn
, machine_mode cc_mode
)
2906 machine_mode flags_mode
;
2908 gcc_checking_assert (XVECLEN (PATTERN (insn
), 0) == 2);
2910 op1
= XVECEXP (PATTERN (insn
), 0, 1);
2911 gcc_checking_assert (GET_CODE (SET_SRC (op1
)) == COMPARE
);
2913 flags
= SET_DEST (op1
);
2914 flags_mode
= GET_MODE (flags
);
2916 if (GET_MODE (SET_SRC (op1
)) != flags_mode
)
2918 if (GET_MODE_CLASS (flags_mode
) != MODE_CC
)
2921 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2922 if (cc_flags_for_mode (flags_mode
) & ~cc_flags_for_mode (cc_mode
))
2928 /* This function is used to help split:
2930 (set (reg) (and (reg) (int)))
2934 (set (reg) (shift (reg) (int))
2935 (set (reg) (shift (reg) (int))
2937 where the shitfs will be shorter than the "and" insn.
2939 It returns the number of bits that should be shifted. A positive
2940 values means that the low bits are to be cleared (and hence the
2941 shifts should be right followed by left) whereas a negative value
2942 means that the high bits are to be cleared (left followed by right).
2943 Zero is returned when it would not be economical to split the AND. */
2946 mn10300_split_and_operand_count (rtx op
)
2948 HOST_WIDE_INT val
= INTVAL (op
);
2953 /* High bit is set, look for bits clear at the bottom. */
2954 count
= exact_log2 (-val
);
2957 /* This is only size win if we can use the asl2 insn. Otherwise we
2958 would be replacing 1 6-byte insn with 2 3-byte insns. */
2959 if (count
> (optimize_insn_for_speed_p () ? 2 : 4))
2965 /* High bit is clear, look for bits set at the bottom. */
2966 count
= exact_log2 (val
+ 1);
2968 /* Again, this is only a size win with asl2. */
2969 if (count
> (optimize_insn_for_speed_p () ? 2 : 4))
2978 enum attr_liw_op op
;
2983 /* Decide if the given insn is a candidate for LIW bundling. If it is then
2984 extract the operands and LIW attributes from the insn and use them to fill
2985 in the liw_data structure. Return true upon success or false if the insn
2986 cannot be bundled. */
2989 extract_bundle (rtx_insn
*insn
, struct liw_data
* pdata
)
2991 bool allow_consts
= true;
2994 gcc_assert (pdata
!= NULL
);
2998 /* Make sure that we are dealing with a simple SET insn. */
2999 p
= single_set (insn
);
3003 /* Make sure that it could go into one of the LIW pipelines. */
3004 pdata
->slot
= get_attr_liw (insn
);
3005 if (pdata
->slot
== LIW_BOTH
)
3008 pdata
->op
= get_attr_liw_op (insn
);
3013 pdata
->dest
= SET_DEST (p
);
3014 pdata
->src
= SET_SRC (p
);
3017 pdata
->dest
= XEXP (SET_SRC (p
), 0);
3018 pdata
->src
= XEXP (SET_SRC (p
), 1);
3025 /* The AND, OR and XOR long instruction words only accept register arguments. */
3026 allow_consts
= false;
3029 pdata
->dest
= SET_DEST (p
);
3030 pdata
->src
= XEXP (SET_SRC (p
), 1);
3034 if (! REG_P (pdata
->dest
))
3037 if (REG_P (pdata
->src
))
3040 return allow_consts
&& satisfies_constraint_O (pdata
->src
);
3043 /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
3044 the instructions with the assumption that LIW1 would be executed before LIW2
3045 so we must check for overlaps between their sources and destinations. */
3048 check_liw_constraints (struct liw_data
* pliw1
, struct liw_data
* pliw2
)
3050 /* Check for slot conflicts. */
3051 if (pliw2
->slot
== pliw1
->slot
&& pliw1
->slot
!= LIW_EITHER
)
3054 /* If either operation is a compare, then "dest" is really an input; the real
3055 destination is CC_REG. So these instructions need different checks. */
3057 /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
3058 check its values prior to any changes made by OP. */
3059 if (pliw1
->op
== LIW_OP_CMP
)
3061 /* Two sequential comparisons means dead code, which ought to
3062 have been eliminated given that bundling only happens with
3063 optimization. We cannot bundle them in any case. */
3064 gcc_assert (pliw1
->op
!= pliw2
->op
);
3068 /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
3069 is the destination of OP, as the CMP will look at the old value, not the new
3071 if (pliw2
->op
== LIW_OP_CMP
)
3073 if (REGNO (pliw2
->dest
) == REGNO (pliw1
->dest
))
3076 if (REG_P (pliw2
->src
))
3077 return REGNO (pliw2
->src
) != REGNO (pliw1
->dest
);
3082 /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
3083 same destination register. */
3084 if (REGNO (pliw2
->dest
) == REGNO (pliw1
->dest
))
3087 /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
3088 of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
3089 we can replace the source in OP2 with the source of OP1. */
3090 if (REG_P (pliw2
->src
) && REGNO (pliw2
->src
) == REGNO (pliw1
->dest
))
3092 if (pliw1
->op
== LIW_OP_MOV
&& REG_P (pliw1
->src
))
3094 if (! REG_P (pliw1
->src
)
3095 && (pliw2
->op
== LIW_OP_AND
3096 || pliw2
->op
== LIW_OP_OR
3097 || pliw2
->op
== LIW_OP_XOR
))
3100 pliw2
->src
= pliw1
->src
;
3106 /* Everything else is OK. */
3110 /* Combine pairs of insns into LIW bundles. */
3113 mn10300_bundle_liw (void)
3117 for (r
= get_insns (); r
!= NULL
; r
= next_nonnote_nondebug_insn (r
))
3119 rtx_insn
*insn1
, *insn2
;
3120 struct liw_data liw1
, liw2
;
3123 if (! extract_bundle (insn1
, & liw1
))
3126 insn2
= next_nonnote_nondebug_insn (insn1
);
3127 if (! extract_bundle (insn2
, & liw2
))
3130 /* Check for source/destination overlap. */
3131 if (! check_liw_constraints (& liw1
, & liw2
))
3134 if (liw1
.slot
== LIW_OP2
|| liw2
.slot
== LIW_OP1
)
3136 struct liw_data temp
;
3143 delete_insn (insn2
);
3146 if (liw1
.op
== LIW_OP_CMP
)
3147 insn2_pat
= gen_cmp_liw (liw2
.dest
, liw2
.src
, liw1
.dest
, liw1
.src
,
3149 else if (liw2
.op
== LIW_OP_CMP
)
3150 insn2_pat
= gen_liw_cmp (liw1
.dest
, liw1
.src
, liw2
.dest
, liw2
.src
,
3153 insn2_pat
= gen_liw (liw1
.dest
, liw2
.dest
, liw1
.src
, liw2
.src
,
3154 GEN_INT (liw1
.op
), GEN_INT (liw2
.op
));
3156 insn2
= emit_insn_after (insn2_pat
, insn1
);
3157 delete_insn (insn1
);
3162 #define DUMP(reason, insn) \
3167 fprintf (dump_file, reason "\n"); \
3168 if (insn != NULL_RTX) \
3169 print_rtl_single (dump_file, insn); \
3170 fprintf(dump_file, "\n"); \
3175 /* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
3176 Insert a SETLB insn just before LABEL. */
3179 mn10300_insert_setlb_lcc (rtx label
, rtx branch
)
3181 rtx lcc
, comparison
, cmp_reg
;
3183 if (LABEL_NUSES (label
) > 1)
3187 /* This label is used both as an entry point to the loop
3188 and as a loop-back point for the loop. We need to separate
3189 these two functions so that the SETLB happens upon entry,
3190 but the loop-back does not go to the SETLB instruction. */
3191 DUMP ("Inserting SETLB insn after:", label
);
3192 insn
= emit_insn_after (gen_setlb (), label
);
3193 label
= gen_label_rtx ();
3194 emit_label_after (label
, insn
);
3195 DUMP ("Created new loop-back label:", label
);
3199 DUMP ("Inserting SETLB insn before:", label
);
3200 emit_insn_before (gen_setlb (), label
);
3203 comparison
= XEXP (SET_SRC (PATTERN (branch
)), 0);
3204 cmp_reg
= XEXP (comparison
, 0);
3205 gcc_assert (REG_P (cmp_reg
));
3207 /* If the comparison has not already been split out of the branch
3209 gcc_assert (REGNO (cmp_reg
) == CC_REG
);
3211 if (GET_MODE (cmp_reg
) == CC_FLOATmode
)
3212 lcc
= gen_FLcc (comparison
, label
);
3214 lcc
= gen_Lcc (comparison
, label
);
3216 rtx_insn
*jump
= emit_jump_insn_before (lcc
, branch
);
3217 mark_jump_label (XVECEXP (lcc
, 0, 0), jump
, 0);
3218 JUMP_LABEL (jump
) = label
;
3219 DUMP ("Replacing branch insn...", branch
);
3220 DUMP ("... with Lcc insn:", jump
);
3221 delete_insn (branch
);
3225 mn10300_block_contains_call (basic_block block
)
3229 FOR_BB_INSNS (block
, insn
)
3237 mn10300_loop_contains_call_insn (loop_p loop
)
3240 bool result
= false;
3243 bbs
= get_loop_body (loop
);
3245 for (i
= 0; i
< loop
->num_nodes
; i
++)
3246 if (mn10300_block_contains_call (bbs
[i
]))
3257 mn10300_scan_for_setlb_lcc (void)
3261 DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX
);
3264 compute_bb_for_insn ();
3266 /* Find the loops. */
3267 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
3269 /* FIXME: For now we only investigate innermost loops. In practice however
3270 if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
3271 be the case that its parent loop is suitable. Thus we should check all
3272 loops, but work from the innermost outwards. */
3273 FOR_EACH_LOOP (loop
, LI_ONLY_INNERMOST
)
3275 const char * reason
= NULL
;
3277 /* Check to see if we can modify this loop. If we cannot
3278 then set 'reason' to describe why it could not be done. */
3279 if (loop
->latch
== NULL
)
3280 reason
= "it contains multiple latches";
3281 else if (loop
->header
!= loop
->latch
)
3282 /* FIXME: We could handle loops that span multiple blocks,
3283 but this requires a lot more work tracking down the branches
3284 that need altering, so for now keep things simple. */
3285 reason
= "the loop spans multiple blocks";
3286 else if (mn10300_loop_contains_call_insn (loop
))
3287 reason
= "it contains CALL insns";
3290 rtx_insn
*branch
= BB_END (loop
->latch
);
3292 gcc_assert (JUMP_P (branch
));
3293 if (single_set (branch
) == NULL_RTX
|| ! any_condjump_p (branch
))
3294 /* We cannot optimize tablejumps and the like. */
3295 /* FIXME: We could handle unconditional jumps. */
3296 reason
= "it is not a simple loop";
3302 flow_loop_dump (loop
, dump_file
, NULL
, 0);
3304 label
= BB_HEAD (loop
->header
);
3305 gcc_assert (LABEL_P (label
));
3307 mn10300_insert_setlb_lcc (label
, branch
);
3311 if (dump_file
&& reason
!= NULL
)
3312 fprintf (dump_file
, "Loop starting with insn %d is not suitable because %s\n",
3313 INSN_UID (BB_HEAD (loop
->header
)),
3317 loop_optimizer_finalize ();
3319 df_finish_pass (false);
3321 DUMP ("SETLB scan complete", NULL_RTX
);
3325 mn10300_reorg (void)
3327 /* These are optimizations, so only run them if optimizing. */
3328 if (TARGET_AM33
&& (optimize
> 0 || optimize_size
))
3330 if (TARGET_ALLOW_SETLB
)
3331 mn10300_scan_for_setlb_lcc ();
3333 if (TARGET_ALLOW_LIW
)
3334 mn10300_bundle_liw ();
3338 /* Initialize the GCC target structure. */
3340 #undef TARGET_MACHINE_DEPENDENT_REORG
3341 #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
3343 #undef TARGET_ASM_ALIGNED_HI_OP
3344 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3346 #undef TARGET_LEGITIMIZE_ADDRESS
3347 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
3349 #undef TARGET_ADDRESS_COST
3350 #define TARGET_ADDRESS_COST mn10300_address_cost
3351 #undef TARGET_REGISTER_MOVE_COST
3352 #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
3353 #undef TARGET_MEMORY_MOVE_COST
3354 #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
3355 #undef TARGET_RTX_COSTS
3356 #define TARGET_RTX_COSTS mn10300_rtx_costs
3358 #undef TARGET_ASM_FILE_START
3359 #define TARGET_ASM_FILE_START mn10300_file_start
3360 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
3361 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
3363 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
3364 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
3366 #undef TARGET_OPTION_OVERRIDE
3367 #define TARGET_OPTION_OVERRIDE mn10300_option_override
3369 #undef TARGET_ENCODE_SECTION_INFO
3370 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
3372 #undef TARGET_PROMOTE_PROTOTYPES
3373 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
3374 #undef TARGET_RETURN_IN_MEMORY
3375 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
3376 #undef TARGET_PASS_BY_REFERENCE
3377 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
3378 #undef TARGET_CALLEE_COPIES
3379 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
3380 #undef TARGET_ARG_PARTIAL_BYTES
3381 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
3382 #undef TARGET_FUNCTION_ARG
3383 #define TARGET_FUNCTION_ARG mn10300_function_arg
3384 #undef TARGET_FUNCTION_ARG_ADVANCE
3385 #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
3387 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
3388 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
3389 #undef TARGET_EXPAND_BUILTIN_VA_START
3390 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
3392 #undef TARGET_CASE_VALUES_THRESHOLD
3393 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
3395 #undef TARGET_LEGITIMATE_ADDRESS_P
3396 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
3397 #undef TARGET_DELEGITIMIZE_ADDRESS
3398 #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
3399 #undef TARGET_LEGITIMATE_CONSTANT_P
3400 #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
3402 #undef TARGET_PREFERRED_RELOAD_CLASS
3403 #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
3404 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
3405 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
3406 mn10300_preferred_output_reload_class
3407 #undef TARGET_SECONDARY_RELOAD
3408 #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
3410 #undef TARGET_TRAMPOLINE_INIT
3411 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
3413 #undef TARGET_FUNCTION_VALUE
3414 #define TARGET_FUNCTION_VALUE mn10300_function_value
3415 #undef TARGET_LIBCALL_VALUE
3416 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
3418 #undef TARGET_ASM_OUTPUT_MI_THUNK
3419 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
3420 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3421 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
3423 #undef TARGET_SCHED_ADJUST_COST
3424 #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
3426 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3427 #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
3429 #undef TARGET_MD_ASM_ADJUST
3430 #define TARGET_MD_ASM_ADJUST mn10300_md_asm_adjust
3432 #undef TARGET_FLAGS_REGNUM
3433 #define TARGET_FLAGS_REGNUM CC_REG
3435 struct gcc_target targetm
= TARGET_INITIALIZER
;