| blob | f7a9f3ebbad32908144dbadda8607c4227a65c9c |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
76 /* This file should be included last. */
79 /* Defined for convenience. */
80 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
82 /* Classifies an address.
84 ADDRESS_REG_IMM
85 A simple base register plus immediate offset.
87 ADDRESS_REG_WB
88 A base register indexed by immediate offset with writeback.
90 ADDRESS_REG_REG
91 A base register indexed by (optionally scaled) register.
93 ADDRESS_REG_UXTW
94 A base register indexed by (optionally scaled) zero-extended register.
96 ADDRESS_REG_SXTW
97 A base register indexed by (optionally scaled) sign-extended register.
99 ADDRESS_LO_SUM
100 A LO_SUM rtx with a base register and "LO12" symbol relocation.
102 ADDRESS_SYMBOLIC:
103 A constant symbolic address, in pc-relative literal pool. */
106 ADDRESS_REG_IMM,
107 ADDRESS_REG_WB,
108 ADDRESS_REG_REG,
109 ADDRESS_REG_UXTW,
110 ADDRESS_REG_SXTW,
111 ADDRESS_LO_SUM,
112 ADDRESS_SYMBOLIC
113 };
117 rtx base;
118 rtx offset;
121 };
123 struct simd_immediate_info
124 {
125 rtx value;
130 };
132 /* The current code model. */
135 #ifdef HAVE_AS_TLS
136 #undef TARGET_HAVE_TLS
137 #define TARGET_HAVE_TLS 1
138 #endif
142 const_tree,
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instructions we are allowed to generate. */
163 /* Mask to specify which instruction scheduling options should be used. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name, y) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
183 #undef AARCH64_FUION_PAIR
185 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name, y) \
186 { name, AARCH64_EXTRA_TUNE_##internal_name },
188 {
193 };
194 #undef AARCH64_EXTRA_TUNING_OPTION
196 /* Tuning parameters. */
199 {
200 {
205 },
211 };
214 {
215 {
220 },
226 };
229 {
230 {
235 },
241 };
244 {
246 /* Avoid the use of slow int<->fp moves for spilling by setting
247 their cost higher than memmov_cost. */
251 };
254 {
256 /* Avoid the use of slow int<->fp moves for spilling by setting
257 their cost higher than memmov_cost. */
261 };
264 {
266 /* Avoid the use of slow int<->fp moves for spilling by setting
267 their cost higher than memmov_cost. */
271 };
274 {
279 };
282 {
284 /* Avoid the use of slow int<->fp moves for spilling by setting
285 their cost higher than memmov_cost. */
289 };
291 /* Generic costs for vector insn classes. */
293 {
306 };
308 /* Generic costs for vector insn classes. */
310 {
323 };
325 /* Generic costs for vector insn classes. */
327 {
340 };
342 /* Generic costs for branch instructions. */
344 {
347 };
350 {
368 };
371 {
390 };
393 {
412 };
415 {
434 };
437 {
455 };
458 {
476 };
478 /* Support for fine-grained override of the tuning structures. */
479 struct aarch64_tuning_override_function
480 {
483 };
488 static const struct aarch64_tuning_override_function
489 aarch64_tuning_override_functions[] =
490 {
494 };
496 /* A processor implementing AArch64. */
497 struct processor
498 {
505 };
507 /* Processor cores implementing AArch64. */
509 {
510 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
511 {NAME, SCHED, #ARCH, ARCH, FLAGS, &COSTS##_tunings},
513 #undef AARCH64_CORE
516 };
518 /* Architectures implementing AArch64. */
520 {
521 #define AARCH64_ARCH(NAME, CORE, ARCH, FLAGS) \
522 {NAME, CORE, #ARCH, ARCH, FLAGS, NULL},
524 #undef AARCH64_ARCH
526 };
528 /* Target specification. These are populated as commandline arguments
529 are processed, or NULL if not specified. */
534 /* The current tuning set. */
537 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
539 /* An ISA extension in the co-processor and main instruction set space. */
540 struct aarch64_option_extension
541 {
545 };
547 /* ISA extensions in AArch64. */
549 {
550 #define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
551 {NAME, FLAGS_ON, FLAGS_OFF},
553 #undef AARCH64_OPT_EXTENSION
555 };
557 /* Used to track the size of an address when generating a pre/post
558 increment address. */
561 /* A table of valid AArch64 "bitmask immediate" values for
562 logical instructions. */
564 #define AARCH64_NUM_BITMASKS 5334
568 {
572 }
573 aarch64_cc;
575 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
577 /* The condition codes of the processor, and the inverse function. */
579 {
582 };
584 void
586 {
590 else
592 }
594 static unsigned int
596 {
600 }
602 static int
605 {
613 }
615 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
616 unsigned
618 {
626 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
627 equivalent DWARF register. */
629 }
631 /* Return TRUE if MODE is any of the large INT modes. */
632 static bool
634 {
636 }
638 /* Return TRUE if MODE is any of the vector modes. */
639 static bool
641 {
644 }
646 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
647 static bool
650 {
657 }
659 /* Implement HARD_REGNO_NREGS. */
661 int
663 {
665 {
671 }
673 }
675 /* Implement HARD_REGNO_MODE_OK. */
677 int
679 {
684 /* The purpose of comparing with ptr_mode is to support the
685 global register variable associated with the stack pointer
686 register via the syntax of asm ("wsp") in ILP32. */
696 {
698 return
700 else
702 }
705 }
707 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
708 machine_mode
710 machine_mode mode)
711 {
712 /* Handle modes that fit within single registers. */
714 {
717 else
719 }
720 /* Fall back to generic for multi-reg and very large modes. */
721 else
723 }
725 /* Return true if calls to DECL should be treated as
726 long-calls (ie called via a register). */
727 static bool
729 {
731 }
733 /* Return true if calls to symbol-ref SYM should be treated as
734 long-calls (ie called via a register). */
735 bool
737 {
739 }
741 /* Return true if the offsets to a zero/sign-extract operation
742 represent an expression that matches an extend operation. The
743 operands represent the paramters from
745 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
746 bool
748 rtx extract_imm)
749 {
766 }
768 /* Emit an insn that's a simple single-set. Both the operands must be
769 known to be valid. */
772 {
774 }
776 /* X and Y are two things to compare using CODE. Emit the compare insn and
777 return the rtx for register 0 in the proper mode. */
778 rtx
780 {
786 }
788 /* Build the SYMBOL_REF for __tls_get_addr. */
792 rtx
794 {
798 }
800 /* Return the TLS model to use for ADDR. */
802 static enum tls_model
804 {
809 {
813 }
818 }
820 /* We'll allow lo_sum's in addresses in our legitimate addresses
821 so that combine would take care of combining addresses where
822 necessary, but for generation purposes, we'll generate the address
823 as :
824 RTL Absolute
825 tmp = hi (symbol_ref); adrp x1, foo
826 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
827 nop
829 PIC TLS
830 adrp x1, :got:foo adrp tmp, :tlsgd:foo
831 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
832 bl __tls_get_addr
833 nop
835 Load TLS symbol, depending on TLS mechanism and TLS access model.
837 Global Dynamic - Traditional TLS:
838 adrp tmp, :tlsgd:imm
839 add dest, tmp, #:tlsgd_lo12:imm
840 bl __tls_get_addr
842 Global Dynamic - TLS Descriptors:
843 adrp dest, :tlsdesc:imm
844 ldr tmp, [dest, #:tlsdesc_lo12:imm]
845 add dest, dest, #:tlsdesc_lo12:imm
846 blr tmp
847 mrs tp, tpidr_el0
848 add dest, dest, tp
850 Initial Exec:
851 mrs tp, tpidr_el0
852 adrp tmp, :gottprel:imm
853 ldr dest, [tmp, #:gottprel_lo12:imm]
854 add dest, dest, tp
856 Local Exec:
857 mrs tp, tpidr_el0
858 add t0, tp, #:tprel_hi12:imm, lsl #12
859 add t0, t0, #:tprel_lo12_nc:imm
860 */
862 static void
865 {
867 {
869 {
870 /* In ILP32, the mode of dest can be either SImode or DImode. */
882 }
889 {
893 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
894 here before rtl expand. Tree IVOPT will generate rtl pattern to
895 decide rtx costs, in which case pic_offset_table_rtx is not
896 initialized. For that case no need to generate the first adrp
897 instruction as the the final cost for global variable access is
898 one instruction. */
900 {
901 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
902 using the page base as GOT base, the first page may be wasted,
903 in the worst scenario, there is only 28K space for GOT).
905 The generate instruction sequence for accessing global variable
906 is:
908 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
910 Only one instruction needed. But we must initialize
911 pic_offset_table_rtx properly. We generate initialize insn for
912 every global access, and allow CSE to remove all redundant.
914 The final instruction sequences will look like the following
915 for multiply global variables access.
917 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
919 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
920 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
921 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
922 ... */
930 }
933 {
936 else
938 }
939 else
940 {
943 }
946 }
949 {
950 /* In ILP32, the mode of dest can be either SImode or DImode,
951 while the got entry is always of SImode size. The mode of
952 dest depends on how dest is used: if dest is assigned to a
953 pointer (e.g. in the memory), it has SImode; it may have
954 DImode if dest is dereferenced to access the memeory.
955 This is why we have to handle three different ldr_got_small
956 patterns here (two patterns for ILP32). */
965 {
968 else
970 }
971 else
972 {
975 }
978 }
981 {
993 }
996 {
999 rtx tp;
1003 /* In ILP32, the got entry is always of SImode size. Unlike
1004 small GOT, the dest is fixed at reg 0. */
1007 else
1017 }
1020 {
1021 /* In ILP32, the mode of dest can be either SImode or DImode,
1022 while the got entry is always of SImode size. The mode of
1023 dest depends on how dest is used: if dest is assigned to a
1024 pointer (e.g. in the memory), it has SImode; it may have
1025 DImode if dest is dereferenced to access the memeory.
1026 This is why we have to handle three different tlsie_small
1027 patterns here (two patterns for ILP32). */
1033 {
1036 else
1037 {
1040 }
1041 }
1042 else
1043 {
1046 }
1051 }
1054 {
1063 }
1071 }
1072 }
1074 /* Emit a move from SRC to DEST. Assume that the move expanders can
1075 handle all moves if !can_create_pseudo_p (). The distinction is
1076 important because, unlike emit_move_insn, the move expanders know
1077 how to force Pmode objects into the constant pool even when the
1078 constant pool address is not itself legitimate. */
1079 static rtx
1081 {
1085 }
1087 /* Split a 128-bit move operation into two 64-bit move operations,
1088 taking care to handle partial overlap of register to register
1089 copies. Special cases are needed when moving between GP regs and
1090 FP regs. SRC can be a register, constant or memory; DST a register
1091 or memory. If either operand is memory it must not have any side
1092 effects. */
1093 void
1095 {
1106 {
1110 /* Handle FP <-> GP regs. */
1112 {
1117 {
1120 }
1121 else
1122 {
1125 }
1127 }
1129 {
1134 {
1137 }
1138 else
1139 {
1142 }
1144 }
1145 }
1152 /* At most one pairing may overlap. */
1154 {
1157 }
1158 else
1159 {
1162 }
1163 }
1165 bool
1167 {
1170 }
1172 /* Split a complex SIMD combine. */
1174 void
1176 {
1183 {
1187 {
1208 }
1212 }
1213 }
1215 /* Split a complex SIMD move. */
1217 void
1219 {
1226 {
1232 {
1253 }
1257 }
1258 }
1260 static rtx
1262 {
1265 else
1266 {
1269 }
1270 }
1273 static rtx
1275 {
1277 {
1278 rtx high;
1279 /* Load the full offset into a register. This
1280 might be improvable in the future. */
1286 }
1288 }
1290 static int
1292 machine_mode mode)
1293 {
1299 rtx subtarget;
1304 {
1307 num_insns++;
1309 }
1312 {
1313 /* We know we can't do this in 1 insn, and we must be able to do it
1314 in two; so don't mess around looking for sequences that don't buy
1315 us anything. */
1317 {
1321 }
1324 }
1326 /* Remaining cases are all for DImode. */
1337 {
1339 one_match++;
1340 else
1341 {
1345 zero_match++;
1346 }
1347 }
1350 {
1351 /* Set one of the quarters and then insert back into result. */
1354 {
1359 }
1362 }
1369 {
1373 {
1375 {
1380 }
1383 }
1385 {
1387 {
1393 }
1396 }
1398 {
1400 {
1406 }
1409 }
1411 {
1413 {
1418 }
1421 }
1422 }
1424 /* See if we can do it by arithmetically combining two
1425 immediates. */
1427 {
1433 {
1435 {
1441 }
1444 }
1447 {
1449 {
1451 {
1456 }
1459 }
1460 }
1461 }
1463 /* See if we can do it by logically combining two immediates. */
1465 {
1467 {
1472 {
1474 {
1480 }
1483 }
1484 }
1486 {
1491 {
1493 {
1499 }
1502 }
1503 }
1504 }
1507 {
1508 /* Set either first three quarters or all but the third. */
1513 num_insns ++;
1515 /* Now insert other two quarters. */
1518 {
1520 {
1524 num_insns ++;
1525 }
1526 }
1528 }
1530 simple_sequence:
1534 {
1536 {
1538 {
1541 num_insns ++;
1543 }
1544 else
1545 {
1549 num_insns ++;
1550 }
1551 }
1552 }
1555 }
1558 void
1560 {
1565 /* Check on what type of symbol it is. */
1569 {
1573 /* If we have (const (plus symbol offset)), separate out the offset
1574 before we start classifying the symbol. */
1579 {
1583 {
1589 }
1604 {
1610 }
1611 /* FALLTHRU */
1621 }
1622 }
1625 {
1628 else
1629 {
1633 }
1636 }
1639 }
1641 static bool
1643 tree exp ATTRIBUTE_UNUSED)
1644 {
1645 /* Currently, always true. */
1647 }
1649 /* Implement TARGET_PASS_BY_REFERENCE. */
1651 static bool
1653 machine_mode mode,
1654 const_tree type,
1656 {
1657 HOST_WIDE_INT size;
1658 machine_mode dummymode;
1661 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1665 /* Aggregates are passed by reference based on their size. */
1667 {
1669 }
1671 /* Variable sized arguments are always returned by reference. */
1675 /* Can this be a candidate to be passed in fp/simd register(s)? */
1678 NULL))
1681 /* Arguments which are variable sized or larger than 2 registers are
1682 passed by reference unless they are a homogenous floating point
1683 aggregate. */
1685 }
1687 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1688 static bool
1690 {
1691 machine_mode dummy_mode;
1694 /* Never happens in little-endian mode. */
1698 /* Only composite types smaller than or equal to 16 bytes can
1699 be potentially returned in registers. */
1705 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1706 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1707 is always passed/returned in the least significant bits of fp/simd
1708 register(s). */
1714 }
1716 /* Implement TARGET_FUNCTION_VALUE.
1717 Define how to find the value returned by a function. */
1719 static rtx
1722 {
1723 machine_mode mode;
1726 machine_mode ag_mode;
1733 {
1737 {
1740 }
1741 }
1745 {
1747 {
1750 }
1751 else
1752 {
1754 rtx par;
1758 {
1763 }
1765 }
1766 }
1767 else
1769 }
1771 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1772 Return true if REGNO is the number of a hard register in which the values
1773 of called function may come back. */
1775 static bool
1777 {
1778 /* Maximum of 16 bytes can be returned in the general registers. Examples
1779 of 16-byte return values are: 128-bit integers and 16-byte small
1780 structures (excluding homogeneous floating-point aggregates). */
1784 /* Up to four fp/simd registers can return a function value, e.g. a
1785 homogeneous floating-point aggregate having four members. */
1790 }
1792 /* Implement TARGET_RETURN_IN_MEMORY.
1794 If the type T of the result of a function is such that
1795 void func (T arg)
1796 would require that arg be passed as a value in a register (or set of
1797 registers) according to the parameter passing rules, then the result
1798 is returned in the same registers as would be used for such an
1799 argument. */
1801 static bool
1803 {
1804 HOST_WIDE_INT size;
1805 machine_mode ag_mode;
1811 /* Simple scalar types always returned in registers. */
1815 type,
1818 NULL))
1821 /* Types larger than 2 registers returned in memory. */
1824 }
1826 static bool
1829 {
1832 type,
1834 nregs,
1835 NULL);
1836 }
1838 /* Given MODE and TYPE of a function argument, return the alignment in
1839 bits. The idea is to suppress any stronger alignment requested by
1840 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1841 This is a helper function for local use only. */
1843 static unsigned int
1845 {
1849 {
1851 {
1854 else
1856 }
1857 else
1859 }
1860 else
1864 }
1866 /* Layout a function argument according to the AAPCS64 rules. The rule
1867 numbers refer to the rule numbers in the AAPCS64. */
1869 static void
1871 const_tree type,
1873 {
1877 HOST_WIDE_INT size;
1879 /* We need to do this once per argument. */
1885 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
1886 size
1888 UNITS_PER_WORD);
1892 mode,
1893 type,
1896 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
1897 The following code thus handles passing by SIMD/FP registers first. */
1901 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
1902 and homogenous short-vector aggregates (HVA). */
1904 {
1909 {
1912 {
1915 }
1916 else
1917 {
1918 rtx par;
1922 {
1925 tmp = gen_rtx_EXPR_LIST
1929 }
1931 }
1933 }
1934 else
1935 {
1936 /* C.3 NSRN is set to 8. */
1939 }
1940 }
1945 /* C6 - C9. though the sign and zero extension semantics are
1946 handled elsewhere. This is the case where the argument fits
1947 entirely general registers. */
1949 {
1954 /* C.8 if the argument has an alignment of 16 then the NGRN is
1955 rounded up to the next even number. */
1957 {
1960 }
1961 /* NREGS can be 0 when e.g. an empty structure is to be passed.
1962 A reg is still generated for it, but the caller should be smart
1963 enough not to use it. */
1965 {
1967 }
1968 else
1969 {
1970 rtx par;
1975 {
1980 }
1982 }
1986 }
1988 /* C.11 */
1991 /* The argument is passed on stack; record the needed number of words for
1992 this argument and align the total size if necessary. */
1993 on_stack:
1999 }
2001 /* Implement TARGET_FUNCTION_ARG. */
2003 static rtx
2006 {
2015 }
2017 void
2019 const_tree fntype ATTRIBUTE_UNUSED,
2020 rtx libname ATTRIBUTE_UNUSED,
2021 const_tree fndecl ATTRIBUTE_UNUSED,
2023 {
2037 {
2044 }
2046 }
2048 static void
2050 machine_mode mode,
2051 const_tree type,
2053 {
2056 {
2066 }
2067 }
2069 bool
2071 {
2074 }
2076 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2077 PARM_BOUNDARY bits of alignment, but will be given anything up
2078 to STACK_BOUNDARY bits if the type requires it. This makes sure
2079 that both before and after the layout of each argument, the Next
2080 Stacked Argument Address (NSAA) will have a minimum alignment of
2081 8 bytes. */
2083 static unsigned int
2085 {
2093 }
2095 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2097 Return true if an argument passed on the stack should be padded upwards,
2098 i.e. if the least-significant byte of the stack slot has useful data.
2100 Small aggregate types are placed in the lowest memory address.
2102 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2104 bool
2106 {
2107 /* On little-endian targets, the least significant byte of every stack
2108 argument is passed at the lowest byte address of the stack slot. */
2112 /* Otherwise, integral, floating-point and pointer types are padded downward:
2113 the least significant byte of a stack argument is passed at the highest
2114 byte address of the stack slot. */
2121 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2123 }
2125 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2127 It specifies padding for the last (may also be the only)
2128 element of a block move between registers and memory. If
2129 assuming the block is in the memory, padding upward means that
2130 the last element is padded after its highest significant byte,
2131 while in downward padding, the last element is padded at the
2132 its least significant byte side.
2134 Small aggregates and small complex types are always padded
2135 upwards.
2137 We don't need to worry about homogeneous floating-point or
2138 short-vector aggregates; their move is not affected by the
2139 padding direction determined here. Regardless of endianness,
2140 each element of such an aggregate is put in the least
2141 significant bits of a fp/simd register.
2143 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2144 register has useful data, and return the opposite if the most
2145 significant byte does. */
2147 bool
2150 {
2152 /* Small composite types are always padded upward. */
2154 {
2159 }
2161 /* Otherwise, use the default padding. */
2163 }
2165 static machine_mode
2167 {
2169 }
2171 static bool
2173 {
2174 /* In aarch64_override_options_after_change
2175 flag_omit_leaf_frame_pointer turns off the frame pointer by
2176 default. Turn it back on now if we've not got a leaf
2177 function. */
2183 }
2185 /* Mark the registers that need to be saved by the callee and calculate
2186 the size of the callee-saved registers area and frame record (both FP
2187 and LR may be omitted). */
2188 static void
2190 {
2197 #define SLOT_NOT_REQUIRED (-2)
2198 #define SLOT_REQUIRED (-1)
2203 /* First mark all the registers that really need to be saved... */
2210 /* ... that includes the eh data registers (if needed)... */
2216 /* ... and any callee saved register that dataflow says is live. */
2229 {
2230 /* FP and LR are placed in the linkage record. */
2237 }
2239 /* Now assign stack slots for them. */
2242 {
2249 }
2253 {
2261 }
2281 }
2283 static bool
2285 {
2287 }
2289 static unsigned
2291 {
2293 regno ++;
2295 }
2297 static void
2299 HOST_WIDE_INT adjustment)
2300 {
2311 }
2313 static rtx
2315 HOST_WIDE_INT adjustment)
2316 {
2318 {
2329 }
2330 }
2332 static void
2335 {
2345 }
2347 static rtx
2349 HOST_WIDE_INT adjustment)
2350 {
2352 {
2361 }
2362 }
2364 static rtx
2366 rtx reg2)
2367 {
2369 {
2378 }
2379 }
2381 static rtx
2383 rtx mem2)
2384 {
2386 {
2395 }
2396 }
2399 static void
2402 {
2412 {
2414 HOST_WIDE_INT offset;
2424 offset));
2432 {
2434 rtx mem2;
2438 offset));
2440 reg2));
2442 /* The first part of a frame-related parallel insn is
2443 always assumed to be relevant to the frame
2444 calculations; subsequent parts, are only
2445 frame-related if explicitly marked. */
2448 }
2449 else
2453 }
2454 }
2456 static void
2460 {
2466 HOST_WIDE_INT offset;
2471 {
2488 {
2490 rtx mem2;
2498 }
2499 else
2502 }
2503 }
2505 /* AArch64 stack frames generated by this compiler look like:
2507 +-------------------------------+
2508 | |
2509 | incoming stack arguments |
2510 | |
2511 +-------------------------------+
2512 | | <-- incoming stack pointer (aligned)
2513 | callee-allocated save area |
2514 | for register varargs |
2515 | |
2516 +-------------------------------+
2517 | local variables | <-- frame_pointer_rtx
2518 | |
2519 +-------------------------------+
2520 | padding0 | \
2521 +-------------------------------+ |
2522 | callee-saved registers | | frame.saved_regs_size
2523 +-------------------------------+ |
2524 | LR' | |
2525 +-------------------------------+ |
2526 | FP' | / <- hard_frame_pointer_rtx (aligned)
2527 +-------------------------------+
2528 | dynamic allocation |
2529 +-------------------------------+
2530 | padding |
2531 +-------------------------------+
2532 | outgoing stack arguments | <-- arg_pointer
2533 | |
2534 +-------------------------------+
2535 | | <-- stack_pointer_rtx (aligned)
2537 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2538 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2539 unchanged. */
2541 /* Generate the prologue instructions for entry into a function.
2542 Establish the stack frame by decreasing the stack pointer with a
2543 properly calculated size and, if necessary, create a frame record
2544 filled with the values of LR and previous frame pointer. The
2545 current FP is also set up if it is in use. */
2547 void
2549 {
2550 /* sub sp, sp, #<frame_size>
2551 stp {fp, lr}, [sp, #<frame_size> - 16]
2552 add fp, sp, #<frame_size> - hardfp_offset
2553 stp {cs_reg}, [fp, #-16] etc.
2555 sub sp, sp, <final_adjustment_if_any>
2556 */
2559 HOST_WIDE_INT hard_fp_offset;
2571 /* Store pairs and load pairs have a range only -512 to 504. */
2573 {
2574 /* When the frame has a large size, an initial decrease is done on
2575 the stack pointer to jump over the callee-allocated save area for
2576 register varargs, the local variable area and/or the callee-saved
2577 register area. This will allow the pre-index write-back
2578 store pair instructions to be used for setting up the stack frame
2579 efficiently. */
2588 {
2598 }
2600 {
2605 {
2609 }
2611 {
2615 }
2616 }
2617 }
2618 else
2622 {
2626 {
2630 {
2637 }
2638 else
2641 /* Set up frame pointer to point to the location of the
2642 previous frame pointer on the stack. */
2644 stack_pointer_rtx,
2648 }
2649 else
2650 {
2658 {
2662 }
2663 else
2664 {
2671 else
2673 }
2674 }
2677 skip_wb);
2679 skip_wb);
2680 }
2682 /* when offset >= 512,
2683 sub sp, sp, #<outgoing_args_size> */
2685 {
2687 {
2692 }
2693 }
2694 }
2696 /* Return TRUE if we can use a simple_return insn.
2698 This function checks whether the callee saved stack is empty, which
2699 means no restore actions are need. The pro_and_epilogue will use
2700 this to check whether shrink-wrapping opt is feasible. */
2702 bool
2704 {
2714 }
2716 /* Generate the epilogue instructions for returning from a function. */
2717 void
2719 {
2721 HOST_WIDE_INT fp_offset;
2722 HOST_WIDE_INT hard_fp_offset;
2724 /* We need to add memory barrier to prevent read from deallocated stack. */
2734 /* Store pairs and load pairs have a range only -512 to 504. */
2736 {
2744 {
2749 }
2750 }
2751 else
2754 /* If there were outgoing arguments or we've done dynamic stack
2755 allocation, then restore the stack pointer from the frame
2756 pointer. This is at most one insn and more efficient than using
2757 GCC's internal mechanism. */
2760 {
2765 hard_frame_pointer_rtx,
2768 }
2771 {
2794 {
2800 {
2805 }
2806 else
2807 {
2814 }
2815 }
2816 else
2817 {
2820 }
2822 /* Reset the CFA to be SP + FRAME_SIZE. */
2829 }
2832 {
2837 {
2841 }
2842 else
2843 {
2848 {
2853 }
2856 }
2858 /* Reset the CFA to be SP + 0. */
2861 }
2863 /* Stack adjustment for exception handler. */
2865 {
2866 /* We need to unwind the stack by the offset computed by
2867 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
2868 to be SP; letting the CFA move during this adjustment
2869 is just as correct as retaining the CFA from the body
2870 of the function. Therefore, do nothing special. */
2872 }
2877 }
2879 /* Return the place to copy the exception unwinding return address to.
2880 This will probably be a stack slot, but could (in theory be the
2881 return register). */
2882 rtx
2884 {
2885 HOST_WIDE_INT fp_offset;
2895 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
2896 result in a store to save LR introduced by builtin_eh_return () being
2897 incorrectly deleted because the alias is not detected.
2898 So in the calculation of the address to copy the exception unwinding
2899 return address to, we note 2 cases.
2900 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
2901 we return a SP-relative location since all the addresses are SP-relative
2902 in this case. This prevents the store from being optimized away.
2903 If the fp_offset is not 0, then the addresses will be FP-relative and
2904 therefore we return a FP-relative location. */
2907 {
2911 else
2914 }
2916 /* If FP is not needed, we calculate the location of LR, which would be
2917 at the top of the saved registers block. */
2921 stack_pointer_rtx,
2922 fp_offset
2925 }
2927 /* Possibly output code to build up a constant in a register. For
2928 the benefit of the costs infrastructure, returns the number of
2929 instructions which would be emitted. GENERATE inhibits or
2930 enables code generation. */
2932 static int
2934 {
2938 {
2942 }
2943 else
2944 {
2949 HOST_WIDE_INT valm;
2950 HOST_WIDE_INT tval;
2953 {
2963 }
2965 /* zcount contains the number of additional MOVK instructions
2966 required if the constant is built up with an initial MOVZ instruction,
2967 while ncount is the number of MOVK instructions required if starting
2968 with a MOVN instruction. Choose the sequence that yields the fewest
2969 number of instructions, preferring MOVZ instructions when they are both
2970 the same. */
2972 {
2977 insns++;
2978 }
2979 else
2980 {
2985 insns++;
2986 }
2991 {
2993 {
2998 insns++;
2999 }
3001 }
3002 }
3004 }
3006 static void
3008 {
3017 {
3020 }
3022 {
3024 {
3030 else
3033 }
3035 {
3039 }
3040 }
3041 }
3043 /* Output code to add DELTA to the first argument, and then jump
3044 to FUNCTION. Used for C++ multiple inheritance. */
3045 static void
3047 HOST_WIDE_INT delta,
3048 HOST_WIDE_INT vcall_offset,
3049 tree function)
3050 {
3051 /* The this pointer is always in x0. Note that this differs from
3052 Arm where the this pointer maybe bumped to r1 if r0 is required
3053 to return a pointer to an aggregate. On AArch64 a result value
3054 pointer will be in x8. */
3064 else
3065 {
3074 {
3078 else
3080 }
3084 else
3091 else
3092 {
3095 }
3099 else
3105 }
3107 /* Generate a tail call to the target function. */
3109 {
3112 }
3124 /* Stop pretending to be a post-reload pass. */
3126 }
3128 static bool
3130 {
3135 {
3139 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3140 TLS offsets, not real symbol references. */
3143 }
3145 }
3148 static int
3150 {
3159 }
3162 static void
3164 {
3170 {
3174 else
3177 {
3179 {
3180 /* set s consecutive bits to 1 (s < 64) */
3182 /* rotate right by r */
3185 /* replicate the constant depending on SIMD size */
3196 }
3199 }
3200 }
3201 }
3205 aarch64_bitmasks_cmp);
3206 }
3209 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3210 a left shift of 0 or 12 bits. */
3211 bool
3213 {
3216 );
3217 }
3220 /* Return true if val is an immediate that can be loaded into a
3221 register by a MOVZ instruction. */
3222 static bool
3224 {
3226 {
3230 }
3231 else
3232 {
3233 /* Ignore sign extension. */
3235 }
3238 }
3241 /* Return true if val is a valid bitmask immediate. */
3242 bool
3244 {
3246 {
3247 /* Replicate bit pattern. */
3250 }
3253 }
3256 /* Return true if val is an immediate that can be loaded into a
3257 register in a single instruction. */
3258 bool
3260 {
3264 }
3266 static bool
3268 {
3276 {
3280 else
3281 /* Avoid generating a 64-bit relocation in ILP32; leave
3282 to aarch64_expand_mov_immediate to handle it properly. */
3284 }
3287 }
3289 /* Return true if register REGNO is a valid index register.
3290 STRICT_P is true if REG_OK_STRICT is in effect. */
3292 bool
3294 {
3296 {
3304 }
3306 }
3308 /* Return true if register REGNO is a valid base register for mode MODE.
3309 STRICT_P is true if REG_OK_STRICT is in effect. */
3311 bool
3313 {
3315 {
3323 }
3325 /* The fake registers will be eliminated to either the stack or
3326 hard frame pointer, both of which are usually valid base registers.
3327 Reload deals with the cases where the eliminated form isn't valid. */
3332 }
3334 /* Return true if X is a valid base register for mode MODE.
3335 STRICT_P is true if REG_OK_STRICT is in effect. */
3337 static bool
3339 {
3344 }
3346 /* Return true if address offset is a valid index. If it is, fill in INFO
3347 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3349 static bool
3352 {
3354 rtx index;
3357 /* (reg:P) */
3360 {
3364 }
3365 /* (sign_extend:DI (reg:SI)) */
3370 {
3375 }
3376 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3383 {
3388 }
3389 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3396 {
3401 }
3402 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3409 {
3417 }
3418 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3419 (const_int 0xffffffff<<shift)) */
3426 {
3432 }
3433 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3440 {
3448 }
3449 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3450 (const_int 0xffffffff<<shift)) */
3457 {
3463 }
3464 /* (mult:P (reg:P) (const_int scale)) */
3469 {
3473 }
3474 /* (ashift:P (reg:P) (const_int shift)) */
3479 {
3483 }
3484 else
3495 {
3500 }
3503 }
3505 bool
3507 {
3511 }
3515 HOST_WIDE_INT offset)
3516 {
3518 }
3522 {
3526 }
3528 /* Return true if X is a valid address for machine mode MODE. If it is,
3529 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3530 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3532 static bool
3536 {
3540 /* On BE, we use load/store pair for all large int mode load/stores. */
3542 || (BYTES_BIG_ENDIAN
3546 !load_store_pair_p
3550 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3551 REG addressing. */
3557 {
3575 {
3581 }
3586 {
3593 /* TImode and TFmode values are allowed in both pairs of X
3594 registers and individual Q registers. The available
3595 address modes are:
3596 X,X: 7-bit signed scaled offset
3597 Q: 9-bit signed offset
3598 We conservatively require an offset representable in either mode.
3599 */
3604 /* A 7bit offset check because OImode will emit a ldp/stp
3605 instruction (only big endian will get here).
3606 For ldp/stp instructions, the offset is scaled for the size of a
3607 single element of the pair. */
3611 /* Three 9/12 bit offsets checks because CImode will emit three
3612 ldr/str instructions (only big endian will get here). */
3619 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3620 instructions (only big endian will get here). */
3629 else
3632 }
3635 {
3636 /* Look for base + (scaled/extended) index register. */
3639 {
3642 }
3645 {
3648 }
3649 }
3670 {
3671 HOST_WIDE_INT offset;
3675 /* TImode and TFmode values are allowed in both pairs of X
3676 registers and individual Q registers. The available
3677 address modes are:
3678 X,X: 7-bit signed scaled offset
3679 Q: 9-bit signed offset
3680 We conservatively require an offset representable in either mode.
3681 */
3689 else
3691 }
3697 /* load literal: pc-relative constant pool entry. Only supported
3698 for SI mode or larger. */
3702 {
3709 }
3718 {
3724 {
3725 /* The symbol and offset must be aligned to the access size. */
3732 {
3736 }
3742 else
3751 }
3752 }
3757 }
3758 }
3760 bool
3762 {
3763 rtx offset;
3767 }
3769 /* Classify the base of symbolic expression X, given that X appears in
3770 context CONTEXT. */
3772 enum aarch64_symbol_type
3775 {
3776 rtx offset;
3780 }
3783 /* Return TRUE if X is a legitimate address for accessing memory in
3784 mode MODE. */
3785 static bool
3787 {
3791 }
3793 /* Return TRUE if X is a legitimate address for accessing memory in
3794 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
3795 pair operation. */
3796 bool
3799 {
3803 }
3805 /* Return TRUE if rtx X is immediate constant 0.0 */
3806 bool
3808 {
3809 REAL_VALUE_TYPE r;
3818 }
3820 /* Return the fixed registers used for condition codes. */
3822 static bool
3824 {
3828 }
3830 /* Emit call insn with PAT and do aarch64-specific handling. */
3832 void
3834 {
3840 }
3842 machine_mode
3844 {
3845 /* All floating point compares return CCFP if it is an equality
3846 comparison, and CCFPE otherwise. */
3848 {
3850 {
3871 }
3872 }
3881 /* A compare with a shifted operand. Because of canonicalization,
3882 the comparison will have to be swapped when we emit the assembly
3883 code. */
3891 /* Similarly for a negated operand, but we can only do this for
3892 equalities. */
3899 /* A compare of a mode narrower than SI mode against zero can be done
3900 by extending the value in the comparison. */
3903 /* Only use sign-extension if we really need it. */
3907 /* For everything else, return CCmode. */
3909 }
3911 static int
3914 int
3916 {
3923 }
3925 static int
3927 {
3930 {
3934 {
3948 }
4003 {
4015 }
4022 {
4034 }
4039 {
4045 }
4050 {
4054 }
4060 }
4069 }
4071 bool
4073 HOST_WIDE_INT minval,
4074 HOST_WIDE_INT maxval)
4075 {
4076 HOST_WIDE_INT firstval;
4093 }
4095 bool
4097 {
4099 }
4101 static unsigned
4103 {
4107 {
4108 count++;
4110 }
4113 }
4115 /* N Z C V. */
4116 #define AARCH64_CC_V 1
4117 #define AARCH64_CC_C (1 << 1)
4118 #define AARCH64_CC_Z (1 << 2)
4119 #define AARCH64_CC_N (1 << 3)
4121 /* N Z C V flags for ccmp. The first code is for AND op and the other
4122 is for IOR op. Indexed by AARCH64_COND_CODE. */
4124 {
4141 };
4143 int
4145 {
4147 {
4180 }
4181 }
4184 void
4186 {
4188 {
4189 /* An integer or symbol address without a preceding # sign. */
4192 {
4204 {
4207 }
4208 /* Fall through. */
4212 }
4216 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4217 {
4222 {
4225 }
4228 {
4241 }
4242 }
4246 {
4249 /* Print N such that 2^N == X. */
4251 {
4254 }
4257 }
4261 /* Print the number of non-zero bits in X (a const_int). */
4263 {
4266 }
4272 /* Print the higher numbered register of a pair (TImode) of regs. */
4274 {
4277 }
4283 {
4285 /* Print a condition (eq, ne, etc). */
4287 /* CONST_TRUE_RTX means always -- that's the default. */
4292 {
4295 }
4300 }
4304 {
4306 /* Print the inverse of a condition (eq <-> ne, etc). */
4308 /* CONST_TRUE_RTX means never -- that's the default. */
4310 {
4313 }
4316 {
4319 }
4324 }
4332 /* Print a scalar FP/SIMD register name. */
4334 {
4335 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4337 }
4345 /* Print the first FP/SIMD register name in a list. */
4347 {
4348 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4350 }
4355 /* Print a scalar FP/SIMD register name + 1. */
4357 {
4358 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4360 }
4365 /* Print bottom 16 bits of integer constant in hex. */
4367 {
4370 }
4376 /* Print a general register name or the zero register (32-bit or
4377 64-bit). */
4380 {
4383 }
4386 {
4389 }
4392 {
4395 }
4397 /* Fall through */
4400 /* Print a normal operand, if it's a general register, then we
4401 assume DImode. */
4403 {
4406 }
4409 {
4430 {
4433 HOST_WIDE_INT_MIN,
4434 HOST_WIDE_INT_MAX));
4436 }
4438 {
4440 }
4441 else
4446 /* CONST_DOUBLE can represent a double-width integer.
4447 In this case, the mode of x is VOIDmode. */
4451 {
4454 }
4456 {
4457 #define buf_size 20
4459 REAL_VALUE_TYPE r;
4466 #undef buf_size
4467 }
4473 }
4481 {
4508 }
4514 {
4541 }
4548 {
4554 }
4559 {
4561 /* Print nzcv. */
4564 {
4567 }
4572 }
4576 {
4578 /* Print nzcv. */
4581 {
4584 }
4589 }
4595 }
4596 }
4598 void
4600 {
4606 {
4610 else
4619 else
4628 else
4637 else
4644 {
4671 }
4682 }
4685 }
4687 bool
4689 {
4696 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4697 referencing instruction, but they are constant offsets, not
4698 symbols. */
4704 {
4706 {
4712 }
4715 }
4718 }
4720 /* Implement REGNO_REG_CLASS. */
4722 enum reg_class
4724 {
4739 }
4741 static rtx
4743 {
4744 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
4745 where mask is selected by alignment and size of the offset.
4746 We try to pick as large a range for the offset as possible to
4747 maximize the chance of a CSE. However, for aligned addresses
4748 we limit the range to 4k so that structures with different sized
4749 elements are likely to use the same base. */
4752 {
4754 HOST_WIDE_INT base_offset;
4756 /* Does it look like we'll need a load/store-pair operation? */
4761 /* For offsets aren't a multiple of the access size, the limit is
4762 -256...255. */
4765 else
4774 NULL_RTX);
4777 }
4780 }
4782 /* Try a machine-dependent way of reloading an illegitimate address
4783 operand. If we find one, push the reload and return the new rtx. */
4785 rtx
4787 machine_mode mode,
4790 {
4793 /* Do not allow mem (plus (reg, const)) if vector struct mode. */
4798 {
4805 }
4807 /* We must recognize output that we have already generated ourselves. */
4813 {
4818 }
4820 /* We wish to handle large displacements off a base register by splitting
4821 the addend across an add and the mem insn. This can cut the number of
4822 extra insns needed from 3 to 1. It is only useful for load/store of a
4823 single register with 12 bit offset field. */
4831 {
4835 HOST_WIDE_INT offs;
4836 rtx cst;
4839 /* In ILP32, xmode can be either DImode or SImode. */
4842 /* Reload non-zero BLKmode offsets. This is because we cannot ascertain
4843 BLKmode alignment. */
4849 /* Align misaligned offset by adjusting high part to compensate. */
4851 {
4853 {
4854 /* Align down. */
4857 }
4858 else
4859 {
4860 /* Align up. */
4865 }
4866 }
4868 /* Check for overflow. */
4876 /* Reload high part into base reg, leaving the low part
4877 in the mem instruction.
4878 Note that replacing this gen_rtx_PLUS with plus_constant is
4879 wrong in this case because we rely on the
4880 (plus (plus reg c1) c2) structure being preserved so that
4881 XEXP (*p, 0) in push_reload below uses the correct term. */
4890 }
4893 }
4896 static reg_class_t
4898 reg_class_t rclass,
4899 machine_mode mode,
4901 {
4902 /* Without the TARGET_SIMD instructions we cannot move a Q register
4903 to a Q register directly. We need a scratch. */
4907 {
4913 }
4915 /* A TFmode or TImode memory access should be handled via an FP_REGS
4916 because AArch64 has richer addressing modes for LDR/STR instructions
4917 than LDP/STP instructions. */
4926 }
4928 static bool
4930 {
4931 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
4932 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
4935 {
4947 }
4948 else
4949 {
4950 /* If we decided that we didn't need a leaf frame pointer but then used
4951 LR in the function, then we'll want a frame pointer after all, so
4952 prevent this elimination to ensure a frame pointer is used. */
4954 && flag_omit_leaf_frame_pointer
4957 }
4960 }
4962 HOST_WIDE_INT
4964 {
4968 {
4975 }
4978 {
4982 }
4985 }
4987 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
4988 previous frame. */
4990 rtx
4992 {
4996 }
4999 static void
5001 {
5003 {
5006 }
5007 else
5008 {
5011 }
5016 }
5018 static void
5020 {
5024 /* Don't need to copy the trailing D-words, we fill those in below. */
5036 /* XXX We should really define a "clear_cache" pattern and use
5037 gen_clear_cache(). */
5042 ptr_mode);
5043 }
5045 static unsigned char
5047 {
5049 {
5056 return
5068 }
5070 }
5072 static reg_class_t
5074 {
5079 {
5085 }
5087 /* If it's an integer immediate that MOVI can't handle, then
5088 FP_REGS is not an option, so we return NO_REGS instead. */
5093 /* Register eliminiation can result in a request for
5094 SP+constant->FP_REGS. We cannot support such operations which
5095 use SP as source and an FP_REG as destination, so reject out
5096 right now. */
5098 {
5101 /* Look through a possible SUBREG introduced by ILP32. */
5107 POINTER_REGS));
5109 }
5112 }
5114 void
5116 {
5118 }
5120 static void
5122 {
5125 else
5126 {
5134 }
5135 }
5137 static void
5139 {
5142 else
5143 {
5151 }
5152 }
5156 {
5162 {
5163 {
5166 },
5167 {
5170 },
5171 {
5174 },
5175 /* We assume that DImode is only generated when not optimizing and
5176 that we don't really need 64-bit address offsets. That would
5177 imply an object file with 8GB of code in a single function! */
5178 {
5181 }
5182 };
5190 /* Need to implement table size reduction, by chaning the code below. */
5200 }
5203 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5204 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5205 operator. */
5207 int
5209 {
5211 {
5214 {
5218 }
5219 }
5221 }
5223 static bool
5225 const_rtx x ATTRIBUTE_UNUSED)
5226 {
5227 /* We can't use blocks for constants when we're using a per-function
5228 constant pool. */
5230 }
5234 rtx x ATTRIBUTE_UNUSED,
5236 {
5237 /* Force all constant pool entries into the current function section. */
5239 }
5242 /* Costs. */
5244 /* Helper function for rtx cost calculation. Strip a shift expression
5245 from X. Returns the inner operand if successful, or the original
5246 expression on failure. */
5247 static rtx
5249 {
5252 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5253 we can convert both to ROR during final output. */
5268 }
5270 /* Helper function for rtx cost calculation. Strip an extend
5271 expression from X. Returns the inner operand if successful, or the
5272 original expression on failure. We deal with a number of possible
5273 canonicalization variations here. */
5274 static rtx
5276 {
5279 /* Zero and sign extraction of a widened value. */
5287 /* It can also be represented (for zero-extend) as an AND with an
5288 immediate. */
5297 /* Now handle extended register, as this may also have an optional
5298 left shift by 1..4. */
5312 }
5314 /* Return true iff CODE is a shift supported in combination
5315 with arithmetic instructions. */
5317 static bool
5319 {
5321 }
5323 /* Helper function for rtx cost calculation. Calculate the cost of
5324 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5325 Return the calculated cost of the expression, recursing manually in to
5326 operands where needed. */
5328 static int
5330 {
5346 /* Integer multiply/fma. */
5348 {
5349 /* The multiply will be canonicalized as a shift, cost it as such. */
5353 {
5357 {
5359 {
5361 /* ARITH + shift-by-register. */
5364 /* ARITH + extended register. We don't have a cost field
5365 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5367 else
5368 /* ARITH + shift-by-immediate. */
5370 }
5371 else
5372 /* LSL (immediate). */
5375 }
5376 /* Strip extends as we will have costed them in the case above. */
5383 }
5385 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5386 compound and let the below cases handle it. After all, MNEG is a
5387 special-case alias of MSUB. */
5389 {
5392 }
5394 /* Integer multiplies or FMAs have zero/sign extending variants. */
5399 {
5404 {
5406 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5408 else
5409 /* MUL/SMULL/UMULL. */
5411 }
5414 }
5416 /* This is either an integer multiply or a MADD. In both cases
5417 we want to recurse and cost the operands. */
5422 {
5424 /* MADD/MSUB. */
5426 else
5427 /* MUL. */
5429 }
5432 }
5433 else
5434 {
5436 {
5437 /* Floating-point FMA/FMUL can also support negations of the
5438 operands. */
5445 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5447 else
5448 /* FMUL/FNMUL. */
5450 }
5455 }
5456 }
5458 static int
5460 machine_mode mode,
5461 addr_space_t as ATTRIBUTE_UNUSED,
5463 {
5471 {
5473 {
5474 /* This is a CONST or SYMBOL ref which will be split
5475 in a different way depending on the code model in use.
5476 Cost it through the generic infrastructure. */
5478 /* Divide through by the cost of one instruction to
5479 bring it to the same units as the address costs. */
5481 /* The cost is then the cost of preparing the address,
5482 followed by an immediate (possibly 0) offset. */
5484 }
5485 else
5486 {
5487 /* This is most likely a jump table from a case
5488 statement. */
5490 }
5491 }
5494 {
5506 else
5522 }
5526 {
5527 /* For the sake of calculating the cost of the shifted register
5528 component, we can treat same sized modes in the same way. */
5530 {
5543 /* We can't tell, or this is a 128-bit vector. */
5547 }
5548 }
5551 }
5553 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5554 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5555 to be taken. */
5557 int
5559 {
5560 /* When optimizing for speed, use the cost of unpredictable branches. */
5566 else
5568 }
5570 /* Return true if the RTX X in mode MODE is a zero or sign extract
5571 usable in an ADD or SUB (extended register) instruction. */
5572 static bool
5574 {
5575 /* Catch add with a sign extract.
5576 This is add_<optab><mode>_multp2. */
5579 {
5590 op1))
5591 {
5593 }
5594 }
5597 }
5599 static bool
5601 {
5603 {
5615 }
5616 }
5618 /* Return true iff X is an rtx that will match an extr instruction
5619 i.e. as described in the *extr<mode>5_insn family of patterns.
5620 OP0 and OP1 will be set to the operands of the shifts involved
5621 on success and will be NULL_RTX otherwise. */
5623 static bool
5625 {
5640 {
5641 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5653 {
5657 }
5658 }
5661 }
5663 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5664 storing it in *COST. Result is true if the total cost of the operation
5665 has now been calculated. */
5666 static bool
5668 {
5669 rtx inner;
5670 rtx comparator;
5674 {
5678 }
5679 else
5680 {
5684 }
5687 {
5688 /* Conditional branch. */
5691 else
5692 {
5694 {
5696 {
5697 /* TBZ/TBNZ/CBZ/CBNZ. */
5699 /* TBZ/TBNZ. */
5702 else
5703 /* CBZ/CBNZ. */
5707 }
5708 }
5710 {
5711 /* TBZ/TBNZ. */
5714 }
5715 }
5716 }
5718 {
5719 /* It's a conditional operation based on the status flags,
5720 so it must be some flavor of CSEL. */
5722 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
5731 }
5733 /* We don't know what this is, cost all operands. */
5735 }
5737 /* Calculate the cost of calculating X, storing it in *COST. Result
5738 is true if the total cost of the operation has now been calculated. */
5739 static bool
5742 {
5748 /* By default, assume that everything has equivalent cost to the
5749 cheapest instruction. Any additional costs are applied as a delta
5750 above this default. */
5754 {
5756 /* The cost depends entirely on the operands to SET. */
5762 {
5765 {
5779 }
5788 /* Fall through. */
5790 /* The cost is one per vector-register copied. */
5792 {
5796 }
5797 /* const0_rtx is in general free, but we will use an
5798 instruction to set a register to 0. */
5800 {
5801 /* The cost is 1 per register copied. */
5805 }
5806 else
5807 /* Cost is just the cost of the RHS of the set. */
5813 /* Bit-field insertion. Strip any redundant widening of
5814 the RHS to meet the width of the target. */
5825 {
5826 /* MOV immediate is assumed to always be cheap. */
5828 }
5829 else
5830 {
5831 /* BFM. */
5835 }
5840 /* We can't make sense of this, assume default cost. */
5843 }
5847 /* If an instruction can incorporate a constant within the
5848 instruction, the instruction's expression avoids calling
5849 rtx_cost() on the constant. If rtx_cost() is called on a
5850 constant, then it is usually because the constant must be
5851 moved into a register by one or more instructions.
5853 The exception is constant 0, which can be expressed
5854 as XZR/WZR and is therefore free. The exception to this is
5855 if we have (set (reg) (const0_rtx)) in which case we must cost
5856 the move. However, we can catch that when we cost the SET, so
5857 we don't need to consider that here. */
5860 else
5861 {
5862 /* To an approximation, building any other constant is
5863 proportionally expensive to the number of instructions
5864 required to build that constant. This is true whether we
5865 are compiling for SPEED or otherwise. */
5868 }
5873 {
5874 /* mov[df,sf]_aarch64. */
5876 /* FMOV (scalar immediate). */
5879 {
5880 /* This will be a load from memory. */
5883 else
5885 }
5886 else
5887 /* Otherwise this is +0.0. We get this using MOVI d0, #0
5888 or MOV v0.s[0], wzr - neither of which are modeled by the
5889 cost tables. Just use the default cost. */
5890 {
5891 }
5892 }
5898 {
5899 /* For loads we want the base cost of a load, plus an
5900 approximation for the additional cost of the addressing
5901 mode. */
5915 }
5923 {
5925 {
5926 /* FNEG. */
5928 }
5930 }
5933 {
5936 {
5937 /* CSETM. */
5940 }
5942 /* Cost this as SUB wzr, X. */
5946 }
5949 {
5950 /* Support (neg(fma...)) as a single instruction only if
5951 sign of zeros is unimportant. This matches the decision
5952 making in aarch64.md. */
5954 {
5955 /* FNMADD. */
5958 }
5960 /* FNEG. */
5963 }
5970 {
5973 else
5975 }
5985 {
5988 }
5991 {
5992 /* TODO: A write to the CC flags possibly costs extra, this
5993 needs encoding in the cost tables. */
5995 /* CC_ZESWPmode supports zero extend for free. */
5999 /* ANDS. */
6001 {
6004 }
6007 {
6008 /* ADDS (and CMN alias). */
6011 }
6014 {
6015 /* SUBS. */
6018 }
6021 {
6022 /* CMN. */
6029 }
6031 /* CMP.
6033 Compare can freely swap the order of operands, and
6034 canonicalization puts the more complex operation first.
6035 But the integer MINUS logic expects the shift/extend
6036 operation in op1. */
6039 {
6042 }
6044 }
6047 {
6048 /* FCMP. */
6053 {
6055 /* FCMP supports constant 0.0 for no extra cost. */
6057 }
6059 }
6062 {
6063 /* Vector compare. */
6068 {
6069 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6070 cost. */
6072 }
6074 }
6078 {
6082 cost_minus:
6085 /* Detect valid immediates. */
6091 {
6093 /* SUB(S) (immediate). */
6096 }
6098 /* Look for SUB (extended register). */
6100 {
6108 }
6112 /* Cost this as an FMA-alike operation. */
6116 {
6119 speed);
6121 }
6126 {
6128 {
6129 /* Vector SUB. */
6131 }
6133 {
6134 /* SUB(S). */
6136 }
6138 {
6139 /* FSUB. */
6141 }
6142 }
6144 }
6147 {
6148 rtx new_op0;
6153 cost_plus:
6156 {
6157 /* CSINC. */
6161 }
6166 {
6170 /* ADD (immediate). */
6173 }
6177 /* Look for ADD (extended register). */
6179 {
6187 }
6189 /* Strip any extend, leave shifts behind as we will
6190 cost them through mult_cost. */
6195 {
6197 speed);
6199 }
6204 {
6206 {
6207 /* Vector ADD. */
6209 }
6211 {
6212 /* ADD. */
6214 }
6216 {
6217 /* FADD. */
6219 }
6220 }
6222 }
6228 {
6231 else
6233 }
6238 {
6242 {
6245 else
6247 }
6249 }
6252 {
6259 }
6260 /* Fall through. */
6263 cost_logic:
6268 {
6272 }
6280 {
6281 /* This is a UBFM/SBFM. */
6286 }
6289 {
6290 /* We possibly get the immediate for free, this is not
6291 modelled. */
6294 {
6301 }
6302 else
6303 {
6306 /* Handle ORN, EON, or BIC. */
6312 /* If we had a shift on op0 then this is a logical-shift-
6313 by-register/immediate operation. Otherwise, this is just
6314 a logical operation. */
6316 {
6318 {
6319 /* Shift by immediate. */
6322 else
6324 }
6325 else
6327 }
6329 /* In both cases we want to cost both operands. */
6334 }
6335 }
6343 {
6344 /* Vector NOT. */
6347 }
6349 /* MVN-shifted-reg. */
6351 {
6358 }
6359 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6360 Handle the second form here taking care that 'a' in the above can
6361 be a shift. */
6363 {
6372 {
6375 else
6377 }
6380 }
6381 /* MVN. */
6390 /* If a value is written in SI mode, then zero extended to DI
6391 mode, the operation will in general be free as a write to
6392 a 'w' register implicitly zeroes the upper bits of an 'x'
6393 register. However, if this is
6395 (set (reg) (zero_extend (reg)))
6397 we must cost the explicit register move. */
6401 {
6405 /* MOV. */
6407 else
6408 /* Free, the cost is that of the SI mode operation. */
6412 }
6414 {
6415 /* All loads can zero extend to any size for free. */
6418 }
6421 {
6423 {
6424 /* UMOV. */
6426 }
6427 else
6428 {
6429 /* UXTB/UXTH. */
6431 }
6432 }
6437 {
6438 /* LDRSH. */
6440 {
6447 }
6449 }
6452 {
6455 else
6457 }
6465 {
6467 {
6469 {
6470 /* Vector shift (immediate). */
6472 }
6473 else
6474 {
6475 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6476 aliases. */
6478 }
6479 }
6481 /* We can incorporate zero/sign extend for free. */
6488 }
6489 else
6490 {
6492 {
6494 {
6495 /* Vector shift (register). */
6497 }
6498 else
6499 {
6500 /* LSLV. */
6502 }
6503 }
6505 }
6515 {
6516 /* ASR (immediate) and friends. */
6518 {
6521 else
6523 }
6527 }
6528 else
6529 {
6531 /* ASR (register) and friends. */
6533 {
6536 else
6538 }
6540 }
6546 {
6547 /* LDR. */
6550 }
6553 {
6554 /* ADRP, followed by ADD. */
6558 }
6561 {
6562 /* ADR. */
6565 }
6568 {
6569 /* One extra load instruction, after accessing the GOT. */
6573 }
6578 /* ADRP/ADD (immediate). */
6585 /* UBFX/SBFX. */
6587 {
6590 else
6592 }
6594 /* We can trust that the immediates used will be correct (there
6595 are no by-register forms), so we need only cost op0. */
6601 /* aarch64_rtx_mult_cost always handles recursion to its
6602 operands. */
6608 {
6620 }
6627 {
6631 /* There is no integer SQRT, so only DIV and UDIV can get
6632 here. */
6634 else
6636 }
6662 {
6665 else
6667 }
6669 /* FMSUB, FNMADD, and FNMSUB are free. */
6676 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
6677 and the by-element operand as operand 0. */
6681 /* Catch vector-by-element operations. The by-element operand can
6682 either be (vec_duplicate (vec_select (x))) or just
6683 (vec_select (x)), depending on whether we are multiplying by
6684 a vector or a scalar.
6686 Canonicalization is not very good in these cases, FMA4 will put the
6687 by-element operand as operand 0, FNMA4 will have it as operand 1. */
6698 /* If the remaining parameters are not registers,
6699 get the cost to put them into registers. */
6713 {
6715 {
6716 /*Vector truncate. */
6718 }
6719 else
6721 }
6726 {
6728 {
6729 /*Vector conversion. */
6731 }
6732 else
6734 }
6740 /* Strip the rounding part. They will all be implemented
6741 by the fcvt* family of instructions anyway. */
6743 {
6752 }
6755 {
6758 else
6760 }
6766 {
6767 /* ABS (vector). */
6770 }
6772 {
6775 /* FABD, which is analogous to FADD. */
6777 {
6784 }
6785 /* Simple FABS is analogous to FNEG. */
6788 }
6789 else
6790 {
6791 /* Integer ABS will either be split to
6792 two arithmetic instructions, or will be an ABS
6793 (scalar), which we don't model. */
6797 }
6803 {
6806 else
6807 {
6808 /* FMAXNM/FMINNM/FMAX/FMIN.
6809 TODO: This may not be accurate for all implementations, but
6810 we do not model this in the cost tables. */
6812 }
6813 }
6817 /* The floating point round to integer frint* instructions. */
6819 {
6824 }
6827 {
6832 }
6837 /* Decompose <su>muldi3_highpart. */
6839 mode == DImode
6840 /* (lshiftrt:TI */
6843 /* (mult:TI */
6845 /* (ANY_EXTEND:TI (reg:DI))
6846 (ANY_EXTEND:TI (reg:DI))) */
6853 /* (const_int 64) */
6856 {
6857 /* UMULH/SMULH. */
6865 }
6867 /* Fall through. */
6870 }
6877 }
6879 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
6880 calculated for X. This cost is stored in *COST. Returns true
6881 if the total cost of X was calculated. */
6882 static bool
6885 {
6889 {
6894 }
6897 }
6899 static int
6902 {
6908 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
6915 /* Moving between GPR and stack cost is the same as GP2GP. */
6920 /* To/From the stack register, we move via the gprs. */
6926 {
6927 /* 128-bit operations on general registers require 2 instructions. */
6935 /* When AdvSIMD instructions are disabled it is not possible to move
6936 a 128-bit value directly between Q registers. This is handled in
6937 secondary reload. A general register is used as a scratch to move
6938 the upper DI value and the lower DI value is moved directly,
6939 hence the cost is the sum of three moves. */
6944 }
6954 }
6956 static int
6958 reg_class_t rclass ATTRIBUTE_UNUSED,
6960 {
6962 }
6964 /* Return the number of instructions that can be issued per cycle. */
6965 static int
6967 {
6969 }
6971 static int
6973 {
6977 }
6979 /* Vectorizer cost model target hooks. */
6981 /* Implement targetm.vectorize.builtin_vectorization_cost. */
6982 static int
6984 tree vectype,
6986 {
6990 {
7037 }
7038 }
7040 /* Implement targetm.vectorize.add_stmt_cost. */
7041 static unsigned
7045 {
7050 {
7055 /* Statements in an inner loop relative to the loop being
7056 vectorized are weighted more heavily. The value here is
7057 a function (linear for now) of the loop nest level. */
7059 {
7065 }
7069 }
7072 }
7076 /* Parse the architecture extension string. */
7078 static void
7080 {
7081 /* The extension string is parsed left to right. */
7084 /* Flag to say whether we are adding or removing an extension. */
7088 {
7092 str++;
7097 else
7101 {
7105 }
7110 {
7114 }
7116 /* Scan over the extensions table trying to find an exact match. */
7118 {
7120 {
7121 /* Add or remove the extension. */
7124 else
7127 }
7128 }
7131 {
7132 /* Extension not found in list. */
7135 }
7138 };
7141 }
7143 /* Parse the ARCH string. */
7145 static void
7147 {
7159 else
7163 {
7166 }
7168 /* Loop through the list of supported ARCHs to find a match. */
7170 {
7172 {
7180 {
7181 /* ARCH string contains at least one extension. */
7183 }
7186 {
7189 }
7192 }
7193 }
7195 /* ARCH name not found in list. */
7198 }
7200 /* Parse the CPU string. */
7202 static void
7204 {
7216 else
7220 {
7223 }
7225 /* Loop through the list of supported CPUs to find a match. */
7227 {
7229 {
7234 {
7235 /* CPU string contains at least one extension. */
7237 }
7240 }
7241 }
7243 /* CPU name not found in list. */
7246 }
7248 /* Parse the TUNE string. */
7250 static void
7252 {
7257 /* Loop through the list of supported CPUs to find a match. */
7259 {
7261 {
7264 }
7265 }
7267 /* CPU name not found in list. */
7270 }
7272 /* Parse TOKEN, which has length LENGTH to see if it is an option
7273 described in FLAG. If it is, return the index bit for that fusion type.
7274 If not, error (printing OPTION_NAME) and return zero. */
7276 static unsigned int
7281 {
7283 {
7287 }
7291 }
7293 /* Parse OPTION which is a comma-separated list of flags to enable.
7294 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7295 default state we inherit from the CPU tuning structures. OPTION_NAME
7296 gives the top-level option we are parsing in the -moverride string,
7297 for use in error messages. */
7299 static unsigned int
7304 {
7311 {
7314 token_length,
7315 flags,
7316 option_name);
7317 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7318 in the token stream, reset the supported operations. So:
7320 adrp+add.cmp+branch.none.adrp+add
7322 would have the result of turning on only adrp+add fusion. */
7328 }
7330 /* We ended with a comma, print something. */
7332 {
7335 }
7337 /* We still have one more token to parse. */
7340 token_length,
7341 flags,
7342 option_name);
7348 }
7350 /* Support for overriding instruction fusion. */
7352 static void
7355 {
7357 aarch64_fusible_pairs,
7360 }
7362 /* Support for overriding other tuning flags. */
7364 static void
7367 {
7368 tune->extra_tuning_flags
7370 aarch64_tuning_flags,
7373 }
7375 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
7376 we understand. If it is, extract the option string and handoff to
7377 the appropriate function. */
7379 void
7383 {
7389 {
7392 }
7394 /* Get the length of the option name. */
7396 /* Skip the '=' to get to the option string. */
7397 option_part++;
7400 {
7402 {
7405 }
7406 }
7410 }
7412 /* Parse STRING looking for options in the format:
7413 string :: option:string
7414 option :: name=substring
7415 name :: {a-z}
7416 substring :: defined by option. */
7418 static void
7421 {
7432 {
7434 /* Make this substring look like a string. */
7438 }
7440 /* One last option to parse. */
7443 }
7445 /* Implement TARGET_OPTION_OVERRIDE. */
7447 static void
7449 {
7450 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
7451 If either of -march or -mtune is given, they override their
7452 respective component of -mcpu.
7454 So, first parse AARCH64_CPU_STRING, then the others, be careful
7455 with -march as, if -mcpu is not present on the command line, march
7456 must set a sensible default CPU. */
7458 {
7460 }
7463 {
7465 }
7468 {
7470 }
7472 #ifndef HAVE_AS_MABI_OPTION
7473 /* The compiler may have been configured with 2.23.* binutils, which does
7474 not have support for ILP32. */
7477 #endif
7483 /* This target defaults to strict volatile bitfields. */
7487 /* If the user did not specify a processor, choose the default
7488 one for them. This will be the CPU set during configuration using
7489 --with-cpu, otherwise it is "generic". */
7491 {
7494 }
7503 /* Make a copy of the tuning parameters attached to the core, which
7504 we may later overwrite. */
7513 {
7514 #ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
7516 #else
7518 #endif
7519 }
7524 }
7526 /* Implement targetm.override_options_after_change. */
7528 static void
7530 {
7536 /* If not optimizing for size, set the default
7537 alignment to what the target wants */
7539 {
7546 }
7547 }
7551 {
7555 }
7557 void
7559 {
7561 }
7563 /* A checking mechanism for the implementation of the various code models. */
7564 static void
7566 {
7568 {
7570 {
7575 #ifdef HAVE_AS_SMALL_PIC_RELOCS
7577 ? AARCH64_CMODEL_SMALL_PIC
7579 #else
7581 #endif
7588 }
7589 }
7590 else
7592 }
7594 /* Return true if SYMBOL_REF X binds locally. */
7596 static bool
7598 {
7602 }
7604 /* Return true if SYMBOL_REF X is thread local */
7605 static bool
7607 {
7615 }
7617 /* Classify a TLS symbol into one of the TLS kinds. */
7618 enum aarch64_symbol_type
7620 {
7624 {
7641 }
7642 }
7644 /* Return the method that should be used to access SYMBOL_REF or
7645 LABEL_REF X in context CONTEXT. */
7647 enum aarch64_symbol_type
7650 {
7652 {
7654 {
7669 }
7670 }
7673 {
7681 {
7683 /* When we retreive symbol + offset address, we have to make sure
7684 the offset does not cause overflow of the final address. But
7685 we have no way of knowing the address of symbol at compile time
7686 so we can't accurately say if the distance between the PC and
7687 symbol + offset is outside the addressible range of +/-1M in the
7688 TINY code model. So we rely on images not being greater than
7689 1M and cap the offset at 1M and anything beyond 1M will have to
7690 be loaded using an alternative mechanism. */
7697 /* Same reasoning as the tiny code model, but the offset cap here is
7698 4G. */
7719 }
7720 }
7722 /* By default push everything into the constant pool. */
7724 }
7726 bool
7728 {
7730 }
7732 bool
7734 {
7742 }
7744 /* Return true if X holds either a quarter-precision or
7745 floating-point +0.0 constant. */
7746 static bool
7748 {
7755 /* We only handle moving 0.0 to a TFmode register. */
7760 }
7762 static bool
7764 {
7765 /* Do not allow vector struct mode constants. We could support
7766 0 and -1 easily, but they need support in aarch64-simd.md. */
7770 /* This could probably go away because
7771 we now decompose CONST_INTs according to expand_mov_immediate. */
7782 }
7784 rtx
7786 {
7792 /* Can return in any reg. */
7795 }
7797 /* On AAPCS systems, this is the "struct __va_list". */
7800 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
7801 Return the type to use as __builtin_va_list.
7803 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
7805 struct __va_list
7806 {
7807 void *__stack;
7808 void *__gr_top;
7809 void *__vr_top;
7810 int __gr_offs;
7811 int __vr_offs;
7812 }; */
7814 static tree
7816 {
7817 tree va_list_name;
7820 /* Create the type. */
7822 /* Give it the required name. */
7824 TYPE_DECL,
7826 va_list_type);
7831 /* Create the fields. */
7834 ptr_type_node);
7837 ptr_type_node);
7840 ptr_type_node);
7843 integer_type_node);
7846 integer_type_node);
7866 /* Compute its layout. */
7870 }
7872 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
7873 static void
7875 {
7879 tree t;
7885 gr_save_area_size
7887 vr_save_area_size
7891 {
7894 }
7903 NULL_TREE);
7905 NULL_TREE);
7907 NULL_TREE);
7909 NULL_TREE);
7911 NULL_TREE);
7913 /* Emit code to initialize STACK, which points to the next varargs stack
7914 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
7915 by named arguments. STACK is 8-byte aligned. */
7922 /* Emit code to initialize GRTOP, the top of the GR save area.
7923 virtual_incoming_args_rtx should have been 16 byte aligned. */
7928 /* Emit code to initialize VRTOP, the top of the VR save area.
7929 This address is gr_save_area_bytes below GRTOP, rounded
7930 down to the next 16-byte boundary. */
7940 /* Emit code to initialize GROFF, the offset from GRTOP of the
7941 next GPR argument. */
7946 /* Likewise emit code to initialize VROFF, the offset from FTOP
7947 of the next VR argument. */
7951 }
7953 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
7955 static tree
7958 {
7959 tree addr;
7965 machine_mode mode;
7992 type,
7996 {
7997 /* TYPE passed in fp/simd registers. */
8009 {
8012 }
8015 {
8017 }
8018 }
8019 else
8020 {
8021 /* TYPE passed in general registers. */
8034 {
8036 }
8037 }
8039 /* Get a local temporary for the field value. */
8042 /* Emit code to branch if off >= 0. */
8048 {
8049 /* Emit: offs = (offs + 15) & -16. */
8055 }
8056 else
8059 /* Update ap.__[g|v]r_offs */
8064 /* String up. */
8068 /* [cond2] if (ap.__[g|v]r_offs > 0) */
8073 /* String up: make sure the assignment happens before the use. */
8077 /* Prepare the trees handling the argument that is passed on the stack;
8078 the top level node will store in ON_STACK. */
8081 {
8082 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
8090 }
8091 else
8093 /* Advance ap.__stack */
8101 /* String up roundup and advance. */
8104 /* String up with arg */
8106 /* Big-endianness related address adjustment. */
8109 {
8113 }
8118 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
8128 {
8129 /* type ha; // treat as "struct {ftype field[n];}"
8130 ... [computing offs]
8131 for (i = 0; i <nregs; ++i, offs += 16)
8132 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
8133 return ha; */
8137 /* Declare a local variable. */
8141 /* Establish the base type. */
8143 {
8156 /* The half precision and quad precision are not fully supported yet. Enable
8157 the following code after the support is complete. Need to find the correct
8158 type node for __fp16 *. */
8159 #if 0
8164 #endif
8167 {
8171 }
8175 }
8177 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
8185 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
8187 {
8197 }
8201 }
8211 }
8213 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
8215 static void
8219 {
8221 CUMULATIVE_ARGS local_cum;
8224 /* The caller has advanced CUM up to, but not beyond, the last named
8225 argument. Advance a local copy of CUM past the last "real" named
8226 argument, to find out how many registers are left over. */
8230 /* Found out how many registers we need to save. */
8235 {
8238 }
8241 {
8243 {
8246 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
8254 }
8256 {
8257 /* We can't use move_block_from_reg, because it will use
8258 the wrong mode, storing D regs only. */
8262 /* Set OFF to the offset from virtual_incoming_args_rtx of
8263 the first vector register. The VR save area lies below
8264 the GR one, and is aligned to 16 bytes. */
8270 {
8278 }
8279 }
8280 }
8282 /* We don't save the size into *PRETEND_SIZE because we want to avoid
8283 any complication of having crtl->args.pretend_args_size changed. */
8288 }
8290 static void
8292 {
8295 {
8297 {
8300 }
8301 }
8302 }
8304 /* Walk down the type tree of TYPE counting consecutive base elements.
8305 If *MODEP is VOIDmode, then set it to the first valid floating point
8306 type. If a non-floating point type is found, or if a floating point
8307 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
8308 otherwise return the count in the sub-tree. */
8309 static int
8311 {
8312 machine_mode mode;
8313 HOST_WIDE_INT size;
8316 {
8344 /* Use V2SImode and V4SImode as representatives of all 64-bit
8345 and 128-bit vector types. */
8348 {
8357 }
8362 /* Vector modes are considered to be opaque: two vectors are
8363 equivalent for the purposes of being homogeneous aggregates
8364 if they are the same size. */
8371 {
8375 /* Can't handle incomplete types nor sizes that are not
8376 fixed. */
8383 || !index
8394 /* There must be no padding. */
8399 }
8402 {
8405 tree field;
8407 /* Can't handle incomplete types nor sizes that are not
8408 fixed. */
8414 {
8422 }
8424 /* There must be no padding. */
8429 }
8433 {
8434 /* These aren't very interesting except in a degenerate case. */
8437 tree field;
8439 /* Can't handle incomplete types nor sizes that are not
8440 fixed. */
8446 {
8454 }
8456 /* There must be no padding. */
8461 }
8465 }
8468 }
8470 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
8471 type as described in AAPCS64 \S 4.1.2.
8473 See the comment above aarch64_composite_type_p for the notes on MODE. */
8475 static bool
8477 machine_mode mode)
8478 {
8488 }
8490 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
8491 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
8492 array types. The C99 floating-point complex types are also considered
8493 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
8494 types, which are GCC extensions and out of the scope of AAPCS64, are
8495 treated as composite types here as well.
8497 Note that MODE itself is not sufficient in determining whether a type
8498 is such a composite type or not. This is because
8499 stor-layout.c:compute_record_mode may have already changed the MODE
8500 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
8501 structure with only one field may have its MODE set to the mode of the
8502 field. Also an integer mode whose size matches the size of the
8503 RECORD_TYPE type may be used to substitute the original mode
8504 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
8505 solely relied on. */
8507 static bool
8509 machine_mode mode)
8510 {
8523 }
8525 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
8526 shall be passed or returned in simd/fp register(s) (providing these
8527 parameter passing registers are available).
8529 Upon successful return, *COUNT returns the number of needed registers,
8530 *BASE_MODE returns the mode of the individual register and when IS_HAF
8531 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
8532 floating-point aggregate or a homogeneous short-vector aggregate. */
8534 static bool
8536 const_tree type,
8540 {
8548 {
8551 }
8553 {
8557 }
8559 {
8563 {
8566 }
8567 else
8569 }
8570 else
8575 }
8577 /* Implement TARGET_STRUCT_VALUE_RTX. */
8579 static rtx
8582 {
8584 }
8586 /* Implements target hook vector_mode_supported_p. */
8587 static bool
8589 {
8600 }
8602 /* Return appropriate SIMD container
8603 for MODE within a vector of WIDTH bits. */
8604 static machine_mode
8606 {
8609 {
8612 {
8627 }
8628 else
8630 {
8641 }
8642 }
8644 }
8646 /* Return 128-bit container as the preferred SIMD mode for MODE. */
8647 static machine_mode
8649 {
8651 }
8653 /* Return the bitmask of possible vector sizes for the vectorizer
8654 to iterate over. */
8655 static unsigned int
8657 {
8659 }
8661 /* Implement TARGET_MANGLE_TYPE. */
8665 {
8666 /* The AArch64 ABI documents say that "__va_list" has to be
8667 managled as if it is in the "std" namespace. */
8671 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
8672 builtin types. */
8676 /* Use the default mangling. */
8678 }
8681 /* Return true if the rtx_insn contains a MEM RTX somewhere
8682 in it. */
8684 static bool
8686 {
8693 }
8695 /* Find the first rtx_insn before insn that will generate an assembly
8696 instruction. */
8700 {
8704 do
8705 {
8707 }
8711 }
8713 static bool
8715 {
8717 /* A number of these may be AArch32 only. */
8722 };
8725 {
8728 }
8731 }
8733 /* Check if there is a register dependency between a load and the insn
8734 for which we hold recog_data. */
8736 static bool
8738 {
8739 rtx load_reg;
8749 {
8755 }
8757 }
8760 /* When working around the Cortex-A53 erratum 835769,
8761 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
8762 instruction and has a preceding memory instruction such that a NOP
8763 should be inserted between them. */
8765 bool
8767 {
8770 rtx body;
8783 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
8784 Restore recog state to INSN to avoid state corruption. */
8792 /* If the previous insn is a memory op and there is no dependency between
8793 it and the DImode madd, emit a NOP between them. If body is NULL then we
8794 have a complex memory operation, probably a load/store pair.
8795 Be conservative for now and emit a NOP. */
8802 }
8805 /* Implement FINAL_PRESCAN_INSN. */
8807 void
8809 {
8812 }
8815 /* Return the equivalent letter for size. */
8816 static char
8818 {
8820 {
8826 }
8827 }
8829 /* Return true iff x is a uniform vector of floating-point
8830 constants, and the constant can be represented in
8831 quarter-precision form. Note, as aarch64_float_const_representable
8832 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
8833 static bool
8835 {
8850 {
8858 }
8861 }
8863 /* Return true for valid and false for invalid. */
8864 bool
8867 {
8868 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
8869 matches = 1; \
8870 for (i = 0; i < idx; i += (STRIDE)) \
8871 if (!(TEST)) \
8872 matches = 0; \
8873 if (matches) \
8874 { \
8875 immtype = (CLASS); \
8876 elsize = (ELSIZE); \
8877 eshift = (SHIFT); \
8878 emvn = (NEG); \
8879 break; \
8880 }
8890 {
8896 {
8901 }
8904 }
8906 /* Splat vector constant out into a byte vector. */
8908 {
8909 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
8910 it must be laid out in the vector register in reverse order. */
8916 {
8919 }
8921 {
8924 }
8925 else
8929 {
8932 {
8935 }
8938 }
8939 }
8941 /* Sanity check. */
8944 do
8945 {
8994 }
9001 {
9011 /* Un-invert bytes of recognized vector, if necessary. */
9017 {
9018 /* FIXME: Broken on 32-bit H_W_I hosts. */
9027 }
9028 else
9029 {
9033 /* Construct 'abcdefgh' because the assembler cannot handle
9034 generic constants. */
9039 }
9040 }
9043 #undef CHECK
9044 }
9046 /* Check of immediate shift constants are within range. */
9047 bool
9049 {
9053 else
9055 }
9057 /* Return true if X is a uniform vector where all elements
9058 are either the floating-point constant 0.0 or the
9059 integer constant 0. */
9060 bool
9062 {
9064 }
9066 bool
9068 {
9073 {
9078 }
9081 }
9083 bool
9086 machine_mode mode)
9087 {
9100 }
9102 /* Return a const_int vector of VAL. */
9103 rtx
9105 {
9114 }
9116 /* Check OP is a legal scalar immediate for the MOVI instruction. */
9118 bool
9120 {
9121 machine_mode vmode;
9127 }
9129 /* Construct and return a PARALLEL RTX vector with elements numbering the
9130 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
9131 the vector - from the perspective of the architecture. This does not
9132 line up with GCC's perspective on lane numbers, so we end up with
9133 different masks depending on our target endian-ness. The diagram
9134 below may help. We must draw the distinction when building masks
9135 which select one half of the vector. An instruction selecting
9136 architectural low-lanes for a big-endian target, must be described using
9137 a mask selecting GCC high-lanes.
9139 Big-Endian Little-Endian
9141 GCC 0 1 2 3 3 2 1 0
9142 | x | x | x | x | | x | x | x | x |
9143 Architecture 3 2 1 0 3 2 1 0
9145 Low Mask: { 2, 3 } { 0, 1 }
9146 High Mask: { 0, 1 } { 2, 3 }
9147 */
9149 rtx
9151 {
9157 rtx t1;
9162 else
9170 }
9172 /* Check OP for validity as a PARALLEL RTX vector with elements
9173 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
9174 from the perspective of the architecture. See the diagram above
9175 aarch64_simd_vect_par_cnst_half for more details. */
9177 bool
9180 {
9193 {
9200 }
9202 }
9204 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
9205 HIGH (exclusive). */
9206 void
9208 const_tree exp)
9209 {
9210 HOST_WIDE_INT lane;
9215 {
9218 else
9220 }
9221 }
9223 /* Return TRUE if OP is a valid vector addressing mode. */
9224 bool
9226 {
9229 }
9231 /* Emit a register copy from operand to operand, taking care not to
9232 early-clobber source registers in the process.
9234 COUNT is the number of components into which the copy needs to be
9235 decomposed. */
9236 void
9239 {
9249 else
9253 }
9255 /* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
9256 one of VSTRUCT modes: OI, CI or XI. */
9257 int
9259 {
9260 machine_mode mode;
9265 {
9268 {
9277 }
9278 }
9280 }
9282 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
9283 one of VSTRUCT modes: OI, CI, EI, or XI. */
9284 int
9286 {
9288 }
9290 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
9291 alignment of a vector to 128 bits. */
9292 static HOST_WIDE_INT
9294 {
9297 }
9299 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
9300 static bool
9302 {
9306 /* We guarantee alignment for vectors up to 128-bits. */
9311 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
9313 }
9315 /* If VALS is a vector constant that can be loaded into a register
9316 using DUP, generate instructions to do so and return an RTX to
9317 assign to the register. Otherwise return NULL_RTX. */
9318 static rtx
9320 {
9325 rtx x;
9332 {
9336 }
9341 /* We can load this constant by using DUP and a constant in a
9342 single ARM register. This will be cheaper than a vector
9343 load. */
9346 }
9349 /* Generate code to load VALS, which is a PARALLEL containing only
9350 constants (for vec_init) or CONST_VECTOR, efficiently into a
9351 register. Returns an RTX to copy into the register, or NULL_RTX
9352 for a PARALLEL that can not be converted into a CONST_VECTOR. */
9353 static rtx
9355 {
9357 rtx const_dup;
9366 {
9367 /* A CONST_VECTOR must contain only CONST_INTs and
9368 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
9369 Only store valid constants in a CONST_VECTOR. */
9371 {
9374 n_const++;
9375 }
9378 }
9379 else
9384 /* Load using MOVI/MVNI. */
9387 /* Loaded using DUP. */
9390 /* Load from constant pool. We can not take advantage of single-cycle
9391 LD1 because we need a PC-relative addressing mode. */
9393 else
9394 /* A PARALLEL containing something not valid inside CONST_VECTOR.
9395 We can not construct an initializer. */
9397 }
9399 void
9401 {
9410 {
9414 else
9419 }
9422 {
9425 {
9428 }
9429 }
9431 /* Splat a single non-constant element if we can. */
9433 {
9437 }
9439 /* Half the fields (or less) are non-constant. Load constant then overwrite
9440 varying fields. Hope that this is more efficient than using the stack. */
9442 {
9445 /* Load constant part of vector. We really don't care what goes into the
9446 parts we will overwrite, but we're more likely to be able to load the
9447 constant efficiently if it has fewer, larger, repeating parts
9448 (see aarch64_simd_valid_immediate). */
9450 {
9456 {
9457 /* Look in the copied vector, as more elements are const. */
9460 {
9463 }
9464 }
9466 }
9469 /* Insert variables. */
9474 {
9480 }
9482 }
9484 /* Construct the vector in memory one field at a time
9485 and load the whole vector. */
9493 }
9495 static unsigned HOST_WIDE_INT
9497 {
9498 return
9501 }
9503 #ifndef TLS_SECTION_ASM_FLAG
9505 #endif
9507 void
9509 tree decl ATTRIBUTE_UNUSED)
9510 {
9513 /* If we have already declared this section, we can use an
9514 abbreviated form to switch back to it -- unless this section is
9515 part of a COMDAT groups, in which case GAS requires the full
9516 declaration every time. */
9519 {
9522 }
9545 {
9551 else
9554 #ifdef TYPE_OPERAND_FMT
9556 #else
9558 #endif
9565 {
9568 else
9571 }
9572 }
9575 }
9577 /* Select a format to encode pointers in exception handling data. */
9578 int
9580 {
9583 {
9589 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
9590 for everything. */
9594 /* No assumptions here. 8-byte relocs required. */
9597 }
9599 }
9601 /* Emit load exclusive. */
9603 static void
9606 {
9610 {
9617 }
9620 }
9622 /* Emit store exclusive. */
9624 static void
9627 {
9631 {
9638 }
9641 }
9643 /* Mark the previous jump instruction as unlikely. */
9645 static void
9647 {
9652 }
9654 /* Expand a compare and swap pattern. */
9656 void
9658 {
9674 /* Normally the succ memory model must be stronger than fail, but in the
9675 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
9676 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
9683 {
9686 /* For short modes, we're going to perform the comparison in SImode,
9687 so do the zero-extension now. */
9691 /* Fall through. */
9695 /* Force the value into a register if needed. */
9702 }
9705 {
9712 }
9722 }
9724 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
9725 sequence implementing an atomic operation. */
9727 static void
9729 {
9736 {
9738 }
9739 }
9741 /* Split a compare and swap pattern. */
9743 void
9745 {
9747 machine_mode mode;
9752 rtx model_rtx;
9766 {
9769 }
9772 /* The initial load can be relaxed for a __sync operation since a final
9773 barrier will be emitted to stop code hoisting. */
9777 else
9789 {
9794 }
9795 else
9796 {
9800 }
9804 /* Emit any final barrier needed for a __sync operation. */
9807 }
9809 /* Split an atomic operation. */
9811 void
9814 {
9820 rtx x;
9829 else
9833 /* The initial load can be relaxed for a __sync operation since a final
9834 barrier will be emitted to stop code hoisting. */
9838 else
9842 {
9856 {
9859 }
9860 /* Fall through. */
9866 }
9876 /* Emit any final barrier needed for a __sync operation. */
9879 }
9881 static void
9883 {
9891 }
9893 static void
9895 {
9897 {
9900 }
9902 {
9907 }
9909 }
9911 /* Target hook for c_mode_for_suffix. */
9912 static machine_mode
9914 {
9919 }
9921 /* We can only represent floating point constants which will fit in
9922 "quarter-precision" values. These values are characterised by
9923 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
9924 by:
9926 (-1)^s * (n/16) * 2^r
9928 Where:
9929 's' is the sign bit.
9930 'n' is an integer in the range 16 <= n <= 31.
9931 'r' is an integer in the range -3 <= r <= 4. */
9933 /* Return true iff X can be represented by a quarter-precision
9934 floating point immediate operand X. Note, we cannot represent 0.0. */
9935 bool
9937 {
9938 /* This represents our current view of how many bits
9939 make up the mantissa. */
9954 /* We cannot represent infinities, NaNs or +/-zero. We won't
9955 know if we have +zero until we analyse the mantissa, but we
9956 can reject the other invalid values. */
9961 /* Extract exponent. */
9965 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
9966 highest (sign) bit, with a fixed binary point at bit point_pos.
9967 m1 holds the low part of the mantissa, m2 the high part.
9968 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
9969 bits for the mantissa, this can fail (low bits will be lost). */
9973 /* If the low part of the mantissa has bits set we cannot represent
9974 the value. */
9977 /* We have rejected the lower HOST_WIDE_INT, so update our
9978 understanding of how many bits lie in the mantissa and
9979 look only at the high HOST_WIDE_INT. */
9983 /* We can only represent values with a mantissa of the form 1.xxxx. */
9988 /* Having filtered unrepresentable values, we may now remove all
9989 but the highest 5 bits. */
9992 /* We cannot represent the value 0.0, so reject it. This is handled
9993 elsewhere. */
9997 /* Then, as bit 4 is always set, we can mask it off, leaving
9998 the mantissa in the range [0, 15]. */
10002 /* GCC internally does not use IEEE754-like encoding (where normalized
10003 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
10004 Our mantissa values are shifted 4 places to the left relative to
10005 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
10006 by 5 places to correct for GCC's representation. */
10010 }
10014 machine_mode mode,
10016 {
10026 /* This will return true to show const_vector is legal for use as either
10027 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
10028 also update INFO to show how the immediate should be generated. */
10037 {
10041 else
10042 {
10043 #define buf_size 20
10044 REAL_VALUE_TYPE r;
10048 #undef buf_size
10052 else
10056 }
10057 }
10069 else
10073 }
10077 machine_mode mode)
10078 {
10079 machine_mode vmode;
10085 }
10087 /* Split operands into moves from op[1] + op[2] into op[0]. */
10089 void
10091 {
10102 {
10103 /* No-op move. Can't split to nothing; emit something. */
10106 }
10108 /* Preserve register attributes for variable tracking. */
10113 /* Special case of reversed high/low parts. */
10116 {
10120 }
10122 {
10123 /* Try to avoid unnecessary moves if part of the result
10124 is in the right place already. */
10129 }
10130 else
10131 {
10136 }
10137 }
10139 /* vec_perm support. */
10141 #define MAX_VECT_LEN 16
10143 struct expand_vec_perm_d
10144 {
10147 machine_mode vmode;
10151 };
10153 /* Generate a variable permutation. */
10155 static void
10157 {
10168 {
10170 {
10171 /* Expand the argument to a V16QI mode by duplicating it. */
10175 }
10176 else
10177 {
10179 }
10180 }
10181 else
10182 {
10183 rtx pair;
10186 {
10190 }
10191 else
10192 {
10196 }
10197 }
10198 }
10200 void
10202 {
10206 rtx mask;
10208 /* The TBL instruction does not use a modulo index, so we must take care
10209 of that ourselves. */
10214 /* For big-endian, we also need to reverse the index within the vector
10215 (but not which vector). */
10217 {
10218 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
10223 }
10225 }
10227 /* Recognize patterns suitable for the TRN instructions. */
10228 static bool
10230 {
10239 /* Note that these are little-endian tests.
10240 We correct for big-endian later. */
10245 else
10250 {
10255 }
10257 /* Success! */
10264 {
10267 }
10271 {
10273 {
10286 }
10287 }
10288 else
10289 {
10291 {
10304 }
10305 }
10309 }
10311 /* Recognize patterns suitable for the UZP instructions. */
10312 static bool
10314 {
10323 /* Note that these are little-endian tests.
10324 We correct for big-endian later. */
10329 else
10334 {
10338 }
10340 /* Success! */
10347 {
10350 }
10354 {
10356 {
10369 }
10370 }
10371 else
10372 {
10374 {
10387 }
10388 }
10392 }
10394 /* Recognize patterns suitable for the ZIP instructions. */
10395 static bool
10397 {
10406 /* Note that these are little-endian tests.
10407 We correct for big-endian later. */
10410 /* Do Nothing. */
10411 ;
10414 else
10419 {
10426 }
10428 /* Success! */
10435 {
10438 }
10442 {
10444 {
10457 }
10458 }
10459 else
10460 {
10462 {
10475 }
10476 }
10480 }
10482 /* Recognize patterns for the EXT insn. */
10484 static bool
10486 {
10489 rtx offset;
10493 /* Check if the extracted indices are increasing by one. */
10495 {
10498 {
10499 /* We'll pass the same vector in twice, so allow indices to wrap. */
10501 }
10504 }
10507 {
10520 }
10522 /* Success! */
10526 /* The case where (location == 0) is a no-op for both big- and little-endian,
10527 and is removed by the mid-end at optimization levels -O1 and higher. */
10530 {
10531 /* After setup, we want the high elements of the first vector (stored
10532 at the LSB end of the register), and the low elements of the second
10533 vector (stored at the MSB end of the register). So swap. */
10535 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
10537 }
10542 }
10544 /* Recognize patterns for the REV insns. */
10546 static bool
10548 {
10557 {
10560 {
10565 }
10569 {
10576 }
10580 {
10591 }
10595 }
10599 {
10600 /* This is guaranteed to be true as the value of diff
10601 is 7, 3, 1 and we should have enough elements in the
10602 queue to generate this. Getting a vector mask with a
10603 value of diff other than these values implies that
10604 something is wrong by the time we get here. */
10608 }
10610 /* Success! */
10616 }
10618 static bool
10620 {
10623 rtx in0;
10626 rtx lane;
10630 {
10633 }
10635 /* The generic preparation in aarch64_expand_vec_perm_const_1
10636 swaps the operand order and the permute indices if it finds
10637 d->perm[0] to be in the second operand. Thus, we can always
10638 use d->op0 and need not do any extra arithmetic to get the
10639 correct lane number. */
10644 {
10657 }
10661 }
10663 static bool
10665 {
10673 /* Generic code will try constant permutation twice. Once with the
10674 original mode and again with the elements lowered to QImode.
10675 So wait and don't do the selector expansion ourselves. */
10680 {
10683 /* If big-endian and two vectors we end up with a weird mixed-endian
10684 mode on NEON. Reverse the index within each word but not the word
10685 itself. */
10688 }
10694 }
10696 static bool
10698 {
10699 /* The pattern matching functions above are written to look for a small
10700 number to begin the sequence (0, 1, N/2). If we begin with an index
10701 from the second operand, we can swap the operands. */
10703 {
10711 }
10714 {
10728 }
10730 }
10732 /* Expand a vec_perm_const pattern. */
10734 bool
10736 {
10750 {
10755 }
10758 {
10767 /* The elements of PERM do not suggest that only the first operand
10768 is used, but both operands are identical. Allow easier matching
10769 of the permutation by folding the permutation into the single
10770 input vector. */
10771 /* Fall Through. */
10783 }
10786 }
10788 static bool
10791 {
10801 /* Calculate whether all elements are in one vector. */
10803 {
10807 }
10809 /* If all elements are from the second vector, reindex as if from the
10810 first vector. */
10815 /* Check whether the mask can be applied to a single vector. */
10828 }
10830 rtx
10832 {
10833 /* We have to reverse each vector because we dont have
10834 a permuted load that can reverse-load according to ABI rules. */
10835 rtx mask;
10849 }
10851 /* Implement MODES_TIEABLE_P. */
10853 bool
10855 {
10859 /* We specifically want to allow elements of "structure" modes to
10860 be tieable to the structure. This more general condition allows
10861 other rarer situations too. */
10868 }
10870 /* Return a new RTX holding the result of moving POINTER forward by
10871 AMOUNT bytes. */
10873 static rtx
10875 {
10880 }
10882 /* Return a new RTX holding the result of moving POINTER forward by the
10883 size of the mode it points to. */
10885 static rtx
10887 {
10891 }
10893 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
10894 MODE bytes. */
10896 static void
10898 machine_mode mode)
10899 {
10902 /* "Cast" the pointers to the correct mode. */
10905 /* Emit the memcpy. */
10908 /* Move the pointers forward. */
10911 }
10913 /* Expand movmem, as if from a __builtin_memcpy. Return true if
10914 we succeed, otherwise return false. */
10916 bool
10918 {
10922 rtx base;
10925 /* When optimizing for size, give a better estimate of the length of a
10926 memcpy call, but use the default otherwise. */
10929 /* We can't do anything smart if the amount to copy is not constant. */
10935 /* Try to keep the number of instructions low. For cases below 16 bytes we
10936 need to make at most two moves. For cases above 16 bytes it will be one
10937 move for each 16 byte chunk, then at most two additional moves. */
10947 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
10948 1-byte chunk. */
10950 {
10952 {
10955 }
10961 }
10963 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
10964 4-byte chunk, partially overlapping with the previously copied chunk. */
10966 {
10970 {
10976 }
10978 }
10980 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
10981 them, then (if applicable) an 8-byte chunk. */
10983 {
10985 {
10988 }
10989 else
10990 {
10993 }
10994 }
10996 /* Finish the final bytes of the copy. We can always do this in one
10997 instruction. We either copy the exact amount we need, or partially
10998 overlap with the previous chunk we copied and copy 8-bytes. */
11007 else
11008 {
11010 {
11014 }
11015 else
11016 {
11022 }
11023 }
11026 }
11028 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
11030 static unsigned HOST_WIDE_INT
11032 {
11034 }
11036 static bool
11041 {
11042 /* STORE_BY_PIECES can be used when copying a constant string, but
11043 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
11044 For now we always fail this and let the move_by_pieces code copy
11045 the string from read-only memory. */
11050 }
11052 static enum machine_mode
11054 {
11056 {
11089 }
11090 }
11092 static rtx
11095 {
11114 {
11130 }
11135 {
11138 }
11152 {
11155 }
11160 }
11162 static rtx
11165 {
11184 {
11202 }
11207 {
11210 }
11227 {
11230 }
11236 }
11238 #undef TARGET_GEN_CCMP_FIRST
11239 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
11241 #undef TARGET_GEN_CCMP_NEXT
11242 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
11244 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
11245 instruction fusion of some sort. */
11247 static bool
11249 {
11251 }
11254 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
11255 should be kept together during scheduling. */
11257 static bool
11259 {
11260 rtx set_dest;
11263 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
11271 {
11272 /* We are trying to match:
11273 prev (mov) == (set (reg r0) (const_int imm16))
11274 curr (movk) == (set (zero_extract (reg r0)
11275 (const_int 16)
11276 (const_int 16))
11277 (const_int imm16_1)) */
11289 {
11291 }
11292 }
11296 {
11298 /* We're trying to match:
11299 prev (adrp) == (set (reg r1)
11300 (high (symbol_ref ("SYM"))))
11301 curr (add) == (set (reg r0)
11302 (lo_sum (reg r1)
11303 (symbol_ref ("SYM"))))
11304 Note that r0 need not necessarily be the same as r1, especially
11305 during pre-regalloc scheduling. */
11309 {
11317 }
11318 }
11322 {
11324 /* We're trying to match:
11325 prev (movk) == (set (zero_extract (reg r0)
11326 (const_int 16)
11327 (const_int 32))
11328 (const_int imm16_1))
11329 curr (movk) == (set (zero_extract (reg r0)
11330 (const_int 16)
11331 (const_int 48))
11332 (const_int imm16_2)) */
11348 }
11351 {
11352 /* We're trying to match:
11353 prev (adrp) == (set (reg r0)
11354 (high (symbol_ref ("SYM"))))
11355 curr (ldr) == (set (reg r1)
11356 (mem (lo_sum (reg r0)
11357 (symbol_ref ("SYM")))))
11358 or
11359 curr (ldr) == (set (reg r1)
11360 (zero_extend (mem
11361 (lo_sum (reg r0)
11362 (symbol_ref ("SYM")))))) */
11365 {
11378 }
11379 }
11383 {
11386 /* FIXME: this misses some which is considered simple arthematic
11387 instructions for ThunderX. Simple shifts are missed here. */
11393 }
11396 }
11398 /* If MEM is in the form of [base+offset], extract the two parts
11399 of address and set to BASE and OFFSET, otherwise return false
11400 after clearing BASE and OFFSET. */
11402 bool
11404 {
11405 rtx addr;
11412 {
11416 }
11420 {
11424 }
11430 }
11432 /* Types for scheduling fusion. */
11433 enum sched_fusion_type
11434 {
11436 SCHED_FUSION_LD_SIGN_EXTEND,
11437 SCHED_FUSION_LD_ZERO_EXTEND,
11438 SCHED_FUSION_LD,
11439 SCHED_FUSION_ST,
11440 SCHED_FUSION_NUM
11441 };
11443 /* If INSN is a load or store of address in the form of [base+offset],
11444 extract the two parts and set to BASE and OFFSET. Return scheduling
11445 fusion type this INSN is. */
11447 static enum sched_fusion_type
11449 {
11466 {
11471 }
11473 {
11478 }
11483 {
11486 }
11487 else
11494 }
11496 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
11498 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
11499 and PRI are only calculated for these instructions. For other instruction,
11500 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
11501 type instruction fusion can be added by returning different priorities.
11503 It's important that irrelevant instructions get the largest FUSION_PRI. */
11505 static void
11508 {
11518 {
11522 }
11524 /* Set FUSION_PRI according to fusion type and base register. */
11527 /* Calculate PRI. */
11530 /* INSN with smaller offset goes first. */
11534 else
11539 }
11541 /* Given OPERANDS of consecutive load/store, check if we can merge
11542 them into ldp/stp. LOAD is true if they are load instructions.
11543 MODE is the mode of memory operands. */
11545 bool
11548 {
11554 {
11562 }
11563 else
11564 {
11569 }
11571 /* The mems cannot be volatile. */
11575 /* Check if the addresses are in the form of [base+offset]. */
11583 /* Check if the bases are same. */
11590 /* Check if the offsets are consecutive. */
11594 /* Check if the addresses are clobbered by load. */
11596 {
11600 /* In increasing order, the last load can clobber the address. */
11603 }
11607 else
11612 else
11615 /* Check if the registers are of same class. */
11620 }
11622 /* Given OPERANDS of consecutive load/store, check if we can merge
11623 them into ldp/stp by adjusting the offset. LOAD is true if they
11624 are load instructions. MODE is the mode of memory operands.
11626 Given below consecutive stores:
11628 str w1, [xb, 0x100]
11629 str w1, [xb, 0x104]
11630 str w1, [xb, 0x108]
11631 str w1, [xb, 0x10c]
11633 Though the offsets are out of the range supported by stp, we can
11634 still pair them after adjusting the offset, like:
11636 add scratch, xb, 0x100
11637 stp w1, w1, [scratch]
11638 stp w1, w1, [scratch, 0x8]
11640 The peephole patterns detecting this opportunity should guarantee
11641 the scratch register is avaliable. */
11643 bool
11646 {
11653 {
11666 }
11667 else
11668 {
11677 }
11678 /* Skip if memory operand is by itslef valid for ldp/stp. */
11682 /* The mems cannot be volatile. */
11687 /* Check if the addresses are in the form of [base+offset]. */
11701 /* Check if the bases are same. */
11712 /* Check if the offsets are consecutive. */
11721 /* Check if the addresses are clobbered by load. */
11723 {
11729 /* In increasing order, the last load can clobber the address. */
11732 }
11736 else
11741 else
11746 else
11751 else
11754 /* Check if the registers are of same class. */
11759 }
11761 /* Given OPERANDS of consecutive load/store, this function pairs them
11762 into ldp/stp after adjusting the offset. It depends on the fact
11763 that addresses of load/store instructions are in increasing order.
11764 MODE is the mode of memory operands. CODE is the rtl operator
11765 which should be applied to all memory operands, it's SIGN_EXTEND,
11766 ZERO_EXTEND or UNKNOWN. */
11768 bool
11771 {
11777 {
11782 }
11783 else
11784 {
11790 }
11795 /* Adjust offset thus it can fit in ldp/stp instruction. */
11803 /* Further adjust to make sure all offsets are OK. */
11805 {
11808 }
11810 /* Make sure the adjustment can be done with ADD/SUB instructions. */
11815 {
11818 }
11820 /* Create new memory references. */
11824 /* Check if the adjusted address is OK for ldp/stp. */
11843 {
11848 }
11850 {
11855 }
11858 {
11863 }
11864 else
11865 {
11870 }
11872 /* Emit adjusting instruction. */
11874 /* Emit ldp/stp instructions. */
11882 }
11884 /* Return 1 if pseudo register should be created and used to hold
11885 GOT address for PIC code. */
11887 bool
11889 {
11891 }
11893 #undef TARGET_ADDRESS_COST
11894 #define TARGET_ADDRESS_COST aarch64_address_cost
11896 /* This hook will determines whether unnamed bitfields affect the alignment
11897 of the containing structure. The hook returns true if the structure
11898 should inherit the alignment requirements of an unnamed bitfield's
11899 type. */
11900 #undef TARGET_ALIGN_ANON_BITFIELD
11901 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
11903 #undef TARGET_ASM_ALIGNED_DI_OP
11906 #undef TARGET_ASM_ALIGNED_HI_OP
11909 #undef TARGET_ASM_ALIGNED_SI_OP
11912 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11913 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
11914 hook_bool_const_tree_hwi_hwi_const_tree_true
11916 #undef TARGET_ASM_FILE_START
11917 #define TARGET_ASM_FILE_START aarch64_start_file
11919 #undef TARGET_ASM_OUTPUT_MI_THUNK
11920 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
11922 #undef TARGET_ASM_SELECT_RTX_SECTION
11923 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
11925 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11926 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
11928 #undef TARGET_BUILD_BUILTIN_VA_LIST
11929 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
11931 #undef TARGET_CALLEE_COPIES
11932 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
11934 #undef TARGET_CAN_ELIMINATE
11935 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
11937 #undef TARGET_CANNOT_FORCE_CONST_MEM
11938 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
11940 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11941 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
11943 /* Only the least significant bit is used for initialization guard
11944 variables. */
11945 #undef TARGET_CXX_GUARD_MASK_BIT
11946 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
11948 #undef TARGET_C_MODE_FOR_SUFFIX
11949 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
11951 #ifdef TARGET_BIG_ENDIAN_DEFAULT
11952 #undef TARGET_DEFAULT_TARGET_FLAGS
11953 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
11954 #endif
11956 #undef TARGET_CLASS_MAX_NREGS
11957 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
11959 #undef TARGET_BUILTIN_DECL
11960 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
11962 #undef TARGET_EXPAND_BUILTIN
11963 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
11965 #undef TARGET_EXPAND_BUILTIN_VA_START
11966 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
11968 #undef TARGET_FOLD_BUILTIN
11969 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
11971 #undef TARGET_FUNCTION_ARG
11972 #define TARGET_FUNCTION_ARG aarch64_function_arg
11974 #undef TARGET_FUNCTION_ARG_ADVANCE
11975 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
11977 #undef TARGET_FUNCTION_ARG_BOUNDARY
11978 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
11980 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11981 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
11983 #undef TARGET_FUNCTION_VALUE
11984 #define TARGET_FUNCTION_VALUE aarch64_function_value
11986 #undef TARGET_FUNCTION_VALUE_REGNO_P
11987 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
11989 #undef TARGET_FRAME_POINTER_REQUIRED
11990 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
11992 #undef TARGET_GIMPLE_FOLD_BUILTIN
11993 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
11995 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11996 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
11998 #undef TARGET_INIT_BUILTINS
11999 #define TARGET_INIT_BUILTINS aarch64_init_builtins
12001 #undef TARGET_LEGITIMATE_ADDRESS_P
12002 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
12004 #undef TARGET_LEGITIMATE_CONSTANT_P
12005 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
12007 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12008 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
12010 #undef TARGET_LRA_P
12011 #define TARGET_LRA_P hook_bool_void_true
12013 #undef TARGET_MANGLE_TYPE
12014 #define TARGET_MANGLE_TYPE aarch64_mangle_type
12016 #undef TARGET_MEMORY_MOVE_COST
12017 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
12019 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
12020 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
12022 #undef TARGET_MUST_PASS_IN_STACK
12023 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12025 /* This target hook should return true if accesses to volatile bitfields
12026 should use the narrowest mode possible. It should return false if these
12027 accesses should use the bitfield container type. */
12028 #undef TARGET_NARROW_VOLATILE_BITFIELD
12029 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
12031 #undef TARGET_OPTION_OVERRIDE
12032 #define TARGET_OPTION_OVERRIDE aarch64_override_options
12034 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
12035 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
12036 aarch64_override_options_after_change
12038 #undef TARGET_PASS_BY_REFERENCE
12039 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
12041 #undef TARGET_PREFERRED_RELOAD_CLASS
12042 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
12044 #undef TARGET_SCHED_REASSOCIATION_WIDTH
12045 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
12047 #undef TARGET_SECONDARY_RELOAD
12048 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
12050 #undef TARGET_SHIFT_TRUNCATION_MASK
12051 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
12053 #undef TARGET_SETUP_INCOMING_VARARGS
12054 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
12056 #undef TARGET_STRUCT_VALUE_RTX
12057 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
12059 #undef TARGET_REGISTER_MOVE_COST
12060 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
12062 #undef TARGET_RETURN_IN_MEMORY
12063 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
12065 #undef TARGET_RETURN_IN_MSB
12066 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
12068 #undef TARGET_RTX_COSTS
12069 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
12071 #undef TARGET_SCHED_ISSUE_RATE
12072 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
12074 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12075 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12076 aarch64_sched_first_cycle_multipass_dfa_lookahead
12078 #undef TARGET_TRAMPOLINE_INIT
12079 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
12081 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12082 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
12084 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12085 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
12087 #undef TARGET_ARRAY_MODE_SUPPORTED_P
12088 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
12090 #undef TARGET_VECTORIZE_ADD_STMT_COST
12091 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
12093 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
12094 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
12095 aarch64_builtin_vectorization_cost
12097 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
12098 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
12100 #undef TARGET_VECTORIZE_BUILTINS
12101 #define TARGET_VECTORIZE_BUILTINS
12103 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
12104 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
12105 aarch64_builtin_vectorized_function
12107 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
12108 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
12109 aarch64_autovectorize_vector_sizes
12111 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
12112 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
12113 aarch64_atomic_assign_expand_fenv
12115 /* Section anchor support. */
12117 #undef TARGET_MIN_ANCHOR_OFFSET
12118 #define TARGET_MIN_ANCHOR_OFFSET -256
12120 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
12121 byte offset; we can do much more for larger data types, but have no way
12122 to determine the size of the access. We assume accesses are aligned. */
12123 #undef TARGET_MAX_ANCHOR_OFFSET
12124 #define TARGET_MAX_ANCHOR_OFFSET 4095
12126 #undef TARGET_VECTOR_ALIGNMENT
12127 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
12129 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
12130 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
12131 aarch64_simd_vector_alignment_reachable
12133 /* vec_perm support. */
12135 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
12136 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
12137 aarch64_vectorize_vec_perm_const_ok
12140 #undef TARGET_FIXED_CONDITION_CODE_REGS
12141 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
12143 #undef TARGET_FLAGS_REGNUM
12144 #define TARGET_FLAGS_REGNUM CC_REGNUM
12146 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
12147 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
12149 #undef TARGET_ASAN_SHADOW_OFFSET
12150 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
12152 #undef TARGET_LEGITIMIZE_ADDRESS
12153 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
12155 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12156 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12157 aarch64_use_by_pieces_infrastructure_p
12159 #undef TARGET_CAN_USE_DOLOOP_P
12160 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
12162 #undef TARGET_SCHED_MACRO_FUSION_P
12163 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
12165 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
12166 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
12168 #undef TARGET_SCHED_FUSION_PRIORITY
12169 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
12171 #undef TARGET_USE_PSEUDO_PIC_REG
12172 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg