1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
34 #include "addresses.h"
40 #include "basic-block.h"
44 #include "tree-pass.h"
46 #ifndef STACK_PUSH_CODE
47 #ifdef STACK_GROWS_DOWNWARD
48 #define STACK_PUSH_CODE PRE_DEC
50 #define STACK_PUSH_CODE PRE_INC
54 #ifndef STACK_POP_CODE
55 #ifdef STACK_GROWS_DOWNWARD
56 #define STACK_POP_CODE POST_INC
58 #define STACK_POP_CODE POST_DEC
62 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
);
63 static rtx
*find_single_use_1 (rtx
, rtx
*);
64 static void validate_replace_src_1 (rtx
*, void *);
65 static rtx
split_insn (rtx
);
67 /* Nonzero means allow operands to be volatile.
68 This should be 0 if you are generating rtl, such as if you are calling
69 the functions in optabs.c and expmed.c (most of the time).
70 This should be 1 if all valid insns need to be recognized,
71 such as in regclass.c and final.c and reload.c.
73 init_recog and init_recog_no_volatile are responsible for setting this. */
77 struct recog_data recog_data
;
79 /* Contains a vector of operand_alternative structures for every operand.
80 Set up by preprocess_constraints. */
81 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
83 /* On return from `constrain_operands', indicate which alternative
86 int which_alternative
;
88 /* Nonzero after end of reload pass.
89 Set to 1 or 0 by toplev.c.
90 Controls the significance of (SUBREG (MEM)). */
94 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
95 int epilogue_completed
;
97 /* Initialize data used by the function `recog'.
98 This must be called once in the compilation of a function
99 before any insn recognition may be done in the function. */
102 init_recog_no_volatile (void)
114 /* Check that X is an insn-body for an `asm' with operands
115 and that the operands mentioned in it are legitimate. */
118 check_asm_operands (rtx x
)
122 const char **constraints
;
125 /* Post-reload, be more strict with things. */
126 if (reload_completed
)
128 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
129 extract_insn (make_insn_raw (x
));
130 constrain_operands (1);
131 return which_alternative
>= 0;
134 noperands
= asm_noperands (x
);
140 operands
= alloca (noperands
* sizeof (rtx
));
141 constraints
= alloca (noperands
* sizeof (char *));
143 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
);
145 for (i
= 0; i
< noperands
; i
++)
147 const char *c
= constraints
[i
];
150 if (ISDIGIT ((unsigned char) c
[0]) && c
[1] == '\0')
151 c
= constraints
[c
[0] - '0'];
153 if (! asm_operand_ok (operands
[i
], c
))
160 /* Static data for the next two routines. */
162 typedef struct change_t
170 static change_t
*changes
;
171 static int changes_allocated
;
173 static int num_changes
= 0;
175 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
176 at which NEW will be placed. If OBJECT is zero, no validation is done,
177 the change is simply made.
179 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
180 will be called with the address and mode as parameters. If OBJECT is
181 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
184 IN_GROUP is nonzero if this is part of a group of changes that must be
185 performed as a group. In that case, the changes will be stored. The
186 function `apply_change_group' will validate and apply the changes.
188 If IN_GROUP is zero, this is a single change. Try to recognize the insn
189 or validate the memory reference with the change applied. If the result
190 is not valid for the machine, suppress the change and return zero.
191 Otherwise, perform the change and return 1. */
194 validate_change (rtx object
, rtx
*loc
, rtx
new, int in_group
)
198 if (old
== new || rtx_equal_p (old
, new))
201 gcc_assert (in_group
!= 0 || num_changes
== 0);
205 /* Save the information describing this change. */
206 if (num_changes
>= changes_allocated
)
208 if (changes_allocated
== 0)
209 /* This value allows for repeated substitutions inside complex
210 indexed addresses, or changes in up to 5 insns. */
211 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
213 changes_allocated
*= 2;
215 changes
= xrealloc (changes
, sizeof (change_t
) * changes_allocated
);
218 changes
[num_changes
].object
= object
;
219 changes
[num_changes
].loc
= loc
;
220 changes
[num_changes
].old
= old
;
222 if (object
&& !MEM_P (object
))
224 /* Set INSN_CODE to force rerecognition of insn. Save old code in
226 changes
[num_changes
].old_code
= INSN_CODE (object
);
227 INSN_CODE (object
) = -1;
232 /* If we are making a group of changes, return 1. Otherwise, validate the
233 change group we made. */
238 return apply_change_group ();
242 /* This subroutine of apply_change_group verifies whether the changes to INSN
243 were valid; i.e. whether INSN can still be recognized. */
246 insn_invalid_p (rtx insn
)
248 rtx pat
= PATTERN (insn
);
249 int num_clobbers
= 0;
250 /* If we are before reload and the pattern is a SET, see if we can add
252 int icode
= recog (pat
, insn
,
253 (GET_CODE (pat
) == SET
254 && ! reload_completed
&& ! reload_in_progress
)
255 ? &num_clobbers
: 0);
256 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
259 /* If this is an asm and the operand aren't legal, then fail. Likewise if
260 this is not an asm and the insn wasn't recognized. */
261 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
262 || (!is_asm
&& icode
< 0))
265 /* If we have to add CLOBBERs, fail if we have to add ones that reference
266 hard registers since our callers can't know if they are live or not.
267 Otherwise, add them. */
268 if (num_clobbers
> 0)
272 if (added_clobbers_hard_reg_p (icode
))
275 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
276 XVECEXP (newpat
, 0, 0) = pat
;
277 add_clobbers (newpat
, icode
);
278 PATTERN (insn
) = pat
= newpat
;
281 /* After reload, verify that all constraints are satisfied. */
282 if (reload_completed
)
286 if (! constrain_operands (1))
290 INSN_CODE (insn
) = icode
;
294 /* Return number of changes made and not validated yet. */
296 num_changes_pending (void)
301 /* Tentatively apply the changes numbered NUM and up.
302 Return 1 if all changes are valid, zero otherwise. */
305 verify_changes (int num
)
308 rtx last_validated
= NULL_RTX
;
310 /* The changes have been applied and all INSN_CODEs have been reset to force
313 The changes are valid if we aren't given an object, or if we are
314 given a MEM and it still is a valid address, or if this is in insn
315 and it is recognized. In the latter case, if reload has completed,
316 we also require that the operands meet the constraints for
319 for (i
= num
; i
< num_changes
; i
++)
321 rtx object
= changes
[i
].object
;
323 /* If there is no object to test or if it is the same as the one we
324 already tested, ignore it. */
325 if (object
== 0 || object
== last_validated
)
330 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
333 else if (insn_invalid_p (object
))
335 rtx pat
= PATTERN (object
);
337 /* Perhaps we couldn't recognize the insn because there were
338 extra CLOBBERs at the end. If so, try to re-recognize
339 without the last CLOBBER (later iterations will cause each of
340 them to be eliminated, in turn). But don't do this if we
341 have an ASM_OPERAND. */
342 if (GET_CODE (pat
) == PARALLEL
343 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
344 && asm_noperands (PATTERN (object
)) < 0)
348 if (XVECLEN (pat
, 0) == 2)
349 newpat
= XVECEXP (pat
, 0, 0);
355 = gen_rtx_PARALLEL (VOIDmode
,
356 rtvec_alloc (XVECLEN (pat
, 0) - 1));
357 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
358 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
361 /* Add a new change to this group to replace the pattern
362 with this new pattern. Then consider this change
363 as having succeeded. The change we added will
364 cause the entire call to fail if things remain invalid.
366 Note that this can lose if a later change than the one
367 we are processing specified &XVECEXP (PATTERN (object), 0, X)
368 but this shouldn't occur. */
370 validate_change (object
, &PATTERN (object
), newpat
, 1);
373 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
374 /* If this insn is a CLOBBER or USE, it is always valid, but is
380 last_validated
= object
;
383 return (i
== num_changes
);
386 /* A group of changes has previously been issued with validate_change and
387 verified with verify_changes. Update the BB_DIRTY flags of the affected
388 blocks, and clear num_changes. */
391 confirm_change_group (void)
396 for (i
= 0; i
< num_changes
; i
++)
397 if (changes
[i
].object
398 && INSN_P (changes
[i
].object
)
399 && (bb
= BLOCK_FOR_INSN (changes
[i
].object
)))
400 bb
->flags
|= BB_DIRTY
;
405 /* Apply a group of changes previously issued with `validate_change'.
406 If all changes are valid, call confirm_change_group and return 1,
407 otherwise, call cancel_changes and return 0. */
410 apply_change_group (void)
412 if (verify_changes (0))
414 confirm_change_group ();
425 /* Return the number of changes so far in the current group. */
428 num_validated_changes (void)
433 /* Retract the changes numbered NUM and up. */
436 cancel_changes (int num
)
440 /* Back out all the changes. Do this in the opposite order in which
442 for (i
= num_changes
- 1; i
>= num
; i
--)
444 *changes
[i
].loc
= changes
[i
].old
;
445 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
446 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
451 /* Replace every occurrence of FROM in X with TO. Mark each change with
452 validate_change passing OBJECT. */
455 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
)
461 enum machine_mode op0_mode
= VOIDmode
;
462 int prev_changes
= num_changes
;
469 fmt
= GET_RTX_FORMAT (code
);
471 op0_mode
= GET_MODE (XEXP (x
, 0));
473 /* X matches FROM if it is the same rtx or they are both referring to the
474 same register in the same mode. Avoid calling rtx_equal_p unless the
475 operands look similar. */
478 || (REG_P (x
) && REG_P (from
)
479 && GET_MODE (x
) == GET_MODE (from
)
480 && REGNO (x
) == REGNO (from
))
481 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
482 && rtx_equal_p (x
, from
)))
484 validate_change (object
, loc
, to
, 1);
488 /* Call ourself recursively to perform the replacements.
489 We must not replace inside already replaced expression, otherwise we
490 get infinite recursion for replacements like (reg X)->(subreg (reg X))
491 done by regmove, so we must special case shared ASM_OPERANDS. */
493 if (GET_CODE (x
) == PARALLEL
)
495 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
497 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
498 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
500 /* Verify that operands are really shared. */
501 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
502 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
504 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
508 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
);
512 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
515 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
516 else if (fmt
[i
] == 'E')
517 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
518 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
521 /* If we didn't substitute, there is nothing more to do. */
522 if (num_changes
== prev_changes
)
525 /* Allow substituted expression to have different mode. This is used by
526 regmove to change mode of pseudo register. */
527 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
528 op0_mode
= GET_MODE (XEXP (x
, 0));
530 /* Do changes needed to keep rtx consistent. Don't do any other
531 simplifications, as it is not our job. */
533 if (SWAPPABLE_OPERANDS_P (x
)
534 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
536 validate_change (object
, loc
,
537 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
538 : swap_condition (code
),
539 GET_MODE (x
), XEXP (x
, 1),
548 /* If we have a PLUS whose second operand is now a CONST_INT, use
549 simplify_gen_binary to try to simplify it.
550 ??? We may want later to remove this, once simplification is
551 separated from this function. */
552 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
553 validate_change (object
, loc
,
555 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
558 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
559 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
560 validate_change (object
, loc
,
562 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
563 simplify_gen_unary (NEG
,
564 GET_MODE (x
), XEXP (x
, 1),
569 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
571 new = simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
573 /* If any of the above failed, substitute in something that
574 we know won't be recognized. */
576 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
577 validate_change (object
, loc
, new, 1);
581 /* All subregs possible to simplify should be simplified. */
582 new = simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
585 /* Subregs of VOIDmode operands are incorrect. */
586 if (!new && GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
587 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
589 validate_change (object
, loc
, new, 1);
593 /* If we are replacing a register with memory, try to change the memory
594 to be the mode required for memory in extract operations (this isn't
595 likely to be an insertion operation; if it was, nothing bad will
596 happen, we might just fail in some cases). */
598 if (MEM_P (XEXP (x
, 0))
599 && GET_CODE (XEXP (x
, 1)) == CONST_INT
600 && GET_CODE (XEXP (x
, 2)) == CONST_INT
601 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
602 && !MEM_VOLATILE_P (XEXP (x
, 0)))
604 enum machine_mode wanted_mode
= VOIDmode
;
605 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
606 int pos
= INTVAL (XEXP (x
, 2));
608 if (GET_CODE (x
) == ZERO_EXTRACT
)
610 enum machine_mode new_mode
611 = mode_for_extraction (EP_extzv
, 1);
612 if (new_mode
!= MAX_MACHINE_MODE
)
613 wanted_mode
= new_mode
;
615 else if (GET_CODE (x
) == SIGN_EXTRACT
)
617 enum machine_mode new_mode
618 = mode_for_extraction (EP_extv
, 1);
619 if (new_mode
!= MAX_MACHINE_MODE
)
620 wanted_mode
= new_mode
;
623 /* If we have a narrower mode, we can do something. */
624 if (wanted_mode
!= VOIDmode
625 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
627 int offset
= pos
/ BITS_PER_UNIT
;
630 /* If the bytes and bits are counted differently, we
631 must adjust the offset. */
632 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
634 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
637 pos
%= GET_MODE_BITSIZE (wanted_mode
);
639 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
641 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
642 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
653 /* Try replacing every occurrence of FROM in INSN with TO. After all
654 changes have been made, validate by seeing if INSN is still valid. */
657 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
659 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
660 return apply_change_group ();
663 /* Try replacing every occurrence of FROM in INSN with TO. */
666 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
668 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
671 /* Function called by note_uses to replace used subexpressions. */
672 struct validate_replace_src_data
674 rtx from
; /* Old RTX */
675 rtx to
; /* New RTX */
676 rtx insn
; /* Insn in which substitution is occurring. */
680 validate_replace_src_1 (rtx
*x
, void *data
)
682 struct validate_replace_src_data
*d
683 = (struct validate_replace_src_data
*) data
;
685 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
);
688 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
692 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
694 struct validate_replace_src_data d
;
699 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
703 /* Return 1 if the insn using CC0 set by INSN does not contain
704 any ordered tests applied to the condition codes.
705 EQ and NE tests do not count. */
708 next_insn_tests_no_inequality (rtx insn
)
710 rtx next
= next_cc0_user (insn
);
712 /* If there is no next insn, we have to take the conservative choice. */
716 return (INSN_P (next
)
717 && ! inequality_comparisons_p (PATTERN (next
)));
721 /* This is used by find_single_use to locate an rtx that contains exactly one
722 use of DEST, which is typically either a REG or CC0. It returns a
723 pointer to the innermost rtx expression containing DEST. Appearances of
724 DEST that are being used to totally replace it are not counted. */
727 find_single_use_1 (rtx dest
, rtx
*loc
)
730 enum rtx_code code
= GET_CODE (x
);
748 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
749 of a REG that occupies all of the REG, the insn uses DEST if
750 it is mentioned in the destination or the source. Otherwise, we
751 need just check the source. */
752 if (GET_CODE (SET_DEST (x
)) != CC0
753 && GET_CODE (SET_DEST (x
)) != PC
754 && !REG_P (SET_DEST (x
))
755 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
756 && REG_P (SUBREG_REG (SET_DEST (x
)))
757 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
758 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
759 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
760 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
763 return find_single_use_1 (dest
, &SET_SRC (x
));
767 return find_single_use_1 (dest
, &XEXP (x
, 0));
773 /* If it wasn't one of the common cases above, check each expression and
774 vector of this code. Look for a unique usage of DEST. */
776 fmt
= GET_RTX_FORMAT (code
);
777 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
781 if (dest
== XEXP (x
, i
)
782 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
783 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
786 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
789 result
= this_result
;
790 else if (this_result
)
791 /* Duplicate usage. */
794 else if (fmt
[i
] == 'E')
798 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
800 if (XVECEXP (x
, i
, j
) == dest
802 && REG_P (XVECEXP (x
, i
, j
))
803 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
806 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
809 result
= this_result
;
810 else if (this_result
)
819 /* See if DEST, produced in INSN, is used only a single time in the
820 sequel. If so, return a pointer to the innermost rtx expression in which
823 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
825 This routine will return usually zero either before flow is called (because
826 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
827 note can't be trusted).
829 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
830 care about REG_DEAD notes or LOG_LINKS.
832 Otherwise, we find the single use by finding an insn that has a
833 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
834 only referenced once in that insn, we know that it must be the first
835 and last insn referencing DEST. */
838 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
847 next
= NEXT_INSN (insn
);
849 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
852 result
= find_single_use_1 (dest
, &PATTERN (next
));
859 if (reload_completed
|| reload_in_progress
|| !REG_P (dest
))
862 for (next
= next_nonnote_insn (insn
);
863 next
!= 0 && !LABEL_P (next
);
864 next
= next_nonnote_insn (next
))
865 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
867 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
868 if (XEXP (link
, 0) == insn
)
873 result
= find_single_use_1 (dest
, &PATTERN (next
));
883 /* Return 1 if OP is a valid general operand for machine mode MODE.
884 This is either a register reference, a memory reference,
885 or a constant. In the case of a memory reference, the address
886 is checked for general validity for the target machine.
888 Register and memory references must have mode MODE in order to be valid,
889 but some constants have no machine mode and are valid for any mode.
891 If MODE is VOIDmode, OP is checked for validity for whatever mode
894 The main use of this function is as a predicate in match_operand
895 expressions in the machine description.
897 For an explanation of this function's behavior for registers of
898 class NO_REGS, see the comment for `register_operand'. */
901 general_operand (rtx op
, enum machine_mode mode
)
903 enum rtx_code code
= GET_CODE (op
);
905 if (mode
== VOIDmode
)
906 mode
= GET_MODE (op
);
908 /* Don't accept CONST_INT or anything similar
909 if the caller wants something floating. */
910 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
911 && GET_MODE_CLASS (mode
) != MODE_INT
912 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
915 if (GET_CODE (op
) == CONST_INT
917 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
921 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
923 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
924 && LEGITIMATE_CONSTANT_P (op
));
926 /* Except for certain constants with VOIDmode, already checked for,
927 OP's mode must match MODE if MODE specifies a mode. */
929 if (GET_MODE (op
) != mode
)
934 rtx sub
= SUBREG_REG (op
);
936 #ifdef INSN_SCHEDULING
937 /* On machines that have insn scheduling, we want all memory
938 reference to be explicit, so outlaw paradoxical SUBREGs.
939 However, we must allow them after reload so that they can
940 get cleaned up by cleanup_subreg_operands. */
941 if (!reload_completed
&& MEM_P (sub
)
942 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
945 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
946 may result in incorrect reference. We should simplify all valid
947 subregs of MEM anyway. But allow this after reload because we
948 might be called from cleanup_subreg_operands.
950 ??? This is a kludge. */
951 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
955 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
956 create such rtl, and we must reject it. */
957 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
958 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
962 code
= GET_CODE (op
);
966 /* A register whose class is NO_REGS is not a general operand. */
967 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
968 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
972 rtx y
= XEXP (op
, 0);
974 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
977 /* Use the mem's mode, since it will be reloaded thus. */
978 if (memory_address_p (GET_MODE (op
), y
))
985 /* Return 1 if OP is a valid memory address for a memory reference
988 The main use of this function is as a predicate in match_operand
989 expressions in the machine description. */
992 address_operand (rtx op
, enum machine_mode mode
)
994 return memory_address_p (mode
, op
);
997 /* Return 1 if OP is a register reference of mode MODE.
998 If MODE is VOIDmode, accept a register in any mode.
1000 The main use of this function is as a predicate in match_operand
1001 expressions in the machine description.
1003 As a special exception, registers whose class is NO_REGS are
1004 not accepted by `register_operand'. The reason for this change
1005 is to allow the representation of special architecture artifacts
1006 (such as a condition code register) without extending the rtl
1007 definitions. Since registers of class NO_REGS cannot be used
1008 as registers in any case where register classes are examined,
1009 it is most consistent to keep this function from accepting them. */
1012 register_operand (rtx op
, enum machine_mode mode
)
1014 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1017 if (GET_CODE (op
) == SUBREG
)
1019 rtx sub
= SUBREG_REG (op
);
1021 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1022 because it is guaranteed to be reloaded into one.
1023 Just make sure the MEM is valid in itself.
1024 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1025 but currently it does result from (SUBREG (REG)...) where the
1026 reg went on the stack.) */
1027 if (! reload_completed
&& MEM_P (sub
))
1028 return general_operand (op
, mode
);
1030 #ifdef CANNOT_CHANGE_MODE_CLASS
1032 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1033 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1034 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1035 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
)
1039 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1040 create such rtl, and we must reject it. */
1041 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1042 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1048 /* We don't consider registers whose class is NO_REGS
1049 to be a register operand. */
1051 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1052 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1055 /* Return 1 for a register in Pmode; ignore the tested mode. */
1058 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1060 return register_operand (op
, Pmode
);
1063 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1064 or a hard register. */
1067 scratch_operand (rtx op
, enum machine_mode mode
)
1069 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1072 return (GET_CODE (op
) == SCRATCH
1074 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1077 /* Return 1 if OP is a valid immediate operand for mode MODE.
1079 The main use of this function is as a predicate in match_operand
1080 expressions in the machine description. */
1083 immediate_operand (rtx op
, enum machine_mode mode
)
1085 /* Don't accept CONST_INT or anything similar
1086 if the caller wants something floating. */
1087 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1088 && GET_MODE_CLASS (mode
) != MODE_INT
1089 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1092 if (GET_CODE (op
) == CONST_INT
1094 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1097 return (CONSTANT_P (op
)
1098 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1099 || GET_MODE (op
) == VOIDmode
)
1100 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1101 && LEGITIMATE_CONSTANT_P (op
));
1104 /* Returns 1 if OP is an operand that is a CONST_INT. */
1107 const_int_operand (rtx op
, enum machine_mode mode
)
1109 if (GET_CODE (op
) != CONST_INT
)
1112 if (mode
!= VOIDmode
1113 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1119 /* Returns 1 if OP is an operand that is a constant integer or constant
1120 floating-point number. */
1123 const_double_operand (rtx op
, enum machine_mode mode
)
1125 /* Don't accept CONST_INT or anything similar
1126 if the caller wants something floating. */
1127 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1128 && GET_MODE_CLASS (mode
) != MODE_INT
1129 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1132 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
1133 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1134 || GET_MODE (op
) == VOIDmode
));
1137 /* Return 1 if OP is a general operand that is not an immediate operand. */
1140 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1142 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1145 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1148 nonmemory_operand (rtx op
, enum machine_mode mode
)
1150 if (CONSTANT_P (op
))
1152 /* Don't accept CONST_INT or anything similar
1153 if the caller wants something floating. */
1154 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1155 && GET_MODE_CLASS (mode
) != MODE_INT
1156 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1159 if (GET_CODE (op
) == CONST_INT
1161 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1164 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1165 || mode
== VOIDmode
)
1166 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1167 && LEGITIMATE_CONSTANT_P (op
));
1170 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1173 if (GET_CODE (op
) == SUBREG
)
1175 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1176 because it is guaranteed to be reloaded into one.
1177 Just make sure the MEM is valid in itself.
1178 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1179 but currently it does result from (SUBREG (REG)...) where the
1180 reg went on the stack.) */
1181 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1182 return general_operand (op
, mode
);
1183 op
= SUBREG_REG (op
);
1186 /* We don't consider registers whose class is NO_REGS
1187 to be a register operand. */
1189 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1190 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1193 /* Return 1 if OP is a valid operand that stands for pushing a
1194 value of mode MODE onto the stack.
1196 The main use of this function is as a predicate in match_operand
1197 expressions in the machine description. */
1200 push_operand (rtx op
, enum machine_mode mode
)
1202 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1204 #ifdef PUSH_ROUNDING
1205 rounded_size
= PUSH_ROUNDING (rounded_size
);
1211 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1216 if (rounded_size
== GET_MODE_SIZE (mode
))
1218 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1223 if (GET_CODE (op
) != PRE_MODIFY
1224 || GET_CODE (XEXP (op
, 1)) != PLUS
1225 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1226 || GET_CODE (XEXP (XEXP (op
, 1), 1)) != CONST_INT
1227 #ifdef STACK_GROWS_DOWNWARD
1228 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1230 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1236 return XEXP (op
, 0) == stack_pointer_rtx
;
1239 /* Return 1 if OP is a valid operand that stands for popping a
1240 value of mode MODE off the stack.
1242 The main use of this function is as a predicate in match_operand
1243 expressions in the machine description. */
1246 pop_operand (rtx op
, enum machine_mode mode
)
1251 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1256 if (GET_CODE (op
) != STACK_POP_CODE
)
1259 return XEXP (op
, 0) == stack_pointer_rtx
;
1262 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1265 memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx addr
)
1267 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1274 /* Return 1 if OP is a valid memory reference with mode MODE,
1275 including a valid address.
1277 The main use of this function is as a predicate in match_operand
1278 expressions in the machine description. */
1281 memory_operand (rtx op
, enum machine_mode mode
)
1285 if (! reload_completed
)
1286 /* Note that no SUBREG is a memory operand before end of reload pass,
1287 because (SUBREG (MEM...)) forces reloading into a register. */
1288 return MEM_P (op
) && general_operand (op
, mode
);
1290 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1294 if (GET_CODE (inner
) == SUBREG
)
1295 inner
= SUBREG_REG (inner
);
1297 return (MEM_P (inner
) && general_operand (op
, mode
));
1300 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1301 that is, a memory reference whose address is a general_operand. */
1304 indirect_operand (rtx op
, enum machine_mode mode
)
1306 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1307 if (! reload_completed
1308 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1310 int offset
= SUBREG_BYTE (op
);
1311 rtx inner
= SUBREG_REG (op
);
1313 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1316 /* The only way that we can have a general_operand as the resulting
1317 address is if OFFSET is zero and the address already is an operand
1318 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1321 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1322 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1323 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1324 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1325 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1329 && memory_operand (op
, mode
)
1330 && general_operand (XEXP (op
, 0), Pmode
));
1333 /* Return 1 if this is a comparison operator. This allows the use of
1334 MATCH_OPERATOR to recognize all the branch insns. */
1337 comparison_operator (rtx op
, enum machine_mode mode
)
1339 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1340 && COMPARISON_P (op
));
1343 /* If BODY is an insn body that uses ASM_OPERANDS,
1344 return the number of operands (both input and output) in the insn.
1345 Otherwise return -1. */
1348 asm_noperands (rtx body
)
1350 switch (GET_CODE (body
))
1353 /* No output operands: return number of input operands. */
1354 return ASM_OPERANDS_INPUT_LENGTH (body
);
1356 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1357 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1358 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1362 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
1363 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1365 /* Multiple output operands, or 1 output plus some clobbers:
1366 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1370 /* Count backwards through CLOBBERs to determine number of SETs. */
1371 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1373 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1375 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1379 /* N_SETS is now number of output operands. */
1382 /* Verify that all the SETs we have
1383 came from a single original asm_operands insn
1384 (so that invalid combinations are blocked). */
1385 for (i
= 0; i
< n_sets
; i
++)
1387 rtx elt
= XVECEXP (body
, 0, i
);
1388 if (GET_CODE (elt
) != SET
)
1390 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1392 /* If these ASM_OPERANDS rtx's came from different original insns
1393 then they aren't allowed together. */
1394 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1395 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1398 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1401 else if (GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1403 /* 0 outputs, but some clobbers:
1404 body is [(asm_operands ...) (clobber (reg ...))...]. */
1407 /* Make sure all the other parallel things really are clobbers. */
1408 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1409 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1412 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1421 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1422 copy its operands (both input and output) into the vector OPERANDS,
1423 the locations of the operands within the insn into the vector OPERAND_LOCS,
1424 and the constraints for the operands into CONSTRAINTS.
1425 Write the modes of the operands into MODES.
1426 Return the assembler-template.
1428 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1429 we don't store that info. */
1432 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1433 const char **constraints
, enum machine_mode
*modes
)
1437 const char *template = 0;
1439 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1441 rtx asmop
= SET_SRC (body
);
1442 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1444 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1446 for (i
= 1; i
< noperands
; i
++)
1449 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1451 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1453 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1455 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1458 /* The output is in the SET.
1459 Its constraint is in the ASM_OPERANDS itself. */
1461 operands
[0] = SET_DEST (body
);
1463 operand_locs
[0] = &SET_DEST (body
);
1465 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1467 modes
[0] = GET_MODE (SET_DEST (body
));
1468 template = ASM_OPERANDS_TEMPLATE (asmop
);
1470 else if (GET_CODE (body
) == ASM_OPERANDS
)
1473 /* No output operands: BODY is (asm_operands ....). */
1475 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1477 /* The input operands are found in the 1st element vector. */
1478 /* Constraints for inputs are in the 2nd element vector. */
1479 for (i
= 0; i
< noperands
; i
++)
1482 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1484 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1486 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1488 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1490 template = ASM_OPERANDS_TEMPLATE (asmop
);
1492 else if (GET_CODE (body
) == PARALLEL
1493 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
1494 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1496 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1497 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1498 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1499 int nout
= 0; /* Does not include CLOBBERs. */
1501 /* At least one output, plus some CLOBBERs. */
1503 /* The outputs are in the SETs.
1504 Their constraints are in the ASM_OPERANDS itself. */
1505 for (i
= 0; i
< nparallel
; i
++)
1507 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1508 break; /* Past last SET */
1511 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1513 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1515 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1517 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1521 for (i
= 0; i
< nin
; i
++)
1524 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1526 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1528 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1530 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1533 template = ASM_OPERANDS_TEMPLATE (asmop
);
1535 else if (GET_CODE (body
) == PARALLEL
1536 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1538 /* No outputs, but some CLOBBERs. */
1540 rtx asmop
= XVECEXP (body
, 0, 0);
1541 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1543 for (i
= 0; i
< nin
; i
++)
1546 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1548 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1550 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1552 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1555 template = ASM_OPERANDS_TEMPLATE (asmop
);
1561 /* Check if an asm_operand matches its constraints.
1562 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1565 asm_operand_ok (rtx op
, const char *constraint
)
1569 /* Use constrain_operands after reload. */
1570 gcc_assert (!reload_completed
);
1574 char c
= *constraint
;
1591 case '0': case '1': case '2': case '3': case '4':
1592 case '5': case '6': case '7': case '8': case '9':
1593 /* For best results, our caller should have given us the
1594 proper matching constraint, but we can't actually fail
1595 the check if they didn't. Indicate that results are
1599 while (ISDIGIT (*constraint
));
1605 if (address_operand (op
, VOIDmode
))
1610 case 'V': /* non-offsettable */
1611 if (memory_operand (op
, VOIDmode
))
1615 case 'o': /* offsettable */
1616 if (offsettable_nonstrict_memref_p (op
))
1621 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1622 excepting those that expand_call created. Further, on some
1623 machines which do not have generalized auto inc/dec, an inc/dec
1624 is not a memory_operand.
1626 Match any memory and hope things are resolved after reload. */
1630 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1631 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1638 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1639 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1645 if (GET_CODE (op
) == CONST_DOUBLE
1646 || (GET_CODE (op
) == CONST_VECTOR
1647 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1652 if (GET_CODE (op
) == CONST_DOUBLE
1653 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1657 if (GET_CODE (op
) == CONST_DOUBLE
1658 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1663 if (GET_CODE (op
) == CONST_INT
1664 || (GET_CODE (op
) == CONST_DOUBLE
1665 && GET_MODE (op
) == VOIDmode
))
1670 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1675 if (GET_CODE (op
) == CONST_INT
1676 || (GET_CODE (op
) == CONST_DOUBLE
1677 && GET_MODE (op
) == VOIDmode
))
1682 if (GET_CODE (op
) == CONST_INT
1683 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1687 if (GET_CODE (op
) == CONST_INT
1688 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1692 if (GET_CODE (op
) == CONST_INT
1693 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1697 if (GET_CODE (op
) == CONST_INT
1698 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1702 if (GET_CODE (op
) == CONST_INT
1703 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1707 if (GET_CODE (op
) == CONST_INT
1708 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1712 if (GET_CODE (op
) == CONST_INT
1713 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1717 if (GET_CODE (op
) == CONST_INT
1718 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1727 if (general_operand (op
, VOIDmode
))
1732 /* For all other letters, we first check for a register class,
1733 otherwise it is an EXTRA_CONSTRAINT. */
1734 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1737 if (GET_MODE (op
) == BLKmode
)
1739 if (register_operand (op
, VOIDmode
))
1742 #ifdef EXTRA_CONSTRAINT_STR
1743 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1745 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
1746 /* Every memory operand can be reloaded to fit. */
1747 && memory_operand (op
, VOIDmode
))
1749 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
)
1750 /* Every address operand can be reloaded to fit. */
1751 && address_operand (op
, VOIDmode
))
1756 len
= CONSTRAINT_LEN (c
, constraint
);
1759 while (--len
&& *constraint
);
1767 /* Given an rtx *P, if it is a sum containing an integer constant term,
1768 return the location (type rtx *) of the pointer to that constant term.
1769 Otherwise, return a null pointer. */
1772 find_constant_term_loc (rtx
*p
)
1775 enum rtx_code code
= GET_CODE (*p
);
1777 /* If *P IS such a constant term, P is its location. */
1779 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1783 /* Otherwise, if not a sum, it has no constant term. */
1785 if (GET_CODE (*p
) != PLUS
)
1788 /* If one of the summands is constant, return its location. */
1790 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1791 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1794 /* Otherwise, check each summand for containing a constant term. */
1796 if (XEXP (*p
, 0) != 0)
1798 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1803 if (XEXP (*p
, 1) != 0)
1805 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1813 /* Return 1 if OP is a memory reference
1814 whose address contains no side effects
1815 and remains valid after the addition
1816 of a positive integer less than the
1817 size of the object being referenced.
1819 We assume that the original address is valid and do not check it.
1821 This uses strict_memory_address_p as a subroutine, so
1822 don't use it before reload. */
1825 offsettable_memref_p (rtx op
)
1827 return ((MEM_P (op
))
1828 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1831 /* Similar, but don't require a strictly valid mem ref:
1832 consider pseudo-regs valid as index or base regs. */
1835 offsettable_nonstrict_memref_p (rtx op
)
1837 return ((MEM_P (op
))
1838 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1841 /* Return 1 if Y is a memory address which contains no side effects
1842 and would remain valid after the addition of a positive integer
1843 less than the size of that mode.
1845 We assume that the original address is valid and do not check it.
1846 We do check that it is valid for narrower modes.
1848 If STRICTP is nonzero, we require a strictly valid address,
1849 for the sake of use in reload.c. */
1852 offsettable_address_p (int strictp
, enum machine_mode mode
, rtx y
)
1854 enum rtx_code ycode
= GET_CODE (y
);
1858 int (*addressp
) (enum machine_mode
, rtx
) =
1859 (strictp
? strict_memory_address_p
: memory_address_p
);
1860 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1862 if (CONSTANT_ADDRESS_P (y
))
1865 /* Adjusting an offsettable address involves changing to a narrower mode.
1866 Make sure that's OK. */
1868 if (mode_dependent_address_p (y
))
1871 /* ??? How much offset does an offsettable BLKmode reference need?
1872 Clearly that depends on the situation in which it's being used.
1873 However, the current situation in which we test 0xffffffff is
1874 less than ideal. Caveat user. */
1876 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1878 /* If the expression contains a constant term,
1879 see if it remains valid when max possible offset is added. */
1881 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1886 *y2
= plus_constant (*y2
, mode_sz
- 1);
1887 /* Use QImode because an odd displacement may be automatically invalid
1888 for any wider mode. But it should be valid for a single byte. */
1889 good
= (*addressp
) (QImode
, y
);
1891 /* In any case, restore old contents of memory. */
1896 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1899 /* The offset added here is chosen as the maximum offset that
1900 any instruction could need to add when operating on something
1901 of the specified mode. We assume that if Y and Y+c are
1902 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1903 go inside a LO_SUM here, so we do so as well. */
1904 if (GET_CODE (y
) == LO_SUM
1906 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
1907 z
= gen_rtx_LO_SUM (GET_MODE (y
), XEXP (y
, 0),
1908 plus_constant (XEXP (y
, 1), mode_sz
- 1));
1910 z
= plus_constant (y
, mode_sz
- 1);
1912 /* Use QImode because an odd displacement may be automatically invalid
1913 for any wider mode. But it should be valid for a single byte. */
1914 return (*addressp
) (QImode
, z
);
1917 /* Return 1 if ADDR is an address-expression whose effect depends
1918 on the mode of the memory reference it is used in.
1920 Autoincrement addressing is a typical example of mode-dependence
1921 because the amount of the increment depends on the mode. */
1924 mode_dependent_address_p (rtx addr ATTRIBUTE_UNUSED
/* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */)
1926 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1928 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1929 win
: ATTRIBUTE_UNUSED_LABEL
1933 /* Like extract_insn, but save insn extracted and don't extract again, when
1934 called again for the same insn expecting that recog_data still contain the
1935 valid information. This is used primary by gen_attr infrastructure that
1936 often does extract insn again and again. */
1938 extract_insn_cached (rtx insn
)
1940 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
1942 extract_insn (insn
);
1943 recog_data
.insn
= insn
;
1946 /* Do cached extract_insn, constrain_operands and complain about failures.
1947 Used by insn_attrtab. */
1949 extract_constrain_insn_cached (rtx insn
)
1951 extract_insn_cached (insn
);
1952 if (which_alternative
== -1
1953 && !constrain_operands (reload_completed
))
1954 fatal_insn_not_found (insn
);
1957 /* Do cached constrain_operands and complain about failures. */
1959 constrain_operands_cached (int strict
)
1961 if (which_alternative
== -1)
1962 return constrain_operands (strict
);
1967 /* Analyze INSN and fill in recog_data. */
1970 extract_insn (rtx insn
)
1975 rtx body
= PATTERN (insn
);
1977 recog_data
.insn
= NULL
;
1978 recog_data
.n_operands
= 0;
1979 recog_data
.n_alternatives
= 0;
1980 recog_data
.n_dups
= 0;
1981 which_alternative
= -1;
1983 switch (GET_CODE (body
))
1993 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1998 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
1999 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2000 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2006 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2009 /* This insn is an `asm' with operands. */
2011 /* expand_asm_operands makes sure there aren't too many operands. */
2012 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2014 /* Now get the operand values and constraints out of the insn. */
2015 decode_asm_operands (body
, recog_data
.operand
,
2016 recog_data
.operand_loc
,
2017 recog_data
.constraints
,
2018 recog_data
.operand_mode
);
2021 const char *p
= recog_data
.constraints
[0];
2022 recog_data
.n_alternatives
= 1;
2024 recog_data
.n_alternatives
+= (*p
++ == ',');
2028 fatal_insn_not_found (insn
);
2032 /* Ordinary insn: recognize it, get the operands via insn_extract
2033 and get the constraints. */
2035 icode
= recog_memoized (insn
);
2037 fatal_insn_not_found (insn
);
2039 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2040 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2041 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2043 insn_extract (insn
);
2045 for (i
= 0; i
< noperands
; i
++)
2047 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2048 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2049 /* VOIDmode match_operands gets mode from their real operand. */
2050 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2051 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2054 for (i
= 0; i
< noperands
; i
++)
2055 recog_data
.operand_type
[i
]
2056 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2057 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2060 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2063 /* After calling extract_insn, you can use this function to extract some
2064 information from the constraint strings into a more usable form.
2065 The collected data is stored in recog_op_alt. */
2067 preprocess_constraints (void)
2071 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2072 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2073 * sizeof (struct operand_alternative
)));
2075 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2078 struct operand_alternative
*op_alt
;
2079 const char *p
= recog_data
.constraints
[i
];
2081 op_alt
= recog_op_alt
[i
];
2083 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2085 op_alt
[j
].cl
= NO_REGS
;
2086 op_alt
[j
].constraint
= p
;
2087 op_alt
[j
].matches
= -1;
2088 op_alt
[j
].matched
= -1;
2090 if (*p
== '\0' || *p
== ',')
2092 op_alt
[j
].anything_ok
= 1;
2102 while (c
!= ',' && c
!= '\0');
2103 if (c
== ',' || c
== '\0')
2111 case '=': case '+': case '*': case '%':
2112 case 'E': case 'F': case 'G': case 'H':
2113 case 's': case 'i': case 'n':
2114 case 'I': case 'J': case 'K': case 'L':
2115 case 'M': case 'N': case 'O': case 'P':
2116 /* These don't say anything we care about. */
2120 op_alt
[j
].reject
+= 6;
2123 op_alt
[j
].reject
+= 600;
2126 op_alt
[j
].earlyclobber
= 1;
2129 case '0': case '1': case '2': case '3': case '4':
2130 case '5': case '6': case '7': case '8': case '9':
2133 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2134 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2140 op_alt
[j
].memory_ok
= 1;
2143 op_alt
[j
].decmem_ok
= 1;
2146 op_alt
[j
].incmem_ok
= 1;
2149 op_alt
[j
].nonoffmem_ok
= 1;
2152 op_alt
[j
].offmem_ok
= 1;
2155 op_alt
[j
].anything_ok
= 1;
2159 op_alt
[j
].is_address
= 1;
2160 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2161 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
2167 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2171 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2173 op_alt
[j
].memory_ok
= 1;
2176 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2178 op_alt
[j
].is_address
= 1;
2180 = (reg_class_subunion
2181 [(int) op_alt
[j
].cl
]
2182 [(int) base_reg_class (VOIDmode
, ADDRESS
,
2188 = (reg_class_subunion
2189 [(int) op_alt
[j
].cl
]
2190 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2193 p
+= CONSTRAINT_LEN (c
, p
);
2199 /* Check the operands of an insn against the insn's operand constraints
2200 and return 1 if they are valid.
2201 The information about the insn's operands, constraints, operand modes
2202 etc. is obtained from the global variables set up by extract_insn.
2204 WHICH_ALTERNATIVE is set to a number which indicates which
2205 alternative of constraints was matched: 0 for the first alternative,
2206 1 for the next, etc.
2208 In addition, when two operands are required to match
2209 and it happens that the output operand is (reg) while the
2210 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2211 make the output operand look like the input.
2212 This is because the output operand is the one the template will print.
2214 This is used in final, just before printing the assembler code and by
2215 the routines that determine an insn's attribute.
2217 If STRICT is a positive nonzero value, it means that we have been
2218 called after reload has been completed. In that case, we must
2219 do all checks strictly. If it is zero, it means that we have been called
2220 before reload has completed. In that case, we first try to see if we can
2221 find an alternative that matches strictly. If not, we try again, this
2222 time assuming that reload will fix up the insn. This provides a "best
2223 guess" for the alternative and is used to compute attributes of insns prior
2224 to reload. A negative value of STRICT is used for this internal call. */
2232 constrain_operands (int strict
)
2234 const char *constraints
[MAX_RECOG_OPERANDS
];
2235 int matching_operands
[MAX_RECOG_OPERANDS
];
2236 int earlyclobber
[MAX_RECOG_OPERANDS
];
2239 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2240 int funny_match_index
;
2242 which_alternative
= 0;
2243 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2246 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2248 constraints
[c
] = recog_data
.constraints
[c
];
2249 matching_operands
[c
] = -1;
2254 int seen_earlyclobber_at
= -1;
2257 funny_match_index
= 0;
2259 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2261 rtx op
= recog_data
.operand
[opno
];
2262 enum machine_mode mode
= GET_MODE (op
);
2263 const char *p
= constraints
[opno
];
2269 earlyclobber
[opno
] = 0;
2271 /* A unary operator may be accepted by the predicate, but it
2272 is irrelevant for matching constraints. */
2276 if (GET_CODE (op
) == SUBREG
)
2278 if (REG_P (SUBREG_REG (op
))
2279 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2280 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2281 GET_MODE (SUBREG_REG (op
)),
2284 op
= SUBREG_REG (op
);
2287 /* An empty constraint or empty alternative
2288 allows anything which matched the pattern. */
2289 if (*p
== 0 || *p
== ',')
2293 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2302 case '?': case '!': case '*': case '%':
2307 /* Ignore rest of this alternative as far as
2308 constraint checking is concerned. */
2311 while (*p
&& *p
!= ',');
2316 earlyclobber
[opno
] = 1;
2317 if (seen_earlyclobber_at
< 0)
2318 seen_earlyclobber_at
= opno
;
2321 case '0': case '1': case '2': case '3': case '4':
2322 case '5': case '6': case '7': case '8': case '9':
2324 /* This operand must be the same as a previous one.
2325 This kind of constraint is used for instructions such
2326 as add when they take only two operands.
2328 Note that the lower-numbered operand is passed first.
2330 If we are not testing strictly, assume that this
2331 constraint will be satisfied. */
2336 match
= strtoul (p
, &end
, 10);
2343 rtx op1
= recog_data
.operand
[match
];
2344 rtx op2
= recog_data
.operand
[opno
];
2346 /* A unary operator may be accepted by the predicate,
2347 but it is irrelevant for matching constraints. */
2349 op1
= XEXP (op1
, 0);
2351 op2
= XEXP (op2
, 0);
2353 val
= operands_match_p (op1
, op2
);
2356 matching_operands
[opno
] = match
;
2357 matching_operands
[match
] = opno
;
2362 /* If output is *x and input is *--x, arrange later
2363 to change the output to *--x as well, since the
2364 output op is the one that will be printed. */
2365 if (val
== 2 && strict
> 0)
2367 funny_match
[funny_match_index
].this = opno
;
2368 funny_match
[funny_match_index
++].other
= match
;
2375 /* p is used for address_operands. When we are called by
2376 gen_reload, no one will have checked that the address is
2377 strictly valid, i.e., that all pseudos requiring hard regs
2378 have gotten them. */
2380 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2385 /* No need to check general_operand again;
2386 it was done in insn-recog.c. Well, except that reload
2387 doesn't check the validity of its replacements, but
2388 that should only matter when there's a bug. */
2390 /* Anything goes unless it is a REG and really has a hard reg
2391 but the hard reg is not in the class GENERAL_REGS. */
2395 || GENERAL_REGS
== ALL_REGS
2396 || (reload_in_progress
2397 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2398 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2401 else if (strict
< 0 || general_operand (op
, mode
))
2406 /* This is used for a MATCH_SCRATCH in the cases when
2407 we don't actually need anything. So anything goes
2413 /* Memory operands must be valid, to the extent
2414 required by STRICT. */
2418 && !strict_memory_address_p (GET_MODE (op
),
2422 && !memory_address_p (GET_MODE (op
), XEXP (op
, 0)))
2426 /* Before reload, accept what reload can turn into mem. */
2427 else if (strict
< 0 && CONSTANT_P (op
))
2429 /* During reload, accept a pseudo */
2430 else if (reload_in_progress
&& REG_P (op
)
2431 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2437 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2438 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2444 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2445 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2451 if (GET_CODE (op
) == CONST_DOUBLE
2452 || (GET_CODE (op
) == CONST_VECTOR
2453 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2459 if (GET_CODE (op
) == CONST_DOUBLE
2460 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2465 if (GET_CODE (op
) == CONST_INT
2466 || (GET_CODE (op
) == CONST_DOUBLE
2467 && GET_MODE (op
) == VOIDmode
))
2470 if (CONSTANT_P (op
))
2475 if (GET_CODE (op
) == CONST_INT
2476 || (GET_CODE (op
) == CONST_DOUBLE
2477 && GET_MODE (op
) == VOIDmode
))
2489 if (GET_CODE (op
) == CONST_INT
2490 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2496 && ((strict
> 0 && ! offsettable_memref_p (op
))
2498 && !(CONSTANT_P (op
) || MEM_P (op
)))
2499 || (reload_in_progress
2501 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2506 if ((strict
> 0 && offsettable_memref_p (op
))
2507 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2508 /* Before reload, accept what reload can handle. */
2510 && (CONSTANT_P (op
) || MEM_P (op
)))
2511 /* During reload, accept a pseudo */
2512 || (reload_in_progress
&& REG_P (op
)
2513 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2522 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2528 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2529 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2531 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2534 #ifdef EXTRA_CONSTRAINT_STR
2535 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2538 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2539 /* Every memory operand can be reloaded to fit. */
2540 && ((strict
< 0 && MEM_P (op
))
2541 /* Before reload, accept what reload can turn
2543 || (strict
< 0 && CONSTANT_P (op
))
2544 /* During reload, accept a pseudo */
2545 || (reload_in_progress
&& REG_P (op
)
2546 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2548 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2549 /* Every address operand can be reloaded to fit. */
2556 while (p
+= len
, c
);
2558 constraints
[opno
] = p
;
2559 /* If this operand did not win somehow,
2560 this alternative loses. */
2564 /* This alternative won; the operands are ok.
2565 Change whichever operands this alternative says to change. */
2570 /* See if any earlyclobber operand conflicts with some other
2573 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2574 for (eopno
= seen_earlyclobber_at
;
2575 eopno
< recog_data
.n_operands
;
2577 /* Ignore earlyclobber operands now in memory,
2578 because we would often report failure when we have
2579 two memory operands, one of which was formerly a REG. */
2580 if (earlyclobber
[eopno
]
2581 && REG_P (recog_data
.operand
[eopno
]))
2582 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2583 if ((MEM_P (recog_data
.operand
[opno
])
2584 || recog_data
.operand_type
[opno
] != OP_OUT
)
2586 /* Ignore things like match_operator operands. */
2587 && *recog_data
.constraints
[opno
] != 0
2588 && ! (matching_operands
[opno
] == eopno
2589 && operands_match_p (recog_data
.operand
[opno
],
2590 recog_data
.operand
[eopno
]))
2591 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2592 recog_data
.operand
[eopno
]))
2597 while (--funny_match_index
>= 0)
2599 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2600 = recog_data
.operand
[funny_match
[funny_match_index
].this];
2607 which_alternative
++;
2609 while (which_alternative
< recog_data
.n_alternatives
);
2611 which_alternative
= -1;
2612 /* If we are about to reject this, but we are not to test strictly,
2613 try a very loose test. Only return failure if it fails also. */
2615 return constrain_operands (-1);
2620 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2621 is a hard reg in class CLASS when its regno is offset by OFFSET
2622 and changed to mode MODE.
2623 If REG occupies multiple hard regs, all of them must be in CLASS. */
2626 reg_fits_class_p (rtx operand
, enum reg_class cl
, int offset
,
2627 enum machine_mode mode
)
2629 int regno
= REGNO (operand
);
2634 if (regno
< FIRST_PSEUDO_REGISTER
2635 && TEST_HARD_REG_BIT (reg_class_contents
[(int) cl
],
2640 for (sr
= hard_regno_nregs
[regno
][mode
] - 1;
2642 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) cl
],
2651 /* Split single instruction. Helper function for split_all_insns and
2652 split_all_insns_noflow. Return last insn in the sequence if successful,
2653 or NULL if unsuccessful. */
2656 split_insn (rtx insn
)
2658 /* Split insns here to get max fine-grain parallelism. */
2659 rtx first
= PREV_INSN (insn
);
2660 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2665 /* try_split returns the NOTE that INSN became. */
2666 SET_INSN_DELETED (insn
);
2668 /* ??? Coddle to md files that generate subregs in post-reload
2669 splitters instead of computing the proper hard register. */
2670 if (reload_completed
&& first
!= last
)
2672 first
= NEXT_INSN (first
);
2676 cleanup_subreg_operands (first
);
2679 first
= NEXT_INSN (first
);
2685 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2688 split_all_insns (int upd_life
)
2694 blocks
= sbitmap_alloc (last_basic_block
);
2695 sbitmap_zero (blocks
);
2698 FOR_EACH_BB_REVERSE (bb
)
2701 bool finish
= false;
2703 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2705 /* Can't use `next_real_insn' because that might go across
2706 CODE_LABELS and short-out basic blocks. */
2707 next
= NEXT_INSN (insn
);
2708 finish
= (insn
== BB_END (bb
));
2711 rtx set
= single_set (insn
);
2713 /* Don't split no-op move insns. These should silently
2714 disappear later in final. Splitting such insns would
2715 break the code that handles REG_NO_CONFLICT blocks. */
2716 if (set
&& set_noop_p (set
))
2718 /* Nops get in the way while scheduling, so delete them
2719 now if register allocation has already been done. It
2720 is too risky to try to do this before register
2721 allocation, and there are unlikely to be very many
2722 nops then anyways. */
2723 if (reload_completed
)
2725 /* If the no-op set has a REG_UNUSED note, we need
2726 to update liveness information. */
2727 if (find_reg_note (insn
, REG_UNUSED
, NULL_RTX
))
2729 SET_BIT (blocks
, bb
->index
);
2732 /* ??? Is life info affected by deleting edges? */
2733 delete_insn_and_edges (insn
);
2738 rtx last
= split_insn (insn
);
2741 /* The split sequence may include barrier, but the
2742 BB boundary we are interested in will be set to
2745 while (BARRIER_P (last
))
2746 last
= PREV_INSN (last
);
2747 SET_BIT (blocks
, bb
->index
);
2757 int old_last_basic_block
= last_basic_block
;
2759 find_many_sub_basic_blocks (blocks
);
2761 if (old_last_basic_block
!= last_basic_block
&& upd_life
)
2762 blocks
= sbitmap_resize (blocks
, last_basic_block
, 1);
2765 if (changed
&& upd_life
)
2766 update_life_info (blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
2769 #ifdef ENABLE_CHECKING
2770 verify_flow_info ();
2773 sbitmap_free (blocks
);
2776 /* Same as split_all_insns, but do not expect CFG to be available.
2777 Used by machine dependent reorg passes. */
2780 split_all_insns_noflow (void)
2784 for (insn
= get_insns (); insn
; insn
= next
)
2786 next
= NEXT_INSN (insn
);
2789 /* Don't split no-op move insns. These should silently
2790 disappear later in final. Splitting such insns would
2791 break the code that handles REG_NO_CONFLICT blocks. */
2792 rtx set
= single_set (insn
);
2793 if (set
&& set_noop_p (set
))
2795 /* Nops get in the way while scheduling, so delete them
2796 now if register allocation has already been done. It
2797 is too risky to try to do this before register
2798 allocation, and there are unlikely to be very many
2801 ??? Should we use delete_insn when the CFG isn't valid? */
2802 if (reload_completed
)
2803 delete_insn_and_edges (insn
);
2812 #ifdef HAVE_peephole2
2813 struct peep2_insn_data
2819 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2820 static int peep2_current
;
2821 /* The number of instructions available to match a peep2. */
2822 int peep2_current_count
;
2824 /* A non-insn marker indicating the last insn of the block.
2825 The live_before regset for this element is correct, indicating
2826 global_live_at_end for the block. */
2827 #define PEEP2_EOB pc_rtx
2829 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2830 does not exist. Used by the recognizer to find the next insn to match
2831 in a multi-insn pattern. */
2834 peep2_next_insn (int n
)
2836 gcc_assert (n
<= peep2_current_count
);
2839 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2840 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2842 return peep2_insn_data
[n
].insn
;
2845 /* Return true if REGNO is dead before the Nth non-note insn
2849 peep2_regno_dead_p (int ofs
, int regno
)
2851 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
2853 ofs
+= peep2_current
;
2854 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2855 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2857 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
2859 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
2862 /* Similarly for a REG. */
2865 peep2_reg_dead_p (int ofs
, rtx reg
)
2869 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
2871 ofs
+= peep2_current
;
2872 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2873 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2875 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
2877 regno
= REGNO (reg
);
2878 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2880 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
2885 /* Try to find a hard register of mode MODE, matching the register class in
2886 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2887 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2888 in which case the only condition is that the register must be available
2889 before CURRENT_INSN.
2890 Registers that already have bits set in REG_SET will not be considered.
2892 If an appropriate register is available, it will be returned and the
2893 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2897 peep2_find_free_register (int from
, int to
, const char *class_str
,
2898 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
2900 static int search_ofs
;
2905 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
2906 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
2908 from
+= peep2_current
;
2909 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
2910 from
-= MAX_INSNS_PER_PEEP2
+ 1;
2911 to
+= peep2_current
;
2912 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
2913 to
-= MAX_INSNS_PER_PEEP2
+ 1;
2915 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
2916 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
2920 HARD_REG_SET this_live
;
2922 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
2924 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
2925 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
2926 IOR_HARD_REG_SET (live
, this_live
);
2929 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
2930 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
2932 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2934 int raw_regno
, regno
, success
, j
;
2936 /* Distribute the free registers as much as possible. */
2937 raw_regno
= search_ofs
+ i
;
2938 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
2939 raw_regno
-= FIRST_PSEUDO_REGISTER
;
2940 #ifdef REG_ALLOC_ORDER
2941 regno
= reg_alloc_order
[raw_regno
];
2946 /* Don't allocate fixed registers. */
2947 if (fixed_regs
[regno
])
2949 /* Make sure the register is of the right class. */
2950 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
))
2952 /* And can support the mode we need. */
2953 if (! HARD_REGNO_MODE_OK (regno
, mode
))
2955 /* And that we don't create an extra save/restore. */
2956 if (! call_used_regs
[regno
] && ! regs_ever_live
[regno
])
2958 /* And we don't clobber traceback for noreturn functions. */
2959 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
2960 && (! reload_completed
|| frame_pointer_needed
))
2964 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
2966 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
2967 || TEST_HARD_REG_BIT (live
, regno
+ j
))
2975 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
2976 SET_HARD_REG_BIT (*reg_set
, regno
+ j
);
2978 /* Start the next search with the next register. */
2979 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
2981 search_ofs
= raw_regno
;
2983 return gen_rtx_REG (mode
, regno
);
2991 /* Perform the peephole2 optimization pass. */
2994 peephole2_optimize (void)
3000 #ifdef HAVE_conditional_execution
3004 bool do_cleanup_cfg
= false;
3005 bool do_global_life_update
= false;
3006 bool do_rebuild_jump_labels
= false;
3008 /* Initialize the regsets we're going to use. */
3009 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3010 peep2_insn_data
[i
].live_before
= ALLOC_REG_SET (®_obstack
);
3011 live
= ALLOC_REG_SET (®_obstack
);
3013 #ifdef HAVE_conditional_execution
3014 blocks
= sbitmap_alloc (last_basic_block
);
3015 sbitmap_zero (blocks
);
3018 count_or_remove_death_notes (NULL
, 1);
3021 FOR_EACH_BB_REVERSE (bb
)
3023 struct propagate_block_info
*pbi
;
3024 reg_set_iterator rsi
;
3027 /* Indicate that all slots except the last holds invalid data. */
3028 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3029 peep2_insn_data
[i
].insn
= NULL_RTX
;
3030 peep2_current_count
= 0;
3032 /* Indicate that the last slot contains live_after data. */
3033 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3034 peep2_current
= MAX_INSNS_PER_PEEP2
;
3036 /* Start up propagation. */
3037 COPY_REG_SET (live
, bb
->il
.rtl
->global_live_at_end
);
3038 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3040 #ifdef HAVE_conditional_execution
3041 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, 0);
3043 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, PROP_DEATH_NOTES
);
3046 for (insn
= BB_END (bb
); ; insn
= prev
)
3048 prev
= PREV_INSN (insn
);
3051 rtx
try, before_try
, x
;
3054 bool was_call
= false;
3056 /* Record this insn. */
3057 if (--peep2_current
< 0)
3058 peep2_current
= MAX_INSNS_PER_PEEP2
;
3059 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
3060 && peep2_insn_data
[peep2_current
].insn
== NULL_RTX
)
3061 peep2_current_count
++;
3062 peep2_insn_data
[peep2_current
].insn
= insn
;
3063 propagate_one_insn (pbi
, insn
);
3064 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3066 if (RTX_FRAME_RELATED_P (insn
))
3068 /* If an insn has RTX_FRAME_RELATED_P set, peephole
3069 substitution would lose the
3070 REG_FRAME_RELATED_EXPR that is attached. */
3071 peep2_current_count
= 0;
3075 /* Match the peephole. */
3076 try = peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3080 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3081 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3082 cfg-related call notes. */
3083 for (i
= 0; i
<= match_len
; ++i
)
3086 rtx old_insn
, new_insn
, note
;
3088 j
= i
+ peep2_current
;
3089 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3090 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3091 old_insn
= peep2_insn_data
[j
].insn
;
3092 if (!CALL_P (old_insn
))
3097 while (new_insn
!= NULL_RTX
)
3099 if (CALL_P (new_insn
))
3101 new_insn
= NEXT_INSN (new_insn
);
3104 gcc_assert (new_insn
!= NULL_RTX
);
3106 CALL_INSN_FUNCTION_USAGE (new_insn
)
3107 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3109 for (note
= REG_NOTES (old_insn
);
3111 note
= XEXP (note
, 1))
3112 switch (REG_NOTE_KIND (note
))
3116 REG_NOTES (new_insn
)
3117 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note
),
3119 REG_NOTES (new_insn
));
3121 /* Discard all other reg notes. */
3125 /* Croak if there is another call in the sequence. */
3126 while (++i
<= match_len
)
3128 j
= i
+ peep2_current
;
3129 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3130 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3131 old_insn
= peep2_insn_data
[j
].insn
;
3132 gcc_assert (!CALL_P (old_insn
));
3137 i
= match_len
+ peep2_current
;
3138 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3139 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3141 note
= find_reg_note (peep2_insn_data
[i
].insn
,
3142 REG_EH_REGION
, NULL_RTX
);
3144 /* Replace the old sequence with the new. */
3145 try = emit_insn_after_setloc (try, peep2_insn_data
[i
].insn
,
3146 INSN_LOCATOR (peep2_insn_data
[i
].insn
));
3147 before_try
= PREV_INSN (insn
);
3148 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
);
3150 /* Re-insert the EH_REGION notes. */
3151 if (note
|| (was_call
&& nonlocal_goto_handler_labels
))
3156 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3157 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3160 for (x
= try ; x
!= before_try
; x
= PREV_INSN (x
))
3162 || (flag_non_call_exceptions
3163 && may_trap_p (PATTERN (x
))
3164 && !find_reg_note (x
, REG_EH_REGION
, NULL
)))
3168 = gen_rtx_EXPR_LIST (REG_EH_REGION
,
3172 if (x
!= BB_END (bb
) && eh_edge
)
3177 nfte
= split_block (bb
, x
);
3178 flags
= (eh_edge
->flags
3179 & (EDGE_EH
| EDGE_ABNORMAL
));
3181 flags
|= EDGE_ABNORMAL_CALL
;
3182 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3185 nehe
->probability
= eh_edge
->probability
;
3187 = REG_BR_PROB_BASE
- nehe
->probability
;
3189 do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3190 #ifdef HAVE_conditional_execution
3191 SET_BIT (blocks
, nfte
->dest
->index
);
3199 /* Converting possibly trapping insn to non-trapping is
3200 possible. Zap dummy outgoing edges. */
3201 do_cleanup_cfg
|= purge_dead_edges (bb
);
3204 #ifdef HAVE_conditional_execution
3205 /* With conditional execution, we cannot back up the
3206 live information so easily, since the conditional
3207 death data structures are not so self-contained.
3208 So record that we've made a modification to this
3209 block and update life information at the end. */
3210 SET_BIT (blocks
, bb
->index
);
3213 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3214 peep2_insn_data
[i
].insn
= NULL_RTX
;
3215 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3216 peep2_current_count
= 0;
3218 /* Back up lifetime information past the end of the
3219 newly created sequence. */
3220 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3222 COPY_REG_SET (live
, peep2_insn_data
[i
].live_before
);
3224 /* Update life information for the new sequence. */
3231 i
= MAX_INSNS_PER_PEEP2
;
3232 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
3233 && peep2_insn_data
[i
].insn
== NULL_RTX
)
3234 peep2_current_count
++;
3235 peep2_insn_data
[i
].insn
= x
;
3236 propagate_one_insn (pbi
, x
);
3237 COPY_REG_SET (peep2_insn_data
[i
].live_before
, live
);
3243 /* ??? Should verify that LIVE now matches what we
3244 had before the new sequence. */
3249 /* If we generated a jump instruction, it won't have
3250 JUMP_LABEL set. Recompute after we're done. */
3251 for (x
= try; x
!= before_try
; x
= PREV_INSN (x
))
3254 do_rebuild_jump_labels
= true;
3260 if (insn
== BB_HEAD (bb
))
3264 /* Some peepholes can decide the don't need one or more of their
3265 inputs. If this happens, local life update is not enough. */
3266 EXECUTE_IF_AND_COMPL_IN_BITMAP (bb
->il
.rtl
->global_live_at_start
, live
,
3269 do_global_life_update
= true;
3273 free_propagate_block_info (pbi
);
3276 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3277 FREE_REG_SET (peep2_insn_data
[i
].live_before
);
3278 FREE_REG_SET (live
);
3280 if (do_rebuild_jump_labels
)
3281 rebuild_jump_labels (get_insns ());
3283 /* If we eliminated EH edges, we may be able to merge blocks. Further,
3284 we've changed global life since exception handlers are no longer
3289 do_global_life_update
= true;
3291 if (do_global_life_update
)
3292 update_life_info (0, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
3293 #ifdef HAVE_conditional_execution
3296 count_or_remove_death_notes (blocks
, 1);
3297 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
3299 sbitmap_free (blocks
);
3302 #endif /* HAVE_peephole2 */
3304 /* Common predicates for use with define_bypass. */
3306 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3307 data not the address operand(s) of the store. IN_INSN must be
3308 single_set. OUT_INSN must be either a single_set or a PARALLEL with
3312 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3314 rtx out_set
, in_set
;
3316 in_set
= single_set (in_insn
);
3317 gcc_assert (in_set
);
3319 if (!MEM_P (SET_DEST (in_set
)))
3322 out_set
= single_set (out_insn
);
3325 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3333 out_pat
= PATTERN (out_insn
);
3334 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3336 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3338 rtx exp
= XVECEXP (out_pat
, 0, i
);
3340 if (GET_CODE (exp
) == CLOBBER
)
3343 gcc_assert (GET_CODE (exp
) == SET
);
3345 if (reg_mentioned_p (SET_DEST (exp
), SET_DEST (in_set
)))
3353 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3354 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3355 or multiple set; IN_INSN should be single_set for truth, but for convenience
3356 of insn categorization may be any JUMP or CALL insn. */
3359 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3361 rtx out_set
, in_set
;
3363 in_set
= single_set (in_insn
);
3366 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3370 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3372 in_set
= SET_SRC (in_set
);
3374 out_set
= single_set (out_insn
);
3377 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3378 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3386 out_pat
= PATTERN (out_insn
);
3387 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3389 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3391 rtx exp
= XVECEXP (out_pat
, 0, i
);
3393 if (GET_CODE (exp
) == CLOBBER
)
3396 gcc_assert (GET_CODE (exp
) == SET
);
3398 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3399 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3408 gate_handle_peephole2 (void)
3410 return (optimize
> 0 && flag_peephole2
);
3414 rest_of_handle_peephole2 (void)
3416 #ifdef HAVE_peephole2
3417 peephole2_optimize ();
3422 struct tree_opt_pass pass_peephole2
=
3424 "peephole2", /* name */
3425 gate_handle_peephole2
, /* gate */
3426 rest_of_handle_peephole2
, /* execute */
3429 0, /* static_pass_number */
3430 TV_PEEPHOLE2
, /* tv_id */
3431 0, /* properties_required */
3432 0, /* properties_provided */
3433 0, /* properties_destroyed */
3434 0, /* todo_flags_start */
3435 TODO_dump_func
, /* todo_flags_finish */
3440 rest_of_handle_split_all_insns (void)
3442 split_all_insns (1);
3446 struct tree_opt_pass pass_split_all_insns
=
3448 "split1", /* name */
3450 rest_of_handle_split_all_insns
, /* execute */
3453 0, /* static_pass_number */
3455 0, /* properties_required */
3456 0, /* properties_provided */
3457 0, /* properties_destroyed */
3458 0, /* todo_flags_start */
3459 TODO_dump_func
, /* todo_flags_finish */
3463 /* The placement of the splitting that we do for shorten_branches
3464 depends on whether regstack is used by the target or not. */
3466 gate_do_final_split (void)
3468 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3475 struct tree_opt_pass pass_split_for_shorten_branches
=
3477 "split3", /* name */
3478 gate_do_final_split
, /* gate */
3479 split_all_insns_noflow
, /* execute */
3482 0, /* static_pass_number */
3483 TV_SHORTEN_BRANCH
, /* tv_id */
3484 0, /* properties_required */
3485 0, /* properties_provided */
3486 0, /* properties_destroyed */
3487 0, /* todo_flags_start */
3488 TODO_dump_func
, /* todo_flags_finish */
3494 gate_handle_split_before_regstack (void)
3496 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3497 /* If flow2 creates new instructions which need splitting
3498 and scheduling after reload is not done, they might not be
3499 split until final which doesn't allow splitting
3500 if HAVE_ATTR_length. */
3501 # ifdef INSN_SCHEDULING
3502 return (optimize
&& !flag_schedule_insns_after_reload
);
3511 struct tree_opt_pass pass_split_before_regstack
=
3513 "split2", /* name */
3514 gate_handle_split_before_regstack
, /* gate */
3515 rest_of_handle_split_all_insns
, /* execute */
3518 0, /* static_pass_number */
3519 TV_SHORTEN_BRANCH
, /* tv_id */
3520 0, /* properties_required */
3521 0, /* properties_provided */
3522 0, /* properties_destroyed */
3523 0, /* todo_flags_start */
3524 TODO_dump_func
, /* todo_flags_finish */