| blob | 09669159c770046b8a281ceb1be609251fcde337 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (CA_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MOVSI_GOT 8)
63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
64 (UNSPEC_FCTIWZ 10)
65 (UNSPEC_FRIM 11)
66 (UNSPEC_FRIN 12)
67 (UNSPEC_FRIP 13)
68 (UNSPEC_FRIZ 14)
69 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
70 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
71 (UNSPEC_TLSGD 17)
72 (UNSPEC_TLSLD 18)
73 (UNSPEC_MOVESI_FROM_CR 19)
74 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPREL 21)
76 (UNSPEC_TLSDTPRELHA 22)
77 (UNSPEC_TLSDTPRELLO 23)
78 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPREL 25)
80 (UNSPEC_TLSTPRELHA 26)
81 (UNSPEC_TLSTPRELLO 27)
82 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_TLSTLS 29)
84 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
85 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
86 (UNSPEC_STFIWX 32)
87 (UNSPEC_POPCNTB 33)
88 (UNSPEC_FRES 34)
89 (UNSPEC_SP_SET 35)
90 (UNSPEC_SP_TEST 36)
91 (UNSPEC_SYNC 37)
92 (UNSPEC_LWSYNC 38)
93 (UNSPEC_ISYNC 39)
94 (UNSPEC_SYNC_OP 40)
95 (UNSPEC_ATOMIC 41)
96 (UNSPEC_CMPXCHG 42)
97 (UNSPEC_XCHG 43)
98 (UNSPEC_AND 44)
99 (UNSPEC_DLMZB 45)
100 (UNSPEC_DLMZB_CR 46)
101 (UNSPEC_DLMZB_STRLEN 47)
102 (UNSPEC_RSQRT 48)
103 (UNSPEC_TOCREL 49)
104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
106 ])
108 ;;
109 ;; UNSPEC_VOLATILE usage
110 ;;
112 (define_constants
113 [(UNSPECV_BLOCK 0)
114 (UNSPECV_LL 1) ; load-locked
115 (UNSPECV_SC 2) ; store-conditional
116 (UNSPECV_EH_RR 9) ; eh_reg_restore
117 ])
118 \f
119 ;; Define an insn type attribute. This is used in function unit delay
120 ;; computations.
121 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
122 (const_string "integer"))
124 ;; Define floating point instruction sub-types for use with Xfpu.md
125 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
127 ;; Length (in bytes).
128 ; '(pc)' in the following doesn't include the instruction itself; it is
129 ; calculated as if the instruction had zero size.
130 (define_attr "length" ""
131 (if_then_else (eq_attr "type" "branch")
132 (if_then_else (and (ge (minus (match_dup 0) (pc))
133 (const_int -32768))
134 (lt (minus (match_dup 0) (pc))
135 (const_int 32764)))
136 (const_int 4)
137 (const_int 8))
138 (const_int 4)))
140 ;; Processor type -- this attribute must exactly match the processor_type
141 ;; enumeration in rs6000.h.
143 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
144 (const (symbol_ref "rs6000_cpu_attr")))
147 ;; If this instruction is microcoded on the CELL processor
148 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
149 (define_attr "cell_micro" "not,conditional,always"
150 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
151 (const_string "always")
152 (const_string "not")))
154 (automata_option "ndfa")
156 (include "rios1.md")
157 (include "rios2.md")
158 (include "rs64.md")
159 (include "mpc.md")
160 (include "40x.md")
161 (include "440.md")
162 (include "476.md")
163 (include "603.md")
164 (include "6xx.md")
165 (include "7xx.md")
166 (include "7450.md")
167 (include "8540.md")
168 (include "e300c2c3.md")
169 (include "e500mc.md")
170 (include "e500mc64.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
174 (include "power7.md")
175 (include "cell.md")
176 (include "xfpu.md")
177 (include "a2.md")
178 (include "titan.md")
180 (include "predicates.md")
181 (include "constraints.md")
183 (include "darwin.md")
185 \f
186 ;; Mode iterators
188 ; This mode iterator allows :GPR to be used to indicate the allowable size
189 ; of whole values in GPRs.
190 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
192 ; Any supported integer mode.
193 (define_mode_iterator INT [QI HI SI DI TI])
195 ; Any supported integer mode that fits in one register.
196 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
198 ; extend modes for DImode
199 (define_mode_iterator QHSI [QI HI SI])
201 ; SImode or DImode, even if DImode doesn't fit in GPRs.
202 (define_mode_iterator SDI [SI DI])
204 ; The size of a pointer. Also, the size of the value that a record-condition
205 ; (one with a '.') will compare; and the size used for arithmetic carries.
206 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
208 ; Any hardware-supported floating-point mode
209 (define_mode_iterator FP [
210 (SF "TARGET_HARD_FLOAT
211 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
212 (DF "TARGET_HARD_FLOAT
213 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
214 (TF "!TARGET_IEEEQUAD
215 && TARGET_HARD_FLOAT
216 && (TARGET_FPRS || TARGET_E500_DOUBLE)
217 && TARGET_LONG_DOUBLE_128")
218 (DD "TARGET_DFP")
219 (TD "TARGET_DFP")])
221 ; These modes do not fit in integer registers in 32-bit mode.
222 ; but on e500v2, the gpr are 64 bit registers
223 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
225 ;; Iterator for reciprocal estimate instructions
226 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
228 ; Various instructions that come in SI and DI forms.
229 ; A generic w/d attribute, for things like cmpw/cmpd.
230 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
232 ; DImode bits
233 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
235 ;; ISEL/ISEL64 target selection
236 (define_mode_attr sel [(SI "") (DI "64")])
238 ;; Suffix for reload patterns
239 (define_mode_attr ptrsize [(SI "32bit")
240 (DI "64bit")])
242 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
243 (DI "TARGET_64BIT")])
245 (define_mode_attr mptrsize [(SI "si")
246 (DI "di")])
248 (define_mode_attr rreg [(SF "f")
249 (DF "Ws")
250 (V4SF "Wf")
251 (V2DF "Wd")])
253 \f
254 ;; Start with fixed-point load and store insns. Here we put only the more
255 ;; complex forms. Basic data transfer is done later.
257 (define_expand "zero_extend<mode>di2"
258 [(set (match_operand:DI 0 "gpc_reg_operand" "")
259 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
260 "TARGET_POWERPC64"
261 "")
263 (define_insn "*zero_extend<mode>di2_internal1"
264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
265 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
266 "TARGET_POWERPC64"
267 "@
268 l<wd>z%U1%X1 %0,%1
269 rldicl %0,%1,0,<dbits>"
270 [(set_attr "type" "load,*")])
272 (define_insn "*zero_extend<mode>di2_internal2"
273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
274 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
275 (const_int 0)))
276 (clobber (match_scratch:DI 2 "=r,r"))]
277 "TARGET_64BIT"
278 "@
279 rldicl. %2,%1,0,<dbits>
280 #"
281 [(set_attr "type" "compare")
282 (set_attr "length" "4,8")])
284 (define_split
285 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
286 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
287 (const_int 0)))
288 (clobber (match_scratch:DI 2 ""))]
289 "TARGET_POWERPC64 && reload_completed"
290 [(set (match_dup 2)
291 (zero_extend:DI (match_dup 1)))
292 (set (match_dup 0)
293 (compare:CC (match_dup 2)
294 (const_int 0)))]
295 "")
297 (define_insn "*zero_extend<mode>di2_internal3"
298 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
299 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
300 (const_int 0)))
301 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
302 (zero_extend:DI (match_dup 1)))]
303 "TARGET_64BIT"
304 "@
305 rldicl. %0,%1,0,<dbits>
306 #"
307 [(set_attr "type" "compare")
308 (set_attr "length" "4,8")])
310 (define_split
311 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
312 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
313 (const_int 0)))
314 (set (match_operand:DI 0 "gpc_reg_operand" "")
315 (zero_extend:DI (match_dup 1)))]
316 "TARGET_POWERPC64 && reload_completed"
317 [(set (match_dup 0)
318 (zero_extend:DI (match_dup 1)))
319 (set (match_dup 2)
320 (compare:CC (match_dup 0)
321 (const_int 0)))]
322 "")
324 (define_insn "extendqidi2"
325 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
326 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
327 "TARGET_POWERPC64"
328 "extsb %0,%1"
329 [(set_attr "type" "exts")])
331 (define_insn ""
332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
333 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
334 (const_int 0)))
335 (clobber (match_scratch:DI 2 "=r,r"))]
336 "TARGET_64BIT"
337 "@
338 extsb. %2,%1
339 #"
340 [(set_attr "type" "compare")
341 (set_attr "length" "4,8")])
343 (define_split
344 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
345 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
346 (const_int 0)))
347 (clobber (match_scratch:DI 2 ""))]
348 "TARGET_POWERPC64 && reload_completed"
349 [(set (match_dup 2)
350 (sign_extend:DI (match_dup 1)))
351 (set (match_dup 0)
352 (compare:CC (match_dup 2)
353 (const_int 0)))]
354 "")
356 (define_insn ""
357 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
358 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
359 (const_int 0)))
360 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
361 (sign_extend:DI (match_dup 1)))]
362 "TARGET_64BIT"
363 "@
364 extsb. %0,%1
365 #"
366 [(set_attr "type" "compare")
367 (set_attr "length" "4,8")])
369 (define_split
370 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
371 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
372 (const_int 0)))
373 (set (match_operand:DI 0 "gpc_reg_operand" "")
374 (sign_extend:DI (match_dup 1)))]
375 "TARGET_POWERPC64 && reload_completed"
376 [(set (match_dup 0)
377 (sign_extend:DI (match_dup 1)))
378 (set (match_dup 2)
379 (compare:CC (match_dup 0)
380 (const_int 0)))]
381 "")
383 (define_expand "extendhidi2"
384 [(set (match_operand:DI 0 "gpc_reg_operand" "")
385 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
386 "TARGET_POWERPC64"
387 "")
389 (define_insn ""
390 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
391 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
392 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
393 "@
394 lha%U1%X1 %0,%1
395 extsh %0,%1"
396 [(set_attr "type" "load_ext,exts")])
398 (define_insn ""
399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
400 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
401 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
402 "extsh %0,%1"
403 [(set_attr "type" "exts")])
405 (define_insn ""
406 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
407 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
408 (const_int 0)))
409 (clobber (match_scratch:DI 2 "=r,r"))]
410 "TARGET_64BIT"
411 "@
412 extsh. %2,%1
413 #"
414 [(set_attr "type" "compare")
415 (set_attr "length" "4,8")])
417 (define_split
418 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
419 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
420 (const_int 0)))
421 (clobber (match_scratch:DI 2 ""))]
422 "TARGET_POWERPC64 && reload_completed"
423 [(set (match_dup 2)
424 (sign_extend:DI (match_dup 1)))
425 (set (match_dup 0)
426 (compare:CC (match_dup 2)
427 (const_int 0)))]
428 "")
430 (define_insn ""
431 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
432 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
433 (const_int 0)))
434 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
435 (sign_extend:DI (match_dup 1)))]
436 "TARGET_64BIT"
437 "@
438 extsh. %0,%1
439 #"
440 [(set_attr "type" "compare")
441 (set_attr "length" "4,8")])
443 (define_split
444 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
445 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
446 (const_int 0)))
447 (set (match_operand:DI 0 "gpc_reg_operand" "")
448 (sign_extend:DI (match_dup 1)))]
449 "TARGET_POWERPC64 && reload_completed"
450 [(set (match_dup 0)
451 (sign_extend:DI (match_dup 1)))
452 (set (match_dup 2)
453 (compare:CC (match_dup 0)
454 (const_int 0)))]
455 "")
457 (define_expand "extendsidi2"
458 [(set (match_operand:DI 0 "gpc_reg_operand" "")
459 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
460 "TARGET_POWERPC64"
461 "")
463 (define_insn ""
464 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
465 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
466 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
467 "@
468 lwa%U1%X1 %0,%1
469 extsw %0,%1"
470 [(set_attr "type" "load_ext,exts")])
472 (define_insn ""
473 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
474 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
475 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
476 "extsw %0,%1"
477 [(set_attr "type" "exts")])
479 (define_insn ""
480 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
481 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
482 (const_int 0)))
483 (clobber (match_scratch:DI 2 "=r,r"))]
484 "TARGET_64BIT"
485 "@
486 extsw. %2,%1
487 #"
488 [(set_attr "type" "compare")
489 (set_attr "length" "4,8")])
491 (define_split
492 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
493 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
494 (const_int 0)))
495 (clobber (match_scratch:DI 2 ""))]
496 "TARGET_POWERPC64 && reload_completed"
497 [(set (match_dup 2)
498 (sign_extend:DI (match_dup 1)))
499 (set (match_dup 0)
500 (compare:CC (match_dup 2)
501 (const_int 0)))]
502 "")
504 (define_insn ""
505 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
506 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
507 (const_int 0)))
508 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
509 (sign_extend:DI (match_dup 1)))]
510 "TARGET_64BIT"
511 "@
512 extsw. %0,%1
513 #"
514 [(set_attr "type" "compare")
515 (set_attr "length" "4,8")])
517 (define_split
518 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
519 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
520 (const_int 0)))
521 (set (match_operand:DI 0 "gpc_reg_operand" "")
522 (sign_extend:DI (match_dup 1)))]
523 "TARGET_POWERPC64 && reload_completed"
524 [(set (match_dup 0)
525 (sign_extend:DI (match_dup 1)))
526 (set (match_dup 2)
527 (compare:CC (match_dup 0)
528 (const_int 0)))]
529 "")
531 (define_expand "zero_extendqisi2"
532 [(set (match_operand:SI 0 "gpc_reg_operand" "")
533 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
534 ""
535 "")
537 (define_insn ""
538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
539 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
540 ""
541 "@
542 lbz%U1%X1 %0,%1
543 {rlinm|rlwinm} %0,%1,0,0xff"
544 [(set_attr "type" "load,*")])
546 (define_insn ""
547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
548 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
549 (const_int 0)))
550 (clobber (match_scratch:SI 2 "=r,r"))]
551 ""
552 "@
553 {andil.|andi.} %2,%1,0xff
554 #"
555 [(set_attr "type" "fast_compare,compare")
556 (set_attr "length" "4,8")])
558 (define_split
559 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
560 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
561 (const_int 0)))
562 (clobber (match_scratch:SI 2 ""))]
563 "reload_completed"
564 [(set (match_dup 2)
565 (zero_extend:SI (match_dup 1)))
566 (set (match_dup 0)
567 (compare:CC (match_dup 2)
568 (const_int 0)))]
569 "")
571 (define_insn ""
572 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
573 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
574 (const_int 0)))
575 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
576 (zero_extend:SI (match_dup 1)))]
577 ""
578 "@
579 {andil.|andi.} %0,%1,0xff
580 #"
581 [(set_attr "type" "fast_compare,compare")
582 (set_attr "length" "4,8")])
584 (define_split
585 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
586 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
587 (const_int 0)))
588 (set (match_operand:SI 0 "gpc_reg_operand" "")
589 (zero_extend:SI (match_dup 1)))]
590 "reload_completed"
591 [(set (match_dup 0)
592 (zero_extend:SI (match_dup 1)))
593 (set (match_dup 2)
594 (compare:CC (match_dup 0)
595 (const_int 0)))]
596 "")
598 (define_expand "extendqisi2"
599 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
600 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
601 ""
602 "
603 {
604 if (TARGET_POWERPC)
605 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
606 else if (TARGET_POWER)
607 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
608 else
609 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
610 DONE;
611 }")
613 (define_insn "extendqisi2_ppc"
614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
616 "TARGET_POWERPC"
617 "extsb %0,%1"
618 [(set_attr "type" "exts")])
620 (define_insn ""
621 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
622 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
623 (const_int 0)))
624 (clobber (match_scratch:SI 2 "=r,r"))]
625 "TARGET_POWERPC"
626 "@
627 extsb. %2,%1
628 #"
629 [(set_attr "type" "compare")
630 (set_attr "length" "4,8")])
632 (define_split
633 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
634 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
635 (const_int 0)))
636 (clobber (match_scratch:SI 2 ""))]
637 "TARGET_POWERPC && reload_completed"
638 [(set (match_dup 2)
639 (sign_extend:SI (match_dup 1)))
640 (set (match_dup 0)
641 (compare:CC (match_dup 2)
642 (const_int 0)))]
643 "")
645 (define_insn ""
646 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
647 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
648 (const_int 0)))
649 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
650 (sign_extend:SI (match_dup 1)))]
651 "TARGET_POWERPC"
652 "@
653 extsb. %0,%1
654 #"
655 [(set_attr "type" "compare")
656 (set_attr "length" "4,8")])
658 (define_split
659 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
660 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
661 (const_int 0)))
662 (set (match_operand:SI 0 "gpc_reg_operand" "")
663 (sign_extend:SI (match_dup 1)))]
664 "TARGET_POWERPC && reload_completed"
665 [(set (match_dup 0)
666 (sign_extend:SI (match_dup 1)))
667 (set (match_dup 2)
668 (compare:CC (match_dup 0)
669 (const_int 0)))]
670 "")
672 (define_expand "extendqisi2_power"
673 [(parallel [(set (match_dup 2)
674 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
675 (const_int 24)))
676 (clobber (scratch:SI))])
677 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
678 (ashiftrt:SI (match_dup 2)
679 (const_int 24)))
680 (clobber (scratch:SI))])]
681 "TARGET_POWER"
682 "
683 { operands[1] = gen_lowpart (SImode, operands[1]);
684 operands[2] = gen_reg_rtx (SImode); }")
686 (define_expand "extendqisi2_no_power"
687 [(set (match_dup 2)
688 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
689 (const_int 24)))
690 (set (match_operand:SI 0 "gpc_reg_operand" "")
691 (ashiftrt:SI (match_dup 2)
692 (const_int 24)))]
693 "! TARGET_POWER && ! TARGET_POWERPC"
694 "
695 { operands[1] = gen_lowpart (SImode, operands[1]);
696 operands[2] = gen_reg_rtx (SImode); }")
698 (define_expand "zero_extendqihi2"
699 [(set (match_operand:HI 0 "gpc_reg_operand" "")
700 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
701 ""
702 "")
704 (define_insn ""
705 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
706 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
707 ""
708 "@
709 lbz%U1%X1 %0,%1
710 {rlinm|rlwinm} %0,%1,0,0xff"
711 [(set_attr "type" "load,*")])
713 (define_insn ""
714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
715 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
716 (const_int 0)))
717 (clobber (match_scratch:HI 2 "=r,r"))]
718 ""
719 "@
720 {andil.|andi.} %2,%1,0xff
721 #"
722 [(set_attr "type" "fast_compare,compare")
723 (set_attr "length" "4,8")])
725 (define_split
726 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
727 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
728 (const_int 0)))
729 (clobber (match_scratch:HI 2 ""))]
730 "reload_completed"
731 [(set (match_dup 2)
732 (zero_extend:HI (match_dup 1)))
733 (set (match_dup 0)
734 (compare:CC (match_dup 2)
735 (const_int 0)))]
736 "")
738 (define_insn ""
739 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
740 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
741 (const_int 0)))
742 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
743 (zero_extend:HI (match_dup 1)))]
744 ""
745 "@
746 {andil.|andi.} %0,%1,0xff
747 #"
748 [(set_attr "type" "fast_compare,compare")
749 (set_attr "length" "4,8")])
751 (define_split
752 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
753 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
754 (const_int 0)))
755 (set (match_operand:HI 0 "gpc_reg_operand" "")
756 (zero_extend:HI (match_dup 1)))]
757 "reload_completed"
758 [(set (match_dup 0)
759 (zero_extend:HI (match_dup 1)))
760 (set (match_dup 2)
761 (compare:CC (match_dup 0)
762 (const_int 0)))]
763 "")
765 (define_expand "extendqihi2"
766 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
767 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
768 ""
769 "
770 {
771 if (TARGET_POWERPC)
772 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
773 else if (TARGET_POWER)
774 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
775 else
776 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
777 DONE;
778 }")
780 (define_insn "extendqihi2_ppc"
781 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
782 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
783 "TARGET_POWERPC"
784 "extsb %0,%1"
785 [(set_attr "type" "exts")])
787 (define_insn ""
788 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
789 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
790 (const_int 0)))
791 (clobber (match_scratch:HI 2 "=r,r"))]
792 "TARGET_POWERPC"
793 "@
794 extsb. %2,%1
795 #"
796 [(set_attr "type" "compare")
797 (set_attr "length" "4,8")])
799 (define_split
800 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
801 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
802 (const_int 0)))
803 (clobber (match_scratch:HI 2 ""))]
804 "TARGET_POWERPC && reload_completed"
805 [(set (match_dup 2)
806 (sign_extend:HI (match_dup 1)))
807 (set (match_dup 0)
808 (compare:CC (match_dup 2)
809 (const_int 0)))]
810 "")
812 (define_insn ""
813 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
814 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815 (const_int 0)))
816 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
817 (sign_extend:HI (match_dup 1)))]
818 "TARGET_POWERPC"
819 "@
820 extsb. %0,%1
821 #"
822 [(set_attr "type" "compare")
823 (set_attr "length" "4,8")])
825 (define_split
826 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
827 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
828 (const_int 0)))
829 (set (match_operand:HI 0 "gpc_reg_operand" "")
830 (sign_extend:HI (match_dup 1)))]
831 "TARGET_POWERPC && reload_completed"
832 [(set (match_dup 0)
833 (sign_extend:HI (match_dup 1)))
834 (set (match_dup 2)
835 (compare:CC (match_dup 0)
836 (const_int 0)))]
837 "")
839 (define_expand "extendqihi2_power"
840 [(parallel [(set (match_dup 2)
841 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
842 (const_int 24)))
843 (clobber (scratch:SI))])
844 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
845 (ashiftrt:SI (match_dup 2)
846 (const_int 24)))
847 (clobber (scratch:SI))])]
848 "TARGET_POWER"
849 "
850 { operands[0] = gen_lowpart (SImode, operands[0]);
851 operands[1] = gen_lowpart (SImode, operands[1]);
852 operands[2] = gen_reg_rtx (SImode); }")
854 (define_expand "extendqihi2_no_power"
855 [(set (match_dup 2)
856 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
857 (const_int 24)))
858 (set (match_operand:HI 0 "gpc_reg_operand" "")
859 (ashiftrt:SI (match_dup 2)
860 (const_int 24)))]
861 "! TARGET_POWER && ! TARGET_POWERPC"
862 "
863 { operands[0] = gen_lowpart (SImode, operands[0]);
864 operands[1] = gen_lowpart (SImode, operands[1]);
865 operands[2] = gen_reg_rtx (SImode); }")
867 (define_expand "zero_extendhisi2"
868 [(set (match_operand:SI 0 "gpc_reg_operand" "")
869 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
870 ""
871 "")
873 (define_insn ""
874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
875 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
876 ""
877 "@
878 lhz%U1%X1 %0,%1
879 {rlinm|rlwinm} %0,%1,0,0xffff"
880 [(set_attr "type" "load,*")])
882 (define_insn ""
883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
884 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
885 (const_int 0)))
886 (clobber (match_scratch:SI 2 "=r,r"))]
887 ""
888 "@
889 {andil.|andi.} %2,%1,0xffff
890 #"
891 [(set_attr "type" "fast_compare,compare")
892 (set_attr "length" "4,8")])
894 (define_split
895 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
896 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
897 (const_int 0)))
898 (clobber (match_scratch:SI 2 ""))]
899 "reload_completed"
900 [(set (match_dup 2)
901 (zero_extend:SI (match_dup 1)))
902 (set (match_dup 0)
903 (compare:CC (match_dup 2)
904 (const_int 0)))]
905 "")
907 (define_insn ""
908 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
909 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
910 (const_int 0)))
911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
912 (zero_extend:SI (match_dup 1)))]
913 ""
914 "@
915 {andil.|andi.} %0,%1,0xffff
916 #"
917 [(set_attr "type" "fast_compare,compare")
918 (set_attr "length" "4,8")])
920 (define_split
921 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
922 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
923 (const_int 0)))
924 (set (match_operand:SI 0 "gpc_reg_operand" "")
925 (zero_extend:SI (match_dup 1)))]
926 "reload_completed"
927 [(set (match_dup 0)
928 (zero_extend:SI (match_dup 1)))
929 (set (match_dup 2)
930 (compare:CC (match_dup 0)
931 (const_int 0)))]
932 "")
934 (define_expand "extendhisi2"
935 [(set (match_operand:SI 0 "gpc_reg_operand" "")
936 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
937 ""
938 "")
940 (define_insn ""
941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
942 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
943 "rs6000_gen_cell_microcode"
944 "@
945 lha%U1%X1 %0,%1
946 {exts|extsh} %0,%1"
947 [(set_attr "type" "load_ext,exts")])
949 (define_insn ""
950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
951 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
952 "!rs6000_gen_cell_microcode"
953 "{exts|extsh} %0,%1"
954 [(set_attr "type" "exts")])
956 (define_insn ""
957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
958 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
959 (const_int 0)))
960 (clobber (match_scratch:SI 2 "=r,r"))]
961 ""
962 "@
963 {exts.|extsh.} %2,%1
964 #"
965 [(set_attr "type" "compare")
966 (set_attr "length" "4,8")])
968 (define_split
969 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
970 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
971 (const_int 0)))
972 (clobber (match_scratch:SI 2 ""))]
973 "reload_completed"
974 [(set (match_dup 2)
975 (sign_extend:SI (match_dup 1)))
976 (set (match_dup 0)
977 (compare:CC (match_dup 2)
978 (const_int 0)))]
979 "")
981 (define_insn ""
982 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
983 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
984 (const_int 0)))
985 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
986 (sign_extend:SI (match_dup 1)))]
987 ""
988 "@
989 {exts.|extsh.} %0,%1
990 #"
991 [(set_attr "type" "compare")
992 (set_attr "length" "4,8")])
993 \f
994 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
996 (define_insn "*macchwc"
997 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
998 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1000 (const_int 16))
1001 (sign_extend:SI
1002 (match_operand:HI 1 "gpc_reg_operand" "r")))
1003 (match_operand:SI 4 "gpc_reg_operand" "0"))
1004 (const_int 0)))
1005 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1006 (plus:SI (mult:SI (ashiftrt:SI
1007 (match_dup 2)
1008 (const_int 16))
1009 (sign_extend:SI
1010 (match_dup 1)))
1011 (match_dup 4)))]
1012 "TARGET_MULHW"
1013 "macchw. %0, %1, %2"
1014 [(set_attr "type" "imul3")])
1016 (define_insn "*macchw"
1017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1018 (plus:SI (mult:SI (ashiftrt:SI
1019 (match_operand:SI 2 "gpc_reg_operand" "r")
1020 (const_int 16))
1021 (sign_extend:SI
1022 (match_operand:HI 1 "gpc_reg_operand" "r")))
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1024 "TARGET_MULHW"
1025 "macchw %0, %1, %2"
1026 [(set_attr "type" "imul3")])
1028 (define_insn "*macchwuc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1031 (match_operand:SI 2 "gpc_reg_operand" "r")
1032 (const_int 16))
1033 (zero_extend:SI
1034 (match_operand:HI 1 "gpc_reg_operand" "r")))
1035 (match_operand:SI 4 "gpc_reg_operand" "0"))
1036 (const_int 0)))
1037 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1038 (plus:SI (mult:SI (lshiftrt:SI
1039 (match_dup 2)
1040 (const_int 16))
1041 (zero_extend:SI
1042 (match_dup 1)))
1043 (match_dup 4)))]
1044 "TARGET_MULHW"
1045 "macchwu. %0, %1, %2"
1046 [(set_attr "type" "imul3")])
1048 (define_insn "*macchwu"
1049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1050 (plus:SI (mult:SI (lshiftrt:SI
1051 (match_operand:SI 2 "gpc_reg_operand" "r")
1052 (const_int 16))
1053 (zero_extend:SI
1054 (match_operand:HI 1 "gpc_reg_operand" "r")))
1055 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1056 "TARGET_MULHW"
1057 "macchwu %0, %1, %2"
1058 [(set_attr "type" "imul3")])
1060 (define_insn "*machhwc"
1061 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1062 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1063 (match_operand:SI 1 "gpc_reg_operand" "%r")
1064 (const_int 16))
1065 (ashiftrt:SI
1066 (match_operand:SI 2 "gpc_reg_operand" "r")
1067 (const_int 16)))
1068 (match_operand:SI 4 "gpc_reg_operand" "0"))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (ashiftrt:SI
1072 (match_dup 1)
1073 (const_int 16))
1074 (ashiftrt:SI
1075 (match_dup 2)
1076 (const_int 16)))
1077 (match_dup 4)))]
1078 "TARGET_MULHW"
1079 "machhw. %0, %1, %2"
1080 [(set_attr "type" "imul3")])
1082 (define_insn "*machhw"
1083 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1084 (plus:SI (mult:SI (ashiftrt:SI
1085 (match_operand:SI 1 "gpc_reg_operand" "%r")
1086 (const_int 16))
1087 (ashiftrt:SI
1088 (match_operand:SI 2 "gpc_reg_operand" "r")
1089 (const_int 16)))
1090 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1091 "TARGET_MULHW"
1092 "machhw %0, %1, %2"
1093 [(set_attr "type" "imul3")])
1095 (define_insn "*machhwuc"
1096 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1097 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1098 (match_operand:SI 1 "gpc_reg_operand" "%r")
1099 (const_int 16))
1100 (lshiftrt:SI
1101 (match_operand:SI 2 "gpc_reg_operand" "r")
1102 (const_int 16)))
1103 (match_operand:SI 4 "gpc_reg_operand" "0"))
1104 (const_int 0)))
1105 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (plus:SI (mult:SI (lshiftrt:SI
1107 (match_dup 1)
1108 (const_int 16))
1109 (lshiftrt:SI
1110 (match_dup 2)
1111 (const_int 16)))
1112 (match_dup 4)))]
1113 "TARGET_MULHW"
1114 "machhwu. %0, %1, %2"
1115 [(set_attr "type" "imul3")])
1117 (define_insn "*machhwu"
1118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1119 (plus:SI (mult:SI (lshiftrt:SI
1120 (match_operand:SI 1 "gpc_reg_operand" "%r")
1121 (const_int 16))
1122 (lshiftrt:SI
1123 (match_operand:SI 2 "gpc_reg_operand" "r")
1124 (const_int 16)))
1125 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1126 "TARGET_MULHW"
1127 "machhwu %0, %1, %2"
1128 [(set_attr "type" "imul3")])
1130 (define_insn "*maclhwc"
1131 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1132 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1133 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1134 (sign_extend:SI
1135 (match_operand:HI 2 "gpc_reg_operand" "r")))
1136 (match_operand:SI 4 "gpc_reg_operand" "0"))
1137 (const_int 0)))
1138 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1139 (plus:SI (mult:SI (sign_extend:SI
1140 (match_dup 1))
1141 (sign_extend:SI
1142 (match_dup 2)))
1143 (match_dup 4)))]
1144 "TARGET_MULHW"
1145 "maclhw. %0, %1, %2"
1146 [(set_attr "type" "imul3")])
1148 (define_insn "*maclhw"
1149 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1150 (plus:SI (mult:SI (sign_extend:SI
1151 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1152 (sign_extend:SI
1153 (match_operand:HI 2 "gpc_reg_operand" "r")))
1154 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1155 "TARGET_MULHW"
1156 "maclhw %0, %1, %2"
1157 [(set_attr "type" "imul3")])
1159 (define_insn "*maclhwuc"
1160 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1161 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (zero_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r")))
1165 (match_operand:SI 4 "gpc_reg_operand" "0"))
1166 (const_int 0)))
1167 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1168 (plus:SI (mult:SI (zero_extend:SI
1169 (match_dup 1))
1170 (zero_extend:SI
1171 (match_dup 2)))
1172 (match_dup 4)))]
1173 "TARGET_MULHW"
1174 "maclhwu. %0, %1, %2"
1175 [(set_attr "type" "imul3")])
1177 (define_insn "*maclhwu"
1178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1179 (plus:SI (mult:SI (zero_extend:SI
1180 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1181 (zero_extend:SI
1182 (match_operand:HI 2 "gpc_reg_operand" "r")))
1183 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1184 "TARGET_MULHW"
1185 "maclhwu %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1188 (define_insn "*nmacchwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 2 "gpc_reg_operand" "r")
1193 (const_int 16))
1194 (sign_extend:SI
1195 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1196 (const_int 0)))
1197 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1198 (minus:SI (match_dup 4)
1199 (mult:SI (ashiftrt:SI
1200 (match_dup 2)
1201 (const_int 16))
1202 (sign_extend:SI
1203 (match_dup 1)))))]
1204 "TARGET_MULHW"
1205 "nmacchw. %0, %1, %2"
1206 [(set_attr "type" "imul3")])
1208 (define_insn "*nmacchw"
1209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1210 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1211 (mult:SI (ashiftrt:SI
1212 (match_operand:SI 2 "gpc_reg_operand" "r")
1213 (const_int 16))
1214 (sign_extend:SI
1215 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1216 "TARGET_MULHW"
1217 "nmacchw %0, %1, %2"
1218 [(set_attr "type" "imul3")])
1220 (define_insn "*nmachhwc"
1221 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1222 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1223 (mult:SI (ashiftrt:SI
1224 (match_operand:SI 1 "gpc_reg_operand" "%r")
1225 (const_int 16))
1226 (ashiftrt:SI
1227 (match_operand:SI 2 "gpc_reg_operand" "r")
1228 (const_int 16))))
1229 (const_int 0)))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (minus:SI (match_dup 4)
1232 (mult:SI (ashiftrt:SI
1233 (match_dup 1)
1234 (const_int 16))
1235 (ashiftrt:SI
1236 (match_dup 2)
1237 (const_int 16)))))]
1238 "TARGET_MULHW"
1239 "nmachhw. %0, %1, %2"
1240 [(set_attr "type" "imul3")])
1242 (define_insn "*nmachhw"
1243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1244 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1245 (mult:SI (ashiftrt:SI
1246 (match_operand:SI 1 "gpc_reg_operand" "%r")
1247 (const_int 16))
1248 (ashiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1250 (const_int 16)))))]
1251 "TARGET_MULHW"
1252 "nmachhw %0, %1, %2"
1253 [(set_attr "type" "imul3")])
1255 (define_insn "*nmaclhwc"
1256 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1257 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1258 (mult:SI (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1260 (sign_extend:SI
1261 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1262 (const_int 0)))
1263 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1264 (minus:SI (match_dup 4)
1265 (mult:SI (sign_extend:SI
1266 (match_dup 1))
1267 (sign_extend:SI
1268 (match_dup 2)))))]
1269 "TARGET_MULHW"
1270 "nmaclhw. %0, %1, %2"
1271 [(set_attr "type" "imul3")])
1273 (define_insn "*nmaclhw"
1274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1276 (mult:SI (sign_extend:SI
1277 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1278 (sign_extend:SI
1279 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1280 "TARGET_MULHW"
1281 "nmaclhw %0, %1, %2"
1282 [(set_attr "type" "imul3")])
1284 (define_insn "*mulchwc"
1285 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1286 (compare:CC (mult:SI (ashiftrt:SI
1287 (match_operand:SI 2 "gpc_reg_operand" "r")
1288 (const_int 16))
1289 (sign_extend:SI
1290 (match_operand:HI 1 "gpc_reg_operand" "r")))
1291 (const_int 0)))
1292 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1293 (mult:SI (ashiftrt:SI
1294 (match_dup 2)
1295 (const_int 16))
1296 (sign_extend:SI
1297 (match_dup 1))))]
1298 "TARGET_MULHW"
1299 "mulchw. %0, %1, %2"
1300 [(set_attr "type" "imul3")])
1302 (define_insn "*mulchw"
1303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1304 (mult:SI (ashiftrt:SI
1305 (match_operand:SI 2 "gpc_reg_operand" "r")
1306 (const_int 16))
1307 (sign_extend:SI
1308 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1309 "TARGET_MULHW"
1310 "mulchw %0, %1, %2"
1311 [(set_attr "type" "imul3")])
1313 (define_insn "*mulchwuc"
1314 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1315 (compare:CC (mult:SI (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))
1318 (zero_extend:SI
1319 (match_operand:HI 1 "gpc_reg_operand" "r")))
1320 (const_int 0)))
1321 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1322 (mult:SI (lshiftrt:SI
1323 (match_dup 2)
1324 (const_int 16))
1325 (zero_extend:SI
1326 (match_dup 1))))]
1327 "TARGET_MULHW"
1328 "mulchwu. %0, %1, %2"
1329 [(set_attr "type" "imul3")])
1331 (define_insn "*mulchwu"
1332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1333 (mult:SI (lshiftrt:SI
1334 (match_operand:SI 2 "gpc_reg_operand" "r")
1335 (const_int 16))
1336 (zero_extend:SI
1337 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1338 "TARGET_MULHW"
1339 "mulchwu %0, %1, %2"
1340 [(set_attr "type" "imul3")])
1342 (define_insn "*mulhhwc"
1343 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1344 (compare:CC (mult:SI (ashiftrt:SI
1345 (match_operand:SI 1 "gpc_reg_operand" "%r")
1346 (const_int 16))
1347 (ashiftrt:SI
1348 (match_operand:SI 2 "gpc_reg_operand" "r")
1349 (const_int 16)))
1350 (const_int 0)))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (mult:SI (ashiftrt:SI
1353 (match_dup 1)
1354 (const_int 16))
1355 (ashiftrt:SI
1356 (match_dup 2)
1357 (const_int 16))))]
1358 "TARGET_MULHW"
1359 "mulhhw. %0, %1, %2"
1360 [(set_attr "type" "imul3")])
1362 (define_insn "*mulhhw"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (ashiftrt:SI
1365 (match_operand:SI 1 "gpc_reg_operand" "%r")
1366 (const_int 16))
1367 (ashiftrt:SI
1368 (match_operand:SI 2 "gpc_reg_operand" "r")
1369 (const_int 16))))]
1370 "TARGET_MULHW"
1371 "mulhhw %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1374 (define_insn "*mulhhwuc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (lshiftrt:SI
1377 (match_operand:SI 1 "gpc_reg_operand" "%r")
1378 (const_int 16))
1379 (lshiftrt:SI
1380 (match_operand:SI 2 "gpc_reg_operand" "r")
1381 (const_int 16)))
1382 (const_int 0)))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1384 (mult:SI (lshiftrt:SI
1385 (match_dup 1)
1386 (const_int 16))
1387 (lshiftrt:SI
1388 (match_dup 2)
1389 (const_int 16))))]
1390 "TARGET_MULHW"
1391 "mulhhwu. %0, %1, %2"
1392 [(set_attr "type" "imul3")])
1394 (define_insn "*mulhhwu"
1395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (lshiftrt:SI
1397 (match_operand:SI 1 "gpc_reg_operand" "%r")
1398 (const_int 16))
1399 (lshiftrt:SI
1400 (match_operand:SI 2 "gpc_reg_operand" "r")
1401 (const_int 16))))]
1402 "TARGET_MULHW"
1403 "mulhhwu %0, %1, %2"
1404 [(set_attr "type" "imul3")])
1406 (define_insn "*mullhwc"
1407 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1408 (compare:CC (mult:SI (sign_extend:SI
1409 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1410 (sign_extend:SI
1411 (match_operand:HI 2 "gpc_reg_operand" "r")))
1412 (const_int 0)))
1413 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1414 (mult:SI (sign_extend:SI
1415 (match_dup 1))
1416 (sign_extend:SI
1417 (match_dup 2))))]
1418 "TARGET_MULHW"
1419 "mullhw. %0, %1, %2"
1420 [(set_attr "type" "imul3")])
1422 (define_insn "*mullhw"
1423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1424 (mult:SI (sign_extend:SI
1425 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1426 (sign_extend:SI
1427 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1428 "TARGET_MULHW"
1429 "mullhw %0, %1, %2"
1430 [(set_attr "type" "imul3")])
1432 (define_insn "*mullhwuc"
1433 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1434 (compare:CC (mult:SI (zero_extend:SI
1435 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1436 (zero_extend:SI
1437 (match_operand:HI 2 "gpc_reg_operand" "r")))
1438 (const_int 0)))
1439 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1440 (mult:SI (zero_extend:SI
1441 (match_dup 1))
1442 (zero_extend:SI
1443 (match_dup 2))))]
1444 "TARGET_MULHW"
1445 "mullhwu. %0, %1, %2"
1446 [(set_attr "type" "imul3")])
1448 (define_insn "*mullhwu"
1449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1450 (mult:SI (zero_extend:SI
1451 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1452 (zero_extend:SI
1453 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1454 "TARGET_MULHW"
1455 "mullhwu %0, %1, %2"
1456 [(set_attr "type" "imul3")])
1457 \f
1458 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1459 (define_insn "dlmzb"
1460 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1461 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1462 (match_operand:SI 2 "gpc_reg_operand" "r")]
1463 UNSPEC_DLMZB_CR))
1464 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1465 (unspec:SI [(match_dup 1)
1466 (match_dup 2)]
1467 UNSPEC_DLMZB))]
1468 "TARGET_DLMZB"
1469 "dlmzb. %0, %1, %2")
1471 (define_expand "strlensi"
1472 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1473 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1474 (match_operand:QI 2 "const_int_operand" "")
1475 (match_operand 3 "const_int_operand" "")]
1476 UNSPEC_DLMZB_STRLEN))
1477 (clobber (match_scratch:CC 4 "=x"))]
1478 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1479 {
1480 rtx result = operands[0];
1481 rtx src = operands[1];
1482 rtx search_char = operands[2];
1483 rtx align = operands[3];
1484 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1485 rtx loop_label, end_label, mem, cr0, cond;
1486 if (search_char != const0_rtx
1487 || GET_CODE (align) != CONST_INT
1488 || INTVAL (align) < 8)
1489 FAIL;
1490 word1 = gen_reg_rtx (SImode);
1491 word2 = gen_reg_rtx (SImode);
1492 scratch_dlmzb = gen_reg_rtx (SImode);
1493 scratch_string = gen_reg_rtx (Pmode);
1494 loop_label = gen_label_rtx ();
1495 end_label = gen_label_rtx ();
1496 addr = force_reg (Pmode, XEXP (src, 0));
1497 emit_move_insn (scratch_string, addr);
1498 emit_label (loop_label);
1499 mem = change_address (src, SImode, scratch_string);
1500 emit_move_insn (word1, mem);
1501 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1502 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1503 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1504 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1505 emit_jump_insn (gen_rtx_SET (VOIDmode,
1506 pc_rtx,
1507 gen_rtx_IF_THEN_ELSE (VOIDmode,
1508 cond,
1509 gen_rtx_LABEL_REF
1510 (VOIDmode,
1511 end_label),
1512 pc_rtx)));
1513 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1514 emit_jump_insn (gen_rtx_SET (VOIDmode,
1515 pc_rtx,
1516 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1517 emit_barrier ();
1518 emit_label (end_label);
1519 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1520 emit_insn (gen_subsi3 (result, scratch_string, addr));
1521 emit_insn (gen_subsi3 (result, result, const1_rtx));
1522 DONE;
1523 })
1524 \f
1525 (define_split
1526 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1527 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1528 (const_int 0)))
1529 (set (match_operand:SI 0 "gpc_reg_operand" "")
1530 (sign_extend:SI (match_dup 1)))]
1531 "reload_completed"
1532 [(set (match_dup 0)
1533 (sign_extend:SI (match_dup 1)))
1534 (set (match_dup 2)
1535 (compare:CC (match_dup 0)
1536 (const_int 0)))]
1537 "")
1539 ;; Fixed-point arithmetic insns.
1541 (define_expand "add<mode>3"
1542 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1543 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1544 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1545 ""
1546 {
1547 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1548 {
1549 if (non_short_cint_operand (operands[2], DImode))
1550 FAIL;
1551 }
1552 else if (GET_CODE (operands[2]) == CONST_INT
1553 && ! add_operand (operands[2], <MODE>mode))
1554 {
1555 rtx tmp = ((!can_create_pseudo_p ()
1556 || rtx_equal_p (operands[0], operands[1]))
1557 ? operands[0] : gen_reg_rtx (<MODE>mode));
1559 HOST_WIDE_INT val = INTVAL (operands[2]);
1560 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1561 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1563 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1564 FAIL;
1566 /* The ordering here is important for the prolog expander.
1567 When space is allocated from the stack, adding 'low' first may
1568 produce a temporary deallocation (which would be bad). */
1569 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1570 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1571 DONE;
1572 }
1573 })
1575 ;; Discourage ai/addic because of carry but provide it in an alternative
1576 ;; allowing register zero as source.
1577 (define_insn "*add<mode>3_internal1"
1578 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1579 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1580 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1581 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1582 "@
1583 {cax|add} %0,%1,%2
1584 {cal %0,%2(%1)|addi %0,%1,%2}
1585 {ai|addic} %0,%1,%2
1586 {cau|addis} %0,%1,%v2"
1587 [(set_attr "length" "4,4,4,4")])
1589 (define_insn "addsi3_high"
1590 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1591 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1592 (high:SI (match_operand 2 "" ""))))]
1593 "TARGET_MACHO && !TARGET_64BIT"
1594 "{cau|addis} %0,%1,ha16(%2)"
1595 [(set_attr "length" "4")])
1597 (define_insn "*add<mode>3_internal2"
1598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1599 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1600 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1601 (const_int 0)))
1602 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1603 ""
1604 "@
1605 {cax.|add.} %3,%1,%2
1606 {ai.|addic.} %3,%1,%2
1607 #
1608 #"
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1612 (define_split
1613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1615 (match_operand:GPR 2 "reg_or_short_operand" ""))
1616 (const_int 0)))
1617 (clobber (match_scratch:GPR 3 ""))]
1618 "reload_completed"
1619 [(set (match_dup 3)
1620 (plus:GPR (match_dup 1)
1621 (match_dup 2)))
1622 (set (match_dup 0)
1623 (compare:CC (match_dup 3)
1624 (const_int 0)))]
1625 "")
1627 (define_insn "*add<mode>3_internal3"
1628 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1629 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1630 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1631 (const_int 0)))
1632 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1633 (plus:P (match_dup 1)
1634 (match_dup 2)))]
1635 ""
1636 "@
1637 {cax.|add.} %0,%1,%2
1638 {ai.|addic.} %0,%1,%2
1639 #
1640 #"
1641 [(set_attr "type" "fast_compare,compare,compare,compare")
1642 (set_attr "length" "4,4,8,8")])
1644 (define_split
1645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1646 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1647 (match_operand:P 2 "reg_or_short_operand" ""))
1648 (const_int 0)))
1649 (set (match_operand:P 0 "gpc_reg_operand" "")
1650 (plus:P (match_dup 1) (match_dup 2)))]
1651 "reload_completed"
1652 [(set (match_dup 0)
1653 (plus:P (match_dup 1)
1654 (match_dup 2)))
1655 (set (match_dup 3)
1656 (compare:CC (match_dup 0)
1657 (const_int 0)))]
1658 "")
1660 ;; Split an add that we can't do in one insn into two insns, each of which
1661 ;; does one 16-bit part. This is used by combine. Note that the low-order
1662 ;; add should be last in case the result gets used in an address.
1664 (define_split
1665 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1666 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1667 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1668 ""
1669 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1670 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1671 {
1672 HOST_WIDE_INT val = INTVAL (operands[2]);
1673 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1674 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1676 operands[4] = GEN_INT (low);
1677 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1678 operands[3] = GEN_INT (rest);
1679 else if (can_create_pseudo_p ())
1680 {
1681 operands[3] = gen_reg_rtx (DImode);
1682 emit_move_insn (operands[3], operands[2]);
1683 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1684 DONE;
1685 }
1686 else
1687 FAIL;
1688 })
1690 (define_insn "one_cmpl<mode>2"
1691 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1692 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1693 ""
1694 "nor %0,%1,%1")
1696 (define_insn ""
1697 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1698 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1699 (const_int 0)))
1700 (clobber (match_scratch:P 2 "=r,r"))]
1701 ""
1702 "@
1703 nor. %2,%1,%1
1704 #"
1705 [(set_attr "type" "fast_compare,compare")
1706 (set_attr "length" "4,8")])
1708 (define_split
1709 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1710 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1711 (const_int 0)))
1712 (clobber (match_scratch:P 2 ""))]
1713 "reload_completed"
1714 [(set (match_dup 2)
1715 (not:P (match_dup 1)))
1716 (set (match_dup 0)
1717 (compare:CC (match_dup 2)
1718 (const_int 0)))]
1719 "")
1721 (define_insn ""
1722 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1723 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1724 (const_int 0)))
1725 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1726 (not:P (match_dup 1)))]
1727 ""
1728 "@
1729 nor. %0,%1,%1
1730 #"
1731 [(set_attr "type" "fast_compare,compare")
1732 (set_attr "length" "4,8")])
1734 (define_split
1735 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1736 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1737 (const_int 0)))
1738 (set (match_operand:P 0 "gpc_reg_operand" "")
1739 (not:P (match_dup 1)))]
1740 "reload_completed"
1741 [(set (match_dup 0)
1742 (not:P (match_dup 1)))
1743 (set (match_dup 2)
1744 (compare:CC (match_dup 0)
1745 (const_int 0)))]
1746 "")
1748 (define_insn ""
1749 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1750 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1751 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1752 "! TARGET_POWERPC"
1753 "{sf%I1|subf%I1c} %0,%2,%1")
1755 (define_insn ""
1756 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1757 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1758 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1759 "TARGET_POWERPC"
1760 "@
1761 subf %0,%2,%1
1762 subfic %0,%2,%1")
1764 (define_insn ""
1765 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1766 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1767 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1768 (const_int 0)))
1769 (clobber (match_scratch:SI 3 "=r,r"))]
1770 "! TARGET_POWERPC"
1771 "@
1772 {sf.|subfc.} %3,%2,%1
1773 #"
1774 [(set_attr "type" "compare")
1775 (set_attr "length" "4,8")])
1777 (define_insn ""
1778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1779 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1780 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1781 (const_int 0)))
1782 (clobber (match_scratch:P 3 "=r,r"))]
1783 "TARGET_POWERPC"
1784 "@
1785 subf. %3,%2,%1
1786 #"
1787 [(set_attr "type" "fast_compare")
1788 (set_attr "length" "4,8")])
1790 (define_split
1791 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1792 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1793 (match_operand:P 2 "gpc_reg_operand" ""))
1794 (const_int 0)))
1795 (clobber (match_scratch:P 3 ""))]
1796 "reload_completed"
1797 [(set (match_dup 3)
1798 (minus:P (match_dup 1)
1799 (match_dup 2)))
1800 (set (match_dup 0)
1801 (compare:CC (match_dup 3)
1802 (const_int 0)))]
1803 "")
1805 (define_insn ""
1806 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1807 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1809 (const_int 0)))
1810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1811 (minus:SI (match_dup 1) (match_dup 2)))]
1812 "! TARGET_POWERPC"
1813 "@
1814 {sf.|subfc.} %0,%2,%1
1815 #"
1816 [(set_attr "type" "compare")
1817 (set_attr "length" "4,8")])
1819 (define_insn ""
1820 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1821 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1822 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1823 (const_int 0)))
1824 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1825 (minus:P (match_dup 1)
1826 (match_dup 2)))]
1827 "TARGET_POWERPC"
1828 "@
1829 subf. %0,%2,%1
1830 #"
1831 [(set_attr "type" "fast_compare")
1832 (set_attr "length" "4,8")])
1834 (define_split
1835 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1836 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1837 (match_operand:P 2 "gpc_reg_operand" ""))
1838 (const_int 0)))
1839 (set (match_operand:P 0 "gpc_reg_operand" "")
1840 (minus:P (match_dup 1)
1841 (match_dup 2)))]
1842 "reload_completed"
1843 [(set (match_dup 0)
1844 (minus:P (match_dup 1)
1845 (match_dup 2)))
1846 (set (match_dup 3)
1847 (compare:CC (match_dup 0)
1848 (const_int 0)))]
1849 "")
1851 (define_expand "sub<mode>3"
1852 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1853 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1854 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1855 ""
1856 "
1857 {
1858 if (GET_CODE (operands[2]) == CONST_INT)
1859 {
1860 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1861 negate_rtx (<MODE>mode, operands[2])));
1862 DONE;
1863 }
1864 }")
1866 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1867 ;; instruction and some auxiliary computations. Then we just have a single
1868 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1869 ;; combine.
1871 (define_expand "sminsi3"
1872 [(set (match_dup 3)
1873 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1874 (match_operand:SI 2 "reg_or_short_operand" ""))
1875 (const_int 0)
1876 (minus:SI (match_dup 2) (match_dup 1))))
1877 (set (match_operand:SI 0 "gpc_reg_operand" "")
1878 (minus:SI (match_dup 2) (match_dup 3)))]
1879 "TARGET_POWER || TARGET_ISEL"
1880 "
1881 {
1882 if (TARGET_ISEL)
1883 {
1884 operands[2] = force_reg (SImode, operands[2]);
1885 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1886 DONE;
1887 }
1889 operands[3] = gen_reg_rtx (SImode);
1890 }")
1892 (define_split
1893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1895 (match_operand:SI 2 "reg_or_short_operand" "")))
1896 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1897 "TARGET_POWER"
1898 [(set (match_dup 3)
1899 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1900 (const_int 0)
1901 (minus:SI (match_dup 2) (match_dup 1))))
1902 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1903 "")
1905 (define_expand "smaxsi3"
1906 [(set (match_dup 3)
1907 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1908 (match_operand:SI 2 "reg_or_short_operand" ""))
1909 (const_int 0)
1910 (minus:SI (match_dup 2) (match_dup 1))))
1911 (set (match_operand:SI 0 "gpc_reg_operand" "")
1912 (plus:SI (match_dup 3) (match_dup 1)))]
1913 "TARGET_POWER || TARGET_ISEL"
1914 "
1915 {
1916 if (TARGET_ISEL)
1917 {
1918 operands[2] = force_reg (SImode, operands[2]);
1919 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1920 DONE;
1921 }
1922 operands[3] = gen_reg_rtx (SImode);
1923 }")
1925 (define_split
1926 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1927 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1928 (match_operand:SI 2 "reg_or_short_operand" "")))
1929 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1930 "TARGET_POWER"
1931 [(set (match_dup 3)
1932 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1933 (const_int 0)
1934 (minus:SI (match_dup 2) (match_dup 1))))
1935 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1936 "")
1938 (define_expand "uminsi3"
1939 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1940 (match_dup 5)))
1941 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1942 (match_dup 5)))
1943 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1944 (const_int 0)
1945 (minus:SI (match_dup 4) (match_dup 3))))
1946 (set (match_operand:SI 0 "gpc_reg_operand" "")
1947 (minus:SI (match_dup 2) (match_dup 3)))]
1948 "TARGET_POWER || TARGET_ISEL"
1949 "
1950 {
1951 if (TARGET_ISEL)
1952 {
1953 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1954 DONE;
1955 }
1956 operands[3] = gen_reg_rtx (SImode);
1957 operands[4] = gen_reg_rtx (SImode);
1958 operands[5] = GEN_INT (-2147483647 - 1);
1959 }")
1961 (define_expand "umaxsi3"
1962 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1963 (match_dup 5)))
1964 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1965 (match_dup 5)))
1966 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1967 (const_int 0)
1968 (minus:SI (match_dup 4) (match_dup 3))))
1969 (set (match_operand:SI 0 "gpc_reg_operand" "")
1970 (plus:SI (match_dup 3) (match_dup 1)))]
1971 "TARGET_POWER || TARGET_ISEL"
1972 "
1973 {
1974 if (TARGET_ISEL)
1975 {
1976 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1977 DONE;
1978 }
1979 operands[3] = gen_reg_rtx (SImode);
1980 operands[4] = gen_reg_rtx (SImode);
1981 operands[5] = GEN_INT (-2147483647 - 1);
1982 }")
1984 (define_insn ""
1985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1986 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1987 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1988 (const_int 0)
1989 (minus:SI (match_dup 2) (match_dup 1))))]
1990 "TARGET_POWER"
1991 "doz%I2 %0,%1,%2")
1993 (define_insn ""
1994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1995 (compare:CC
1996 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1997 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1998 (const_int 0)
1999 (minus:SI (match_dup 2) (match_dup 1)))
2000 (const_int 0)))
2001 (clobber (match_scratch:SI 3 "=r,r"))]
2002 "TARGET_POWER"
2003 "@
2004 doz%I2. %3,%1,%2
2005 #"
2006 [(set_attr "type" "delayed_compare")
2007 (set_attr "length" "4,8")])
2009 (define_split
2010 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2011 (compare:CC
2012 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2013 (match_operand:SI 2 "reg_or_short_operand" ""))
2014 (const_int 0)
2015 (minus:SI (match_dup 2) (match_dup 1)))
2016 (const_int 0)))
2017 (clobber (match_scratch:SI 3 ""))]
2018 "TARGET_POWER && reload_completed"
2019 [(set (match_dup 3)
2020 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2021 (const_int 0)
2022 (minus:SI (match_dup 2) (match_dup 1))))
2023 (set (match_dup 0)
2024 (compare:CC (match_dup 3)
2025 (const_int 0)))]
2026 "")
2028 (define_insn ""
2029 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2030 (compare:CC
2031 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2032 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2033 (const_int 0)
2034 (minus:SI (match_dup 2) (match_dup 1)))
2035 (const_int 0)))
2036 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2037 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2038 (const_int 0)
2039 (minus:SI (match_dup 2) (match_dup 1))))]
2040 "TARGET_POWER"
2041 "@
2042 doz%I2. %0,%1,%2
2043 #"
2044 [(set_attr "type" "delayed_compare")
2045 (set_attr "length" "4,8")])
2047 (define_split
2048 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2049 (compare:CC
2050 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2051 (match_operand:SI 2 "reg_or_short_operand" ""))
2052 (const_int 0)
2053 (minus:SI (match_dup 2) (match_dup 1)))
2054 (const_int 0)))
2055 (set (match_operand:SI 0 "gpc_reg_operand" "")
2056 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2057 (const_int 0)
2058 (minus:SI (match_dup 2) (match_dup 1))))]
2059 "TARGET_POWER && reload_completed"
2060 [(set (match_dup 0)
2061 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2062 (const_int 0)
2063 (minus:SI (match_dup 2) (match_dup 1))))
2064 (set (match_dup 3)
2065 (compare:CC (match_dup 0)
2066 (const_int 0)))]
2067 "")
2069 ;; We don't need abs with condition code because such comparisons should
2070 ;; never be done.
2071 (define_expand "abssi2"
2072 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2073 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2074 ""
2075 "
2076 {
2077 if (TARGET_ISEL)
2078 {
2079 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2080 DONE;
2081 }
2082 else if (! TARGET_POWER)
2083 {
2084 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2085 DONE;
2086 }
2087 }")
2089 (define_insn "*abssi2_power"
2090 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2091 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2092 "TARGET_POWER"
2093 "abs %0,%1")
2095 (define_insn_and_split "abs<mode>2_isel"
2096 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2097 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2098 (clobber (match_scratch:GPR 2 "=&b"))
2099 (clobber (match_scratch:CC 3 "=y"))]
2100 "TARGET_ISEL"
2101 "#"
2102 "&& reload_completed"
2103 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2104 (set (match_dup 3)
2105 (compare:CC (match_dup 1)
2106 (const_int 0)))
2107 (set (match_dup 0)
2108 (if_then_else:GPR (ge (match_dup 3)
2109 (const_int 0))
2110 (match_dup 1)
2111 (match_dup 2)))]
2112 "")
2114 (define_insn_and_split "nabs<mode>2_isel"
2115 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2116 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2117 (clobber (match_scratch:GPR 2 "=&b"))
2118 (clobber (match_scratch:CC 3 "=y"))]
2119 "TARGET_ISEL"
2120 "#"
2121 "&& reload_completed"
2122 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2123 (set (match_dup 3)
2124 (compare:CC (match_dup 1)
2125 (const_int 0)))
2126 (set (match_dup 0)
2127 (if_then_else:GPR (ge (match_dup 3)
2128 (const_int 0))
2129 (match_dup 2)
2130 (match_dup 1)))]
2131 "")
2133 (define_insn_and_split "abssi2_nopower"
2134 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2135 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2136 (clobber (match_scratch:SI 2 "=&r,&r"))]
2137 "! TARGET_POWER && ! TARGET_ISEL"
2138 "#"
2139 "&& reload_completed"
2140 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2141 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2142 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2143 "")
2145 (define_insn "*nabs_power"
2146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2147 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2148 "TARGET_POWER"
2149 "nabs %0,%1")
2151 (define_insn_and_split "*nabs_nopower"
2152 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2153 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2154 (clobber (match_scratch:SI 2 "=&r,&r"))]
2155 "! TARGET_POWER"
2156 "#"
2157 "&& reload_completed"
2158 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2159 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2160 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2161 "")
2163 (define_expand "neg<mode>2"
2164 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2165 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2166 ""
2167 "")
2169 (define_insn "*neg<mode>2_internal"
2170 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2171 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2172 ""
2173 "neg %0,%1")
2175 (define_insn ""
2176 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2177 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2178 (const_int 0)))
2179 (clobber (match_scratch:P 2 "=r,r"))]
2180 ""
2181 "@
2182 neg. %2,%1
2183 #"
2184 [(set_attr "type" "fast_compare")
2185 (set_attr "length" "4,8")])
2187 (define_split
2188 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2189 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2190 (const_int 0)))
2191 (clobber (match_scratch:P 2 ""))]
2192 "reload_completed"
2193 [(set (match_dup 2)
2194 (neg:P (match_dup 1)))
2195 (set (match_dup 0)
2196 (compare:CC (match_dup 2)
2197 (const_int 0)))]
2198 "")
2200 (define_insn ""
2201 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2202 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2203 (const_int 0)))
2204 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2205 (neg:P (match_dup 1)))]
2206 ""
2207 "@
2208 neg. %0,%1
2209 #"
2210 [(set_attr "type" "fast_compare")
2211 (set_attr "length" "4,8")])
2213 (define_split
2214 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2215 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2216 (const_int 0)))
2217 (set (match_operand:P 0 "gpc_reg_operand" "")
2218 (neg:P (match_dup 1)))]
2219 "reload_completed"
2220 [(set (match_dup 0)
2221 (neg:P (match_dup 1)))
2222 (set (match_dup 2)
2223 (compare:CC (match_dup 0)
2224 (const_int 0)))]
2225 "")
2227 (define_insn "clz<mode>2"
2228 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2229 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2230 ""
2231 "{cntlz|cntlz<wd>} %0,%1"
2232 [(set_attr "type" "cntlz")])
2234 (define_expand "ctz<mode>2"
2235 [(set (match_dup 2)
2236 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2237 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2238 (match_dup 2)))
2239 (clobber (scratch:CC))])
2240 (set (match_dup 4) (clz:GPR (match_dup 3)))
2241 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2242 (minus:GPR (match_dup 5) (match_dup 4)))]
2243 ""
2244 {
2245 operands[2] = gen_reg_rtx (<MODE>mode);
2246 operands[3] = gen_reg_rtx (<MODE>mode);
2247 operands[4] = gen_reg_rtx (<MODE>mode);
2248 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2249 })
2251 (define_expand "ffs<mode>2"
2252 [(set (match_dup 2)
2253 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2254 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2255 (match_dup 2)))
2256 (clobber (scratch:CC))])
2257 (set (match_dup 4) (clz:GPR (match_dup 3)))
2258 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2259 (minus:GPR (match_dup 5) (match_dup 4)))]
2260 ""
2261 {
2262 operands[2] = gen_reg_rtx (<MODE>mode);
2263 operands[3] = gen_reg_rtx (<MODE>mode);
2264 operands[4] = gen_reg_rtx (<MODE>mode);
2265 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2266 })
2268 (define_insn "popcntb<mode>2"
2269 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2270 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2271 UNSPEC_POPCNTB))]
2272 "TARGET_POPCNTB"
2273 "popcntb %0,%1")
2275 (define_insn "popcntwsi2"
2276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2277 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2278 "TARGET_POPCNTD"
2279 "popcntw %0,%1")
2281 (define_insn "popcntddi2"
2282 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2283 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2284 "TARGET_POPCNTD && TARGET_POWERPC64"
2285 "popcntd %0,%1")
2287 (define_expand "popcount<mode>2"
2288 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2289 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2290 "TARGET_POPCNTB || TARGET_POPCNTD"
2291 {
2292 rs6000_emit_popcount (operands[0], operands[1]);
2293 DONE;
2294 })
2296 (define_expand "parity<mode>2"
2297 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2298 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2299 "TARGET_POPCNTB"
2300 {
2301 rs6000_emit_parity (operands[0], operands[1]);
2302 DONE;
2303 })
2305 ;; Since the hardware zeros the upper part of the register, save generating the
2306 ;; AND immediate if we are converting to unsigned
2307 (define_insn "*bswaphi2_extenddi"
2308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2309 (zero_extend:DI
2310 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2311 "TARGET_POWERPC64"
2312 "lhbrx %0,%y1"
2313 [(set_attr "length" "4")
2314 (set_attr "type" "load")])
2316 (define_insn "*bswaphi2_extendsi"
2317 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2318 (zero_extend:SI
2319 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2320 "TARGET_POWERPC"
2321 "lhbrx %0,%y1"
2322 [(set_attr "length" "4")
2323 (set_attr "type" "load")])
2325 (define_expand "bswaphi2"
2326 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2327 (bswap:HI
2328 (match_operand:HI 1 "reg_or_mem_operand" "")))
2329 (clobber (match_scratch:SI 2 ""))])]
2330 ""
2331 {
2332 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2333 operands[1] = force_reg (HImode, operands[1]);
2334 })
2336 (define_insn "bswaphi2_internal"
2337 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2338 (bswap:HI
2339 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2340 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2341 "TARGET_POWERPC"
2342 "@
2343 lhbrx %0,%y1
2344 sthbrx %1,%y0
2345 #"
2346 [(set_attr "length" "4,4,12")
2347 (set_attr "type" "load,store,*")])
2349 (define_split
2350 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2351 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2352 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2353 "TARGET_POWERPC && reload_completed"
2354 [(set (match_dup 3)
2355 (zero_extract:SI (match_dup 4)
2356 (const_int 8)
2357 (const_int 16)))
2358 (set (match_dup 2)
2359 (and:SI (ashift:SI (match_dup 4)
2360 (const_int 8))
2361 (const_int 65280))) ;; 0xff00
2362 (set (match_dup 3)
2363 (ior:SI (match_dup 3)
2364 (match_dup 2)))]
2365 "
2366 {
2367 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2368 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2369 }")
2371 (define_insn "*bswapsi2_extenddi"
2372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2373 (zero_extend:DI
2374 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2375 "TARGET_POWERPC64"
2376 "lwbrx %0,%y1"
2377 [(set_attr "length" "4")
2378 (set_attr "type" "load")])
2380 (define_expand "bswapsi2"
2381 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2382 (bswap:SI
2383 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2384 ""
2385 {
2386 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2387 operands[1] = force_reg (SImode, operands[1]);
2388 })
2390 (define_insn "*bswapsi2_internal"
2391 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2392 (bswap:SI
2393 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2394 ""
2395 "@
2396 {lbrx|lwbrx} %0,%y1
2397 {stbrx|stwbrx} %1,%y0
2398 #"
2399 [(set_attr "length" "4,4,12")
2400 (set_attr "type" "load,store,*")])
2402 (define_split
2403 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2404 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2405 "reload_completed"
2406 [(set (match_dup 0)
2407 (rotate:SI (match_dup 1) (const_int 8)))
2408 (set (zero_extract:SI (match_dup 0)
2409 (const_int 8)
2410 (const_int 0))
2411 (match_dup 1))
2412 (set (zero_extract:SI (match_dup 0)
2413 (const_int 8)
2414 (const_int 16))
2415 (rotate:SI (match_dup 1)
2416 (const_int 16)))]
2417 "")
2419 (define_expand "bswapdi2"
2420 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2421 (bswap:DI
2422 (match_operand:DI 1 "reg_or_mem_operand" "")))
2423 (clobber (match_scratch:DI 2 ""))
2424 (clobber (match_scratch:DI 3 ""))
2425 (clobber (match_scratch:DI 4 ""))])]
2426 ""
2427 {
2428 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2429 operands[1] = force_reg (DImode, operands[1]);
2431 if (!TARGET_POWERPC64)
2432 {
2433 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2434 that uses 64-bit registers needs the same scratch registers as 64-bit
2435 mode. */
2436 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2437 DONE;
2438 }
2439 })
2441 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2442 (define_insn "*bswapdi2_ldbrx"
2443 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2444 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2445 (clobber (match_scratch:DI 2 "=X,X,&r"))
2446 (clobber (match_scratch:DI 3 "=X,X,&r"))
2447 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2448 "TARGET_POWERPC64 && TARGET_LDBRX
2449 && (REG_P (operands[0]) || REG_P (operands[1]))"
2450 "@
2451 ldbrx %0,%y1
2452 stdbrx %1,%y0
2453 #"
2454 [(set_attr "length" "4,4,36")
2455 (set_attr "type" "load,store,*")])
2457 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2458 (define_insn "*bswapdi2_64bit"
2459 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2460 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2461 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2462 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2463 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2464 "TARGET_POWERPC64 && !TARGET_LDBRX
2465 && (REG_P (operands[0]) || REG_P (operands[1]))"
2466 "#"
2467 [(set_attr "length" "16,12,36")])
2469 (define_split
2470 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2471 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2472 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2473 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2474 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2475 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2476 [(const_int 0)]
2477 "
2478 {
2479 rtx dest = operands[0];
2480 rtx src = operands[1];
2481 rtx op2 = operands[2];
2482 rtx op3 = operands[3];
2483 rtx op4 = operands[4];
2484 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2485 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2486 rtx addr1;
2487 rtx addr2;
2488 rtx word_high;
2489 rtx word_low;
2491 addr1 = XEXP (src, 0);
2492 if (GET_CODE (addr1) == PLUS)
2493 {
2494 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2495 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2496 }
2497 else
2498 {
2499 emit_move_insn (op2, GEN_INT (4));
2500 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2501 }
2503 if (BYTES_BIG_ENDIAN)
2504 {
2505 word_high = change_address (src, SImode, addr1);
2506 word_low = change_address (src, SImode, addr2);
2507 }
2508 else
2509 {
2510 word_high = change_address (src, SImode, addr2);
2511 word_low = change_address (src, SImode, addr1);
2512 }
2514 emit_insn (gen_bswapsi2 (op3_32, word_low));
2515 emit_insn (gen_bswapsi2 (op4_32, word_high));
2516 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2517 emit_insn (gen_iordi3 (dest, dest, op4));
2518 }")
2520 (define_split
2521 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2522 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2523 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2524 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2525 (clobber (match_operand:DI 4 "" ""))]
2526 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2527 [(const_int 0)]
2528 "
2529 {
2530 rtx dest = operands[0];
2531 rtx src = operands[1];
2532 rtx op2 = operands[2];
2533 rtx op3 = operands[3];
2534 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2535 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2536 rtx addr1;
2537 rtx addr2;
2538 rtx word_high;
2539 rtx word_low;
2541 addr1 = XEXP (dest, 0);
2542 if (GET_CODE (addr1) == PLUS)
2543 {
2544 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2545 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2546 }
2547 else
2548 {
2549 emit_move_insn (op2, GEN_INT (4));
2550 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2551 }
2553 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2554 if (BYTES_BIG_ENDIAN)
2555 {
2556 word_high = change_address (dest, SImode, addr1);
2557 word_low = change_address (dest, SImode, addr2);
2558 emit_insn (gen_bswapsi2 (word_high, src_si));
2559 emit_insn (gen_bswapsi2 (word_low, op3_si));
2560 }
2561 else
2562 {
2563 word_high = change_address (dest, SImode, addr2);
2564 word_low = change_address (dest, SImode, addr1);
2565 emit_insn (gen_bswapsi2 (word_low, src_si));
2566 emit_insn (gen_bswapsi2 (word_high, op3_si));
2567 }
2568 }")
2570 (define_split
2571 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2572 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2573 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2574 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2575 (clobber (match_operand:DI 4 "" ""))]
2576 "TARGET_POWERPC64 && reload_completed"
2577 [(const_int 0)]
2578 "
2579 {
2580 rtx dest = operands[0];
2581 rtx src = operands[1];
2582 rtx op2 = operands[2];
2583 rtx op3 = operands[3];
2584 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2585 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2586 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2587 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2589 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2590 emit_insn (gen_bswapsi2 (dest_si, src_si));
2591 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2592 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2593 emit_insn (gen_iordi3 (dest, dest, op3));
2594 }")
2596 (define_insn "bswapdi2_32bit"
2597 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2598 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2599 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2600 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2601 "#"
2602 [(set_attr "length" "16,12,36")])
2604 (define_split
2605 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2606 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2607 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2608 "!TARGET_POWERPC64 && reload_completed"
2609 [(const_int 0)]
2610 "
2611 {
2612 rtx dest = operands[0];
2613 rtx src = operands[1];
2614 rtx op2 = operands[2];
2615 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2616 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2617 rtx addr1;
2618 rtx addr2;
2619 rtx word_high;
2620 rtx word_low;
2622 addr1 = XEXP (src, 0);
2623 if (GET_CODE (addr1) == PLUS)
2624 {
2625 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2626 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2627 }
2628 else
2629 {
2630 emit_move_insn (op2, GEN_INT (4));
2631 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2632 }
2634 if (BYTES_BIG_ENDIAN)
2635 {
2636 word_high = change_address (src, SImode, addr1);
2637 word_low = change_address (src, SImode, addr2);
2638 }
2639 else
2640 {
2641 word_high = change_address (src, SImode, addr2);
2642 word_low = change_address (src, SImode, addr1);
2643 }
2645 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2646 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2647 }")
2649 (define_split
2650 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2651 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2652 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2653 "!TARGET_POWERPC64 && reload_completed"
2654 [(const_int 0)]
2655 "
2656 {
2657 rtx dest = operands[0];
2658 rtx src = operands[1];
2659 rtx op2 = operands[2];
2660 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2661 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2662 rtx addr1;
2663 rtx addr2;
2664 rtx word_high;
2665 rtx word_low;
2667 addr1 = XEXP (dest, 0);
2668 if (GET_CODE (addr1) == PLUS)
2669 {
2670 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2671 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2672 }
2673 else
2674 {
2675 emit_move_insn (op2, GEN_INT (4));
2676 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2677 }
2679 if (BYTES_BIG_ENDIAN)
2680 {
2681 word_high = change_address (dest, SImode, addr1);
2682 word_low = change_address (dest, SImode, addr2);
2683 }
2684 else
2685 {
2686 word_high = change_address (dest, SImode, addr2);
2687 word_low = change_address (dest, SImode, addr1);
2688 }
2690 emit_insn (gen_bswapsi2 (word_high, src_low));
2691 emit_insn (gen_bswapsi2 (word_low, src_high));
2692 }")
2694 (define_split
2695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2696 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2697 (clobber (match_operand:SI 2 "" ""))]
2698 "!TARGET_POWERPC64 && reload_completed"
2699 [(const_int 0)]
2700 "
2701 {
2702 rtx dest = operands[0];
2703 rtx src = operands[1];
2704 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2705 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2706 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2707 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2709 emit_insn (gen_bswapsi2 (dest_high, src_low));
2710 emit_insn (gen_bswapsi2 (dest_low, src_high));
2711 }")
2713 (define_expand "mulsi3"
2714 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2715 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2716 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2717 ""
2718 "
2719 {
2720 if (TARGET_POWER)
2721 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2722 else
2723 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2724 DONE;
2725 }")
2727 (define_insn "mulsi3_mq"
2728 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2729 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2730 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2731 (clobber (match_scratch:SI 3 "=q,q"))]
2732 "TARGET_POWER"
2733 "@
2734 {muls|mullw} %0,%1,%2
2735 {muli|mulli} %0,%1,%2"
2736 [(set (attr "type")
2737 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2738 (const_string "imul3")
2739 (match_operand:SI 2 "short_cint_operand" "")
2740 (const_string "imul2")]
2741 (const_string "imul")))])
2743 (define_insn "mulsi3_no_mq"
2744 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2745 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2746 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2747 "! TARGET_POWER"
2748 "@
2749 {muls|mullw} %0,%1,%2
2750 {muli|mulli} %0,%1,%2"
2751 [(set (attr "type")
2752 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2753 (const_string "imul3")
2754 (match_operand:SI 2 "short_cint_operand" "")
2755 (const_string "imul2")]
2756 (const_string "imul")))])
2758 (define_insn "*mulsi3_mq_internal1"
2759 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2760 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2761 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2762 (const_int 0)))
2763 (clobber (match_scratch:SI 3 "=r,r"))
2764 (clobber (match_scratch:SI 4 "=q,q"))]
2765 "TARGET_POWER"
2766 "@
2767 {muls.|mullw.} %3,%1,%2
2768 #"
2769 [(set_attr "type" "imul_compare")
2770 (set_attr "length" "4,8")])
2772 (define_split
2773 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2774 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2775 (match_operand:SI 2 "gpc_reg_operand" ""))
2776 (const_int 0)))
2777 (clobber (match_scratch:SI 3 ""))
2778 (clobber (match_scratch:SI 4 ""))]
2779 "TARGET_POWER && reload_completed"
2780 [(parallel [(set (match_dup 3)
2781 (mult:SI (match_dup 1) (match_dup 2)))
2782 (clobber (match_dup 4))])
2783 (set (match_dup 0)
2784 (compare:CC (match_dup 3)
2785 (const_int 0)))]
2786 "")
2788 (define_insn "*mulsi3_no_mq_internal1"
2789 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2792 (const_int 0)))
2793 (clobber (match_scratch:SI 3 "=r,r"))]
2794 "! TARGET_POWER"
2795 "@
2796 {muls.|mullw.} %3,%1,%2
2797 #"
2798 [(set_attr "type" "imul_compare")
2799 (set_attr "length" "4,8")])
2801 (define_split
2802 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2803 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2804 (match_operand:SI 2 "gpc_reg_operand" ""))
2805 (const_int 0)))
2806 (clobber (match_scratch:SI 3 ""))]
2807 "! TARGET_POWER && reload_completed"
2808 [(set (match_dup 3)
2809 (mult:SI (match_dup 1) (match_dup 2)))
2810 (set (match_dup 0)
2811 (compare:CC (match_dup 3)
2812 (const_int 0)))]
2813 "")
2815 (define_insn "*mulsi3_mq_internal2"
2816 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2817 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2818 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2819 (const_int 0)))
2820 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2821 (mult:SI (match_dup 1) (match_dup 2)))
2822 (clobber (match_scratch:SI 4 "=q,q"))]
2823 "TARGET_POWER"
2824 "@
2825 {muls.|mullw.} %0,%1,%2
2826 #"
2827 [(set_attr "type" "imul_compare")
2828 (set_attr "length" "4,8")])
2830 (define_split
2831 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2832 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2833 (match_operand:SI 2 "gpc_reg_operand" ""))
2834 (const_int 0)))
2835 (set (match_operand:SI 0 "gpc_reg_operand" "")
2836 (mult:SI (match_dup 1) (match_dup 2)))
2837 (clobber (match_scratch:SI 4 ""))]
2838 "TARGET_POWER && reload_completed"
2839 [(parallel [(set (match_dup 0)
2840 (mult:SI (match_dup 1) (match_dup 2)))
2841 (clobber (match_dup 4))])
2842 (set (match_dup 3)
2843 (compare:CC (match_dup 0)
2844 (const_int 0)))]
2845 "")
2847 (define_insn "*mulsi3_no_mq_internal2"
2848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2849 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2850 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2851 (const_int 0)))
2852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2853 (mult:SI (match_dup 1) (match_dup 2)))]
2854 "! TARGET_POWER"
2855 "@
2856 {muls.|mullw.} %0,%1,%2
2857 #"
2858 [(set_attr "type" "imul_compare")
2859 (set_attr "length" "4,8")])
2861 (define_split
2862 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2863 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2864 (match_operand:SI 2 "gpc_reg_operand" ""))
2865 (const_int 0)))
2866 (set (match_operand:SI 0 "gpc_reg_operand" "")
2867 (mult:SI (match_dup 1) (match_dup 2)))]
2868 "! TARGET_POWER && reload_completed"
2869 [(set (match_dup 0)
2870 (mult:SI (match_dup 1) (match_dup 2)))
2871 (set (match_dup 3)
2872 (compare:CC (match_dup 0)
2873 (const_int 0)))]
2874 "")
2876 ;; Operand 1 is divided by operand 2; quotient goes to operand
2877 ;; 0 and remainder to operand 3.
2878 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2880 (define_expand "divmodsi4"
2881 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2882 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2883 (match_operand:SI 2 "gpc_reg_operand" "")))
2884 (set (match_operand:SI 3 "register_operand" "")
2885 (mod:SI (match_dup 1) (match_dup 2)))])]
2886 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2887 "
2888 {
2889 if (! TARGET_POWER && ! TARGET_POWERPC)
2890 {
2891 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2892 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2893 emit_insn (gen_divss_call ());
2894 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2895 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2896 DONE;
2897 }
2898 }")
2900 (define_insn "*divmodsi4_internal"
2901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2902 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2903 (match_operand:SI 2 "gpc_reg_operand" "r")))
2904 (set (match_operand:SI 3 "register_operand" "=q")
2905 (mod:SI (match_dup 1) (match_dup 2)))]
2906 "TARGET_POWER"
2907 "divs %0,%1,%2"
2908 [(set_attr "type" "idiv")])
2910 (define_expand "udiv<mode>3"
2911 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2912 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2913 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2914 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2915 "
2916 {
2917 if (! TARGET_POWER && ! TARGET_POWERPC)
2918 {
2919 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2920 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2921 emit_insn (gen_quous_call ());
2922 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2923 DONE;
2924 }
2925 else if (TARGET_POWER)
2926 {
2927 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2928 DONE;
2929 }
2930 }")
2932 (define_insn "udivsi3_mq"
2933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2934 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2935 (match_operand:SI 2 "gpc_reg_operand" "r")))
2936 (clobber (match_scratch:SI 3 "=q"))]
2937 "TARGET_POWERPC && TARGET_POWER"
2938 "divwu %0,%1,%2"
2939 [(set_attr "type" "idiv")])
2941 (define_insn "*udivsi3_no_mq"
2942 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2943 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2944 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2945 "TARGET_POWERPC && ! TARGET_POWER"
2946 "div<wd>u %0,%1,%2"
2947 [(set (attr "type")
2948 (cond [(match_operand:SI 0 "" "")
2949 (const_string "idiv")]
2950 (const_string "ldiv")))])
2953 ;; For powers of two we can do srai/aze for divide and then adjust for
2954 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2955 ;; used; for PowerPC, force operands into register and do a normal divide;
2956 ;; for AIX common-mode, use quoss call on register operands.
2957 (define_expand "div<mode>3"
2958 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2959 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2960 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2961 ""
2962 "
2963 {
2964 if (GET_CODE (operands[2]) == CONST_INT
2965 && INTVAL (operands[2]) > 0
2966 && exact_log2 (INTVAL (operands[2])) >= 0)
2967 ;
2968 else if (TARGET_POWERPC)
2969 {
2970 operands[2] = force_reg (<MODE>mode, operands[2]);
2971 if (TARGET_POWER)
2972 {
2973 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2974 DONE;
2975 }
2976 }
2977 else if (TARGET_POWER)
2978 FAIL;
2979 else
2980 {
2981 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2982 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2983 emit_insn (gen_quoss_call ());
2984 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2985 DONE;
2986 }
2987 }")
2989 (define_insn "divsi3_mq"
2990 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2991 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2992 (match_operand:SI 2 "gpc_reg_operand" "r")))
2993 (clobber (match_scratch:SI 3 "=q"))]
2994 "TARGET_POWERPC && TARGET_POWER"
2995 "divw %0,%1,%2"
2996 [(set_attr "type" "idiv")])
2998 (define_insn "*div<mode>3_no_mq"
2999 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3000 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3001 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3002 "TARGET_POWERPC && ! TARGET_POWER"
3003 "div<wd> %0,%1,%2"
3004 [(set (attr "type")
3005 (cond [(match_operand:SI 0 "" "")
3006 (const_string "idiv")]
3007 (const_string "ldiv")))])
3009 (define_expand "mod<mode>3"
3010 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3011 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3012 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3013 ""
3014 "
3015 {
3016 int i;
3017 rtx temp1;
3018 rtx temp2;
3020 if (GET_CODE (operands[2]) != CONST_INT
3021 || INTVAL (operands[2]) <= 0
3022 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3023 FAIL;
3025 temp1 = gen_reg_rtx (<MODE>mode);
3026 temp2 = gen_reg_rtx (<MODE>mode);
3028 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3029 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3030 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3031 DONE;
3032 }")
3034 (define_insn ""
3035 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3036 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3037 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3038 ""
3039 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3040 [(set_attr "type" "two")
3041 (set_attr "length" "8")])
3043 (define_insn ""
3044 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3045 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3046 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3047 (const_int 0)))
3048 (clobber (match_scratch:P 3 "=r,r"))]
3049 ""
3050 "@
3051 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3052 #"
3053 [(set_attr "type" "compare")
3054 (set_attr "length" "8,12")
3055 (set_attr "cell_micro" "not")])
3057 (define_split
3058 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3059 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3060 (match_operand:GPR 2 "exact_log2_cint_operand"
3061 ""))
3062 (const_int 0)))
3063 (clobber (match_scratch:GPR 3 ""))]
3064 "reload_completed"
3065 [(set (match_dup 3)
3066 (div:<MODE> (match_dup 1) (match_dup 2)))
3067 (set (match_dup 0)
3068 (compare:CC (match_dup 3)
3069 (const_int 0)))]
3070 "")
3072 (define_insn ""
3073 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3074 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3075 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3076 (const_int 0)))
3077 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3078 (div:P (match_dup 1) (match_dup 2)))]
3079 ""
3080 "@
3081 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3082 #"
3083 [(set_attr "type" "compare")
3084 (set_attr "length" "8,12")
3085 (set_attr "cell_micro" "not")])
3087 (define_split
3088 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3089 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3090 (match_operand:GPR 2 "exact_log2_cint_operand"
3091 ""))
3092 (const_int 0)))
3093 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3094 (div:GPR (match_dup 1) (match_dup 2)))]
3095 "reload_completed"
3096 [(set (match_dup 0)
3097 (div:<MODE> (match_dup 1) (match_dup 2)))
3098 (set (match_dup 3)
3099 (compare:CC (match_dup 0)
3100 (const_int 0)))]
3101 "")
3103 (define_insn ""
3104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3105 (udiv:SI
3106 (plus:DI (ashift:DI
3107 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3108 (const_int 32))
3109 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3110 (match_operand:SI 3 "gpc_reg_operand" "r")))
3111 (set (match_operand:SI 2 "register_operand" "=*q")
3112 (umod:SI
3113 (plus:DI (ashift:DI
3114 (zero_extend:DI (match_dup 1)) (const_int 32))
3115 (zero_extend:DI (match_dup 4)))
3116 (match_dup 3)))]
3117 "TARGET_POWER"
3118 "div %0,%1,%3"
3119 [(set_attr "type" "idiv")])
3121 ;; To do unsigned divide we handle the cases of the divisor looking like a
3122 ;; negative number. If it is a constant that is less than 2**31, we don't
3123 ;; have to worry about the branches. So make a few subroutines here.
3124 ;;
3125 ;; First comes the normal case.
3126 (define_expand "udivmodsi4_normal"
3127 [(set (match_dup 4) (const_int 0))
3128 (parallel [(set (match_operand:SI 0 "" "")
3129 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3130 (const_int 32))
3131 (zero_extend:DI (match_operand:SI 1 "" "")))
3132 (match_operand:SI 2 "" "")))
3133 (set (match_operand:SI 3 "" "")
3134 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3135 (const_int 32))
3136 (zero_extend:DI (match_dup 1)))
3137 (match_dup 2)))])]
3138 "TARGET_POWER"
3139 "
3140 { operands[4] = gen_reg_rtx (SImode); }")
3142 ;; This handles the branches.
3143 (define_expand "udivmodsi4_tests"
3144 [(set (match_operand:SI 0 "" "") (const_int 0))
3145 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3146 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3147 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3148 (label_ref (match_operand:SI 4 "" "")) (pc)))
3149 (set (match_dup 0) (const_int 1))
3150 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3151 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3152 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3153 (label_ref (match_dup 4)) (pc)))]
3154 "TARGET_POWER"
3155 "
3156 { operands[5] = gen_reg_rtx (CCUNSmode);
3157 operands[6] = gen_reg_rtx (CCmode);
3158 }")
3160 (define_expand "udivmodsi4"
3161 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3162 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3163 (match_operand:SI 2 "reg_or_cint_operand" "")))
3164 (set (match_operand:SI 3 "gpc_reg_operand" "")
3165 (umod:SI (match_dup 1) (match_dup 2)))])]
3166 ""
3167 "
3168 {
3169 rtx label = 0;
3171 if (! TARGET_POWER)
3172 {
3173 if (! TARGET_POWERPC)
3174 {
3175 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3176 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3177 emit_insn (gen_divus_call ());
3178 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3179 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3180 DONE;
3181 }
3182 else
3183 FAIL;
3184 }
3186 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3187 {
3188 operands[2] = force_reg (SImode, operands[2]);
3189 label = gen_label_rtx ();
3190 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3191 operands[3], label));
3192 }
3193 else
3194 operands[2] = force_reg (SImode, operands[2]);
3196 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3197 operands[3]));
3198 if (label)
3199 emit_label (label);
3201 DONE;
3202 }")
3204 ;; AIX architecture-independent common-mode multiply (DImode),
3205 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3206 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3207 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3208 ;; assumed unused if generating common-mode, so ignore.
3209 (define_insn "mulh_call"
3210 [(set (reg:SI 3)
3211 (truncate:SI
3212 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3213 (sign_extend:DI (reg:SI 4)))
3214 (const_int 32))))
3215 (clobber (reg:SI LR_REGNO))]
3216 "! TARGET_POWER && ! TARGET_POWERPC"
3217 "bla __mulh"
3218 [(set_attr "type" "imul")])
3220 (define_insn "mull_call"
3221 [(set (reg:DI 3)
3222 (mult:DI (sign_extend:DI (reg:SI 3))
3223 (sign_extend:DI (reg:SI 4))))
3224 (clobber (reg:SI LR_REGNO))
3225 (clobber (reg:SI 0))]
3226 "! TARGET_POWER && ! TARGET_POWERPC"
3227 "bla __mull"
3228 [(set_attr "type" "imul")])
3230 (define_insn "divss_call"
3231 [(set (reg:SI 3)
3232 (div:SI (reg:SI 3) (reg:SI 4)))
3233 (set (reg:SI 4)
3234 (mod:SI (reg:SI 3) (reg:SI 4)))
3235 (clobber (reg:SI LR_REGNO))
3236 (clobber (reg:SI 0))]
3237 "! TARGET_POWER && ! TARGET_POWERPC"
3238 "bla __divss"
3239 [(set_attr "type" "idiv")])
3241 (define_insn "divus_call"
3242 [(set (reg:SI 3)
3243 (udiv:SI (reg:SI 3) (reg:SI 4)))
3244 (set (reg:SI 4)
3245 (umod:SI (reg:SI 3) (reg:SI 4)))
3246 (clobber (reg:SI LR_REGNO))
3247 (clobber (reg:SI 0))
3248 (clobber (match_scratch:CC 0 "=x"))
3249 (clobber (reg:CC CR1_REGNO))]
3250 "! TARGET_POWER && ! TARGET_POWERPC"
3251 "bla __divus"
3252 [(set_attr "type" "idiv")])
3254 (define_insn "quoss_call"
3255 [(set (reg:SI 3)
3256 (div:SI (reg:SI 3) (reg:SI 4)))
3257 (clobber (reg:SI LR_REGNO))]
3258 "! TARGET_POWER && ! TARGET_POWERPC"
3259 "bla __quoss"
3260 [(set_attr "type" "idiv")])
3262 (define_insn "quous_call"
3263 [(set (reg:SI 3)
3264 (udiv:SI (reg:SI 3) (reg:SI 4)))
3265 (clobber (reg:SI LR_REGNO))
3266 (clobber (reg:SI 0))
3267 (clobber (match_scratch:CC 0 "=x"))
3268 (clobber (reg:CC CR1_REGNO))]
3269 "! TARGET_POWER && ! TARGET_POWERPC"
3270 "bla __quous"
3271 [(set_attr "type" "idiv")])
3272 \f
3273 ;; Logical instructions
3274 ;; The logical instructions are mostly combined by using match_operator,
3275 ;; but the plain AND insns are somewhat different because there is no
3276 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3277 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3279 (define_expand "andsi3"
3280 [(parallel
3281 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3282 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3283 (match_operand:SI 2 "and_operand" "")))
3284 (clobber (match_scratch:CC 3 ""))])]
3285 ""
3286 "")
3288 (define_insn "andsi3_mc"
3289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3290 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3291 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3292 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3293 "rs6000_gen_cell_microcode"
3294 "@
3295 and %0,%1,%2
3296 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3297 {andil.|andi.} %0,%1,%b2
3298 {andiu.|andis.} %0,%1,%u2"
3299 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3301 (define_insn "andsi3_nomc"
3302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3303 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3304 (match_operand:SI 2 "and_operand" "?r,T")))
3305 (clobber (match_scratch:CC 3 "=X,X"))]
3306 "!rs6000_gen_cell_microcode"
3307 "@
3308 and %0,%1,%2
3309 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3311 (define_insn "andsi3_internal0_nomc"
3312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3313 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3314 (match_operand:SI 2 "and_operand" "?r,T")))]
3315 "!rs6000_gen_cell_microcode"
3316 "@
3317 and %0,%1,%2
3318 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3321 ;; Note to set cr's other than cr0 we do the and immediate and then
3322 ;; the test again -- this avoids a mfcr which on the higher end
3323 ;; machines causes an execution serialization
3325 (define_insn "*andsi3_internal2_mc"
3326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3327 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3328 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3329 (const_int 0)))
3330 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3331 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3332 "TARGET_32BIT && rs6000_gen_cell_microcode"
3333 "@
3334 and. %3,%1,%2
3335 {andil.|andi.} %3,%1,%b2
3336 {andiu.|andis.} %3,%1,%u2
3337 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3338 #
3339 #
3340 #
3341 #"
3342 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3343 compare,compare,compare,compare")
3344 (set_attr "length" "4,4,4,4,8,8,8,8")])
3346 (define_insn "*andsi3_internal3_mc"
3347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3348 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3349 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3350 (const_int 0)))
3351 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3352 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3353 "TARGET_64BIT && rs6000_gen_cell_microcode"
3354 "@
3355 #
3356 {andil.|andi.} %3,%1,%b2
3357 {andiu.|andis.} %3,%1,%u2
3358 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3359 #
3360 #
3361 #
3362 #"
3363 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3364 compare,compare,compare")
3365 (set_attr "length" "8,4,4,4,8,8,8,8")])
3367 (define_split
3368 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3369 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3370 (match_operand:GPR 2 "and_operand" ""))
3371 (const_int 0)))
3372 (clobber (match_scratch:GPR 3 ""))
3373 (clobber (match_scratch:CC 4 ""))]
3374 "reload_completed"
3375 [(parallel [(set (match_dup 3)
3376 (and:<MODE> (match_dup 1)
3377 (match_dup 2)))
3378 (clobber (match_dup 4))])
3379 (set (match_dup 0)
3380 (compare:CC (match_dup 3)
3381 (const_int 0)))]
3382 "")
3384 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3385 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3387 (define_split
3388 [(set (match_operand:CC 0 "cc_reg_operand" "")
3389 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3390 (match_operand:SI 2 "gpc_reg_operand" ""))
3391 (const_int 0)))
3392 (clobber (match_scratch:SI 3 ""))
3393 (clobber (match_scratch:CC 4 ""))]
3394 "TARGET_POWERPC64 && reload_completed"
3395 [(parallel [(set (match_dup 3)
3396 (and:SI (match_dup 1)
3397 (match_dup 2)))
3398 (clobber (match_dup 4))])
3399 (set (match_dup 0)
3400 (compare:CC (match_dup 3)
3401 (const_int 0)))]
3402 "")
3404 (define_insn "*andsi3_internal4"
3405 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3406 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3407 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3408 (const_int 0)))
3409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3410 (and:SI (match_dup 1)
3411 (match_dup 2)))
3412 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3413 "TARGET_32BIT && rs6000_gen_cell_microcode"
3414 "@
3415 and. %0,%1,%2
3416 {andil.|andi.} %0,%1,%b2
3417 {andiu.|andis.} %0,%1,%u2
3418 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3419 #
3420 #
3421 #
3422 #"
3423 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3424 compare,compare,compare,compare")
3425 (set_attr "length" "4,4,4,4,8,8,8,8")])
3427 (define_insn "*andsi3_internal5_mc"
3428 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3429 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3430 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3431 (const_int 0)))
3432 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3433 (and:SI (match_dup 1)
3434 (match_dup 2)))
3435 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3436 "TARGET_64BIT && rs6000_gen_cell_microcode"
3437 "@
3438 #
3439 {andil.|andi.} %0,%1,%b2
3440 {andiu.|andis.} %0,%1,%u2
3441 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3442 #
3443 #
3444 #
3445 #"
3446 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3447 compare,compare,compare")
3448 (set_attr "length" "8,4,4,4,8,8,8,8")])
3450 (define_split
3451 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3452 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3453 (match_operand:SI 2 "and_operand" ""))
3454 (const_int 0)))
3455 (set (match_operand:SI 0 "gpc_reg_operand" "")
3456 (and:SI (match_dup 1)
3457 (match_dup 2)))
3458 (clobber (match_scratch:CC 4 ""))]
3459 "reload_completed"
3460 [(parallel [(set (match_dup 0)
3461 (and:SI (match_dup 1)
3462 (match_dup 2)))
3463 (clobber (match_dup 4))])
3464 (set (match_dup 3)
3465 (compare:CC (match_dup 0)
3466 (const_int 0)))]
3467 "")
3469 (define_split
3470 [(set (match_operand:CC 3 "cc_reg_operand" "")
3471 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3472 (match_operand:SI 2 "gpc_reg_operand" ""))
3473 (const_int 0)))
3474 (set (match_operand:SI 0 "gpc_reg_operand" "")
3475 (and:SI (match_dup 1)
3476 (match_dup 2)))
3477 (clobber (match_scratch:CC 4 ""))]
3478 "TARGET_POWERPC64 && reload_completed"
3479 [(parallel [(set (match_dup 0)
3480 (and:SI (match_dup 1)
3481 (match_dup 2)))
3482 (clobber (match_dup 4))])
3483 (set (match_dup 3)
3484 (compare:CC (match_dup 0)
3485 (const_int 0)))]
3486 "")
3488 ;; Handle the PowerPC64 rlwinm corner case
3490 (define_insn_and_split "*andsi3_internal6"
3491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3492 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3493 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3494 "TARGET_POWERPC64"
3495 "#"
3496 "TARGET_POWERPC64"
3497 [(set (match_dup 0)
3498 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3499 (match_dup 4)))
3500 (set (match_dup 0)
3501 (rotate:SI (match_dup 0) (match_dup 5)))]
3502 "
3503 {
3504 int mb = extract_MB (operands[2]);
3505 int me = extract_ME (operands[2]);
3506 operands[3] = GEN_INT (me + 1);
3507 operands[5] = GEN_INT (32 - (me + 1));
3508 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3509 }"
3510 [(set_attr "length" "8")])
3512 (define_expand "iorsi3"
3513 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3514 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3515 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3516 ""
3517 "
3518 {
3519 if (GET_CODE (operands[2]) == CONST_INT
3520 && ! logical_operand (operands[2], SImode))
3521 {
3522 HOST_WIDE_INT value = INTVAL (operands[2]);
3523 rtx tmp = ((!can_create_pseudo_p ()
3524 || rtx_equal_p (operands[0], operands[1]))
3525 ? operands[0] : gen_reg_rtx (SImode));
3527 emit_insn (gen_iorsi3 (tmp, operands[1],
3528 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3529 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3530 DONE;
3531 }
3532 }")
3534 (define_expand "xorsi3"
3535 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3536 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3537 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3538 ""
3539 "
3540 {
3541 if (GET_CODE (operands[2]) == CONST_INT
3542 && ! logical_operand (operands[2], SImode))
3543 {
3544 HOST_WIDE_INT value = INTVAL (operands[2]);
3545 rtx tmp = ((!can_create_pseudo_p ()
3546 || rtx_equal_p (operands[0], operands[1]))
3547 ? operands[0] : gen_reg_rtx (SImode));
3549 emit_insn (gen_xorsi3 (tmp, operands[1],
3550 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3551 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3552 DONE;
3553 }
3554 }")
3556 (define_insn "*boolsi3_internal1"
3557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3558 (match_operator:SI 3 "boolean_or_operator"
3559 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3560 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3561 ""
3562 "@
3563 %q3 %0,%1,%2
3564 {%q3il|%q3i} %0,%1,%b2
3565 {%q3iu|%q3is} %0,%1,%u2")
3567 (define_insn "*boolsi3_internal2"
3568 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3569 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3570 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3571 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3572 (const_int 0)))
3573 (clobber (match_scratch:SI 3 "=r,r"))]
3574 "TARGET_32BIT"
3575 "@
3576 %q4. %3,%1,%2
3577 #"
3578 [(set_attr "type" "fast_compare,compare")
3579 (set_attr "length" "4,8")])
3581 (define_split
3582 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3583 (compare:CC (match_operator:SI 4 "boolean_operator"
3584 [(match_operand:SI 1 "gpc_reg_operand" "")
3585 (match_operand:SI 2 "gpc_reg_operand" "")])
3586 (const_int 0)))
3587 (clobber (match_scratch:SI 3 ""))]
3588 "TARGET_32BIT && reload_completed"
3589 [(set (match_dup 3) (match_dup 4))
3590 (set (match_dup 0)
3591 (compare:CC (match_dup 3)
3592 (const_int 0)))]
3593 "")
3595 (define_insn "*boolsi3_internal3"
3596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3597 (compare:CC (match_operator:SI 4 "boolean_operator"
3598 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3599 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3600 (const_int 0)))
3601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3602 (match_dup 4))]
3603 "TARGET_32BIT"
3604 "@
3605 %q4. %0,%1,%2
3606 #"
3607 [(set_attr "type" "fast_compare,compare")
3608 (set_attr "length" "4,8")])
3610 (define_split
3611 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3612 (compare:CC (match_operator:SI 4 "boolean_operator"
3613 [(match_operand:SI 1 "gpc_reg_operand" "")
3614 (match_operand:SI 2 "gpc_reg_operand" "")])
3615 (const_int 0)))
3616 (set (match_operand:SI 0 "gpc_reg_operand" "")
3617 (match_dup 4))]
3618 "TARGET_32BIT && reload_completed"
3619 [(set (match_dup 0) (match_dup 4))
3620 (set (match_dup 3)
3621 (compare:CC (match_dup 0)
3622 (const_int 0)))]
3623 "")
3625 ;; Split a logical operation that we can't do in one insn into two insns,
3626 ;; each of which does one 16-bit part. This is used by combine.
3628 (define_split
3629 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3630 (match_operator:SI 3 "boolean_or_operator"
3631 [(match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3633 ""
3634 [(set (match_dup 0) (match_dup 4))
3635 (set (match_dup 0) (match_dup 5))]
3636 "
3637 {
3638 rtx i;
3639 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3640 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3641 operands[1], i);
3642 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3643 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3644 operands[0], i);
3645 }")
3647 (define_insn "*boolcsi3_internal1"
3648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3649 (match_operator:SI 3 "boolean_operator"
3650 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3651 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3652 ""
3653 "%q3 %0,%2,%1")
3655 (define_insn "*boolcsi3_internal2"
3656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3657 (compare:CC (match_operator:SI 4 "boolean_operator"
3658 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3659 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3660 (const_int 0)))
3661 (clobber (match_scratch:SI 3 "=r,r"))]
3662 "TARGET_32BIT"
3663 "@
3664 %q4. %3,%2,%1
3665 #"
3666 [(set_attr "type" "compare")
3667 (set_attr "length" "4,8")])
3669 (define_split
3670 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3671 (compare:CC (match_operator:SI 4 "boolean_operator"
3672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3673 (match_operand:SI 2 "gpc_reg_operand" "")])
3674 (const_int 0)))
3675 (clobber (match_scratch:SI 3 ""))]
3676 "TARGET_32BIT && reload_completed"
3677 [(set (match_dup 3) (match_dup 4))
3678 (set (match_dup 0)
3679 (compare:CC (match_dup 3)
3680 (const_int 0)))]
3681 "")
3683 (define_insn "*boolcsi3_internal3"
3684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3685 (compare:CC (match_operator:SI 4 "boolean_operator"
3686 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3687 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3688 (const_int 0)))
3689 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3690 (match_dup 4))]
3691 "TARGET_32BIT"
3692 "@
3693 %q4. %0,%2,%1
3694 #"
3695 [(set_attr "type" "compare")
3696 (set_attr "length" "4,8")])
3698 (define_split
3699 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3700 (compare:CC (match_operator:SI 4 "boolean_operator"
3701 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3702 (match_operand:SI 2 "gpc_reg_operand" "")])
3703 (const_int 0)))
3704 (set (match_operand:SI 0 "gpc_reg_operand" "")
3705 (match_dup 4))]
3706 "TARGET_32BIT && reload_completed"
3707 [(set (match_dup 0) (match_dup 4))
3708 (set (match_dup 3)
3709 (compare:CC (match_dup 0)
3710 (const_int 0)))]
3711 "")
3713 (define_insn "*boolccsi3_internal1"
3714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3715 (match_operator:SI 3 "boolean_operator"
3716 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3717 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3718 ""
3719 "%q3 %0,%1,%2")
3721 (define_insn "*boolccsi3_internal2"
3722 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3723 (compare:CC (match_operator:SI 4 "boolean_operator"
3724 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3725 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3726 (const_int 0)))
3727 (clobber (match_scratch:SI 3 "=r,r"))]
3728 "TARGET_32BIT"
3729 "@
3730 %q4. %3,%1,%2
3731 #"
3732 [(set_attr "type" "fast_compare,compare")
3733 (set_attr "length" "4,8")])
3735 (define_split
3736 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3737 (compare:CC (match_operator:SI 4 "boolean_operator"
3738 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3739 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3740 (const_int 0)))
3741 (clobber (match_scratch:SI 3 ""))]
3742 "TARGET_32BIT && reload_completed"
3743 [(set (match_dup 3) (match_dup 4))
3744 (set (match_dup 0)
3745 (compare:CC (match_dup 3)
3746 (const_int 0)))]
3747 "")
3749 (define_insn "*boolccsi3_internal3"
3750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3751 (compare:CC (match_operator:SI 4 "boolean_operator"
3752 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3753 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3754 (const_int 0)))
3755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3756 (match_dup 4))]
3757 "TARGET_32BIT"
3758 "@
3759 %q4. %0,%1,%2
3760 #"
3761 [(set_attr "type" "fast_compare,compare")
3762 (set_attr "length" "4,8")])
3764 (define_split
3765 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3766 (compare:CC (match_operator:SI 4 "boolean_operator"
3767 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3768 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3769 (const_int 0)))
3770 (set (match_operand:SI 0 "gpc_reg_operand" "")
3771 (match_dup 4))]
3772 "TARGET_32BIT && reload_completed"
3773 [(set (match_dup 0) (match_dup 4))
3774 (set (match_dup 3)
3775 (compare:CC (match_dup 0)
3776 (const_int 0)))]
3777 "")
3779 ;; maskir insn. We need four forms because things might be in arbitrary
3780 ;; orders. Don't define forms that only set CR fields because these
3781 ;; would modify an input register.
3783 (define_insn "*maskir_internal1"
3784 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3785 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3786 (match_operand:SI 1 "gpc_reg_operand" "0"))
3787 (and:SI (match_dup 2)
3788 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3789 "TARGET_POWER"
3790 "maskir %0,%3,%2")
3792 (define_insn "*maskir_internal2"
3793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3794 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3795 (match_operand:SI 1 "gpc_reg_operand" "0"))
3796 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3797 (match_dup 2))))]
3798 "TARGET_POWER"
3799 "maskir %0,%3,%2")
3801 (define_insn "*maskir_internal3"
3802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3803 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3804 (match_operand:SI 3 "gpc_reg_operand" "r"))
3805 (and:SI (not:SI (match_dup 2))
3806 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3807 "TARGET_POWER"
3808 "maskir %0,%3,%2")
3810 (define_insn "*maskir_internal4"
3811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3812 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3813 (match_operand:SI 2 "gpc_reg_operand" "r"))
3814 (and:SI (not:SI (match_dup 2))
3815 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3816 "TARGET_POWER"
3817 "maskir %0,%3,%2")
3819 (define_insn "*maskir_internal5"
3820 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3821 (compare:CC
3822 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3823 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3824 (and:SI (match_dup 2)
3825 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3826 (const_int 0)))
3827 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3828 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3829 (and:SI (match_dup 2) (match_dup 3))))]
3830 "TARGET_POWER"
3831 "@
3832 maskir. %0,%3,%2
3833 #"
3834 [(set_attr "type" "compare")
3835 (set_attr "length" "4,8")])
3837 (define_split
3838 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3839 (compare:CC
3840 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3841 (match_operand:SI 1 "gpc_reg_operand" ""))
3842 (and:SI (match_dup 2)
3843 (match_operand:SI 3 "gpc_reg_operand" "")))
3844 (const_int 0)))
3845 (set (match_operand:SI 0 "gpc_reg_operand" "")
3846 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3847 (and:SI (match_dup 2) (match_dup 3))))]
3848 "TARGET_POWER && reload_completed"
3849 [(set (match_dup 0)
3850 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3851 (and:SI (match_dup 2) (match_dup 3))))
3852 (set (match_dup 4)
3853 (compare:CC (match_dup 0)
3854 (const_int 0)))]
3855 "")
3857 (define_insn "*maskir_internal6"
3858 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3859 (compare:CC
3860 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3861 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3862 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3863 (match_dup 2)))
3864 (const_int 0)))
3865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3866 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3867 (and:SI (match_dup 3) (match_dup 2))))]
3868 "TARGET_POWER"
3869 "@
3870 maskir. %0,%3,%2
3871 #"
3872 [(set_attr "type" "compare")
3873 (set_attr "length" "4,8")])
3875 (define_split
3876 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3877 (compare:CC
3878 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3879 (match_operand:SI 1 "gpc_reg_operand" ""))
3880 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3881 (match_dup 2)))
3882 (const_int 0)))
3883 (set (match_operand:SI 0 "gpc_reg_operand" "")
3884 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3885 (and:SI (match_dup 3) (match_dup 2))))]
3886 "TARGET_POWER && reload_completed"
3887 [(set (match_dup 0)
3888 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3889 (and:SI (match_dup 3) (match_dup 2))))
3890 (set (match_dup 4)
3891 (compare:CC (match_dup 0)
3892 (const_int 0)))]
3893 "")
3895 (define_insn "*maskir_internal7"
3896 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3897 (compare:CC
3898 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3899 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3900 (and:SI (not:SI (match_dup 2))
3901 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3902 (const_int 0)))
3903 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3904 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3905 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3906 "TARGET_POWER"
3907 "@
3908 maskir. %0,%3,%2
3909 #"
3910 [(set_attr "type" "compare")
3911 (set_attr "length" "4,8")])
3913 (define_split
3914 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3915 (compare:CC
3916 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3917 (match_operand:SI 3 "gpc_reg_operand" ""))
3918 (and:SI (not:SI (match_dup 2))
3919 (match_operand:SI 1 "gpc_reg_operand" "")))
3920 (const_int 0)))
3921 (set (match_operand:SI 0 "gpc_reg_operand" "")
3922 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3923 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3924 "TARGET_POWER && reload_completed"
3925 [(set (match_dup 0)
3926 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3927 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3928 (set (match_dup 4)
3929 (compare:CC (match_dup 0)
3930 (const_int 0)))]
3931 "")
3933 (define_insn "*maskir_internal8"
3934 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3935 (compare:CC
3936 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3937 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3938 (and:SI (not:SI (match_dup 2))
3939 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3940 (const_int 0)))
3941 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3942 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3943 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3944 "TARGET_POWER"
3945 "@
3946 maskir. %0,%3,%2
3947 #"
3948 [(set_attr "type" "compare")
3949 (set_attr "length" "4,8")])
3951 (define_split
3952 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3953 (compare:CC
3954 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3955 (match_operand:SI 2 "gpc_reg_operand" ""))
3956 (and:SI (not:SI (match_dup 2))
3957 (match_operand:SI 1 "gpc_reg_operand" "")))
3958 (const_int 0)))
3959 (set (match_operand:SI 0 "gpc_reg_operand" "")
3960 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3961 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3962 "TARGET_POWER && reload_completed"
3963 [(set (match_dup 0)
3964 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3965 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3966 (set (match_dup 4)
3967 (compare:CC (match_dup 0)
3968 (const_int 0)))]
3969 "")
3970 \f
3971 ;; Rotate and shift insns, in all their variants. These support shifts,
3972 ;; field inserts and extracts, and various combinations thereof.
3973 (define_expand "insv"
3974 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3975 (match_operand:SI 1 "const_int_operand" "")
3976 (match_operand:SI 2 "const_int_operand" ""))
3977 (match_operand 3 "gpc_reg_operand" ""))]
3978 ""
3979 "
3980 {
3981 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3982 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3983 compiler if the address of the structure is taken later. Likewise, do
3984 not handle invalid E500 subregs. */
3985 if (GET_CODE (operands[0]) == SUBREG
3986 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3987 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3988 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3989 FAIL;
3991 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3992 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3993 else
3994 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3995 DONE;
3996 }")
3998 (define_insn "insvsi"
3999 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4000 (match_operand:SI 1 "const_int_operand" "i")
4001 (match_operand:SI 2 "const_int_operand" "i"))
4002 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4003 ""
4004 "*
4005 {
4006 int start = INTVAL (operands[2]) & 31;
4007 int size = INTVAL (operands[1]) & 31;
4009 operands[4] = GEN_INT (32 - start - size);
4010 operands[1] = GEN_INT (start + size - 1);
4011 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4012 }"
4013 [(set_attr "type" "insert_word")])
4015 (define_insn "*insvsi_internal1"
4016 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4017 (match_operand:SI 1 "const_int_operand" "i")
4018 (match_operand:SI 2 "const_int_operand" "i"))
4019 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4020 (match_operand:SI 4 "const_int_operand" "i")))]
4021 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4022 "*
4023 {
4024 int shift = INTVAL (operands[4]) & 31;
4025 int start = INTVAL (operands[2]) & 31;
4026 int size = INTVAL (operands[1]) & 31;
4028 operands[4] = GEN_INT (shift - start - size);
4029 operands[1] = GEN_INT (start + size - 1);
4030 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4031 }"
4032 [(set_attr "type" "insert_word")])
4034 (define_insn "*insvsi_internal2"
4035 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4036 (match_operand:SI 1 "const_int_operand" "i")
4037 (match_operand:SI 2 "const_int_operand" "i"))
4038 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4039 (match_operand:SI 4 "const_int_operand" "i")))]
4040 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4041 "*
4042 {
4043 int shift = INTVAL (operands[4]) & 31;
4044 int start = INTVAL (operands[2]) & 31;
4045 int size = INTVAL (operands[1]) & 31;
4047 operands[4] = GEN_INT (32 - shift - start - size);
4048 operands[1] = GEN_INT (start + size - 1);
4049 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4050 }"
4051 [(set_attr "type" "insert_word")])
4053 (define_insn "*insvsi_internal3"
4054 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4055 (match_operand:SI 1 "const_int_operand" "i")
4056 (match_operand:SI 2 "const_int_operand" "i"))
4057 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4058 (match_operand:SI 4 "const_int_operand" "i")))]
4059 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4060 "*
4061 {
4062 int shift = INTVAL (operands[4]) & 31;
4063 int start = INTVAL (operands[2]) & 31;
4064 int size = INTVAL (operands[1]) & 31;
4066 operands[4] = GEN_INT (32 - shift - start - size);
4067 operands[1] = GEN_INT (start + size - 1);
4068 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4069 }"
4070 [(set_attr "type" "insert_word")])
4072 (define_insn "*insvsi_internal4"
4073 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4074 (match_operand:SI 1 "const_int_operand" "i")
4075 (match_operand:SI 2 "const_int_operand" "i"))
4076 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4077 (match_operand:SI 4 "const_int_operand" "i")
4078 (match_operand:SI 5 "const_int_operand" "i")))]
4079 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4080 "*
4081 {
4082 int extract_start = INTVAL (operands[5]) & 31;
4083 int extract_size = INTVAL (operands[4]) & 31;
4084 int insert_start = INTVAL (operands[2]) & 31;
4085 int insert_size = INTVAL (operands[1]) & 31;
4087 /* Align extract field with insert field */
4088 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4089 operands[1] = GEN_INT (insert_start + insert_size - 1);
4090 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4091 }"
4092 [(set_attr "type" "insert_word")])
4094 ;; combine patterns for rlwimi
4095 (define_insn "*insvsi_internal5"
4096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4097 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4098 (match_operand:SI 1 "mask_operand" "i"))
4099 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4100 (match_operand:SI 2 "const_int_operand" "i"))
4101 (match_operand:SI 5 "mask_operand" "i"))))]
4102 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4103 "*
4104 {
4105 int me = extract_ME(operands[5]);
4106 int mb = extract_MB(operands[5]);
4107 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4108 operands[2] = GEN_INT(mb);
4109 operands[1] = GEN_INT(me);
4110 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4111 }"
4112 [(set_attr "type" "insert_word")])
4114 (define_insn "*insvsi_internal6"
4115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4116 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4117 (match_operand:SI 2 "const_int_operand" "i"))
4118 (match_operand:SI 5 "mask_operand" "i"))
4119 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4120 (match_operand:SI 1 "mask_operand" "i"))))]
4121 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4122 "*
4123 {
4124 int me = extract_ME(operands[5]);
4125 int mb = extract_MB(operands[5]);
4126 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4127 operands[2] = GEN_INT(mb);
4128 operands[1] = GEN_INT(me);
4129 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4130 }"
4131 [(set_attr "type" "insert_word")])
4133 (define_insn "insvdi"
4134 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4135 (match_operand:SI 1 "const_int_operand" "i")
4136 (match_operand:SI 2 "const_int_operand" "i"))
4137 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4138 "TARGET_POWERPC64"
4139 "*
4140 {
4141 int start = INTVAL (operands[2]) & 63;
4142 int size = INTVAL (operands[1]) & 63;
4144 operands[1] = GEN_INT (64 - start - size);
4145 return \"rldimi %0,%3,%H1,%H2\";
4146 }"
4147 [(set_attr "type" "insert_dword")])
4149 (define_insn "*insvdi_internal2"
4150 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4151 (match_operand:SI 1 "const_int_operand" "i")
4152 (match_operand:SI 2 "const_int_operand" "i"))
4153 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4154 (match_operand:SI 4 "const_int_operand" "i")))]
4155 "TARGET_POWERPC64
4156 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4157 "*
4158 {
4159 int shift = INTVAL (operands[4]) & 63;
4160 int start = (INTVAL (operands[2]) & 63) - 32;
4161 int size = INTVAL (operands[1]) & 63;
4163 operands[4] = GEN_INT (64 - shift - start - size);
4164 operands[2] = GEN_INT (start);
4165 operands[1] = GEN_INT (start + size - 1);
4166 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4167 }")
4169 (define_insn "*insvdi_internal3"
4170 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4171 (match_operand:SI 1 "const_int_operand" "i")
4172 (match_operand:SI 2 "const_int_operand" "i"))
4173 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4174 (match_operand:SI 4 "const_int_operand" "i")))]
4175 "TARGET_POWERPC64
4176 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4177 "*
4178 {
4179 int shift = INTVAL (operands[4]) & 63;
4180 int start = (INTVAL (operands[2]) & 63) - 32;
4181 int size = INTVAL (operands[1]) & 63;
4183 operands[4] = GEN_INT (64 - shift - start - size);
4184 operands[2] = GEN_INT (start);
4185 operands[1] = GEN_INT (start + size - 1);
4186 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4187 }")
4189 (define_expand "extzv"
4190 [(set (match_operand 0 "gpc_reg_operand" "")
4191 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4192 (match_operand:SI 2 "const_int_operand" "")
4193 (match_operand:SI 3 "const_int_operand" "")))]
4194 ""
4195 "
4196 {
4197 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4198 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4199 compiler if the address of the structure is taken later. */
4200 if (GET_CODE (operands[0]) == SUBREG
4201 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4202 FAIL;
4204 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4205 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4206 else
4207 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4208 DONE;
4209 }")
4211 (define_insn "extzvsi"
4212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4213 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4214 (match_operand:SI 2 "const_int_operand" "i")
4215 (match_operand:SI 3 "const_int_operand" "i")))]
4216 ""
4217 "*
4218 {
4219 int start = INTVAL (operands[3]) & 31;
4220 int size = INTVAL (operands[2]) & 31;
4222 if (start + size >= 32)
4223 operands[3] = const0_rtx;
4224 else
4225 operands[3] = GEN_INT (start + size);
4226 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4227 }")
4229 (define_insn "*extzvsi_internal1"
4230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4231 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4232 (match_operand:SI 2 "const_int_operand" "i,i")
4233 (match_operand:SI 3 "const_int_operand" "i,i"))
4234 (const_int 0)))
4235 (clobber (match_scratch:SI 4 "=r,r"))]
4236 ""
4237 "*
4238 {
4239 int start = INTVAL (operands[3]) & 31;
4240 int size = INTVAL (operands[2]) & 31;
4242 /* Force split for non-cc0 compare. */
4243 if (which_alternative == 1)
4244 return \"#\";
4246 /* If the bit-field being tested fits in the upper or lower half of a
4247 word, it is possible to use andiu. or andil. to test it. This is
4248 useful because the condition register set-use delay is smaller for
4249 andi[ul]. than for rlinm. This doesn't work when the starting bit
4250 position is 0 because the LT and GT bits may be set wrong. */
4252 if ((start > 0 && start + size <= 16) || start >= 16)
4253 {
4254 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4255 - (1 << (16 - (start & 15) - size))));
4256 if (start < 16)
4257 return \"{andiu.|andis.} %4,%1,%3\";
4258 else
4259 return \"{andil.|andi.} %4,%1,%3\";
4260 }
4262 if (start + size >= 32)
4263 operands[3] = const0_rtx;
4264 else
4265 operands[3] = GEN_INT (start + size);
4266 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4267 }"
4268 [(set_attr "type" "delayed_compare")
4269 (set_attr "length" "4,8")])
4271 (define_split
4272 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4273 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4274 (match_operand:SI 2 "const_int_operand" "")
4275 (match_operand:SI 3 "const_int_operand" ""))
4276 (const_int 0)))
4277 (clobber (match_scratch:SI 4 ""))]
4278 "reload_completed"
4279 [(set (match_dup 4)
4280 (zero_extract:SI (match_dup 1) (match_dup 2)
4281 (match_dup 3)))
4282 (set (match_dup 0)
4283 (compare:CC (match_dup 4)
4284 (const_int 0)))]
4285 "")
4287 (define_insn "*extzvsi_internal2"
4288 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4289 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4290 (match_operand:SI 2 "const_int_operand" "i,i")
4291 (match_operand:SI 3 "const_int_operand" "i,i"))
4292 (const_int 0)))
4293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4294 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4295 ""
4296 "*
4297 {
4298 int start = INTVAL (operands[3]) & 31;
4299 int size = INTVAL (operands[2]) & 31;
4301 /* Force split for non-cc0 compare. */
4302 if (which_alternative == 1)
4303 return \"#\";
4305 /* Since we are using the output value, we can't ignore any need for
4306 a shift. The bit-field must end at the LSB. */
4307 if (start >= 16 && start + size == 32)
4308 {
4309 operands[3] = GEN_INT ((1 << size) - 1);
4310 return \"{andil.|andi.} %0,%1,%3\";
4311 }
4313 if (start + size >= 32)
4314 operands[3] = const0_rtx;
4315 else
4316 operands[3] = GEN_INT (start + size);
4317 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4318 }"
4319 [(set_attr "type" "delayed_compare")
4320 (set_attr "length" "4,8")])
4322 (define_split
4323 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4324 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4325 (match_operand:SI 2 "const_int_operand" "")
4326 (match_operand:SI 3 "const_int_operand" ""))
4327 (const_int 0)))
4328 (set (match_operand:SI 0 "gpc_reg_operand" "")
4329 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4330 "reload_completed"
4331 [(set (match_dup 0)
4332 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4333 (set (match_dup 4)
4334 (compare:CC (match_dup 0)
4335 (const_int 0)))]
4336 "")
4338 (define_insn "extzvdi"
4339 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4340 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4341 (match_operand:SI 2 "const_int_operand" "i")
4342 (match_operand:SI 3 "const_int_operand" "i")))]
4343 "TARGET_POWERPC64"
4344 "*
4345 {
4346 int start = INTVAL (operands[3]) & 63;
4347 int size = INTVAL (operands[2]) & 63;
4349 if (start + size >= 64)
4350 operands[3] = const0_rtx;
4351 else
4352 operands[3] = GEN_INT (start + size);
4353 operands[2] = GEN_INT (64 - size);
4354 return \"rldicl %0,%1,%3,%2\";
4355 }")
4357 (define_insn "*extzvdi_internal1"
4358 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4359 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4360 (match_operand:SI 2 "const_int_operand" "i")
4361 (match_operand:SI 3 "const_int_operand" "i"))
4362 (const_int 0)))
4363 (clobber (match_scratch:DI 4 "=r"))]
4364 "TARGET_64BIT && rs6000_gen_cell_microcode"
4365 "*
4366 {
4367 int start = INTVAL (operands[3]) & 63;
4368 int size = INTVAL (operands[2]) & 63;
4370 if (start + size >= 64)
4371 operands[3] = const0_rtx;
4372 else
4373 operands[3] = GEN_INT (start + size);
4374 operands[2] = GEN_INT (64 - size);
4375 return \"rldicl. %4,%1,%3,%2\";
4376 }"
4377 [(set_attr "type" "compare")])
4379 (define_insn "*extzvdi_internal2"
4380 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4381 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4382 (match_operand:SI 2 "const_int_operand" "i")
4383 (match_operand:SI 3 "const_int_operand" "i"))
4384 (const_int 0)))
4385 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4386 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4387 "TARGET_64BIT && rs6000_gen_cell_microcode"
4388 "*
4389 {
4390 int start = INTVAL (operands[3]) & 63;
4391 int size = INTVAL (operands[2]) & 63;
4393 if (start + size >= 64)
4394 operands[3] = const0_rtx;
4395 else
4396 operands[3] = GEN_INT (start + size);
4397 operands[2] = GEN_INT (64 - size);
4398 return \"rldicl. %0,%1,%3,%2\";
4399 }"
4400 [(set_attr "type" "compare")])
4402 (define_insn "rotlsi3"
4403 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4404 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4405 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4406 ""
4407 "@
4408 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4409 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4410 [(set_attr "type" "var_shift_rotate,integer")])
4412 (define_insn "*rotlsi3_64"
4413 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4414 (zero_extend:DI
4415 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4416 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4417 "TARGET_64BIT"
4418 "@
4419 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4420 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4421 [(set_attr "type" "var_shift_rotate,integer")])
4423 (define_insn "*rotlsi3_internal2"
4424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4425 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4426 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4427 (const_int 0)))
4428 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4429 ""
4430 "@
4431 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4432 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4433 #
4434 #"
4435 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4436 (set_attr "length" "4,4,8,8")])
4438 (define_split
4439 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4440 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4441 (match_operand:SI 2 "reg_or_cint_operand" ""))
4442 (const_int 0)))
4443 (clobber (match_scratch:SI 3 ""))]
4444 "reload_completed"
4445 [(set (match_dup 3)
4446 (rotate:SI (match_dup 1) (match_dup 2)))
4447 (set (match_dup 0)
4448 (compare:CC (match_dup 3)
4449 (const_int 0)))]
4450 "")
4452 (define_insn "*rotlsi3_internal3"
4453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4454 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4456 (const_int 0)))
4457 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4458 (rotate:SI (match_dup 1) (match_dup 2)))]
4459 ""
4460 "@
4461 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4462 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4463 #
4464 #"
4465 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4466 (set_attr "length" "4,4,8,8")])
4468 (define_split
4469 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4470 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4471 (match_operand:SI 2 "reg_or_cint_operand" ""))
4472 (const_int 0)))
4473 (set (match_operand:SI 0 "gpc_reg_operand" "")
4474 (rotate:SI (match_dup 1) (match_dup 2)))]
4475 "reload_completed"
4476 [(set (match_dup 0)
4477 (rotate:SI (match_dup 1) (match_dup 2)))
4478 (set (match_dup 3)
4479 (compare:CC (match_dup 0)
4480 (const_int 0)))]
4481 "")
4483 (define_insn "*rotlsi3_internal4"
4484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4485 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4486 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4487 (match_operand:SI 3 "mask_operand" "n,n")))]
4488 ""
4489 "@
4490 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4491 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4492 [(set_attr "type" "var_shift_rotate,integer")])
4494 (define_insn "*rotlsi3_internal5"
4495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4496 (compare:CC (and:SI
4497 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4498 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4499 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4500 (const_int 0)))
4501 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4502 ""
4503 "@
4504 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4505 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4506 #
4507 #"
4508 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4509 (set_attr "length" "4,4,8,8")])
4511 (define_split
4512 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4513 (compare:CC (and:SI
4514 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4515 (match_operand:SI 2 "reg_or_cint_operand" ""))
4516 (match_operand:SI 3 "mask_operand" ""))
4517 (const_int 0)))
4518 (clobber (match_scratch:SI 4 ""))]
4519 "reload_completed"
4520 [(set (match_dup 4)
4521 (and:SI (rotate:SI (match_dup 1)
4522 (match_dup 2))
4523 (match_dup 3)))
4524 (set (match_dup 0)
4525 (compare:CC (match_dup 4)
4526 (const_int 0)))]
4527 "")
4529 (define_insn "*rotlsi3_internal6"
4530 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4531 (compare:CC (and:SI
4532 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4533 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4534 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4535 (const_int 0)))
4536 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4537 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4538 ""
4539 "@
4540 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4541 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4542 #
4543 #"
4544 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4545 (set_attr "length" "4,4,8,8")])
4547 (define_split
4548 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4549 (compare:CC (and:SI
4550 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4551 (match_operand:SI 2 "reg_or_cint_operand" ""))
4552 (match_operand:SI 3 "mask_operand" ""))
4553 (const_int 0)))
4554 (set (match_operand:SI 0 "gpc_reg_operand" "")
4555 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4556 "reload_completed"
4557 [(set (match_dup 0)
4558 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4559 (set (match_dup 4)
4560 (compare:CC (match_dup 0)
4561 (const_int 0)))]
4562 "")
4564 (define_insn "*rotlsi3_internal7"
4565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4566 (zero_extend:SI
4567 (subreg:QI
4568 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4569 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4570 ""
4571 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4572 [(set (attr "cell_micro")
4573 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4574 (const_string "not")
4575 (const_string "always")))])
4577 (define_insn "*rotlsi3_internal8"
4578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4579 (compare:CC (zero_extend:SI
4580 (subreg:QI
4581 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4582 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4583 (const_int 0)))
4584 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4585 ""
4586 "@
4587 {rlnm.|rlwnm.} %3,%1,%2,0xff
4588 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4589 #
4590 #"
4591 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4592 (set_attr "length" "4,4,8,8")])
4594 (define_split
4595 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4596 (compare:CC (zero_extend:SI
4597 (subreg:QI
4598 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4599 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4600 (const_int 0)))
4601 (clobber (match_scratch:SI 3 ""))]
4602 "reload_completed"
4603 [(set (match_dup 3)
4604 (zero_extend:SI (subreg:QI
4605 (rotate:SI (match_dup 1)
4606 (match_dup 2)) 0)))
4607 (set (match_dup 0)
4608 (compare:CC (match_dup 3)
4609 (const_int 0)))]
4610 "")
4612 (define_insn "*rotlsi3_internal9"
4613 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4614 (compare:CC (zero_extend:SI
4615 (subreg:QI
4616 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4617 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4618 (const_int 0)))
4619 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4620 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4621 ""
4622 "@
4623 {rlnm.|rlwnm.} %0,%1,%2,0xff
4624 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4625 #
4626 #"
4627 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4628 (set_attr "length" "4,4,8,8")])
4630 (define_split
4631 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4632 (compare:CC (zero_extend:SI
4633 (subreg:QI
4634 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4635 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4636 (const_int 0)))
4637 (set (match_operand:SI 0 "gpc_reg_operand" "")
4638 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4639 "reload_completed"
4640 [(set (match_dup 0)
4641 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4642 (set (match_dup 3)
4643 (compare:CC (match_dup 0)
4644 (const_int 0)))]
4645 "")
4647 (define_insn "*rotlsi3_internal10"
4648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4649 (zero_extend:SI
4650 (subreg:HI
4651 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4652 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4653 ""
4654 "@
4655 {rlnm|rlwnm} %0,%1,%2,0xffff
4656 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4657 [(set_attr "type" "var_shift_rotate,integer")])
4660 (define_insn "*rotlsi3_internal11"
4661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4662 (compare:CC (zero_extend:SI
4663 (subreg:HI
4664 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4665 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4666 (const_int 0)))
4667 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4668 ""
4669 "@
4670 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4671 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4672 #
4673 #"
4674 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4675 (set_attr "length" "4,4,8,8")])
4677 (define_split
4678 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4679 (compare:CC (zero_extend:SI
4680 (subreg:HI
4681 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4682 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4683 (const_int 0)))
4684 (clobber (match_scratch:SI 3 ""))]
4685 "reload_completed"
4686 [(set (match_dup 3)
4687 (zero_extend:SI (subreg:HI
4688 (rotate:SI (match_dup 1)
4689 (match_dup 2)) 0)))
4690 (set (match_dup 0)
4691 (compare:CC (match_dup 3)
4692 (const_int 0)))]
4693 "")
4695 (define_insn "*rotlsi3_internal12"
4696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4697 (compare:CC (zero_extend:SI
4698 (subreg:HI
4699 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4700 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4701 (const_int 0)))
4702 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4703 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4704 ""
4705 "@
4706 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4707 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4708 #
4709 #"
4710 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4711 (set_attr "length" "4,4,8,8")])
4713 (define_split
4714 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4715 (compare:CC (zero_extend:SI
4716 (subreg:HI
4717 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4718 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4719 (const_int 0)))
4720 (set (match_operand:SI 0 "gpc_reg_operand" "")
4721 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4722 "reload_completed"
4723 [(set (match_dup 0)
4724 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4725 (set (match_dup 3)
4726 (compare:CC (match_dup 0)
4727 (const_int 0)))]
4728 "")
4730 ;; Note that we use "sle." instead of "sl." so that we can set
4731 ;; SHIFT_COUNT_TRUNCATED.
4733 (define_expand "ashlsi3"
4734 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4735 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4736 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4737 ""
4738 "
4739 {
4740 if (TARGET_POWER)
4741 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4742 else
4743 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4744 DONE;
4745 }")
4747 (define_insn "ashlsi3_power"
4748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4749 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4750 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4751 (clobber (match_scratch:SI 3 "=q,X"))]
4752 "TARGET_POWER"
4753 "@
4754 sle %0,%1,%2
4755 {sli|slwi} %0,%1,%h2")
4757 (define_insn "ashlsi3_no_power"
4758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4759 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4760 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4761 "! TARGET_POWER"
4762 "@
4763 {sl|slw} %0,%1,%2
4764 {sli|slwi} %0,%1,%h2"
4765 [(set_attr "type" "var_shift_rotate,shift")])
4767 (define_insn "*ashlsi3_64"
4768 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4769 (zero_extend:DI
4770 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4771 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4772 "TARGET_POWERPC64"
4773 "@
4774 {sl|slw} %0,%1,%2
4775 {sli|slwi} %0,%1,%h2"
4776 [(set_attr "type" "var_shift_rotate,shift")])
4778 (define_insn ""
4779 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4780 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4781 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4782 (const_int 0)))
4783 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4784 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4785 "TARGET_POWER"
4786 "@
4787 sle. %3,%1,%2
4788 {sli.|slwi.} %3,%1,%h2
4789 #
4790 #"
4791 [(set_attr "type" "delayed_compare")
4792 (set_attr "length" "4,4,8,8")])
4794 (define_split
4795 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4796 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4797 (match_operand:SI 2 "reg_or_cint_operand" ""))
4798 (const_int 0)))
4799 (clobber (match_scratch:SI 3 ""))
4800 (clobber (match_scratch:SI 4 ""))]
4801 "TARGET_POWER && reload_completed"
4802 [(parallel [(set (match_dup 3)
4803 (ashift:SI (match_dup 1) (match_dup 2)))
4804 (clobber (match_dup 4))])
4805 (set (match_dup 0)
4806 (compare:CC (match_dup 3)
4807 (const_int 0)))]
4808 "")
4810 (define_insn ""
4811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4812 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4813 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4814 (const_int 0)))
4815 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4816 "! TARGET_POWER && TARGET_32BIT"
4817 "@
4818 {sl.|slw.} %3,%1,%2
4819 {sli.|slwi.} %3,%1,%h2
4820 #
4821 #"
4822 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4823 (set_attr "length" "4,4,8,8")])
4825 (define_split
4826 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4827 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4828 (match_operand:SI 2 "reg_or_cint_operand" ""))
4829 (const_int 0)))
4830 (clobber (match_scratch:SI 3 ""))]
4831 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4832 [(set (match_dup 3)
4833 (ashift:SI (match_dup 1) (match_dup 2)))
4834 (set (match_dup 0)
4835 (compare:CC (match_dup 3)
4836 (const_int 0)))]
4837 "")
4839 (define_insn ""
4840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4841 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4842 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4843 (const_int 0)))
4844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4845 (ashift:SI (match_dup 1) (match_dup 2)))
4846 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4847 "TARGET_POWER"
4848 "@
4849 sle. %0,%1,%2
4850 {sli.|slwi.} %0,%1,%h2
4851 #
4852 #"
4853 [(set_attr "type" "delayed_compare")
4854 (set_attr "length" "4,4,8,8")])
4856 (define_split
4857 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4858 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4859 (match_operand:SI 2 "reg_or_cint_operand" ""))
4860 (const_int 0)))
4861 (set (match_operand:SI 0 "gpc_reg_operand" "")
4862 (ashift:SI (match_dup 1) (match_dup 2)))
4863 (clobber (match_scratch:SI 4 ""))]
4864 "TARGET_POWER && reload_completed"
4865 [(parallel [(set (match_dup 0)
4866 (ashift:SI (match_dup 1) (match_dup 2)))
4867 (clobber (match_dup 4))])
4868 (set (match_dup 3)
4869 (compare:CC (match_dup 0)
4870 (const_int 0)))]
4871 "")
4873 (define_insn ""
4874 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4875 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4876 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4877 (const_int 0)))
4878 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4879 (ashift:SI (match_dup 1) (match_dup 2)))]
4880 "! TARGET_POWER && TARGET_32BIT"
4881 "@
4882 {sl.|slw.} %0,%1,%2
4883 {sli.|slwi.} %0,%1,%h2
4884 #
4885 #"
4886 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4887 (set_attr "length" "4,4,8,8")])
4889 (define_split
4890 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4891 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4892 (match_operand:SI 2 "reg_or_cint_operand" ""))
4893 (const_int 0)))
4894 (set (match_operand:SI 0 "gpc_reg_operand" "")
4895 (ashift:SI (match_dup 1) (match_dup 2)))]
4896 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4897 [(set (match_dup 0)
4898 (ashift:SI (match_dup 1) (match_dup 2)))
4899 (set (match_dup 3)
4900 (compare:CC (match_dup 0)
4901 (const_int 0)))]
4902 "")
4904 (define_insn "rlwinm"
4905 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4906 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4907 (match_operand:SI 2 "const_int_operand" "i"))
4908 (match_operand:SI 3 "mask_operand" "n")))]
4909 "includes_lshift_p (operands[2], operands[3])"
4910 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4912 (define_insn ""
4913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4914 (compare:CC
4915 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4916 (match_operand:SI 2 "const_int_operand" "i,i"))
4917 (match_operand:SI 3 "mask_operand" "n,n"))
4918 (const_int 0)))
4919 (clobber (match_scratch:SI 4 "=r,r"))]
4920 "includes_lshift_p (operands[2], operands[3])"
4921 "@
4922 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4923 #"
4924 [(set_attr "type" "delayed_compare")
4925 (set_attr "length" "4,8")])
4927 (define_split
4928 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4929 (compare:CC
4930 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4931 (match_operand:SI 2 "const_int_operand" ""))
4932 (match_operand:SI 3 "mask_operand" ""))
4933 (const_int 0)))
4934 (clobber (match_scratch:SI 4 ""))]
4935 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4936 [(set (match_dup 4)
4937 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4938 (match_dup 3)))
4939 (set (match_dup 0)
4940 (compare:CC (match_dup 4)
4941 (const_int 0)))]
4942 "")
4944 (define_insn ""
4945 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4946 (compare:CC
4947 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4948 (match_operand:SI 2 "const_int_operand" "i,i"))
4949 (match_operand:SI 3 "mask_operand" "n,n"))
4950 (const_int 0)))
4951 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4952 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4953 "includes_lshift_p (operands[2], operands[3])"
4954 "@
4955 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4956 #"
4957 [(set_attr "type" "delayed_compare")
4958 (set_attr "length" "4,8")])
4960 (define_split
4961 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4962 (compare:CC
4963 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4964 (match_operand:SI 2 "const_int_operand" ""))
4965 (match_operand:SI 3 "mask_operand" ""))
4966 (const_int 0)))
4967 (set (match_operand:SI 0 "gpc_reg_operand" "")
4968 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4969 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4970 [(set (match_dup 0)
4971 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4972 (set (match_dup 4)
4973 (compare:CC (match_dup 0)
4974 (const_int 0)))]
4975 "")
4977 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4978 ;; "sli x,x,0".
4979 (define_expand "lshrsi3"
4980 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4981 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4982 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4983 ""
4984 "
4985 {
4986 if (TARGET_POWER)
4987 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4988 else
4989 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4990 DONE;
4991 }")
4993 (define_insn "lshrsi3_power"
4994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4995 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4996 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4997 (clobber (match_scratch:SI 3 "=q,X,X"))]
4998 "TARGET_POWER"
4999 "@
5000 sre %0,%1,%2
5001 mr %0,%1
5002 {s%A2i|s%A2wi} %0,%1,%h2")
5004 (define_insn "lshrsi3_no_power"
5005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5006 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5007 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5008 "! TARGET_POWER"
5009 "@
5010 mr %0,%1
5011 {sr|srw} %0,%1,%2
5012 {sri|srwi} %0,%1,%h2"
5013 [(set_attr "type" "integer,var_shift_rotate,shift")])
5015 (define_insn "*lshrsi3_64"
5016 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5017 (zero_extend:DI
5018 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5019 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5020 "TARGET_POWERPC64"
5021 "@
5022 {sr|srw} %0,%1,%2
5023 {sri|srwi} %0,%1,%h2"
5024 [(set_attr "type" "var_shift_rotate,shift")])
5026 (define_insn ""
5027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5028 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5029 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5030 (const_int 0)))
5031 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5032 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5033 "TARGET_POWER"
5034 "@
5035 sre. %3,%1,%2
5036 mr. %1,%1
5037 {s%A2i.|s%A2wi.} %3,%1,%h2
5038 #
5039 #
5040 #"
5041 [(set_attr "type" "delayed_compare")
5042 (set_attr "length" "4,4,4,8,8,8")])
5044 (define_split
5045 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5046 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5047 (match_operand:SI 2 "reg_or_cint_operand" ""))
5048 (const_int 0)))
5049 (clobber (match_scratch:SI 3 ""))
5050 (clobber (match_scratch:SI 4 ""))]
5051 "TARGET_POWER && reload_completed"
5052 [(parallel [(set (match_dup 3)
5053 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5054 (clobber (match_dup 4))])
5055 (set (match_dup 0)
5056 (compare:CC (match_dup 3)
5057 (const_int 0)))]
5058 "")
5060 (define_insn ""
5061 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5062 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5063 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5064 (const_int 0)))
5065 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5066 "! TARGET_POWER && TARGET_32BIT"
5067 "@
5068 mr. %1,%1
5069 {sr.|srw.} %3,%1,%2
5070 {sri.|srwi.} %3,%1,%h2
5071 #
5072 #
5073 #"
5074 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5075 (set_attr "length" "4,4,4,8,8,8")])
5077 (define_split
5078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5079 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5080 (match_operand:SI 2 "reg_or_cint_operand" ""))
5081 (const_int 0)))
5082 (clobber (match_scratch:SI 3 ""))]
5083 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5084 [(set (match_dup 3)
5085 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5086 (set (match_dup 0)
5087 (compare:CC (match_dup 3)
5088 (const_int 0)))]
5089 "")
5091 (define_insn ""
5092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5093 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5094 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5095 (const_int 0)))
5096 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5097 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5098 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5099 "TARGET_POWER"
5100 "@
5101 sre. %0,%1,%2
5102 mr. %0,%1
5103 {s%A2i.|s%A2wi.} %0,%1,%h2
5104 #
5105 #
5106 #"
5107 [(set_attr "type" "delayed_compare")
5108 (set_attr "length" "4,4,4,8,8,8")])
5110 (define_split
5111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5112 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5113 (match_operand:SI 2 "reg_or_cint_operand" ""))
5114 (const_int 0)))
5115 (set (match_operand:SI 0 "gpc_reg_operand" "")
5116 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5117 (clobber (match_scratch:SI 4 ""))]
5118 "TARGET_POWER && reload_completed"
5119 [(parallel [(set (match_dup 0)
5120 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5121 (clobber (match_dup 4))])
5122 (set (match_dup 3)
5123 (compare:CC (match_dup 0)
5124 (const_int 0)))]
5125 "")
5127 (define_insn ""
5128 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5129 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5130 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5131 (const_int 0)))
5132 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5133 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5134 "! TARGET_POWER && TARGET_32BIT"
5135 "@
5136 mr. %0,%1
5137 {sr.|srw.} %0,%1,%2
5138 {sri.|srwi.} %0,%1,%h2
5139 #
5140 #
5141 #"
5142 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5143 (set_attr "length" "4,4,4,8,8,8")])
5145 (define_split
5146 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5147 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5148 (match_operand:SI 2 "reg_or_cint_operand" ""))
5149 (const_int 0)))
5150 (set (match_operand:SI 0 "gpc_reg_operand" "")
5151 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5152 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5153 [(set (match_dup 0)
5154 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5155 (set (match_dup 3)
5156 (compare:CC (match_dup 0)
5157 (const_int 0)))]
5158 "")
5160 (define_insn ""
5161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5162 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5163 (match_operand:SI 2 "const_int_operand" "i"))
5164 (match_operand:SI 3 "mask_operand" "n")))]
5165 "includes_rshift_p (operands[2], operands[3])"
5166 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5168 (define_insn ""
5169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5170 (compare:CC
5171 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5172 (match_operand:SI 2 "const_int_operand" "i,i"))
5173 (match_operand:SI 3 "mask_operand" "n,n"))
5174 (const_int 0)))
5175 (clobber (match_scratch:SI 4 "=r,r"))]
5176 "includes_rshift_p (operands[2], operands[3])"
5177 "@
5178 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5179 #"
5180 [(set_attr "type" "delayed_compare")
5181 (set_attr "length" "4,8")])
5183 (define_split
5184 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5185 (compare:CC
5186 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5187 (match_operand:SI 2 "const_int_operand" ""))
5188 (match_operand:SI 3 "mask_operand" ""))
5189 (const_int 0)))
5190 (clobber (match_scratch:SI 4 ""))]
5191 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5192 [(set (match_dup 4)
5193 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5194 (match_dup 3)))
5195 (set (match_dup 0)
5196 (compare:CC (match_dup 4)
5197 (const_int 0)))]
5198 "")
5200 (define_insn ""
5201 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5202 (compare:CC
5203 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5204 (match_operand:SI 2 "const_int_operand" "i,i"))
5205 (match_operand:SI 3 "mask_operand" "n,n"))
5206 (const_int 0)))
5207 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5208 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5209 "includes_rshift_p (operands[2], operands[3])"
5210 "@
5211 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5212 #"
5213 [(set_attr "type" "delayed_compare")
5214 (set_attr "length" "4,8")])
5216 (define_split
5217 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5218 (compare:CC
5219 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5220 (match_operand:SI 2 "const_int_operand" ""))
5221 (match_operand:SI 3 "mask_operand" ""))
5222 (const_int 0)))
5223 (set (match_operand:SI 0 "gpc_reg_operand" "")
5224 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5225 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5226 [(set (match_dup 0)
5227 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5228 (set (match_dup 4)
5229 (compare:CC (match_dup 0)
5230 (const_int 0)))]
5231 "")
5233 (define_insn ""
5234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5235 (zero_extend:SI
5236 (subreg:QI
5237 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5238 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5239 "includes_rshift_p (operands[2], GEN_INT (255))"
5240 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5242 (define_insn ""
5243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5244 (compare:CC
5245 (zero_extend:SI
5246 (subreg:QI
5247 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5248 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5249 (const_int 0)))
5250 (clobber (match_scratch:SI 3 "=r,r"))]
5251 "includes_rshift_p (operands[2], GEN_INT (255))"
5252 "@
5253 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5254 #"
5255 [(set_attr "type" "delayed_compare")
5256 (set_attr "length" "4,8")])
5258 (define_split
5259 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5260 (compare:CC
5261 (zero_extend:SI
5262 (subreg:QI
5263 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5264 (match_operand:SI 2 "const_int_operand" "")) 0))
5265 (const_int 0)))
5266 (clobber (match_scratch:SI 3 ""))]
5267 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5268 [(set (match_dup 3)
5269 (zero_extend:SI (subreg:QI
5270 (lshiftrt:SI (match_dup 1)
5271 (match_dup 2)) 0)))
5272 (set (match_dup 0)
5273 (compare:CC (match_dup 3)
5274 (const_int 0)))]
5275 "")
5277 (define_insn ""
5278 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5279 (compare:CC
5280 (zero_extend:SI
5281 (subreg:QI
5282 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5283 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5284 (const_int 0)))
5285 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5286 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5287 "includes_rshift_p (operands[2], GEN_INT (255))"
5288 "@
5289 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5290 #"
5291 [(set_attr "type" "delayed_compare")
5292 (set_attr "length" "4,8")])
5294 (define_split
5295 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5296 (compare:CC
5297 (zero_extend:SI
5298 (subreg:QI
5299 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5300 (match_operand:SI 2 "const_int_operand" "")) 0))
5301 (const_int 0)))
5302 (set (match_operand:SI 0 "gpc_reg_operand" "")
5303 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5304 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5305 [(set (match_dup 0)
5306 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5307 (set (match_dup 3)
5308 (compare:CC (match_dup 0)
5309 (const_int 0)))]
5310 "")
5312 (define_insn ""
5313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5314 (zero_extend:SI
5315 (subreg:HI
5316 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5317 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5318 "includes_rshift_p (operands[2], GEN_INT (65535))"
5319 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5321 (define_insn ""
5322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5323 (compare:CC
5324 (zero_extend:SI
5325 (subreg:HI
5326 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5327 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5328 (const_int 0)))
5329 (clobber (match_scratch:SI 3 "=r,r"))]
5330 "includes_rshift_p (operands[2], GEN_INT (65535))"
5331 "@
5332 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5333 #"
5334 [(set_attr "type" "delayed_compare")
5335 (set_attr "length" "4,8")])
5337 (define_split
5338 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5339 (compare:CC
5340 (zero_extend:SI
5341 (subreg:HI
5342 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5343 (match_operand:SI 2 "const_int_operand" "")) 0))
5344 (const_int 0)))
5345 (clobber (match_scratch:SI 3 ""))]
5346 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5347 [(set (match_dup 3)
5348 (zero_extend:SI (subreg:HI
5349 (lshiftrt:SI (match_dup 1)
5350 (match_dup 2)) 0)))
5351 (set (match_dup 0)
5352 (compare:CC (match_dup 3)
5353 (const_int 0)))]
5354 "")
5356 (define_insn ""
5357 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5358 (compare:CC
5359 (zero_extend:SI
5360 (subreg:HI
5361 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5362 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5363 (const_int 0)))
5364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5365 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5366 "includes_rshift_p (operands[2], GEN_INT (65535))"
5367 "@
5368 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5369 #"
5370 [(set_attr "type" "delayed_compare")
5371 (set_attr "length" "4,8")])
5373 (define_split
5374 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5375 (compare:CC
5376 (zero_extend:SI
5377 (subreg:HI
5378 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5379 (match_operand:SI 2 "const_int_operand" "")) 0))
5380 (const_int 0)))
5381 (set (match_operand:SI 0 "gpc_reg_operand" "")
5382 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5383 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5384 [(set (match_dup 0)
5385 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5386 (set (match_dup 3)
5387 (compare:CC (match_dup 0)
5388 (const_int 0)))]
5389 "")
5391 (define_insn ""
5392 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5393 (const_int 1)
5394 (match_operand:SI 1 "gpc_reg_operand" "r"))
5395 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5396 (const_int 31)))]
5397 "TARGET_POWER"
5398 "rrib %0,%1,%2")
5400 (define_insn ""
5401 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5402 (const_int 1)
5403 (match_operand:SI 1 "gpc_reg_operand" "r"))
5404 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5405 (const_int 31)))]
5406 "TARGET_POWER"
5407 "rrib %0,%1,%2")
5409 (define_insn ""
5410 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5411 (const_int 1)
5412 (match_operand:SI 1 "gpc_reg_operand" "r"))
5413 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5414 (const_int 1)
5415 (const_int 0)))]
5416 "TARGET_POWER"
5417 "rrib %0,%1,%2")
5419 (define_expand "ashrsi3"
5420 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5421 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5422 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5423 ""
5424 "
5425 {
5426 if (TARGET_POWER)
5427 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5428 else
5429 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5430 DONE;
5431 }")
5433 (define_insn "ashrsi3_power"
5434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5435 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5436 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5437 (clobber (match_scratch:SI 3 "=q,X"))]
5438 "TARGET_POWER"
5439 "@
5440 srea %0,%1,%2
5441 {srai|srawi} %0,%1,%h2"
5442 [(set_attr "type" "shift")])
5444 (define_insn "ashrsi3_no_power"
5445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5446 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5447 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5448 "! TARGET_POWER"
5449 "@
5450 {sra|sraw} %0,%1,%2
5451 {srai|srawi} %0,%1,%h2"
5452 [(set_attr "type" "var_shift_rotate,shift")])
5454 (define_insn "*ashrsi3_64"
5455 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5456 (sign_extend:DI
5457 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5458 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5459 "TARGET_POWERPC64"
5460 "@
5461 {sra|sraw} %0,%1,%2
5462 {srai|srawi} %0,%1,%h2"
5463 [(set_attr "type" "var_shift_rotate,shift")])
5465 (define_insn ""
5466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5467 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5468 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5469 (const_int 0)))
5470 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5471 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5472 "TARGET_POWER"
5473 "@
5474 srea. %3,%1,%2
5475 {srai.|srawi.} %3,%1,%h2
5476 #
5477 #"
5478 [(set_attr "type" "delayed_compare")
5479 (set_attr "length" "4,4,8,8")])
5481 (define_split
5482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5483 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5484 (match_operand:SI 2 "reg_or_cint_operand" ""))
5485 (const_int 0)))
5486 (clobber (match_scratch:SI 3 ""))
5487 (clobber (match_scratch:SI 4 ""))]
5488 "TARGET_POWER && reload_completed"
5489 [(parallel [(set (match_dup 3)
5490 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5491 (clobber (match_dup 4))])
5492 (set (match_dup 0)
5493 (compare:CC (match_dup 3)
5494 (const_int 0)))]
5495 "")
5497 (define_insn ""
5498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5499 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5500 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5501 (const_int 0)))
5502 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5503 "! TARGET_POWER"
5504 "@
5505 {sra.|sraw.} %3,%1,%2
5506 {srai.|srawi.} %3,%1,%h2
5507 #
5508 #"
5509 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5510 (set_attr "length" "4,4,8,8")])
5512 (define_split
5513 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5514 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5515 (match_operand:SI 2 "reg_or_cint_operand" ""))
5516 (const_int 0)))
5517 (clobber (match_scratch:SI 3 ""))]
5518 "! TARGET_POWER && reload_completed"
5519 [(set (match_dup 3)
5520 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5521 (set (match_dup 0)
5522 (compare:CC (match_dup 3)
5523 (const_int 0)))]
5524 "")
5526 (define_insn ""
5527 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5528 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5529 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5530 (const_int 0)))
5531 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5532 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5533 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5534 "TARGET_POWER"
5535 "@
5536 srea. %0,%1,%2
5537 {srai.|srawi.} %0,%1,%h2
5538 #
5539 #"
5540 [(set_attr "type" "delayed_compare")
5541 (set_attr "length" "4,4,8,8")])
5543 (define_split
5544 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5545 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5546 (match_operand:SI 2 "reg_or_cint_operand" ""))
5547 (const_int 0)))
5548 (set (match_operand:SI 0 "gpc_reg_operand" "")
5549 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5550 (clobber (match_scratch:SI 4 ""))]
5551 "TARGET_POWER && reload_completed"
5552 [(parallel [(set (match_dup 0)
5553 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5554 (clobber (match_dup 4))])
5555 (set (match_dup 3)
5556 (compare:CC (match_dup 0)
5557 (const_int 0)))]
5558 "")
5560 (define_insn ""
5561 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5562 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5563 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5564 (const_int 0)))
5565 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5566 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5567 "! TARGET_POWER"
5568 "@
5569 {sra.|sraw.} %0,%1,%2
5570 {srai.|srawi.} %0,%1,%h2
5571 #
5572 #"
5573 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5574 (set_attr "length" "4,4,8,8")])
5575 \f
5576 ;; Builtins to replace a division to generate FRE reciprocal estimate
5577 ;; instructions and the necessary fixup instructions
5578 (define_expand "recip<mode>3"
5579 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5580 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5581 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5582 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5583 {
5584 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5585 DONE;
5586 })
5588 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5589 ;; hardware division. This is only done before register allocation and with
5590 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5591 (define_split
5592 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5593 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5594 (match_operand 2 "gpc_reg_operand" "")))]
5595 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5596 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5597 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5598 [(const_int 0)]
5599 {
5600 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5601 DONE;
5602 })
5604 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5605 ;; appropriate fixup.
5606 (define_expand "rsqrt<mode>2"
5607 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5608 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5609 "RS6000_RECIP_HAVE_RSQRT_P (<MODE>mode)"
5610 {
5611 rs6000_emit_swrsqrt (operands[0], operands[1]);
5612 DONE;
5613 })
5614 \f
5615 (define_split
5616 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5617 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5618 (match_operand:SI 2 "reg_or_cint_operand" ""))
5619 (const_int 0)))
5620 (set (match_operand:SI 0 "gpc_reg_operand" "")
5621 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5622 "! TARGET_POWER && reload_completed"
5623 [(set (match_dup 0)
5624 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5625 (set (match_dup 3)
5626 (compare:CC (match_dup 0)
5627 (const_int 0)))]
5628 "")
5630 ;; Floating-point insns, excluding normal data motion.
5631 ;;
5632 ;; PowerPC has a full set of single-precision floating point instructions.
5633 ;;
5634 ;; For the POWER architecture, we pretend that we have both SFmode and
5635 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5636 ;; The only conversions we will do will be when storing to memory. In that
5637 ;; case, we will use the "frsp" instruction before storing.
5638 ;;
5639 ;; Note that when we store into a single-precision memory location, we need to
5640 ;; use the frsp insn first. If the register being stored isn't dead, we
5641 ;; need a scratch register for the frsp. But this is difficult when the store
5642 ;; is done by reload. It is not incorrect to do the frsp on the register in
5643 ;; this case, we just lose precision that we would have otherwise gotten but
5644 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5646 (define_expand "extendsfdf2"
5647 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5648 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5649 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5650 "")
5652 (define_insn_and_split "*extendsfdf2_fpr"
5653 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5654 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5655 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5656 "@
5657 #
5658 fmr %0,%1
5659 lfs%U1%X1 %0,%1"
5660 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5661 [(const_int 0)]
5662 {
5663 emit_note (NOTE_INSN_DELETED);
5664 DONE;
5665 }
5666 [(set_attr "type" "fp,fp,fpload")])
5668 (define_expand "truncdfsf2"
5669 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5670 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5671 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5672 "")
5674 (define_insn "*truncdfsf2_fpr"
5675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5676 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5677 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5678 "frsp %0,%1"
5679 [(set_attr "type" "fp")])
5681 (define_insn "aux_truncdfsf2"
5682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5683 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5684 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5685 "frsp %0,%1"
5686 [(set_attr "type" "fp")])
5688 (define_expand "negsf2"
5689 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5690 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5691 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5692 "")
5694 (define_insn "*negsf2"
5695 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5696 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5697 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5698 "fneg %0,%1"
5699 [(set_attr "type" "fp")])
5701 (define_expand "abssf2"
5702 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5703 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5704 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5705 "")
5707 (define_insn "*abssf2"
5708 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5709 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5710 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5711 "fabs %0,%1"
5712 [(set_attr "type" "fp")])
5714 (define_insn ""
5715 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5716 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5717 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5718 "fnabs %0,%1"
5719 [(set_attr "type" "fp")])
5721 (define_expand "addsf3"
5722 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5723 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5724 (match_operand:SF 2 "gpc_reg_operand" "")))]
5725 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5726 "")
5728 (define_insn ""
5729 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5730 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5731 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5732 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5733 "fadds %0,%1,%2"
5734 [(set_attr "type" "fp")
5735 (set_attr "fp_type" "fp_addsub_s")])
5737 (define_insn ""
5738 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5739 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5740 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5741 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5742 "{fa|fadd} %0,%1,%2"
5743 [(set_attr "type" "fp")])
5745 (define_expand "subsf3"
5746 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5747 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5748 (match_operand:SF 2 "gpc_reg_operand" "")))]
5749 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5750 "")
5752 (define_insn ""
5753 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5754 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5755 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5756 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5757 "fsubs %0,%1,%2"
5758 [(set_attr "type" "fp")
5759 (set_attr "fp_type" "fp_addsub_s")])
5761 (define_insn ""
5762 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5763 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5764 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5765 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5766 "{fs|fsub} %0,%1,%2"
5767 [(set_attr "type" "fp")])
5769 (define_expand "mulsf3"
5770 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5771 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5772 (match_operand:SF 2 "gpc_reg_operand" "")))]
5773 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5774 "")
5776 (define_insn ""
5777 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5778 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5779 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5780 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5781 "fmuls %0,%1,%2"
5782 [(set_attr "type" "fp")
5783 (set_attr "fp_type" "fp_mul_s")])
5785 (define_insn ""
5786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5787 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5788 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5789 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5790 "{fm|fmul} %0,%1,%2"
5791 [(set_attr "type" "dmul")])
5793 (define_expand "divsf3"
5794 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5795 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5796 (match_operand:SF 2 "gpc_reg_operand" "")))]
5797 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5798 "")
5800 (define_insn ""
5801 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5802 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5803 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5804 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5805 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5806 "fdivs %0,%1,%2"
5807 [(set_attr "type" "sdiv")])
5809 (define_insn ""
5810 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5811 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5812 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5813 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5814 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5815 "{fd|fdiv} %0,%1,%2"
5816 [(set_attr "type" "ddiv")])
5818 (define_insn "fres"
5819 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5820 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5821 "TARGET_FRES"
5822 "fres %0,%1"
5823 [(set_attr "type" "fp")])
5825 (define_insn "*fmaddsf4_powerpc"
5826 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5827 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5828 (match_operand:SF 2 "gpc_reg_operand" "f"))
5829 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5830 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5831 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5832 "fmadds %0,%1,%2,%3"
5833 [(set_attr "type" "fp")
5834 (set_attr "fp_type" "fp_maddsub_s")])
5836 (define_insn "*fmaddsf4_power"
5837 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5838 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5839 (match_operand:SF 2 "gpc_reg_operand" "f"))
5840 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5841 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5842 "{fma|fmadd} %0,%1,%2,%3"
5843 [(set_attr "type" "dmul")])
5845 (define_insn "*fmsubsf4_powerpc"
5846 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5847 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5848 (match_operand:SF 2 "gpc_reg_operand" "f"))
5849 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5850 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5851 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5852 "fmsubs %0,%1,%2,%3"
5853 [(set_attr "type" "fp")
5854 (set_attr "fp_type" "fp_maddsub_s")])
5856 (define_insn "*fmsubsf4_power"
5857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5858 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5859 (match_operand:SF 2 "gpc_reg_operand" "f"))
5860 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5861 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5862 "{fms|fmsub} %0,%1,%2,%3"
5863 [(set_attr "type" "dmul")])
5865 (define_insn "*fnmaddsf4_powerpc_1"
5866 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5867 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5868 (match_operand:SF 2 "gpc_reg_operand" "f"))
5869 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5870 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5871 && TARGET_SINGLE_FLOAT"
5872 "fnmadds %0,%1,%2,%3"
5873 [(set_attr "type" "fp")
5874 (set_attr "fp_type" "fp_maddsub_s")])
5876 (define_insn "*fnmaddsf4_powerpc_2"
5877 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5878 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5879 (match_operand:SF 2 "gpc_reg_operand" "f"))
5880 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5881 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5882 && ! HONOR_SIGNED_ZEROS (SFmode)"
5883 "fnmadds %0,%1,%2,%3"
5884 [(set_attr "type" "fp")
5885 (set_attr "fp_type" "fp_maddsub_s")])
5887 (define_insn "*fnmaddsf4_power_1"
5888 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5889 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5890 (match_operand:SF 2 "gpc_reg_operand" "f"))
5891 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5892 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5893 "{fnma|fnmadd} %0,%1,%2,%3"
5894 [(set_attr "type" "dmul")])
5896 (define_insn "*fnmaddsf4_power_2"
5897 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5898 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5899 (match_operand:SF 2 "gpc_reg_operand" "f"))
5900 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5901 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5902 && ! HONOR_SIGNED_ZEROS (SFmode)"
5903 "{fnma|fnmadd} %0,%1,%2,%3"
5904 [(set_attr "type" "dmul")])
5906 (define_insn "*fnmsubsf4_powerpc_1"
5907 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5908 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5909 (match_operand:SF 2 "gpc_reg_operand" "f"))
5910 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5911 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5912 && TARGET_SINGLE_FLOAT"
5913 "fnmsubs %0,%1,%2,%3"
5914 [(set_attr "type" "fp")
5915 (set_attr "fp_type" "fp_maddsub_s")])
5917 (define_insn "*fnmsubsf4_powerpc_2"
5918 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5919 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5920 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5921 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5922 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5923 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5924 "fnmsubs %0,%1,%2,%3"
5925 [(set_attr "type" "fp")
5926 (set_attr "fp_type" "fp_maddsub_s")])
5928 (define_insn "*fnmsubsf4_power_1"
5929 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5930 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5931 (match_operand:SF 2 "gpc_reg_operand" "f"))
5932 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5933 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5934 "{fnms|fnmsub} %0,%1,%2,%3"
5935 [(set_attr "type" "dmul")])
5937 (define_insn "*fnmsubsf4_power_2"
5938 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5939 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5940 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5941 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5942 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5943 && ! HONOR_SIGNED_ZEROS (SFmode)"
5944 "{fnms|fnmsub} %0,%1,%2,%3"
5945 [(set_attr "type" "dmul")])
5947 (define_expand "sqrtsf2"
5948 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5949 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5950 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5951 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5952 && !TARGET_SIMPLE_FPU"
5953 "")
5955 (define_insn ""
5956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5957 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5958 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5959 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5960 "fsqrts %0,%1"
5961 [(set_attr "type" "ssqrt")])
5963 (define_insn ""
5964 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5965 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5966 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5967 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5968 "fsqrt %0,%1"
5969 [(set_attr "type" "dsqrt")])
5971 (define_insn "*rsqrtsf_internal1"
5972 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5973 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5974 UNSPEC_RSQRT))]
5975 "TARGET_FRSQRTES"
5976 "frsqrtes %0,%1"
5977 [(set_attr "type" "fp")])
5979 (define_expand "copysignsf3"
5980 [(set (match_dup 3)
5981 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5982 (set (match_dup 4)
5983 (neg:SF (abs:SF (match_dup 1))))
5984 (set (match_operand:SF 0 "gpc_reg_operand" "")
5985 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5986 (match_dup 5))
5987 (match_dup 3)
5988 (match_dup 4)))]
5989 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5990 && ((TARGET_PPC_GFXOPT
5991 && !HONOR_NANS (SFmode)
5992 && !HONOR_SIGNED_ZEROS (SFmode))
5993 || VECTOR_UNIT_VSX_P (DFmode))"
5994 {
5995 if (VECTOR_UNIT_VSX_P (DFmode))
5996 {
5997 emit_insn (gen_vsx_copysignsf3 (operands[0], operands[1], operands[2],
5998 CONST0_RTX (SFmode)));
5999 DONE;
6000 }
6001 operands[3] = gen_reg_rtx (SFmode);
6002 operands[4] = gen_reg_rtx (SFmode);
6003 operands[5] = CONST0_RTX (SFmode);
6004 })
6006 (define_expand "copysigndf3"
6007 [(set (match_dup 3)
6008 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
6009 (set (match_dup 4)
6010 (neg:DF (abs:DF (match_dup 1))))
6011 (set (match_operand:DF 0 "gpc_reg_operand" "")
6012 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
6013 (match_dup 5))
6014 (match_dup 3)
6015 (match_dup 4)))]
6016 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6017 && ((TARGET_PPC_GFXOPT
6018 && !HONOR_NANS (DFmode)
6019 && !HONOR_SIGNED_ZEROS (DFmode))
6020 || VECTOR_UNIT_VSX_P (DFmode))"
6021 {
6022 if (VECTOR_UNIT_VSX_P (DFmode))
6023 {
6024 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
6025 operands[2], CONST0_RTX (DFmode)));
6026 DONE;
6027 }
6028 operands[3] = gen_reg_rtx (DFmode);
6029 operands[4] = gen_reg_rtx (DFmode);
6030 operands[5] = CONST0_RTX (DFmode);
6031 })
6033 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6034 ;; fsel instruction and some auxiliary computations. Then we just have a
6035 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6036 ;; combine.
6037 (define_expand "smaxsf3"
6038 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6039 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6040 (match_operand:SF 2 "gpc_reg_operand" ""))
6041 (match_dup 1)
6042 (match_dup 2)))]
6043 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6044 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6045 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6047 (define_expand "sminsf3"
6048 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6049 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6050 (match_operand:SF 2 "gpc_reg_operand" ""))
6051 (match_dup 2)
6052 (match_dup 1)))]
6053 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6054 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6055 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6057 (define_split
6058 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6059 (match_operator:SF 3 "min_max_operator"
6060 [(match_operand:SF 1 "gpc_reg_operand" "")
6061 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6062 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6063 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6064 [(const_int 0)]
6065 "
6066 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6067 operands[1], operands[2]);
6068 DONE;
6069 }")
6071 (define_expand "mov<mode>cc"
6072 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6073 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6074 (match_operand:GPR 2 "gpc_reg_operand" "")
6075 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6076 "TARGET_ISEL<sel>"
6077 "
6078 {
6079 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6080 DONE;
6081 else
6082 FAIL;
6083 }")
6085 ;; We use the BASE_REGS for the isel input operands because, if rA is
6086 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6087 ;; because we may switch the operands and rB may end up being rA.
6088 ;;
6089 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6090 ;; leave out the mode in operand 4 and use one pattern, but reload can
6091 ;; change the mode underneath our feet and then gets confused trying
6092 ;; to reload the value.
6093 (define_insn "isel_signed_<mode>"
6094 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6095 (if_then_else:GPR
6096 (match_operator 1 "scc_comparison_operator"
6097 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6098 (const_int 0)])
6099 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6100 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6101 "TARGET_ISEL<sel>"
6102 "*
6103 { return output_isel (operands); }"
6104 [(set_attr "type" "isel")
6105 (set_attr "length" "4")])
6107 (define_insn "isel_unsigned_<mode>"
6108 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6109 (if_then_else:GPR
6110 (match_operator 1 "scc_comparison_operator"
6111 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6112 (const_int 0)])
6113 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6114 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6115 "TARGET_ISEL<sel>"
6116 "*
6117 { return output_isel (operands); }"
6118 [(set_attr "type" "isel")
6119 (set_attr "length" "4")])
6121 (define_expand "movsfcc"
6122 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6123 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6124 (match_operand:SF 2 "gpc_reg_operand" "")
6125 (match_operand:SF 3 "gpc_reg_operand" "")))]
6126 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6127 "
6128 {
6129 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6130 DONE;
6131 else
6132 FAIL;
6133 }")
6135 (define_insn "*fselsfsf4"
6136 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6137 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6138 (match_operand:SF 4 "zero_fp_constant" "F"))
6139 (match_operand:SF 2 "gpc_reg_operand" "f")
6140 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6141 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6142 "fsel %0,%1,%2,%3"
6143 [(set_attr "type" "fp")])
6145 (define_insn "*fseldfsf4"
6146 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6147 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6148 (match_operand:DF 4 "zero_fp_constant" "F"))
6149 (match_operand:SF 2 "gpc_reg_operand" "f")
6150 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6151 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6152 "fsel %0,%1,%2,%3"
6153 [(set_attr "type" "fp")])
6155 (define_expand "negdf2"
6156 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6157 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6158 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6159 "")
6161 (define_insn "*negdf2_fpr"
6162 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6163 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6164 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6165 && !VECTOR_UNIT_VSX_P (DFmode)"
6166 "fneg %0,%1"
6167 [(set_attr "type" "fp")])
6169 (define_expand "absdf2"
6170 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6171 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6172 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6173 "")
6175 (define_insn "*absdf2_fpr"
6176 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6177 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6178 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6179 && !VECTOR_UNIT_VSX_P (DFmode)"
6180 "fabs %0,%1"
6181 [(set_attr "type" "fp")])
6183 (define_insn "*nabsdf2_fpr"
6184 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6185 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6186 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6187 && !VECTOR_UNIT_VSX_P (DFmode)"
6188 "fnabs %0,%1"
6189 [(set_attr "type" "fp")])
6191 (define_expand "adddf3"
6192 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6193 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6194 (match_operand:DF 2 "gpc_reg_operand" "")))]
6195 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6196 "")
6198 (define_insn "*adddf3_fpr"
6199 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6200 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6201 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6202 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6203 && !VECTOR_UNIT_VSX_P (DFmode)"
6204 "{fa|fadd} %0,%1,%2"
6205 [(set_attr "type" "fp")
6206 (set_attr "fp_type" "fp_addsub_d")])
6208 (define_expand "subdf3"
6209 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6210 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6211 (match_operand:DF 2 "gpc_reg_operand" "")))]
6212 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6213 "")
6215 (define_insn "*subdf3_fpr"
6216 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6217 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6218 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6219 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6220 && !VECTOR_UNIT_VSX_P (DFmode)"
6221 "{fs|fsub} %0,%1,%2"
6222 [(set_attr "type" "fp")
6223 (set_attr "fp_type" "fp_addsub_d")])
6225 (define_expand "muldf3"
6226 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6227 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6228 (match_operand:DF 2 "gpc_reg_operand" "")))]
6229 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6230 "")
6232 (define_insn "*muldf3_fpr"
6233 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6234 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6235 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6236 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6237 && !VECTOR_UNIT_VSX_P (DFmode)"
6238 "{fm|fmul} %0,%1,%2"
6239 [(set_attr "type" "dmul")
6240 (set_attr "fp_type" "fp_mul_d")])
6242 (define_expand "divdf3"
6243 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6244 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6245 (match_operand:DF 2 "gpc_reg_operand" "")))]
6246 "TARGET_HARD_FLOAT
6247 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6248 && !TARGET_SIMPLE_FPU"
6249 "")
6251 (define_insn "*divdf3_fpr"
6252 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6253 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6254 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6255 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6256 && !VECTOR_UNIT_VSX_P (DFmode)"
6257 "{fd|fdiv} %0,%1,%2"
6258 [(set_attr "type" "ddiv")])
6260 (define_insn "*fred_fpr"
6261 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6262 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6263 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6264 "fre %0,%1"
6265 [(set_attr "type" "fp")])
6267 (define_insn "*rsqrtdf_internal1"
6268 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6269 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6270 UNSPEC_RSQRT))]
6271 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6272 "frsqrte %0,%1"
6273 [(set_attr "type" "fp")])
6275 (define_insn "*fmadddf4_fpr"
6276 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6277 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6278 (match_operand:DF 2 "gpc_reg_operand" "d"))
6279 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6280 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6281 && VECTOR_UNIT_NONE_P (DFmode)"
6282 "{fma|fmadd} %0,%1,%2,%3"
6283 [(set_attr "type" "dmul")
6284 (set_attr "fp_type" "fp_maddsub_d")])
6286 (define_insn "*fmsubdf4_fpr"
6287 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6288 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6289 (match_operand:DF 2 "gpc_reg_operand" "d"))
6290 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6291 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6292 && VECTOR_UNIT_NONE_P (DFmode)"
6293 "{fms|fmsub} %0,%1,%2,%3"
6294 [(set_attr "type" "dmul")
6295 (set_attr "fp_type" "fp_maddsub_d")])
6297 (define_insn "*fnmadddf4_fpr_1"
6298 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6299 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6300 (match_operand:DF 2 "gpc_reg_operand" "d"))
6301 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6302 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6303 && VECTOR_UNIT_NONE_P (DFmode)"
6304 "{fnma|fnmadd} %0,%1,%2,%3"
6305 [(set_attr "type" "dmul")
6306 (set_attr "fp_type" "fp_maddsub_d")])
6308 (define_insn "*fnmadddf4_fpr_2"
6309 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6310 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6311 (match_operand:DF 2 "gpc_reg_operand" "d"))
6312 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6313 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6314 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6315 "{fnma|fnmadd} %0,%1,%2,%3"
6316 [(set_attr "type" "dmul")
6317 (set_attr "fp_type" "fp_maddsub_d")])
6319 (define_insn "*fnmsubdf4_fpr_1"
6320 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6321 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6322 (match_operand:DF 2 "gpc_reg_operand" "d"))
6323 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6324 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6325 && VECTOR_UNIT_NONE_P (DFmode)"
6326 "{fnms|fnmsub} %0,%1,%2,%3"
6327 [(set_attr "type" "dmul")
6328 (set_attr "fp_type" "fp_maddsub_d")])
6330 (define_insn "*fnmsubdf4_fpr_2"
6331 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6332 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6333 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6334 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6335 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6336 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6337 "{fnms|fnmsub} %0,%1,%2,%3"
6338 [(set_attr "type" "dmul")
6339 (set_attr "fp_type" "fp_maddsub_d")])
6341 (define_expand "sqrtdf2"
6342 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6343 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6344 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6345 && TARGET_DOUBLE_FLOAT"
6346 "")
6348 (define_insn "*sqrtdf2_fpr"
6349 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6350 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6351 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6352 && TARGET_DOUBLE_FLOAT
6353 && !VECTOR_UNIT_VSX_P (DFmode)"
6354 "fsqrt %0,%1"
6355 [(set_attr "type" "dsqrt")])
6357 ;; The conditional move instructions allow us to perform max and min
6358 ;; operations even when
6360 (define_expand "smaxdf3"
6361 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6362 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6363 (match_operand:DF 2 "gpc_reg_operand" ""))
6364 (match_dup 1)
6365 (match_dup 2)))]
6366 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6367 && !flag_trapping_math"
6368 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6370 (define_expand "smindf3"
6371 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6372 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6373 (match_operand:DF 2 "gpc_reg_operand" ""))
6374 (match_dup 2)
6375 (match_dup 1)))]
6376 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6377 && !flag_trapping_math"
6378 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6380 (define_split
6381 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6382 (match_operator:DF 3 "min_max_operator"
6383 [(match_operand:DF 1 "gpc_reg_operand" "")
6384 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6385 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6386 && !flag_trapping_math"
6387 [(const_int 0)]
6388 "
6389 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6390 operands[1], operands[2]);
6391 DONE;
6392 }")
6394 (define_expand "movdfcc"
6395 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6396 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6397 (match_operand:DF 2 "gpc_reg_operand" "")
6398 (match_operand:DF 3 "gpc_reg_operand" "")))]
6399 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6400 "
6401 {
6402 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6403 DONE;
6404 else
6405 FAIL;
6406 }")
6408 (define_insn "*fseldfdf4"
6409 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6410 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6411 (match_operand:DF 4 "zero_fp_constant" "F"))
6412 (match_operand:DF 2 "gpc_reg_operand" "d")
6413 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6414 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6415 "fsel %0,%1,%2,%3"
6416 [(set_attr "type" "fp")])
6418 (define_insn "*fselsfdf4"
6419 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6420 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6421 (match_operand:SF 4 "zero_fp_constant" "F"))
6422 (match_operand:DF 2 "gpc_reg_operand" "d")
6423 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6424 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6425 "fsel %0,%1,%2,%3"
6426 [(set_attr "type" "fp")])
6427 \f
6428 ;; Conversions to and from floating-point.
6430 (define_expand "fixuns_truncsfsi2"
6431 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6432 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6433 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6434 "")
6436 (define_expand "fix_truncsfsi2"
6437 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6438 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6439 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6440 "")
6442 (define_expand "fixuns_truncdfsi2"
6443 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6444 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6445 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6446 "")
6448 (define_expand "fixuns_truncdfdi2"
6449 [(set (match_operand:DI 0 "register_operand" "")
6450 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6451 "TARGET_HARD_FLOAT && TARGET_VSX"
6452 "")
6454 ; For each of these conversions, there is a define_expand, a define_insn
6455 ; with a '#' template, and a define_split (with C code). The idea is
6456 ; to allow constant folding with the template of the define_insn,
6457 ; then to have the insns split later (between sched1 and final).
6459 (define_expand "floatsidf2"
6460 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6461 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6462 (use (match_dup 2))
6463 (use (match_dup 3))
6464 (clobber (match_dup 4))
6465 (clobber (match_dup 5))
6466 (clobber (match_dup 6))])]
6467 "TARGET_HARD_FLOAT
6468 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6469 "
6470 {
6471 if (TARGET_E500_DOUBLE)
6472 {
6473 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6474 DONE;
6475 }
6476 if (TARGET_POWERPC64)
6477 {
6478 rtx x = convert_to_mode (DImode, operands[1], 0);
6479 emit_insn (gen_floatdidf2 (operands[0], x));
6480 DONE;
6481 }
6483 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6484 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6485 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6486 operands[5] = gen_reg_rtx (DFmode);
6487 operands[6] = gen_reg_rtx (SImode);
6488 }")
6490 (define_insn_and_split "*floatsidf2_internal"
6491 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6492 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6493 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6494 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6495 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6496 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6497 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6498 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6499 "#"
6500 ""
6501 [(pc)]
6502 "
6503 {
6504 rtx lowword, highword;
6505 gcc_assert (MEM_P (operands[4]));
6506 highword = adjust_address (operands[4], SImode, 0);
6507 lowword = adjust_address (operands[4], SImode, 4);
6508 if (! WORDS_BIG_ENDIAN)
6509 {
6510 rtx tmp;
6511 tmp = highword; highword = lowword; lowword = tmp;
6512 }
6514 emit_insn (gen_xorsi3 (operands[6], operands[1],
6515 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6516 emit_move_insn (lowword, operands[6]);
6517 emit_move_insn (highword, operands[2]);
6518 emit_move_insn (operands[5], operands[4]);
6519 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6520 DONE;
6521 }"
6522 [(set_attr "length" "24")])
6524 (define_expand "floatunssisf2"
6525 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6526 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6527 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6528 "")
6530 (define_expand "floatunssidf2"
6531 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6532 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6533 (use (match_dup 2))
6534 (use (match_dup 3))
6535 (clobber (match_dup 4))
6536 (clobber (match_dup 5))])]
6537 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6538 "
6539 {
6540 if (TARGET_E500_DOUBLE)
6541 {
6542 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6543 DONE;
6544 }
6545 if (TARGET_POWERPC64)
6546 {
6547 rtx x = convert_to_mode (DImode, operands[1], 1);
6548 emit_insn (gen_floatdidf2 (operands[0], x));
6549 DONE;
6550 }
6552 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6553 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6554 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6555 operands[5] = gen_reg_rtx (DFmode);
6556 }")
6558 (define_insn_and_split "*floatunssidf2_internal"
6559 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6560 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6561 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6562 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6563 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6564 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6565 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6566 "#"
6567 ""
6568 [(pc)]
6569 "
6570 {
6571 rtx lowword, highword;
6572 gcc_assert (MEM_P (operands[4]));
6573 highword = adjust_address (operands[4], SImode, 0);
6574 lowword = adjust_address (operands[4], SImode, 4);
6575 if (! WORDS_BIG_ENDIAN)
6576 {
6577 rtx tmp;
6578 tmp = highword; highword = lowword; lowword = tmp;
6579 }
6581 emit_move_insn (lowword, operands[1]);
6582 emit_move_insn (highword, operands[2]);
6583 emit_move_insn (operands[5], operands[4]);
6584 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6585 DONE;
6586 }"
6587 [(set_attr "length" "20")])
6589 (define_expand "fix_truncdfsi2"
6590 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6591 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6592 (clobber (match_dup 2))
6593 (clobber (match_dup 3))])]
6594 "(TARGET_POWER2 || TARGET_POWERPC)
6595 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6596 "
6597 {
6598 if (TARGET_E500_DOUBLE)
6599 {
6600 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6601 DONE;
6602 }
6603 operands[2] = gen_reg_rtx (DImode);
6604 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6605 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6606 {
6607 operands[3] = gen_reg_rtx (DImode);
6608 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6609 operands[2], operands[3]));
6610 DONE;
6611 }
6612 if (TARGET_PPC_GFXOPT)
6613 {
6614 rtx orig_dest = operands[0];
6615 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6616 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6617 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6618 operands[2]));
6619 if (operands[0] != orig_dest)
6620 emit_move_insn (orig_dest, operands[0]);
6621 DONE;
6622 }
6623 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6624 }")
6626 (define_insn_and_split "*fix_truncdfsi2_internal"
6627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6628 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6629 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6630 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6631 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6632 && TARGET_DOUBLE_FLOAT"
6633 "#"
6634 ""
6635 [(pc)]
6636 "
6637 {
6638 rtx lowword;
6639 gcc_assert (MEM_P (operands[3]));
6640 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6642 emit_insn (gen_fctiwz (operands[2], operands[1]));
6643 emit_move_insn (operands[3], operands[2]);
6644 emit_move_insn (operands[0], lowword);
6645 DONE;
6646 }"
6647 [(set_attr "length" "16")])
6649 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6650 [(set (match_operand:SI 0 "memory_operand" "=Z")
6651 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6652 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6653 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6654 && TARGET_DOUBLE_FLOAT
6655 && TARGET_PPC_GFXOPT"
6656 "#"
6657 "&& 1"
6658 [(pc)]
6659 "
6660 {
6661 emit_insn (gen_fctiwz (operands[2], operands[1]));
6662 emit_insn (gen_stfiwx (operands[0], operands[2]));
6663 DONE;
6664 }"
6665 [(set_attr "length" "16")])
6667 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6669 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6670 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6671 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6672 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6673 && TARGET_DOUBLE_FLOAT"
6674 "#"
6675 "&& 1"
6676 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6677 (set (match_dup 3) (match_dup 2))
6678 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6679 ""
6680 [(set_attr "length" "12")])
6682 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6683 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6684 ; because the first makes it clear that operand 0 is not live
6685 ; before the instruction.
6686 (define_insn "fctiwz"
6687 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6688 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6689 UNSPEC_FCTIWZ))]
6690 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6691 && TARGET_DOUBLE_FLOAT"
6692 "{fcirz|fctiwz} %0,%1"
6693 [(set_attr "type" "fp")])
6695 (define_expand "btruncdf2"
6696 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6697 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6698 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6699 "")
6701 (define_insn "*btruncdf2_fpr"
6702 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6703 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6704 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6705 && !VECTOR_UNIT_VSX_P (DFmode)"
6706 "friz %0,%1"
6707 [(set_attr "type" "fp")])
6709 (define_insn "btruncsf2"
6710 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6711 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6712 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6713 "friz %0,%1"
6714 [(set_attr "type" "fp")])
6716 (define_expand "ceildf2"
6717 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6718 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6719 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6720 "")
6722 (define_insn "*ceildf2_fpr"
6723 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6724 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6725 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6726 && !VECTOR_UNIT_VSX_P (DFmode)"
6727 "frip %0,%1"
6728 [(set_attr "type" "fp")])
6730 (define_insn "ceilsf2"
6731 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6732 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6733 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6734 "frip %0,%1"
6735 [(set_attr "type" "fp")])
6737 (define_expand "floordf2"
6738 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6739 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6740 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6741 "")
6743 (define_insn "*floordf2_fpr"
6744 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6745 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6746 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6747 && !VECTOR_UNIT_VSX_P (DFmode)"
6748 "frim %0,%1"
6749 [(set_attr "type" "fp")])
6751 (define_insn "floorsf2"
6752 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6753 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6754 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6755 "frim %0,%1"
6756 [(set_attr "type" "fp")])
6758 ;; No VSX equivalent to frin
6759 (define_insn "rounddf2"
6760 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6761 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6762 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6763 "frin %0,%1"
6764 [(set_attr "type" "fp")])
6766 (define_insn "roundsf2"
6767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6768 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6769 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6770 "frin %0,%1"
6771 [(set_attr "type" "fp")])
6773 (define_expand "ftruncdf2"
6774 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6775 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6776 "VECTOR_UNIT_VSX_P (DFmode)"
6777 "")
6779 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6780 (define_insn "stfiwx"
6781 [(set (match_operand:SI 0 "memory_operand" "=Z")
6782 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6783 UNSPEC_STFIWX))]
6784 "TARGET_PPC_GFXOPT"
6785 "stfiwx %1,%y0"
6786 [(set_attr "type" "fpstore")])
6788 (define_expand "floatsisf2"
6789 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6790 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6791 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6792 "")
6794 (define_expand "floatdidf2"
6795 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6796 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6797 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6798 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6799 "")
6801 (define_insn "*floatdidf2_fpr"
6802 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6803 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6804 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6805 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6806 && !VECTOR_UNIT_VSX_P (DFmode)"
6807 "fcfid %0,%1"
6808 [(set_attr "type" "fp")])
6810 (define_expand "floatunsdidf2"
6811 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6812 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6813 "TARGET_VSX"
6814 "")
6816 (define_expand "fix_truncdfdi2"
6817 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6818 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6819 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6820 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6821 "")
6823 (define_insn "*fix_truncdfdi2_fpr"
6824 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6825 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6826 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6827 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6828 && !VECTOR_UNIT_VSX_P (DFmode)"
6829 "fctidz %0,%1"
6830 [(set_attr "type" "fp")])
6832 (define_expand "floatdisf2"
6833 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6834 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6835 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6836 "
6837 {
6838 rtx val = operands[1];
6839 if (!flag_unsafe_math_optimizations)
6840 {
6841 rtx label = gen_label_rtx ();
6842 val = gen_reg_rtx (DImode);
6843 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6844 emit_label (label);
6845 }
6846 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6847 DONE;
6848 }")
6850 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6851 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6852 ;; from double rounding.
6853 (define_insn_and_split "floatdisf2_internal1"
6854 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6855 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6856 (clobber (match_scratch:DF 2 "=d"))]
6857 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6858 "#"
6859 "&& reload_completed"
6860 [(set (match_dup 2)
6861 (float:DF (match_dup 1)))
6862 (set (match_dup 0)
6863 (float_truncate:SF (match_dup 2)))]
6864 "")
6866 ;; Twiddles bits to avoid double rounding.
6867 ;; Bits that might be truncated when converting to DFmode are replaced
6868 ;; by a bit that won't be lost at that stage, but is below the SFmode
6869 ;; rounding position.
6870 (define_expand "floatdisf2_internal2"
6871 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6872 (const_int 53)))
6873 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6874 (const_int 2047)))
6875 (clobber (scratch:CC))])
6876 (set (match_dup 3) (plus:DI (match_dup 3)
6877 (const_int 1)))
6878 (set (match_dup 0) (plus:DI (match_dup 0)
6879 (const_int 2047)))
6880 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6881 (const_int 2)))
6882 (set (match_dup 0) (ior:DI (match_dup 0)
6883 (match_dup 1)))
6884 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6885 (const_int -2048)))
6886 (clobber (scratch:CC))])
6887 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6888 (label_ref (match_operand:DI 2 "" ""))
6889 (pc)))
6890 (set (match_dup 0) (match_dup 1))]
6891 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6892 "
6893 {
6894 operands[3] = gen_reg_rtx (DImode);
6895 operands[4] = gen_reg_rtx (CCUNSmode);
6896 }")
6897 \f
6898 ;; Define the DImode operations that can be done in a small number
6899 ;; of instructions. The & constraints are to prevent the register
6900 ;; allocator from allocating registers that overlap with the inputs
6901 ;; (for example, having an input in 7,8 and an output in 6,7). We
6902 ;; also allow for the output being the same as one of the inputs.
6904 (define_insn "*adddi3_noppc64"
6905 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6906 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6907 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6908 "! TARGET_POWERPC64"
6909 "*
6910 {
6911 if (WORDS_BIG_ENDIAN)
6912 return (GET_CODE (operands[2])) != CONST_INT
6913 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6914 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6915 else
6916 return (GET_CODE (operands[2])) != CONST_INT
6917 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6918 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6919 }"
6920 [(set_attr "type" "two")
6921 (set_attr "length" "8")])
6923 (define_insn "*subdi3_noppc64"
6924 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6925 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6926 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6927 "! TARGET_POWERPC64"
6928 "*
6929 {
6930 if (WORDS_BIG_ENDIAN)
6931 return (GET_CODE (operands[1]) != CONST_INT)
6932 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6933 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6934 else
6935 return (GET_CODE (operands[1]) != CONST_INT)
6936 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6937 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6938 }"
6939 [(set_attr "type" "two")
6940 (set_attr "length" "8")])
6942 (define_insn "*negdi2_noppc64"
6943 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6944 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6945 "! TARGET_POWERPC64"
6946 "*
6947 {
6948 return (WORDS_BIG_ENDIAN)
6949 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6950 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6951 }"
6952 [(set_attr "type" "two")
6953 (set_attr "length" "8")])
6955 (define_expand "mulsidi3"
6956 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6957 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6958 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6959 "! TARGET_POWERPC64"
6960 "
6961 {
6962 if (! TARGET_POWER && ! TARGET_POWERPC)
6963 {
6964 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6965 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6966 emit_insn (gen_mull_call ());
6967 if (WORDS_BIG_ENDIAN)
6968 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6969 else
6970 {
6971 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6972 gen_rtx_REG (SImode, 3));
6973 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6974 gen_rtx_REG (SImode, 4));
6975 }
6976 DONE;
6977 }
6978 else if (TARGET_POWER)
6979 {
6980 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6981 DONE;
6982 }
6983 }")
6985 (define_insn "mulsidi3_mq"
6986 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6987 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6988 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6989 (clobber (match_scratch:SI 3 "=q"))]
6990 "TARGET_POWER"
6991 "mul %0,%1,%2\;mfmq %L0"
6992 [(set_attr "type" "imul")
6993 (set_attr "length" "8")])
6995 (define_insn "*mulsidi3_no_mq"
6996 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6997 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6998 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6999 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7000 "*
7001 {
7002 return (WORDS_BIG_ENDIAN)
7003 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7004 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7005 }"
7006 [(set_attr "type" "imul")
7007 (set_attr "length" "8")])
7009 (define_split
7010 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7011 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7012 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7013 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7014 [(set (match_dup 3)
7015 (truncate:SI
7016 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7017 (sign_extend:DI (match_dup 2)))
7018 (const_int 32))))
7019 (set (match_dup 4)
7020 (mult:SI (match_dup 1)
7021 (match_dup 2)))]
7022 "
7023 {
7024 int endian = (WORDS_BIG_ENDIAN == 0);
7025 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7026 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7027 }")
7029 (define_expand "umulsidi3"
7030 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7031 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7032 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7033 "TARGET_POWERPC && ! TARGET_POWERPC64"
7034 "
7035 {
7036 if (TARGET_POWER)
7037 {
7038 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7039 DONE;
7040 }
7041 }")
7043 (define_insn "umulsidi3_mq"
7044 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7045 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7046 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7047 (clobber (match_scratch:SI 3 "=q"))]
7048 "TARGET_POWERPC && TARGET_POWER"
7049 "*
7050 {
7051 return (WORDS_BIG_ENDIAN)
7052 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7053 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7054 }"
7055 [(set_attr "type" "imul")
7056 (set_attr "length" "8")])
7058 (define_insn "*umulsidi3_no_mq"
7059 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7060 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7061 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7062 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7063 "*
7064 {
7065 return (WORDS_BIG_ENDIAN)
7066 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7067 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7068 }"
7069 [(set_attr "type" "imul")
7070 (set_attr "length" "8")])
7072 (define_split
7073 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7074 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7075 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7076 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7077 [(set (match_dup 3)
7078 (truncate:SI
7079 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7080 (zero_extend:DI (match_dup 2)))
7081 (const_int 32))))
7082 (set (match_dup 4)
7083 (mult:SI (match_dup 1)
7084 (match_dup 2)))]
7085 "
7086 {
7087 int endian = (WORDS_BIG_ENDIAN == 0);
7088 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7089 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7090 }")
7092 (define_expand "smulsi3_highpart"
7093 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7094 (truncate:SI
7095 (lshiftrt:DI (mult:DI (sign_extend:DI
7096 (match_operand:SI 1 "gpc_reg_operand" ""))
7097 (sign_extend:DI
7098 (match_operand:SI 2 "gpc_reg_operand" "")))
7099 (const_int 32))))]
7100 ""
7101 "
7102 {
7103 if (! TARGET_POWER && ! TARGET_POWERPC)
7104 {
7105 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7106 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7107 emit_insn (gen_mulh_call ());
7108 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7109 DONE;
7110 }
7111 else if (TARGET_POWER)
7112 {
7113 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7114 DONE;
7115 }
7116 }")
7118 (define_insn "smulsi3_highpart_mq"
7119 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7120 (truncate:SI
7121 (lshiftrt:DI (mult:DI (sign_extend:DI
7122 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7123 (sign_extend:DI
7124 (match_operand:SI 2 "gpc_reg_operand" "r")))
7125 (const_int 32))))
7126 (clobber (match_scratch:SI 3 "=q"))]
7127 "TARGET_POWER"
7128 "mul %0,%1,%2"
7129 [(set_attr "type" "imul")])
7131 (define_insn "*smulsi3_highpart_no_mq"
7132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7133 (truncate:SI
7134 (lshiftrt:DI (mult:DI (sign_extend:DI
7135 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7136 (sign_extend:DI
7137 (match_operand:SI 2 "gpc_reg_operand" "r")))
7138 (const_int 32))))]
7139 "TARGET_POWERPC && ! TARGET_POWER"
7140 "mulhw %0,%1,%2"
7141 [(set_attr "type" "imul")])
7143 (define_expand "umulsi3_highpart"
7144 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7145 (truncate:SI
7146 (lshiftrt:DI (mult:DI (zero_extend:DI
7147 (match_operand:SI 1 "gpc_reg_operand" ""))
7148 (zero_extend:DI
7149 (match_operand:SI 2 "gpc_reg_operand" "")))
7150 (const_int 32))))]
7151 "TARGET_POWERPC"
7152 "
7153 {
7154 if (TARGET_POWER)
7155 {
7156 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7157 DONE;
7158 }
7159 }")
7161 (define_insn "umulsi3_highpart_mq"
7162 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7163 (truncate:SI
7164 (lshiftrt:DI (mult:DI (zero_extend:DI
7165 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7166 (zero_extend:DI
7167 (match_operand:SI 2 "gpc_reg_operand" "r")))
7168 (const_int 32))))
7169 (clobber (match_scratch:SI 3 "=q"))]
7170 "TARGET_POWERPC && TARGET_POWER"
7171 "mulhwu %0,%1,%2"
7172 [(set_attr "type" "imul")])
7174 (define_insn "*umulsi3_highpart_no_mq"
7175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7176 (truncate:SI
7177 (lshiftrt:DI (mult:DI (zero_extend:DI
7178 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7179 (zero_extend:DI
7180 (match_operand:SI 2 "gpc_reg_operand" "r")))
7181 (const_int 32))))]
7182 "TARGET_POWERPC && ! TARGET_POWER"
7183 "mulhwu %0,%1,%2"
7184 [(set_attr "type" "imul")])
7186 ;; If operands 0 and 2 are in the same register, we have a problem. But
7187 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7188 ;; why we have the strange constraints below.
7189 (define_insn "ashldi3_power"
7190 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7191 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7192 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7193 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7194 "TARGET_POWER"
7195 "@
7196 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7197 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7198 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7199 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7200 [(set_attr "length" "8")])
7202 (define_insn "lshrdi3_power"
7203 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7204 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7205 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7206 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7207 "TARGET_POWER"
7208 "@
7209 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7210 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7211 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7212 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7213 [(set_attr "length" "8")])
7215 ;; Shift by a variable amount is too complex to be worth open-coding. We
7216 ;; just handle shifts by constants.
7217 (define_insn "ashrdi3_power"
7218 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7219 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7220 (match_operand:SI 2 "const_int_operand" "M,i")))
7221 (clobber (match_scratch:SI 3 "=X,q"))]
7222 "TARGET_POWER"
7223 "@
7224 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7225 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7226 [(set_attr "type" "shift")
7227 (set_attr "length" "8")])
7229 (define_insn "ashrdi3_no_power"
7230 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7231 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7232 (match_operand:SI 2 "const_int_operand" "M,i")))]
7233 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7234 "@
7235 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7236 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7237 [(set_attr "type" "two,three")
7238 (set_attr "length" "8,12")])
7240 (define_insn "*ashrdisi3_noppc64"
7241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7242 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7243 (const_int 32)) 4))]
7244 "TARGET_32BIT && !TARGET_POWERPC64"
7245 "*
7246 {
7247 if (REGNO (operands[0]) == REGNO (operands[1]))
7248 return \"\";
7249 else
7250 return \"mr %0,%1\";
7251 }"
7252 [(set_attr "length" "4")])
7254 \f
7255 ;; PowerPC64 DImode operations.
7257 (define_expand "absdi2"
7258 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7259 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7260 "TARGET_POWERPC64"
7261 "
7262 {
7263 if (TARGET_ISEL)
7264 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7265 else
7266 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7267 DONE;
7268 }")
7270 (define_insn_and_split "absdi2_internal"
7271 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7272 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7273 (clobber (match_scratch:DI 2 "=&r,&r"))]
7274 "TARGET_POWERPC64 && !TARGET_ISEL"
7275 "#"
7276 "&& reload_completed"
7277 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7278 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7279 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7280 "")
7282 (define_insn_and_split "*nabsdi2"
7283 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7284 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7285 (clobber (match_scratch:DI 2 "=&r,&r"))]
7286 "TARGET_POWERPC64 && !TARGET_ISEL"
7287 "#"
7288 "&& reload_completed"
7289 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7290 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7291 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7292 "")
7294 (define_insn "muldi3"
7295 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7296 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7297 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7298 "TARGET_POWERPC64"
7299 "@
7300 mulld %0,%1,%2
7301 mulli %0,%1,%2"
7302 [(set (attr "type")
7303 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7304 (const_string "imul3")
7305 (match_operand:SI 2 "short_cint_operand" "")
7306 (const_string "imul2")]
7307 (const_string "lmul")))])
7309 (define_insn "*muldi3_internal1"
7310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7311 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7312 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7313 (const_int 0)))
7314 (clobber (match_scratch:DI 3 "=r,r"))]
7315 "TARGET_POWERPC64"
7316 "@
7317 mulld. %3,%1,%2
7318 #"
7319 [(set_attr "type" "lmul_compare")
7320 (set_attr "length" "4,8")])
7322 (define_split
7323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7324 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7325 (match_operand:DI 2 "gpc_reg_operand" ""))
7326 (const_int 0)))
7327 (clobber (match_scratch:DI 3 ""))]
7328 "TARGET_POWERPC64 && reload_completed"
7329 [(set (match_dup 3)
7330 (mult:DI (match_dup 1) (match_dup 2)))
7331 (set (match_dup 0)
7332 (compare:CC (match_dup 3)
7333 (const_int 0)))]
7334 "")
7336 (define_insn "*muldi3_internal2"
7337 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7338 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7339 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7340 (const_int 0)))
7341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7342 (mult:DI (match_dup 1) (match_dup 2)))]
7343 "TARGET_POWERPC64"
7344 "@
7345 mulld. %0,%1,%2
7346 #"
7347 [(set_attr "type" "lmul_compare")
7348 (set_attr "length" "4,8")])
7350 (define_split
7351 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7352 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7353 (match_operand:DI 2 "gpc_reg_operand" ""))
7354 (const_int 0)))
7355 (set (match_operand:DI 0 "gpc_reg_operand" "")
7356 (mult:DI (match_dup 1) (match_dup 2)))]
7357 "TARGET_POWERPC64 && reload_completed"
7358 [(set (match_dup 0)
7359 (mult:DI (match_dup 1) (match_dup 2)))
7360 (set (match_dup 3)
7361 (compare:CC (match_dup 0)
7362 (const_int 0)))]
7363 "")
7365 (define_insn "smuldi3_highpart"
7366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7367 (truncate:DI
7368 (lshiftrt:TI (mult:TI (sign_extend:TI
7369 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7370 (sign_extend:TI
7371 (match_operand:DI 2 "gpc_reg_operand" "r")))
7372 (const_int 64))))]
7373 "TARGET_POWERPC64"
7374 "mulhd %0,%1,%2"
7375 [(set_attr "type" "lmul")])
7377 (define_insn "umuldi3_highpart"
7378 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7379 (truncate:DI
7380 (lshiftrt:TI (mult:TI (zero_extend:TI
7381 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7382 (zero_extend:TI
7383 (match_operand:DI 2 "gpc_reg_operand" "r")))
7384 (const_int 64))))]
7385 "TARGET_POWERPC64"
7386 "mulhdu %0,%1,%2"
7387 [(set_attr "type" "lmul")])
7389 (define_insn "rotldi3"
7390 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7391 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7392 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7393 "TARGET_POWERPC64"
7394 "@
7395 rldcl %0,%1,%2,0
7396 rldicl %0,%1,%H2,0"
7397 [(set_attr "type" "var_shift_rotate,integer")])
7399 (define_insn "*rotldi3_internal2"
7400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7401 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7402 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7403 (const_int 0)))
7404 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7405 "TARGET_64BIT"
7406 "@
7407 rldcl. %3,%1,%2,0
7408 rldicl. %3,%1,%H2,0
7409 #
7410 #"
7411 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7412 (set_attr "length" "4,4,8,8")])
7414 (define_split
7415 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7416 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7417 (match_operand:DI 2 "reg_or_cint_operand" ""))
7418 (const_int 0)))
7419 (clobber (match_scratch:DI 3 ""))]
7420 "TARGET_POWERPC64 && reload_completed"
7421 [(set (match_dup 3)
7422 (rotate:DI (match_dup 1) (match_dup 2)))
7423 (set (match_dup 0)
7424 (compare:CC (match_dup 3)
7425 (const_int 0)))]
7426 "")
7428 (define_insn "*rotldi3_internal3"
7429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7430 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7431 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7432 (const_int 0)))
7433 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7434 (rotate:DI (match_dup 1) (match_dup 2)))]
7435 "TARGET_64BIT"
7436 "@
7437 rldcl. %0,%1,%2,0
7438 rldicl. %0,%1,%H2,0
7439 #
7440 #"
7441 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7442 (set_attr "length" "4,4,8,8")])
7444 (define_split
7445 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7446 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7447 (match_operand:DI 2 "reg_or_cint_operand" ""))
7448 (const_int 0)))
7449 (set (match_operand:DI 0 "gpc_reg_operand" "")
7450 (rotate:DI (match_dup 1) (match_dup 2)))]
7451 "TARGET_POWERPC64 && reload_completed"
7452 [(set (match_dup 0)
7453 (rotate:DI (match_dup 1) (match_dup 2)))
7454 (set (match_dup 3)
7455 (compare:CC (match_dup 0)
7456 (const_int 0)))]
7457 "")
7459 (define_insn "*rotldi3_internal4"
7460 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7461 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7462 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7463 (match_operand:DI 3 "mask64_operand" "n,n")))]
7464 "TARGET_POWERPC64"
7465 "@
7466 rldc%B3 %0,%1,%2,%S3
7467 rldic%B3 %0,%1,%H2,%S3"
7468 [(set_attr "type" "var_shift_rotate,integer")])
7470 (define_insn "*rotldi3_internal5"
7471 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7472 (compare:CC (and:DI
7473 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7474 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7475 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7476 (const_int 0)))
7477 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7478 "TARGET_64BIT"
7479 "@
7480 rldc%B3. %4,%1,%2,%S3
7481 rldic%B3. %4,%1,%H2,%S3
7482 #
7483 #"
7484 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7485 (set_attr "length" "4,4,8,8")])
7487 (define_split
7488 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7489 (compare:CC (and:DI
7490 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7491 (match_operand:DI 2 "reg_or_cint_operand" ""))
7492 (match_operand:DI 3 "mask64_operand" ""))
7493 (const_int 0)))
7494 (clobber (match_scratch:DI 4 ""))]
7495 "TARGET_POWERPC64 && reload_completed"
7496 [(set (match_dup 4)
7497 (and:DI (rotate:DI (match_dup 1)
7498 (match_dup 2))
7499 (match_dup 3)))
7500 (set (match_dup 0)
7501 (compare:CC (match_dup 4)
7502 (const_int 0)))]
7503 "")
7505 (define_insn "*rotldi3_internal6"
7506 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7507 (compare:CC (and:DI
7508 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7509 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7510 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7511 (const_int 0)))
7512 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7513 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7514 "TARGET_64BIT"
7515 "@
7516 rldc%B3. %0,%1,%2,%S3
7517 rldic%B3. %0,%1,%H2,%S3
7518 #
7519 #"
7520 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7521 (set_attr "length" "4,4,8,8")])
7523 (define_split
7524 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7525 (compare:CC (and:DI
7526 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7527 (match_operand:DI 2 "reg_or_cint_operand" ""))
7528 (match_operand:DI 3 "mask64_operand" ""))
7529 (const_int 0)))
7530 (set (match_operand:DI 0 "gpc_reg_operand" "")
7531 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7532 "TARGET_POWERPC64 && reload_completed"
7533 [(set (match_dup 0)
7534 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7535 (set (match_dup 4)
7536 (compare:CC (match_dup 0)
7537 (const_int 0)))]
7538 "")
7540 (define_insn "*rotldi3_internal7"
7541 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7542 (zero_extend:DI
7543 (subreg:QI
7544 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7545 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7546 "TARGET_POWERPC64"
7547 "@
7548 rldcl %0,%1,%2,56
7549 rldicl %0,%1,%H2,56"
7550 [(set_attr "type" "var_shift_rotate,integer")])
7552 (define_insn "*rotldi3_internal8"
7553 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7554 (compare:CC (zero_extend:DI
7555 (subreg:QI
7556 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7557 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7558 (const_int 0)))
7559 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7560 "TARGET_64BIT"
7561 "@
7562 rldcl. %3,%1,%2,56
7563 rldicl. %3,%1,%H2,56
7564 #
7565 #"
7566 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7567 (set_attr "length" "4,4,8,8")])
7569 (define_split
7570 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7571 (compare:CC (zero_extend:DI
7572 (subreg:QI
7573 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7574 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7575 (const_int 0)))
7576 (clobber (match_scratch:DI 3 ""))]
7577 "TARGET_POWERPC64 && reload_completed"
7578 [(set (match_dup 3)
7579 (zero_extend:DI (subreg:QI
7580 (rotate:DI (match_dup 1)
7581 (match_dup 2)) 0)))
7582 (set (match_dup 0)
7583 (compare:CC (match_dup 3)
7584 (const_int 0)))]
7585 "")
7587 (define_insn "*rotldi3_internal9"
7588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7589 (compare:CC (zero_extend:DI
7590 (subreg:QI
7591 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7592 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7593 (const_int 0)))
7594 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7595 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7596 "TARGET_64BIT"
7597 "@
7598 rldcl. %0,%1,%2,56
7599 rldicl. %0,%1,%H2,56
7600 #
7601 #"
7602 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7603 (set_attr "length" "4,4,8,8")])
7605 (define_split
7606 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7607 (compare:CC (zero_extend:DI
7608 (subreg:QI
7609 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7610 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7611 (const_int 0)))
7612 (set (match_operand:DI 0 "gpc_reg_operand" "")
7613 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7614 "TARGET_POWERPC64 && reload_completed"
7615 [(set (match_dup 0)
7616 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7617 (set (match_dup 3)
7618 (compare:CC (match_dup 0)
7619 (const_int 0)))]
7620 "")
7622 (define_insn "*rotldi3_internal10"
7623 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7624 (zero_extend:DI
7625 (subreg:HI
7626 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7627 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7628 "TARGET_POWERPC64"
7629 "@
7630 rldcl %0,%1,%2,48
7631 rldicl %0,%1,%H2,48"
7632 [(set_attr "type" "var_shift_rotate,integer")])
7634 (define_insn "*rotldi3_internal11"
7635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7636 (compare:CC (zero_extend:DI
7637 (subreg:HI
7638 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7639 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7640 (const_int 0)))
7641 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7642 "TARGET_64BIT"
7643 "@
7644 rldcl. %3,%1,%2,48
7645 rldicl. %3,%1,%H2,48
7646 #
7647 #"
7648 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7649 (set_attr "length" "4,4,8,8")])
7651 (define_split
7652 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7653 (compare:CC (zero_extend:DI
7654 (subreg:HI
7655 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7656 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7657 (const_int 0)))
7658 (clobber (match_scratch:DI 3 ""))]
7659 "TARGET_POWERPC64 && reload_completed"
7660 [(set (match_dup 3)
7661 (zero_extend:DI (subreg:HI
7662 (rotate:DI (match_dup 1)
7663 (match_dup 2)) 0)))
7664 (set (match_dup 0)
7665 (compare:CC (match_dup 3)
7666 (const_int 0)))]
7667 "")
7669 (define_insn "*rotldi3_internal12"
7670 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7671 (compare:CC (zero_extend:DI
7672 (subreg:HI
7673 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7674 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7675 (const_int 0)))
7676 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7677 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7678 "TARGET_64BIT"
7679 "@
7680 rldcl. %0,%1,%2,48
7681 rldicl. %0,%1,%H2,48
7682 #
7683 #"
7684 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7685 (set_attr "length" "4,4,8,8")])
7687 (define_split
7688 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7689 (compare:CC (zero_extend:DI
7690 (subreg:HI
7691 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7692 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7693 (const_int 0)))
7694 (set (match_operand:DI 0 "gpc_reg_operand" "")
7695 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7696 "TARGET_POWERPC64 && reload_completed"
7697 [(set (match_dup 0)
7698 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7699 (set (match_dup 3)
7700 (compare:CC (match_dup 0)
7701 (const_int 0)))]
7702 "")
7704 (define_insn "*rotldi3_internal13"
7705 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7706 (zero_extend:DI
7707 (subreg:SI
7708 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7709 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7710 "TARGET_POWERPC64"
7711 "@
7712 rldcl %0,%1,%2,32
7713 rldicl %0,%1,%H2,32"
7714 [(set_attr "type" "var_shift_rotate,integer")])
7716 (define_insn "*rotldi3_internal14"
7717 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7718 (compare:CC (zero_extend:DI
7719 (subreg:SI
7720 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7721 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7722 (const_int 0)))
7723 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7724 "TARGET_64BIT"
7725 "@
7726 rldcl. %3,%1,%2,32
7727 rldicl. %3,%1,%H2,32
7728 #
7729 #"
7730 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7731 (set_attr "length" "4,4,8,8")])
7733 (define_split
7734 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7735 (compare:CC (zero_extend:DI
7736 (subreg:SI
7737 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7738 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7739 (const_int 0)))
7740 (clobber (match_scratch:DI 3 ""))]
7741 "TARGET_POWERPC64 && reload_completed"
7742 [(set (match_dup 3)
7743 (zero_extend:DI (subreg:SI
7744 (rotate:DI (match_dup 1)
7745 (match_dup 2)) 0)))
7746 (set (match_dup 0)
7747 (compare:CC (match_dup 3)
7748 (const_int 0)))]
7749 "")
7751 (define_insn "*rotldi3_internal15"
7752 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7753 (compare:CC (zero_extend:DI
7754 (subreg:SI
7755 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7756 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7757 (const_int 0)))
7758 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7759 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7760 "TARGET_64BIT"
7761 "@
7762 rldcl. %0,%1,%2,32
7763 rldicl. %0,%1,%H2,32
7764 #
7765 #"
7766 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7767 (set_attr "length" "4,4,8,8")])
7769 (define_split
7770 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7771 (compare:CC (zero_extend:DI
7772 (subreg:SI
7773 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7774 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7775 (const_int 0)))
7776 (set (match_operand:DI 0 "gpc_reg_operand" "")
7777 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7778 "TARGET_POWERPC64 && reload_completed"
7779 [(set (match_dup 0)
7780 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7781 (set (match_dup 3)
7782 (compare:CC (match_dup 0)
7783 (const_int 0)))]
7784 "")
7786 (define_expand "ashldi3"
7787 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7788 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7789 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7790 "TARGET_POWERPC64 || TARGET_POWER"
7791 "
7792 {
7793 if (TARGET_POWERPC64)
7794 ;
7795 else if (TARGET_POWER)
7796 {
7797 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7798 DONE;
7799 }
7800 else
7801 FAIL;
7802 }")
7804 (define_insn "*ashldi3_internal1"
7805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7806 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7807 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7808 "TARGET_POWERPC64"
7809 "@
7810 sld %0,%1,%2
7811 sldi %0,%1,%H2"
7812 [(set_attr "type" "var_shift_rotate,shift")])
7814 (define_insn "*ashldi3_internal2"
7815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7816 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7817 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7818 (const_int 0)))
7819 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7820 "TARGET_64BIT"
7821 "@
7822 sld. %3,%1,%2
7823 sldi. %3,%1,%H2
7824 #
7825 #"
7826 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7827 (set_attr "length" "4,4,8,8")])
7829 (define_split
7830 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7831 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7832 (match_operand:SI 2 "reg_or_cint_operand" ""))
7833 (const_int 0)))
7834 (clobber (match_scratch:DI 3 ""))]
7835 "TARGET_POWERPC64 && reload_completed"
7836 [(set (match_dup 3)
7837 (ashift:DI (match_dup 1) (match_dup 2)))
7838 (set (match_dup 0)
7839 (compare:CC (match_dup 3)
7840 (const_int 0)))]
7841 "")
7843 (define_insn "*ashldi3_internal3"
7844 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7845 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7846 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7847 (const_int 0)))
7848 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7849 (ashift:DI (match_dup 1) (match_dup 2)))]
7850 "TARGET_64BIT"
7851 "@
7852 sld. %0,%1,%2
7853 sldi. %0,%1,%H2
7854 #
7855 #"
7856 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7857 (set_attr "length" "4,4,8,8")])
7859 (define_split
7860 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7861 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7862 (match_operand:SI 2 "reg_or_cint_operand" ""))
7863 (const_int 0)))
7864 (set (match_operand:DI 0 "gpc_reg_operand" "")
7865 (ashift:DI (match_dup 1) (match_dup 2)))]
7866 "TARGET_POWERPC64 && reload_completed"
7867 [(set (match_dup 0)
7868 (ashift:DI (match_dup 1) (match_dup 2)))
7869 (set (match_dup 3)
7870 (compare:CC (match_dup 0)
7871 (const_int 0)))]
7872 "")
7874 (define_insn "*ashldi3_internal4"
7875 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7876 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7877 (match_operand:SI 2 "const_int_operand" "i"))
7878 (match_operand:DI 3 "const_int_operand" "n")))]
7879 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7880 "rldic %0,%1,%H2,%W3")
7882 (define_insn "ashldi3_internal5"
7883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7884 (compare:CC
7885 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7886 (match_operand:SI 2 "const_int_operand" "i,i"))
7887 (match_operand:DI 3 "const_int_operand" "n,n"))
7888 (const_int 0)))
7889 (clobber (match_scratch:DI 4 "=r,r"))]
7890 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7891 "@
7892 rldic. %4,%1,%H2,%W3
7893 #"
7894 [(set_attr "type" "compare")
7895 (set_attr "length" "4,8")])
7897 (define_split
7898 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7899 (compare:CC
7900 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7901 (match_operand:SI 2 "const_int_operand" ""))
7902 (match_operand:DI 3 "const_int_operand" ""))
7903 (const_int 0)))
7904 (clobber (match_scratch:DI 4 ""))]
7905 "TARGET_POWERPC64 && reload_completed
7906 && includes_rldic_lshift_p (operands[2], operands[3])"
7907 [(set (match_dup 4)
7908 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7909 (match_dup 3)))
7910 (set (match_dup 0)
7911 (compare:CC (match_dup 4)
7912 (const_int 0)))]
7913 "")
7915 (define_insn "*ashldi3_internal6"
7916 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7917 (compare:CC
7918 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7919 (match_operand:SI 2 "const_int_operand" "i,i"))
7920 (match_operand:DI 3 "const_int_operand" "n,n"))
7921 (const_int 0)))
7922 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7923 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7924 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7925 "@
7926 rldic. %0,%1,%H2,%W3
7927 #"
7928 [(set_attr "type" "compare")
7929 (set_attr "length" "4,8")])
7931 (define_split
7932 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7933 (compare:CC
7934 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7935 (match_operand:SI 2 "const_int_operand" ""))
7936 (match_operand:DI 3 "const_int_operand" ""))
7937 (const_int 0)))
7938 (set (match_operand:DI 0 "gpc_reg_operand" "")
7939 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7940 "TARGET_POWERPC64 && reload_completed
7941 && includes_rldic_lshift_p (operands[2], operands[3])"
7942 [(set (match_dup 0)
7943 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7944 (match_dup 3)))
7945 (set (match_dup 4)
7946 (compare:CC (match_dup 0)
7947 (const_int 0)))]
7948 "")
7950 (define_insn "*ashldi3_internal7"
7951 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7952 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7953 (match_operand:SI 2 "const_int_operand" "i"))
7954 (match_operand:DI 3 "mask64_operand" "n")))]
7955 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7956 "rldicr %0,%1,%H2,%S3")
7958 (define_insn "ashldi3_internal8"
7959 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7960 (compare:CC
7961 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7962 (match_operand:SI 2 "const_int_operand" "i,i"))
7963 (match_operand:DI 3 "mask64_operand" "n,n"))
7964 (const_int 0)))
7965 (clobber (match_scratch:DI 4 "=r,r"))]
7966 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7967 "@
7968 rldicr. %4,%1,%H2,%S3
7969 #"
7970 [(set_attr "type" "compare")
7971 (set_attr "length" "4,8")])
7973 (define_split
7974 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7975 (compare:CC
7976 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7977 (match_operand:SI 2 "const_int_operand" ""))
7978 (match_operand:DI 3 "mask64_operand" ""))
7979 (const_int 0)))
7980 (clobber (match_scratch:DI 4 ""))]
7981 "TARGET_POWERPC64 && reload_completed
7982 && includes_rldicr_lshift_p (operands[2], operands[3])"
7983 [(set (match_dup 4)
7984 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7985 (match_dup 3)))
7986 (set (match_dup 0)
7987 (compare:CC (match_dup 4)
7988 (const_int 0)))]
7989 "")
7991 (define_insn "*ashldi3_internal9"
7992 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7993 (compare:CC
7994 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7995 (match_operand:SI 2 "const_int_operand" "i,i"))
7996 (match_operand:DI 3 "mask64_operand" "n,n"))
7997 (const_int 0)))
7998 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7999 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8000 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8001 "@
8002 rldicr. %0,%1,%H2,%S3
8003 #"
8004 [(set_attr "type" "compare")
8005 (set_attr "length" "4,8")])
8007 (define_split
8008 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8009 (compare:CC
8010 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8011 (match_operand:SI 2 "const_int_operand" ""))
8012 (match_operand:DI 3 "mask64_operand" ""))
8013 (const_int 0)))
8014 (set (match_operand:DI 0 "gpc_reg_operand" "")
8015 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8016 "TARGET_POWERPC64 && reload_completed
8017 && includes_rldicr_lshift_p (operands[2], operands[3])"
8018 [(set (match_dup 0)
8019 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8020 (match_dup 3)))
8021 (set (match_dup 4)
8022 (compare:CC (match_dup 0)
8023 (const_int 0)))]
8024 "")
8026 (define_expand "lshrdi3"
8027 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8028 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8029 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8030 "TARGET_POWERPC64 || TARGET_POWER"
8031 "
8032 {
8033 if (TARGET_POWERPC64)
8034 ;
8035 else if (TARGET_POWER)
8036 {
8037 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8038 DONE;
8039 }
8040 else
8041 FAIL;
8042 }")
8044 (define_insn "*lshrdi3_internal1"
8045 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8046 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8047 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8048 "TARGET_POWERPC64"
8049 "@
8050 srd %0,%1,%2
8051 srdi %0,%1,%H2"
8052 [(set_attr "type" "var_shift_rotate,shift")])
8054 (define_insn "*lshrdi3_internal2"
8055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8056 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8057 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8058 (const_int 0)))
8059 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8060 "TARGET_64BIT "
8061 "@
8062 srd. %3,%1,%2
8063 srdi. %3,%1,%H2
8064 #
8065 #"
8066 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8067 (set_attr "length" "4,4,8,8")])
8069 (define_split
8070 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8071 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8072 (match_operand:SI 2 "reg_or_cint_operand" ""))
8073 (const_int 0)))
8074 (clobber (match_scratch:DI 3 ""))]
8075 "TARGET_POWERPC64 && reload_completed"
8076 [(set (match_dup 3)
8077 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8078 (set (match_dup 0)
8079 (compare:CC (match_dup 3)
8080 (const_int 0)))]
8081 "")
8083 (define_insn "*lshrdi3_internal3"
8084 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8085 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8086 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8087 (const_int 0)))
8088 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8089 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8090 "TARGET_64BIT"
8091 "@
8092 srd. %0,%1,%2
8093 srdi. %0,%1,%H2
8094 #
8095 #"
8096 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8097 (set_attr "length" "4,4,8,8")])
8099 (define_split
8100 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8101 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8102 (match_operand:SI 2 "reg_or_cint_operand" ""))
8103 (const_int 0)))
8104 (set (match_operand:DI 0 "gpc_reg_operand" "")
8105 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8106 "TARGET_POWERPC64 && reload_completed"
8107 [(set (match_dup 0)
8108 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8109 (set (match_dup 3)
8110 (compare:CC (match_dup 0)
8111 (const_int 0)))]
8112 "")
8114 (define_expand "ashrdi3"
8115 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8116 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8117 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8118 "WORDS_BIG_ENDIAN"
8119 "
8120 {
8121 if (TARGET_POWERPC64)
8122 ;
8123 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8124 {
8125 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8126 DONE;
8127 }
8128 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8129 && WORDS_BIG_ENDIAN)
8130 {
8131 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8132 DONE;
8133 }
8134 else
8135 FAIL;
8136 }")
8138 (define_insn "*ashrdi3_internal1"
8139 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8140 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8141 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8142 "TARGET_POWERPC64"
8143 "@
8144 srad %0,%1,%2
8145 sradi %0,%1,%H2"
8146 [(set_attr "type" "var_shift_rotate,shift")])
8148 (define_insn "*ashrdi3_internal2"
8149 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8150 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8151 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8152 (const_int 0)))
8153 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8154 "TARGET_64BIT"
8155 "@
8156 srad. %3,%1,%2
8157 sradi. %3,%1,%H2
8158 #
8159 #"
8160 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8161 (set_attr "length" "4,4,8,8")])
8163 (define_split
8164 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8165 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8166 (match_operand:SI 2 "reg_or_cint_operand" ""))
8167 (const_int 0)))
8168 (clobber (match_scratch:DI 3 ""))]
8169 "TARGET_POWERPC64 && reload_completed"
8170 [(set (match_dup 3)
8171 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8172 (set (match_dup 0)
8173 (compare:CC (match_dup 3)
8174 (const_int 0)))]
8175 "")
8177 (define_insn "*ashrdi3_internal3"
8178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8179 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8180 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8181 (const_int 0)))
8182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8183 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8184 "TARGET_64BIT"
8185 "@
8186 srad. %0,%1,%2
8187 sradi. %0,%1,%H2
8188 #
8189 #"
8190 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8191 (set_attr "length" "4,4,8,8")])
8193 (define_split
8194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8195 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8196 (match_operand:SI 2 "reg_or_cint_operand" ""))
8197 (const_int 0)))
8198 (set (match_operand:DI 0 "gpc_reg_operand" "")
8199 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8200 "TARGET_POWERPC64 && reload_completed"
8201 [(set (match_dup 0)
8202 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8203 (set (match_dup 3)
8204 (compare:CC (match_dup 0)
8205 (const_int 0)))]
8206 "")
8208 (define_expand "anddi3"
8209 [(parallel
8210 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8211 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8212 (match_operand:DI 2 "and64_2_operand" "")))
8213 (clobber (match_scratch:CC 3 ""))])]
8214 "TARGET_POWERPC64"
8215 "")
8217 (define_insn "anddi3_mc"
8218 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8219 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8220 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8221 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8222 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8223 "@
8224 and %0,%1,%2
8225 rldic%B2 %0,%1,0,%S2
8226 rlwinm %0,%1,0,%m2,%M2
8227 andi. %0,%1,%b2
8228 andis. %0,%1,%u2
8229 #"
8230 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8231 (set_attr "length" "4,4,4,4,4,8")])
8233 (define_insn "anddi3_nomc"
8234 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8235 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8236 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8237 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8238 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8239 "@
8240 and %0,%1,%2
8241 rldic%B2 %0,%1,0,%S2
8242 rlwinm %0,%1,0,%m2,%M2
8243 #"
8244 [(set_attr "length" "4,4,4,8")])
8246 (define_split
8247 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8248 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8249 (match_operand:DI 2 "mask64_2_operand" "")))
8250 (clobber (match_scratch:CC 3 ""))]
8251 "TARGET_POWERPC64
8252 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8253 && !mask_operand (operands[2], DImode)
8254 && !mask64_operand (operands[2], DImode)"
8255 [(set (match_dup 0)
8256 (and:DI (rotate:DI (match_dup 1)
8257 (match_dup 4))
8258 (match_dup 5)))
8259 (set (match_dup 0)
8260 (and:DI (rotate:DI (match_dup 0)
8261 (match_dup 6))
8262 (match_dup 7)))]
8263 {
8264 build_mask64_2_operands (operands[2], &operands[4]);
8265 })
8267 (define_insn "*anddi3_internal2_mc"
8268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8269 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8270 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8271 (const_int 0)))
8272 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8273 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8274 "TARGET_64BIT && rs6000_gen_cell_microcode"
8275 "@
8276 and. %3,%1,%2
8277 rldic%B2. %3,%1,0,%S2
8278 rlwinm. %3,%1,0,%m2,%M2
8279 andi. %3,%1,%b2
8280 andis. %3,%1,%u2
8281 #
8282 #
8283 #
8284 #
8285 #
8286 #
8287 #"
8288 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8289 fast_compare,compare,compare,compare,compare,compare,\
8290 compare,compare")
8291 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8293 (define_split
8294 [(set (match_operand:CC 0 "cc_reg_operand" "")
8295 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8296 (match_operand:DI 2 "mask64_2_operand" ""))
8297 (const_int 0)))
8298 (clobber (match_scratch:DI 3 ""))
8299 (clobber (match_scratch:CC 4 ""))]
8300 "TARGET_64BIT && reload_completed
8301 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8302 && !mask_operand (operands[2], DImode)
8303 && !mask64_operand (operands[2], DImode)"
8304 [(set (match_dup 3)
8305 (and:DI (rotate:DI (match_dup 1)
8306 (match_dup 5))
8307 (match_dup 6)))
8308 (parallel [(set (match_dup 0)
8309 (compare:CC (and:DI (rotate:DI (match_dup 3)
8310 (match_dup 7))
8311 (match_dup 8))
8312 (const_int 0)))
8313 (clobber (match_dup 3))])]
8314 "
8315 {
8316 build_mask64_2_operands (operands[2], &operands[5]);
8317 }")
8319 (define_insn "*anddi3_internal3_mc"
8320 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8321 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8322 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8323 (const_int 0)))
8324 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8325 (and:DI (match_dup 1) (match_dup 2)))
8326 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8327 "TARGET_64BIT && rs6000_gen_cell_microcode"
8328 "@
8329 and. %0,%1,%2
8330 rldic%B2. %0,%1,0,%S2
8331 rlwinm. %0,%1,0,%m2,%M2
8332 andi. %0,%1,%b2
8333 andis. %0,%1,%u2
8334 #
8335 #
8336 #
8337 #
8338 #
8339 #
8340 #"
8341 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8342 fast_compare,compare,compare,compare,compare,compare,\
8343 compare,compare")
8344 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8346 (define_split
8347 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8348 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8349 (match_operand:DI 2 "and64_2_operand" ""))
8350 (const_int 0)))
8351 (set (match_operand:DI 0 "gpc_reg_operand" "")
8352 (and:DI (match_dup 1) (match_dup 2)))
8353 (clobber (match_scratch:CC 4 ""))]
8354 "TARGET_64BIT && reload_completed"
8355 [(parallel [(set (match_dup 0)
8356 (and:DI (match_dup 1) (match_dup 2)))
8357 (clobber (match_dup 4))])
8358 (set (match_dup 3)
8359 (compare:CC (match_dup 0)
8360 (const_int 0)))]
8361 "")
8363 (define_split
8364 [(set (match_operand:CC 3 "cc_reg_operand" "")
8365 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8366 (match_operand:DI 2 "mask64_2_operand" ""))
8367 (const_int 0)))
8368 (set (match_operand:DI 0 "gpc_reg_operand" "")
8369 (and:DI (match_dup 1) (match_dup 2)))
8370 (clobber (match_scratch:CC 4 ""))]
8371 "TARGET_64BIT && reload_completed
8372 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8373 && !mask_operand (operands[2], DImode)
8374 && !mask64_operand (operands[2], DImode)"
8375 [(set (match_dup 0)
8376 (and:DI (rotate:DI (match_dup 1)
8377 (match_dup 5))
8378 (match_dup 6)))
8379 (parallel [(set (match_dup 3)
8380 (compare:CC (and:DI (rotate:DI (match_dup 0)
8381 (match_dup 7))
8382 (match_dup 8))
8383 (const_int 0)))
8384 (set (match_dup 0)
8385 (and:DI (rotate:DI (match_dup 0)
8386 (match_dup 7))
8387 (match_dup 8)))])]
8388 "
8389 {
8390 build_mask64_2_operands (operands[2], &operands[5]);
8391 }")
8393 (define_expand "iordi3"
8394 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8395 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8396 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8397 "TARGET_POWERPC64"
8398 "
8399 {
8400 if (non_logical_cint_operand (operands[2], DImode))
8401 {
8402 HOST_WIDE_INT value;
8403 rtx tmp = ((!can_create_pseudo_p ()
8404 || rtx_equal_p (operands[0], operands[1]))
8405 ? operands[0] : gen_reg_rtx (DImode));
8407 if (GET_CODE (operands[2]) == CONST_INT)
8408 {
8409 value = INTVAL (operands[2]);
8410 emit_insn (gen_iordi3 (tmp, operands[1],
8411 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8412 }
8413 else
8414 {
8415 value = CONST_DOUBLE_LOW (operands[2]);
8416 emit_insn (gen_iordi3 (tmp, operands[1],
8417 immed_double_const (value
8418 & (~ (HOST_WIDE_INT) 0xffff),
8419 0, DImode)));
8420 }
8422 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8423 DONE;
8424 }
8425 }")
8427 (define_expand "xordi3"
8428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8429 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8430 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8431 "TARGET_POWERPC64"
8432 "
8433 {
8434 if (non_logical_cint_operand (operands[2], DImode))
8435 {
8436 HOST_WIDE_INT value;
8437 rtx tmp = ((!can_create_pseudo_p ()
8438 || rtx_equal_p (operands[0], operands[1]))
8439 ? operands[0] : gen_reg_rtx (DImode));
8441 if (GET_CODE (operands[2]) == CONST_INT)
8442 {
8443 value = INTVAL (operands[2]);
8444 emit_insn (gen_xordi3 (tmp, operands[1],
8445 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8446 }
8447 else
8448 {
8449 value = CONST_DOUBLE_LOW (operands[2]);
8450 emit_insn (gen_xordi3 (tmp, operands[1],
8451 immed_double_const (value
8452 & (~ (HOST_WIDE_INT) 0xffff),
8453 0, DImode)));
8454 }
8456 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8457 DONE;
8458 }
8459 }")
8461 (define_insn "*booldi3_internal1"
8462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8463 (match_operator:DI 3 "boolean_or_operator"
8464 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8465 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8466 "TARGET_POWERPC64"
8467 "@
8468 %q3 %0,%1,%2
8469 %q3i %0,%1,%b2
8470 %q3is %0,%1,%u2")
8472 (define_insn "*booldi3_internal2"
8473 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8474 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8475 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8476 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8477 (const_int 0)))
8478 (clobber (match_scratch:DI 3 "=r,r"))]
8479 "TARGET_64BIT"
8480 "@
8481 %q4. %3,%1,%2
8482 #"
8483 [(set_attr "type" "fast_compare,compare")
8484 (set_attr "length" "4,8")])
8486 (define_split
8487 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8488 (compare:CC (match_operator:DI 4 "boolean_operator"
8489 [(match_operand:DI 1 "gpc_reg_operand" "")
8490 (match_operand:DI 2 "gpc_reg_operand" "")])
8491 (const_int 0)))
8492 (clobber (match_scratch:DI 3 ""))]
8493 "TARGET_POWERPC64 && reload_completed"
8494 [(set (match_dup 3) (match_dup 4))
8495 (set (match_dup 0)
8496 (compare:CC (match_dup 3)
8497 (const_int 0)))]
8498 "")
8500 (define_insn "*booldi3_internal3"
8501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8502 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8503 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8504 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8505 (const_int 0)))
8506 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8507 (match_dup 4))]
8508 "TARGET_64BIT"
8509 "@
8510 %q4. %0,%1,%2
8511 #"
8512 [(set_attr "type" "fast_compare,compare")
8513 (set_attr "length" "4,8")])
8515 (define_split
8516 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8517 (compare:CC (match_operator:DI 4 "boolean_operator"
8518 [(match_operand:DI 1 "gpc_reg_operand" "")
8519 (match_operand:DI 2 "gpc_reg_operand" "")])
8520 (const_int 0)))
8521 (set (match_operand:DI 0 "gpc_reg_operand" "")
8522 (match_dup 4))]
8523 "TARGET_POWERPC64 && reload_completed"
8524 [(set (match_dup 0) (match_dup 4))
8525 (set (match_dup 3)
8526 (compare:CC (match_dup 0)
8527 (const_int 0)))]
8528 "")
8530 ;; Split a logical operation that we can't do in one insn into two insns,
8531 ;; each of which does one 16-bit part. This is used by combine.
8533 (define_split
8534 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8535 (match_operator:DI 3 "boolean_or_operator"
8536 [(match_operand:DI 1 "gpc_reg_operand" "")
8537 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8538 "TARGET_POWERPC64"
8539 [(set (match_dup 0) (match_dup 4))
8540 (set (match_dup 0) (match_dup 5))]
8541 "
8542 {
8543 rtx i3,i4;
8545 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8546 {
8547 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8548 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8549 0, DImode);
8550 i4 = GEN_INT (value & 0xffff);
8551 }
8552 else
8553 {
8554 i3 = GEN_INT (INTVAL (operands[2])
8555 & (~ (HOST_WIDE_INT) 0xffff));
8556 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8557 }
8558 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8559 operands[1], i3);
8560 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8561 operands[0], i4);
8562 }")
8564 (define_insn "*boolcdi3_internal1"
8565 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8566 (match_operator:DI 3 "boolean_operator"
8567 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8568 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8569 "TARGET_POWERPC64"
8570 "%q3 %0,%2,%1")
8572 (define_insn "*boolcdi3_internal2"
8573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8574 (compare:CC (match_operator:DI 4 "boolean_operator"
8575 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8576 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8577 (const_int 0)))
8578 (clobber (match_scratch:DI 3 "=r,r"))]
8579 "TARGET_64BIT"
8580 "@
8581 %q4. %3,%2,%1
8582 #"
8583 [(set_attr "type" "fast_compare,compare")
8584 (set_attr "length" "4,8")])
8586 (define_split
8587 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8588 (compare:CC (match_operator:DI 4 "boolean_operator"
8589 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8590 (match_operand:DI 2 "gpc_reg_operand" "")])
8591 (const_int 0)))
8592 (clobber (match_scratch:DI 3 ""))]
8593 "TARGET_POWERPC64 && reload_completed"
8594 [(set (match_dup 3) (match_dup 4))
8595 (set (match_dup 0)
8596 (compare:CC (match_dup 3)
8597 (const_int 0)))]
8598 "")
8600 (define_insn "*boolcdi3_internal3"
8601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8602 (compare:CC (match_operator:DI 4 "boolean_operator"
8603 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8604 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8605 (const_int 0)))
8606 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8607 (match_dup 4))]
8608 "TARGET_64BIT"
8609 "@
8610 %q4. %0,%2,%1
8611 #"
8612 [(set_attr "type" "fast_compare,compare")
8613 (set_attr "length" "4,8")])
8615 (define_split
8616 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8617 (compare:CC (match_operator:DI 4 "boolean_operator"
8618 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8619 (match_operand:DI 2 "gpc_reg_operand" "")])
8620 (const_int 0)))
8621 (set (match_operand:DI 0 "gpc_reg_operand" "")
8622 (match_dup 4))]
8623 "TARGET_POWERPC64 && reload_completed"
8624 [(set (match_dup 0) (match_dup 4))
8625 (set (match_dup 3)
8626 (compare:CC (match_dup 0)
8627 (const_int 0)))]
8628 "")
8630 (define_insn "*boolccdi3_internal1"
8631 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8632 (match_operator:DI 3 "boolean_operator"
8633 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8634 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8635 "TARGET_POWERPC64"
8636 "%q3 %0,%1,%2")
8638 (define_insn "*boolccdi3_internal2"
8639 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8640 (compare:CC (match_operator:DI 4 "boolean_operator"
8641 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8642 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8643 (const_int 0)))
8644 (clobber (match_scratch:DI 3 "=r,r"))]
8645 "TARGET_64BIT"
8646 "@
8647 %q4. %3,%1,%2
8648 #"
8649 [(set_attr "type" "fast_compare,compare")
8650 (set_attr "length" "4,8")])
8652 (define_split
8653 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8654 (compare:CC (match_operator:DI 4 "boolean_operator"
8655 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8656 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8657 (const_int 0)))
8658 (clobber (match_scratch:DI 3 ""))]
8659 "TARGET_POWERPC64 && reload_completed"
8660 [(set (match_dup 3) (match_dup 4))
8661 (set (match_dup 0)
8662 (compare:CC (match_dup 3)
8663 (const_int 0)))]
8664 "")
8666 (define_insn "*boolccdi3_internal3"
8667 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8668 (compare:CC (match_operator:DI 4 "boolean_operator"
8669 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8670 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8671 (const_int 0)))
8672 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8673 (match_dup 4))]
8674 "TARGET_64BIT"
8675 "@
8676 %q4. %0,%1,%2
8677 #"
8678 [(set_attr "type" "fast_compare,compare")
8679 (set_attr "length" "4,8")])
8681 (define_split
8682 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8683 (compare:CC (match_operator:DI 4 "boolean_operator"
8684 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8685 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8686 (const_int 0)))
8687 (set (match_operand:DI 0 "gpc_reg_operand" "")
8688 (match_dup 4))]
8689 "TARGET_POWERPC64 && reload_completed"
8690 [(set (match_dup 0) (match_dup 4))
8691 (set (match_dup 3)
8692 (compare:CC (match_dup 0)
8693 (const_int 0)))]
8694 "")
8696 (define_expand "smindi3"
8697 [(match_operand:DI 0 "gpc_reg_operand" "")
8698 (match_operand:DI 1 "gpc_reg_operand" "")
8699 (match_operand:DI 2 "gpc_reg_operand" "")]
8700 "TARGET_ISEL64"
8701 "
8702 {
8703 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8704 DONE;
8705 }")
8707 (define_expand "smaxdi3"
8708 [(match_operand:DI 0 "gpc_reg_operand" "")
8709 (match_operand:DI 1 "gpc_reg_operand" "")
8710 (match_operand:DI 2 "gpc_reg_operand" "")]
8711 "TARGET_ISEL64"
8712 "
8713 {
8714 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8715 DONE;
8716 }")
8718 (define_expand "umindi3"
8719 [(match_operand:DI 0 "gpc_reg_operand" "")
8720 (match_operand:DI 1 "gpc_reg_operand" "")
8721 (match_operand:DI 2 "gpc_reg_operand" "")]
8722 "TARGET_ISEL64"
8723 "
8724 {
8725 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8726 DONE;
8727 }")
8729 (define_expand "umaxdi3"
8730 [(match_operand:DI 0 "gpc_reg_operand" "")
8731 (match_operand:DI 1 "gpc_reg_operand" "")
8732 (match_operand:DI 2 "gpc_reg_operand" "")]
8733 "TARGET_ISEL64"
8734 "
8735 {
8736 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8737 DONE;
8738 }")
8740 \f
8741 ;; Now define ways of moving data around.
8743 ;; Set up a register with a value from the GOT table
8745 (define_expand "movsi_got"
8746 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8747 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8748 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8749 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8750 "
8751 {
8752 if (GET_CODE (operands[1]) == CONST)
8753 {
8754 rtx offset = const0_rtx;
8755 HOST_WIDE_INT value;
8757 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8758 value = INTVAL (offset);
8759 if (value != 0)
8760 {
8761 rtx tmp = (!can_create_pseudo_p ()
8762 ? operands[0]
8763 : gen_reg_rtx (Pmode));
8764 emit_insn (gen_movsi_got (tmp, operands[1]));
8765 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8766 DONE;
8767 }
8768 }
8770 operands[2] = rs6000_got_register (operands[1]);
8771 }")
8773 (define_insn "*movsi_got_internal"
8774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8775 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8776 (match_operand:SI 2 "gpc_reg_operand" "b")]
8777 UNSPEC_MOVSI_GOT))]
8778 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8779 "{l|lwz} %0,%a1@got(%2)"
8780 [(set_attr "type" "load")])
8782 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8783 ;; didn't get allocated to a hard register.
8784 (define_split
8785 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8786 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8787 (match_operand:SI 2 "memory_operand" "")]
8788 UNSPEC_MOVSI_GOT))]
8789 "DEFAULT_ABI == ABI_V4
8790 && flag_pic == 1
8791 && (reload_in_progress || reload_completed)"
8792 [(set (match_dup 0) (match_dup 2))
8793 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8794 UNSPEC_MOVSI_GOT))]
8795 "")
8797 ;; For SI, we special-case integers that can't be loaded in one insn. We
8798 ;; do the load 16-bits at a time. We could do this by loading from memory,
8799 ;; and this is even supposed to be faster, but it is simpler not to get
8800 ;; integers in the TOC.
8801 (define_insn "movsi_low"
8802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8803 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8804 (match_operand 2 "" ""))))]
8805 "TARGET_MACHO && ! TARGET_64BIT"
8806 "{l|lwz} %0,lo16(%2)(%1)"
8807 [(set_attr "type" "load")
8808 (set_attr "length" "4")])
8810 (define_insn "*movsi_internal1"
8811 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8812 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8813 "!TARGET_SINGLE_FPU &&
8814 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8815 "@
8816 mr %0,%1
8817 {cal|la} %0,%a1
8818 {l%U1%X1|lwz%U1%X1} %0,%1
8819 {st%U0%X0|stw%U0%X0} %1,%0
8820 {lil|li} %0,%1
8821 {liu|lis} %0,%v1
8822 #
8823 {cal|la} %0,%a1
8824 mf%1 %0
8825 mt%0 %1
8826 mt%0 %1
8827 mt%0 %1
8828 {cror 0,0,0|nop}"
8829 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8830 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8832 (define_insn "*movsi_internal1_single"
8833 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8834 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8835 "TARGET_SINGLE_FPU &&
8836 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8837 "@
8838 mr %0,%1
8839 {cal|la} %0,%a1
8840 {l%U1%X1|lwz%U1%X1} %0,%1
8841 {st%U0%X0|stw%U0%X0} %1,%0
8842 {lil|li} %0,%1
8843 {liu|lis} %0,%v1
8844 #
8845 {cal|la} %0,%a1
8846 mf%1 %0
8847 mt%0 %1
8848 mt%0 %1
8849 mt%0 %1
8850 {cror 0,0,0|nop}
8851 stfs%U0%X0 %1, %0
8852 lfs%U1%X1 %0, %1"
8853 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8854 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8856 ;; Split a load of a large constant into the appropriate two-insn
8857 ;; sequence.
8859 (define_split
8860 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8861 (match_operand:SI 1 "const_int_operand" ""))]
8862 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8863 && (INTVAL (operands[1]) & 0xffff) != 0"
8864 [(set (match_dup 0)
8865 (match_dup 2))
8866 (set (match_dup 0)
8867 (ior:SI (match_dup 0)
8868 (match_dup 3)))]
8869 "
8870 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8872 if (tem == operands[0])
8873 DONE;
8874 else
8875 FAIL;
8876 }")
8878 (define_insn "*mov<mode>_internal2"
8879 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8880 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8881 (const_int 0)))
8882 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8883 ""
8884 "@
8885 {cmpi|cmp<wd>i} %2,%0,0
8886 mr. %0,%1
8887 #"
8888 [(set_attr "type" "cmp,compare,cmp")
8889 (set_attr "length" "4,4,8")])
8891 (define_split
8892 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8893 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8894 (const_int 0)))
8895 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8896 "reload_completed"
8897 [(set (match_dup 0) (match_dup 1))
8898 (set (match_dup 2)
8899 (compare:CC (match_dup 0)
8900 (const_int 0)))]
8901 "")
8902 \f
8903 (define_insn "*movhi_internal"
8904 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8905 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8906 "gpc_reg_operand (operands[0], HImode)
8907 || gpc_reg_operand (operands[1], HImode)"
8908 "@
8909 mr %0,%1
8910 lhz%U1%X1 %0,%1
8911 sth%U0%X0 %1,%0
8912 {lil|li} %0,%w1
8913 mf%1 %0
8914 mt%0 %1
8915 mt%0 %1
8916 {cror 0,0,0|nop}"
8917 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8919 (define_expand "mov<mode>"
8920 [(set (match_operand:INT 0 "general_operand" "")
8921 (match_operand:INT 1 "any_operand" ""))]
8922 ""
8923 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8925 (define_insn "*movqi_internal"
8926 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8927 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8928 "gpc_reg_operand (operands[0], QImode)
8929 || gpc_reg_operand (operands[1], QImode)"
8930 "@
8931 mr %0,%1
8932 lbz%U1%X1 %0,%1
8933 stb%U0%X0 %1,%0
8934 {lil|li} %0,%1
8935 mf%1 %0
8936 mt%0 %1
8937 mt%0 %1
8938 {cror 0,0,0|nop}"
8939 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8940 \f
8941 ;; Here is how to move condition codes around. When we store CC data in
8942 ;; an integer register or memory, we store just the high-order 4 bits.
8943 ;; This lets us not shift in the most common case of CR0.
8944 (define_expand "movcc"
8945 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8946 (match_operand:CC 1 "nonimmediate_operand" ""))]
8947 ""
8948 "")
8950 (define_insn "*movcc_internal1"
8951 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8952 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8953 "register_operand (operands[0], CCmode)
8954 || register_operand (operands[1], CCmode)"
8955 "@
8956 mcrf %0,%1
8957 mtcrf 128,%1
8958 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8959 crxor %0,%0,%0
8960 mfcr %0%Q1
8961 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8962 mr %0,%1
8963 {lil|li} %0,%1
8964 mf%1 %0
8965 mt%0 %1
8966 mt%0 %1
8967 {l%U1%X1|lwz%U1%X1} %0,%1
8968 {st%U0%U1|stw%U0%U1} %1,%0"
8969 [(set (attr "type")
8970 (cond [(eq_attr "alternative" "0,3")
8971 (const_string "cr_logical")
8972 (eq_attr "alternative" "1,2")
8973 (const_string "mtcr")
8974 (eq_attr "alternative" "6,7,9")
8975 (const_string "integer")
8976 (eq_attr "alternative" "8")
8977 (const_string "mfjmpr")
8978 (eq_attr "alternative" "10")
8979 (const_string "mtjmpr")
8980 (eq_attr "alternative" "11")
8981 (const_string "load")
8982 (eq_attr "alternative" "12")
8983 (const_string "store")
8984 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8985 (const_string "mfcrf")
8986 ]
8987 (const_string "mfcr")))
8988 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8989 \f
8990 ;; For floating-point, we normally deal with the floating-point registers
8991 ;; unless -msoft-float is used. The sole exception is that parameter passing
8992 ;; can produce floating-point values in fixed-point registers. Unless the
8993 ;; value is a simple constant or already in memory, we deal with this by
8994 ;; allocating memory and copying the value explicitly via that memory location.
8995 (define_expand "movsf"
8996 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8997 (match_operand:SF 1 "any_operand" ""))]
8998 ""
8999 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9001 (define_split
9002 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9003 (match_operand:SF 1 "const_double_operand" ""))]
9004 "reload_completed
9005 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9006 || (GET_CODE (operands[0]) == SUBREG
9007 && GET_CODE (SUBREG_REG (operands[0])) == REG
9008 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9009 [(set (match_dup 2) (match_dup 3))]
9010 "
9011 {
9012 long l;
9013 REAL_VALUE_TYPE rv;
9015 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9016 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9018 if (! TARGET_POWERPC64)
9019 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9020 else
9021 operands[2] = gen_lowpart (SImode, operands[0]);
9023 operands[3] = gen_int_mode (l, SImode);
9024 }")
9026 (define_insn "*movsf_hardfloat"
9027 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9028 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9029 "(gpc_reg_operand (operands[0], SFmode)
9030 || gpc_reg_operand (operands[1], SFmode))
9031 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9032 "@
9033 mr %0,%1
9034 {l%U1%X1|lwz%U1%X1} %0,%1
9035 {st%U0%X0|stw%U0%X0} %1,%0
9036 fmr %0,%1
9037 lfs%U1%X1 %0,%1
9038 stfs%U0%X0 %1,%0
9039 mt%0 %1
9040 mt%0 %1
9041 mf%1 %0
9042 {cror 0,0,0|nop}
9043 #
9044 #"
9045 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9046 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9048 (define_insn "*movsf_softfloat"
9049 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9050 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9051 "(gpc_reg_operand (operands[0], SFmode)
9052 || gpc_reg_operand (operands[1], SFmode))
9053 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9054 "@
9055 mr %0,%1
9056 mt%0 %1
9057 mt%0 %1
9058 mf%1 %0
9059 {l%U1%X1|lwz%U1%X1} %0,%1
9060 {st%U0%X0|stw%U0%X0} %1,%0
9061 {lil|li} %0,%1
9062 {liu|lis} %0,%v1
9063 {cal|la} %0,%a1
9064 #
9065 #
9066 {cror 0,0,0|nop}"
9067 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9068 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9070 \f
9071 (define_expand "movdf"
9072 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9073 (match_operand:DF 1 "any_operand" ""))]
9074 ""
9075 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9077 (define_split
9078 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9079 (match_operand:DF 1 "const_int_operand" ""))]
9080 "! TARGET_POWERPC64 && reload_completed
9081 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9082 || (GET_CODE (operands[0]) == SUBREG
9083 && GET_CODE (SUBREG_REG (operands[0])) == REG
9084 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9085 [(set (match_dup 2) (match_dup 4))
9086 (set (match_dup 3) (match_dup 1))]
9087 "
9088 {
9089 int endian = (WORDS_BIG_ENDIAN == 0);
9090 HOST_WIDE_INT value = INTVAL (operands[1]);
9092 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9093 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9094 #if HOST_BITS_PER_WIDE_INT == 32
9095 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9096 #else
9097 operands[4] = GEN_INT (value >> 32);
9098 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9099 #endif
9100 }")
9102 (define_split
9103 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9104 (match_operand:DF 1 "const_double_operand" ""))]
9105 "! TARGET_POWERPC64 && reload_completed
9106 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9107 || (GET_CODE (operands[0]) == SUBREG
9108 && GET_CODE (SUBREG_REG (operands[0])) == REG
9109 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9110 [(set (match_dup 2) (match_dup 4))
9111 (set (match_dup 3) (match_dup 5))]
9112 "
9113 {
9114 int endian = (WORDS_BIG_ENDIAN == 0);
9115 long l[2];
9116 REAL_VALUE_TYPE rv;
9118 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9119 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9121 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9122 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9123 operands[4] = gen_int_mode (l[endian], SImode);
9124 operands[5] = gen_int_mode (l[1 - endian], SImode);
9125 }")
9127 (define_split
9128 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9129 (match_operand:DF 1 "const_double_operand" ""))]
9130 "TARGET_POWERPC64 && reload_completed
9131 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9132 || (GET_CODE (operands[0]) == SUBREG
9133 && GET_CODE (SUBREG_REG (operands[0])) == REG
9134 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9135 [(set (match_dup 2) (match_dup 3))]
9136 "
9137 {
9138 int endian = (WORDS_BIG_ENDIAN == 0);
9139 long l[2];
9140 REAL_VALUE_TYPE rv;
9141 #if HOST_BITS_PER_WIDE_INT >= 64
9142 HOST_WIDE_INT val;
9143 #endif
9145 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9146 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9148 operands[2] = gen_lowpart (DImode, operands[0]);
9149 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9150 #if HOST_BITS_PER_WIDE_INT >= 64
9151 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9152 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9154 operands[3] = gen_int_mode (val, DImode);
9155 #else
9156 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9157 #endif
9158 }")
9160 ;; Don't have reload use general registers to load a constant. First,
9161 ;; it might not work if the output operand is the equivalent of
9162 ;; a non-offsettable memref, but also it is less efficient than loading
9163 ;; the constant into an FP register, since it will probably be used there.
9164 ;; The "??" is a kludge until we can figure out a more reasonable way
9165 ;; of handling these non-offsettable values.
9166 (define_insn "*movdf_hardfloat32"
9167 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9168 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9169 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9170 && (gpc_reg_operand (operands[0], DFmode)
9171 || gpc_reg_operand (operands[1], DFmode))"
9172 "*
9173 {
9174 switch (which_alternative)
9175 {
9176 default:
9177 gcc_unreachable ();
9178 case 0:
9179 case 1:
9180 case 2:
9181 return \"#\";
9182 case 3:
9183 case 4:
9184 return \"xxlor %x0,%x1,%x1\";
9185 case 5:
9186 case 6:
9187 return \"lxsd%U1x %x0,%y1\";
9188 case 7:
9189 case 8:
9190 return \"stxsd%U0x %x1,%y0\";
9191 case 9:
9192 return \"fmr %0,%1\";
9193 case 10:
9194 return \"lfd%U1%X1 %0,%1\";
9195 case 11:
9196 return \"stfd%U0%X0 %1,%0\";
9197 case 12:
9198 return \"xxlxor %x0,%x0,%x0\";
9199 case 13:
9200 case 14:
9201 case 15:
9202 return \"#\";
9203 }
9204 }"
9205 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9206 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9208 (define_insn "*movdf_softfloat32"
9209 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9210 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9211 "! TARGET_POWERPC64
9212 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9213 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9214 && (gpc_reg_operand (operands[0], DFmode)
9215 || gpc_reg_operand (operands[1], DFmode))"
9216 "#"
9217 [(set_attr "type" "two,load,store,*,*,*")
9218 (set_attr "length" "8,8,8,8,12,16")])
9220 ; ld/std require word-aligned displacements -> 'Y' constraint.
9221 ; List Y->r and r->Y before r->r for reload.
9222 (define_insn "*movdf_hardfloat64_mfpgpr"
9223 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9224 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9225 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9226 && TARGET_DOUBLE_FLOAT
9227 && (gpc_reg_operand (operands[0], DFmode)
9228 || gpc_reg_operand (operands[1], DFmode))"
9229 "@
9230 std%U0%X0 %1,%0
9231 ld%U1%X1 %0,%1
9232 mr %0,%1
9233 xxlor %x0,%x1,%x1
9234 xxlor %x0,%x1,%x1
9235 lxsd%U1x %x0,%y1
9236 lxsd%U1x %x0,%y1
9237 stxsd%U0x %x1,%y0
9238 stxsd%U0x %x1,%y0
9239 fmr %0,%1
9240 lfd%U1%X1 %0,%1
9241 stfd%U0%X0 %1,%0
9242 xxlxor %x0,%x0,%x0
9243 mt%0 %1
9244 mf%1 %0
9245 {cror 0,0,0|nop}
9246 #
9247 #
9248 #
9249 mftgpr %0,%1
9250 mffgpr %0,%1"
9251 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9252 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9254 ; ld/std require word-aligned displacements -> 'Y' constraint.
9255 ; List Y->r and r->Y before r->r for reload.
9256 (define_insn "*movdf_hardfloat64"
9257 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9258 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9259 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9260 && TARGET_DOUBLE_FLOAT
9261 && (gpc_reg_operand (operands[0], DFmode)
9262 || gpc_reg_operand (operands[1], DFmode))"
9263 "@
9264 std%U0%X0 %1,%0
9265 ld%U1%X1 %0,%1
9266 mr %0,%1
9267 xxlor %x0,%x1,%x1
9268 xxlor %x0,%x1,%x1
9269 lxsd%U1x %x0,%y1
9270 lxsd%U1x %x0,%y1
9271 stxsd%U0x %x1,%y0
9272 stxsd%U0x %x1,%y0
9273 fmr %0,%1
9274 lfd%U1%X1 %0,%1
9275 stfd%U0%X0 %1,%0
9276 xxlxor %x0,%x0,%x0
9277 mt%0 %1
9278 mf%1 %0
9279 {cror 0,0,0|nop}
9280 #
9281 #
9282 #"
9283 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9284 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9286 (define_insn "*movdf_softfloat64"
9287 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9288 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9289 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9290 && (gpc_reg_operand (operands[0], DFmode)
9291 || gpc_reg_operand (operands[1], DFmode))"
9292 "@
9293 ld%U1%X1 %0,%1
9294 std%U0%X0 %1,%0
9295 mr %0,%1
9296 mt%0 %1
9297 mf%1 %0
9298 #
9299 #
9300 #
9301 {cror 0,0,0|nop}"
9302 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9303 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9304 \f
9305 (define_expand "movtf"
9306 [(set (match_operand:TF 0 "general_operand" "")
9307 (match_operand:TF 1 "any_operand" ""))]
9308 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9309 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9311 ; It's important to list the o->f and f->o moves before f->f because
9312 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9313 ; which doesn't make progress. Likewise r->Y must be before r->r.
9314 (define_insn_and_split "*movtf_internal"
9315 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9316 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9317 "!TARGET_IEEEQUAD
9318 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9319 && (gpc_reg_operand (operands[0], TFmode)
9320 || gpc_reg_operand (operands[1], TFmode))"
9321 "#"
9322 "&& reload_completed"
9323 [(pc)]
9324 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9325 [(set_attr "length" "8,8,8,20,20,16")])
9327 (define_insn_and_split "*movtf_softfloat"
9328 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9329 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9330 "!TARGET_IEEEQUAD
9331 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9332 && (gpc_reg_operand (operands[0], TFmode)
9333 || gpc_reg_operand (operands[1], TFmode))"
9334 "#"
9335 "&& reload_completed"
9336 [(pc)]
9337 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9338 [(set_attr "length" "20,20,16")])
9340 (define_expand "extenddftf2"
9341 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9342 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9343 "!TARGET_IEEEQUAD
9344 && TARGET_HARD_FLOAT
9345 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9346 && TARGET_LONG_DOUBLE_128"
9347 {
9348 if (TARGET_E500_DOUBLE)
9349 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9350 else
9351 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9352 DONE;
9353 })
9355 (define_expand "extenddftf2_fprs"
9356 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9357 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9358 (use (match_dup 2))])]
9359 "!TARGET_IEEEQUAD
9360 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9361 && TARGET_LONG_DOUBLE_128"
9362 {
9363 operands[2] = CONST0_RTX (DFmode);
9364 /* Generate GOT reference early for SVR4 PIC. */
9365 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9366 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9367 })
9369 (define_insn_and_split "*extenddftf2_internal"
9370 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9371 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9372 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9373 "!TARGET_IEEEQUAD
9374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9375 && TARGET_LONG_DOUBLE_128"
9376 "#"
9377 "&& reload_completed"
9378 [(pc)]
9379 {
9380 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9381 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9382 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9383 operands[1]);
9384 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9385 operands[2]);
9386 DONE;
9387 })
9389 (define_expand "extendsftf2"
9390 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9391 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9392 "!TARGET_IEEEQUAD
9393 && TARGET_HARD_FLOAT
9394 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9395 && TARGET_LONG_DOUBLE_128"
9396 {
9397 rtx tmp = gen_reg_rtx (DFmode);
9398 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9399 emit_insn (gen_extenddftf2 (operands[0], tmp));
9400 DONE;
9401 })
9403 (define_expand "trunctfdf2"
9404 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9405 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9406 "!TARGET_IEEEQUAD
9407 && TARGET_HARD_FLOAT
9408 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9409 && TARGET_LONG_DOUBLE_128"
9410 "")
9412 (define_insn_and_split "trunctfdf2_internal1"
9413 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9414 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9415 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9416 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9417 "@
9418 #
9419 fmr %0,%1"
9420 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9421 [(const_int 0)]
9422 {
9423 emit_note (NOTE_INSN_DELETED);
9424 DONE;
9425 }
9426 [(set_attr "type" "fp")])
9428 (define_insn "trunctfdf2_internal2"
9429 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9430 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9431 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9432 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9433 && TARGET_LONG_DOUBLE_128"
9434 "fadd %0,%1,%L1"
9435 [(set_attr "type" "fp")
9436 (set_attr "fp_type" "fp_addsub_d")])
9438 (define_expand "trunctfsf2"
9439 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9440 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9441 "!TARGET_IEEEQUAD
9442 && TARGET_HARD_FLOAT
9443 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9444 && TARGET_LONG_DOUBLE_128"
9445 {
9446 if (TARGET_E500_DOUBLE)
9447 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9448 else
9449 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9450 DONE;
9451 })
9453 (define_insn_and_split "trunctfsf2_fprs"
9454 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9455 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9456 (clobber (match_scratch:DF 2 "=d"))]
9457 "!TARGET_IEEEQUAD
9458 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9459 && TARGET_LONG_DOUBLE_128"
9460 "#"
9461 "&& reload_completed"
9462 [(set (match_dup 2)
9463 (float_truncate:DF (match_dup 1)))
9464 (set (match_dup 0)
9465 (float_truncate:SF (match_dup 2)))]
9466 "")
9468 (define_expand "floatsitf2"
9469 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9470 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9471 "!TARGET_IEEEQUAD
9472 && TARGET_HARD_FLOAT
9473 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9474 && TARGET_LONG_DOUBLE_128"
9475 {
9476 rtx tmp = gen_reg_rtx (DFmode);
9477 expand_float (tmp, operands[1], false);
9478 emit_insn (gen_extenddftf2 (operands[0], tmp));
9479 DONE;
9480 })
9482 ; fadd, but rounding towards zero.
9483 ; This is probably not the optimal code sequence.
9484 (define_insn "fix_trunc_helper"
9485 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9486 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9487 UNSPEC_FIX_TRUNC_TF))
9488 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9489 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9490 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9491 [(set_attr "type" "fp")
9492 (set_attr "length" "20")])
9494 (define_expand "fix_trunctfsi2"
9495 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9496 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9497 "!TARGET_IEEEQUAD
9498 && (TARGET_POWER2 || TARGET_POWERPC)
9499 && TARGET_HARD_FLOAT
9500 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9501 && TARGET_LONG_DOUBLE_128"
9502 {
9503 if (TARGET_E500_DOUBLE)
9504 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9505 else
9506 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9507 DONE;
9508 })
9510 (define_expand "fix_trunctfsi2_fprs"
9511 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9512 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9513 (clobber (match_dup 2))
9514 (clobber (match_dup 3))
9515 (clobber (match_dup 4))
9516 (clobber (match_dup 5))])]
9517 "!TARGET_IEEEQUAD
9518 && (TARGET_POWER2 || TARGET_POWERPC)
9519 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9520 {
9521 operands[2] = gen_reg_rtx (DFmode);
9522 operands[3] = gen_reg_rtx (DFmode);
9523 operands[4] = gen_reg_rtx (DImode);
9524 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9525 })
9527 (define_insn_and_split "*fix_trunctfsi2_internal"
9528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9529 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9530 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9531 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9532 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9533 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9534 "!TARGET_IEEEQUAD
9535 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9536 "#"
9537 ""
9538 [(pc)]
9539 {
9540 rtx lowword;
9541 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9543 gcc_assert (MEM_P (operands[5]));
9544 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9546 emit_insn (gen_fctiwz (operands[4], operands[2]));
9547 emit_move_insn (operands[5], operands[4]);
9548 emit_move_insn (operands[0], lowword);
9549 DONE;
9550 })
9552 (define_expand "negtf2"
9553 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9554 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9555 "!TARGET_IEEEQUAD
9556 && TARGET_HARD_FLOAT
9557 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9558 && TARGET_LONG_DOUBLE_128"
9559 "")
9561 (define_insn "negtf2_internal"
9562 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9563 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9564 "!TARGET_IEEEQUAD
9565 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9566 "*
9567 {
9568 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9569 return \"fneg %L0,%L1\;fneg %0,%1\";
9570 else
9571 return \"fneg %0,%1\;fneg %L0,%L1\";
9572 }"
9573 [(set_attr "type" "fp")
9574 (set_attr "length" "8")])
9576 (define_expand "abstf2"
9577 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9578 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9579 "!TARGET_IEEEQUAD
9580 && TARGET_HARD_FLOAT
9581 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9582 && TARGET_LONG_DOUBLE_128"
9583 "
9584 {
9585 rtx label = gen_label_rtx ();
9586 if (TARGET_E500_DOUBLE)
9587 {
9588 if (flag_finite_math_only && !flag_trapping_math)
9589 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9590 else
9591 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9592 }
9593 else
9594 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9595 emit_label (label);
9596 DONE;
9597 }")
9599 (define_expand "abstf2_internal"
9600 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9601 (match_operand:TF 1 "gpc_reg_operand" ""))
9602 (set (match_dup 3) (match_dup 5))
9603 (set (match_dup 5) (abs:DF (match_dup 5)))
9604 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9605 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9606 (label_ref (match_operand 2 "" ""))
9607 (pc)))
9608 (set (match_dup 6) (neg:DF (match_dup 6)))]
9609 "!TARGET_IEEEQUAD
9610 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9611 && TARGET_LONG_DOUBLE_128"
9612 "
9613 {
9614 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9615 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9616 operands[3] = gen_reg_rtx (DFmode);
9617 operands[4] = gen_reg_rtx (CCFPmode);
9618 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9619 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9620 }")
9621 \f
9622 ;; Next come the multi-word integer load and store and the load and store
9623 ;; multiple insns.
9625 ; List r->r after r->"o<>", otherwise reload will try to reload a
9626 ; non-offsettable address by using r->r which won't make progress.
9627 (define_insn "*movdi_internal32"
9628 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9629 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9630 "! TARGET_POWERPC64
9631 && (gpc_reg_operand (operands[0], DImode)
9632 || gpc_reg_operand (operands[1], DImode))"
9633 "@
9634 #
9635 #
9636 #
9637 fmr %0,%1
9638 lfd%U1%X1 %0,%1
9639 stfd%U0%X0 %1,%0
9640 #"
9641 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9643 (define_split
9644 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9645 (match_operand:DI 1 "const_int_operand" ""))]
9646 "! TARGET_POWERPC64 && reload_completed"
9647 [(set (match_dup 2) (match_dup 4))
9648 (set (match_dup 3) (match_dup 1))]
9649 "
9650 {
9651 HOST_WIDE_INT value = INTVAL (operands[1]);
9652 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9653 DImode);
9654 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9655 DImode);
9656 #if HOST_BITS_PER_WIDE_INT == 32
9657 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9658 #else
9659 operands[4] = GEN_INT (value >> 32);
9660 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9661 #endif
9662 }")
9664 (define_split
9665 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9666 (match_operand:DIFD 1 "input_operand" ""))]
9667 "reload_completed && !TARGET_POWERPC64
9668 && gpr_or_gpr_p (operands[0], operands[1])"
9669 [(pc)]
9670 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9672 (define_insn "*movdi_mfpgpr"
9673 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9674 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9675 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9676 && (gpc_reg_operand (operands[0], DImode)
9677 || gpc_reg_operand (operands[1], DImode))"
9678 "@
9679 mr %0,%1
9680 ld%U1%X1 %0,%1
9681 std%U0%X0 %1,%0
9682 li %0,%1
9683 lis %0,%v1
9684 #
9685 {cal|la} %0,%a1
9686 fmr %0,%1
9687 lfd%U1%X1 %0,%1
9688 stfd%U0%X0 %1,%0
9689 mf%1 %0
9690 mt%0 %1
9691 {cror 0,0,0|nop}
9692 mftgpr %0,%1
9693 mffgpr %0,%1"
9694 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9695 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9697 (define_insn "*movdi_internal64"
9698 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9699 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9700 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9701 && (gpc_reg_operand (operands[0], DImode)
9702 || gpc_reg_operand (operands[1], DImode))"
9703 "@
9704 mr %0,%1
9705 ld%U1%X1 %0,%1
9706 std%U0%X0 %1,%0
9707 li %0,%1
9708 lis %0,%v1
9709 #
9710 {cal|la} %0,%a1
9711 fmr %0,%1
9712 lfd%U1%X1 %0,%1
9713 stfd%U0%X0 %1,%0
9714 mf%1 %0
9715 mt%0 %1
9716 {cror 0,0,0|nop}"
9717 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9718 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9720 ;; immediate value valid for a single instruction hiding in a const_double
9721 (define_insn ""
9722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9723 (match_operand:DI 1 "const_double_operand" "F"))]
9724 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9725 && GET_CODE (operands[1]) == CONST_DOUBLE
9726 && num_insns_constant (operands[1], DImode) == 1"
9727 "*
9728 {
9729 return ((unsigned HOST_WIDE_INT)
9730 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9731 ? \"li %0,%1\" : \"lis %0,%v1\";
9732 }")
9734 ;; Generate all one-bits and clear left or right.
9735 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9736 (define_split
9737 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9738 (match_operand:DI 1 "mask64_operand" ""))]
9739 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9740 [(set (match_dup 0) (const_int -1))
9741 (set (match_dup 0)
9742 (and:DI (rotate:DI (match_dup 0)
9743 (const_int 0))
9744 (match_dup 1)))]
9745 "")
9747 ;; Split a load of a large constant into the appropriate five-instruction
9748 ;; sequence. Handle anything in a constant number of insns.
9749 ;; When non-easy constants can go in the TOC, this should use
9750 ;; easy_fp_constant predicate.
9751 (define_split
9752 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9753 (match_operand:DI 1 "const_int_operand" ""))]
9754 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9755 [(set (match_dup 0) (match_dup 2))
9756 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9757 "
9758 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9760 if (tem == operands[0])
9761 DONE;
9762 else
9763 FAIL;
9764 }")
9766 (define_split
9767 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9768 (match_operand:DI 1 "const_double_operand" ""))]
9769 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9770 [(set (match_dup 0) (match_dup 2))
9771 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9772 "
9773 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9775 if (tem == operands[0])
9776 DONE;
9777 else
9778 FAIL;
9779 }")
9780 \f
9781 ;; TImode is similar, except that we usually want to compute the address into
9782 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9783 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9785 ;; We say that MQ is clobbered in the last alternative because the first
9786 ;; alternative would never get used otherwise since it would need a reload
9787 ;; while the 2nd alternative would not. We put memory cases first so they
9788 ;; are preferred. Otherwise, we'd try to reload the output instead of
9789 ;; giving the SCRATCH mq.
9791 (define_insn "*movti_power"
9792 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9793 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9794 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9795 "TARGET_POWER && ! TARGET_POWERPC64
9796 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9797 "*
9798 {
9799 switch (which_alternative)
9800 {
9801 default:
9802 gcc_unreachable ();
9804 case 0:
9805 if (TARGET_STRING)
9806 return \"{stsi|stswi} %1,%P0,16\";
9807 case 1:
9808 case 2:
9809 return \"#\";
9810 case 3:
9811 /* If the address is not used in the output, we can use lsi. Otherwise,
9812 fall through to generating four loads. */
9813 if (TARGET_STRING
9814 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9815 return \"{lsi|lswi} %0,%P1,16\";
9816 /* ... fall through ... */
9817 case 4:
9818 case 5:
9819 return \"#\";
9820 }
9821 }"
9822 [(set_attr "type" "store,store,*,load,load,*")])
9824 (define_insn "*movti_string"
9825 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9826 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9827 "! TARGET_POWER && ! TARGET_POWERPC64
9828 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9829 "*
9830 {
9831 switch (which_alternative)
9832 {
9833 default:
9834 gcc_unreachable ();
9835 case 0:
9836 if (TARGET_STRING)
9837 return \"{stsi|stswi} %1,%P0,16\";
9838 case 1:
9839 case 2:
9840 return \"#\";
9841 case 3:
9842 /* If the address is not used in the output, we can use lsi. Otherwise,
9843 fall through to generating four loads. */
9844 if (TARGET_STRING
9845 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9846 return \"{lsi|lswi} %0,%P1,16\";
9847 /* ... fall through ... */
9848 case 4:
9849 case 5:
9850 return \"#\";
9851 }
9852 }"
9853 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9854 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9855 (const_string "always")
9856 (const_string "conditional")))])
9858 (define_insn "*movti_ppc64"
9859 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9860 (match_operand:TI 1 "input_operand" "r,r,m"))]
9861 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9862 || gpc_reg_operand (operands[1], TImode)))
9863 && VECTOR_MEM_NONE_P (TImode)"
9864 "#"
9865 [(set_attr "type" "*,store,load")])
9867 (define_split
9868 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9869 (match_operand:TI 1 "const_double_operand" ""))]
9870 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9871 [(set (match_dup 2) (match_dup 4))
9872 (set (match_dup 3) (match_dup 5))]
9873 "
9874 {
9875 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9876 TImode);
9877 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9878 TImode);
9879 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9880 {
9881 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9882 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9883 }
9884 else if (GET_CODE (operands[1]) == CONST_INT)
9885 {
9886 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9887 operands[5] = operands[1];
9888 }
9889 else
9890 FAIL;
9891 }")
9893 (define_split
9894 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9895 (match_operand:TI 1 "input_operand" ""))]
9896 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9897 && gpr_or_gpr_p (operands[0], operands[1])"
9898 [(pc)]
9899 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9900 \f
9901 (define_expand "load_multiple"
9902 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9903 (match_operand:SI 1 "" ""))
9904 (use (match_operand:SI 2 "" ""))])]
9905 "TARGET_STRING && !TARGET_POWERPC64"
9906 "
9907 {
9908 int regno;
9909 int count;
9910 rtx op1;
9911 int i;
9913 /* Support only loading a constant number of fixed-point registers from
9914 memory and only bother with this if more than two; the machine
9915 doesn't support more than eight. */
9916 if (GET_CODE (operands[2]) != CONST_INT
9917 || INTVAL (operands[2]) <= 2
9918 || INTVAL (operands[2]) > 8
9919 || GET_CODE (operands[1]) != MEM
9920 || GET_CODE (operands[0]) != REG
9921 || REGNO (operands[0]) >= 32)
9922 FAIL;
9924 count = INTVAL (operands[2]);
9925 regno = REGNO (operands[0]);
9927 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9928 op1 = replace_equiv_address (operands[1],
9929 force_reg (SImode, XEXP (operands[1], 0)));
9931 for (i = 0; i < count; i++)
9932 XVECEXP (operands[3], 0, i)
9933 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9934 adjust_address_nv (op1, SImode, i * 4));
9935 }")
9937 (define_insn "*ldmsi8"
9938 [(match_parallel 0 "load_multiple_operation"
9939 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9940 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9941 (set (match_operand:SI 3 "gpc_reg_operand" "")
9942 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9943 (set (match_operand:SI 4 "gpc_reg_operand" "")
9944 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9945 (set (match_operand:SI 5 "gpc_reg_operand" "")
9946 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9947 (set (match_operand:SI 6 "gpc_reg_operand" "")
9948 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9949 (set (match_operand:SI 7 "gpc_reg_operand" "")
9950 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9951 (set (match_operand:SI 8 "gpc_reg_operand" "")
9952 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9953 (set (match_operand:SI 9 "gpc_reg_operand" "")
9954 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9955 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9956 "*
9957 { return rs6000_output_load_multiple (operands); }"
9958 [(set_attr "type" "load_ux")
9959 (set_attr "length" "32")])
9961 (define_insn "*ldmsi7"
9962 [(match_parallel 0 "load_multiple_operation"
9963 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9964 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9965 (set (match_operand:SI 3 "gpc_reg_operand" "")
9966 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9967 (set (match_operand:SI 4 "gpc_reg_operand" "")
9968 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9969 (set (match_operand:SI 5 "gpc_reg_operand" "")
9970 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9971 (set (match_operand:SI 6 "gpc_reg_operand" "")
9972 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9973 (set (match_operand:SI 7 "gpc_reg_operand" "")
9974 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9975 (set (match_operand:SI 8 "gpc_reg_operand" "")
9976 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9977 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9978 "*
9979 { return rs6000_output_load_multiple (operands); }"
9980 [(set_attr "type" "load_ux")
9981 (set_attr "length" "32")])
9983 (define_insn "*ldmsi6"
9984 [(match_parallel 0 "load_multiple_operation"
9985 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9986 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9987 (set (match_operand:SI 3 "gpc_reg_operand" "")
9988 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9989 (set (match_operand:SI 4 "gpc_reg_operand" "")
9990 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9991 (set (match_operand:SI 5 "gpc_reg_operand" "")
9992 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9993 (set (match_operand:SI 6 "gpc_reg_operand" "")
9994 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9995 (set (match_operand:SI 7 "gpc_reg_operand" "")
9996 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9997 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9998 "*
9999 { return rs6000_output_load_multiple (operands); }"
10000 [(set_attr "type" "load_ux")
10001 (set_attr "length" "32")])
10003 (define_insn "*ldmsi5"
10004 [(match_parallel 0 "load_multiple_operation"
10005 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10006 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10007 (set (match_operand:SI 3 "gpc_reg_operand" "")
10008 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10009 (set (match_operand:SI 4 "gpc_reg_operand" "")
10010 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10011 (set (match_operand:SI 5 "gpc_reg_operand" "")
10012 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10013 (set (match_operand:SI 6 "gpc_reg_operand" "")
10014 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10015 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10016 "*
10017 { return rs6000_output_load_multiple (operands); }"
10018 [(set_attr "type" "load_ux")
10019 (set_attr "length" "32")])
10021 (define_insn "*ldmsi4"
10022 [(match_parallel 0 "load_multiple_operation"
10023 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10024 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10025 (set (match_operand:SI 3 "gpc_reg_operand" "")
10026 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10027 (set (match_operand:SI 4 "gpc_reg_operand" "")
10028 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10029 (set (match_operand:SI 5 "gpc_reg_operand" "")
10030 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10031 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10032 "*
10033 { return rs6000_output_load_multiple (operands); }"
10034 [(set_attr "type" "load_ux")
10035 (set_attr "length" "32")])
10037 (define_insn "*ldmsi3"
10038 [(match_parallel 0 "load_multiple_operation"
10039 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10040 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10041 (set (match_operand:SI 3 "gpc_reg_operand" "")
10042 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10043 (set (match_operand:SI 4 "gpc_reg_operand" "")
10044 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10045 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10046 "*
10047 { return rs6000_output_load_multiple (operands); }"
10048 [(set_attr "type" "load_ux")
10049 (set_attr "length" "32")])
10051 (define_expand "store_multiple"
10052 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10053 (match_operand:SI 1 "" ""))
10054 (clobber (scratch:SI))
10055 (use (match_operand:SI 2 "" ""))])]
10056 "TARGET_STRING && !TARGET_POWERPC64"
10057 "
10058 {
10059 int regno;
10060 int count;
10061 rtx to;
10062 rtx op0;
10063 int i;
10065 /* Support only storing a constant number of fixed-point registers to
10066 memory and only bother with this if more than two; the machine
10067 doesn't support more than eight. */
10068 if (GET_CODE (operands[2]) != CONST_INT
10069 || INTVAL (operands[2]) <= 2
10070 || INTVAL (operands[2]) > 8
10071 || GET_CODE (operands[0]) != MEM
10072 || GET_CODE (operands[1]) != REG
10073 || REGNO (operands[1]) >= 32)
10074 FAIL;
10076 count = INTVAL (operands[2]);
10077 regno = REGNO (operands[1]);
10079 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10080 to = force_reg (SImode, XEXP (operands[0], 0));
10081 op0 = replace_equiv_address (operands[0], to);
10083 XVECEXP (operands[3], 0, 0)
10084 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10085 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10086 gen_rtx_SCRATCH (SImode));
10088 for (i = 1; i < count; i++)
10089 XVECEXP (operands[3], 0, i + 1)
10090 = gen_rtx_SET (VOIDmode,
10091 adjust_address_nv (op0, SImode, i * 4),
10092 gen_rtx_REG (SImode, regno + i));
10093 }")
10095 (define_insn "*stmsi8"
10096 [(match_parallel 0 "store_multiple_operation"
10097 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10098 (match_operand:SI 2 "gpc_reg_operand" "r"))
10099 (clobber (match_scratch:SI 3 "=X"))
10100 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10101 (match_operand:SI 4 "gpc_reg_operand" "r"))
10102 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10103 (match_operand:SI 5 "gpc_reg_operand" "r"))
10104 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10105 (match_operand:SI 6 "gpc_reg_operand" "r"))
10106 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10107 (match_operand:SI 7 "gpc_reg_operand" "r"))
10108 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10109 (match_operand:SI 8 "gpc_reg_operand" "r"))
10110 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10111 (match_operand:SI 9 "gpc_reg_operand" "r"))
10112 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10113 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10114 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10115 "{stsi|stswi} %2,%1,%O0"
10116 [(set_attr "type" "store_ux")
10117 (set_attr "cell_micro" "always")])
10119 (define_insn "*stmsi7"
10120 [(match_parallel 0 "store_multiple_operation"
10121 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10122 (match_operand:SI 2 "gpc_reg_operand" "r"))
10123 (clobber (match_scratch:SI 3 "=X"))
10124 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10125 (match_operand:SI 4 "gpc_reg_operand" "r"))
10126 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10127 (match_operand:SI 5 "gpc_reg_operand" "r"))
10128 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10129 (match_operand:SI 6 "gpc_reg_operand" "r"))
10130 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10131 (match_operand:SI 7 "gpc_reg_operand" "r"))
10132 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10133 (match_operand:SI 8 "gpc_reg_operand" "r"))
10134 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10135 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10136 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10137 "{stsi|stswi} %2,%1,%O0"
10138 [(set_attr "type" "store_ux")
10139 (set_attr "cell_micro" "always")])
10141 (define_insn "*stmsi6"
10142 [(match_parallel 0 "store_multiple_operation"
10143 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10144 (match_operand:SI 2 "gpc_reg_operand" "r"))
10145 (clobber (match_scratch:SI 3 "=X"))
10146 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10147 (match_operand:SI 4 "gpc_reg_operand" "r"))
10148 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10149 (match_operand:SI 5 "gpc_reg_operand" "r"))
10150 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10151 (match_operand:SI 6 "gpc_reg_operand" "r"))
10152 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10153 (match_operand:SI 7 "gpc_reg_operand" "r"))
10154 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10155 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10156 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10157 "{stsi|stswi} %2,%1,%O0"
10158 [(set_attr "type" "store_ux")
10159 (set_attr "cell_micro" "always")])
10161 (define_insn "*stmsi5"
10162 [(match_parallel 0 "store_multiple_operation"
10163 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10164 (match_operand:SI 2 "gpc_reg_operand" "r"))
10165 (clobber (match_scratch:SI 3 "=X"))
10166 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10167 (match_operand:SI 4 "gpc_reg_operand" "r"))
10168 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10169 (match_operand:SI 5 "gpc_reg_operand" "r"))
10170 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10171 (match_operand:SI 6 "gpc_reg_operand" "r"))
10172 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10173 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10174 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10175 "{stsi|stswi} %2,%1,%O0"
10176 [(set_attr "type" "store_ux")
10177 (set_attr "cell_micro" "always")])
10179 (define_insn "*stmsi4"
10180 [(match_parallel 0 "store_multiple_operation"
10181 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10182 (match_operand:SI 2 "gpc_reg_operand" "r"))
10183 (clobber (match_scratch:SI 3 "=X"))
10184 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10185 (match_operand:SI 4 "gpc_reg_operand" "r"))
10186 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10187 (match_operand:SI 5 "gpc_reg_operand" "r"))
10188 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10189 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10190 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10191 "{stsi|stswi} %2,%1,%O0"
10192 [(set_attr "type" "store_ux")
10193 (set_attr "cell_micro" "always")])
10195 (define_insn "*stmsi3"
10196 [(match_parallel 0 "store_multiple_operation"
10197 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10198 (match_operand:SI 2 "gpc_reg_operand" "r"))
10199 (clobber (match_scratch:SI 3 "=X"))
10200 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10201 (match_operand:SI 4 "gpc_reg_operand" "r"))
10202 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10203 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10204 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10205 "{stsi|stswi} %2,%1,%O0"
10206 [(set_attr "type" "store_ux")
10207 (set_attr "cell_micro" "always")])
10209 (define_insn "*stmsi8_power"
10210 [(match_parallel 0 "store_multiple_operation"
10211 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10212 (match_operand:SI 2 "gpc_reg_operand" "r"))
10213 (clobber (match_scratch:SI 3 "=q"))
10214 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10215 (match_operand:SI 4 "gpc_reg_operand" "r"))
10216 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10217 (match_operand:SI 5 "gpc_reg_operand" "r"))
10218 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10219 (match_operand:SI 6 "gpc_reg_operand" "r"))
10220 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10221 (match_operand:SI 7 "gpc_reg_operand" "r"))
10222 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10223 (match_operand:SI 8 "gpc_reg_operand" "r"))
10224 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10225 (match_operand:SI 9 "gpc_reg_operand" "r"))
10226 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10227 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10228 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10229 "{stsi|stswi} %2,%1,%O0"
10230 [(set_attr "type" "store_ux")
10231 (set_attr "cell_micro" "always")])
10233 (define_insn "*stmsi7_power"
10234 [(match_parallel 0 "store_multiple_operation"
10235 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10236 (match_operand:SI 2 "gpc_reg_operand" "r"))
10237 (clobber (match_scratch:SI 3 "=q"))
10238 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10239 (match_operand:SI 4 "gpc_reg_operand" "r"))
10240 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10241 (match_operand:SI 5 "gpc_reg_operand" "r"))
10242 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10243 (match_operand:SI 6 "gpc_reg_operand" "r"))
10244 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10245 (match_operand:SI 7 "gpc_reg_operand" "r"))
10246 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10247 (match_operand:SI 8 "gpc_reg_operand" "r"))
10248 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10249 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10250 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10251 "{stsi|stswi} %2,%1,%O0"
10252 [(set_attr "type" "store_ux")
10253 (set_attr "cell_micro" "always")])
10255 (define_insn "*stmsi6_power"
10256 [(match_parallel 0 "store_multiple_operation"
10257 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10258 (match_operand:SI 2 "gpc_reg_operand" "r"))
10259 (clobber (match_scratch:SI 3 "=q"))
10260 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10261 (match_operand:SI 4 "gpc_reg_operand" "r"))
10262 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10263 (match_operand:SI 5 "gpc_reg_operand" "r"))
10264 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10265 (match_operand:SI 6 "gpc_reg_operand" "r"))
10266 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10267 (match_operand:SI 7 "gpc_reg_operand" "r"))
10268 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10269 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10270 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10271 "{stsi|stswi} %2,%1,%O0"
10272 [(set_attr "type" "store_ux")
10273 (set_attr "cell_micro" "always")])
10275 (define_insn "*stmsi5_power"
10276 [(match_parallel 0 "store_multiple_operation"
10277 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10278 (match_operand:SI 2 "gpc_reg_operand" "r"))
10279 (clobber (match_scratch:SI 3 "=q"))
10280 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10281 (match_operand:SI 4 "gpc_reg_operand" "r"))
10282 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10283 (match_operand:SI 5 "gpc_reg_operand" "r"))
10284 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10285 (match_operand:SI 6 "gpc_reg_operand" "r"))
10286 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10287 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10288 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10289 "{stsi|stswi} %2,%1,%O0"
10290 [(set_attr "type" "store_ux")
10291 (set_attr "cell_micro" "always")])
10293 (define_insn "*stmsi4_power"
10294 [(match_parallel 0 "store_multiple_operation"
10295 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10296 (match_operand:SI 2 "gpc_reg_operand" "r"))
10297 (clobber (match_scratch:SI 3 "=q"))
10298 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10299 (match_operand:SI 4 "gpc_reg_operand" "r"))
10300 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10301 (match_operand:SI 5 "gpc_reg_operand" "r"))
10302 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10303 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10304 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10305 "{stsi|stswi} %2,%1,%O0"
10306 [(set_attr "type" "store_ux")
10307 (set_attr "cell_micro" "always")])
10309 (define_insn "*stmsi3_power"
10310 [(match_parallel 0 "store_multiple_operation"
10311 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10312 (match_operand:SI 2 "gpc_reg_operand" "r"))
10313 (clobber (match_scratch:SI 3 "=q"))
10314 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10315 (match_operand:SI 4 "gpc_reg_operand" "r"))
10316 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10317 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10318 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10319 "{stsi|stswi} %2,%1,%O0"
10320 [(set_attr "type" "store_ux")
10321 (set_attr "cell_micro" "always")])
10322 \f
10323 (define_expand "setmemsi"
10324 [(parallel [(set (match_operand:BLK 0 "" "")
10325 (match_operand 2 "const_int_operand" ""))
10326 (use (match_operand:SI 1 "" ""))
10327 (use (match_operand:SI 3 "" ""))])]
10328 ""
10329 "
10330 {
10331 /* If value to set is not zero, use the library routine. */
10332 if (operands[2] != const0_rtx)
10333 FAIL;
10335 if (expand_block_clear (operands))
10336 DONE;
10337 else
10338 FAIL;
10339 }")
10341 ;; String/block move insn.
10342 ;; Argument 0 is the destination
10343 ;; Argument 1 is the source
10344 ;; Argument 2 is the length
10345 ;; Argument 3 is the alignment
10347 (define_expand "movmemsi"
10348 [(parallel [(set (match_operand:BLK 0 "" "")
10349 (match_operand:BLK 1 "" ""))
10350 (use (match_operand:SI 2 "" ""))
10351 (use (match_operand:SI 3 "" ""))])]
10352 ""
10353 "
10354 {
10355 if (expand_block_move (operands))
10356 DONE;
10357 else
10358 FAIL;
10359 }")
10361 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10362 ;; register allocator doesn't have a clue about allocating 8 word registers.
10363 ;; rD/rS = r5 is preferred, efficient form.
10364 (define_expand "movmemsi_8reg"
10365 [(parallel [(set (match_operand 0 "" "")
10366 (match_operand 1 "" ""))
10367 (use (match_operand 2 "" ""))
10368 (use (match_operand 3 "" ""))
10369 (clobber (reg:SI 5))
10370 (clobber (reg:SI 6))
10371 (clobber (reg:SI 7))
10372 (clobber (reg:SI 8))
10373 (clobber (reg:SI 9))
10374 (clobber (reg:SI 10))
10375 (clobber (reg:SI 11))
10376 (clobber (reg:SI 12))
10377 (clobber (match_scratch:SI 4 ""))])]
10378 "TARGET_STRING"
10379 "")
10381 (define_insn ""
10382 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10383 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10384 (use (match_operand:SI 2 "immediate_operand" "i"))
10385 (use (match_operand:SI 3 "immediate_operand" "i"))
10386 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10387 (clobber (reg:SI 6))
10388 (clobber (reg:SI 7))
10389 (clobber (reg:SI 8))
10390 (clobber (reg:SI 9))
10391 (clobber (reg:SI 10))
10392 (clobber (reg:SI 11))
10393 (clobber (reg:SI 12))
10394 (clobber (match_scratch:SI 5 "=q"))]
10395 "TARGET_STRING && TARGET_POWER
10396 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10397 || INTVAL (operands[2]) == 0)
10398 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10399 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10400 && REGNO (operands[4]) == 5"
10401 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10402 [(set_attr "type" "store_ux")
10403 (set_attr "cell_micro" "always")
10404 (set_attr "length" "8")])
10406 (define_insn ""
10407 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10408 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10409 (use (match_operand:SI 2 "immediate_operand" "i"))
10410 (use (match_operand:SI 3 "immediate_operand" "i"))
10411 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10412 (clobber (reg:SI 6))
10413 (clobber (reg:SI 7))
10414 (clobber (reg:SI 8))
10415 (clobber (reg:SI 9))
10416 (clobber (reg:SI 10))
10417 (clobber (reg:SI 11))
10418 (clobber (reg:SI 12))
10419 (clobber (match_scratch:SI 5 "=X"))]
10420 "TARGET_STRING && ! TARGET_POWER
10421 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10422 || INTVAL (operands[2]) == 0)
10423 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10424 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10425 && REGNO (operands[4]) == 5"
10426 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10427 [(set_attr "type" "store_ux")
10428 (set_attr "cell_micro" "always")
10429 (set_attr "length" "8")])
10431 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10432 ;; register allocator doesn't have a clue about allocating 6 word registers.
10433 ;; rD/rS = r5 is preferred, efficient form.
10434 (define_expand "movmemsi_6reg"
10435 [(parallel [(set (match_operand 0 "" "")
10436 (match_operand 1 "" ""))
10437 (use (match_operand 2 "" ""))
10438 (use (match_operand 3 "" ""))
10439 (clobber (reg:SI 5))
10440 (clobber (reg:SI 6))
10441 (clobber (reg:SI 7))
10442 (clobber (reg:SI 8))
10443 (clobber (reg:SI 9))
10444 (clobber (reg:SI 10))
10445 (clobber (match_scratch:SI 4 ""))])]
10446 "TARGET_STRING"
10447 "")
10449 (define_insn ""
10450 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10451 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10452 (use (match_operand:SI 2 "immediate_operand" "i"))
10453 (use (match_operand:SI 3 "immediate_operand" "i"))
10454 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10455 (clobber (reg:SI 6))
10456 (clobber (reg:SI 7))
10457 (clobber (reg:SI 8))
10458 (clobber (reg:SI 9))
10459 (clobber (reg:SI 10))
10460 (clobber (match_scratch:SI 5 "=q"))]
10461 "TARGET_STRING && TARGET_POWER
10462 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10463 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10464 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10465 && REGNO (operands[4]) == 5"
10466 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10467 [(set_attr "type" "store_ux")
10468 (set_attr "cell_micro" "always")
10469 (set_attr "length" "8")])
10471 (define_insn ""
10472 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10473 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10474 (use (match_operand:SI 2 "immediate_operand" "i"))
10475 (use (match_operand:SI 3 "immediate_operand" "i"))
10476 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10477 (clobber (reg:SI 6))
10478 (clobber (reg:SI 7))
10479 (clobber (reg:SI 8))
10480 (clobber (reg:SI 9))
10481 (clobber (reg:SI 10))
10482 (clobber (match_scratch:SI 5 "=X"))]
10483 "TARGET_STRING && ! TARGET_POWER
10484 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10485 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10486 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10487 && REGNO (operands[4]) == 5"
10488 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10489 [(set_attr "type" "store_ux")
10490 (set_attr "cell_micro" "always")
10491 (set_attr "length" "8")])
10493 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10494 ;; problems with TImode.
10495 ;; rD/rS = r5 is preferred, efficient form.
10496 (define_expand "movmemsi_4reg"
10497 [(parallel [(set (match_operand 0 "" "")
10498 (match_operand 1 "" ""))
10499 (use (match_operand 2 "" ""))
10500 (use (match_operand 3 "" ""))
10501 (clobber (reg:SI 5))
10502 (clobber (reg:SI 6))
10503 (clobber (reg:SI 7))
10504 (clobber (reg:SI 8))
10505 (clobber (match_scratch:SI 4 ""))])]
10506 "TARGET_STRING"
10507 "")
10509 (define_insn ""
10510 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10511 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10512 (use (match_operand:SI 2 "immediate_operand" "i"))
10513 (use (match_operand:SI 3 "immediate_operand" "i"))
10514 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10515 (clobber (reg:SI 6))
10516 (clobber (reg:SI 7))
10517 (clobber (reg:SI 8))
10518 (clobber (match_scratch:SI 5 "=q"))]
10519 "TARGET_STRING && TARGET_POWER
10520 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10521 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10522 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10523 && REGNO (operands[4]) == 5"
10524 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10525 [(set_attr "type" "store_ux")
10526 (set_attr "cell_micro" "always")
10527 (set_attr "length" "8")])
10529 (define_insn ""
10530 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10531 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10532 (use (match_operand:SI 2 "immediate_operand" "i"))
10533 (use (match_operand:SI 3 "immediate_operand" "i"))
10534 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10535 (clobber (reg:SI 6))
10536 (clobber (reg:SI 7))
10537 (clobber (reg:SI 8))
10538 (clobber (match_scratch:SI 5 "=X"))]
10539 "TARGET_STRING && ! TARGET_POWER
10540 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10541 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10542 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10543 && REGNO (operands[4]) == 5"
10544 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10545 [(set_attr "type" "store_ux")
10546 (set_attr "cell_micro" "always")
10547 (set_attr "length" "8")])
10549 ;; Move up to 8 bytes at a time.
10550 (define_expand "movmemsi_2reg"
10551 [(parallel [(set (match_operand 0 "" "")
10552 (match_operand 1 "" ""))
10553 (use (match_operand 2 "" ""))
10554 (use (match_operand 3 "" ""))
10555 (clobber (match_scratch:DI 4 ""))
10556 (clobber (match_scratch:SI 5 ""))])]
10557 "TARGET_STRING && ! TARGET_POWERPC64"
10558 "")
10560 (define_insn ""
10561 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10562 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10563 (use (match_operand:SI 2 "immediate_operand" "i"))
10564 (use (match_operand:SI 3 "immediate_operand" "i"))
10565 (clobber (match_scratch:DI 4 "=&r"))
10566 (clobber (match_scratch:SI 5 "=q"))]
10567 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10568 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10569 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10570 [(set_attr "type" "store_ux")
10571 (set_attr "cell_micro" "always")
10572 (set_attr "length" "8")])
10574 (define_insn ""
10575 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10576 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10577 (use (match_operand:SI 2 "immediate_operand" "i"))
10578 (use (match_operand:SI 3 "immediate_operand" "i"))
10579 (clobber (match_scratch:DI 4 "=&r"))
10580 (clobber (match_scratch:SI 5 "=X"))]
10581 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10582 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10583 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10584 [(set_attr "type" "store_ux")
10585 (set_attr "cell_micro" "always")
10586 (set_attr "length" "8")])
10588 ;; Move up to 4 bytes at a time.
10589 (define_expand "movmemsi_1reg"
10590 [(parallel [(set (match_operand 0 "" "")
10591 (match_operand 1 "" ""))
10592 (use (match_operand 2 "" ""))
10593 (use (match_operand 3 "" ""))
10594 (clobber (match_scratch:SI 4 ""))
10595 (clobber (match_scratch:SI 5 ""))])]
10596 "TARGET_STRING"
10597 "")
10599 (define_insn ""
10600 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10601 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10602 (use (match_operand:SI 2 "immediate_operand" "i"))
10603 (use (match_operand:SI 3 "immediate_operand" "i"))
10604 (clobber (match_scratch:SI 4 "=&r"))
10605 (clobber (match_scratch:SI 5 "=q"))]
10606 "TARGET_STRING && TARGET_POWER
10607 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10608 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10609 [(set_attr "type" "store_ux")
10610 (set_attr "cell_micro" "always")
10611 (set_attr "length" "8")])
10613 (define_insn ""
10614 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10615 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10616 (use (match_operand:SI 2 "immediate_operand" "i"))
10617 (use (match_operand:SI 3 "immediate_operand" "i"))
10618 (clobber (match_scratch:SI 4 "=&r"))
10619 (clobber (match_scratch:SI 5 "=X"))]
10620 "TARGET_STRING && ! TARGET_POWER
10621 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10622 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10623 [(set_attr "type" "store_ux")
10624 (set_attr "cell_micro" "always")
10625 (set_attr "length" "8")])
10626 \f
10627 ;; Define insns that do load or store with update. Some of these we can
10628 ;; get by using pre-decrement or pre-increment, but the hardware can also
10629 ;; do cases where the increment is not the size of the object.
10630 ;;
10631 ;; In all these cases, we use operands 0 and 1 for the register being
10632 ;; incremented because those are the operands that local-alloc will
10633 ;; tie and these are the pair most likely to be tieable (and the ones
10634 ;; that will benefit the most).
10636 (define_insn "*movdi_update1"
10637 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10638 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10639 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10640 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10641 (plus:DI (match_dup 1) (match_dup 2)))]
10642 "TARGET_POWERPC64 && TARGET_UPDATE
10643 && (!avoiding_indexed_address_p (DImode)
10644 || !gpc_reg_operand (operands[2], DImode))"
10645 "@
10646 ldux %3,%0,%2
10647 ldu %3,%2(%0)"
10648 [(set_attr "type" "load_ux,load_u")])
10650 (define_insn "movdi_<mode>_update"
10651 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10652 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10653 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10654 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10655 (plus:P (match_dup 1) (match_dup 2)))]
10656 "TARGET_POWERPC64 && TARGET_UPDATE
10657 && (!avoiding_indexed_address_p (Pmode)
10658 || !gpc_reg_operand (operands[2], Pmode)
10659 || (REG_P (operands[0])
10660 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10661 "@
10662 stdux %3,%0,%2
10663 stdu %3,%2(%0)"
10664 [(set_attr "type" "store_ux,store_u")])
10666 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10667 ;; needed for stack allocation, even if the user passes -mno-update.
10668 (define_insn "movdi_<mode>_update_stack"
10669 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10670 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10671 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10672 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10673 (plus:P (match_dup 1) (match_dup 2)))]
10674 "TARGET_POWERPC64"
10675 "@
10676 stdux %3,%0,%2
10677 stdu %3,%2(%0)"
10678 [(set_attr "type" "store_ux,store_u")])
10680 (define_insn "*movsi_update1"
10681 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10682 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10683 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10684 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10685 (plus:SI (match_dup 1) (match_dup 2)))]
10686 "TARGET_UPDATE
10687 && (!avoiding_indexed_address_p (SImode)
10688 || !gpc_reg_operand (operands[2], SImode))"
10689 "@
10690 {lux|lwzux} %3,%0,%2
10691 {lu|lwzu} %3,%2(%0)"
10692 [(set_attr "type" "load_ux,load_u")])
10694 (define_insn "*movsi_update2"
10695 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10696 (sign_extend:DI
10697 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10698 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10699 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10700 (plus:DI (match_dup 1) (match_dup 2)))]
10701 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10702 && !avoiding_indexed_address_p (DImode)"
10703 "lwaux %3,%0,%2"
10704 [(set_attr "type" "load_ext_ux")])
10706 (define_insn "movsi_update"
10707 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10708 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10709 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10710 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10711 (plus:SI (match_dup 1) (match_dup 2)))]
10712 "TARGET_UPDATE
10713 && (!avoiding_indexed_address_p (SImode)
10714 || !gpc_reg_operand (operands[2], SImode)
10715 || (REG_P (operands[0])
10716 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10717 "@
10718 {stux|stwux} %3,%0,%2
10719 {stu|stwu} %3,%2(%0)"
10720 [(set_attr "type" "store_ux,store_u")])
10722 ;; This is an unconditional pattern; needed for stack allocation, even
10723 ;; if the user passes -mno-update.
10724 (define_insn "movsi_update_stack"
10725 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10726 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10727 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10728 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10729 (plus:SI (match_dup 1) (match_dup 2)))]
10730 ""
10731 "@
10732 {stux|stwux} %3,%0,%2
10733 {stu|stwu} %3,%2(%0)"
10734 [(set_attr "type" "store_ux,store_u")])
10736 (define_insn "*movhi_update1"
10737 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10738 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10739 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10740 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10741 (plus:SI (match_dup 1) (match_dup 2)))]
10742 "TARGET_UPDATE
10743 && (!avoiding_indexed_address_p (SImode)
10744 || !gpc_reg_operand (operands[2], SImode))"
10745 "@
10746 lhzux %3,%0,%2
10747 lhzu %3,%2(%0)"
10748 [(set_attr "type" "load_ux,load_u")])
10750 (define_insn "*movhi_update2"
10751 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10752 (zero_extend:SI
10753 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10754 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10755 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10756 (plus:SI (match_dup 1) (match_dup 2)))]
10757 "TARGET_UPDATE
10758 && (!avoiding_indexed_address_p (SImode)
10759 || !gpc_reg_operand (operands[2], SImode))"
10760 "@
10761 lhzux %3,%0,%2
10762 lhzu %3,%2(%0)"
10763 [(set_attr "type" "load_ux,load_u")])
10765 (define_insn "*movhi_update3"
10766 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10767 (sign_extend:SI
10768 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10769 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10770 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10771 (plus:SI (match_dup 1) (match_dup 2)))]
10772 "TARGET_UPDATE && rs6000_gen_cell_microcode
10773 && (!avoiding_indexed_address_p (SImode)
10774 || !gpc_reg_operand (operands[2], SImode))"
10775 "@
10776 lhaux %3,%0,%2
10777 lhau %3,%2(%0)"
10778 [(set_attr "type" "load_ext_ux,load_ext_u")])
10780 (define_insn "*movhi_update4"
10781 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10782 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10783 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10784 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10785 (plus:SI (match_dup 1) (match_dup 2)))]
10786 "TARGET_UPDATE
10787 && (!avoiding_indexed_address_p (SImode)
10788 || !gpc_reg_operand (operands[2], SImode))"
10789 "@
10790 sthux %3,%0,%2
10791 sthu %3,%2(%0)"
10792 [(set_attr "type" "store_ux,store_u")])
10794 (define_insn "*movqi_update1"
10795 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10796 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10797 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10798 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10799 (plus:SI (match_dup 1) (match_dup 2)))]
10800 "TARGET_UPDATE
10801 && (!avoiding_indexed_address_p (SImode)
10802 || !gpc_reg_operand (operands[2], SImode))"
10803 "@
10804 lbzux %3,%0,%2
10805 lbzu %3,%2(%0)"
10806 [(set_attr "type" "load_ux,load_u")])
10808 (define_insn "*movqi_update2"
10809 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10810 (zero_extend:SI
10811 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10812 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10813 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10814 (plus:SI (match_dup 1) (match_dup 2)))]
10815 "TARGET_UPDATE
10816 && (!avoiding_indexed_address_p (SImode)
10817 || !gpc_reg_operand (operands[2], SImode))"
10818 "@
10819 lbzux %3,%0,%2
10820 lbzu %3,%2(%0)"
10821 [(set_attr "type" "load_ux,load_u")])
10823 (define_insn "*movqi_update3"
10824 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10825 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10826 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10827 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10828 (plus:SI (match_dup 1) (match_dup 2)))]
10829 "TARGET_UPDATE
10830 && (!avoiding_indexed_address_p (SImode)
10831 || !gpc_reg_operand (operands[2], SImode))"
10832 "@
10833 stbux %3,%0,%2
10834 stbu %3,%2(%0)"
10835 [(set_attr "type" "store_ux,store_u")])
10837 (define_insn "*movsf_update1"
10838 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10839 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10840 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10841 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10842 (plus:SI (match_dup 1) (match_dup 2)))]
10843 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10844 && (!avoiding_indexed_address_p (SImode)
10845 || !gpc_reg_operand (operands[2], SImode))"
10846 "@
10847 lfsux %3,%0,%2
10848 lfsu %3,%2(%0)"
10849 [(set_attr "type" "fpload_ux,fpload_u")])
10851 (define_insn "*movsf_update2"
10852 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10853 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10854 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10855 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10856 (plus:SI (match_dup 1) (match_dup 2)))]
10857 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10858 && (!avoiding_indexed_address_p (SImode)
10859 || !gpc_reg_operand (operands[2], SImode))"
10860 "@
10861 stfsux %3,%0,%2
10862 stfsu %3,%2(%0)"
10863 [(set_attr "type" "fpstore_ux,fpstore_u")])
10865 (define_insn "*movsf_update3"
10866 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10867 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10868 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10869 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10870 (plus:SI (match_dup 1) (match_dup 2)))]
10871 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10872 && (!avoiding_indexed_address_p (SImode)
10873 || !gpc_reg_operand (operands[2], SImode))"
10874 "@
10875 {lux|lwzux} %3,%0,%2
10876 {lu|lwzu} %3,%2(%0)"
10877 [(set_attr "type" "load_ux,load_u")])
10879 (define_insn "*movsf_update4"
10880 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10881 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10882 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10883 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10884 (plus:SI (match_dup 1) (match_dup 2)))]
10885 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10886 && (!avoiding_indexed_address_p (SImode)
10887 || !gpc_reg_operand (operands[2], SImode))"
10888 "@
10889 {stux|stwux} %3,%0,%2
10890 {stu|stwu} %3,%2(%0)"
10891 [(set_attr "type" "store_ux,store_u")])
10893 (define_insn "*movdf_update1"
10894 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10895 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10896 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10897 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10898 (plus:SI (match_dup 1) (match_dup 2)))]
10899 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10900 && (!avoiding_indexed_address_p (SImode)
10901 || !gpc_reg_operand (operands[2], SImode))"
10902 "@
10903 lfdux %3,%0,%2
10904 lfdu %3,%2(%0)"
10905 [(set_attr "type" "fpload_ux,fpload_u")])
10907 (define_insn "*movdf_update2"
10908 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10909 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10910 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10911 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10912 (plus:SI (match_dup 1) (match_dup 2)))]
10913 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10914 && (!avoiding_indexed_address_p (SImode)
10915 || !gpc_reg_operand (operands[2], SImode))"
10916 "@
10917 stfdux %3,%0,%2
10918 stfdu %3,%2(%0)"
10919 [(set_attr "type" "fpstore_ux,fpstore_u")])
10921 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10923 (define_insn "*lfq_power2"
10924 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10925 (match_operand:V2DF 1 "memory_operand" ""))]
10926 "TARGET_POWER2
10927 && TARGET_HARD_FLOAT && TARGET_FPRS"
10928 "lfq%U1%X1 %0,%1")
10930 (define_peephole2
10931 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10932 (match_operand:DF 1 "memory_operand" ""))
10933 (set (match_operand:DF 2 "gpc_reg_operand" "")
10934 (match_operand:DF 3 "memory_operand" ""))]
10935 "TARGET_POWER2
10936 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10937 && registers_ok_for_quad_peep (operands[0], operands[2])
10938 && mems_ok_for_quad_peep (operands[1], operands[3])"
10939 [(set (match_dup 0)
10940 (match_dup 1))]
10941 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10942 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10944 (define_insn "*stfq_power2"
10945 [(set (match_operand:V2DF 0 "memory_operand" "")
10946 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10947 "TARGET_POWER2
10948 && TARGET_HARD_FLOAT && TARGET_FPRS"
10949 "stfq%U0%X0 %1,%0")
10952 (define_peephole2
10953 [(set (match_operand:DF 0 "memory_operand" "")
10954 (match_operand:DF 1 "gpc_reg_operand" ""))
10955 (set (match_operand:DF 2 "memory_operand" "")
10956 (match_operand:DF 3 "gpc_reg_operand" ""))]
10957 "TARGET_POWER2
10958 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10959 && registers_ok_for_quad_peep (operands[1], operands[3])
10960 && mems_ok_for_quad_peep (operands[0], operands[2])"
10961 [(set (match_dup 0)
10962 (match_dup 1))]
10963 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10964 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10966 ;; After inserting conditional returns we can sometimes have
10967 ;; unnecessary register moves. Unfortunately we cannot have a
10968 ;; modeless peephole here, because some single SImode sets have early
10969 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10970 ;; sequences, using get_attr_length here will smash the operands
10971 ;; array. Neither is there an early_cobbler_p predicate.
10972 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10973 (define_peephole2
10974 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10975 (match_operand:DF 1 "any_operand" ""))
10976 (set (match_operand:DF 2 "gpc_reg_operand" "")
10977 (match_dup 0))]
10978 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10979 && peep2_reg_dead_p (2, operands[0])"
10980 [(set (match_dup 2) (match_dup 1))])
10982 (define_peephole2
10983 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10984 (match_operand:SF 1 "any_operand" ""))
10985 (set (match_operand:SF 2 "gpc_reg_operand" "")
10986 (match_dup 0))]
10987 "peep2_reg_dead_p (2, operands[0])"
10988 [(set (match_dup 2) (match_dup 1))])
10990 \f
10991 ;; TLS support.
10993 ;; Mode attributes for different ABIs.
10994 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10995 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10996 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10997 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10999 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11000 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11001 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11002 (match_operand 4 "" "g")))
11003 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11004 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11005 UNSPEC_TLSGD)
11006 (clobber (reg:SI LR_REGNO))]
11007 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11008 {
11009 if (TARGET_CMODEL != CMODEL_SMALL)
11010 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11011 else
11012 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11013 }
11014 "&& TARGET_TLS_MARKERS"
11015 [(set (match_dup 0)
11016 (unspec:TLSmode [(match_dup 1)
11017 (match_dup 2)]
11018 UNSPEC_TLSGD))
11019 (parallel [(set (match_dup 0)
11020 (call (mem:TLSmode (match_dup 3))
11021 (match_dup 4)))
11022 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11023 (clobber (reg:SI LR_REGNO))])]
11024 ""
11025 [(set_attr "type" "two")
11026 (set (attr "length")
11027 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11028 (const_int 16)
11029 (const_int 12)))])
11031 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11032 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11033 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11034 (match_operand 4 "" "g")))
11035 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11036 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11037 UNSPEC_TLSGD)
11038 (clobber (reg:SI LR_REGNO))]
11039 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11040 {
11041 if (flag_pic)
11042 {
11043 if (TARGET_SECURE_PLT && flag_pic == 2)
11044 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11045 else
11046 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11047 }
11048 else
11049 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11050 }
11051 "&& TARGET_TLS_MARKERS"
11052 [(set (match_dup 0)
11053 (unspec:TLSmode [(match_dup 1)
11054 (match_dup 2)]
11055 UNSPEC_TLSGD))
11056 (parallel [(set (match_dup 0)
11057 (call (mem:TLSmode (match_dup 3))
11058 (match_dup 4)))
11059 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11060 (clobber (reg:SI LR_REGNO))])]
11061 ""
11062 [(set_attr "type" "two")
11063 (set_attr "length" "8")])
11065 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11066 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11067 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11068 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11069 UNSPEC_TLSGD))]
11070 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11071 "addi %0,%1,%2@got@tlsgd"
11072 "&& TARGET_CMODEL != CMODEL_SMALL"
11073 [(set (match_dup 3)
11074 (plus:TLSmode (match_dup 1)
11075 (high:TLSmode
11076 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD))))
11077 (set (match_dup 0)
11078 (lo_sum:TLSmode (match_dup 3)
11079 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11080 "
11081 {
11082 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11083 }"
11084 [(set (attr "length")
11085 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11086 (const_int 8)
11087 (const_int 4)))])
11089 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11090 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11091 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11092 (high:TLSmode
11093 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11094 UNSPEC_TLSGD))))]
11095 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11096 "addis %0,%1,%2@got@tlsgd@ha"
11097 [(set_attr "length" "4")])
11099 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11100 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11101 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11102 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11103 UNSPEC_TLSGD)))]
11104 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11105 "addi %0,%1,%2@got@tlsgd@l"
11106 [(set_attr "length" "4")])
11108 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11109 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11110 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11111 (match_operand 2 "" "g")))
11112 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11113 UNSPEC_TLSGD)
11114 (clobber (reg:SI LR_REGNO))]
11115 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11116 "bl %z1(%3@tlsgd)\;%."
11117 [(set_attr "type" "branch")
11118 (set_attr "length" "8")])
11120 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11121 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11122 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11123 (match_operand 2 "" "g")))
11124 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11125 UNSPEC_TLSGD)
11126 (clobber (reg:SI LR_REGNO))]
11127 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11128 {
11129 if (flag_pic)
11130 {
11131 if (TARGET_SECURE_PLT && flag_pic == 2)
11132 return "bl %z1+32768(%3@tlsgd)@plt";
11133 return "bl %z1(%3@tlsgd)@plt";
11134 }
11135 return "bl %z1(%3@tlsgd)";
11136 }
11137 [(set_attr "type" "branch")
11138 (set_attr "length" "4")])
11140 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11141 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11142 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11143 (match_operand 3 "" "g")))
11144 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11145 UNSPEC_TLSLD)
11146 (clobber (reg:SI LR_REGNO))]
11147 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11148 {
11149 if (TARGET_CMODEL != CMODEL_SMALL)
11150 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11151 else
11152 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11153 }
11154 "&& TARGET_TLS_MARKERS"
11155 [(set (match_dup 0)
11156 (unspec:TLSmode [(match_dup 1)]
11157 UNSPEC_TLSLD))
11158 (parallel [(set (match_dup 0)
11159 (call (mem:TLSmode (match_dup 2))
11160 (match_dup 3)))
11161 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11162 (clobber (reg:SI LR_REGNO))])]
11163 ""
11164 [(set_attr "type" "two")
11165 (set (attr "length")
11166 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11167 (const_int 16)
11168 (const_int 12)))])
11170 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11171 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11172 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11173 (match_operand 3 "" "g")))
11174 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11175 UNSPEC_TLSLD)
11176 (clobber (reg:SI LR_REGNO))]
11177 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11178 {
11179 if (flag_pic)
11180 {
11181 if (TARGET_SECURE_PLT && flag_pic == 2)
11182 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11183 else
11184 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11185 }
11186 else
11187 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11188 }
11189 "&& TARGET_TLS_MARKERS"
11190 [(set (match_dup 0)
11191 (unspec:TLSmode [(match_dup 1)]
11192 UNSPEC_TLSLD))
11193 (parallel [(set (match_dup 0)
11194 (call (mem:TLSmode (match_dup 2))
11195 (match_dup 3)))
11196 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11197 (clobber (reg:SI LR_REGNO))])]
11198 ""
11199 [(set_attr "length" "8")])
11201 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11202 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11203 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11204 UNSPEC_TLSLD))]
11205 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11206 "addi %0,%1,%&@got@tlsld"
11207 "&& TARGET_CMODEL != CMODEL_SMALL"
11208 [(set (match_dup 2)
11209 (plus:TLSmode (match_dup 1)
11210 (high:TLSmode
11211 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))
11212 (set (match_dup 0)
11213 (lo_sum:TLSmode (match_dup 2)
11214 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11215 "
11216 {
11217 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11218 }"
11219 [(set (attr "length")
11220 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11221 (const_int 8)
11222 (const_int 4)))])
11224 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11225 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11226 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11227 (high:TLSmode
11228 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))]
11229 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11230 "addis %0,%1,%&@got@tlsld@ha"
11231 [(set_attr "length" "4")])
11233 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11234 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11235 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11236 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11237 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11238 "addi %0,%1,%&@got@tlsld@l"
11239 [(set_attr "length" "4")])
11241 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11242 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11243 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11244 (match_operand 2 "" "g")))
11245 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11246 (clobber (reg:SI LR_REGNO))]
11247 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11248 "bl %z1(%&@tlsld)\;%."
11249 [(set_attr "type" "branch")
11250 (set_attr "length" "8")])
11252 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11253 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11254 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11255 (match_operand 2 "" "g")))
11256 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11257 (clobber (reg:SI LR_REGNO))]
11258 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11259 {
11260 if (flag_pic)
11261 {
11262 if (TARGET_SECURE_PLT && flag_pic == 2)
11263 return "bl %z1+32768(%&@tlsld)@plt";
11264 return "bl %z1(%&@tlsld)@plt";
11265 }
11266 return "bl %z1(%&@tlsld)";
11267 }
11268 [(set_attr "type" "branch")
11269 (set_attr "length" "4")])
11271 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11272 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11273 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11274 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11275 UNSPEC_TLSDTPREL))]
11276 "HAVE_AS_TLS"
11277 "addi %0,%1,%2@dtprel")
11279 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11280 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11281 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11282 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11283 UNSPEC_TLSDTPRELHA))]
11284 "HAVE_AS_TLS"
11285 "addis %0,%1,%2@dtprel@ha")
11287 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11288 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11289 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11290 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11291 UNSPEC_TLSDTPRELLO))]
11292 "HAVE_AS_TLS"
11293 "addi %0,%1,%2@dtprel@l")
11295 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11296 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11297 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11298 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11299 UNSPEC_TLSGOTDTPREL))]
11300 "HAVE_AS_TLS"
11301 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11302 "&& TARGET_CMODEL != CMODEL_SMALL"
11303 [(set (match_dup 3)
11304 (plus:TLSmode (match_dup 1)
11305 (high:TLSmode
11306 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL))))
11307 (set (match_dup 0)
11308 (lo_sum:TLSmode (match_dup 3)
11309 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11310 "
11311 {
11312 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11313 }"
11314 [(set (attr "length")
11315 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11316 (const_int 8)
11317 (const_int 4)))])
11319 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11320 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11321 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11322 (high:TLSmode
11323 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11324 UNSPEC_TLSGOTDTPREL))))]
11325 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11326 "addis %0,%1,%2@got@dtprel@ha"
11327 [(set_attr "length" "4")])
11329 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11330 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11331 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11332 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11333 UNSPEC_TLSGOTDTPREL)))]
11334 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11335 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11336 [(set_attr "length" "4")])
11338 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11339 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11340 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11341 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11342 UNSPEC_TLSTPREL))]
11343 "HAVE_AS_TLS"
11344 "addi %0,%1,%2@tprel")
11346 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11347 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11348 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11349 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11350 UNSPEC_TLSTPRELHA))]
11351 "HAVE_AS_TLS"
11352 "addis %0,%1,%2@tprel@ha")
11354 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11355 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11356 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11357 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11358 UNSPEC_TLSTPRELLO))]
11359 "HAVE_AS_TLS"
11360 "addi %0,%1,%2@tprel@l")
11362 ;; "b" output constraint here and on tls_tls input to support linker tls
11363 ;; optimization. The linker may edit the instructions emitted by a
11364 ;; tls_got_tprel/tls_tls pair to addis,addi.
11365 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11366 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11367 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11368 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11369 UNSPEC_TLSGOTTPREL))]
11370 "HAVE_AS_TLS"
11371 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11372 "&& TARGET_CMODEL != CMODEL_SMALL"
11373 [(set (match_dup 3)
11374 (plus:TLSmode (match_dup 1)
11375 (high:TLSmode
11376 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL))))
11377 (set (match_dup 0)
11378 (lo_sum:TLSmode (match_dup 3)
11379 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11380 "
11381 {
11382 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11383 }"
11384 [(set (attr "length")
11385 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11386 (const_int 8)
11387 (const_int 4)))])
11389 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11390 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11391 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11392 (high:TLSmode
11393 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11394 UNSPEC_TLSGOTTPREL))))]
11395 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11396 "addis %0,%1,%2@got@tprel@ha"
11397 [(set_attr "length" "4")])
11399 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11400 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11401 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11402 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11403 UNSPEC_TLSGOTTPREL)))]
11404 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11405 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11406 [(set_attr "length" "4")])
11408 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11409 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11410 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11411 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11412 UNSPEC_TLSTLS))]
11413 "HAVE_AS_TLS"
11414 "add %0,%1,%2@tls")
11415 \f
11416 ;; Next come insns related to the calling sequence.
11417 ;;
11418 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11419 ;; We move the back-chain and decrement the stack pointer.
11421 (define_expand "allocate_stack"
11422 [(set (match_operand 0 "gpc_reg_operand" "")
11423 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11424 (set (reg 1)
11425 (minus (reg 1) (match_dup 1)))]
11426 ""
11427 "
11428 { rtx chain = gen_reg_rtx (Pmode);
11429 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11430 rtx neg_op0;
11431 rtx insn, par, set, mem;
11433 emit_move_insn (chain, stack_bot);
11435 /* Check stack bounds if necessary. */
11436 if (crtl->limit_stack)
11437 {
11438 rtx available;
11439 available = expand_binop (Pmode, sub_optab,
11440 stack_pointer_rtx, stack_limit_rtx,
11441 NULL_RTX, 1, OPTAB_WIDEN);
11442 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11443 }
11445 if (GET_CODE (operands[1]) != CONST_INT
11446 || INTVAL (operands[1]) < -32767
11447 || INTVAL (operands[1]) > 32768)
11448 {
11449 neg_op0 = gen_reg_rtx (Pmode);
11450 if (TARGET_32BIT)
11451 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11452 else
11453 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11454 }
11455 else
11456 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11458 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11459 : gen_movdi_di_update_stack))
11460 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11461 chain));
11462 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11463 it now and set the alias set/attributes. The above gen_*_update
11464 calls will generate a PARALLEL with the MEM set being the first
11465 operation. */
11466 par = PATTERN (insn);
11467 gcc_assert (GET_CODE (par) == PARALLEL);
11468 set = XVECEXP (par, 0, 0);
11469 gcc_assert (GET_CODE (set) == SET);
11470 mem = SET_DEST (set);
11471 gcc_assert (MEM_P (mem));
11472 MEM_NOTRAP_P (mem) = 1;
11473 set_mem_alias_set (mem, get_frame_alias_set ());
11475 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11476 DONE;
11477 }")
11479 ;; These patterns say how to save and restore the stack pointer. We need not
11480 ;; save the stack pointer at function level since we are careful to
11481 ;; preserve the backchain. At block level, we have to restore the backchain
11482 ;; when we restore the stack pointer.
11483 ;;
11484 ;; For nonlocal gotos, we must save both the stack pointer and its
11485 ;; backchain and restore both. Note that in the nonlocal case, the
11486 ;; save area is a memory location.
11488 (define_expand "save_stack_function"
11489 [(match_operand 0 "any_operand" "")
11490 (match_operand 1 "any_operand" "")]
11491 ""
11492 "DONE;")
11494 (define_expand "restore_stack_function"
11495 [(match_operand 0 "any_operand" "")
11496 (match_operand 1 "any_operand" "")]
11497 ""
11498 "DONE;")
11500 ;; Adjust stack pointer (op0) to a new value (op1).
11501 ;; First copy old stack backchain to new location, and ensure that the
11502 ;; scheduler won't reorder the sp assignment before the backchain write.
11503 (define_expand "restore_stack_block"
11504 [(set (match_dup 2) (match_dup 3))
11505 (set (match_dup 4) (match_dup 2))
11506 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11507 (set (match_operand 0 "register_operand" "")
11508 (match_operand 1 "register_operand" ""))]
11509 ""
11510 "
11511 {
11512 operands[1] = force_reg (Pmode, operands[1]);
11513 operands[2] = gen_reg_rtx (Pmode);
11514 operands[3] = gen_frame_mem (Pmode, operands[0]);
11515 operands[4] = gen_frame_mem (Pmode, operands[1]);
11516 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11517 }")
11519 (define_expand "save_stack_nonlocal"
11520 [(set (match_dup 3) (match_dup 4))
11521 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11522 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11523 ""
11524 "
11525 {
11526 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11528 /* Copy the backchain to the first word, sp to the second. */
11529 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11530 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11531 operands[3] = gen_reg_rtx (Pmode);
11532 operands[4] = gen_frame_mem (Pmode, operands[1]);
11533 }")
11535 (define_expand "restore_stack_nonlocal"
11536 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11537 (set (match_dup 3) (match_dup 4))
11538 (set (match_dup 5) (match_dup 2))
11539 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11540 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11541 ""
11542 "
11543 {
11544 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11546 /* Restore the backchain from the first word, sp from the second. */
11547 operands[2] = gen_reg_rtx (Pmode);
11548 operands[3] = gen_reg_rtx (Pmode);
11549 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11550 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11551 operands[5] = gen_frame_mem (Pmode, operands[3]);
11552 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11553 }")
11554 \f
11555 ;; TOC register handling.
11557 ;; Code to initialize the TOC register...
11559 (define_insn "load_toc_aix_si"
11560 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11561 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11562 (use (reg:SI 2))])]
11563 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11564 "*
11565 {
11566 char buf[30];
11567 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11568 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11569 operands[2] = gen_rtx_REG (Pmode, 2);
11570 return \"{l|lwz} %0,%1(%2)\";
11571 }"
11572 [(set_attr "type" "load")])
11574 (define_insn "load_toc_aix_di"
11575 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11576 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11577 (use (reg:DI 2))])]
11578 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11579 "*
11580 {
11581 char buf[30];
11582 #ifdef TARGET_RELOCATABLE
11583 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11584 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11585 #else
11586 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11587 #endif
11588 if (TARGET_ELF)
11589 strcat (buf, \"@toc\");
11590 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11591 operands[2] = gen_rtx_REG (Pmode, 2);
11592 return \"ld %0,%1(%2)\";
11593 }"
11594 [(set_attr "type" "load")])
11596 (define_insn "load_toc_v4_pic_si"
11597 [(set (reg:SI LR_REGNO)
11598 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11599 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11600 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11601 [(set_attr "type" "branch")
11602 (set_attr "length" "4")])
11604 (define_insn "load_toc_v4_PIC_1"
11605 [(set (reg:SI LR_REGNO)
11606 (match_operand:SI 0 "immediate_operand" "s"))
11607 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11608 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11609 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11610 "bcl 20,31,%0\\n%0:"
11611 [(set_attr "type" "branch")
11612 (set_attr "length" "4")])
11614 (define_insn "load_toc_v4_PIC_1b"
11615 [(set (reg:SI LR_REGNO)
11616 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11617 (label_ref (match_operand 1 "" ""))]
11618 UNSPEC_TOCPTR))
11619 (match_dup 1)]
11620 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11621 "bcl 20,31,$+8\;.long %0-$"
11622 [(set_attr "type" "branch")
11623 (set_attr "length" "8")])
11625 (define_insn "load_toc_v4_PIC_2"
11626 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11627 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11628 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11629 (match_operand:SI 3 "immediate_operand" "s")))))]
11630 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11631 "{l|lwz} %0,%2-%3(%1)"
11632 [(set_attr "type" "load")])
11634 (define_insn "load_toc_v4_PIC_3b"
11635 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11636 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11637 (high:SI
11638 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11639 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11640 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11641 "{cau|addis} %0,%1,%2-%3@ha")
11643 (define_insn "load_toc_v4_PIC_3c"
11644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11645 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11646 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11647 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11648 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11649 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
11651 ;; If the TOC is shared over a translation unit, as happens with all
11652 ;; the kinds of PIC that we support, we need to restore the TOC
11653 ;; pointer only when jumping over units of translation.
11654 ;; On Darwin, we need to reload the picbase.
11656 (define_expand "builtin_setjmp_receiver"
11657 [(use (label_ref (match_operand 0 "" "")))]
11658 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11659 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11660 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11661 "
11662 {
11663 #if TARGET_MACHO
11664 if (DEFAULT_ABI == ABI_DARWIN)
11665 {
11666 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11667 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11668 rtx tmplabrtx;
11669 char tmplab[20];
11671 crtl->uses_pic_offset_table = 1;
11672 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11673 CODE_LABEL_NUMBER (operands[0]));
11674 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11676 emit_insn (gen_load_macho_picbase (tmplabrtx));
11677 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11678 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11679 }
11680 else
11681 #endif
11682 rs6000_emit_load_toc_table (FALSE);
11683 DONE;
11684 }")
11686 ;; Elf specific ways of loading addresses for non-PIC code.
11687 ;; The output of this could be r0, but we make a very strong
11688 ;; preference for a base register because it will usually
11689 ;; be needed there.
11690 (define_insn "elf_high"
11691 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11692 (high:SI (match_operand 1 "" "")))]
11693 "TARGET_ELF && ! TARGET_64BIT"
11694 "{liu|lis} %0,%1@ha")
11696 (define_insn "elf_low"
11697 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11698 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11699 (match_operand 2 "" "")))]
11700 "TARGET_ELF && ! TARGET_64BIT"
11701 "@
11702 {cal|la} %0,%2@l(%1)
11703 {ai|addic} %0,%1,%K2")
11705 ;; Largetoc support
11706 (define_insn "largetoc_high"
11707 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
11708 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
11709 (high:DI (match_operand:DI 2 "" ""))))]
11710 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11711 "{cau|addis} %0,%1,%2@ha")
11713 (define_insn "largetoc_low"
11714 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11715 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
11716 (match_operand:DI 2 "" "")))]
11717 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11718 "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
11719 \f
11720 ;; A function pointer under AIX is a pointer to a data area whose first word
11721 ;; contains the actual address of the function, whose second word contains a
11722 ;; pointer to its TOC, and whose third word contains a value to place in the
11723 ;; static chain register (r11). Note that if we load the static chain, our
11724 ;; "trampoline" need not have any executable code.
11726 (define_expand "call_indirect_aix32"
11727 [(set (match_dup 2)
11728 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11729 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11730 (reg:SI 2))
11731 (set (reg:SI 11)
11732 (mem:SI (plus:SI (match_dup 0)
11733 (const_int 8))))
11734 (parallel [(call (mem:SI (match_dup 2))
11735 (match_operand 1 "" ""))
11736 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11737 (use (reg:SI 11))
11738 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11739 (clobber (reg:SI LR_REGNO))])]
11740 "TARGET_32BIT"
11741 "
11742 { operands[2] = gen_reg_rtx (SImode); }")
11744 (define_expand "call_indirect_aix64"
11745 [(set (match_dup 2)
11746 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11747 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11748 (reg:DI 2))
11749 (set (reg:DI 11)
11750 (mem:DI (plus:DI (match_dup 0)
11751 (const_int 16))))
11752 (parallel [(call (mem:SI (match_dup 2))
11753 (match_operand 1 "" ""))
11754 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11755 (use (reg:DI 11))
11756 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11757 (clobber (reg:SI LR_REGNO))])]
11758 "TARGET_64BIT"
11759 "
11760 { operands[2] = gen_reg_rtx (DImode); }")
11762 (define_expand "call_value_indirect_aix32"
11763 [(set (match_dup 3)
11764 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11765 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11766 (reg:SI 2))
11767 (set (reg:SI 11)
11768 (mem:SI (plus:SI (match_dup 1)
11769 (const_int 8))))
11770 (parallel [(set (match_operand 0 "" "")
11771 (call (mem:SI (match_dup 3))
11772 (match_operand 2 "" "")))
11773 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11774 (use (reg:SI 11))
11775 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11776 (clobber (reg:SI LR_REGNO))])]
11777 "TARGET_32BIT"
11778 "
11779 { operands[3] = gen_reg_rtx (SImode); }")
11781 (define_expand "call_value_indirect_aix64"
11782 [(set (match_dup 3)
11783 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11784 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11785 (reg:DI 2))
11786 (set (reg:DI 11)
11787 (mem:DI (plus:DI (match_dup 1)
11788 (const_int 16))))
11789 (parallel [(set (match_operand 0 "" "")
11790 (call (mem:SI (match_dup 3))
11791 (match_operand 2 "" "")))
11792 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11793 (use (reg:DI 11))
11794 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11795 (clobber (reg:SI LR_REGNO))])]
11796 "TARGET_64BIT"
11797 "
11798 { operands[3] = gen_reg_rtx (DImode); }")
11800 ;; Now the definitions for the call and call_value insns
11801 (define_expand "call"
11802 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11803 (match_operand 1 "" ""))
11804 (use (match_operand 2 "" ""))
11805 (clobber (reg:SI LR_REGNO))])]
11806 ""
11807 "
11808 {
11809 #if TARGET_MACHO
11810 if (MACHOPIC_INDIRECT)
11811 operands[0] = machopic_indirect_call_target (operands[0]);
11812 #endif
11814 gcc_assert (GET_CODE (operands[0]) == MEM);
11815 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11817 operands[0] = XEXP (operands[0], 0);
11819 if (GET_CODE (operands[0]) != SYMBOL_REF
11820 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11821 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11822 {
11823 if (INTVAL (operands[2]) & CALL_LONG)
11824 operands[0] = rs6000_longcall_ref (operands[0]);
11826 switch (DEFAULT_ABI)
11827 {
11828 case ABI_V4:
11829 case ABI_DARWIN:
11830 operands[0] = force_reg (Pmode, operands[0]);
11831 break;
11833 case ABI_AIX:
11834 /* AIX function pointers are really pointers to a three word
11835 area. */
11836 emit_call_insn (TARGET_32BIT
11837 ? gen_call_indirect_aix32 (force_reg (SImode,
11838 operands[0]),
11839 operands[1])
11840 : gen_call_indirect_aix64 (force_reg (DImode,
11841 operands[0]),
11842 operands[1]));
11843 DONE;
11845 default:
11846 gcc_unreachable ();
11847 }
11848 }
11849 }")
11851 (define_expand "call_value"
11852 [(parallel [(set (match_operand 0 "" "")
11853 (call (mem:SI (match_operand 1 "address_operand" ""))
11854 (match_operand 2 "" "")))
11855 (use (match_operand 3 "" ""))
11856 (clobber (reg:SI LR_REGNO))])]
11857 ""
11858 "
11859 {
11860 #if TARGET_MACHO
11861 if (MACHOPIC_INDIRECT)
11862 operands[1] = machopic_indirect_call_target (operands[1]);
11863 #endif
11865 gcc_assert (GET_CODE (operands[1]) == MEM);
11866 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11868 operands[1] = XEXP (operands[1], 0);
11870 if (GET_CODE (operands[1]) != SYMBOL_REF
11871 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11872 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11873 {
11874 if (INTVAL (operands[3]) & CALL_LONG)
11875 operands[1] = rs6000_longcall_ref (operands[1]);
11877 switch (DEFAULT_ABI)
11878 {
11879 case ABI_V4:
11880 case ABI_DARWIN:
11881 operands[1] = force_reg (Pmode, operands[1]);
11882 break;
11884 case ABI_AIX:
11885 /* AIX function pointers are really pointers to a three word
11886 area. */
11887 emit_call_insn (TARGET_32BIT
11888 ? gen_call_value_indirect_aix32 (operands[0],
11889 force_reg (SImode,
11890 operands[1]),
11891 operands[2])
11892 : gen_call_value_indirect_aix64 (operands[0],
11893 force_reg (DImode,
11894 operands[1]),
11895 operands[2]));
11896 DONE;
11898 default:
11899 gcc_unreachable ();
11900 }
11901 }
11902 }")
11904 ;; Call to function in current module. No TOC pointer reload needed.
11905 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11906 ;; either the function was not prototyped, or it was prototyped as a
11907 ;; variable argument function. It is > 0 if FP registers were passed
11908 ;; and < 0 if they were not.
11910 (define_insn "*call_local32"
11911 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11912 (match_operand 1 "" "g,g"))
11913 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11914 (clobber (reg:SI LR_REGNO))]
11915 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11916 "*
11917 {
11918 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11919 output_asm_insn (\"crxor 6,6,6\", operands);
11921 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11922 output_asm_insn (\"creqv 6,6,6\", operands);
11924 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11925 }"
11926 [(set_attr "type" "branch")
11927 (set_attr "length" "4,8")])
11929 (define_insn "*call_local64"
11930 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11931 (match_operand 1 "" "g,g"))
11932 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11933 (clobber (reg:SI LR_REGNO))]
11934 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11935 "*
11936 {
11937 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11938 output_asm_insn (\"crxor 6,6,6\", operands);
11940 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11941 output_asm_insn (\"creqv 6,6,6\", operands);
11943 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11944 }"
11945 [(set_attr "type" "branch")
11946 (set_attr "length" "4,8")])
11948 (define_insn "*call_value_local32"
11949 [(set (match_operand 0 "" "")
11950 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11951 (match_operand 2 "" "g,g")))
11952 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11953 (clobber (reg:SI LR_REGNO))]
11954 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11955 "*
11956 {
11957 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11958 output_asm_insn (\"crxor 6,6,6\", operands);
11960 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11961 output_asm_insn (\"creqv 6,6,6\", operands);
11963 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11964 }"
11965 [(set_attr "type" "branch")
11966 (set_attr "length" "4,8")])
11969 (define_insn "*call_value_local64"
11970 [(set (match_operand 0 "" "")
11971 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11972 (match_operand 2 "" "g,g")))
11973 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11974 (clobber (reg:SI LR_REGNO))]
11975 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11976 "*
11977 {
11978 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11979 output_asm_insn (\"crxor 6,6,6\", operands);
11981 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11982 output_asm_insn (\"creqv 6,6,6\", operands);
11984 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11985 }"
11986 [(set_attr "type" "branch")
11987 (set_attr "length" "4,8")])
11989 ;; Call to function which may be in another module. Restore the TOC
11990 ;; pointer (r2) after the call unless this is System V.
11991 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11992 ;; either the function was not prototyped, or it was prototyped as a
11993 ;; variable argument function. It is > 0 if FP registers were passed
11994 ;; and < 0 if they were not.
11996 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11997 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11998 (match_operand 1 "" "g,g"))
11999 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
12000 (use (reg:SI 11))
12001 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12002 (clobber (reg:SI LR_REGNO))]
12003 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12004 "#"
12005 "&& reload_completed"
12006 [(set (reg:SI 2)
12007 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
12008 (parallel [(call (mem:SI (match_dup 0))
12009 (match_dup 1))
12010 (use (reg:SI 2))
12011 (use (reg:SI 11))
12012 (set (reg:SI 2)
12013 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12014 (clobber (reg:SI LR_REGNO))])]
12015 ""
12016 [(set_attr "type" "jmpreg")
12017 (set_attr "length" "12")])
12019 (define_insn "*call_indirect_nonlocal_aix32"
12020 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12021 (match_operand 1 "" "g,g"))
12022 (use (reg:SI 2))
12023 (use (reg:SI 11))
12024 (set (reg:SI 2)
12025 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12026 (clobber (reg:SI LR_REGNO))]
12027 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12028 "b%T0l\;{l|lwz} 2,20(1)"
12029 [(set_attr "type" "jmpreg")
12030 (set_attr "length" "8")])
12032 (define_insn "*call_nonlocal_aix32"
12033 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12034 (match_operand 1 "" "g"))
12035 (use (match_operand:SI 2 "immediate_operand" "O"))
12036 (clobber (reg:SI LR_REGNO))]
12037 "TARGET_32BIT
12038 && DEFAULT_ABI == ABI_AIX
12039 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12040 "bl %z0\;%."
12041 [(set_attr "type" "branch")
12042 (set_attr "length" "8")])
12044 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
12045 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12046 (match_operand 1 "" "g,g"))
12047 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
12048 (const_int 8))))
12049 (use (reg:DI 11))
12050 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12051 (clobber (reg:SI LR_REGNO))]
12052 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12053 "#"
12054 "&& reload_completed"
12055 [(set (reg:DI 2)
12056 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
12057 (parallel [(call (mem:SI (match_dup 0))
12058 (match_dup 1))
12059 (use (reg:DI 2))
12060 (use (reg:DI 11))
12061 (set (reg:DI 2)
12062 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12063 (clobber (reg:SI LR_REGNO))])]
12064 ""
12065 [(set_attr "type" "jmpreg")
12066 (set_attr "length" "12")])
12068 (define_insn "*call_indirect_nonlocal_aix64"
12069 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12070 (match_operand 1 "" "g,g"))
12071 (use (reg:DI 2))
12072 (use (reg:DI 11))
12073 (set (reg:DI 2)
12074 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12075 (clobber (reg:SI LR_REGNO))]
12076 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12077 "b%T0l\;ld 2,40(1)"
12078 [(set_attr "type" "jmpreg")
12079 (set_attr "length" "8")])
12081 (define_insn "*call_nonlocal_aix64"
12082 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12083 (match_operand 1 "" "g"))
12084 (use (match_operand:SI 2 "immediate_operand" "O"))
12085 (clobber (reg:SI LR_REGNO))]
12086 "TARGET_64BIT
12087 && DEFAULT_ABI == ABI_AIX
12088 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12089 "bl %z0\;%."
12090 [(set_attr "type" "branch")
12091 (set_attr "length" "8")])
12093 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
12094 [(set (match_operand 0 "" "")
12095 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12096 (match_operand 2 "" "g,g")))
12097 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
12098 (const_int 4))))
12099 (use (reg:SI 11))
12100 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12101 (clobber (reg:SI LR_REGNO))]
12102 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12103 "#"
12104 "&& reload_completed"
12105 [(set (reg:SI 2)
12106 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
12107 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12108 (match_dup 2)))
12109 (use (reg:SI 2))
12110 (use (reg:SI 11))
12111 (set (reg:SI 2)
12112 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12113 (clobber (reg:SI LR_REGNO))])]
12114 ""
12115 [(set_attr "type" "jmpreg")
12116 (set_attr "length" "12")])
12118 (define_insn "*call_value_indirect_nonlocal_aix32"
12119 [(set (match_operand 0 "" "")
12120 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12121 (match_operand 2 "" "g,g")))
12122 (use (reg:SI 2))
12123 (use (reg:SI 11))
12124 (set (reg:SI 2)
12125 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12126 (clobber (reg:SI LR_REGNO))]
12127 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12128 "b%T1l\;{l|lwz} 2,20(1)"
12129 [(set_attr "type" "jmpreg")
12130 (set_attr "length" "8")])
12132 (define_insn "*call_value_nonlocal_aix32"
12133 [(set (match_operand 0 "" "")
12134 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12135 (match_operand 2 "" "g")))
12136 (use (match_operand:SI 3 "immediate_operand" "O"))
12137 (clobber (reg:SI LR_REGNO))]
12138 "TARGET_32BIT
12139 && DEFAULT_ABI == ABI_AIX
12140 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12141 "bl %z1\;%."
12142 [(set_attr "type" "branch")
12143 (set_attr "length" "8")])
12145 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
12146 [(set (match_operand 0 "" "")
12147 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12148 (match_operand 2 "" "g,g")))
12149 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
12150 (const_int 8))))
12151 (use (reg:DI 11))
12152 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12153 (clobber (reg:SI LR_REGNO))]
12154 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12155 "#"
12156 "&& reload_completed"
12157 [(set (reg:DI 2)
12158 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12159 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12160 (match_dup 2)))
12161 (use (reg:DI 2))
12162 (use (reg:DI 11))
12163 (set (reg:DI 2)
12164 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12165 (clobber (reg:SI LR_REGNO))])]
12166 ""
12167 [(set_attr "type" "jmpreg")
12168 (set_attr "length" "12")])
12170 (define_insn "*call_value_indirect_nonlocal_aix64"
12171 [(set (match_operand 0 "" "")
12172 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12173 (match_operand 2 "" "g,g")))
12174 (use (reg:DI 2))
12175 (use (reg:DI 11))
12176 (set (reg:DI 2)
12177 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12178 (clobber (reg:SI LR_REGNO))]
12179 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12180 "b%T1l\;ld 2,40(1)"
12181 [(set_attr "type" "jmpreg")
12182 (set_attr "length" "8")])
12184 (define_insn "*call_value_nonlocal_aix64"
12185 [(set (match_operand 0 "" "")
12186 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12187 (match_operand 2 "" "g")))
12188 (use (match_operand:SI 3 "immediate_operand" "O"))
12189 (clobber (reg:SI LR_REGNO))]
12190 "TARGET_64BIT
12191 && DEFAULT_ABI == ABI_AIX
12192 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12193 "bl %z1\;%."
12194 [(set_attr "type" "branch")
12195 (set_attr "length" "8")])
12197 ;; A function pointer under System V is just a normal pointer
12198 ;; operands[0] is the function pointer
12199 ;; operands[1] is the stack size to clean up
12200 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12201 ;; which indicates how to set cr1
12203 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12204 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12205 (match_operand 1 "" "g,g,g,g"))
12206 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12207 (clobber (reg:SI LR_REGNO))]
12208 "DEFAULT_ABI == ABI_V4
12209 || DEFAULT_ABI == ABI_DARWIN"
12210 {
12211 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12212 output_asm_insn ("crxor 6,6,6", operands);
12214 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12215 output_asm_insn ("creqv 6,6,6", operands);
12217 return "b%T0l";
12218 }
12219 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12220 (set_attr "length" "4,4,8,8")])
12222 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12223 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12224 (match_operand 1 "" "g,g"))
12225 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12226 (clobber (reg:SI LR_REGNO))]
12227 "(DEFAULT_ABI == ABI_DARWIN
12228 || (DEFAULT_ABI == ABI_V4
12229 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12230 {
12231 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12232 output_asm_insn ("crxor 6,6,6", operands);
12234 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12235 output_asm_insn ("creqv 6,6,6", operands);
12237 #if TARGET_MACHO
12238 return output_call(insn, operands, 0, 2);
12239 #else
12240 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12241 {
12242 gcc_assert (!TARGET_SECURE_PLT);
12243 return "bl %z0@plt";
12244 }
12245 else
12246 return "bl %z0";
12247 #endif
12248 }
12249 "DEFAULT_ABI == ABI_V4
12250 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12251 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12252 [(parallel [(call (mem:SI (match_dup 0))
12253 (match_dup 1))
12254 (use (match_dup 2))
12255 (use (match_dup 3))
12256 (clobber (reg:SI LR_REGNO))])]
12257 {
12258 operands[3] = pic_offset_table_rtx;
12259 }
12260 [(set_attr "type" "branch,branch")
12261 (set_attr "length" "4,8")])
12263 (define_insn "*call_nonlocal_sysv_secure<mode>"
12264 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12265 (match_operand 1 "" "g,g"))
12266 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12267 (use (match_operand:SI 3 "register_operand" "r,r"))
12268 (clobber (reg:SI LR_REGNO))]
12269 "(DEFAULT_ABI == ABI_V4
12270 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12271 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12272 {
12273 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12274 output_asm_insn ("crxor 6,6,6", operands);
12276 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12277 output_asm_insn ("creqv 6,6,6", operands);
12279 if (flag_pic == 2)
12280 /* The magic 32768 offset here and in the other sysv call insns
12281 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12282 See sysv4.h:toc_section. */
12283 return "bl %z0+32768@plt";
12284 else
12285 return "bl %z0@plt";
12286 }
12287 [(set_attr "type" "branch,branch")
12288 (set_attr "length" "4,8")])
12290 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12291 [(set (match_operand 0 "" "")
12292 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12293 (match_operand 2 "" "g,g,g,g")))
12294 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12295 (clobber (reg:SI LR_REGNO))]
12296 "DEFAULT_ABI == ABI_V4
12297 || DEFAULT_ABI == ABI_DARWIN"
12298 {
12299 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12300 output_asm_insn ("crxor 6,6,6", operands);
12302 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12303 output_asm_insn ("creqv 6,6,6", operands);
12305 return "b%T1l";
12306 }
12307 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12308 (set_attr "length" "4,4,8,8")])
12310 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12311 [(set (match_operand 0 "" "")
12312 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12313 (match_operand 2 "" "g,g")))
12314 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12315 (clobber (reg:SI LR_REGNO))]
12316 "(DEFAULT_ABI == ABI_DARWIN
12317 || (DEFAULT_ABI == ABI_V4
12318 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12319 {
12320 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12321 output_asm_insn ("crxor 6,6,6", operands);
12323 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12324 output_asm_insn ("creqv 6,6,6", operands);
12326 #if TARGET_MACHO
12327 return output_call(insn, operands, 1, 3);
12328 #else
12329 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12330 {
12331 gcc_assert (!TARGET_SECURE_PLT);
12332 return "bl %z1@plt";
12333 }
12334 else
12335 return "bl %z1";
12336 #endif
12337 }
12338 "DEFAULT_ABI == ABI_V4
12339 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12340 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12341 [(parallel [(set (match_dup 0)
12342 (call (mem:SI (match_dup 1))
12343 (match_dup 2)))
12344 (use (match_dup 3))
12345 (use (match_dup 4))
12346 (clobber (reg:SI LR_REGNO))])]
12347 {
12348 operands[4] = pic_offset_table_rtx;
12349 }
12350 [(set_attr "type" "branch,branch")
12351 (set_attr "length" "4,8")])
12353 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12354 [(set (match_operand 0 "" "")
12355 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12356 (match_operand 2 "" "g,g")))
12357 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12358 (use (match_operand:SI 4 "register_operand" "r,r"))
12359 (clobber (reg:SI LR_REGNO))]
12360 "(DEFAULT_ABI == ABI_V4
12361 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12362 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12363 {
12364 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12365 output_asm_insn ("crxor 6,6,6", operands);
12367 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12368 output_asm_insn ("creqv 6,6,6", operands);
12370 if (flag_pic == 2)
12371 return "bl %z1+32768@plt";
12372 else
12373 return "bl %z1@plt";
12374 }
12375 [(set_attr "type" "branch,branch")
12376 (set_attr "length" "4,8")])
12378 ;; Call subroutine returning any type.
12379 (define_expand "untyped_call"
12380 [(parallel [(call (match_operand 0 "" "")
12381 (const_int 0))
12382 (match_operand 1 "" "")
12383 (match_operand 2 "" "")])]
12384 ""
12385 "
12386 {
12387 int i;
12389 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12391 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12392 {
12393 rtx set = XVECEXP (operands[2], 0, i);
12394 emit_move_insn (SET_DEST (set), SET_SRC (set));
12395 }
12397 /* The optimizer does not know that the call sets the function value
12398 registers we stored in the result block. We avoid problems by
12399 claiming that all hard registers are used and clobbered at this
12400 point. */
12401 emit_insn (gen_blockage ());
12403 DONE;
12404 }")
12406 ;; sibling call patterns
12407 (define_expand "sibcall"
12408 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12409 (match_operand 1 "" ""))
12410 (use (match_operand 2 "" ""))
12411 (use (reg:SI LR_REGNO))
12412 (return)])]
12413 ""
12414 "
12415 {
12416 #if TARGET_MACHO
12417 if (MACHOPIC_INDIRECT)
12418 operands[0] = machopic_indirect_call_target (operands[0]);
12419 #endif
12421 gcc_assert (GET_CODE (operands[0]) == MEM);
12422 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12424 operands[0] = XEXP (operands[0], 0);
12425 }")
12427 ;; this and similar patterns must be marked as using LR, otherwise
12428 ;; dataflow will try to delete the store into it. This is true
12429 ;; even when the actual reg to jump to is in CTR, when LR was
12430 ;; saved and restored around the PIC-setting BCL.
12431 (define_insn "*sibcall_local32"
12432 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12433 (match_operand 1 "" "g,g"))
12434 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12435 (use (reg:SI LR_REGNO))
12436 (return)]
12437 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12438 "*
12439 {
12440 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12441 output_asm_insn (\"crxor 6,6,6\", operands);
12443 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12444 output_asm_insn (\"creqv 6,6,6\", operands);
12446 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12447 }"
12448 [(set_attr "type" "branch")
12449 (set_attr "length" "4,8")])
12451 (define_insn "*sibcall_local64"
12452 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12453 (match_operand 1 "" "g,g"))
12454 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12455 (use (reg:SI LR_REGNO))
12456 (return)]
12457 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12458 "*
12459 {
12460 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12461 output_asm_insn (\"crxor 6,6,6\", operands);
12463 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12464 output_asm_insn (\"creqv 6,6,6\", operands);
12466 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12467 }"
12468 [(set_attr "type" "branch")
12469 (set_attr "length" "4,8")])
12471 (define_insn "*sibcall_value_local32"
12472 [(set (match_operand 0 "" "")
12473 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12474 (match_operand 2 "" "g,g")))
12475 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12476 (use (reg:SI LR_REGNO))
12477 (return)]
12478 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12479 "*
12480 {
12481 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12482 output_asm_insn (\"crxor 6,6,6\", operands);
12484 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12485 output_asm_insn (\"creqv 6,6,6\", operands);
12487 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12488 }"
12489 [(set_attr "type" "branch")
12490 (set_attr "length" "4,8")])
12493 (define_insn "*sibcall_value_local64"
12494 [(set (match_operand 0 "" "")
12495 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12496 (match_operand 2 "" "g,g")))
12497 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12498 (use (reg:SI LR_REGNO))
12499 (return)]
12500 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12501 "*
12502 {
12503 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12504 output_asm_insn (\"crxor 6,6,6\", operands);
12506 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12507 output_asm_insn (\"creqv 6,6,6\", operands);
12509 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12510 }"
12511 [(set_attr "type" "branch")
12512 (set_attr "length" "4,8")])
12514 (define_insn "*sibcall_nonlocal_aix32"
12515 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12516 (match_operand 1 "" "g"))
12517 (use (match_operand:SI 2 "immediate_operand" "O"))
12518 (use (reg:SI LR_REGNO))
12519 (return)]
12520 "TARGET_32BIT
12521 && DEFAULT_ABI == ABI_AIX
12522 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12523 "b %z0"
12524 [(set_attr "type" "branch")
12525 (set_attr "length" "4")])
12527 (define_insn "*sibcall_nonlocal_aix64"
12528 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12529 (match_operand 1 "" "g"))
12530 (use (match_operand:SI 2 "immediate_operand" "O"))
12531 (use (reg:SI LR_REGNO))
12532 (return)]
12533 "TARGET_64BIT
12534 && DEFAULT_ABI == ABI_AIX
12535 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12536 "b %z0"
12537 [(set_attr "type" "branch")
12538 (set_attr "length" "4")])
12540 (define_insn "*sibcall_value_nonlocal_aix32"
12541 [(set (match_operand 0 "" "")
12542 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12543 (match_operand 2 "" "g")))
12544 (use (match_operand:SI 3 "immediate_operand" "O"))
12545 (use (reg:SI LR_REGNO))
12546 (return)]
12547 "TARGET_32BIT
12548 && DEFAULT_ABI == ABI_AIX
12549 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12550 "b %z1"
12551 [(set_attr "type" "branch")
12552 (set_attr "length" "4")])
12554 (define_insn "*sibcall_value_nonlocal_aix64"
12555 [(set (match_operand 0 "" "")
12556 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12557 (match_operand 2 "" "g")))
12558 (use (match_operand:SI 3 "immediate_operand" "O"))
12559 (use (reg:SI LR_REGNO))
12560 (return)]
12561 "TARGET_64BIT
12562 && DEFAULT_ABI == ABI_AIX
12563 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12564 "b %z1"
12565 [(set_attr "type" "branch")
12566 (set_attr "length" "4")])
12568 (define_insn "*sibcall_nonlocal_sysv<mode>"
12569 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12570 (match_operand 1 "" ""))
12571 (use (match_operand 2 "immediate_operand" "O,n"))
12572 (use (reg:SI LR_REGNO))
12573 (return)]
12574 "(DEFAULT_ABI == ABI_DARWIN
12575 || DEFAULT_ABI == ABI_V4)
12576 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12577 "*
12578 {
12579 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12580 output_asm_insn (\"crxor 6,6,6\", operands);
12582 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12583 output_asm_insn (\"creqv 6,6,6\", operands);
12585 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12586 {
12587 gcc_assert (!TARGET_SECURE_PLT);
12588 return \"b %z0@plt\";
12589 }
12590 else
12591 return \"b %z0\";
12592 }"
12593 [(set_attr "type" "branch,branch")
12594 (set_attr "length" "4,8")])
12596 (define_expand "sibcall_value"
12597 [(parallel [(set (match_operand 0 "register_operand" "")
12598 (call (mem:SI (match_operand 1 "address_operand" ""))
12599 (match_operand 2 "" "")))
12600 (use (match_operand 3 "" ""))
12601 (use (reg:SI LR_REGNO))
12602 (return)])]
12603 ""
12604 "
12605 {
12606 #if TARGET_MACHO
12607 if (MACHOPIC_INDIRECT)
12608 operands[1] = machopic_indirect_call_target (operands[1]);
12609 #endif
12611 gcc_assert (GET_CODE (operands[1]) == MEM);
12612 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12614 operands[1] = XEXP (operands[1], 0);
12615 }")
12617 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12618 [(set (match_operand 0 "" "")
12619 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12620 (match_operand 2 "" "")))
12621 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12622 (use (reg:SI LR_REGNO))
12623 (return)]
12624 "(DEFAULT_ABI == ABI_DARWIN
12625 || DEFAULT_ABI == ABI_V4)
12626 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12627 "*
12628 {
12629 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12630 output_asm_insn (\"crxor 6,6,6\", operands);
12632 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12633 output_asm_insn (\"creqv 6,6,6\", operands);
12635 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12636 {
12637 gcc_assert (!TARGET_SECURE_PLT);
12638 return \"b %z1@plt\";
12639 }
12640 else
12641 return \"b %z1\";
12642 }"
12643 [(set_attr "type" "branch,branch")
12644 (set_attr "length" "4,8")])
12646 (define_expand "sibcall_epilogue"
12647 [(use (const_int 0))]
12648 "TARGET_SCHED_PROLOG"
12649 "
12650 {
12651 rs6000_emit_epilogue (TRUE);
12652 DONE;
12653 }")
12655 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12656 ;; all of memory. This blocks insns from being moved across this point.
12658 (define_insn "blockage"
12659 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12660 ""
12661 "")
12663 (define_insn "probe_stack"
12664 [(set (match_operand 0 "memory_operand" "=m")
12665 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12666 ""
12667 "{st%U0%X0|stw%U0%X0} 0,%0"
12668 [(set_attr "type" "store")
12669 (set_attr "length" "4")])
12670 \f
12671 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12672 ;; signed & unsigned, and one type of branch.
12673 ;;
12674 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12675 ;; insns, and branches.
12677 (define_expand "cbranch<mode>4"
12678 [(use (match_operator 0 "rs6000_cbranch_operator"
12679 [(match_operand:GPR 1 "gpc_reg_operand" "")
12680 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12681 (use (match_operand 3 ""))]
12682 ""
12683 "
12684 {
12685 /* Take care of the possibility that operands[2] might be negative but
12686 this might be a logical operation. That insn doesn't exist. */
12687 if (GET_CODE (operands[2]) == CONST_INT
12688 && INTVAL (operands[2]) < 0)
12689 {
12690 operands[2] = force_reg (<MODE>mode, operands[2]);
12691 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12692 GET_MODE (operands[0]),
12693 operands[1], operands[2]);
12694 }
12696 rs6000_emit_cbranch (<MODE>mode, operands);
12697 DONE;
12698 }")
12700 (define_expand "cbranch<mode>4"
12701 [(use (match_operator 0 "rs6000_cbranch_operator"
12702 [(match_operand:FP 1 "gpc_reg_operand" "")
12703 (match_operand:FP 2 "gpc_reg_operand" "")]))
12704 (use (match_operand 3 ""))]
12705 ""
12706 "
12707 {
12708 rs6000_emit_cbranch (<MODE>mode, operands);
12709 DONE;
12710 }")
12712 (define_expand "cstore<mode>4"
12713 [(use (match_operator 1 "rs6000_cbranch_operator"
12714 [(match_operand:GPR 2 "gpc_reg_operand" "")
12715 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12716 (clobber (match_operand:SI 0 "register_operand"))]
12717 ""
12718 "
12719 {
12720 /* Take care of the possibility that operands[3] might be negative but
12721 this might be a logical operation. That insn doesn't exist. */
12722 if (GET_CODE (operands[3]) == CONST_INT
12723 && INTVAL (operands[3]) < 0)
12724 {
12725 operands[3] = force_reg (<MODE>mode, operands[3]);
12726 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12727 GET_MODE (operands[1]),
12728 operands[2], operands[3]);
12729 }
12731 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12732 For SEQ, likewise, except that comparisons with zero should be done
12733 with an scc insns. However, due to the order that combine see the
12734 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12735 the cases we don't want to handle or are best handled by portable
12736 code. */
12737 if (GET_CODE (operands[1]) == NE)
12738 FAIL;
12739 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12740 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12741 && operands[3] == const0_rtx)
12742 FAIL;
12743 rs6000_emit_sCOND (<MODE>mode, operands);
12744 DONE;
12745 }")
12747 (define_expand "cstore<mode>4"
12748 [(use (match_operator 1 "rs6000_cbranch_operator"
12749 [(match_operand:FP 2 "gpc_reg_operand" "")
12750 (match_operand:FP 3 "gpc_reg_operand" "")]))
12751 (clobber (match_operand:SI 0 "register_operand"))]
12752 ""
12753 "
12754 {
12755 rs6000_emit_sCOND (<MODE>mode, operands);
12756 DONE;
12757 }")
12760 (define_expand "stack_protect_set"
12761 [(match_operand 0 "memory_operand" "")
12762 (match_operand 1 "memory_operand" "")]
12763 ""
12764 {
12765 #ifdef TARGET_THREAD_SSP_OFFSET
12766 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12767 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12768 operands[1] = gen_rtx_MEM (Pmode, addr);
12769 #endif
12770 if (TARGET_64BIT)
12771 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12772 else
12773 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12774 DONE;
12775 })
12777 (define_insn "stack_protect_setsi"
12778 [(set (match_operand:SI 0 "memory_operand" "=m")
12779 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12780 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12781 "TARGET_32BIT"
12782 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12783 [(set_attr "type" "three")
12784 (set_attr "length" "12")])
12786 (define_insn "stack_protect_setdi"
12787 [(set (match_operand:DI 0 "memory_operand" "=m")
12788 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12789 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12790 "TARGET_64BIT"
12791 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12792 [(set_attr "type" "three")
12793 (set_attr "length" "12")])
12795 (define_expand "stack_protect_test"
12796 [(match_operand 0 "memory_operand" "")
12797 (match_operand 1 "memory_operand" "")
12798 (match_operand 2 "" "")]
12799 ""
12800 {
12801 rtx test, op0, op1;
12802 #ifdef TARGET_THREAD_SSP_OFFSET
12803 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12804 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12805 operands[1] = gen_rtx_MEM (Pmode, addr);
12806 #endif
12807 op0 = operands[0];
12808 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12809 test = gen_rtx_EQ (VOIDmode, op0, op1);
12810 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12811 DONE;
12812 })
12814 (define_insn "stack_protect_testsi"
12815 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12816 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12817 (match_operand:SI 2 "memory_operand" "m,m")]
12818 UNSPEC_SP_TEST))
12819 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12820 (clobber (match_scratch:SI 3 "=&r,&r"))]
12821 "TARGET_32BIT"
12822 "@
12823 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12824 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12825 [(set_attr "length" "16,20")])
12827 (define_insn "stack_protect_testdi"
12828 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12829 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12830 (match_operand:DI 2 "memory_operand" "m,m")]
12831 UNSPEC_SP_TEST))
12832 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12833 (clobber (match_scratch:DI 3 "=&r,&r"))]
12834 "TARGET_64BIT"
12835 "@
12836 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12837 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12838 [(set_attr "length" "16,20")])
12840 \f
12841 ;; Here are the actual compare insns.
12842 (define_insn "*cmp<mode>_internal1"
12843 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12844 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12845 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12846 ""
12847 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12848 [(set_attr "type" "cmp")])
12850 ;; If we are comparing a register for equality with a large constant,
12851 ;; we can do this with an XOR followed by a compare. But this is profitable
12852 ;; only if the large constant is only used for the comparison (and in this
12853 ;; case we already have a register to reuse as scratch).
12854 ;;
12855 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12856 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12858 (define_peephole2
12859 [(set (match_operand:SI 0 "register_operand")
12860 (match_operand:SI 1 "logical_const_operand" ""))
12861 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12862 [(match_dup 0)
12863 (match_operand:SI 2 "logical_const_operand" "")]))
12864 (set (match_operand:CC 4 "cc_reg_operand" "")
12865 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12866 (match_dup 0)))
12867 (set (pc)
12868 (if_then_else (match_operator 6 "equality_operator"
12869 [(match_dup 4) (const_int 0)])
12870 (match_operand 7 "" "")
12871 (match_operand 8 "" "")))]
12872 "peep2_reg_dead_p (3, operands[0])
12873 && peep2_reg_dead_p (4, operands[4])"
12874 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12875 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12876 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12878 {
12879 /* Get the constant we are comparing against, and see what it looks like
12880 when sign-extended from 16 to 32 bits. Then see what constant we could
12881 XOR with SEXTC to get the sign-extended value. */
12882 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12883 SImode,
12884 operands[1], operands[2]);
12885 HOST_WIDE_INT c = INTVAL (cnst);
12886 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12887 HOST_WIDE_INT xorv = c ^ sextc;
12889 operands[9] = GEN_INT (xorv);
12890 operands[10] = GEN_INT (sextc);
12891 })
12893 (define_insn "*cmpsi_internal2"
12894 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12895 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12896 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12897 ""
12898 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12899 [(set_attr "type" "cmp")])
12901 (define_insn "*cmpdi_internal2"
12902 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12903 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12904 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12905 ""
12906 "cmpld%I2 %0,%1,%b2"
12907 [(set_attr "type" "cmp")])
12909 ;; The following two insns don't exist as single insns, but if we provide
12910 ;; them, we can swap an add and compare, which will enable us to overlap more
12911 ;; of the required delay between a compare and branch. We generate code for
12912 ;; them by splitting.
12914 (define_insn ""
12915 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12916 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12917 (match_operand:SI 2 "short_cint_operand" "i")))
12918 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12919 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12920 ""
12921 "#"
12922 [(set_attr "length" "8")])
12924 (define_insn ""
12925 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12926 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12927 (match_operand:SI 2 "u_short_cint_operand" "i")))
12928 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12929 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12930 ""
12931 "#"
12932 [(set_attr "length" "8")])
12934 (define_split
12935 [(set (match_operand:CC 3 "cc_reg_operand" "")
12936 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12937 (match_operand:SI 2 "short_cint_operand" "")))
12938 (set (match_operand:SI 0 "gpc_reg_operand" "")
12939 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12940 ""
12941 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12942 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12944 (define_split
12945 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12946 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12947 (match_operand:SI 2 "u_short_cint_operand" "")))
12948 (set (match_operand:SI 0 "gpc_reg_operand" "")
12949 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12950 ""
12951 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12952 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12954 (define_insn "*cmpsf_internal1"
12955 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12956 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12957 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12958 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12959 "fcmpu %0,%1,%2"
12960 [(set_attr "type" "fpcompare")])
12962 (define_insn "*cmpdf_internal1"
12963 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12964 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12965 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12966 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12967 && !VECTOR_UNIT_VSX_P (DFmode)"
12968 "fcmpu %0,%1,%2"
12969 [(set_attr "type" "fpcompare")])
12971 ;; Only need to compare second words if first words equal
12972 (define_insn "*cmptf_internal1"
12973 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12974 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12975 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12976 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12977 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12978 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12979 [(set_attr "type" "fpcompare")
12980 (set_attr "length" "12")])
12982 (define_insn_and_split "*cmptf_internal2"
12983 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12984 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12985 (match_operand:TF 2 "gpc_reg_operand" "d")))
12986 (clobber (match_scratch:DF 3 "=d"))
12987 (clobber (match_scratch:DF 4 "=d"))
12988 (clobber (match_scratch:DF 5 "=d"))
12989 (clobber (match_scratch:DF 6 "=d"))
12990 (clobber (match_scratch:DF 7 "=d"))
12991 (clobber (match_scratch:DF 8 "=d"))
12992 (clobber (match_scratch:DF 9 "=d"))
12993 (clobber (match_scratch:DF 10 "=d"))
12994 (clobber (match_scratch:GPR 11 "=b"))]
12995 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12996 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12997 "#"
12998 "&& reload_completed"
12999 [(set (match_dup 3) (match_dup 14))
13000 (set (match_dup 4) (match_dup 15))
13001 (set (match_dup 9) (abs:DF (match_dup 5)))
13002 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13003 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13004 (label_ref (match_dup 12))
13005 (pc)))
13006 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13007 (set (pc) (label_ref (match_dup 13)))
13008 (match_dup 12)
13009 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13010 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13011 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13012 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13013 (match_dup 13)]
13014 {
13015 REAL_VALUE_TYPE rv;
13016 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13017 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13019 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13020 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13021 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13022 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13023 operands[12] = gen_label_rtx ();
13024 operands[13] = gen_label_rtx ();
13025 real_inf (&rv);
13026 operands[14] = force_const_mem (DFmode,
13027 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13028 operands[15] = force_const_mem (DFmode,
13029 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13030 DFmode));
13031 if (TARGET_TOC)
13032 {
13033 rtx tocref;
13034 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13035 operands[14] = gen_const_mem (DFmode, tocref);
13036 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13037 operands[15] = gen_const_mem (DFmode, tocref);
13038 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13039 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13040 }
13041 })
13042 \f
13043 ;; Now we have the scc insns. We can do some combinations because of the
13044 ;; way the machine works.
13045 ;;
13046 ;; Note that this is probably faster if we can put an insn between the
13047 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13048 ;; cases the insns below which don't use an intermediate CR field will
13049 ;; be used instead.
13050 (define_insn ""
13051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13052 (match_operator:SI 1 "scc_comparison_operator"
13053 [(match_operand 2 "cc_reg_operand" "y")
13054 (const_int 0)]))]
13055 ""
13056 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13057 [(set (attr "type")
13058 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13059 (const_string "mfcrf")
13060 ]
13061 (const_string "mfcr")))
13062 (set_attr "length" "8")])
13064 ;; Same as above, but get the GT bit.
13065 (define_insn "move_from_CR_gt_bit"
13066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13067 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13068 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13069 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13070 [(set_attr "type" "mfcr")
13071 (set_attr "length" "8")])
13073 ;; Same as above, but get the OV/ORDERED bit.
13074 (define_insn "move_from_CR_ov_bit"
13075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13076 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13077 "TARGET_ISEL"
13078 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13079 [(set_attr "type" "mfcr")
13080 (set_attr "length" "8")])
13082 (define_insn ""
13083 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13084 (match_operator:DI 1 "scc_comparison_operator"
13085 [(match_operand 2 "cc_reg_operand" "y")
13086 (const_int 0)]))]
13087 "TARGET_POWERPC64"
13088 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13089 [(set (attr "type")
13090 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13091 (const_string "mfcrf")
13092 ]
13093 (const_string "mfcr")))
13094 (set_attr "length" "8")])
13096 (define_insn ""
13097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13098 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13099 [(match_operand 2 "cc_reg_operand" "y,y")
13100 (const_int 0)])
13101 (const_int 0)))
13102 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13103 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13104 "TARGET_32BIT"
13105 "@
13106 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13107 #"
13108 [(set_attr "type" "delayed_compare")
13109 (set_attr "length" "8,16")])
13111 (define_split
13112 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13113 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13114 [(match_operand 2 "cc_reg_operand" "")
13115 (const_int 0)])
13116 (const_int 0)))
13117 (set (match_operand:SI 3 "gpc_reg_operand" "")
13118 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13119 "TARGET_32BIT && reload_completed"
13120 [(set (match_dup 3)
13121 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13122 (set (match_dup 0)
13123 (compare:CC (match_dup 3)
13124 (const_int 0)))]
13125 "")
13127 (define_insn ""
13128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13129 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13130 [(match_operand 2 "cc_reg_operand" "y")
13131 (const_int 0)])
13132 (match_operand:SI 3 "const_int_operand" "n")))]
13133 ""
13134 "*
13135 {
13136 int is_bit = ccr_bit (operands[1], 1);
13137 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13138 int count;
13140 if (is_bit >= put_bit)
13141 count = is_bit - put_bit;
13142 else
13143 count = 32 - (put_bit - is_bit);
13145 operands[4] = GEN_INT (count);
13146 operands[5] = GEN_INT (put_bit);
13148 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13149 }"
13150 [(set (attr "type")
13151 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13152 (const_string "mfcrf")
13153 ]
13154 (const_string "mfcr")))
13155 (set_attr "length" "8")])
13157 (define_insn ""
13158 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13159 (compare:CC
13160 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13161 [(match_operand 2 "cc_reg_operand" "y,y")
13162 (const_int 0)])
13163 (match_operand:SI 3 "const_int_operand" "n,n"))
13164 (const_int 0)))
13165 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13166 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13167 (match_dup 3)))]
13168 ""
13169 "*
13170 {
13171 int is_bit = ccr_bit (operands[1], 1);
13172 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13173 int count;
13175 /* Force split for non-cc0 compare. */
13176 if (which_alternative == 1)
13177 return \"#\";
13179 if (is_bit >= put_bit)
13180 count = is_bit - put_bit;
13181 else
13182 count = 32 - (put_bit - is_bit);
13184 operands[5] = GEN_INT (count);
13185 operands[6] = GEN_INT (put_bit);
13187 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13188 }"
13189 [(set_attr "type" "delayed_compare")
13190 (set_attr "length" "8,16")])
13192 (define_split
13193 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13194 (compare:CC
13195 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13196 [(match_operand 2 "cc_reg_operand" "")
13197 (const_int 0)])
13198 (match_operand:SI 3 "const_int_operand" ""))
13199 (const_int 0)))
13200 (set (match_operand:SI 4 "gpc_reg_operand" "")
13201 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13202 (match_dup 3)))]
13203 "reload_completed"
13204 [(set (match_dup 4)
13205 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13206 (match_dup 3)))
13207 (set (match_dup 0)
13208 (compare:CC (match_dup 4)
13209 (const_int 0)))]
13210 "")
13212 ;; There is a 3 cycle delay between consecutive mfcr instructions
13213 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13215 (define_peephole
13216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13217 (match_operator:SI 1 "scc_comparison_operator"
13218 [(match_operand 2 "cc_reg_operand" "y")
13219 (const_int 0)]))
13220 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13221 (match_operator:SI 4 "scc_comparison_operator"
13222 [(match_operand 5 "cc_reg_operand" "y")
13223 (const_int 0)]))]
13224 "REGNO (operands[2]) != REGNO (operands[5])"
13225 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13226 [(set_attr "type" "mfcr")
13227 (set_attr "length" "12")])
13229 (define_peephole
13230 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13231 (match_operator:DI 1 "scc_comparison_operator"
13232 [(match_operand 2 "cc_reg_operand" "y")
13233 (const_int 0)]))
13234 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13235 (match_operator:DI 4 "scc_comparison_operator"
13236 [(match_operand 5 "cc_reg_operand" "y")
13237 (const_int 0)]))]
13238 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13239 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13240 [(set_attr "type" "mfcr")
13241 (set_attr "length" "12")])
13243 ;; There are some scc insns that can be done directly, without a compare.
13244 ;; These are faster because they don't involve the communications between
13245 ;; the FXU and branch units. In fact, we will be replacing all of the
13246 ;; integer scc insns here or in the portable methods in emit_store_flag.
13247 ;;
13248 ;; Also support (neg (scc ..)) since that construct is used to replace
13249 ;; branches, (plus (scc ..) ..) since that construct is common and
13250 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13251 ;; cases where it is no more expensive than (neg (scc ..)).
13253 ;; Have reload force a constant into a register for the simple insns that
13254 ;; otherwise won't accept constants. We do this because it is faster than
13255 ;; the cmp/mfcr sequence we would otherwise generate.
13257 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13258 (DI "rKJI")])
13260 (define_insn_and_split "*eq<mode>"
13261 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13262 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13263 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13264 "!TARGET_POWER"
13265 "#"
13266 "!TARGET_POWER"
13267 [(set (match_dup 0)
13268 (clz:GPR (match_dup 3)))
13269 (set (match_dup 0)
13270 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13271 {
13272 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13273 {
13274 /* Use output operand as intermediate. */
13275 operands[3] = operands[0];
13277 if (logical_operand (operands[2], <MODE>mode))
13278 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13279 gen_rtx_XOR (<MODE>mode,
13280 operands[1], operands[2])));
13281 else
13282 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13283 gen_rtx_PLUS (<MODE>mode, operands[1],
13284 negate_rtx (<MODE>mode,
13285 operands[2]))));
13286 }
13287 else
13288 operands[3] = operands[1];
13290 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13291 })
13293 (define_insn_and_split "*eq<mode>_compare"
13294 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13295 (compare:CC
13296 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13297 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13298 (const_int 0)))
13299 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13300 (eq:P (match_dup 1) (match_dup 2)))]
13301 "!TARGET_POWER && optimize_size"
13302 "#"
13303 "!TARGET_POWER && optimize_size"
13304 [(set (match_dup 0)
13305 (clz:P (match_dup 4)))
13306 (parallel [(set (match_dup 3)
13307 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13308 (const_int 0)))
13309 (set (match_dup 0)
13310 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13311 {
13312 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13313 {
13314 /* Use output operand as intermediate. */
13315 operands[4] = operands[0];
13317 if (logical_operand (operands[2], <MODE>mode))
13318 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13319 gen_rtx_XOR (<MODE>mode,
13320 operands[1], operands[2])));
13321 else
13322 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13323 gen_rtx_PLUS (<MODE>mode, operands[1],
13324 negate_rtx (<MODE>mode,
13325 operands[2]))));
13326 }
13327 else
13328 operands[4] = operands[1];
13330 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13331 })
13333 (define_insn "*eqsi_power"
13334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13335 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13336 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13337 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13338 "TARGET_POWER"
13339 "@
13340 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13341 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13342 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13343 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13344 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13345 [(set_attr "type" "three,two,three,three,three")
13346 (set_attr "length" "12,8,12,12,12")])
13348 ;; We have insns of the form shown by the first define_insn below. If
13349 ;; there is something inside the comparison operation, we must split it.
13350 (define_split
13351 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13352 (plus:SI (match_operator 1 "comparison_operator"
13353 [(match_operand:SI 2 "" "")
13354 (match_operand:SI 3
13355 "reg_or_cint_operand" "")])
13356 (match_operand:SI 4 "gpc_reg_operand" "")))
13357 (clobber (match_operand:SI 5 "register_operand" ""))]
13358 "! gpc_reg_operand (operands[2], SImode)"
13359 [(set (match_dup 5) (match_dup 2))
13360 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13361 (match_dup 4)))])
13363 (define_insn "*plus_eqsi"
13364 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13365 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13366 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13367 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13368 "TARGET_32BIT"
13369 "@
13370 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13371 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13372 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13373 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13374 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13375 [(set_attr "type" "three,two,three,three,three")
13376 (set_attr "length" "12,8,12,12,12")])
13378 (define_insn "*compare_plus_eqsi"
13379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13380 (compare:CC
13381 (plus:SI
13382 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13383 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13384 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13385 (const_int 0)))
13386 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13387 "TARGET_32BIT && optimize_size"
13388 "@
13389 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13390 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13391 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13392 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13393 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13394 #
13395 #
13396 #
13397 #
13398 #"
13399 [(set_attr "type" "compare")
13400 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13402 (define_split
13403 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13404 (compare:CC
13405 (plus:SI
13406 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13407 (match_operand:SI 2 "scc_eq_operand" ""))
13408 (match_operand:SI 3 "gpc_reg_operand" ""))
13409 (const_int 0)))
13410 (clobber (match_scratch:SI 4 ""))]
13411 "TARGET_32BIT && optimize_size && reload_completed"
13412 [(set (match_dup 4)
13413 (plus:SI (eq:SI (match_dup 1)
13414 (match_dup 2))
13415 (match_dup 3)))
13416 (set (match_dup 0)
13417 (compare:CC (match_dup 4)
13418 (const_int 0)))]
13419 "")
13421 (define_insn "*plus_eqsi_compare"
13422 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13423 (compare:CC
13424 (plus:SI
13425 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13426 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13427 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13428 (const_int 0)))
13429 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13430 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13431 "TARGET_32BIT && optimize_size"
13432 "@
13433 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13434 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13435 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13436 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13437 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13438 #
13439 #
13440 #
13441 #
13442 #"
13443 [(set_attr "type" "compare")
13444 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13446 (define_split
13447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13448 (compare:CC
13449 (plus:SI
13450 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13451 (match_operand:SI 2 "scc_eq_operand" ""))
13452 (match_operand:SI 3 "gpc_reg_operand" ""))
13453 (const_int 0)))
13454 (set (match_operand:SI 0 "gpc_reg_operand" "")
13455 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13456 "TARGET_32BIT && optimize_size && reload_completed"
13457 [(set (match_dup 0)
13458 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13459 (set (match_dup 4)
13460 (compare:CC (match_dup 0)
13461 (const_int 0)))]
13462 "")
13464 (define_insn "*neg_eq0<mode>"
13465 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13466 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13467 (const_int 0))))]
13468 ""
13469 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13470 [(set_attr "type" "two")
13471 (set_attr "length" "8")])
13473 (define_insn_and_split "*neg_eq<mode>"
13474 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13475 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13476 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13477 ""
13478 "#"
13479 ""
13480 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13481 {
13482 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13483 {
13484 /* Use output operand as intermediate. */
13485 operands[3] = operands[0];
13487 if (logical_operand (operands[2], <MODE>mode))
13488 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13489 gen_rtx_XOR (<MODE>mode,
13490 operands[1], operands[2])));
13491 else
13492 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13493 gen_rtx_PLUS (<MODE>mode, operands[1],
13494 negate_rtx (<MODE>mode,
13495 operands[2]))));
13496 }
13497 else
13498 operands[3] = operands[1];
13499 })
13501 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13502 ;; since it nabs/sr is just as fast.
13503 (define_insn "*ne0si"
13504 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13505 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13506 (const_int 31)))
13507 (clobber (match_scratch:SI 2 "=&r"))]
13508 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13509 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13510 [(set_attr "type" "two")
13511 (set_attr "length" "8")])
13513 (define_insn "*ne0di"
13514 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13515 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13516 (const_int 63)))
13517 (clobber (match_scratch:DI 2 "=&r"))]
13518 "TARGET_64BIT"
13519 "addic %2,%1,-1\;subfe %0,%2,%1"
13520 [(set_attr "type" "two")
13521 (set_attr "length" "8")])
13523 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13524 (define_insn "*plus_ne0si"
13525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13526 (plus:SI (lshiftrt:SI
13527 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13528 (const_int 31))
13529 (match_operand:SI 2 "gpc_reg_operand" "r")))
13530 (clobber (match_scratch:SI 3 "=&r"))]
13531 "TARGET_32BIT"
13532 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13533 [(set_attr "type" "two")
13534 (set_attr "length" "8")])
13536 (define_insn "*plus_ne0di"
13537 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13538 (plus:DI (lshiftrt:DI
13539 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13540 (const_int 63))
13541 (match_operand:DI 2 "gpc_reg_operand" "r")))
13542 (clobber (match_scratch:DI 3 "=&r"))]
13543 "TARGET_64BIT"
13544 "addic %3,%1,-1\;addze %0,%2"
13545 [(set_attr "type" "two")
13546 (set_attr "length" "8")])
13548 (define_insn "*compare_plus_ne0si"
13549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13550 (compare:CC
13551 (plus:SI (lshiftrt:SI
13552 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13553 (const_int 31))
13554 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13555 (const_int 0)))
13556 (clobber (match_scratch:SI 3 "=&r,&r"))
13557 (clobber (match_scratch:SI 4 "=X,&r"))]
13558 "TARGET_32BIT"
13559 "@
13560 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13561 #"
13562 [(set_attr "type" "compare")
13563 (set_attr "length" "8,12")])
13565 (define_split
13566 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13567 (compare:CC
13568 (plus:SI (lshiftrt:SI
13569 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13570 (const_int 31))
13571 (match_operand:SI 2 "gpc_reg_operand" ""))
13572 (const_int 0)))
13573 (clobber (match_scratch:SI 3 ""))
13574 (clobber (match_scratch:SI 4 ""))]
13575 "TARGET_32BIT && reload_completed"
13576 [(parallel [(set (match_dup 3)
13577 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13578 (const_int 31))
13579 (match_dup 2)))
13580 (clobber (match_dup 4))])
13581 (set (match_dup 0)
13582 (compare:CC (match_dup 3)
13583 (const_int 0)))]
13584 "")
13586 (define_insn "*compare_plus_ne0di"
13587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13588 (compare:CC
13589 (plus:DI (lshiftrt:DI
13590 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13591 (const_int 63))
13592 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13593 (const_int 0)))
13594 (clobber (match_scratch:DI 3 "=&r,&r"))]
13595 "TARGET_64BIT"
13596 "@
13597 addic %3,%1,-1\;addze. %3,%2
13598 #"
13599 [(set_attr "type" "compare")
13600 (set_attr "length" "8,12")])
13602 (define_split
13603 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13604 (compare:CC
13605 (plus:DI (lshiftrt:DI
13606 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13607 (const_int 63))
13608 (match_operand:DI 2 "gpc_reg_operand" ""))
13609 (const_int 0)))
13610 (clobber (match_scratch:DI 3 ""))]
13611 "TARGET_64BIT && reload_completed"
13612 [(set (match_dup 3)
13613 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13614 (const_int 63))
13615 (match_dup 2)))
13616 (set (match_dup 0)
13617 (compare:CC (match_dup 3)
13618 (const_int 0)))]
13619 "")
13621 (define_insn "*plus_ne0si_compare"
13622 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13623 (compare:CC
13624 (plus:SI (lshiftrt:SI
13625 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13626 (const_int 31))
13627 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13628 (const_int 0)))
13629 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13630 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13631 (match_dup 2)))
13632 (clobber (match_scratch:SI 3 "=&r,&r"))]
13633 "TARGET_32BIT"
13634 "@
13635 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13636 #"
13637 [(set_attr "type" "compare")
13638 (set_attr "length" "8,12")])
13640 (define_split
13641 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13642 (compare:CC
13643 (plus:SI (lshiftrt:SI
13644 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13645 (const_int 31))
13646 (match_operand:SI 2 "gpc_reg_operand" ""))
13647 (const_int 0)))
13648 (set (match_operand:SI 0 "gpc_reg_operand" "")
13649 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13650 (match_dup 2)))
13651 (clobber (match_scratch:SI 3 ""))]
13652 "TARGET_32BIT && reload_completed"
13653 [(parallel [(set (match_dup 0)
13654 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13655 (match_dup 2)))
13656 (clobber (match_dup 3))])
13657 (set (match_dup 4)
13658 (compare:CC (match_dup 0)
13659 (const_int 0)))]
13660 "")
13662 (define_insn "*plus_ne0di_compare"
13663 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13664 (compare:CC
13665 (plus:DI (lshiftrt:DI
13666 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13667 (const_int 63))
13668 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13669 (const_int 0)))
13670 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13671 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13672 (match_dup 2)))
13673 (clobber (match_scratch:DI 3 "=&r,&r"))]
13674 "TARGET_64BIT"
13675 "@
13676 addic %3,%1,-1\;addze. %0,%2
13677 #"
13678 [(set_attr "type" "compare")
13679 (set_attr "length" "8,12")])
13681 (define_split
13682 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13683 (compare:CC
13684 (plus:DI (lshiftrt:DI
13685 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13686 (const_int 63))
13687 (match_operand:DI 2 "gpc_reg_operand" ""))
13688 (const_int 0)))
13689 (set (match_operand:DI 0 "gpc_reg_operand" "")
13690 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13691 (match_dup 2)))
13692 (clobber (match_scratch:DI 3 ""))]
13693 "TARGET_64BIT && reload_completed"
13694 [(parallel [(set (match_dup 0)
13695 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13696 (match_dup 2)))
13697 (clobber (match_dup 3))])
13698 (set (match_dup 4)
13699 (compare:CC (match_dup 0)
13700 (const_int 0)))]
13701 "")
13703 (define_insn ""
13704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13705 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13706 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13707 (clobber (match_scratch:SI 3 "=r,X"))]
13708 "TARGET_POWER"
13709 "@
13710 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13711 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13712 [(set_attr "length" "12")])
13714 (define_insn ""
13715 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13716 (compare:CC
13717 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13718 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13719 (const_int 0)))
13720 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13721 (le:SI (match_dup 1) (match_dup 2)))
13722 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13723 "TARGET_POWER"
13724 "@
13725 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13726 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13727 #
13728 #"
13729 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13730 (set_attr "length" "12,12,16,16")])
13732 (define_split
13733 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13734 (compare:CC
13735 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13736 (match_operand:SI 2 "reg_or_short_operand" ""))
13737 (const_int 0)))
13738 (set (match_operand:SI 0 "gpc_reg_operand" "")
13739 (le:SI (match_dup 1) (match_dup 2)))
13740 (clobber (match_scratch:SI 3 ""))]
13741 "TARGET_POWER && reload_completed"
13742 [(parallel [(set (match_dup 0)
13743 (le:SI (match_dup 1) (match_dup 2)))
13744 (clobber (match_dup 3))])
13745 (set (match_dup 4)
13746 (compare:CC (match_dup 0)
13747 (const_int 0)))]
13748 "")
13750 (define_insn ""
13751 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13752 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13753 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13754 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13755 "TARGET_POWER"
13756 "@
13757 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13758 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13759 [(set_attr "length" "12")])
13761 (define_insn ""
13762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13763 (compare:CC
13764 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13765 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13766 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13767 (const_int 0)))
13768 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13769 "TARGET_POWER"
13770 "@
13771 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13772 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13773 #
13774 #"
13775 [(set_attr "type" "compare")
13776 (set_attr "length" "12,12,16,16")])
13778 (define_split
13779 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13780 (compare:CC
13781 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13782 (match_operand:SI 2 "reg_or_short_operand" ""))
13783 (match_operand:SI 3 "gpc_reg_operand" ""))
13784 (const_int 0)))
13785 (clobber (match_scratch:SI 4 ""))]
13786 "TARGET_POWER && reload_completed"
13787 [(set (match_dup 4)
13788 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13789 (match_dup 3)))
13790 (set (match_dup 0)
13791 (compare:CC (match_dup 4)
13792 (const_int 0)))]
13793 "")
13795 (define_insn ""
13796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13797 (compare:CC
13798 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13799 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13800 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13801 (const_int 0)))
13802 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13803 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13804 "TARGET_POWER"
13805 "@
13806 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13807 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13808 #
13809 #"
13810 [(set_attr "type" "compare")
13811 (set_attr "length" "12,12,16,16")])
13813 (define_split
13814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13815 (compare:CC
13816 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13817 (match_operand:SI 2 "reg_or_short_operand" ""))
13818 (match_operand:SI 3 "gpc_reg_operand" ""))
13819 (const_int 0)))
13820 (set (match_operand:SI 0 "gpc_reg_operand" "")
13821 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13822 "TARGET_POWER && reload_completed"
13823 [(set (match_dup 0)
13824 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13825 (set (match_dup 4)
13826 (compare:CC (match_dup 0)
13827 (const_int 0)))]
13828 "")
13830 (define_insn ""
13831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13832 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13833 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13834 "TARGET_POWER"
13835 "@
13836 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13837 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13838 [(set_attr "length" "12")])
13840 (define_insn "*leu<mode>"
13841 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13842 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13843 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13844 ""
13845 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13846 [(set_attr "type" "three")
13847 (set_attr "length" "12")])
13849 (define_insn "*leu<mode>_compare"
13850 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13851 (compare:CC
13852 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13853 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13854 (const_int 0)))
13855 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13856 (leu:P (match_dup 1) (match_dup 2)))]
13857 ""
13858 "@
13859 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13860 #"
13861 [(set_attr "type" "compare")
13862 (set_attr "length" "12,16")])
13864 (define_split
13865 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13866 (compare:CC
13867 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13868 (match_operand:P 2 "reg_or_short_operand" ""))
13869 (const_int 0)))
13870 (set (match_operand:P 0 "gpc_reg_operand" "")
13871 (leu:P (match_dup 1) (match_dup 2)))]
13872 "reload_completed"
13873 [(set (match_dup 0)
13874 (leu:P (match_dup 1) (match_dup 2)))
13875 (set (match_dup 3)
13876 (compare:CC (match_dup 0)
13877 (const_int 0)))]
13878 "")
13880 (define_insn "*plus_leu<mode>"
13881 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13882 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13883 (match_operand:P 2 "reg_or_short_operand" "rI"))
13884 (match_operand:P 3 "gpc_reg_operand" "r")))]
13885 ""
13886 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13887 [(set_attr "type" "two")
13888 (set_attr "length" "8")])
13890 (define_insn ""
13891 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13892 (compare:CC
13893 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13894 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13895 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13896 (const_int 0)))
13897 (clobber (match_scratch:SI 4 "=&r,&r"))]
13898 "TARGET_32BIT"
13899 "@
13900 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13901 #"
13902 [(set_attr "type" "compare")
13903 (set_attr "length" "8,12")])
13905 (define_split
13906 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13907 (compare:CC
13908 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13909 (match_operand:SI 2 "reg_or_short_operand" ""))
13910 (match_operand:SI 3 "gpc_reg_operand" ""))
13911 (const_int 0)))
13912 (clobber (match_scratch:SI 4 ""))]
13913 "TARGET_32BIT && reload_completed"
13914 [(set (match_dup 4)
13915 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13916 (match_dup 3)))
13917 (set (match_dup 0)
13918 (compare:CC (match_dup 4)
13919 (const_int 0)))]
13920 "")
13922 (define_insn ""
13923 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13924 (compare:CC
13925 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13926 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13927 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13928 (const_int 0)))
13929 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13930 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13931 "TARGET_32BIT"
13932 "@
13933 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13934 #"
13935 [(set_attr "type" "compare")
13936 (set_attr "length" "8,12")])
13938 (define_split
13939 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13940 (compare:CC
13941 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13942 (match_operand:SI 2 "reg_or_short_operand" ""))
13943 (match_operand:SI 3 "gpc_reg_operand" ""))
13944 (const_int 0)))
13945 (set (match_operand:SI 0 "gpc_reg_operand" "")
13946 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13947 "TARGET_32BIT && reload_completed"
13948 [(set (match_dup 0)
13949 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13950 (set (match_dup 4)
13951 (compare:CC (match_dup 0)
13952 (const_int 0)))]
13953 "")
13955 (define_insn "*neg_leu<mode>"
13956 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13957 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13958 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13959 ""
13960 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13961 [(set_attr "type" "three")
13962 (set_attr "length" "12")])
13964 (define_insn "*and_neg_leu<mode>"
13965 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13966 (and:P (neg:P
13967 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13968 (match_operand:P 2 "reg_or_short_operand" "rI")))
13969 (match_operand:P 3 "gpc_reg_operand" "r")))]
13970 ""
13971 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13972 [(set_attr "type" "three")
13973 (set_attr "length" "12")])
13975 (define_insn ""
13976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13977 (compare:CC
13978 (and:SI (neg:SI
13979 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13980 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13981 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13982 (const_int 0)))
13983 (clobber (match_scratch:SI 4 "=&r,&r"))]
13984 "TARGET_32BIT"
13985 "@
13986 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13987 #"
13988 [(set_attr "type" "compare")
13989 (set_attr "length" "12,16")])
13991 (define_split
13992 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13993 (compare:CC
13994 (and:SI (neg:SI
13995 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13996 (match_operand:SI 2 "reg_or_short_operand" "")))
13997 (match_operand:SI 3 "gpc_reg_operand" ""))
13998 (const_int 0)))
13999 (clobber (match_scratch:SI 4 ""))]
14000 "TARGET_32BIT && reload_completed"
14001 [(set (match_dup 4)
14002 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14003 (match_dup 3)))
14004 (set (match_dup 0)
14005 (compare:CC (match_dup 4)
14006 (const_int 0)))]
14007 "")
14009 (define_insn ""
14010 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14011 (compare:CC
14012 (and:SI (neg:SI
14013 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14014 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14015 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14016 (const_int 0)))
14017 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14018 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14019 "TARGET_32BIT"
14020 "@
14021 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14022 #"
14023 [(set_attr "type" "compare")
14024 (set_attr "length" "12,16")])
14026 (define_split
14027 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14028 (compare:CC
14029 (and:SI (neg:SI
14030 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14031 (match_operand:SI 2 "reg_or_short_operand" "")))
14032 (match_operand:SI 3 "gpc_reg_operand" ""))
14033 (const_int 0)))
14034 (set (match_operand:SI 0 "gpc_reg_operand" "")
14035 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14036 "TARGET_32BIT && reload_completed"
14037 [(set (match_dup 0)
14038 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14039 (match_dup 3)))
14040 (set (match_dup 4)
14041 (compare:CC (match_dup 0)
14042 (const_int 0)))]
14043 "")
14045 (define_insn ""
14046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14047 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14048 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14049 "TARGET_POWER"
14050 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14051 [(set_attr "length" "12")])
14053 (define_insn ""
14054 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14055 (compare:CC
14056 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14057 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14058 (const_int 0)))
14059 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14060 (lt:SI (match_dup 1) (match_dup 2)))]
14061 "TARGET_POWER"
14062 "@
14063 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14064 #"
14065 [(set_attr "type" "delayed_compare")
14066 (set_attr "length" "12,16")])
14068 (define_split
14069 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14070 (compare:CC
14071 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14072 (match_operand:SI 2 "reg_or_short_operand" ""))
14073 (const_int 0)))
14074 (set (match_operand:SI 0 "gpc_reg_operand" "")
14075 (lt:SI (match_dup 1) (match_dup 2)))]
14076 "TARGET_POWER && reload_completed"
14077 [(set (match_dup 0)
14078 (lt:SI (match_dup 1) (match_dup 2)))
14079 (set (match_dup 3)
14080 (compare:CC (match_dup 0)
14081 (const_int 0)))]
14082 "")
14084 (define_insn ""
14085 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14086 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14087 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14088 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14089 "TARGET_POWER"
14090 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14091 [(set_attr "length" "12")])
14093 (define_insn ""
14094 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14095 (compare:CC
14096 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14097 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14098 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14099 (const_int 0)))
14100 (clobber (match_scratch:SI 4 "=&r,&r"))]
14101 "TARGET_POWER"
14102 "@
14103 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14104 #"
14105 [(set_attr "type" "compare")
14106 (set_attr "length" "12,16")])
14108 (define_split
14109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14110 (compare:CC
14111 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14112 (match_operand:SI 2 "reg_or_short_operand" ""))
14113 (match_operand:SI 3 "gpc_reg_operand" ""))
14114 (const_int 0)))
14115 (clobber (match_scratch:SI 4 ""))]
14116 "TARGET_POWER && reload_completed"
14117 [(set (match_dup 4)
14118 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14119 (match_dup 3)))
14120 (set (match_dup 0)
14121 (compare:CC (match_dup 4)
14122 (const_int 0)))]
14123 "")
14125 (define_insn ""
14126 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14127 (compare:CC
14128 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14129 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14130 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14131 (const_int 0)))
14132 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14133 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14134 "TARGET_POWER"
14135 "@
14136 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14137 #"
14138 [(set_attr "type" "compare")
14139 (set_attr "length" "12,16")])
14141 (define_split
14142 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14143 (compare:CC
14144 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14145 (match_operand:SI 2 "reg_or_short_operand" ""))
14146 (match_operand:SI 3 "gpc_reg_operand" ""))
14147 (const_int 0)))
14148 (set (match_operand:SI 0 "gpc_reg_operand" "")
14149 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14150 "TARGET_POWER && reload_completed"
14151 [(set (match_dup 0)
14152 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14153 (set (match_dup 4)
14154 (compare:CC (match_dup 0)
14155 (const_int 0)))]
14156 "")
14158 (define_insn ""
14159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14160 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14161 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14162 "TARGET_POWER"
14163 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14164 [(set_attr "length" "12")])
14166 (define_insn_and_split "*ltu<mode>"
14167 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14168 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14169 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14170 ""
14171 "#"
14172 ""
14173 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14174 (set (match_dup 0) (neg:P (match_dup 0)))]
14175 "")
14177 (define_insn_and_split "*ltu<mode>_compare"
14178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14179 (compare:CC
14180 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14181 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14182 (const_int 0)))
14183 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14184 (ltu:P (match_dup 1) (match_dup 2)))]
14185 ""
14186 "#"
14187 ""
14188 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14189 (parallel [(set (match_dup 3)
14190 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14191 (set (match_dup 0) (neg:P (match_dup 0)))])]
14192 "")
14194 (define_insn_and_split "*plus_ltu<mode>"
14195 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14196 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14197 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14198 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14199 ""
14200 "#"
14201 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14202 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14203 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14204 "")
14206 (define_insn_and_split "*plus_ltu<mode>_compare"
14207 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14208 (compare:CC
14209 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14210 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14211 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14212 (const_int 0)))
14213 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14214 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14215 ""
14216 "#"
14217 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14218 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14219 (parallel [(set (match_dup 4)
14220 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14221 (const_int 0)))
14222 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14223 "")
14225 (define_insn "*neg_ltu<mode>"
14226 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14227 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14228 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14229 ""
14230 "@
14231 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14232 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14233 [(set_attr "type" "two")
14234 (set_attr "length" "8")])
14236 (define_insn ""
14237 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14238 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14239 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14240 (clobber (match_scratch:SI 3 "=r"))]
14241 "TARGET_POWER"
14242 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14243 [(set_attr "length" "12")])
14245 (define_insn ""
14246 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14247 (compare:CC
14248 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14249 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14250 (const_int 0)))
14251 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14252 (ge:SI (match_dup 1) (match_dup 2)))
14253 (clobber (match_scratch:SI 3 "=r,r"))]
14254 "TARGET_POWER"
14255 "@
14256 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14257 #"
14258 [(set_attr "type" "compare")
14259 (set_attr "length" "12,16")])
14261 (define_split
14262 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14263 (compare:CC
14264 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14265 (match_operand:SI 2 "reg_or_short_operand" ""))
14266 (const_int 0)))
14267 (set (match_operand:SI 0 "gpc_reg_operand" "")
14268 (ge:SI (match_dup 1) (match_dup 2)))
14269 (clobber (match_scratch:SI 3 ""))]
14270 "TARGET_POWER && reload_completed"
14271 [(parallel [(set (match_dup 0)
14272 (ge:SI (match_dup 1) (match_dup 2)))
14273 (clobber (match_dup 3))])
14274 (set (match_dup 4)
14275 (compare:CC (match_dup 0)
14276 (const_int 0)))]
14277 "")
14279 (define_insn ""
14280 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14281 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14282 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14283 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14284 "TARGET_POWER"
14285 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14286 [(set_attr "length" "12")])
14288 (define_insn ""
14289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14290 (compare:CC
14291 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14292 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14293 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14294 (const_int 0)))
14295 (clobber (match_scratch:SI 4 "=&r,&r"))]
14296 "TARGET_POWER"
14297 "@
14298 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14299 #"
14300 [(set_attr "type" "compare")
14301 (set_attr "length" "12,16")])
14303 (define_split
14304 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14305 (compare:CC
14306 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14307 (match_operand:SI 2 "reg_or_short_operand" ""))
14308 (match_operand:SI 3 "gpc_reg_operand" ""))
14309 (const_int 0)))
14310 (clobber (match_scratch:SI 4 ""))]
14311 "TARGET_POWER && reload_completed"
14312 [(set (match_dup 4)
14313 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14314 (match_dup 3)))
14315 (set (match_dup 0)
14316 (compare:CC (match_dup 4)
14317 (const_int 0)))]
14318 "")
14320 (define_insn ""
14321 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14322 (compare:CC
14323 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14324 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14325 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14326 (const_int 0)))
14327 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14328 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14329 "TARGET_POWER"
14330 "@
14331 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14332 #"
14333 [(set_attr "type" "compare")
14334 (set_attr "length" "12,16")])
14336 (define_split
14337 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14338 (compare:CC
14339 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14340 (match_operand:SI 2 "reg_or_short_operand" ""))
14341 (match_operand:SI 3 "gpc_reg_operand" ""))
14342 (const_int 0)))
14343 (set (match_operand:SI 0 "gpc_reg_operand" "")
14344 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14345 "TARGET_POWER && reload_completed"
14346 [(set (match_dup 0)
14347 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14348 (set (match_dup 4)
14349 (compare:CC (match_dup 0)
14350 (const_int 0)))]
14351 "")
14353 (define_insn ""
14354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14355 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14356 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14357 "TARGET_POWER"
14358 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14359 [(set_attr "length" "12")])
14361 (define_insn "*geu<mode>"
14362 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14363 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14364 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14365 ""
14366 "@
14367 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14368 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14369 [(set_attr "type" "three")
14370 (set_attr "length" "12")])
14372 (define_insn "*geu<mode>_compare"
14373 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14374 (compare:CC
14375 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14376 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14377 (const_int 0)))
14378 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14379 (geu:P (match_dup 1) (match_dup 2)))]
14380 ""
14381 "@
14382 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14383 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14384 #
14385 #"
14386 [(set_attr "type" "compare")
14387 (set_attr "length" "12,12,16,16")])
14389 (define_split
14390 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14391 (compare:CC
14392 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14393 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14394 (const_int 0)))
14395 (set (match_operand:P 0 "gpc_reg_operand" "")
14396 (geu:P (match_dup 1) (match_dup 2)))]
14397 "reload_completed"
14398 [(set (match_dup 0)
14399 (geu:P (match_dup 1) (match_dup 2)))
14400 (set (match_dup 3)
14401 (compare:CC (match_dup 0)
14402 (const_int 0)))]
14403 "")
14405 (define_insn "*plus_geu<mode>"
14406 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14407 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14408 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14409 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14410 ""
14411 "@
14412 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14413 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14414 [(set_attr "type" "two")
14415 (set_attr "length" "8")])
14417 (define_insn ""
14418 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14419 (compare:CC
14420 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14421 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14422 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14423 (const_int 0)))
14424 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14425 "TARGET_32BIT"
14426 "@
14427 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14428 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14429 #
14430 #"
14431 [(set_attr "type" "compare")
14432 (set_attr "length" "8,8,12,12")])
14434 (define_split
14435 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14436 (compare:CC
14437 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14438 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14439 (match_operand:SI 3 "gpc_reg_operand" ""))
14440 (const_int 0)))
14441 (clobber (match_scratch:SI 4 ""))]
14442 "TARGET_32BIT && reload_completed"
14443 [(set (match_dup 4)
14444 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14445 (match_dup 3)))
14446 (set (match_dup 0)
14447 (compare:CC (match_dup 4)
14448 (const_int 0)))]
14449 "")
14451 (define_insn ""
14452 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14453 (compare:CC
14454 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14455 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14456 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14457 (const_int 0)))
14458 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14459 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14460 "TARGET_32BIT"
14461 "@
14462 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14463 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14464 #
14465 #"
14466 [(set_attr "type" "compare")
14467 (set_attr "length" "8,8,12,12")])
14469 (define_split
14470 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14471 (compare:CC
14472 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14473 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14474 (match_operand:SI 3 "gpc_reg_operand" ""))
14475 (const_int 0)))
14476 (set (match_operand:SI 0 "gpc_reg_operand" "")
14477 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14478 "TARGET_32BIT && reload_completed"
14479 [(set (match_dup 0)
14480 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14481 (set (match_dup 4)
14482 (compare:CC (match_dup 0)
14483 (const_int 0)))]
14484 "")
14486 (define_insn "*neg_geu<mode>"
14487 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14488 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14489 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14490 ""
14491 "@
14492 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14493 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14494 [(set_attr "type" "three")
14495 (set_attr "length" "12")])
14497 (define_insn "*and_neg_geu<mode>"
14498 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14499 (and:P (neg:P
14500 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14501 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14502 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14503 ""
14504 "@
14505 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14506 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14507 [(set_attr "type" "three")
14508 (set_attr "length" "12")])
14510 (define_insn ""
14511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14512 (compare:CC
14513 (and:SI (neg:SI
14514 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14515 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14516 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14517 (const_int 0)))
14518 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14519 "TARGET_32BIT"
14520 "@
14521 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14522 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14523 #
14524 #"
14525 [(set_attr "type" "compare")
14526 (set_attr "length" "12,12,16,16")])
14528 (define_split
14529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14530 (compare:CC
14531 (and:SI (neg:SI
14532 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14533 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14534 (match_operand:SI 3 "gpc_reg_operand" ""))
14535 (const_int 0)))
14536 (clobber (match_scratch:SI 4 ""))]
14537 "TARGET_32BIT && reload_completed"
14538 [(set (match_dup 4)
14539 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14540 (match_dup 3)))
14541 (set (match_dup 0)
14542 (compare:CC (match_dup 4)
14543 (const_int 0)))]
14544 "")
14546 (define_insn ""
14547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14548 (compare:CC
14549 (and:SI (neg:SI
14550 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14551 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14552 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14553 (const_int 0)))
14554 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14555 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14556 "TARGET_32BIT"
14557 "@
14558 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14559 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14560 #
14561 #"
14562 [(set_attr "type" "compare")
14563 (set_attr "length" "12,12,16,16")])
14565 (define_split
14566 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14567 (compare:CC
14568 (and:SI (neg:SI
14569 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14570 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14571 (match_operand:SI 3 "gpc_reg_operand" ""))
14572 (const_int 0)))
14573 (set (match_operand:SI 0 "gpc_reg_operand" "")
14574 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14575 "TARGET_32BIT && reload_completed"
14576 [(set (match_dup 0)
14577 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14578 (set (match_dup 4)
14579 (compare:CC (match_dup 0)
14580 (const_int 0)))]
14581 "")
14583 (define_insn ""
14584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14585 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14586 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14587 "TARGET_POWER"
14588 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14589 [(set_attr "length" "12")])
14591 (define_insn ""
14592 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14593 (compare:CC
14594 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14595 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14596 (const_int 0)))
14597 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14598 (gt:SI (match_dup 1) (match_dup 2)))]
14599 "TARGET_POWER"
14600 "@
14601 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14602 #"
14603 [(set_attr "type" "delayed_compare")
14604 (set_attr "length" "12,16")])
14606 (define_split
14607 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14608 (compare:CC
14609 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14610 (match_operand:SI 2 "reg_or_short_operand" ""))
14611 (const_int 0)))
14612 (set (match_operand:SI 0 "gpc_reg_operand" "")
14613 (gt:SI (match_dup 1) (match_dup 2)))]
14614 "TARGET_POWER && reload_completed"
14615 [(set (match_dup 0)
14616 (gt:SI (match_dup 1) (match_dup 2)))
14617 (set (match_dup 3)
14618 (compare:CC (match_dup 0)
14619 (const_int 0)))]
14620 "")
14622 (define_insn "*plus_gt0<mode>"
14623 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14624 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14625 (const_int 0))
14626 (match_operand:P 2 "gpc_reg_operand" "r")))]
14627 ""
14628 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14629 [(set_attr "type" "three")
14630 (set_attr "length" "12")])
14632 (define_insn ""
14633 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14634 (compare:CC
14635 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14636 (const_int 0))
14637 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14638 (const_int 0)))
14639 (clobber (match_scratch:SI 3 "=&r,&r"))]
14640 "TARGET_32BIT"
14641 "@
14642 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14643 #"
14644 [(set_attr "type" "compare")
14645 (set_attr "length" "12,16")])
14647 (define_split
14648 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14649 (compare:CC
14650 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14651 (const_int 0))
14652 (match_operand:SI 2 "gpc_reg_operand" ""))
14653 (const_int 0)))
14654 (clobber (match_scratch:SI 3 ""))]
14655 "TARGET_32BIT && reload_completed"
14656 [(set (match_dup 3)
14657 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14658 (match_dup 2)))
14659 (set (match_dup 0)
14660 (compare:CC (match_dup 3)
14661 (const_int 0)))]
14662 "")
14664 (define_insn ""
14665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14666 (compare:CC
14667 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14668 (const_int 0))
14669 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14670 (const_int 0)))
14671 (clobber (match_scratch:DI 3 "=&r,&r"))]
14672 "TARGET_64BIT"
14673 "@
14674 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14675 #"
14676 [(set_attr "type" "compare")
14677 (set_attr "length" "12,16")])
14679 (define_split
14680 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14681 (compare:CC
14682 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14683 (const_int 0))
14684 (match_operand:DI 2 "gpc_reg_operand" ""))
14685 (const_int 0)))
14686 (clobber (match_scratch:DI 3 ""))]
14687 "TARGET_64BIT && reload_completed"
14688 [(set (match_dup 3)
14689 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14690 (match_dup 2)))
14691 (set (match_dup 0)
14692 (compare:CC (match_dup 3)
14693 (const_int 0)))]
14694 "")
14696 (define_insn ""
14697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14698 (compare:CC
14699 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14700 (const_int 0))
14701 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14702 (const_int 0)))
14703 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14704 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14705 "TARGET_32BIT"
14706 "@
14707 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14708 #"
14709 [(set_attr "type" "compare")
14710 (set_attr "length" "12,16")])
14712 (define_split
14713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14714 (compare:CC
14715 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14716 (const_int 0))
14717 (match_operand:SI 2 "gpc_reg_operand" ""))
14718 (const_int 0)))
14719 (set (match_operand:SI 0 "gpc_reg_operand" "")
14720 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14721 "TARGET_32BIT && reload_completed"
14722 [(set (match_dup 0)
14723 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14724 (set (match_dup 3)
14725 (compare:CC (match_dup 0)
14726 (const_int 0)))]
14727 "")
14729 (define_insn ""
14730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14731 (compare:CC
14732 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14733 (const_int 0))
14734 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14735 (const_int 0)))
14736 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14737 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14738 "TARGET_64BIT"
14739 "@
14740 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14741 #"
14742 [(set_attr "type" "compare")
14743 (set_attr "length" "12,16")])
14745 (define_split
14746 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14747 (compare:CC
14748 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14749 (const_int 0))
14750 (match_operand:DI 2 "gpc_reg_operand" ""))
14751 (const_int 0)))
14752 (set (match_operand:DI 0 "gpc_reg_operand" "")
14753 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14754 "TARGET_64BIT && reload_completed"
14755 [(set (match_dup 0)
14756 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14757 (set (match_dup 3)
14758 (compare:CC (match_dup 0)
14759 (const_int 0)))]
14760 "")
14762 (define_insn ""
14763 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14764 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14765 (match_operand:SI 2 "reg_or_short_operand" "r"))
14766 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14767 "TARGET_POWER"
14768 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14769 [(set_attr "length" "12")])
14771 (define_insn ""
14772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14773 (compare:CC
14774 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14775 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14776 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14777 (const_int 0)))
14778 (clobber (match_scratch:SI 4 "=&r,&r"))]
14779 "TARGET_POWER"
14780 "@
14781 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14782 #"
14783 [(set_attr "type" "compare")
14784 (set_attr "length" "12,16")])
14786 (define_split
14787 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14788 (compare:CC
14789 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14790 (match_operand:SI 2 "reg_or_short_operand" ""))
14791 (match_operand:SI 3 "gpc_reg_operand" ""))
14792 (const_int 0)))
14793 (clobber (match_scratch:SI 4 ""))]
14794 "TARGET_POWER && reload_completed"
14795 [(set (match_dup 4)
14796 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14797 (set (match_dup 0)
14798 (compare:CC (match_dup 4)
14799 (const_int 0)))]
14800 "")
14802 (define_insn ""
14803 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14804 (compare:CC
14805 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14806 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14807 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14808 (const_int 0)))
14809 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14810 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14811 "TARGET_POWER"
14812 "@
14813 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14814 #"
14815 [(set_attr "type" "compare")
14816 (set_attr "length" "12,16")])
14818 (define_split
14819 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14820 (compare:CC
14821 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14822 (match_operand:SI 2 "reg_or_short_operand" ""))
14823 (match_operand:SI 3 "gpc_reg_operand" ""))
14824 (const_int 0)))
14825 (set (match_operand:SI 0 "gpc_reg_operand" "")
14826 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14827 "TARGET_POWER && reload_completed"
14828 [(set (match_dup 0)
14829 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14830 (set (match_dup 4)
14831 (compare:CC (match_dup 0)
14832 (const_int 0)))]
14833 "")
14835 (define_insn ""
14836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14837 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14838 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14839 "TARGET_POWER"
14840 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14841 [(set_attr "length" "12")])
14843 (define_insn_and_split "*gtu<mode>"
14844 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14845 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14846 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14847 ""
14848 "#"
14849 ""
14850 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14851 (set (match_dup 0) (neg:P (match_dup 0)))]
14852 "")
14854 (define_insn_and_split "*gtu<mode>_compare"
14855 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14856 (compare:CC
14857 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14858 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14859 (const_int 0)))
14860 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14861 (gtu:P (match_dup 1) (match_dup 2)))]
14862 ""
14863 "#"
14864 ""
14865 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14866 (parallel [(set (match_dup 3)
14867 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14868 (set (match_dup 0) (neg:P (match_dup 0)))])]
14869 "")
14871 (define_insn_and_split "*plus_gtu<mode>"
14872 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14873 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14874 (match_operand:P 2 "reg_or_short_operand" "rI"))
14875 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14876 ""
14877 "#"
14878 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14879 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14880 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14881 "")
14883 (define_insn_and_split "*plus_gtu<mode>_compare"
14884 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14885 (compare:CC
14886 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14887 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14888 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14889 (const_int 0)))
14890 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14891 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14892 ""
14893 "#"
14894 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14895 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14896 (parallel [(set (match_dup 4)
14897 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14898 (const_int 0)))
14899 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14900 "")
14902 (define_insn "*neg_gtu<mode>"
14903 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14904 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14905 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14906 ""
14907 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14908 [(set_attr "type" "two")
14909 (set_attr "length" "8")])
14911 \f
14912 ;; Define both directions of branch and return. If we need a reload
14913 ;; register, we'd rather use CR0 since it is much easier to copy a
14914 ;; register CC value to there.
14916 (define_insn ""
14917 [(set (pc)
14918 (if_then_else (match_operator 1 "branch_comparison_operator"
14919 [(match_operand 2
14920 "cc_reg_operand" "y")
14921 (const_int 0)])
14922 (label_ref (match_operand 0 "" ""))
14923 (pc)))]
14924 ""
14925 "*
14926 {
14927 return output_cbranch (operands[1], \"%l0\", 0, insn);
14928 }"
14929 [(set_attr "type" "branch")])
14931 (define_insn ""
14932 [(set (pc)
14933 (if_then_else (match_operator 0 "branch_comparison_operator"
14934 [(match_operand 1
14935 "cc_reg_operand" "y")
14936 (const_int 0)])
14937 (return)
14938 (pc)))]
14939 "direct_return ()"
14940 "*
14941 {
14942 return output_cbranch (operands[0], NULL, 0, insn);
14943 }"
14944 [(set_attr "type" "jmpreg")
14945 (set_attr "length" "4")])
14947 (define_insn ""
14948 [(set (pc)
14949 (if_then_else (match_operator 1 "branch_comparison_operator"
14950 [(match_operand 2
14951 "cc_reg_operand" "y")
14952 (const_int 0)])
14953 (pc)
14954 (label_ref (match_operand 0 "" ""))))]
14955 ""
14956 "*
14957 {
14958 return output_cbranch (operands[1], \"%l0\", 1, insn);
14959 }"
14960 [(set_attr "type" "branch")])
14962 (define_insn ""
14963 [(set (pc)
14964 (if_then_else (match_operator 0 "branch_comparison_operator"
14965 [(match_operand 1
14966 "cc_reg_operand" "y")
14967 (const_int 0)])
14968 (pc)
14969 (return)))]
14970 "direct_return ()"
14971 "*
14972 {
14973 return output_cbranch (operands[0], NULL, 1, insn);
14974 }"
14975 [(set_attr "type" "jmpreg")
14976 (set_attr "length" "4")])
14978 ;; Logic on condition register values.
14980 ; This pattern matches things like
14981 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14982 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14983 ; (const_int 1)))
14984 ; which are generated by the branch logic.
14985 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14987 (define_insn "*cceq_ior_compare"
14988 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14989 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14990 [(match_operator:SI 2
14991 "branch_positive_comparison_operator"
14992 [(match_operand 3
14993 "cc_reg_operand" "y,y")
14994 (const_int 0)])
14995 (match_operator:SI 4
14996 "branch_positive_comparison_operator"
14997 [(match_operand 5
14998 "cc_reg_operand" "0,y")
14999 (const_int 0)])])
15000 (const_int 1)))]
15001 ""
15002 "cr%q1 %E0,%j2,%j4"
15003 [(set_attr "type" "cr_logical,delayed_cr")])
15005 ; Why is the constant -1 here, but 1 in the previous pattern?
15006 ; Because ~1 has all but the low bit set.
15007 (define_insn ""
15008 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15009 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15010 [(not:SI (match_operator:SI 2
15011 "branch_positive_comparison_operator"
15012 [(match_operand 3
15013 "cc_reg_operand" "y,y")
15014 (const_int 0)]))
15015 (match_operator:SI 4
15016 "branch_positive_comparison_operator"
15017 [(match_operand 5
15018 "cc_reg_operand" "0,y")
15019 (const_int 0)])])
15020 (const_int -1)))]
15021 ""
15022 "cr%q1 %E0,%j2,%j4"
15023 [(set_attr "type" "cr_logical,delayed_cr")])
15025 (define_insn "*cceq_rev_compare"
15026 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15027 (compare:CCEQ (match_operator:SI 1
15028 "branch_positive_comparison_operator"
15029 [(match_operand 2
15030 "cc_reg_operand" "0,y")
15031 (const_int 0)])
15032 (const_int 0)))]
15033 ""
15034 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15035 [(set_attr "type" "cr_logical,delayed_cr")])
15037 ;; If we are comparing the result of two comparisons, this can be done
15038 ;; using creqv or crxor.
15040 (define_insn_and_split ""
15041 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15042 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15043 [(match_operand 2 "cc_reg_operand" "y")
15044 (const_int 0)])
15045 (match_operator 3 "branch_comparison_operator"
15046 [(match_operand 4 "cc_reg_operand" "y")
15047 (const_int 0)])))]
15048 ""
15049 "#"
15050 ""
15051 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15052 (match_dup 5)))]
15053 "
15054 {
15055 int positive_1, positive_2;
15057 positive_1 = branch_positive_comparison_operator (operands[1],
15058 GET_MODE (operands[1]));
15059 positive_2 = branch_positive_comparison_operator (operands[3],
15060 GET_MODE (operands[3]));
15062 if (! positive_1)
15063 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15064 GET_CODE (operands[1])),
15065 SImode,
15066 operands[2], const0_rtx);
15067 else if (GET_MODE (operands[1]) != SImode)
15068 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15069 operands[2], const0_rtx);
15071 if (! positive_2)
15072 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15073 GET_CODE (operands[3])),
15074 SImode,
15075 operands[4], const0_rtx);
15076 else if (GET_MODE (operands[3]) != SImode)
15077 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15078 operands[4], const0_rtx);
15080 if (positive_1 == positive_2)
15081 {
15082 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15083 operands[5] = constm1_rtx;
15084 }
15085 else
15086 {
15087 operands[5] = const1_rtx;
15088 }
15089 }")
15091 ;; Unconditional branch and return.
15093 (define_insn "jump"
15094 [(set (pc)
15095 (label_ref (match_operand 0 "" "")))]
15096 ""
15097 "b %l0"
15098 [(set_attr "type" "branch")])
15100 (define_insn "return"
15101 [(return)]
15102 "direct_return ()"
15103 "{br|blr}"
15104 [(set_attr "type" "jmpreg")])
15106 (define_expand "indirect_jump"
15107 [(set (pc) (match_operand 0 "register_operand" ""))])
15109 (define_insn "*indirect_jump<mode>"
15110 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15111 ""
15112 "@
15113 bctr
15114 {br|blr}"
15115 [(set_attr "type" "jmpreg")])
15117 ;; Table jump for switch statements:
15118 (define_expand "tablejump"
15119 [(use (match_operand 0 "" ""))
15120 (use (label_ref (match_operand 1 "" "")))]
15121 ""
15122 "
15123 {
15124 if (TARGET_32BIT)
15125 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15126 else
15127 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15128 DONE;
15129 }")
15131 (define_expand "tablejumpsi"
15132 [(set (match_dup 3)
15133 (plus:SI (match_operand:SI 0 "" "")
15134 (match_dup 2)))
15135 (parallel [(set (pc) (match_dup 3))
15136 (use (label_ref (match_operand 1 "" "")))])]
15137 "TARGET_32BIT"
15138 "
15139 { operands[0] = force_reg (SImode, operands[0]);
15140 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15141 operands[3] = gen_reg_rtx (SImode);
15142 }")
15144 (define_expand "tablejumpdi"
15145 [(set (match_dup 4)
15146 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15147 (set (match_dup 3)
15148 (plus:DI (match_dup 4)
15149 (match_dup 2)))
15150 (parallel [(set (pc) (match_dup 3))
15151 (use (label_ref (match_operand 1 "" "")))])]
15152 "TARGET_64BIT"
15153 "
15154 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15155 operands[3] = gen_reg_rtx (DImode);
15156 operands[4] = gen_reg_rtx (DImode);
15157 }")
15159 (define_insn "*tablejump<mode>_internal1"
15160 [(set (pc)
15161 (match_operand:P 0 "register_operand" "c,*l"))
15162 (use (label_ref (match_operand 1 "" "")))]
15163 ""
15164 "@
15165 bctr
15166 {br|blr}"
15167 [(set_attr "type" "jmpreg")])
15169 (define_insn "nop"
15170 [(const_int 0)]
15171 ""
15172 "{cror 0,0,0|nop}")
15173 \f
15174 ;; Define the subtract-one-and-jump insns, starting with the template
15175 ;; so loop.c knows what to generate.
15177 (define_expand "doloop_end"
15178 [(use (match_operand 0 "" "")) ; loop pseudo
15179 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15180 (use (match_operand 2 "" "")) ; max iterations
15181 (use (match_operand 3 "" "")) ; loop level
15182 (use (match_operand 4 "" ""))] ; label
15183 ""
15184 "
15185 {
15186 /* Only use this on innermost loops. */
15187 if (INTVAL (operands[3]) > 1)
15188 FAIL;
15189 if (TARGET_64BIT)
15190 {
15191 if (GET_MODE (operands[0]) != DImode)
15192 FAIL;
15193 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15194 }
15195 else
15196 {
15197 if (GET_MODE (operands[0]) != SImode)
15198 FAIL;
15199 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15200 }
15201 DONE;
15202 }")
15204 (define_expand "ctr<mode>"
15205 [(parallel [(set (pc)
15206 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15207 (const_int 1))
15208 (label_ref (match_operand 1 "" ""))
15209 (pc)))
15210 (set (match_dup 0)
15211 (plus:P (match_dup 0)
15212 (const_int -1)))
15213 (clobber (match_scratch:CC 2 ""))
15214 (clobber (match_scratch:P 3 ""))])]
15215 ""
15216 "")
15218 ;; We need to be able to do this for any operand, including MEM, or we
15219 ;; will cause reload to blow up since we don't allow output reloads on
15220 ;; JUMP_INSNs.
15221 ;; For the length attribute to be calculated correctly, the
15222 ;; label MUST be operand 0.
15224 (define_insn "*ctr<mode>_internal1"
15225 [(set (pc)
15226 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15227 (const_int 1))
15228 (label_ref (match_operand 0 "" ""))
15229 (pc)))
15230 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15231 (plus:P (match_dup 1)
15232 (const_int -1)))
15233 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15234 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15235 ""
15236 "*
15237 {
15238 if (which_alternative != 0)
15239 return \"#\";
15240 else if (get_attr_length (insn) == 4)
15241 return \"{bdn|bdnz} %l0\";
15242 else
15243 return \"bdz $+8\;b %l0\";
15244 }"
15245 [(set_attr "type" "branch")
15246 (set_attr "length" "*,12,16,16")])
15248 (define_insn "*ctr<mode>_internal2"
15249 [(set (pc)
15250 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15251 (const_int 1))
15252 (pc)
15253 (label_ref (match_operand 0 "" ""))))
15254 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15255 (plus:P (match_dup 1)
15256 (const_int -1)))
15257 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15258 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15259 ""
15260 "*
15261 {
15262 if (which_alternative != 0)
15263 return \"#\";
15264 else if (get_attr_length (insn) == 4)
15265 return \"bdz %l0\";
15266 else
15267 return \"{bdn|bdnz} $+8\;b %l0\";
15268 }"
15269 [(set_attr "type" "branch")
15270 (set_attr "length" "*,12,16,16")])
15272 ;; Similar but use EQ
15274 (define_insn "*ctr<mode>_internal5"
15275 [(set (pc)
15276 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15277 (const_int 1))
15278 (label_ref (match_operand 0 "" ""))
15279 (pc)))
15280 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15281 (plus:P (match_dup 1)
15282 (const_int -1)))
15283 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15284 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15285 ""
15286 "*
15287 {
15288 if (which_alternative != 0)
15289 return \"#\";
15290 else if (get_attr_length (insn) == 4)
15291 return \"bdz %l0\";
15292 else
15293 return \"{bdn|bdnz} $+8\;b %l0\";
15294 }"
15295 [(set_attr "type" "branch")
15296 (set_attr "length" "*,12,16,16")])
15298 (define_insn "*ctr<mode>_internal6"
15299 [(set (pc)
15300 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15301 (const_int 1))
15302 (pc)
15303 (label_ref (match_operand 0 "" ""))))
15304 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15305 (plus:P (match_dup 1)
15306 (const_int -1)))
15307 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15308 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15309 ""
15310 "*
15311 {
15312 if (which_alternative != 0)
15313 return \"#\";
15314 else if (get_attr_length (insn) == 4)
15315 return \"{bdn|bdnz} %l0\";
15316 else
15317 return \"bdz $+8\;b %l0\";
15318 }"
15319 [(set_attr "type" "branch")
15320 (set_attr "length" "*,12,16,16")])
15322 ;; Now the splitters if we could not allocate the CTR register
15324 (define_split
15325 [(set (pc)
15326 (if_then_else (match_operator 2 "comparison_operator"
15327 [(match_operand:P 1 "gpc_reg_operand" "")
15328 (const_int 1)])
15329 (match_operand 5 "" "")
15330 (match_operand 6 "" "")))
15331 (set (match_operand:P 0 "gpc_reg_operand" "")
15332 (plus:P (match_dup 1) (const_int -1)))
15333 (clobber (match_scratch:CC 3 ""))
15334 (clobber (match_scratch:P 4 ""))]
15335 "reload_completed"
15336 [(parallel [(set (match_dup 3)
15337 (compare:CC (plus:P (match_dup 1)
15338 (const_int -1))
15339 (const_int 0)))
15340 (set (match_dup 0)
15341 (plus:P (match_dup 1)
15342 (const_int -1)))])
15343 (set (pc) (if_then_else (match_dup 7)
15344 (match_dup 5)
15345 (match_dup 6)))]
15346 "
15347 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15348 operands[3], const0_rtx); }")
15350 (define_split
15351 [(set (pc)
15352 (if_then_else (match_operator 2 "comparison_operator"
15353 [(match_operand:P 1 "gpc_reg_operand" "")
15354 (const_int 1)])
15355 (match_operand 5 "" "")
15356 (match_operand 6 "" "")))
15357 (set (match_operand:P 0 "nonimmediate_operand" "")
15358 (plus:P (match_dup 1) (const_int -1)))
15359 (clobber (match_scratch:CC 3 ""))
15360 (clobber (match_scratch:P 4 ""))]
15361 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15362 [(parallel [(set (match_dup 3)
15363 (compare:CC (plus:P (match_dup 1)
15364 (const_int -1))
15365 (const_int 0)))
15366 (set (match_dup 4)
15367 (plus:P (match_dup 1)
15368 (const_int -1)))])
15369 (set (match_dup 0)
15370 (match_dup 4))
15371 (set (pc) (if_then_else (match_dup 7)
15372 (match_dup 5)
15373 (match_dup 6)))]
15374 "
15375 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15376 operands[3], const0_rtx); }")
15377 \f
15378 (define_insn "trap"
15379 [(trap_if (const_int 1) (const_int 0))]
15380 ""
15381 "{t 31,0,0|trap}"
15382 [(set_attr "type" "trap")])
15384 (define_expand "ctrap<mode>4"
15385 [(trap_if (match_operator 0 "ordered_comparison_operator"
15386 [(match_operand:GPR 1 "register_operand")
15387 (match_operand:GPR 2 "reg_or_short_operand")])
15388 (match_operand 3 "zero_constant" ""))]
15389 ""
15390 "")
15392 (define_insn ""
15393 [(trap_if (match_operator 0 "ordered_comparison_operator"
15394 [(match_operand:GPR 1 "register_operand" "r")
15395 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15396 (const_int 0))]
15397 ""
15398 "{t|t<wd>}%V0%I2 %1,%2"
15399 [(set_attr "type" "trap")])
15400 \f
15401 ;; Insns related to generating the function prologue and epilogue.
15403 (define_expand "prologue"
15404 [(use (const_int 0))]
15405 "TARGET_SCHED_PROLOG"
15406 "
15407 {
15408 rs6000_emit_prologue ();
15409 DONE;
15410 }")
15412 (define_insn "*movesi_from_cr_one"
15413 [(match_parallel 0 "mfcr_operation"
15414 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15415 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15416 (match_operand 3 "immediate_operand" "n")]
15417 UNSPEC_MOVESI_FROM_CR))])]
15418 "TARGET_MFCRF"
15419 "*
15420 {
15421 int mask = 0;
15422 int i;
15423 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15424 {
15425 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15426 operands[4] = GEN_INT (mask);
15427 output_asm_insn (\"mfcr %1,%4\", operands);
15428 }
15429 return \"\";
15430 }"
15431 [(set_attr "type" "mfcrf")])
15433 (define_insn "movesi_from_cr"
15434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15435 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15436 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15437 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15438 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15439 UNSPEC_MOVESI_FROM_CR))]
15440 ""
15441 "mfcr %0"
15442 [(set_attr "type" "mfcr")])
15444 (define_insn "*stmw"
15445 [(match_parallel 0 "stmw_operation"
15446 [(set (match_operand:SI 1 "memory_operand" "=m")
15447 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15448 "TARGET_MULTIPLE"
15449 "{stm|stmw} %2,%1"
15450 [(set_attr "type" "store_ux")])
15452 (define_insn "*save_gpregs_<mode>"
15453 [(match_parallel 0 "any_parallel_operand"
15454 [(clobber (reg:P 65))
15455 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15456 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15457 (set (match_operand:P 3 "memory_operand" "=m")
15458 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15459 ""
15460 "bl %1"
15461 [(set_attr "type" "branch")
15462 (set_attr "length" "4")])
15464 (define_insn "*save_fpregs_<mode>"
15465 [(match_parallel 0 "any_parallel_operand"
15466 [(clobber (reg:P 65))
15467 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15468 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15469 (set (match_operand:DF 3 "memory_operand" "=m")
15470 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15471 ""
15472 "bl %1"
15473 [(set_attr "type" "branch")
15474 (set_attr "length" "4")])
15476 ; These are to explain that changes to the stack pointer should
15477 ; not be moved over stores to stack memory.
15478 (define_insn "stack_tie"
15479 [(set (match_operand:BLK 0 "memory_operand" "+m")
15480 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15481 ""
15482 ""
15483 [(set_attr "length" "0")])
15485 ; Like stack_tie, but depend on both fp and sp based memory.
15486 (define_insn "frame_tie"
15487 [(set (match_operand:BLK 0 "memory_operand" "+m")
15488 (unspec:BLK [(match_dup 0)
15489 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15490 ""
15491 ""
15492 [(set_attr "length" "0")])
15495 (define_expand "epilogue"
15496 [(use (const_int 0))]
15497 "TARGET_SCHED_PROLOG"
15498 "
15499 {
15500 rs6000_emit_epilogue (FALSE);
15501 DONE;
15502 }")
15504 ; On some processors, doing the mtcrf one CC register at a time is
15505 ; faster (like on the 604e). On others, doing them all at once is
15506 ; faster; for instance, on the 601 and 750.
15508 (define_expand "movsi_to_cr_one"
15509 [(set (match_operand:CC 0 "cc_reg_operand" "")
15510 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15511 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15512 ""
15513 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15515 (define_insn "*movsi_to_cr"
15516 [(match_parallel 0 "mtcrf_operation"
15517 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15518 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15519 (match_operand 3 "immediate_operand" "n")]
15520 UNSPEC_MOVESI_TO_CR))])]
15521 ""
15522 "*
15523 {
15524 int mask = 0;
15525 int i;
15526 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15527 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15528 operands[4] = GEN_INT (mask);
15529 return \"mtcrf %4,%2\";
15530 }"
15531 [(set_attr "type" "mtcr")])
15533 (define_insn "*mtcrfsi"
15534 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15535 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15536 (match_operand 2 "immediate_operand" "n")]
15537 UNSPEC_MOVESI_TO_CR))]
15538 "GET_CODE (operands[0]) == REG
15539 && CR_REGNO_P (REGNO (operands[0]))
15540 && GET_CODE (operands[2]) == CONST_INT
15541 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15542 "mtcrf %R0,%1"
15543 [(set_attr "type" "mtcr")])
15545 ; The load-multiple instructions have similar properties.
15546 ; Note that "load_multiple" is a name known to the machine-independent
15547 ; code that actually corresponds to the PowerPC load-string.
15549 (define_insn "*lmw"
15550 [(match_parallel 0 "lmw_operation"
15551 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15552 (match_operand:SI 2 "memory_operand" "m"))])]
15553 "TARGET_MULTIPLE"
15554 "{lm|lmw} %1,%2"
15555 [(set_attr "type" "load_ux")
15556 (set_attr "cell_micro" "always")])
15558 (define_insn "*return_internal_<mode>"
15559 [(return)
15560 (use (match_operand:P 0 "register_operand" "lc"))]
15561 ""
15562 "b%T0"
15563 [(set_attr "type" "jmpreg")])
15565 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15566 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15568 (define_insn "*restore_gpregs_<mode>"
15569 [(match_parallel 0 "any_parallel_operand"
15570 [(clobber (match_operand:P 1 "register_operand" "=l"))
15571 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15572 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15573 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15574 (match_operand:P 5 "memory_operand" "m"))])]
15575 ""
15576 "bl %2"
15577 [(set_attr "type" "branch")
15578 (set_attr "length" "4")])
15580 (define_insn "*return_and_restore_gpregs_<mode>"
15581 [(match_parallel 0 "any_parallel_operand"
15582 [(return)
15583 (clobber (match_operand:P 1 "register_operand" "=l"))
15584 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15585 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15586 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15587 (match_operand:P 5 "memory_operand" "m"))])]
15588 ""
15589 "b %2"
15590 [(set_attr "type" "branch")
15591 (set_attr "length" "4")])
15593 (define_insn "*return_and_restore_fpregs_<mode>"
15594 [(match_parallel 0 "any_parallel_operand"
15595 [(return)
15596 (clobber (match_operand:P 1 "register_operand" "=l"))
15597 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15598 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15599 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15600 (match_operand:DF 5 "memory_operand" "m"))])]
15601 ""
15602 "b %2"
15603 [(set_attr "type" "branch")
15604 (set_attr "length" "4")])
15606 (define_insn "*return_and_restore_fpregs_aix_<mode>"
15607 [(match_parallel 0 "any_parallel_operand"
15608 [(return)
15609 (use (match_operand:P 1 "register_operand" "l"))
15610 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15611 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15612 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15613 (match_operand:DF 5 "memory_operand" "m"))])]
15614 ""
15615 "b %2"
15616 [(set_attr "type" "branch")
15617 (set_attr "length" "4")])
15619 ; This is used in compiling the unwind routines.
15620 (define_expand "eh_return"
15621 [(use (match_operand 0 "general_operand" ""))]
15622 ""
15623 "
15624 {
15625 if (TARGET_32BIT)
15626 emit_insn (gen_eh_set_lr_si (operands[0]));
15627 else
15628 emit_insn (gen_eh_set_lr_di (operands[0]));
15629 DONE;
15630 }")
15632 ; We can't expand this before we know where the link register is stored.
15633 (define_insn "eh_set_lr_<mode>"
15634 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15635 UNSPECV_EH_RR)
15636 (clobber (match_scratch:P 1 "=&b"))]
15637 ""
15638 "#")
15640 (define_split
15641 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15642 (clobber (match_scratch 1 ""))]
15643 "reload_completed"
15644 [(const_int 0)]
15645 "
15646 {
15647 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15648 DONE;
15649 }")
15651 (define_insn "prefetch"
15652 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15653 (match_operand:SI 1 "const_int_operand" "n")
15654 (match_operand:SI 2 "const_int_operand" "n"))]
15655 "TARGET_POWERPC"
15656 "*
15657 {
15658 if (GET_CODE (operands[0]) == REG)
15659 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15660 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15661 }"
15662 [(set_attr "type" "load")])
15663 \f
15664 (define_insn "bpermd_<mode>"
15665 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15666 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15667 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15668 "TARGET_POPCNTD"
15669 "bpermd %0,%1,%2"
15670 [(set_attr "type" "integer")])
15672 \f
15674 (include "sync.md")
15675 (include "vector.md")
15676 (include "vsx.md")
15677 (include "altivec.md")
15678 (include "spe.md")
15679 (include "dfp.md")
15680 (include "paired.md")