gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2016 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 415   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 416   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0;
 417
 418   bool arch;
 419
 420   unsigned int l2sizekb = 0;
 421
 422   if (argc < 1)
 423     return NULL;
 424
 425   arch = !strcmp (argv[0], "arch");
 426
 427   if (!arch && strcmp (argv[0], "tune"))
 428     return NULL;
 429
 430   max_level = __get_cpuid_max (0, &vendor);
 431   if (max_level < 1)
 432     goto done;
 433
 434   __cpuid (1, eax, ebx, ecx, edx);
 435
 436   model = (eax >> 4) & 0x0f;
 437   family = (eax >> 8) & 0x0f;
 438   if (vendor == signature_INTEL_ebx
 439       || vendor == signature_AMD_ebx)
 440     {
 441       unsigned int extended_model, extended_family;
 442
 443       extended_model = (eax >> 12) & 0xf0;
 444       extended_family = (eax >> 20) & 0xff;
 445       if (family == 0x0f)
 446         {
 447           family += extended_family;
 448           model += extended_model;
 449         }
 450       else if (family == 0x06)
 451         model += extended_model;
 452     }
 453
 454   has_sse3 = ecx & bit_SSE3;
 455   has_ssse3 = ecx & bit_SSSE3;
 456   has_sse4_1 = ecx & bit_SSE4_1;
 457   has_sse4_2 = ecx & bit_SSE4_2;
 458   has_avx = ecx & bit_AVX;
 459   has_osxsave = ecx & bit_OSXSAVE;
 460   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 461   has_movbe = ecx & bit_MOVBE;
 462   has_popcnt = ecx & bit_POPCNT;
 463   has_aes = ecx & bit_AES;
 464   has_pclmul = ecx & bit_PCLMUL;
 465   has_fma = ecx & bit_FMA;
 466   has_f16c = ecx & bit_F16C;
 467   has_rdrnd = ecx & bit_RDRND;
 468   has_xsave = ecx & bit_XSAVE;
 469
 470   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 471   has_cmov = edx & bit_CMOV;
 472   has_mmx = edx & bit_MMX;
 473   has_fxsr = edx & bit_FXSAVE;
 474   has_sse = edx & bit_SSE;
 475   has_sse2 = edx & bit_SSE2;
 476
 477   if (max_level >= 7)
 478     {
 479       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 480
 481       has_bmi = ebx & bit_BMI;
 482       has_hle = ebx & bit_HLE;
 483       has_rtm = ebx & bit_RTM;
 484       has_avx2 = ebx & bit_AVX2;
 485       has_bmi2 = ebx & bit_BMI2;
 486       has_fsgsbase = ebx & bit_FSGSBASE;
 487       has_rdseed = ebx & bit_RDSEED;
 488       has_adx = ebx & bit_ADX;
 489       has_avx512f = ebx & bit_AVX512F;
 490       has_avx512er = ebx & bit_AVX512ER;
 491       has_avx512pf = ebx & bit_AVX512PF;
 492       has_avx512cd = ebx & bit_AVX512CD;
 493       has_sha = ebx & bit_SHA;
 494       has_clflushopt = ebx & bit_CLFLUSHOPT;
 495       has_clwb = ebx & bit_CLWB;
 496       has_avx512dq = ebx & bit_AVX512DQ;
 497       has_avx512bw = ebx & bit_AVX512BW;
 498       has_avx512vl = ebx & bit_AVX512VL;
 499       has_avx512ifma = ebx & bit_AVX512IFMA;
 500
 501       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 502       has_avx512vbmi = ecx & bit_AVX512VBMI;
 503       has_pku = ecx & bit_OSPKE;
 504     }
 505
 506   if (max_level >= 13)
 507     {
 508       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 509
 510       has_xsaveopt = eax & bit_XSAVEOPT;
 511       has_xsavec = eax & bit_XSAVEC;
 512       has_xsaves = eax & bit_XSAVES;
 513     }
 514
 515   /* Check cpuid level of extended features.  */
 516   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 517
 518   if (ext_level >= 0x80000001)
 519     {
 520       __cpuid (0x80000001, eax, ebx, ecx, edx);
 521
 522       has_lahf_lm = ecx & bit_LAHF_LM;
 523       has_sse4a = ecx & bit_SSE4a;
 524       has_abm = ecx & bit_ABM;
 525       has_lwp = ecx & bit_LWP;
 526       has_fma4 = ecx & bit_FMA4;
 527       has_xop = ecx & bit_XOP;
 528       has_tbm = ecx & bit_TBM;
 529       has_lzcnt = ecx & bit_LZCNT;
 530       has_prfchw = ecx & bit_PRFCHW;
 531
 532       has_longmode = edx & bit_LM;
 533       has_3dnowp = edx & bit_3DNOWP;
 534       has_3dnow = edx & bit_3DNOW;
 535       has_mwaitx = ecx & bit_MWAITX;
 536     }
 537
 538   if (ext_level >= 0x80000008)
 539     {
 540       __cpuid (0x80000008, eax, ebx, ecx, edx);
 541       has_clzero = ebx & bit_CLZERO;
 542     }
 543
 544   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 545 #define XCR_XFEATURE_ENABLED_MASK       0x0
 546 #define XSTATE_FP                       0x1
 547 #define XSTATE_SSE                      0x2
 548 #define XSTATE_YMM                      0x4
 549 #define XSTATE_OPMASK                   0x20
 550 #define XSTATE_ZMM                      0x40
 551 #define XSTATE_HI_ZMM                   0x80
 552
 553 #define XCR_AVX_ENABLED_MASK \
 554   (XSTATE_SSE | XSTATE_YMM)
 555 #define XCR_AVX512F_ENABLED_MASK \
 556   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
 557
 558   if (has_osxsave)
 559     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 560          : "=a" (eax), "=d" (edx)
 561          : "c" (XCR_XFEATURE_ENABLED_MASK));
 562   else
 563     eax = 0;
 564
 565   /* Check if AVX registers are supported.  */
 566   if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
 567     {
 568       has_avx = 0;
 569       has_avx2 = 0;
 570       has_fma = 0;
 571       has_fma4 = 0;
 572       has_f16c = 0;
 573       has_xop = 0;
 574       has_xsave = 0;
 575       has_xsaveopt = 0;
 576       has_xsaves = 0;
 577       has_xsavec = 0;
 578     }
 579
 580   /* Check if AVX512F registers are supported.  */
 581   if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
 582     {
 583       has_avx512f = 0;
 584       has_avx512er = 0;
 585       has_avx512pf = 0;
 586       has_avx512cd = 0;
 587       has_avx512dq = 0;
 588       has_avx512bw = 0;
 589       has_avx512vl = 0;
 590     }
 591
 592   if (!arch)
 593     {
 594       if (vendor == signature_AMD_ebx
 595           || vendor == signature_CENTAUR_ebx
 596           || vendor == signature_CYRIX_ebx
 597           || vendor == signature_NSC_ebx)
 598         cache = detect_caches_amd (ext_level);
 599       else if (vendor == signature_INTEL_ebx)
 600         {
 601           bool xeon_mp = (family == 15 && model == 6);
 602           cache = detect_caches_intel (xeon_mp, max_level,
 603                                        ext_level, &l2sizekb);
 604         }
 605     }
 606
 607   if (vendor == signature_AMD_ebx)
 608     {
 609       unsigned int name;
 610
 611       /* Detect geode processor by its processor signature.  */
 612       if (ext_level >= 0x80000002)
 613         __cpuid (0x80000002, name, ebx, ecx, edx);
 614       else
 615         name = 0;
 616
 617       if (name == signature_NSC_ebx)
 618         processor = PROCESSOR_GEODE;
 619       else if (has_movbe && family == 22)
 620         processor = PROCESSOR_BTVER2;
 621       else if (has_clzero)
 622         processor = PROCESSOR_ZNVER1;
 623       else if (has_avx2)
 624         processor = PROCESSOR_BDVER4;
 625       else if (has_xsaveopt)
 626         processor = PROCESSOR_BDVER3;
 627       else if (has_bmi)
 628         processor = PROCESSOR_BDVER2;
 629       else if (has_xop)
 630         processor = PROCESSOR_BDVER1;
 631       else if (has_sse4a && has_ssse3)
 632         processor = PROCESSOR_BTVER1;
 633       else if (has_sse4a)
 634         processor = PROCESSOR_AMDFAM10;
 635       else if (has_sse2 || has_longmode)
 636         processor = PROCESSOR_K8;
 637       else if (has_3dnowp && family == 6)
 638         processor = PROCESSOR_ATHLON;
 639       else if (has_mmx)
 640         processor = PROCESSOR_K6;
 641       else
 642         processor = PROCESSOR_PENTIUM;
 643     }
 644   else if (vendor == signature_CENTAUR_ebx)
 645     {
 646       processor = PROCESSOR_GENERIC;
 647
 648       switch (family)
 649         {
 650         default:
 651           /* We have no idea.  */
 652           break;
 653
 654         case 5:
 655           if (has_3dnow || has_mmx)
 656             processor = PROCESSOR_I486;
 657           break;
 658
 659         case 6:
 660           if (has_longmode)
 661             processor = PROCESSOR_K8;
 662           else if (model >= 9)
 663             processor = PROCESSOR_PENTIUMPRO;
 664           else if (model >= 6)
 665             processor = PROCESSOR_I486;
 666         }
 667     }
 668   else
 669     {
 670       switch (family)
 671         {
 672         case 4:
 673           processor = PROCESSOR_I486;
 674           break;
 675         case 5:
 676           processor = PROCESSOR_PENTIUM;
 677           break;
 678         case 6:
 679           processor = PROCESSOR_PENTIUMPRO;
 680           break;
 681         case 15:
 682           processor = PROCESSOR_PENTIUM4;
 683           break;
 684         default:
 685           /* We have no idea.  */
 686           processor = PROCESSOR_GENERIC;
 687         }
 688     }
 689
 690   switch (processor)
 691     {
 692     case PROCESSOR_I386:
 693       /* Default.  */
 694       break;
 695     case PROCESSOR_I486:
 696       if (arch && vendor == signature_CENTAUR_ebx)
 697         {
 698           if (model >= 6)
 699             cpu = "c3";
 700           else if (has_3dnow)
 701             cpu = "winchip2";
 702           else
 703             /* Assume WinChip C6.  */
 704             cpu = "winchip-c6";
 705         }
 706       else
 707         cpu = "i486";
 708       break;
 709     case PROCESSOR_PENTIUM:
 710       if (arch && has_mmx)
 711         cpu = "pentium-mmx";
 712       else
 713         cpu = "pentium";
 714       break;
 715     case PROCESSOR_PENTIUMPRO:
 716       switch (model)
 717         {
 718         case 0x1c:
 719         case 0x26:
 720           /* Bonnell.  */
 721           cpu = "bonnell";
 722           break;
 723         case 0x37:
 724         case 0x4a:
 725         case 0x4d:
 726         case 0x5a:
 727         case 0x5d:
 728           /* Silvermont.  */
 729           cpu = "silvermont";
 730           break;
 731         case 0x0f:
 732           /* Merom.  */
 733         case 0x17:
 734         case 0x1d:
 735           /* Penryn.  */
 736           cpu = "core2";
 737           break;
 738         case 0x1a:
 739         case 0x1e:
 740         case 0x1f:
 741         case 0x2e:
 742           /* Nehalem.  */
 743           cpu = "nehalem";
 744           break;
 745         case 0x25:
 746         case 0x2c:
 747         case 0x2f:
 748           /* Westmere.  */
 749           cpu = "westmere";
 750           break;
 751         case 0x2a:
 752         case 0x2d:
 753           /* Sandy Bridge.  */
 754           cpu = "sandybridge";
 755           break;
 756         case 0x3a:
 757         case 0x3e:
 758           /* Ivy Bridge.  */
 759           cpu = "ivybridge";
 760           break;
 761         case 0x3c:
 762         case 0x3f:
 763         case 0x45:
 764         case 0x46:
 765           /* Haswell.  */
 766           cpu = "haswell";
 767           break;
 768         case 0x3d:
 769         case 0x47:
 770         case 0x4f:
 771         case 0x56:
 772           /* Broadwell.  */
 773           cpu = "broadwell";
 774           break;
 775         case 0x4e:
 776         case 0x5e:
 777           /* Skylake.  */
 778           cpu = "skylake";
 779           break;
 780         case 0x57:
 781           /* Knights Landing.  */
 782           cpu = "knl";
 783           break;
 784         default:
 785           if (arch)
 786             {
 787               /* This is unknown family 0x6 CPU.  */
 788               /* Assume Knights Landing.  */
 789               if (has_avx512f)
 790                 cpu = "knl";
 791               /* Assume Broadwell.  */
 792               else if (has_adx)
 793                 cpu = "broadwell";
 794               else if (has_avx2)
 795                 /* Assume Haswell.  */
 796                 cpu = "haswell";
 797               else if (has_avx)
 798                 /* Assume Sandy Bridge.  */
 799                 cpu = "sandybridge";
 800               else if (has_sse4_2)
 801                 {
 802                   if (has_movbe)
 803                     /* Assume Silvermont.  */
 804                     cpu = "silvermont";
 805                   else
 806                     /* Assume Nehalem.  */
 807                     cpu = "nehalem";
 808                 }
 809               else if (has_ssse3)
 810                 {
 811                   if (has_movbe)
 812                     /* Assume Bonnell.  */
 813                     cpu = "bonnell";
 814                   else
 815                     /* Assume Core 2.  */
 816                     cpu = "core2";
 817                 }
 818               else if (has_longmode)
 819                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 820                    -march=native would be unusable for 64-bit compilations,
 821                    as all the CPUs below are 32-bit only.  */
 822                 cpu = "x86-64";
 823               else if (has_sse3)
 824                 {
 825                   if (vendor == signature_CENTAUR_ebx)
 826                     /* C7 / Eden "Esther" */
 827                     cpu = "c7";
 828                   else
 829                     /* It is Core Duo.  */
 830                     cpu = "pentium-m";
 831                 }
 832               else if (has_sse2)
 833                 /* It is Pentium M.  */
 834                 cpu = "pentium-m";
 835               else if (has_sse)
 836                 {
 837                   if (vendor == signature_CENTAUR_ebx)
 838                     {
 839                       if (model >= 9)
 840                         /* Eden "Nehemiah" */
 841                         cpu = "nehemiah";
 842                       else
 843                         cpu = "c3-2";
 844                     }
 845                   else
 846                     /* It is Pentium III.  */
 847                     cpu = "pentium3";
 848                 }
 849               else if (has_mmx)
 850                 /* It is Pentium II.  */
 851                 cpu = "pentium2";
 852               else
 853                 /* Default to Pentium Pro.  */
 854                 cpu = "pentiumpro";
 855             }
 856           else
 857             /* For -mtune, we default to -mtune=generic.  */
 858             cpu = "generic";
 859           break;
 860         }
 861       break;
 862     case PROCESSOR_PENTIUM4:
 863       if (has_sse3)
 864         {
 865           if (has_longmode)
 866             cpu = "nocona";
 867           else
 868             cpu = "prescott";
 869         }
 870       else
 871         cpu = "pentium4";
 872       break;
 873     case PROCESSOR_GEODE:
 874       cpu = "geode";
 875       break;
 876     case PROCESSOR_K6:
 877       if (arch && has_3dnow)
 878         cpu = "k6-3";
 879       else
 880         cpu = "k6";
 881       break;
 882     case PROCESSOR_ATHLON:
 883       if (arch && has_sse)
 884         cpu = "athlon-4";
 885       else
 886         cpu = "athlon";
 887       break;
 888     case PROCESSOR_K8:
 889       if (arch)
 890         {
 891           if (vendor == signature_CENTAUR_ebx)
 892             {
 893               if (has_sse4_1)
 894                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 895                 cpu = "nano-3000";
 896               else if (has_ssse3)
 897                 /* Nano 1000 | Nano 2000 */
 898                 cpu = "nano";
 899               else if (has_sse3)
 900                 /* Eden X2 */
 901                 cpu = "eden-x2";
 902               else
 903                 /* Default to k8 */
 904                 cpu = "k8";
 905             }
 906           else if (has_sse3)
 907             cpu = "k8-sse3";
 908           else
 909             cpu = "k8";
 910         }
 911       else
 912         /* For -mtune, we default to -mtune=k8 */
 913         cpu = "k8";
 914       break;
 915     case PROCESSOR_AMDFAM10:
 916       cpu = "amdfam10";
 917       break;
 918     case PROCESSOR_BDVER1:
 919       cpu = "bdver1";
 920       break;
 921     case PROCESSOR_BDVER2:
 922       cpu = "bdver2";
 923       break;
 924     case PROCESSOR_BDVER3:
 925       cpu = "bdver3";
 926       break;
 927     case PROCESSOR_BDVER4:
 928       cpu = "bdver4";
 929       break;
 930     case PROCESSOR_ZNVER1:
 931       cpu = "znver1";
 932       break;
 933     case PROCESSOR_BTVER1:
 934       cpu = "btver1";
 935       break;
 936     case PROCESSOR_BTVER2:
 937       cpu = "btver2";
 938       break;
 939
 940     default:
 941       /* Use something reasonable.  */
 942       if (arch)
 943         {
 944           if (has_ssse3)
 945             cpu = "core2";
 946           else if (has_sse3)
 947             {
 948               if (has_longmode)
 949                 cpu = "nocona";
 950               else
 951                 cpu = "prescott";
 952             }
 953           else if (has_longmode)
 954             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 955                -march=native would be unusable for 64-bit compilations,
 956                as all the CPUs below are 32-bit only.  */
 957             cpu = "x86-64";
 958           else if (has_sse2)
 959             cpu = "pentium4";
 960           else if (has_cmov)
 961             cpu = "pentiumpro";
 962           else if (has_mmx)
 963             cpu = "pentium-mmx";
 964           else if (has_cmpxchg8b)
 965             cpu = "pentium";
 966         }
 967       else
 968         cpu = "generic";
 969     }
 970
 971   if (arch)
 972     {
 973       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 974       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 975       const char *sse = has_sse ? " -msse" : " -mno-sse";
 976       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 977       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 978       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 979       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 980       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 981       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 982       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 983       const char *aes = has_aes ? " -maes" : " -mno-aes";
 984       const char *sha = has_sha ? " -msha" : " -mno-sha";
 985       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 986       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 987       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 988       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 989       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 990       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 991       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 992       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 993       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 994       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 995       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 996       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 997       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 998       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 999       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
1000       const char *hle = has_hle ? " -mhle" : " -mno-hle";
1001       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
1002       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
1003       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
1004       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
1005       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1006       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1007       const char *adx = has_adx ? " -madx" : " -mno-adx";
1008       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1009       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1010       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1011       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1012       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1013       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1014       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1015       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1016       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1017       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1018       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1019       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1020       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1021       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1022       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1023       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1024       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1025       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1026       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1027       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1028       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1029                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1030                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
1031                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1032                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1033                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1034                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1035                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1036                         avx512ifma, avx512vbmi, clwb, mwaitx,
1037                         clzero, pku, NULL);
1038     }
1039
1040 done:
1041   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1042 }
1043 #else
1044
1045 /* If we are compiling with GCC where %EBX register is fixed, then the
1046    driver will just ignore -march and -mtune "native" target and will leave
1047    to the newly built compiler to generate code for its default target.  */
1048
1049 const char *host_detect_local_cpu (int, const char **)
1050 {
1051   return NULL;
1052 }
1053 #endif /* __GNUC__ */