1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
101 #include "tree-pass.h"
103 #include "valtrack.h"
107 /* Number of attempts to combine instructions in this function. */
109 static int combine_attempts
;
111 /* Number of attempts that got as far as substitution in this function. */
113 static int combine_merges
;
115 /* Number of instructions combined with added SETs in this function. */
117 static int combine_extras
;
119 /* Number of instructions combined in this function. */
121 static int combine_successes
;
123 /* Totals over entire compilation. */
125 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
138 static rtx i2mod_old_rhs
;
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
142 static rtx i2mod_new_rhs
;
144 typedef struct reg_stat_struct
{
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick
;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
214 char last_set_sign_bit_copies
;
215 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid
;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies
;
237 unsigned HOST_WIDE_INT nonzero_bits
;
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
243 int truncation_label
;
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
250 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
254 static vec
<reg_stat_type
> reg_stat
;
256 /* Record the luid of the last insn that invalidated memory
257 (anything that writes memory, and subroutine calls, but not pushes). */
259 static int mem_last_set
;
261 /* Record the luid of the last CALL_INSN
262 so we can tell whether a potential combination crosses any calls. */
264 static int last_call_luid
;
266 /* When `subst' is called, this is the insn that is being modified
267 (by combining in a previous insn). The PATTERN of this insn
268 is still the old pattern partially modified and it should not be
269 looked at, but this may be used to examine the successors of the insn
270 to judge whether a simplification is valid. */
272 static rtx subst_insn
;
274 /* This is the lowest LUID that `subst' is currently dealing with.
275 get_last_value will not return a value if the register was set at or
276 after this LUID. If not for this mechanism, we could get confused if
277 I2 or I1 in try_combine were an insn that used the old value of a register
278 to obtain a new value. In that case, we might erroneously get the
279 new value of the register when we wanted the old one. */
281 static int subst_low_luid
;
283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
284 must consider all these registers to be always live. */
286 static HARD_REG_SET newpat_used_regs
;
288 /* This is an insn to which a LOG_LINKS entry has been added. If this
289 insn is the earlier than I2 or I3, combine should rescan starting at
292 static rtx added_links_insn
;
294 /* Basic block in which we are performing combines. */
295 static basic_block this_basic_block
;
296 static bool optimize_this_for_speed_p
;
299 /* Length of the currently allocated uid_insn_cost array. */
301 static int max_uid_known
;
303 /* The following array records the insn_rtx_cost for every insn
304 in the instruction stream. */
306 static int *uid_insn_cost
;
308 /* The following array records the LOG_LINKS for every insn in the
309 instruction stream as struct insn_link pointers. */
313 struct insn_link
*next
;
316 static struct insn_link
**uid_log_links
;
318 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
319 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
321 #define FOR_EACH_LOG_LINK(L, INSN) \
322 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
324 /* Links for LOG_LINKS are allocated from this obstack. */
326 static struct obstack insn_link_obstack
;
328 /* Allocate a link. */
330 static inline struct insn_link
*
331 alloc_insn_link (rtx insn
, struct insn_link
*next
)
334 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
335 sizeof (struct insn_link
));
341 /* Incremented for each basic block. */
343 static int label_tick
;
345 /* Reset to label_tick for each extended basic block in scanning order. */
347 static int label_tick_ebb_start
;
349 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
350 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
352 static enum machine_mode nonzero_bits_mode
;
354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
355 be safely used. It is zero while computing them and after combine has
356 completed. This former test prevents propagating values based on
357 previously set values, which can be incorrect if a variable is modified
360 static int nonzero_sign_valid
;
363 /* Record one modification to rtl structure
364 to be undone by storing old_contents into *where. */
366 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
372 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
373 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
377 num_undo says how many are currently recorded.
379 other_insn is nonzero if we have modified some other insn in the process
380 of working on subst_insn. It must be verified too. */
389 static struct undobuf undobuf
;
391 /* Number of times the pseudo being substituted for
392 was found and replaced. */
394 static int n_occurrences
;
396 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
398 unsigned HOST_WIDE_INT
,
399 unsigned HOST_WIDE_INT
*);
400 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
402 unsigned int, unsigned int *);
403 static void do_SUBST (rtx
*, rtx
);
404 static void do_SUBST_INT (int *, int);
405 static void init_reg_last (void);
406 static void setup_incoming_promotions (rtx
);
407 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
408 static int cant_combine_insn_p (rtx
);
409 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
410 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
411 static int contains_muldiv (rtx
);
412 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
413 static void undo_all (void);
414 static void undo_commit (void);
415 static rtx
*find_split_point (rtx
*, rtx
, bool);
416 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
417 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
418 static rtx
simplify_if_then_else (rtx
);
419 static rtx
simplify_set (rtx
);
420 static rtx
simplify_logical (rtx
);
421 static rtx
expand_compound_operation (rtx
);
422 static const_rtx
expand_field_assignment (const_rtx
);
423 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
424 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
425 static rtx
extract_left_shift (rtx
, int);
426 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
427 unsigned HOST_WIDE_INT
*);
428 static rtx
canon_reg_for_combine (rtx
, rtx
);
429 static rtx
force_to_mode (rtx
, enum machine_mode
,
430 unsigned HOST_WIDE_INT
, int);
431 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
432 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
433 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
434 static rtx
make_field_assignment (rtx
);
435 static rtx
apply_distributive_law (rtx
);
436 static rtx
distribute_and_simplify_rtx (rtx
, int);
437 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
438 unsigned HOST_WIDE_INT
);
439 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
440 unsigned HOST_WIDE_INT
);
441 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
442 HOST_WIDE_INT
, enum machine_mode
, int *);
443 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
444 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
446 static int recog_for_combine (rtx
*, rtx
, rtx
*);
447 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
448 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
449 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
450 static void update_table_tick (rtx
);
451 static void record_value_for_reg (rtx
, rtx
, rtx
);
452 static void check_promoted_subreg (rtx
, rtx
);
453 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
454 static void record_dead_and_set_regs (rtx
);
455 static int get_last_value_validate (rtx
*, rtx
, int, int);
456 static rtx
get_last_value (const_rtx
);
457 static int use_crosses_set_p (const_rtx
, int);
458 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
459 static int reg_dead_at_p (rtx
, rtx
);
460 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
461 static int reg_bitfield_target_p (rtx
, rtx
);
462 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
463 static void distribute_links (struct insn_link
*);
464 static void mark_used_regs_combine (rtx
);
465 static void record_promoted_value (rtx
, rtx
);
466 static int unmentioned_reg_p_1 (rtx
*, void *);
467 static bool unmentioned_reg_p (rtx
, rtx
);
468 static int record_truncated_value (rtx
*, void *);
469 static void record_truncated_values (rtx
*, void *);
470 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
471 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
474 /* It is not safe to use ordinary gen_lowpart in combine.
475 See comments in gen_lowpart_for_combine. */
476 #undef RTL_HOOKS_GEN_LOWPART
477 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
479 /* Our implementation of gen_lowpart never emits a new pseudo. */
480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
484 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
492 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
495 /* Convenience wrapper for the canonicalize_comparison target hook.
496 Target hooks cannot use enum rtx_code. */
498 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
499 bool op0_preserve_value
)
501 int code_int
= (int)*code
;
502 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
503 *code
= (enum rtx_code
)code_int
;
506 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
507 PATTERN can not be split. Otherwise, it returns an insn sequence.
508 This is a wrapper around split_insns which ensures that the
509 reg_stat vector is made larger if the splitter creates a new
513 combine_split_insns (rtx pattern
, rtx insn
)
518 ret
= split_insns (pattern
, insn
);
519 nregs
= max_reg_num ();
520 if (nregs
> reg_stat
.length ())
521 reg_stat
.safe_grow_cleared (nregs
);
525 /* This is used by find_single_use to locate an rtx in LOC that
526 contains exactly one use of DEST, which is typically either a REG
527 or CC0. It returns a pointer to the innermost rtx expression
528 containing DEST. Appearances of DEST that are being used to
529 totally replace it are not counted. */
532 find_single_use_1 (rtx dest
, rtx
*loc
)
535 enum rtx_code code
= GET_CODE (x
);
551 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
552 of a REG that occupies all of the REG, the insn uses DEST if
553 it is mentioned in the destination or the source. Otherwise, we
554 need just check the source. */
555 if (GET_CODE (SET_DEST (x
)) != CC0
556 && GET_CODE (SET_DEST (x
)) != PC
557 && !REG_P (SET_DEST (x
))
558 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
559 && REG_P (SUBREG_REG (SET_DEST (x
)))
560 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
561 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
562 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
563 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
566 return find_single_use_1 (dest
, &SET_SRC (x
));
570 return find_single_use_1 (dest
, &XEXP (x
, 0));
576 /* If it wasn't one of the common cases above, check each expression and
577 vector of this code. Look for a unique usage of DEST. */
579 fmt
= GET_RTX_FORMAT (code
);
580 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
584 if (dest
== XEXP (x
, i
)
585 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
586 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
589 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
592 result
= this_result
;
593 else if (this_result
)
594 /* Duplicate usage. */
597 else if (fmt
[i
] == 'E')
601 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
603 if (XVECEXP (x
, i
, j
) == dest
605 && REG_P (XVECEXP (x
, i
, j
))
606 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
609 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
612 result
= this_result
;
613 else if (this_result
)
623 /* See if DEST, produced in INSN, is used only a single time in the
624 sequel. If so, return a pointer to the innermost rtx expression in which
627 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
629 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
630 care about REG_DEAD notes or LOG_LINKS.
632 Otherwise, we find the single use by finding an insn that has a
633 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
634 only referenced once in that insn, we know that it must be the first
635 and last insn referencing DEST. */
638 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
643 struct insn_link
*link
;
648 next
= NEXT_INSN (insn
);
650 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
653 result
= find_single_use_1 (dest
, &PATTERN (next
));
663 bb
= BLOCK_FOR_INSN (insn
);
664 for (next
= NEXT_INSN (insn
);
665 next
&& BLOCK_FOR_INSN (next
) == bb
;
666 next
= NEXT_INSN (next
))
667 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
669 FOR_EACH_LOG_LINK (link
, next
)
670 if (link
->insn
== insn
)
675 result
= find_single_use_1 (dest
, &PATTERN (next
));
685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
686 insn. The substitution can be undone by undo_all. If INTO is already
687 set to NEWVAL, do not record this change. Because computing NEWVAL might
688 also call SUBST, we have to compute it before we put anything into
692 do_SUBST (rtx
*into
, rtx newval
)
697 if (oldval
== newval
)
700 /* We'd like to catch as many invalid transformations here as
701 possible. Unfortunately, there are way too many mode changes
702 that are perfectly valid, so we'd waste too much effort for
703 little gain doing the checks here. Focus on catching invalid
704 transformations involving integer constants. */
705 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
706 && CONST_INT_P (newval
))
708 /* Sanity check that we're replacing oldval with a CONST_INT
709 that is a valid sign-extension for the original mode. */
710 gcc_assert (INTVAL (newval
)
711 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
713 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
714 CONST_INT is not valid, because after the replacement, the
715 original mode would be gone. Unfortunately, we can't tell
716 when do_SUBST is called to replace the operand thereof, so we
717 perform this test on oldval instead, checking whether an
718 invalid replacement took place before we got here. */
719 gcc_assert (!(GET_CODE (oldval
) == SUBREG
720 && CONST_INT_P (SUBREG_REG (oldval
))));
721 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
722 && CONST_INT_P (XEXP (oldval
, 0))));
726 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
728 buf
= XNEW (struct undo
);
730 buf
->kind
= UNDO_RTX
;
732 buf
->old_contents
.r
= oldval
;
735 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
738 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
740 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
741 for the value of a HOST_WIDE_INT value (including CONST_INT) is
745 do_SUBST_INT (int *into
, int newval
)
750 if (oldval
== newval
)
754 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
756 buf
= XNEW (struct undo
);
758 buf
->kind
= UNDO_INT
;
760 buf
->old_contents
.i
= oldval
;
763 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
766 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
768 /* Similar to SUBST, but just substitute the mode. This is used when
769 changing the mode of a pseudo-register, so that any other
770 references to the entry in the regno_reg_rtx array will change as
774 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
777 enum machine_mode oldval
= GET_MODE (*into
);
779 if (oldval
== newval
)
783 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
785 buf
= XNEW (struct undo
);
787 buf
->kind
= UNDO_MODE
;
789 buf
->old_contents
.m
= oldval
;
790 adjust_reg_mode (*into
, newval
);
792 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
795 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
801 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
804 struct insn_link
* oldval
= *into
;
806 if (oldval
== newval
)
810 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
812 buf
= XNEW (struct undo
);
814 buf
->kind
= UNDO_LINKS
;
816 buf
->old_contents
.l
= oldval
;
819 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
825 /* Subroutine of try_combine. Determine whether the replacement patterns
826 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
827 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
828 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
829 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
830 of all the instructions can be estimated and the replacements are more
831 expensive than the original sequence. */
834 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
835 rtx newi2pat
, rtx newotherpat
)
837 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
838 int new_i2_cost
, new_i3_cost
;
839 int old_cost
, new_cost
;
841 /* Lookup the original insn_rtx_costs. */
842 i2_cost
= INSN_COST (i2
);
843 i3_cost
= INSN_COST (i3
);
847 i1_cost
= INSN_COST (i1
);
850 i0_cost
= INSN_COST (i0
);
851 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
852 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
856 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
857 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
863 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
864 i1_cost
= i0_cost
= 0;
867 /* Calculate the replacement insn_rtx_costs. */
868 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
871 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
872 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
873 ? new_i2_cost
+ new_i3_cost
: 0;
877 new_cost
= new_i3_cost
;
881 if (undobuf
.other_insn
)
883 int old_other_cost
, new_other_cost
;
885 old_other_cost
= INSN_COST (undobuf
.other_insn
);
886 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
887 if (old_other_cost
> 0 && new_other_cost
> 0)
889 old_cost
+= old_other_cost
;
890 new_cost
+= new_other_cost
;
896 /* Disallow this combination if both new_cost and old_cost are greater than
897 zero, and new_cost is greater than old cost. */
898 if (old_cost
> 0 && new_cost
> old_cost
)
905 "rejecting combination of insns %d, %d, %d and %d\n",
906 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
908 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
909 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
914 "rejecting combination of insns %d, %d and %d\n",
915 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
916 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
917 i1_cost
, i2_cost
, i3_cost
, old_cost
);
922 "rejecting combination of insns %d and %d\n",
923 INSN_UID (i2
), INSN_UID (i3
));
924 fprintf (dump_file
, "original costs %d + %d = %d\n",
925 i2_cost
, i3_cost
, old_cost
);
930 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
931 new_i2_cost
, new_i3_cost
, new_cost
);
934 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
940 /* Update the uid_insn_cost array with the replacement costs. */
941 INSN_COST (i2
) = new_i2_cost
;
942 INSN_COST (i3
) = new_i3_cost
;
954 /* Delete any insns that copy a register to itself. */
957 delete_noop_moves (void)
964 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
966 next
= NEXT_INSN (insn
);
967 if (INSN_P (insn
) && noop_move_p (insn
))
970 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
972 delete_insn_and_edges (insn
);
979 /* Fill in log links field for all insns. */
982 create_log_links (void)
986 df_ref
*def_vec
, *use_vec
;
988 next_use
= XCNEWVEC (rtx
, max_reg_num ());
990 /* Pass through each block from the end, recording the uses of each
991 register and establishing log links when def is encountered.
992 Note that we do not clear next_use array in order to save time,
993 so we have to test whether the use is in the same basic block as def.
995 There are a few cases below when we do not consider the definition or
996 usage -- these are taken from original flow.c did. Don't ask me why it is
997 done this way; I don't know and if it works, I don't want to know. */
1001 FOR_BB_INSNS_REVERSE (bb
, insn
)
1003 if (!NONDEBUG_INSN_P (insn
))
1006 /* Log links are created only once. */
1007 gcc_assert (!LOG_LINKS (insn
));
1009 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1011 df_ref def
= *def_vec
;
1012 int regno
= DF_REF_REGNO (def
);
1015 if (!next_use
[regno
])
1018 /* Do not consider if it is pre/post modification in MEM. */
1019 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1022 /* Do not make the log link for frame pointer. */
1023 if ((regno
== FRAME_POINTER_REGNUM
1024 && (! reload_completed
|| frame_pointer_needed
))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026 || (regno
== HARD_FRAME_POINTER_REGNUM
1027 && (! reload_completed
|| frame_pointer_needed
))
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1035 use_insn
= next_use
[regno
];
1036 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1040 We don't build a LOG_LINK for hard registers contained
1041 in ASM_OPERANDs. If these registers get replaced,
1042 we might wind up changing the semantics of the insn,
1043 even if reload can make what appear to be valid
1044 assignments later. */
1045 if (regno
>= FIRST_PSEUDO_REGISTER
1046 || asm_noperands (PATTERN (use_insn
)) < 0)
1048 /* Don't add duplicate links between instructions. */
1049 struct insn_link
*links
;
1050 FOR_EACH_LOG_LINK (links
, use_insn
)
1051 if (insn
== links
->insn
)
1055 LOG_LINKS (use_insn
)
1056 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1059 next_use
[regno
] = NULL_RTX
;
1062 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1064 df_ref use
= *use_vec
;
1065 int regno
= DF_REF_REGNO (use
);
1067 /* Do not consider the usage of the stack pointer
1068 by function call. */
1069 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1072 next_use
[regno
] = insn
;
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1081 true if we found a LOG_LINK that proves that A feeds B. This only works
1082 if there are no instructions between A and B which could have a link
1083 depending on A, since in that case we would not record a link for B.
1084 We also check the implicit dependency created by a cc0 setter/user
1088 insn_a_feeds_b (rtx a
, rtx b
)
1090 struct insn_link
*links
;
1091 FOR_EACH_LOG_LINK (links
, b
)
1092 if (links
->insn
== a
)
1101 /* Main entry point for combiner. F is the first insn of the function.
1102 NREGS is the first unused pseudo-reg number.
1104 Return nonzero if the combiner has turned an indirect jump
1105 instruction into a direct jump. */
1107 combine_instructions (rtx f
, unsigned int nregs
)
1113 struct insn_link
*links
, *nextlinks
;
1115 basic_block last_bb
;
1117 int new_direct_jump_p
= 0;
1119 for (first
= f
; first
&& !INSN_P (first
); )
1120 first
= NEXT_INSN (first
);
1124 combine_attempts
= 0;
1127 combine_successes
= 0;
1129 rtl_hooks
= combine_rtl_hooks
;
1131 reg_stat
.safe_grow_cleared (nregs
);
1133 init_recog_no_volatile ();
1135 /* Allocate array for insn info. */
1136 max_uid_known
= get_max_uid ();
1137 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1138 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1139 gcc_obstack_init (&insn_link_obstack
);
1141 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1143 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1144 problems when, for example, we have j <<= 1 in a loop. */
1146 nonzero_sign_valid
= 0;
1147 label_tick
= label_tick_ebb_start
= 1;
1149 /* Scan all SETs and see if we can deduce anything about what
1150 bits are known to be zero for some registers and how many copies
1151 of the sign bit are known to exist for those registers.
1153 Also set any known values so that we can use it while searching
1154 for what bits are known to be set. */
1156 setup_incoming_promotions (first
);
1157 /* Allow the entry block and the first block to fall into the same EBB.
1158 Conceptually the incoming promotions are assigned to the entry block. */
1159 last_bb
= ENTRY_BLOCK_PTR
;
1161 create_log_links ();
1162 FOR_EACH_BB (this_basic_block
)
1164 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1169 if (!single_pred_p (this_basic_block
)
1170 || single_pred (this_basic_block
) != last_bb
)
1171 label_tick_ebb_start
= label_tick
;
1172 last_bb
= this_basic_block
;
1174 FOR_BB_INSNS (this_basic_block
, insn
)
1175 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1181 subst_low_luid
= DF_INSN_LUID (insn
);
1184 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1186 record_dead_and_set_regs (insn
);
1189 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1190 if (REG_NOTE_KIND (links
) == REG_INC
)
1191 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1195 /* Record the current insn_rtx_cost of this instruction. */
1196 if (NONJUMP_INSN_P (insn
))
1197 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1198 optimize_this_for_speed_p
);
1200 fprintf(dump_file
, "insn_cost %d: %d\n",
1201 INSN_UID (insn
), INSN_COST (insn
));
1205 nonzero_sign_valid
= 1;
1207 /* Now scan all the insns in forward order. */
1208 label_tick
= label_tick_ebb_start
= 1;
1210 setup_incoming_promotions (first
);
1211 last_bb
= ENTRY_BLOCK_PTR
;
1213 FOR_EACH_BB (this_basic_block
)
1215 rtx last_combined_insn
= NULL_RTX
;
1216 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1221 if (!single_pred_p (this_basic_block
)
1222 || single_pred (this_basic_block
) != last_bb
)
1223 label_tick_ebb_start
= label_tick
;
1224 last_bb
= this_basic_block
;
1226 rtl_profile_for_bb (this_basic_block
);
1227 for (insn
= BB_HEAD (this_basic_block
);
1228 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1229 insn
= next
? next
: NEXT_INSN (insn
))
1232 if (NONDEBUG_INSN_P (insn
))
1234 while (last_combined_insn
1235 && INSN_DELETED_P (last_combined_insn
))
1236 last_combined_insn
= PREV_INSN (last_combined_insn
);
1237 if (last_combined_insn
== NULL_RTX
1238 || BARRIER_P (last_combined_insn
)
1239 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1240 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1241 last_combined_insn
= insn
;
1243 /* See if we know about function return values before this
1244 insn based upon SUBREG flags. */
1245 check_promoted_subreg (insn
, PATTERN (insn
));
1247 /* See if we can find hardregs and subreg of pseudos in
1248 narrower modes. This could help turning TRUNCATEs
1250 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1252 /* Try this insn with each insn it links back to. */
1254 FOR_EACH_LOG_LINK (links
, insn
)
1255 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1256 NULL_RTX
, &new_direct_jump_p
,
1257 last_combined_insn
)) != 0)
1260 /* Try each sequence of three linked insns ending with this one. */
1262 FOR_EACH_LOG_LINK (links
, insn
)
1264 rtx link
= links
->insn
;
1266 /* If the linked insn has been replaced by a note, then there
1267 is no point in pursuing this chain any further. */
1271 FOR_EACH_LOG_LINK (nextlinks
, link
)
1272 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1273 NULL_RTX
, &new_direct_jump_p
,
1274 last_combined_insn
)) != 0)
1279 /* Try to combine a jump insn that uses CC0
1280 with a preceding insn that sets CC0, and maybe with its
1281 logical predecessor as well.
1282 This is how we make decrement-and-branch insns.
1283 We need this special code because data flow connections
1284 via CC0 do not get entered in LOG_LINKS. */
1287 && (prev
= prev_nonnote_insn (insn
)) != 0
1288 && NONJUMP_INSN_P (prev
)
1289 && sets_cc0_p (PATTERN (prev
)))
1291 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1293 last_combined_insn
)) != 0)
1296 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1297 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1298 NULL_RTX
, &new_direct_jump_p
,
1299 last_combined_insn
)) != 0)
1303 /* Do the same for an insn that explicitly references CC0. */
1304 if (NONJUMP_INSN_P (insn
)
1305 && (prev
= prev_nonnote_insn (insn
)) != 0
1306 && NONJUMP_INSN_P (prev
)
1307 && sets_cc0_p (PATTERN (prev
))
1308 && GET_CODE (PATTERN (insn
)) == SET
1309 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1311 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1313 last_combined_insn
)) != 0)
1316 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1317 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1318 NULL_RTX
, &new_direct_jump_p
,
1319 last_combined_insn
)) != 0)
1323 /* Finally, see if any of the insns that this insn links to
1324 explicitly references CC0. If so, try this insn, that insn,
1325 and its predecessor if it sets CC0. */
1326 FOR_EACH_LOG_LINK (links
, insn
)
1327 if (NONJUMP_INSN_P (links
->insn
)
1328 && GET_CODE (PATTERN (links
->insn
)) == SET
1329 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1330 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && (next
= try_combine (insn
, links
->insn
,
1334 prev
, NULL_RTX
, &new_direct_jump_p
,
1335 last_combined_insn
)) != 0)
1339 /* Try combining an insn with two different insns whose results it
1341 FOR_EACH_LOG_LINK (links
, insn
)
1342 for (nextlinks
= links
->next
; nextlinks
;
1343 nextlinks
= nextlinks
->next
)
1344 if ((next
= try_combine (insn
, links
->insn
,
1345 nextlinks
->insn
, NULL_RTX
,
1347 last_combined_insn
)) != 0)
1350 /* Try four-instruction combinations. */
1351 FOR_EACH_LOG_LINK (links
, insn
)
1353 struct insn_link
*next1
;
1354 rtx link
= links
->insn
;
1356 /* If the linked insn has been replaced by a note, then there
1357 is no point in pursuing this chain any further. */
1361 FOR_EACH_LOG_LINK (next1
, link
)
1363 rtx link1
= next1
->insn
;
1366 /* I0 -> I1 -> I2 -> I3. */
1367 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1368 if ((next
= try_combine (insn
, link
, link1
,
1371 last_combined_insn
)) != 0)
1373 /* I0, I1 -> I2, I2 -> I3. */
1374 for (nextlinks
= next1
->next
; nextlinks
;
1375 nextlinks
= nextlinks
->next
)
1376 if ((next
= try_combine (insn
, link
, link1
,
1379 last_combined_insn
)) != 0)
1383 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1385 rtx link1
= next1
->insn
;
1388 /* I0 -> I2; I1, I2 -> I3. */
1389 FOR_EACH_LOG_LINK (nextlinks
, link
)
1390 if ((next
= try_combine (insn
, link
, link1
,
1393 last_combined_insn
)) != 0)
1395 /* I0 -> I1; I1, I2 -> I3. */
1396 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1397 if ((next
= try_combine (insn
, link
, link1
,
1400 last_combined_insn
)) != 0)
1405 /* Try this insn with each REG_EQUAL note it links back to. */
1406 FOR_EACH_LOG_LINK (links
, insn
)
1409 rtx temp
= links
->insn
;
1410 if ((set
= single_set (temp
)) != 0
1411 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1412 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1413 /* Avoid using a register that may already been marked
1414 dead by an earlier instruction. */
1415 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1416 && (GET_MODE (note
) == VOIDmode
1417 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1418 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1420 /* Temporarily replace the set's source with the
1421 contents of the REG_EQUAL note. The insn will
1422 be deleted or recognized by try_combine. */
1423 rtx orig
= SET_SRC (set
);
1424 SET_SRC (set
) = note
;
1426 i2mod_old_rhs
= copy_rtx (orig
);
1427 i2mod_new_rhs
= copy_rtx (note
);
1428 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1430 last_combined_insn
);
1434 SET_SRC (set
) = orig
;
1439 record_dead_and_set_regs (insn
);
1447 default_rtl_profile ();
1449 new_direct_jump_p
|= purge_all_dead_edges ();
1450 delete_noop_moves ();
1453 obstack_free (&insn_link_obstack
, NULL
);
1454 free (uid_log_links
);
1455 free (uid_insn_cost
);
1456 reg_stat
.release ();
1459 struct undo
*undo
, *next
;
1460 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1468 total_attempts
+= combine_attempts
;
1469 total_merges
+= combine_merges
;
1470 total_extras
+= combine_extras
;
1471 total_successes
+= combine_successes
;
1473 nonzero_sign_valid
= 0;
1474 rtl_hooks
= general_rtl_hooks
;
1476 /* Make recognizer allow volatile MEMs again. */
1479 return new_direct_jump_p
;
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1485 init_reg_last (void)
1490 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1491 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1494 /* Set up any promoted values for incoming argument registers. */
1497 setup_incoming_promotions (rtx first
)
1500 bool strictly_local
= false;
1502 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1503 arg
= DECL_CHAIN (arg
))
1505 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1507 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1509 /* Only continue if the incoming argument is in a register. */
1513 /* Determine, if possible, whether all call sites of the current
1514 function lie within the current compilation unit. (This does
1515 take into account the exporting of a function via taking its
1516 address, and so forth.) */
1517 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1519 /* The mode and signedness of the argument before any promotions happen
1520 (equal to the mode of the pseudo holding it at that stage). */
1521 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1522 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1524 /* The mode and signedness of the argument after any source language and
1525 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1526 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1527 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1529 /* The mode and signedness of the argument as it is actually passed,
1530 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1531 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1532 TREE_TYPE (cfun
->decl
), 0);
1534 /* The mode of the register in which the argument is being passed. */
1535 mode4
= GET_MODE (reg
);
1537 /* Eliminate sign extensions in the callee when:
1538 (a) A mode promotion has occurred; */
1541 /* (b) The mode of the register is the same as the mode of
1542 the argument as it is passed; */
1545 /* (c) There's no language level extension; */
1548 /* (c.1) All callers are from the current compilation unit. If that's
1549 the case we don't have to rely on an ABI, we only have to know
1550 what we're generating right now, and we know that we will do the
1551 mode1 to mode2 promotion with the given sign. */
1552 else if (!strictly_local
)
1554 /* (c.2) The combination of the two promotions is useful. This is
1555 true when the signs match, or if the first promotion is unsigned.
1556 In the later case, (sign_extend (zero_extend x)) is the same as
1557 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1563 /* Record that the value was promoted from mode1 to mode3,
1564 so that any sign extension at the head of the current
1565 function may be eliminated. */
1566 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1567 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1568 record_value_for_reg (reg
, first
, x
);
1572 /* Called via note_stores. If X is a pseudo that is narrower than
1573 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1575 If we are setting only a portion of X and we can't figure out what
1576 portion, assume all bits will be used since we don't know what will
1579 Similarly, set how many bits of X are known to be copies of the sign bit
1580 at all locations in the function. This is the smallest number implied
1584 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1586 rtx insn
= (rtx
) data
;
1590 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1591 /* If this register is undefined at the start of the file, we can't
1592 say what its contents were. */
1593 && ! REGNO_REG_SET_P
1594 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1595 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1597 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1599 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1601 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1602 rsp
->sign_bit_copies
= 1;
1606 /* If this register is being initialized using itself, and the
1607 register is uninitialized in this basic block, and there are
1608 no LOG_LINKS which set the register, then part of the
1609 register is uninitialized. In that case we can't assume
1610 anything about the number of nonzero bits.
1612 ??? We could do better if we checked this in
1613 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1614 could avoid making assumptions about the insn which initially
1615 sets the register, while still using the information in other
1616 insns. We would have to be careful to check every insn
1617 involved in the combination. */
1620 && reg_referenced_p (x
, PATTERN (insn
))
1621 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1624 struct insn_link
*link
;
1626 FOR_EACH_LOG_LINK (link
, insn
)
1627 if (dead_or_set_p (link
->insn
, x
))
1631 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1632 rsp
->sign_bit_copies
= 1;
1637 /* If this is a complex assignment, see if we can convert it into a
1638 simple assignment. */
1639 set
= expand_field_assignment (set
);
1641 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642 set what we know about X. */
1644 if (SET_DEST (set
) == x
1645 || (paradoxical_subreg_p (SET_DEST (set
))
1646 && SUBREG_REG (SET_DEST (set
)) == x
))
1648 rtx src
= SET_SRC (set
);
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651 /* If X is narrower than a word and SRC is a non-negative
1652 constant that would appear negative in the mode of X,
1653 sign-extend it for use in reg_stat[].nonzero_bits because some
1654 machines (maybe most) will actually do the sign-extension
1655 and this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard
1658 instead of this kludge. */
1660 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1661 && CONST_INT_P (src
)
1663 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1664 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1667 /* Don't call nonzero_bits if it cannot change anything. */
1668 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1669 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1670 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1671 if (rsp
->sign_bit_copies
== 0
1672 || rsp
->sign_bit_copies
> num
)
1673 rsp
->sign_bit_copies
= num
;
1677 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1678 rsp
->sign_bit_copies
= 1;
1683 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1684 optionally insns that were previously combined into I3 or that will be
1685 combined into the merger of INSN and I3. The order is PRED, PRED2,
1686 INSN, SUCC, SUCC2, I3.
1688 Return 0 if the combination is not allowed for any reason.
1690 If the combination is allowed, *PDEST will be set to the single
1691 destination of INSN and *PSRC to the single source, and this function
1695 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1696 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1697 rtx
*pdest
, rtx
*psrc
)
1706 bool all_adjacent
= true;
1707 int (*is_volatile_p
) (const_rtx
);
1713 if (next_active_insn (succ2
) != i3
)
1714 all_adjacent
= false;
1715 if (next_active_insn (succ
) != succ2
)
1716 all_adjacent
= false;
1718 else if (next_active_insn (succ
) != i3
)
1719 all_adjacent
= false;
1720 if (next_active_insn (insn
) != succ
)
1721 all_adjacent
= false;
1723 else if (next_active_insn (insn
) != i3
)
1724 all_adjacent
= false;
1726 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727 or a PARALLEL consisting of such a SET and CLOBBERs.
1729 If INSN has CLOBBER parallel parts, ignore them for our processing.
1730 By definition, these happen during the execution of the insn. When it
1731 is merged with another insn, all bets are off. If they are, in fact,
1732 needed and aren't also supplied in I3, they may be added by
1733 recog_for_combine. Otherwise, it won't match.
1735 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1738 Get the source and destination of INSN. If more than one, can't
1741 if (GET_CODE (PATTERN (insn
)) == SET
)
1742 set
= PATTERN (insn
);
1743 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1744 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1746 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1748 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1750 switch (GET_CODE (elt
))
1752 /* This is important to combine floating point insns
1753 for the SH4 port. */
1755 /* Combining an isolated USE doesn't make sense.
1756 We depend here on combinable_i3pat to reject them. */
1757 /* The code below this loop only verifies that the inputs of
1758 the SET in INSN do not change. We call reg_set_between_p
1759 to verify that the REG in the USE does not change between
1761 If the USE in INSN was for a pseudo register, the matching
1762 insn pattern will likely match any register; combining this
1763 with any other USE would only be safe if we knew that the
1764 used registers have identical values, or if there was
1765 something to tell them apart, e.g. different modes. For
1766 now, we forgo such complicated tests and simply disallow
1767 combining of USES of pseudo registers with any other USE. */
1768 if (REG_P (XEXP (elt
, 0))
1769 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1771 rtx i3pat
= PATTERN (i3
);
1772 int i
= XVECLEN (i3pat
, 0) - 1;
1773 unsigned int regno
= REGNO (XEXP (elt
, 0));
1777 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1779 if (GET_CODE (i3elt
) == USE
1780 && REG_P (XEXP (i3elt
, 0))
1781 && (REGNO (XEXP (i3elt
, 0)) == regno
1782 ? reg_set_between_p (XEXP (elt
, 0),
1783 PREV_INSN (insn
), i3
)
1784 : regno
>= FIRST_PSEUDO_REGISTER
))
1791 /* We can ignore CLOBBERs. */
1796 /* Ignore SETs whose result isn't used but not those that
1797 have side-effects. */
1798 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1799 && insn_nothrow_p (insn
)
1800 && !side_effects_p (elt
))
1803 /* If we have already found a SET, this is a second one and
1804 so we cannot combine with this insn. */
1812 /* Anything else means we can't combine. */
1818 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819 so don't do anything with it. */
1820 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1829 /* The simplification in expand_field_assignment may call back to
1830 get_last_value, so set safe guard here. */
1831 subst_low_luid
= DF_INSN_LUID (insn
);
1833 set
= expand_field_assignment (set
);
1834 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1836 /* Don't eliminate a store in the stack pointer. */
1837 if (dest
== stack_pointer_rtx
1838 /* Don't combine with an insn that sets a register to itself if it has
1839 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1840 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1841 /* Can't merge an ASM_OPERANDS. */
1842 || GET_CODE (src
) == ASM_OPERANDS
1843 /* Can't merge a function call. */
1844 || GET_CODE (src
) == CALL
1845 /* Don't eliminate a function call argument. */
1847 && (find_reg_fusage (i3
, USE
, dest
)
1849 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1850 && global_regs
[REGNO (dest
)])))
1851 /* Don't substitute into an incremented register. */
1852 || FIND_REG_INC_NOTE (i3
, dest
)
1853 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1854 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1855 /* Don't substitute into a non-local goto, this confuses CFG. */
1856 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1857 /* Make sure that DEST is not used after SUCC but before I3. */
1860 && (reg_used_between_p (dest
, succ2
, i3
)
1861 || reg_used_between_p (dest
, succ
, succ2
)))
1862 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1863 /* Make sure that the value that is to be substituted for the register
1864 does not use any registers whose values alter in between. However,
1865 If the insns are adjacent, a use can't cross a set even though we
1866 think it might (this can happen for a sequence of insns each setting
1867 the same destination; last_set of that register might point to
1868 a NOTE). If INSN has a REG_EQUIV note, the register is always
1869 equivalent to the memory so the substitution is valid even if there
1870 are intervening stores. Also, don't move a volatile asm or
1871 UNSPEC_VOLATILE across any other insns. */
1874 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1875 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1876 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1877 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1878 /* Don't combine across a CALL_INSN, because that would possibly
1879 change whether the life span of some REGs crosses calls or not,
1880 and it is a pain to update that information.
1881 Exception: if source is a constant, moving it later can't hurt.
1882 Accept that as a special case. */
1883 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1886 /* DEST must either be a REG or CC0. */
1889 /* If register alignment is being enforced for multi-word items in all
1890 cases except for parameters, it is possible to have a register copy
1891 insn referencing a hard register that is not allowed to contain the
1892 mode being copied and which would not be valid as an operand of most
1893 insns. Eliminate this problem by not combining with such an insn.
1895 Also, on some machines we don't want to extend the life of a hard
1899 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1901 /* Don't extend the life of a hard register unless it is
1902 user variable (if we have few registers) or it can't
1903 fit into the desired register (meaning something special
1905 Also avoid substituting a return register into I3, because
1906 reload can't handle a conflict with constraints of other
1908 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1909 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1912 else if (GET_CODE (dest
) != CC0
)
1916 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1917 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1918 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1920 /* Don't substitute for a register intended as a clobberable
1922 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1923 if (rtx_equal_p (reg
, dest
))
1926 /* If the clobber represents an earlyclobber operand, we must not
1927 substitute an expression containing the clobbered register.
1928 As we do not analyze the constraint strings here, we have to
1929 make the conservative assumption. However, if the register is
1930 a fixed hard reg, the clobber cannot represent any operand;
1931 we leave it up to the machine description to either accept or
1932 reject use-and-clobber patterns. */
1934 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1935 || !fixed_regs
[REGNO (reg
)])
1936 if (reg_overlap_mentioned_p (reg
, src
))
1940 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941 or not), reject, unless nothing volatile comes between it and I3 */
1943 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1945 /* Make sure neither succ nor succ2 contains a volatile reference. */
1946 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1948 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1950 /* We'll check insns between INSN and I3 below. */
1953 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954 to be an explicit register variable, and was chosen for a reason. */
1956 if (GET_CODE (src
) == ASM_OPERANDS
1957 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1960 /* If INSN contains volatile references (specifically volatile MEMs),
1961 we cannot combine across any other volatile references.
1962 Even if INSN doesn't contain volatile references, any intervening
1963 volatile insn might affect machine state. */
1965 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1969 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1970 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1973 /* If INSN contains an autoincrement or autodecrement, make sure that
1974 register is not used between there and I3, and not already used in
1975 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1976 Also insist that I3 not be a jump; if it were one
1977 and the incremented register were spilled, we would lose. */
1980 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1981 if (REG_NOTE_KIND (link
) == REG_INC
1983 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1984 || (pred
!= NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1986 || (pred2
!= NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1988 || (succ
!= NULL_RTX
1989 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1990 || (succ2
!= NULL_RTX
1991 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1992 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1997 /* Don't combine an insn that follows a CC0-setting insn.
1998 An insn that uses CC0 must not be separated from the one that sets it.
1999 We do, however, allow I2 to follow a CC0-setting insn if that insn
2000 is passed as I1; in that case it will be deleted also.
2001 We also allow combining in this case if all the insns are adjacent
2002 because that would leave the two CC0 insns adjacent as well.
2003 It would be more logical to test whether CC0 occurs inside I1 or I2,
2004 but that would be much slower, and this ought to be equivalent. */
2006 p
= prev_nonnote_insn (insn
);
2007 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2012 /* If we get here, we have passed all the tests and the combination is
2021 /* LOC is the location within I3 that contains its pattern or the component
2022 of a PARALLEL of the pattern. We validate that it is valid for combining.
2024 One problem is if I3 modifies its output, as opposed to replacing it
2025 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026 doing so would produce an insn that is not equivalent to the original insns.
2030 (set (reg:DI 101) (reg:DI 100))
2031 (set (subreg:SI (reg:DI 101) 0) <foo>)
2033 This is NOT equivalent to:
2035 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036 (set (reg:DI 101) (reg:DI 100))])
2038 Not only does this modify 100 (in which case it might still be valid
2039 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2041 We can also run into a problem if I2 sets a register that I1
2042 uses and I1 gets directly substituted into I3 (not via I2). In that
2043 case, we would be getting the wrong value of I2DEST into I3, so we
2044 must reject the combination. This case occurs when I2 and I1 both
2045 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047 of a SET must prevent combination from occurring. The same situation
2048 can occur for I0, in which case I0_NOT_IN_SRC is set.
2050 Before doing the above check, we first try to expand a field assignment
2051 into a set of logical operations.
2053 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054 we place a register that is both set and used within I3. If more than one
2055 such register is detected, we fail.
2057 Return 1 if the combination is valid, zero otherwise. */
2060 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2061 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2065 if (GET_CODE (x
) == SET
)
2068 rtx dest
= SET_DEST (set
);
2069 rtx src
= SET_SRC (set
);
2070 rtx inner_dest
= dest
;
2073 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2074 || GET_CODE (inner_dest
) == SUBREG
2075 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2076 inner_dest
= XEXP (inner_dest
, 0);
2078 /* Check for the case where I3 modifies its output, as discussed
2079 above. We don't want to prevent pseudos from being combined
2080 into the address of a MEM, so only prevent the combination if
2081 i1 or i2 set the same MEM. */
2082 if ((inner_dest
!= dest
&&
2083 (!MEM_P (inner_dest
)
2084 || rtx_equal_p (i2dest
, inner_dest
)
2085 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2086 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2087 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2088 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2089 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2091 /* This is the same test done in can_combine_p except we can't test
2092 all_adjacent; we don't have to, since this instruction will stay
2093 in place, thus we are not considering increasing the lifetime of
2096 Also, if this insn sets a function argument, combining it with
2097 something that might need a spill could clobber a previous
2098 function argument; the all_adjacent test in can_combine_p also
2099 checks this; here, we do a more specific test for this case. */
2101 || (REG_P (inner_dest
)
2102 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2103 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2104 GET_MODE (inner_dest
))))
2105 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2106 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2109 /* If DEST is used in I3, it is being killed in this insn, so
2110 record that for later. We have to consider paradoxical
2111 subregs here, since they kill the whole register, but we
2112 ignore partial subregs, STRICT_LOW_PART, etc.
2113 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114 STACK_POINTER_REGNUM, since these are always considered to be
2115 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2117 if (GET_CODE (subdest
) == SUBREG
2118 && (GET_MODE_SIZE (GET_MODE (subdest
))
2119 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2120 subdest
= SUBREG_REG (subdest
);
2123 && reg_referenced_p (subdest
, PATTERN (i3
))
2124 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2130 || ! fixed_regs
[REGNO (subdest
)])
2132 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2134 if (*pi3dest_killed
)
2137 *pi3dest_killed
= subdest
;
2141 else if (GET_CODE (x
) == PARALLEL
)
2145 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2146 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2147 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155 and division. We don't count multiplications by powers of two here. */
2158 contains_muldiv (rtx x
)
2160 switch (GET_CODE (x
))
2162 case MOD
: case DIV
: case UMOD
: case UDIV
:
2166 return ! (CONST_INT_P (XEXP (x
, 1))
2167 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2170 return contains_muldiv (XEXP (x
, 0))
2171 || contains_muldiv (XEXP (x
, 1));
2174 return contains_muldiv (XEXP (x
, 0));
2180 /* Determine whether INSN can be used in a combination. Return nonzero if
2181 not. This is used in try_combine to detect early some cases where we
2182 can't perform combinations. */
2185 cant_combine_insn_p (rtx insn
)
2190 /* If this isn't really an insn, we can't do anything.
2191 This can occur when flow deletes an insn that it has merged into an
2192 auto-increment address. */
2193 if (! INSN_P (insn
))
2196 /* Never combine loads and stores involving hard regs that are likely
2197 to be spilled. The register allocator can usually handle such
2198 reg-reg moves by tying. If we allow the combiner to make
2199 substitutions of likely-spilled regs, reload might die.
2200 As an exception, we allow combinations involving fixed regs; these are
2201 not available to the register allocator so there's no risk involved. */
2203 set
= single_set (insn
);
2206 src
= SET_SRC (set
);
2207 dest
= SET_DEST (set
);
2208 if (GET_CODE (src
) == SUBREG
)
2209 src
= SUBREG_REG (src
);
2210 if (GET_CODE (dest
) == SUBREG
)
2211 dest
= SUBREG_REG (dest
);
2212 if (REG_P (src
) && REG_P (dest
)
2213 && ((HARD_REGISTER_P (src
)
2214 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2215 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2216 || (HARD_REGISTER_P (dest
)
2217 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2218 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2224 struct likely_spilled_retval_info
2226 unsigned regno
, nregs
;
2230 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2231 hard registers that are known to be written to / clobbered in full. */
2233 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2235 struct likely_spilled_retval_info
*const info
=
2236 (struct likely_spilled_retval_info
*) data
;
2237 unsigned regno
, nregs
;
2240 if (!REG_P (XEXP (set
, 0)))
2243 if (regno
>= info
->regno
+ info
->nregs
)
2245 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2246 if (regno
+ nregs
<= info
->regno
)
2248 new_mask
= (2U << (nregs
- 1)) - 1;
2249 if (regno
< info
->regno
)
2250 new_mask
>>= info
->regno
- regno
;
2252 new_mask
<<= regno
- info
->regno
;
2253 info
->mask
&= ~new_mask
;
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257 it is likely spilled. This can happen when more than one insn is needed
2258 to copy the return value, e.g. when we consider to combine into the
2259 second copy insn for a complex value. */
2262 likely_spilled_retval_p (rtx insn
)
2264 rtx use
= BB_END (this_basic_block
);
2266 unsigned regno
, nregs
;
2267 /* We assume here that no machine mode needs more than
2268 32 hard registers when the value overlaps with a register
2269 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2271 struct likely_spilled_retval_info info
;
2273 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2275 reg
= XEXP (PATTERN (use
), 0);
2276 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2278 regno
= REGNO (reg
);
2279 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2282 mask
= (2U << (nregs
- 1)) - 1;
2284 /* Disregard parts of the return value that are set later. */
2288 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2290 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2293 /* Check if any of the (probably) live return value registers is
2298 if ((mask
& 1 << nregs
)
2299 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2305 /* Adjust INSN after we made a change to its destination.
2307 Changing the destination can invalidate notes that say something about
2308 the results of the insn and a LOG_LINK pointing to the insn. */
2311 adjust_for_new_dest (rtx insn
)
2313 /* For notes, be conservative and simply remove them. */
2314 remove_reg_equal_equiv_notes (insn
);
2316 /* The new insn will have a destination that was previously the destination
2317 of an insn just above it. Call distribute_links to make a LOG_LINK from
2318 the next use of that destination. */
2319 distribute_links (alloc_insn_link (insn
, NULL
));
2321 df_insn_rescan (insn
);
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325 ADDED_SETS is nonzero if the original set is still required. */
2327 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2335 /* Allow hard registers if the new mode is legal, and occupies no more
2336 registers than the old mode. */
2337 if (regno
< FIRST_PSEUDO_REGISTER
)
2338 return (HARD_REGNO_MODE_OK (regno
, mode
)
2339 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2340 >= hard_regno_nregs
[regno
][mode
]));
2342 /* Or a pseudo that is only used once. */
2343 return (REG_N_SETS (regno
) == 1 && !added_sets
2344 && !REG_USERVAR_P (x
));
2348 /* Check whether X, the destination of a set, refers to part of
2349 the register specified by REG. */
2352 reg_subword_p (rtx x
, rtx reg
)
2354 /* Check that reg is an integer mode register. */
2355 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2358 if (GET_CODE (x
) == STRICT_LOW_PART
2359 || GET_CODE (x
) == ZERO_EXTRACT
)
2362 return GET_CODE (x
) == SUBREG
2363 && SUBREG_REG (x
) == reg
2364 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368 Note that the INSN should be deleted *after* removing dead edges, so
2369 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370 but not for a (set (pc) (label_ref FOO)). */
2373 update_cfg_for_uncondjump (rtx insn
)
2375 basic_block bb
= BLOCK_FOR_INSN (insn
);
2376 gcc_assert (BB_END (bb
) == insn
);
2378 purge_dead_edges (bb
);
2381 if (EDGE_COUNT (bb
->succs
) == 1)
2385 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2387 /* Remove barriers from the footer if there are any. */
2388 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2389 if (BARRIER_P (insn
))
2391 if (PREV_INSN (insn
))
2392 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2394 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2395 if (NEXT_INSN (insn
))
2396 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2398 else if (LABEL_P (insn
))
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404 Here I0, I1 and I2 appear earlier than I3.
2405 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2408 If we are combining more than two insns and the resulting insn is not
2409 recognized, try splitting it into two insns. If that happens, I2 and I3
2410 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411 Otherwise, I0, I1 and I2 are pseudo-deleted.
2413 Return 0 if the combination does not work. Then nothing is changed.
2414 If we did the combination, return the insn at which combine should
2417 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418 new direct jump instruction.
2420 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421 been I3 passed to an earlier try_combine within the same basic
2425 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2426 rtx last_combined_insn
)
2428 /* New patterns for I3 and I2, respectively. */
2429 rtx newpat
, newi2pat
= 0;
2430 rtvec newpat_vec_with_clobbers
= 0;
2431 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2432 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2434 int added_sets_0
, added_sets_1
, added_sets_2
;
2435 /* Total number of SETs to put into I3. */
2437 /* Nonzero if I2's or I1's body now appears in I3. */
2438 int i2_is_used
= 0, i1_is_used
= 0;
2439 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2440 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2441 /* Contains I3 if the destination of I3 is used in its source, which means
2442 that the old life of I3 is being killed. If that usage is placed into
2443 I2 and not in I3, a REG_DEAD note must be made. */
2444 rtx i3dest_killed
= 0;
2445 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2446 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2447 /* Copy of SET_SRC of I1 and I0, if needed. */
2448 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2449 /* Set if I2DEST was reused as a scratch register. */
2450 bool i2scratch
= false;
2451 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2452 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2453 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2454 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2455 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2456 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2457 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2458 /* Notes that must be added to REG_NOTES in I3 and I2. */
2459 rtx new_i3_notes
, new_i2_notes
;
2460 /* Notes that we substituted I3 into I2 instead of the normal case. */
2461 int i3_subst_into_i2
= 0;
2462 /* Notes that I1, I2 or I3 is a MULT operation. */
2465 int changed_i3_dest
= 0;
2469 struct insn_link
*link
;
2471 rtx new_other_notes
;
2474 /* Only try four-insn combinations when there's high likelihood of
2475 success. Look for simple insns, such as loads of constants or
2476 binary operations involving a constant. */
2483 if (!flag_expensive_optimizations
)
2486 for (i
= 0; i
< 4; i
++)
2488 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2489 rtx set
= single_set (insn
);
2493 src
= SET_SRC (set
);
2494 if (CONSTANT_P (src
))
2499 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2501 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2502 || GET_CODE (src
) == LSHIFTRT
)
2505 if (ngood
< 2 && nshift
< 2)
2509 /* Exit early if one of the insns involved can't be used for
2511 if (cant_combine_insn_p (i3
)
2512 || cant_combine_insn_p (i2
)
2513 || (i1
&& cant_combine_insn_p (i1
))
2514 || (i0
&& cant_combine_insn_p (i0
))
2515 || likely_spilled_retval_p (i3
))
2519 undobuf
.other_insn
= 0;
2521 /* Reset the hard register usage information. */
2522 CLEAR_HARD_REG_SET (newpat_used_regs
);
2524 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2527 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2528 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2530 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2531 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2533 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2534 INSN_UID (i2
), INSN_UID (i3
));
2537 /* If multiple insns feed into one of I2 or I3, they can be in any
2538 order. To simplify the code below, reorder them in sequence. */
2539 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2540 temp
= i2
, i2
= i0
, i0
= temp
;
2541 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2542 temp
= i1
, i1
= i0
, i0
= temp
;
2543 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2544 temp
= i1
, i1
= i2
, i2
= temp
;
2546 added_links_insn
= 0;
2548 /* First check for one important special case that the code below will
2549 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2550 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2551 we may be able to replace that destination with the destination of I3.
2552 This occurs in the common code where we compute both a quotient and
2553 remainder into a structure, in which case we want to do the computation
2554 directly into the structure to avoid register-register copies.
2556 Note that this case handles both multiple sets in I2 and also cases
2557 where I2 has a number of CLOBBERs inside the PARALLEL.
2559 We make very conservative checks below and only try to handle the
2560 most common cases of this. For example, we only handle the case
2561 where I2 and I3 are adjacent to avoid making difficult register
2564 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2565 && REG_P (SET_SRC (PATTERN (i3
)))
2566 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2567 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2568 && GET_CODE (PATTERN (i2
)) == PARALLEL
2569 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2570 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571 below would need to check what is inside (and reg_overlap_mentioned_p
2572 doesn't support those codes anyway). Don't allow those destinations;
2573 the resulting insn isn't likely to be recognized anyway. */
2574 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2575 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2576 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2577 SET_DEST (PATTERN (i3
)))
2578 && next_active_insn (i2
) == i3
)
2580 rtx p2
= PATTERN (i2
);
2582 /* Make sure that the destination of I3,
2583 which we are going to substitute into one output of I2,
2584 is not used within another output of I2. We must avoid making this:
2585 (parallel [(set (mem (reg 69)) ...)
2586 (set (reg 69) ...)])
2587 which is not well-defined as to order of actions.
2588 (Besides, reload can't handle output reloads for this.)
2590 The problem can also happen if the dest of I3 is a memory ref,
2591 if another dest in I2 is an indirect memory ref. */
2592 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2593 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2594 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2595 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2596 SET_DEST (XVECEXP (p2
, 0, i
))))
2599 if (i
== XVECLEN (p2
, 0))
2600 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2601 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2602 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2607 subst_low_luid
= DF_INSN_LUID (i2
);
2609 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2610 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2611 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2612 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2614 /* Replace the dest in I2 with our dest and make the resulting
2615 insn the new pattern for I3. Then skip to where we validate
2616 the pattern. Everything was set up above. */
2617 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2619 i3_subst_into_i2
= 1;
2620 goto validate_replacement
;
2624 /* If I2 is setting a pseudo to a constant and I3 is setting some
2625 sub-part of it to another constant, merge them by making a new
2628 && (temp
= single_set (i2
)) != 0
2629 && CONST_SCALAR_INT_P (SET_SRC (temp
))
2630 && GET_CODE (PATTERN (i3
)) == SET
2631 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2632 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2634 rtx dest
= SET_DEST (PATTERN (i3
));
2638 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2640 if (CONST_INT_P (XEXP (dest
, 1))
2641 && CONST_INT_P (XEXP (dest
, 2)))
2643 width
= INTVAL (XEXP (dest
, 1));
2644 offset
= INTVAL (XEXP (dest
, 2));
2645 dest
= XEXP (dest
, 0);
2646 if (BITS_BIG_ENDIAN
)
2647 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2652 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2653 dest
= XEXP (dest
, 0);
2654 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2660 /* If this is the low part, we're done. */
2661 if (subreg_lowpart_p (dest
))
2663 /* Handle the case where inner is twice the size of outer. */
2664 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2665 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2666 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2667 /* Otherwise give up for now. */
2673 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2674 <= HOST_BITS_PER_DOUBLE_INT
))
2677 rtx inner
= SET_SRC (PATTERN (i3
));
2678 rtx outer
= SET_SRC (temp
);
2680 o
= rtx_to_double_int (outer
);
2681 i
= rtx_to_double_int (inner
);
2683 m
= double_int::mask (width
);
2685 m
= m
.llshift (offset
, HOST_BITS_PER_DOUBLE_INT
);
2686 i
= i
.llshift (offset
, HOST_BITS_PER_DOUBLE_INT
);
2687 o
= o
.and_not (m
) | i
;
2691 subst_low_luid
= DF_INSN_LUID (i2
);
2692 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2693 i2dest
= SET_DEST (temp
);
2694 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2696 /* Replace the source in I2 with the new constant and make the
2697 resulting insn the new pattern for I3. Then skip to where we
2698 validate the pattern. Everything was set up above. */
2699 SUBST (SET_SRC (temp
),
2700 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2702 newpat
= PATTERN (i2
);
2704 /* The dest of I3 has been replaced with the dest of I2. */
2705 changed_i3_dest
= 1;
2706 goto validate_replacement
;
2711 /* If we have no I1 and I2 looks like:
2712 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2714 make up a dummy I1 that is
2717 (set (reg:CC X) (compare:CC Y (const_int 0)))
2719 (We can ignore any trailing CLOBBERs.)
2721 This undoes a previous combination and allows us to match a branch-and-
2724 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2725 && XVECLEN (PATTERN (i2
), 0) >= 2
2726 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2727 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2729 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2730 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2731 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2732 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2733 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2734 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2736 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2737 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2742 /* We make I1 with the same INSN_UID as I2. This gives it
2743 the same DF_INSN_LUID for value tracking. Our fake I1 will
2744 never appear in the insn stream so giving it the same INSN_UID
2745 as I2 will not cause a problem. */
2747 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2748 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2749 INSN_LOCATION (i2
), -1, NULL_RTX
);
2751 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2752 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2753 SET_DEST (PATTERN (i1
)));
2754 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2759 /* Verify that I2 and I1 are valid for combining. */
2760 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2761 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2763 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2770 /* Record whether I2DEST is used in I2SRC and similarly for the other
2771 cases. Knowing this will help in register status updating below. */
2772 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2773 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2774 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2775 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2776 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2777 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2778 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2779 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2780 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2782 /* For the earlier insns, determine which of the subsequent ones they
2784 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2785 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2786 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2787 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2788 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2790 /* Ensure that I3's pattern can be the destination of combines. */
2791 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2792 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2793 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2794 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2801 /* See if any of the insns is a MULT operation. Unless one is, we will
2802 reject a combination that is, since it must be slower. Be conservative
2804 if (GET_CODE (i2src
) == MULT
2805 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2806 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2807 || (GET_CODE (PATTERN (i3
)) == SET
2808 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2811 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2812 We used to do this EXCEPT in one case: I3 has a post-inc in an
2813 output operand. However, that exception can give rise to insns like
2815 which is a famous insn on the PDP-11 where the value of r3 used as the
2816 source was model-dependent. Avoid this sort of thing. */
2819 if (!(GET_CODE (PATTERN (i3
)) == SET
2820 && REG_P (SET_SRC (PATTERN (i3
)))
2821 && MEM_P (SET_DEST (PATTERN (i3
)))
2822 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2823 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2824 /* It's not the exception. */
2829 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2830 if (REG_NOTE_KIND (link
) == REG_INC
2831 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2833 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2841 /* See if the SETs in I1 or I2 need to be kept around in the merged
2842 instruction: whenever the value set there is still needed past I3.
2843 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2845 For the SET in I1, we have two cases: if I1 and I2 independently feed
2846 into I3, the set in I1 needs to be kept around unless I1DEST dies
2847 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2848 in I1 needs to be kept around unless I1DEST dies or is set in either
2849 I2 or I3. The same considerations apply to I0. */
2851 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2854 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2855 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2860 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2861 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2862 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2863 && dead_or_set_p (i2
, i0dest
)));
2867 /* We are about to copy insns for the case where they need to be kept
2868 around. Check that they can be copied in the merged instruction. */
2870 if (targetm
.cannot_copy_insn_p
2871 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2872 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2873 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2879 /* If the set in I2 needs to be kept around, we must make a copy of
2880 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2881 PATTERN (I2), we are only substituting for the original I1DEST, not into
2882 an already-substituted copy. This also prevents making self-referential
2883 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2888 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2889 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2891 i2pat
= copy_rtx (PATTERN (i2
));
2896 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2897 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2899 i1pat
= copy_rtx (PATTERN (i1
));
2904 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2905 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2907 i0pat
= copy_rtx (PATTERN (i0
));
2912 /* Substitute in the latest insn for the regs set by the earlier ones. */
2914 maxreg
= max_reg_num ();
2919 /* Many machines that don't use CC0 have insns that can both perform an
2920 arithmetic operation and set the condition code. These operations will
2921 be represented as a PARALLEL with the first element of the vector
2922 being a COMPARE of an arithmetic operation with the constant zero.
2923 The second element of the vector will set some pseudo to the result
2924 of the same arithmetic operation. If we simplify the COMPARE, we won't
2925 match such a pattern and so will generate an extra insn. Here we test
2926 for this case, where both the comparison and the operation result are
2927 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2928 I2SRC. Later we will make the PARALLEL that contains I2. */
2930 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2931 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2932 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2933 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2936 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
2937 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2938 enum machine_mode compare_mode
, orig_compare_mode
;
2939 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2941 newpat
= PATTERN (i3
);
2942 newpat_dest
= SET_DEST (newpat
);
2943 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2945 if (undobuf
.other_insn
== 0
2946 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2949 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2950 compare_code
= simplify_compare_const (compare_code
,
2952 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2955 /* Do the rest only if op1 is const0_rtx, which may be the
2956 result of simplification. */
2957 if (op1
== const0_rtx
)
2959 /* If a single use of the CC is found, prepare to modify it
2960 when SELECT_CC_MODE returns a new CC-class mode, or when
2961 the above simplify_compare_const() returned a new comparison
2962 operator. undobuf.other_insn is assigned the CC use insn
2963 when modifying it. */
2966 #ifdef SELECT_CC_MODE
2967 enum machine_mode new_mode
2968 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2969 if (new_mode
!= orig_compare_mode
2970 && can_change_dest_mode (SET_DEST (newpat
),
2971 added_sets_2
, new_mode
))
2973 unsigned int regno
= REGNO (newpat_dest
);
2974 compare_mode
= new_mode
;
2975 if (regno
< FIRST_PSEUDO_REGISTER
)
2976 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
2979 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2980 newpat_dest
= regno_reg_rtx
[regno
];
2984 /* Cases for modifying the CC-using comparison. */
2985 if (compare_code
!= orig_compare_code
2986 /* ??? Do we need to verify the zero rtx? */
2987 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
2989 /* Replace cc_use_loc with entire new RTX. */
2991 gen_rtx_fmt_ee (compare_code
, compare_mode
,
2992 newpat_dest
, const0_rtx
));
2993 undobuf
.other_insn
= cc_use_insn
;
2995 else if (compare_mode
!= orig_compare_mode
)
2997 /* Just replace the CC reg with a new mode. */
2998 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
2999 undobuf
.other_insn
= cc_use_insn
;
3003 /* Now we modify the current newpat:
3004 First, SET_DEST(newpat) is updated if the CC mode has been
3005 altered. For targets without SELECT_CC_MODE, this should be
3007 if (compare_mode
!= orig_compare_mode
)
3008 SUBST (SET_DEST (newpat
), newpat_dest
);
3009 /* This is always done to propagate i2src into newpat. */
3010 SUBST (SET_SRC (newpat
),
3011 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3012 /* Create new version of i2pat if needed; the below PARALLEL
3013 creation needs this to work correctly. */
3014 if (! rtx_equal_p (i2src
, op0
))
3015 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3021 if (i2_is_used
== 0)
3023 /* It is possible that the source of I2 or I1 may be performing
3024 an unneeded operation, such as a ZERO_EXTEND of something
3025 that is known to have the high part zero. Handle that case
3026 by letting subst look at the inner insns.
3028 Another way to do this would be to have a function that tries
3029 to simplify a single insn instead of merging two or more
3030 insns. We don't do this because of the potential of infinite
3031 loops and because of the potential extra memory required.
3032 However, doing it the way we are is a bit of a kludge and
3033 doesn't catch all cases.
3035 But only do this if -fexpensive-optimizations since it slows
3036 things down and doesn't usually win.
3038 This is not done in the COMPARE case above because the
3039 unmodified I2PAT is used in the PARALLEL and so a pattern
3040 with a modified I2SRC would not match. */
3042 if (flag_expensive_optimizations
)
3044 /* Pass pc_rtx so no substitutions are done, just
3048 subst_low_luid
= DF_INSN_LUID (i1
);
3049 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3052 subst_low_luid
= DF_INSN_LUID (i2
);
3053 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3056 n_occurrences
= 0; /* `subst' counts here */
3057 subst_low_luid
= DF_INSN_LUID (i2
);
3059 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3060 copy of I2SRC each time we substitute it, in order to avoid creating
3061 self-referential RTL when we will be substituting I1SRC for I1DEST
3062 later. Likewise if I0 feeds into I2, either directly or indirectly
3063 through I1, and I0DEST is in I0SRC. */
3064 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3065 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3066 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3067 && i0dest_in_i0src
));
3070 /* Record whether I2's body now appears within I3's body. */
3071 i2_is_used
= n_occurrences
;
3074 /* If we already got a failure, don't try to do more. Otherwise, try to
3075 substitute I1 if we have it. */
3077 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3079 /* Check that an autoincrement side-effect on I1 has not been lost.
3080 This happens if I1DEST is mentioned in I2 and dies there, and
3081 has disappeared from the new pattern. */
3082 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3084 && dead_or_set_p (i2
, i1dest
)
3085 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3086 /* Before we can do this substitution, we must redo the test done
3087 above (see detailed comments there) that ensures I1DEST isn't
3088 mentioned in any SETs in NEWPAT that are field assignments. */
3089 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3097 subst_low_luid
= DF_INSN_LUID (i1
);
3099 /* If the following substitution will modify I1SRC, make a copy of it
3100 for the case where it is substituted for I1DEST in I2PAT later. */
3101 if (added_sets_2
&& i1_feeds_i2_n
)
3102 i1src_copy
= copy_rtx (i1src
);
3104 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3105 copy of I1SRC each time we substitute it, in order to avoid creating
3106 self-referential RTL when we will be substituting I0SRC for I0DEST
3108 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3109 i0_feeds_i1_n
&& i0dest_in_i0src
);
3112 /* Record whether I1's body now appears within I3's body. */
3113 i1_is_used
= n_occurrences
;
3116 /* Likewise for I0 if we have it. */
3118 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3120 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3121 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3122 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3123 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3124 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3131 /* If the following substitution will modify I0SRC, make a copy of it
3132 for the case where it is substituted for I0DEST in I1PAT later. */
3133 if (added_sets_1
&& i0_feeds_i1_n
)
3134 i0src_copy
= copy_rtx (i0src
);
3135 /* And a copy for I0DEST in I2PAT substitution. */
3136 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3137 || (i0_feeds_i2_n
)))
3138 i0src_copy2
= copy_rtx (i0src
);
3141 subst_low_luid
= DF_INSN_LUID (i0
);
3142 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3146 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3147 to count all the ways that I2SRC and I1SRC can be used. */
3148 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3149 && i2_is_used
+ added_sets_2
> 1)
3150 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3151 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3153 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3154 && (n_occurrences
+ added_sets_0
3155 + (added_sets_1
&& i0_feeds_i1_n
)
3156 + (added_sets_2
&& i0_feeds_i2_n
)
3158 /* Fail if we tried to make a new register. */
3159 || max_reg_num () != maxreg
3160 /* Fail if we couldn't do something and have a CLOBBER. */
3161 || GET_CODE (newpat
) == CLOBBER
3162 /* Fail if this new pattern is a MULT and we didn't have one before
3163 at the outer level. */
3164 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3171 /* If the actions of the earlier insns must be kept
3172 in addition to substituting them into the latest one,
3173 we must make a new PARALLEL for the latest insn
3174 to hold additional the SETs. */
3176 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3178 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3181 if (GET_CODE (newpat
) == PARALLEL
)
3183 rtvec old
= XVEC (newpat
, 0);
3184 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3185 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3186 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3187 sizeof (old
->elem
[0]) * old
->num_elem
);
3192 total_sets
= 1 + extra_sets
;
3193 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3194 XVECEXP (newpat
, 0, 0) = old
;
3198 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3204 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3206 XVECEXP (newpat
, 0, --total_sets
) = t
;
3212 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3213 i0_feeds_i1_n
&& i0dest_in_i0src
);
3214 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3215 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3217 XVECEXP (newpat
, 0, --total_sets
) = t
;
3221 validate_replacement
:
3223 /* Note which hard regs this insn has as inputs. */
3224 mark_used_regs_combine (newpat
);
3226 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3227 consider splitting this pattern, we might need these clobbers. */
3228 if (i1
&& GET_CODE (newpat
) == PARALLEL
3229 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3231 int len
= XVECLEN (newpat
, 0);
3233 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3234 for (i
= 0; i
< len
; i
++)
3235 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3238 /* Is the result of combination a valid instruction? */
3239 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3241 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242 the second SET's destination is a register that is unused and isn't
3243 marked as an instruction that might trap in an EH region. In that case,
3244 we just need the first SET. This can occur when simplifying a divmod
3245 insn. We *must* test for this case here because the code below that
3246 splits two independent SETs doesn't handle this case correctly when it
3247 updates the register status.
3249 It's pointless doing this if we originally had two sets, one from
3250 i3, and one from i2. Combining then splitting the parallel results
3251 in the original i2 again plus an invalid insn (which we delete).
3252 The net effect is only to move instructions around, which makes
3253 debug info less accurate.
3255 Also check the case where the first SET's destination is unused.
3256 That would not cause incorrect code, but does cause an unneeded
3259 if (insn_code_number
< 0
3260 && !(added_sets_2
&& i1
== 0)
3261 && GET_CODE (newpat
) == PARALLEL
3262 && XVECLEN (newpat
, 0) == 2
3263 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3264 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3265 && asm_noperands (newpat
) < 0)
3267 rtx set0
= XVECEXP (newpat
, 0, 0);
3268 rtx set1
= XVECEXP (newpat
, 0, 1);
3270 if (((REG_P (SET_DEST (set1
))
3271 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3272 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3273 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3274 && insn_nothrow_p (i3
)
3275 && !side_effects_p (SET_SRC (set1
)))
3278 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3281 else if (((REG_P (SET_DEST (set0
))
3282 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3283 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3284 && find_reg_note (i3
, REG_UNUSED
,
3285 SUBREG_REG (SET_DEST (set0
)))))
3286 && insn_nothrow_p (i3
)
3287 && !side_effects_p (SET_SRC (set0
)))
3290 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3292 if (insn_code_number
>= 0)
3293 changed_i3_dest
= 1;
3297 /* If we were combining three insns and the result is a simple SET
3298 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299 insns. There are two ways to do this. It can be split using a
3300 machine-specific method (like when you have an addition of a large
3301 constant) or by combine in the function find_split_point. */
3303 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3304 && asm_noperands (newpat
) < 0)
3306 rtx parallel
, m_split
, *split
;
3308 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3309 use I2DEST as a scratch register will help. In the latter case,
3310 convert I2DEST to the mode of the source of NEWPAT if we can. */
3312 m_split
= combine_split_insns (newpat
, i3
);
3314 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315 inputs of NEWPAT. */
3317 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318 possible to try that as a scratch reg. This would require adding
3319 more code to make it work though. */
3321 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3323 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3325 /* First try to split using the original register as a
3326 scratch register. */
3327 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3328 gen_rtvec (2, newpat
,
3329 gen_rtx_CLOBBER (VOIDmode
,
3331 m_split
= combine_split_insns (parallel
, i3
);
3333 /* If that didn't work, try changing the mode of I2DEST if
3336 && new_mode
!= GET_MODE (i2dest
)
3337 && new_mode
!= VOIDmode
3338 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3340 enum machine_mode old_mode
= GET_MODE (i2dest
);
3343 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3344 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3347 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3348 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3351 parallel
= (gen_rtx_PARALLEL
3353 gen_rtvec (2, newpat
,
3354 gen_rtx_CLOBBER (VOIDmode
,
3356 m_split
= combine_split_insns (parallel
, i3
);
3359 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3363 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3364 buf
= undobuf
.undos
;
3365 undobuf
.undos
= buf
->next
;
3366 buf
->next
= undobuf
.frees
;
3367 undobuf
.frees
= buf
;
3371 i2scratch
= m_split
!= 0;
3374 /* If recog_for_combine has discarded clobbers, try to use them
3375 again for the split. */
3376 if (m_split
== 0 && newpat_vec_with_clobbers
)
3378 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3379 m_split
= combine_split_insns (parallel
, i3
);
3382 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3384 m_split
= PATTERN (m_split
);
3385 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3386 if (insn_code_number
>= 0)
3389 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3390 && (next_nonnote_nondebug_insn (i2
) == i3
3391 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3394 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3395 newi2pat
= PATTERN (m_split
);
3397 i3set
= single_set (NEXT_INSN (m_split
));
3398 i2set
= single_set (m_split
);
3400 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3402 /* If I2 or I3 has multiple SETs, we won't know how to track
3403 register status, so don't use these insns. If I2's destination
3404 is used between I2 and I3, we also can't use these insns. */
3406 if (i2_code_number
>= 0 && i2set
&& i3set
3407 && (next_nonnote_nondebug_insn (i2
) == i3
3408 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3409 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3411 if (insn_code_number
>= 0)
3414 /* It is possible that both insns now set the destination of I3.
3415 If so, we must show an extra use of it. */
3417 if (insn_code_number
>= 0)
3419 rtx new_i3_dest
= SET_DEST (i3set
);
3420 rtx new_i2_dest
= SET_DEST (i2set
);
3422 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3423 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3424 || GET_CODE (new_i3_dest
) == SUBREG
)
3425 new_i3_dest
= XEXP (new_i3_dest
, 0);
3427 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3428 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3429 || GET_CODE (new_i2_dest
) == SUBREG
)
3430 new_i2_dest
= XEXP (new_i2_dest
, 0);
3432 if (REG_P (new_i3_dest
)
3433 && REG_P (new_i2_dest
)
3434 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3435 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3439 /* If we can split it and use I2DEST, go ahead and see if that
3440 helps things be recognized. Verify that none of the registers
3441 are set between I2 and I3. */
3442 if (insn_code_number
< 0
3443 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3447 /* We need I2DEST in the proper mode. If it is a hard register
3448 or the only use of a pseudo, we can change its mode.
3449 Make sure we don't change a hard register to have a mode that
3450 isn't valid for it, or change the number of registers. */
3451 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3452 || GET_MODE (*split
) == VOIDmode
3453 || can_change_dest_mode (i2dest
, added_sets_2
,
3455 && (next_nonnote_nondebug_insn (i2
) == i3
3456 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3457 /* We can't overwrite I2DEST if its value is still used by
3459 && ! reg_referenced_p (i2dest
, newpat
))
3461 rtx newdest
= i2dest
;
3462 enum rtx_code split_code
= GET_CODE (*split
);
3463 enum machine_mode split_mode
= GET_MODE (*split
);
3464 bool subst_done
= false;
3465 newi2pat
= NULL_RTX
;
3469 /* *SPLIT may be part of I2SRC, so make sure we have the
3470 original expression around for later debug processing.
3471 We should not need I2SRC any more in other cases. */
3472 if (MAY_HAVE_DEBUG_INSNS
)
3473 i2src
= copy_rtx (i2src
);
3477 /* Get NEWDEST as a register in the proper mode. We have already
3478 validated that we can do this. */
3479 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3481 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3482 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3485 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3486 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3490 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491 an ASHIFT. This can occur if it was inside a PLUS and hence
3492 appeared to be a memory address. This is a kludge. */
3493 if (split_code
== MULT
3494 && CONST_INT_P (XEXP (*split
, 1))
3495 && INTVAL (XEXP (*split
, 1)) > 0
3496 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3498 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3499 XEXP (*split
, 0), GEN_INT (i
)));
3500 /* Update split_code because we may not have a multiply
3502 split_code
= GET_CODE (*split
);
3505 #ifdef INSN_SCHEDULING
3506 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507 be written as a ZERO_EXTEND. */
3508 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3510 #ifdef LOAD_EXTEND_OP
3511 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512 what it really is. */
3513 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3515 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3516 SUBREG_REG (*split
)));
3519 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3520 SUBREG_REG (*split
)));
3524 /* Attempt to split binary operators using arithmetic identities. */
3525 if (BINARY_P (SET_SRC (newpat
))
3526 && split_mode
== GET_MODE (SET_SRC (newpat
))
3527 && ! side_effects_p (SET_SRC (newpat
)))
3529 rtx setsrc
= SET_SRC (newpat
);
3530 enum machine_mode mode
= GET_MODE (setsrc
);
3531 enum rtx_code code
= GET_CODE (setsrc
);
3532 rtx src_op0
= XEXP (setsrc
, 0);
3533 rtx src_op1
= XEXP (setsrc
, 1);
3535 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3536 if (rtx_equal_p (src_op0
, src_op1
))
3538 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3539 SUBST (XEXP (setsrc
, 0), newdest
);
3540 SUBST (XEXP (setsrc
, 1), newdest
);
3543 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3544 else if ((code
== PLUS
|| code
== MULT
)
3545 && GET_CODE (src_op0
) == code
3546 && GET_CODE (XEXP (src_op0
, 0)) == code
3547 && (INTEGRAL_MODE_P (mode
)
3548 || (FLOAT_MODE_P (mode
)
3549 && flag_unsafe_math_optimizations
)))
3551 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3552 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3553 rtx r
= XEXP (src_op0
, 1);
3556 /* Split both "((X op Y) op X) op Y" and
3557 "((X op Y) op Y) op X" as "T op T" where T is
3559 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3560 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3562 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3564 SUBST (XEXP (setsrc
, 0), newdest
);
3565 SUBST (XEXP (setsrc
, 1), newdest
);
3568 /* Split "((X op X) op Y) op Y)" as "T op T" where
3570 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3572 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3573 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3574 SUBST (XEXP (setsrc
, 0), newdest
);
3575 SUBST (XEXP (setsrc
, 1), newdest
);
3583 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3584 SUBST (*split
, newdest
);
3587 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3589 /* recog_for_combine might have added CLOBBERs to newi2pat.
3590 Make sure NEWPAT does not depend on the clobbered regs. */
3591 if (GET_CODE (newi2pat
) == PARALLEL
)
3592 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3593 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3595 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3596 if (reg_overlap_mentioned_p (reg
, newpat
))
3603 /* If the split point was a MULT and we didn't have one before,
3604 don't use one now. */
3605 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3606 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3610 /* Check for a case where we loaded from memory in a narrow mode and
3611 then sign extended it, but we need both registers. In that case,
3612 we have a PARALLEL with both loads from the same memory location.
3613 We can split this into a load from memory followed by a register-register
3614 copy. This saves at least one insn, more if register allocation can
3617 We cannot do this if the destination of the first assignment is a
3618 condition code register or cc0. We eliminate this case by making sure
3619 the SET_DEST and SET_SRC have the same mode.
3621 We cannot do this if the destination of the second assignment is
3622 a register that we have already assumed is zero-extended. Similarly
3623 for a SUBREG of such a register. */
3625 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3626 && GET_CODE (newpat
) == PARALLEL
3627 && XVECLEN (newpat
, 0) == 2
3628 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3629 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3630 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3631 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3632 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3633 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3634 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3635 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3637 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3638 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3639 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3641 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3642 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3643 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3644 && (reg_stat
[REGNO (temp
)].nonzero_bits
3645 != GET_MODE_MASK (word_mode
))))
3646 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3647 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3649 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3650 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3651 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3652 && (reg_stat
[REGNO (temp
)].nonzero_bits
3653 != GET_MODE_MASK (word_mode
)))))
3654 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3655 SET_SRC (XVECEXP (newpat
, 0, 1)))
3656 && ! find_reg_note (i3
, REG_UNUSED
,
3657 SET_DEST (XVECEXP (newpat
, 0, 0))))
3661 newi2pat
= XVECEXP (newpat
, 0, 0);
3662 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3663 newpat
= XVECEXP (newpat
, 0, 1);
3664 SUBST (SET_SRC (newpat
),
3665 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3666 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3668 if (i2_code_number
>= 0)
3669 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3671 if (insn_code_number
>= 0)
3675 /* Similarly, check for a case where we have a PARALLEL of two independent
3676 SETs but we started with three insns. In this case, we can do the sets
3677 as two separate insns. This case occurs when some SET allows two
3678 other insns to combine, but the destination of that SET is still live. */
3680 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3681 && GET_CODE (newpat
) == PARALLEL
3682 && XVECLEN (newpat
, 0) == 2
3683 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3684 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3685 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3686 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3687 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3688 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3689 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3690 XVECEXP (newpat
, 0, 0))
3691 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3692 XVECEXP (newpat
, 0, 1))
3693 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3694 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3696 /* Normally, it doesn't matter which of the two is done first,
3697 but the one that references cc0 can't be the second, and
3698 one which uses any regs/memory set in between i2 and i3 can't
3700 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3703 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3707 newi2pat
= XVECEXP (newpat
, 0, 1);
3708 newpat
= XVECEXP (newpat
, 0, 0);
3710 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3713 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3717 newi2pat
= XVECEXP (newpat
, 0, 0);
3718 newpat
= XVECEXP (newpat
, 0, 1);
3726 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3728 if (i2_code_number
>= 0)
3730 /* recog_for_combine might have added CLOBBERs to newi2pat.
3731 Make sure NEWPAT does not depend on the clobbered regs. */
3732 if (GET_CODE (newi2pat
) == PARALLEL
)
3734 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3735 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3737 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3738 if (reg_overlap_mentioned_p (reg
, newpat
))
3746 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3750 /* If it still isn't recognized, fail and change things back the way they
3752 if ((insn_code_number
< 0
3753 /* Is the result a reasonable ASM_OPERANDS? */
3754 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3760 /* If we had to change another insn, make sure it is valid also. */
3761 if (undobuf
.other_insn
)
3763 CLEAR_HARD_REG_SET (newpat_used_regs
);
3765 other_pat
= PATTERN (undobuf
.other_insn
);
3766 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3769 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3777 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3778 they are adjacent to each other or not. */
3780 rtx p
= prev_nonnote_insn (i3
);
3781 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3782 && sets_cc0_p (newi2pat
))
3790 /* Only allow this combination if insn_rtx_costs reports that the
3791 replacement instructions are cheaper than the originals. */
3792 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3798 if (MAY_HAVE_DEBUG_INSNS
)
3802 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3803 if (undo
->kind
== UNDO_MODE
)
3805 rtx reg
= *undo
->where
.r
;
3806 enum machine_mode new_mode
= GET_MODE (reg
);
3807 enum machine_mode old_mode
= undo
->old_contents
.m
;
3809 /* Temporarily revert mode back. */
3810 adjust_reg_mode (reg
, old_mode
);
3812 if (reg
== i2dest
&& i2scratch
)
3814 /* If we used i2dest as a scratch register with a
3815 different mode, substitute it for the original
3816 i2src while its original mode is temporarily
3817 restored, and then clear i2scratch so that we don't
3818 do it again later. */
3819 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3822 /* Put back the new mode. */
3823 adjust_reg_mode (reg
, new_mode
);
3827 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3833 last
= last_combined_insn
;
3838 last
= undobuf
.other_insn
;
3840 if (DF_INSN_LUID (last
)
3841 < DF_INSN_LUID (last_combined_insn
))
3842 last
= last_combined_insn
;
3845 /* We're dealing with a reg that changed mode but not
3846 meaning, so we want to turn it into a subreg for
3847 the new mode. However, because of REG sharing and
3848 because its mode had already changed, we have to do
3849 it in two steps. First, replace any debug uses of
3850 reg, with its original mode temporarily restored,
3851 with this copy we have created; then, replace the
3852 copy with the SUBREG of the original shared reg,
3853 once again changed to the new mode. */
3854 propagate_for_debug (first
, last
, reg
, tempreg
,
3856 adjust_reg_mode (reg
, new_mode
);
3857 propagate_for_debug (first
, last
, tempreg
,
3858 lowpart_subreg (old_mode
, reg
, new_mode
),
3864 /* If we will be able to accept this, we have made a
3865 change to the destination of I3. This requires us to
3866 do a few adjustments. */
3868 if (changed_i3_dest
)
3870 PATTERN (i3
) = newpat
;
3871 adjust_for_new_dest (i3
);
3874 /* We now know that we can do this combination. Merge the insns and
3875 update the status of registers and LOG_LINKS. */
3877 if (undobuf
.other_insn
)
3881 PATTERN (undobuf
.other_insn
) = other_pat
;
3883 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3884 are still valid. Then add any non-duplicate notes added by
3885 recog_for_combine. */
3886 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3888 next
= XEXP (note
, 1);
3890 if (REG_NOTE_KIND (note
) == REG_UNUSED
3891 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3892 remove_note (undobuf
.other_insn
, note
);
3895 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3896 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3903 struct insn_link
*link
;
3906 /* I3 now uses what used to be its destination and which is now
3907 I2's destination. This requires us to do a few adjustments. */
3908 PATTERN (i3
) = newpat
;
3909 adjust_for_new_dest (i3
);
3911 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3914 However, some later insn might be using I2's dest and have
3915 a LOG_LINK pointing at I3. We must remove this link.
3916 The simplest way to remove the link is to point it at I1,
3917 which we know will be a NOTE. */
3919 /* newi2pat is usually a SET here; however, recog_for_combine might
3920 have added some clobbers. */
3921 if (GET_CODE (newi2pat
) == PARALLEL
)
3922 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3924 ni2dest
= SET_DEST (newi2pat
);
3926 for (insn
= NEXT_INSN (i3
);
3927 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3928 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3929 insn
= NEXT_INSN (insn
))
3931 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3933 FOR_EACH_LOG_LINK (link
, insn
)
3934 if (link
->insn
== i3
)
3943 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3944 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
3947 /* Compute which registers we expect to eliminate. newi2pat may be setting
3948 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3949 same as i3dest, in which case newi2pat may be setting i1dest. */
3950 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3951 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3954 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3955 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3958 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3959 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3963 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3965 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3966 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3968 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3970 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3972 /* Ensure that we do not have something that should not be shared but
3973 occurs multiple times in the new insns. Check this by first
3974 resetting all the `used' flags and then copying anything is shared. */
3976 reset_used_flags (i3notes
);
3977 reset_used_flags (i2notes
);
3978 reset_used_flags (i1notes
);
3979 reset_used_flags (i0notes
);
3980 reset_used_flags (newpat
);
3981 reset_used_flags (newi2pat
);
3982 if (undobuf
.other_insn
)
3983 reset_used_flags (PATTERN (undobuf
.other_insn
));
3985 i3notes
= copy_rtx_if_shared (i3notes
);
3986 i2notes
= copy_rtx_if_shared (i2notes
);
3987 i1notes
= copy_rtx_if_shared (i1notes
);
3988 i0notes
= copy_rtx_if_shared (i0notes
);
3989 newpat
= copy_rtx_if_shared (newpat
);
3990 newi2pat
= copy_rtx_if_shared (newi2pat
);
3991 if (undobuf
.other_insn
)
3992 reset_used_flags (PATTERN (undobuf
.other_insn
));
3994 INSN_CODE (i3
) = insn_code_number
;
3995 PATTERN (i3
) = newpat
;
3997 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3999 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4001 reset_used_flags (call_usage
);
4002 call_usage
= copy_rtx (call_usage
);
4006 /* I2SRC must still be meaningful at this point. Some splitting
4007 operations can invalidate I2SRC, but those operations do not
4010 replace_rtx (call_usage
, i2dest
, i2src
);
4014 replace_rtx (call_usage
, i1dest
, i1src
);
4016 replace_rtx (call_usage
, i0dest
, i0src
);
4018 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4021 if (undobuf
.other_insn
)
4022 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4024 /* We had one special case above where I2 had more than one set and
4025 we replaced a destination of one of those sets with the destination
4026 of I3. In that case, we have to update LOG_LINKS of insns later
4027 in this basic block. Note that this (expensive) case is rare.
4029 Also, in this case, we must pretend that all REG_NOTEs for I2
4030 actually came from I3, so that REG_UNUSED notes from I2 will be
4031 properly handled. */
4033 if (i3_subst_into_i2
)
4035 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4036 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4037 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4038 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4039 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4040 && ! find_reg_note (i2
, REG_UNUSED
,
4041 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4042 for (temp
= NEXT_INSN (i2
);
4043 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4044 || BB_HEAD (this_basic_block
) != temp
);
4045 temp
= NEXT_INSN (temp
))
4046 if (temp
!= i3
&& INSN_P (temp
))
4047 FOR_EACH_LOG_LINK (link
, temp
)
4048 if (link
->insn
== i2
)
4054 while (XEXP (link
, 1))
4055 link
= XEXP (link
, 1);
4056 XEXP (link
, 1) = i2notes
;
4063 LOG_LINKS (i3
) = NULL
;
4065 LOG_LINKS (i2
) = NULL
;
4070 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4071 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4073 INSN_CODE (i2
) = i2_code_number
;
4074 PATTERN (i2
) = newi2pat
;
4078 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4079 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4081 SET_INSN_DELETED (i2
);
4086 LOG_LINKS (i1
) = NULL
;
4088 if (MAY_HAVE_DEBUG_INSNS
)
4089 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4091 SET_INSN_DELETED (i1
);
4096 LOG_LINKS (i0
) = NULL
;
4098 if (MAY_HAVE_DEBUG_INSNS
)
4099 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4101 SET_INSN_DELETED (i0
);
4104 /* Get death notes for everything that is now used in either I3 or
4105 I2 and used to die in a previous insn. If we built two new
4106 patterns, move from I1 to I2 then I2 to I3 so that we get the
4107 proper movement on registers that I2 modifies. */
4110 from_luid
= DF_INSN_LUID (i0
);
4112 from_luid
= DF_INSN_LUID (i1
);
4114 from_luid
= DF_INSN_LUID (i2
);
4116 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4117 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4119 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4121 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4122 elim_i2
, elim_i1
, elim_i0
);
4124 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4125 elim_i2
, elim_i1
, elim_i0
);
4127 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4128 elim_i2
, elim_i1
, elim_i0
);
4130 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4131 elim_i2
, elim_i1
, elim_i0
);
4133 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4134 elim_i2
, elim_i1
, elim_i0
);
4136 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4137 know these are REG_UNUSED and want them to go to the desired insn,
4138 so we always pass it as i3. */
4140 if (newi2pat
&& new_i2_notes
)
4141 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4145 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4148 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4149 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4150 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4151 in that case, it might delete I2. Similarly for I2 and I1.
4152 Show an additional death due to the REG_DEAD note we make here. If
4153 we discard it in distribute_notes, we will decrement it again. */
4157 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4158 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4159 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, elim_i2
,
4162 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4163 elim_i2
, elim_i1
, elim_i0
);
4166 if (i2dest_in_i2src
)
4168 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4169 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4170 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4171 NULL_RTX
, NULL_RTX
);
4173 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4174 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4177 if (i1dest_in_i1src
)
4179 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4180 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4181 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4182 NULL_RTX
, NULL_RTX
);
4184 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4185 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4188 if (i0dest_in_i0src
)
4190 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4191 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4192 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4193 NULL_RTX
, NULL_RTX
);
4195 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4196 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4199 distribute_links (i3links
);
4200 distribute_links (i2links
);
4201 distribute_links (i1links
);
4202 distribute_links (i0links
);
4206 struct insn_link
*link
;
4207 rtx i2_insn
= 0, i2_val
= 0, set
;
4209 /* The insn that used to set this register doesn't exist, and
4210 this life of the register may not exist either. See if one of
4211 I3's links points to an insn that sets I2DEST. If it does,
4212 that is now the last known value for I2DEST. If we don't update
4213 this and I2 set the register to a value that depended on its old
4214 contents, we will get confused. If this insn is used, thing
4215 will be set correctly in combine_instructions. */
4216 FOR_EACH_LOG_LINK (link
, i3
)
4217 if ((set
= single_set (link
->insn
)) != 0
4218 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4219 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4221 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4223 /* If the reg formerly set in I2 died only once and that was in I3,
4224 zero its use count so it won't make `reload' do any work. */
4226 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4227 && ! i2dest_in_i2src
)
4228 INC_REG_N_SETS (REGNO (i2dest
), -1);
4231 if (i1
&& REG_P (i1dest
))
4233 struct insn_link
*link
;
4234 rtx i1_insn
= 0, i1_val
= 0, set
;
4236 FOR_EACH_LOG_LINK (link
, i3
)
4237 if ((set
= single_set (link
->insn
)) != 0
4238 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4239 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4241 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4243 if (! added_sets_1
&& ! i1dest_in_i1src
)
4244 INC_REG_N_SETS (REGNO (i1dest
), -1);
4247 if (i0
&& REG_P (i0dest
))
4249 struct insn_link
*link
;
4250 rtx i0_insn
= 0, i0_val
= 0, set
;
4252 FOR_EACH_LOG_LINK (link
, i3
)
4253 if ((set
= single_set (link
->insn
)) != 0
4254 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4255 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4257 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4259 if (! added_sets_0
&& ! i0dest_in_i0src
)
4260 INC_REG_N_SETS (REGNO (i0dest
), -1);
4263 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4264 been made to this insn. The order of
4265 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4266 can affect nonzero_bits of newpat */
4268 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4269 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4272 if (undobuf
.other_insn
!= NULL_RTX
)
4276 fprintf (dump_file
, "modifying other_insn ");
4277 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4279 df_insn_rescan (undobuf
.other_insn
);
4282 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4286 fprintf (dump_file
, "modifying insn i1 ");
4287 dump_insn_slim (dump_file
, i0
);
4289 df_insn_rescan (i0
);
4292 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4296 fprintf (dump_file
, "modifying insn i1 ");
4297 dump_insn_slim (dump_file
, i1
);
4299 df_insn_rescan (i1
);
4302 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4306 fprintf (dump_file
, "modifying insn i2 ");
4307 dump_insn_slim (dump_file
, i2
);
4309 df_insn_rescan (i2
);
4312 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4316 fprintf (dump_file
, "modifying insn i3 ");
4317 dump_insn_slim (dump_file
, i3
);
4319 df_insn_rescan (i3
);
4322 /* Set new_direct_jump_p if a new return or simple jump instruction
4323 has been created. Adjust the CFG accordingly. */
4325 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4327 *new_direct_jump_p
= 1;
4328 mark_jump_label (PATTERN (i3
), i3
, 0);
4329 update_cfg_for_uncondjump (i3
);
4332 if (undobuf
.other_insn
!= NULL_RTX
4333 && (returnjump_p (undobuf
.other_insn
)
4334 || any_uncondjump_p (undobuf
.other_insn
)))
4336 *new_direct_jump_p
= 1;
4337 update_cfg_for_uncondjump (undobuf
.other_insn
);
4340 /* A noop might also need cleaning up of CFG, if it comes from the
4341 simplification of a jump. */
4343 && GET_CODE (newpat
) == SET
4344 && SET_SRC (newpat
) == pc_rtx
4345 && SET_DEST (newpat
) == pc_rtx
)
4347 *new_direct_jump_p
= 1;
4348 update_cfg_for_uncondjump (i3
);
4351 if (undobuf
.other_insn
!= NULL_RTX
4352 && JUMP_P (undobuf
.other_insn
)
4353 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4354 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4355 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4357 *new_direct_jump_p
= 1;
4358 update_cfg_for_uncondjump (undobuf
.other_insn
);
4361 combine_successes
++;
4364 if (added_links_insn
4365 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4366 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4367 return added_links_insn
;
4369 return newi2pat
? i2
: i3
;
4372 /* Undo all the modifications recorded in undobuf. */
4377 struct undo
*undo
, *next
;
4379 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4385 *undo
->where
.r
= undo
->old_contents
.r
;
4388 *undo
->where
.i
= undo
->old_contents
.i
;
4391 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4394 *undo
->where
.l
= undo
->old_contents
.l
;
4400 undo
->next
= undobuf
.frees
;
4401 undobuf
.frees
= undo
;
4407 /* We've committed to accepting the changes we made. Move all
4408 of the undos to the free list. */
4413 struct undo
*undo
, *next
;
4415 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4418 undo
->next
= undobuf
.frees
;
4419 undobuf
.frees
= undo
;
4424 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4425 where we have an arithmetic expression and return that point. LOC will
4428 try_combine will call this function to see if an insn can be split into
4432 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4435 enum rtx_code code
= GET_CODE (x
);
4437 unsigned HOST_WIDE_INT len
= 0;
4438 HOST_WIDE_INT pos
= 0;
4440 rtx inner
= NULL_RTX
;
4442 /* First special-case some codes. */
4446 #ifdef INSN_SCHEDULING
4447 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4449 if (MEM_P (SUBREG_REG (x
)))
4452 return find_split_point (&SUBREG_REG (x
), insn
, false);
4456 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4457 using LO_SUM and HIGH. */
4458 if (GET_CODE (XEXP (x
, 0)) == CONST
4459 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4461 enum machine_mode address_mode
= get_address_mode (x
);
4464 gen_rtx_LO_SUM (address_mode
,
4465 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4467 return &XEXP (XEXP (x
, 0), 0);
4471 /* If we have a PLUS whose second operand is a constant and the
4472 address is not valid, perhaps will can split it up using
4473 the machine-specific way to split large constants. We use
4474 the first pseudo-reg (one of the virtual regs) as a placeholder;
4475 it will not remain in the result. */
4476 if (GET_CODE (XEXP (x
, 0)) == PLUS
4477 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4478 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4479 MEM_ADDR_SPACE (x
)))
4481 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4482 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4486 /* This should have produced two insns, each of which sets our
4487 placeholder. If the source of the second is a valid address,
4488 we can make put both sources together and make a split point
4492 && NEXT_INSN (seq
) != NULL_RTX
4493 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4494 && NONJUMP_INSN_P (seq
)
4495 && GET_CODE (PATTERN (seq
)) == SET
4496 && SET_DEST (PATTERN (seq
)) == reg
4497 && ! reg_mentioned_p (reg
,
4498 SET_SRC (PATTERN (seq
)))
4499 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4500 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4501 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4502 && memory_address_addr_space_p
4503 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4504 MEM_ADDR_SPACE (x
)))
4506 rtx src1
= SET_SRC (PATTERN (seq
));
4507 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4509 /* Replace the placeholder in SRC2 with SRC1. If we can
4510 find where in SRC2 it was placed, that can become our
4511 split point and we can replace this address with SRC2.
4512 Just try two obvious places. */
4514 src2
= replace_rtx (src2
, reg
, src1
);
4516 if (XEXP (src2
, 0) == src1
)
4517 split
= &XEXP (src2
, 0);
4518 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4519 && XEXP (XEXP (src2
, 0), 0) == src1
)
4520 split
= &XEXP (XEXP (src2
, 0), 0);
4524 SUBST (XEXP (x
, 0), src2
);
4529 /* If that didn't work, perhaps the first operand is complex and
4530 needs to be computed separately, so make a split point there.
4531 This will occur on machines that just support REG + CONST
4532 and have a constant moved through some previous computation. */
4534 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4535 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4536 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4537 return &XEXP (XEXP (x
, 0), 0);
4540 /* If we have a PLUS whose first operand is complex, try computing it
4541 separately by making a split there. */
4542 if (GET_CODE (XEXP (x
, 0)) == PLUS
4543 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4545 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4546 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4547 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4548 return &XEXP (XEXP (x
, 0), 0);
4553 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4554 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4555 we need to put the operand into a register. So split at that
4558 if (SET_DEST (x
) == cc0_rtx
4559 && GET_CODE (SET_SRC (x
)) != COMPARE
4560 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4561 && !OBJECT_P (SET_SRC (x
))
4562 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4563 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4564 return &SET_SRC (x
);
4567 /* See if we can split SET_SRC as it stands. */
4568 split
= find_split_point (&SET_SRC (x
), insn
, true);
4569 if (split
&& split
!= &SET_SRC (x
))
4572 /* See if we can split SET_DEST as it stands. */
4573 split
= find_split_point (&SET_DEST (x
), insn
, false);
4574 if (split
&& split
!= &SET_DEST (x
))
4577 /* See if this is a bitfield assignment with everything constant. If
4578 so, this is an IOR of an AND, so split it into that. */
4579 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4580 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4581 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4582 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4583 && CONST_INT_P (SET_SRC (x
))
4584 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4585 + INTVAL (XEXP (SET_DEST (x
), 2)))
4586 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4587 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4589 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4590 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4591 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4592 rtx dest
= XEXP (SET_DEST (x
), 0);
4593 enum machine_mode mode
= GET_MODE (dest
);
4594 unsigned HOST_WIDE_INT mask
4595 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4598 if (BITS_BIG_ENDIAN
)
4599 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4601 or_mask
= gen_int_mode (src
<< pos
, mode
);
4604 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4607 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4609 simplify_gen_binary (IOR
, mode
,
4610 simplify_gen_binary (AND
, mode
,
4615 SUBST (SET_DEST (x
), dest
);
4617 split
= find_split_point (&SET_SRC (x
), insn
, true);
4618 if (split
&& split
!= &SET_SRC (x
))
4622 /* Otherwise, see if this is an operation that we can split into two.
4623 If so, try to split that. */
4624 code
= GET_CODE (SET_SRC (x
));
4629 /* If we are AND'ing with a large constant that is only a single
4630 bit and the result is only being used in a context where we
4631 need to know if it is zero or nonzero, replace it with a bit
4632 extraction. This will avoid the large constant, which might
4633 have taken more than one insn to make. If the constant were
4634 not a valid argument to the AND but took only one insn to make,
4635 this is no worse, but if it took more than one insn, it will
4638 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4639 && REG_P (XEXP (SET_SRC (x
), 0))
4640 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4641 && REG_P (SET_DEST (x
))
4642 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4643 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4644 && XEXP (*split
, 0) == SET_DEST (x
)
4645 && XEXP (*split
, 1) == const0_rtx
)
4647 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4648 XEXP (SET_SRC (x
), 0),
4649 pos
, NULL_RTX
, 1, 1, 0, 0);
4650 if (extraction
!= 0)
4652 SUBST (SET_SRC (x
), extraction
);
4653 return find_split_point (loc
, insn
, false);
4659 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4660 is known to be on, this can be converted into a NEG of a shift. */
4661 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4662 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4663 && 1 <= (pos
= exact_log2
4664 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4665 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4667 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4671 gen_rtx_LSHIFTRT (mode
,
4672 XEXP (SET_SRC (x
), 0),
4675 split
= find_split_point (&SET_SRC (x
), insn
, true);
4676 if (split
&& split
!= &SET_SRC (x
))
4682 inner
= XEXP (SET_SRC (x
), 0);
4684 /* We can't optimize if either mode is a partial integer
4685 mode as we don't know how many bits are significant
4687 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4688 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4692 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4698 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4699 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4701 inner
= XEXP (SET_SRC (x
), 0);
4702 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4703 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4705 if (BITS_BIG_ENDIAN
)
4706 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4707 unsignedp
= (code
== ZERO_EXTRACT
);
4716 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4718 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4720 /* For unsigned, we have a choice of a shift followed by an
4721 AND or two shifts. Use two shifts for field sizes where the
4722 constant might be too large. We assume here that we can
4723 always at least get 8-bit constants in an AND insn, which is
4724 true for every current RISC. */
4726 if (unsignedp
&& len
<= 8)
4728 unsigned HOST_WIDE_INT mask
4729 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4733 (mode
, gen_lowpart (mode
, inner
),
4735 gen_int_mode (mask
, mode
)));
4737 split
= find_split_point (&SET_SRC (x
), insn
, true);
4738 if (split
&& split
!= &SET_SRC (x
))
4745 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4746 gen_rtx_ASHIFT (mode
,
4747 gen_lowpart (mode
, inner
),
4748 GEN_INT (GET_MODE_PRECISION (mode
)
4750 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4752 split
= find_split_point (&SET_SRC (x
), insn
, true);
4753 if (split
&& split
!= &SET_SRC (x
))
4758 /* See if this is a simple operation with a constant as the second
4759 operand. It might be that this constant is out of range and hence
4760 could be used as a split point. */
4761 if (BINARY_P (SET_SRC (x
))
4762 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4763 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4764 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4765 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4766 return &XEXP (SET_SRC (x
), 1);
4768 /* Finally, see if this is a simple operation with its first operand
4769 not in a register. The operation might require this operand in a
4770 register, so return it as a split point. We can always do this
4771 because if the first operand were another operation, we would have
4772 already found it as a split point. */
4773 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4774 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4775 return &XEXP (SET_SRC (x
), 0);
4781 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4782 it is better to write this as (not (ior A B)) so we can split it.
4783 Similarly for IOR. */
4784 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4787 gen_rtx_NOT (GET_MODE (x
),
4788 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4790 XEXP (XEXP (x
, 0), 0),
4791 XEXP (XEXP (x
, 1), 0))));
4792 return find_split_point (loc
, insn
, set_src
);
4795 /* Many RISC machines have a large set of logical insns. If the
4796 second operand is a NOT, put it first so we will try to split the
4797 other operand first. */
4798 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4800 rtx tem
= XEXP (x
, 0);
4801 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4802 SUBST (XEXP (x
, 1), tem
);
4808 /* Canonicalization can produce (minus A (mult B C)), where C is a
4809 constant. It may be better to try splitting (plus (mult B -C) A)
4810 instead if this isn't a multiply by a power of two. */
4811 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4812 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4813 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4815 enum machine_mode mode
= GET_MODE (x
);
4816 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4817 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4818 SUBST (*loc
, gen_rtx_PLUS (mode
,
4820 XEXP (XEXP (x
, 1), 0),
4821 gen_int_mode (other_int
,
4824 return find_split_point (loc
, insn
, set_src
);
4827 /* Split at a multiply-accumulate instruction. However if this is
4828 the SET_SRC, we likely do not have such an instruction and it's
4829 worthless to try this split. */
4830 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4837 /* Otherwise, select our actions depending on our rtx class. */
4838 switch (GET_RTX_CLASS (code
))
4840 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4842 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4845 /* ... fall through ... */
4847 case RTX_COMM_ARITH
:
4849 case RTX_COMM_COMPARE
:
4850 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4853 /* ... fall through ... */
4855 /* Some machines have (and (shift ...) ...) insns. If X is not
4856 an AND, but XEXP (X, 0) is, use it as our split point. */
4857 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4858 return &XEXP (x
, 0);
4860 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4866 /* Otherwise, we don't have a split point. */
4871 /* Throughout X, replace FROM with TO, and return the result.
4872 The result is TO if X is FROM;
4873 otherwise the result is X, but its contents may have been modified.
4874 If they were modified, a record was made in undobuf so that
4875 undo_all will (among other things) return X to its original state.
4877 If the number of changes necessary is too much to record to undo,
4878 the excess changes are not made, so the result is invalid.
4879 The changes already made can still be undone.
4880 undobuf.num_undo is incremented for such changes, so by testing that
4881 the caller can tell whether the result is valid.
4883 `n_occurrences' is incremented each time FROM is replaced.
4885 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4887 IN_COND is nonzero if we are at the top level of a condition.
4889 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4890 by copying if `n_occurrences' is nonzero. */
4893 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4895 enum rtx_code code
= GET_CODE (x
);
4896 enum machine_mode op0_mode
= VOIDmode
;
4901 /* Two expressions are equal if they are identical copies of a shared
4902 RTX or if they are both registers with the same register number
4905 #define COMBINE_RTX_EQUAL_P(X,Y) \
4907 || (REG_P (X) && REG_P (Y) \
4908 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4910 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4913 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4916 /* If X and FROM are the same register but different modes, they
4917 will not have been seen as equal above. However, the log links code
4918 will make a LOG_LINKS entry for that case. If we do nothing, we
4919 will try to rerecognize our original insn and, when it succeeds,
4920 we will delete the feeding insn, which is incorrect.
4922 So force this insn not to match in this (rare) case. */
4923 if (! in_dest
&& code
== REG
&& REG_P (from
)
4924 && reg_overlap_mentioned_p (x
, from
))
4925 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4927 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4928 of which may contain things that can be combined. */
4929 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4932 /* It is possible to have a subexpression appear twice in the insn.
4933 Suppose that FROM is a register that appears within TO.
4934 Then, after that subexpression has been scanned once by `subst',
4935 the second time it is scanned, TO may be found. If we were
4936 to scan TO here, we would find FROM within it and create a
4937 self-referent rtl structure which is completely wrong. */
4938 if (COMBINE_RTX_EQUAL_P (x
, to
))
4941 /* Parallel asm_operands need special attention because all of the
4942 inputs are shared across the arms. Furthermore, unsharing the
4943 rtl results in recognition failures. Failure to handle this case
4944 specially can result in circular rtl.
4946 Solve this by doing a normal pass across the first entry of the
4947 parallel, and only processing the SET_DESTs of the subsequent
4950 if (code
== PARALLEL
4951 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4952 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4954 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
4956 /* If this substitution failed, this whole thing fails. */
4957 if (GET_CODE (new_rtx
) == CLOBBER
4958 && XEXP (new_rtx
, 0) == const0_rtx
)
4961 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4963 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4965 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4968 && GET_CODE (dest
) != CC0
4969 && GET_CODE (dest
) != PC
)
4971 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
4973 /* If this substitution failed, this whole thing fails. */
4974 if (GET_CODE (new_rtx
) == CLOBBER
4975 && XEXP (new_rtx
, 0) == const0_rtx
)
4978 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4984 len
= GET_RTX_LENGTH (code
);
4985 fmt
= GET_RTX_FORMAT (code
);
4987 /* We don't need to process a SET_DEST that is a register, CC0,
4988 or PC, so set up to skip this common case. All other cases
4989 where we want to suppress replacing something inside a
4990 SET_SRC are handled via the IN_DEST operand. */
4992 && (REG_P (SET_DEST (x
))
4993 || GET_CODE (SET_DEST (x
)) == CC0
4994 || GET_CODE (SET_DEST (x
)) == PC
))
4997 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5000 op0_mode
= GET_MODE (XEXP (x
, 0));
5002 for (i
= 0; i
< len
; i
++)
5007 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5009 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5011 new_rtx
= (unique_copy
&& n_occurrences
5012 ? copy_rtx (to
) : to
);
5017 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5020 /* If this substitution failed, this whole thing
5022 if (GET_CODE (new_rtx
) == CLOBBER
5023 && XEXP (new_rtx
, 0) == const0_rtx
)
5027 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5030 else if (fmt
[i
] == 'e')
5032 /* If this is a register being set, ignore it. */
5033 new_rtx
= XEXP (x
, i
);
5036 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5038 || code
== STRICT_LOW_PART
))
5041 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5043 /* In general, don't install a subreg involving two
5044 modes not tieable. It can worsen register
5045 allocation, and can even make invalid reload
5046 insns, since the reg inside may need to be copied
5047 from in the outside mode, and that may be invalid
5048 if it is an fp reg copied in integer mode.
5050 We allow two exceptions to this: It is valid if
5051 it is inside another SUBREG and the mode of that
5052 SUBREG and the mode of the inside of TO is
5053 tieable and it is valid if X is a SET that copies
5056 if (GET_CODE (to
) == SUBREG
5057 && ! MODES_TIEABLE_P (GET_MODE (to
),
5058 GET_MODE (SUBREG_REG (to
)))
5059 && ! (code
== SUBREG
5060 && MODES_TIEABLE_P (GET_MODE (x
),
5061 GET_MODE (SUBREG_REG (to
))))
5063 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5066 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5068 #ifdef CANNOT_CHANGE_MODE_CLASS
5071 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5072 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5075 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5078 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5082 /* If we are in a SET_DEST, suppress most cases unless we
5083 have gone inside a MEM, in which case we want to
5084 simplify the address. We assume here that things that
5085 are actually part of the destination have their inner
5086 parts in the first expression. This is true for SUBREG,
5087 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5088 things aside from REG and MEM that should appear in a
5090 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5092 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5093 || code
== ZERO_EXTRACT
))
5096 code
== IF_THEN_ELSE
&& i
== 0,
5099 /* If we found that we will have to reject this combination,
5100 indicate that by returning the CLOBBER ourselves, rather than
5101 an expression containing it. This will speed things up as
5102 well as prevent accidents where two CLOBBERs are considered
5103 to be equal, thus producing an incorrect simplification. */
5105 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5108 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5110 enum machine_mode mode
= GET_MODE (x
);
5112 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5113 GET_MODE (SUBREG_REG (x
)),
5116 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5118 else if (CONST_INT_P (new_rtx
)
5119 && GET_CODE (x
) == ZERO_EXTEND
)
5121 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5122 new_rtx
, GET_MODE (XEXP (x
, 0)));
5126 SUBST (XEXP (x
, i
), new_rtx
);
5131 /* Check if we are loading something from the constant pool via float
5132 extension; in this case we would undo compress_float_constant
5133 optimization and degenerate constant load to an immediate value. */
5134 if (GET_CODE (x
) == FLOAT_EXTEND
5135 && MEM_P (XEXP (x
, 0))
5136 && MEM_READONLY_P (XEXP (x
, 0)))
5138 rtx tmp
= avoid_constant_pool_reference (x
);
5143 /* Try to simplify X. If the simplification changed the code, it is likely
5144 that further simplification will help, so loop, but limit the number
5145 of repetitions that will be performed. */
5147 for (i
= 0; i
< 4; i
++)
5149 /* If X is sufficiently simple, don't bother trying to do anything
5151 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5152 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5154 if (GET_CODE (x
) == code
)
5157 code
= GET_CODE (x
);
5159 /* We no longer know the original mode of operand 0 since we
5160 have changed the form of X) */
5161 op0_mode
= VOIDmode
;
5167 /* Simplify X, a piece of RTL. We just operate on the expression at the
5168 outer level; call `subst' to simplify recursively. Return the new
5171 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5172 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5176 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5179 enum rtx_code code
= GET_CODE (x
);
5180 enum machine_mode mode
= GET_MODE (x
);
5184 /* If this is a commutative operation, put a constant last and a complex
5185 expression first. We don't need to do this for comparisons here. */
5186 if (COMMUTATIVE_ARITH_P (x
)
5187 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5190 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5191 SUBST (XEXP (x
, 1), temp
);
5194 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5195 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5196 things. Check for cases where both arms are testing the same
5199 Don't do anything if all operands are very simple. */
5202 && ((!OBJECT_P (XEXP (x
, 0))
5203 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5204 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5205 || (!OBJECT_P (XEXP (x
, 1))
5206 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5207 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5209 && (!OBJECT_P (XEXP (x
, 0))
5210 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5211 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5213 rtx cond
, true_rtx
, false_rtx
;
5215 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5217 /* If everything is a comparison, what we have is highly unlikely
5218 to be simpler, so don't use it. */
5219 && ! (COMPARISON_P (x
)
5220 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5222 rtx cop1
= const0_rtx
;
5223 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5225 if (cond_code
== NE
&& COMPARISON_P (cond
))
5228 /* Simplify the alternative arms; this may collapse the true and
5229 false arms to store-flag values. Be careful to use copy_rtx
5230 here since true_rtx or false_rtx might share RTL with x as a
5231 result of the if_then_else_cond call above. */
5232 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5233 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5235 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5236 is unlikely to be simpler. */
5237 if (general_operand (true_rtx
, VOIDmode
)
5238 && general_operand (false_rtx
, VOIDmode
))
5240 enum rtx_code reversed
;
5242 /* Restarting if we generate a store-flag expression will cause
5243 us to loop. Just drop through in this case. */
5245 /* If the result values are STORE_FLAG_VALUE and zero, we can
5246 just make the comparison operation. */
5247 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5248 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5250 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5251 && ((reversed
= reversed_comparison_code_parts
5252 (cond_code
, cond
, cop1
, NULL
))
5254 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5257 /* Likewise, we can make the negate of a comparison operation
5258 if the result values are - STORE_FLAG_VALUE and zero. */
5259 else if (CONST_INT_P (true_rtx
)
5260 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5261 && false_rtx
== const0_rtx
)
5262 x
= simplify_gen_unary (NEG
, mode
,
5263 simplify_gen_relational (cond_code
,
5267 else if (CONST_INT_P (false_rtx
)
5268 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5269 && true_rtx
== const0_rtx
5270 && ((reversed
= reversed_comparison_code_parts
5271 (cond_code
, cond
, cop1
, NULL
))
5273 x
= simplify_gen_unary (NEG
, mode
,
5274 simplify_gen_relational (reversed
,
5279 return gen_rtx_IF_THEN_ELSE (mode
,
5280 simplify_gen_relational (cond_code
,
5285 true_rtx
, false_rtx
);
5287 code
= GET_CODE (x
);
5288 op0_mode
= VOIDmode
;
5293 /* Try to fold this expression in case we have constants that weren't
5296 switch (GET_RTX_CLASS (code
))
5299 if (op0_mode
== VOIDmode
)
5300 op0_mode
= GET_MODE (XEXP (x
, 0));
5301 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5304 case RTX_COMM_COMPARE
:
5306 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5307 if (cmp_mode
== VOIDmode
)
5309 cmp_mode
= GET_MODE (XEXP (x
, 1));
5310 if (cmp_mode
== VOIDmode
)
5311 cmp_mode
= op0_mode
;
5313 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5314 XEXP (x
, 0), XEXP (x
, 1));
5317 case RTX_COMM_ARITH
:
5319 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5321 case RTX_BITFIELD_OPS
:
5323 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5324 XEXP (x
, 1), XEXP (x
, 2));
5333 code
= GET_CODE (temp
);
5334 op0_mode
= VOIDmode
;
5335 mode
= GET_MODE (temp
);
5338 /* First see if we can apply the inverse distributive law. */
5339 if (code
== PLUS
|| code
== MINUS
5340 || code
== AND
|| code
== IOR
|| code
== XOR
)
5342 x
= apply_distributive_law (x
);
5343 code
= GET_CODE (x
);
5344 op0_mode
= VOIDmode
;
5347 /* If CODE is an associative operation not otherwise handled, see if we
5348 can associate some operands. This can win if they are constants or
5349 if they are logically related (i.e. (a & b) & a). */
5350 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5351 || code
== AND
|| code
== IOR
|| code
== XOR
5352 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5353 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5354 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5356 if (GET_CODE (XEXP (x
, 0)) == code
)
5358 rtx other
= XEXP (XEXP (x
, 0), 0);
5359 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5360 rtx inner_op1
= XEXP (x
, 1);
5363 /* Make sure we pass the constant operand if any as the second
5364 one if this is a commutative operation. */
5365 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5367 rtx tem
= inner_op0
;
5368 inner_op0
= inner_op1
;
5371 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5372 : code
== DIV
? MULT
5374 mode
, inner_op0
, inner_op1
);
5376 /* For commutative operations, try the other pair if that one
5378 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5380 other
= XEXP (XEXP (x
, 0), 1);
5381 inner
= simplify_binary_operation (code
, mode
,
5382 XEXP (XEXP (x
, 0), 0),
5387 return simplify_gen_binary (code
, mode
, other
, inner
);
5391 /* A little bit of algebraic simplification here. */
5395 /* Ensure that our address has any ASHIFTs converted to MULT in case
5396 address-recognizing predicates are called later. */
5397 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5398 SUBST (XEXP (x
, 0), temp
);
5402 if (op0_mode
== VOIDmode
)
5403 op0_mode
= GET_MODE (SUBREG_REG (x
));
5405 /* See if this can be moved to simplify_subreg. */
5406 if (CONSTANT_P (SUBREG_REG (x
))
5407 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5408 /* Don't call gen_lowpart if the inner mode
5409 is VOIDmode and we cannot simplify it, as SUBREG without
5410 inner mode is invalid. */
5411 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5412 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5413 return gen_lowpart (mode
, SUBREG_REG (x
));
5415 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5419 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5424 /* If op is known to have all lower bits zero, the result is zero. */
5426 && SCALAR_INT_MODE_P (mode
)
5427 && SCALAR_INT_MODE_P (op0_mode
)
5428 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5429 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5430 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5431 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5432 & GET_MODE_MASK (mode
)) == 0)
5433 return CONST0_RTX (mode
);
5436 /* Don't change the mode of the MEM if that would change the meaning
5438 if (MEM_P (SUBREG_REG (x
))
5439 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5440 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5441 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5442 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5444 /* Note that we cannot do any narrowing for non-constants since
5445 we might have been counting on using the fact that some bits were
5446 zero. We now do this in the SET. */
5451 temp
= expand_compound_operation (XEXP (x
, 0));
5453 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5454 replaced by (lshiftrt X C). This will convert
5455 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5457 if (GET_CODE (temp
) == ASHIFTRT
5458 && CONST_INT_P (XEXP (temp
, 1))
5459 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5460 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5461 INTVAL (XEXP (temp
, 1)));
5463 /* If X has only a single bit that might be nonzero, say, bit I, convert
5464 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5465 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5466 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5467 or a SUBREG of one since we'd be making the expression more
5468 complex if it was just a register. */
5471 && ! (GET_CODE (temp
) == SUBREG
5472 && REG_P (SUBREG_REG (temp
)))
5473 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5475 rtx temp1
= simplify_shift_const
5476 (NULL_RTX
, ASHIFTRT
, mode
,
5477 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5478 GET_MODE_PRECISION (mode
) - 1 - i
),
5479 GET_MODE_PRECISION (mode
) - 1 - i
);
5481 /* If all we did was surround TEMP with the two shifts, we
5482 haven't improved anything, so don't use it. Otherwise,
5483 we are better off with TEMP1. */
5484 if (GET_CODE (temp1
) != ASHIFTRT
5485 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5486 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5492 /* We can't handle truncation to a partial integer mode here
5493 because we don't know the real bitsize of the partial
5495 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5498 if (HWI_COMPUTABLE_MODE_P (mode
))
5500 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5501 GET_MODE_MASK (mode
), 0));
5503 /* We can truncate a constant value and return it. */
5504 if (CONST_INT_P (XEXP (x
, 0)))
5505 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5507 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5508 whose value is a comparison can be replaced with a subreg if
5509 STORE_FLAG_VALUE permits. */
5510 if (HWI_COMPUTABLE_MODE_P (mode
)
5511 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5512 && (temp
= get_last_value (XEXP (x
, 0)))
5513 && COMPARISON_P (temp
))
5514 return gen_lowpart (mode
, XEXP (x
, 0));
5518 /* (const (const X)) can become (const X). Do it this way rather than
5519 returning the inner CONST since CONST can be shared with a
5521 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5522 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5527 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5528 can add in an offset. find_split_point will split this address up
5529 again if it doesn't match. */
5530 if (GET_CODE (XEXP (x
, 0)) == HIGH
5531 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5537 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5538 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5539 bit-field and can be replaced by either a sign_extend or a
5540 sign_extract. The `and' may be a zero_extend and the two
5541 <c>, -<c> constants may be reversed. */
5542 if (GET_CODE (XEXP (x
, 0)) == XOR
5543 && CONST_INT_P (XEXP (x
, 1))
5544 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5545 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5546 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5547 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5548 && HWI_COMPUTABLE_MODE_P (mode
)
5549 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5550 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5551 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5552 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5553 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5554 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5555 == (unsigned int) i
+ 1))))
5556 return simplify_shift_const
5557 (NULL_RTX
, ASHIFTRT
, mode
,
5558 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5559 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5560 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5561 GET_MODE_PRECISION (mode
) - (i
+ 1));
5563 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5564 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5565 the bitsize of the mode - 1. This allows simplification of
5566 "a = (b & 8) == 0;" */
5567 if (XEXP (x
, 1) == constm1_rtx
5568 && !REG_P (XEXP (x
, 0))
5569 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5570 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5571 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5572 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5573 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5574 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5575 GET_MODE_PRECISION (mode
) - 1),
5576 GET_MODE_PRECISION (mode
) - 1);
5578 /* If we are adding two things that have no bits in common, convert
5579 the addition into an IOR. This will often be further simplified,
5580 for example in cases like ((a & 1) + (a & 2)), which can
5583 if (HWI_COMPUTABLE_MODE_P (mode
)
5584 && (nonzero_bits (XEXP (x
, 0), mode
)
5585 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5587 /* Try to simplify the expression further. */
5588 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5589 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5591 /* If we could, great. If not, do not go ahead with the IOR
5592 replacement, since PLUS appears in many special purpose
5593 address arithmetic instructions. */
5594 if (GET_CODE (temp
) != CLOBBER
5595 && (GET_CODE (temp
) != IOR
5596 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5597 || XEXP (temp
, 1) != XEXP (x
, 1))
5598 && (XEXP (temp
, 0) != XEXP (x
, 1)
5599 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5605 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5606 (and <foo> (const_int pow2-1)) */
5607 if (GET_CODE (XEXP (x
, 1)) == AND
5608 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5609 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5610 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5611 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5612 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5616 /* If we have (mult (plus A B) C), apply the distributive law and then
5617 the inverse distributive law to see if things simplify. This
5618 occurs mostly in addresses, often when unrolling loops. */
5620 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5622 rtx result
= distribute_and_simplify_rtx (x
, 0);
5627 /* Try simplify a*(b/c) as (a*b)/c. */
5628 if (FLOAT_MODE_P (mode
) && flag_associative_math
5629 && GET_CODE (XEXP (x
, 0)) == DIV
)
5631 rtx tem
= simplify_binary_operation (MULT
, mode
,
5632 XEXP (XEXP (x
, 0), 0),
5635 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5640 /* If this is a divide by a power of two, treat it as a shift if
5641 its first operand is a shift. */
5642 if (CONST_INT_P (XEXP (x
, 1))
5643 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5644 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5645 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5646 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5647 || GET_CODE (XEXP (x
, 0)) == ROTATE
5648 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5649 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5653 case GT
: case GTU
: case GE
: case GEU
:
5654 case LT
: case LTU
: case LE
: case LEU
:
5655 case UNEQ
: case LTGT
:
5656 case UNGT
: case UNGE
:
5657 case UNLT
: case UNLE
:
5658 case UNORDERED
: case ORDERED
:
5659 /* If the first operand is a condition code, we can't do anything
5661 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5662 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5663 && ! CC0_P (XEXP (x
, 0))))
5665 rtx op0
= XEXP (x
, 0);
5666 rtx op1
= XEXP (x
, 1);
5667 enum rtx_code new_code
;
5669 if (GET_CODE (op0
) == COMPARE
)
5670 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5672 /* Simplify our comparison, if possible. */
5673 new_code
= simplify_comparison (code
, &op0
, &op1
);
5675 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5676 if only the low-order bit is possibly nonzero in X (such as when
5677 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5678 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5679 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5682 Remove any ZERO_EXTRACT we made when thinking this was a
5683 comparison. It may now be simpler to use, e.g., an AND. If a
5684 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5685 the call to make_compound_operation in the SET case.
5687 Don't apply these optimizations if the caller would
5688 prefer a comparison rather than a value.
5689 E.g., for the condition in an IF_THEN_ELSE most targets need
5690 an explicit comparison. */
5695 else if (STORE_FLAG_VALUE
== 1
5696 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5697 && op1
== const0_rtx
5698 && mode
== GET_MODE (op0
)
5699 && nonzero_bits (op0
, mode
) == 1)
5700 return gen_lowpart (mode
,
5701 expand_compound_operation (op0
));
5703 else if (STORE_FLAG_VALUE
== 1
5704 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5705 && op1
== const0_rtx
5706 && mode
== GET_MODE (op0
)
5707 && (num_sign_bit_copies (op0
, mode
)
5708 == GET_MODE_PRECISION (mode
)))
5710 op0
= expand_compound_operation (op0
);
5711 return simplify_gen_unary (NEG
, mode
,
5712 gen_lowpart (mode
, op0
),
5716 else if (STORE_FLAG_VALUE
== 1
5717 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5718 && op1
== const0_rtx
5719 && mode
== GET_MODE (op0
)
5720 && nonzero_bits (op0
, mode
) == 1)
5722 op0
= expand_compound_operation (op0
);
5723 return simplify_gen_binary (XOR
, mode
,
5724 gen_lowpart (mode
, op0
),
5728 else if (STORE_FLAG_VALUE
== 1
5729 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5730 && op1
== const0_rtx
5731 && mode
== GET_MODE (op0
)
5732 && (num_sign_bit_copies (op0
, mode
)
5733 == GET_MODE_PRECISION (mode
)))
5735 op0
= expand_compound_operation (op0
);
5736 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5739 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5744 else if (STORE_FLAG_VALUE
== -1
5745 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5746 && op1
== const0_rtx
5747 && (num_sign_bit_copies (op0
, mode
)
5748 == GET_MODE_PRECISION (mode
)))
5749 return gen_lowpart (mode
,
5750 expand_compound_operation (op0
));
5752 else if (STORE_FLAG_VALUE
== -1
5753 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5754 && op1
== const0_rtx
5755 && mode
== GET_MODE (op0
)
5756 && nonzero_bits (op0
, mode
) == 1)
5758 op0
= expand_compound_operation (op0
);
5759 return simplify_gen_unary (NEG
, mode
,
5760 gen_lowpart (mode
, op0
),
5764 else if (STORE_FLAG_VALUE
== -1
5765 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5766 && op1
== const0_rtx
5767 && mode
== GET_MODE (op0
)
5768 && (num_sign_bit_copies (op0
, mode
)
5769 == GET_MODE_PRECISION (mode
)))
5771 op0
= expand_compound_operation (op0
);
5772 return simplify_gen_unary (NOT
, mode
,
5773 gen_lowpart (mode
, op0
),
5777 /* If X is 0/1, (eq X 0) is X-1. */
5778 else if (STORE_FLAG_VALUE
== -1
5779 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5780 && op1
== const0_rtx
5781 && mode
== GET_MODE (op0
)
5782 && nonzero_bits (op0
, mode
) == 1)
5784 op0
= expand_compound_operation (op0
);
5785 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5788 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5789 one bit that might be nonzero, we can convert (ne x 0) to
5790 (ashift x c) where C puts the bit in the sign bit. Remove any
5791 AND with STORE_FLAG_VALUE when we are done, since we are only
5792 going to test the sign bit. */
5793 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5794 && HWI_COMPUTABLE_MODE_P (mode
)
5795 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5796 && op1
== const0_rtx
5797 && mode
== GET_MODE (op0
)
5798 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5800 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5801 expand_compound_operation (op0
),
5802 GET_MODE_PRECISION (mode
) - 1 - i
);
5803 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5809 /* If the code changed, return a whole new comparison.
5810 We also need to avoid using SUBST in cases where
5811 simplify_comparison has widened a comparison with a CONST_INT,
5812 since in that case the wider CONST_INT may fail the sanity
5813 checks in do_SUBST. */
5814 if (new_code
!= code
5815 || (CONST_INT_P (op1
)
5816 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5817 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5818 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5820 /* Otherwise, keep this operation, but maybe change its operands.
5821 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5822 SUBST (XEXP (x
, 0), op0
);
5823 SUBST (XEXP (x
, 1), op1
);
5828 return simplify_if_then_else (x
);
5834 /* If we are processing SET_DEST, we are done. */
5838 return expand_compound_operation (x
);
5841 return simplify_set (x
);
5845 return simplify_logical (x
);
5852 /* If this is a shift by a constant amount, simplify it. */
5853 if (CONST_INT_P (XEXP (x
, 1)))
5854 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5855 INTVAL (XEXP (x
, 1)));
5857 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5859 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5860 ((unsigned HOST_WIDE_INT
) 1
5861 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5873 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5876 simplify_if_then_else (rtx x
)
5878 enum machine_mode mode
= GET_MODE (x
);
5879 rtx cond
= XEXP (x
, 0);
5880 rtx true_rtx
= XEXP (x
, 1);
5881 rtx false_rtx
= XEXP (x
, 2);
5882 enum rtx_code true_code
= GET_CODE (cond
);
5883 int comparison_p
= COMPARISON_P (cond
);
5886 enum rtx_code false_code
;
5889 /* Simplify storing of the truth value. */
5890 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5891 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5892 XEXP (cond
, 0), XEXP (cond
, 1));
5894 /* Also when the truth value has to be reversed. */
5896 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5897 && (reversed
= reversed_comparison (cond
, mode
)))
5900 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5901 in it is being compared against certain values. Get the true and false
5902 comparisons and see if that says anything about the value of each arm. */
5905 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5907 && REG_P (XEXP (cond
, 0)))
5910 rtx from
= XEXP (cond
, 0);
5911 rtx true_val
= XEXP (cond
, 1);
5912 rtx false_val
= true_val
;
5915 /* If FALSE_CODE is EQ, swap the codes and arms. */
5917 if (false_code
== EQ
)
5919 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5920 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5923 /* If we are comparing against zero and the expression being tested has
5924 only a single bit that might be nonzero, that is its value when it is
5925 not equal to zero. Similarly if it is known to be -1 or 0. */
5927 if (true_code
== EQ
&& true_val
== const0_rtx
5928 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5931 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5933 else if (true_code
== EQ
&& true_val
== const0_rtx
5934 && (num_sign_bit_copies (from
, GET_MODE (from
))
5935 == GET_MODE_PRECISION (GET_MODE (from
))))
5938 false_val
= constm1_rtx
;
5941 /* Now simplify an arm if we know the value of the register in the
5942 branch and it is used in the arm. Be careful due to the potential
5943 of locally-shared RTL. */
5945 if (reg_mentioned_p (from
, true_rtx
))
5946 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5948 pc_rtx
, pc_rtx
, 0, 0, 0);
5949 if (reg_mentioned_p (from
, false_rtx
))
5950 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5952 pc_rtx
, pc_rtx
, 0, 0, 0);
5954 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5955 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5957 true_rtx
= XEXP (x
, 1);
5958 false_rtx
= XEXP (x
, 2);
5959 true_code
= GET_CODE (cond
);
5962 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5963 reversed, do so to avoid needing two sets of patterns for
5964 subtract-and-branch insns. Similarly if we have a constant in the true
5965 arm, the false arm is the same as the first operand of the comparison, or
5966 the false arm is more complicated than the true arm. */
5969 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5970 && (true_rtx
== pc_rtx
5971 || (CONSTANT_P (true_rtx
)
5972 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5973 || true_rtx
== const0_rtx
5974 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5975 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5976 && !OBJECT_P (false_rtx
))
5977 || reg_mentioned_p (true_rtx
, false_rtx
)
5978 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5980 true_code
= reversed_comparison_code (cond
, NULL
);
5981 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5982 SUBST (XEXP (x
, 1), false_rtx
);
5983 SUBST (XEXP (x
, 2), true_rtx
);
5985 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5988 /* It is possible that the conditional has been simplified out. */
5989 true_code
= GET_CODE (cond
);
5990 comparison_p
= COMPARISON_P (cond
);
5993 /* If the two arms are identical, we don't need the comparison. */
5995 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5998 /* Convert a == b ? b : a to "a". */
5999 if (true_code
== EQ
&& ! side_effects_p (cond
)
6000 && !HONOR_NANS (mode
)
6001 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6002 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6004 else if (true_code
== NE
&& ! side_effects_p (cond
)
6005 && !HONOR_NANS (mode
)
6006 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6007 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6010 /* Look for cases where we have (abs x) or (neg (abs X)). */
6012 if (GET_MODE_CLASS (mode
) == MODE_INT
6014 && XEXP (cond
, 1) == const0_rtx
6015 && GET_CODE (false_rtx
) == NEG
6016 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6017 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6018 && ! side_effects_p (true_rtx
))
6023 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6027 simplify_gen_unary (NEG
, mode
,
6028 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6034 /* Look for MIN or MAX. */
6036 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6038 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6039 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6040 && ! side_effects_p (cond
))
6045 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6048 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6051 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6054 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6059 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6060 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6061 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6062 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6063 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6064 neither 1 or -1, but it isn't worth checking for. */
6066 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6068 && GET_MODE_CLASS (mode
) == MODE_INT
6069 && ! side_effects_p (x
))
6071 rtx t
= make_compound_operation (true_rtx
, SET
);
6072 rtx f
= make_compound_operation (false_rtx
, SET
);
6073 rtx cond_op0
= XEXP (cond
, 0);
6074 rtx cond_op1
= XEXP (cond
, 1);
6075 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6076 enum machine_mode m
= mode
;
6077 rtx z
= 0, c1
= NULL_RTX
;
6079 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6080 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6081 || GET_CODE (t
) == ASHIFT
6082 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6083 && rtx_equal_p (XEXP (t
, 0), f
))
6084 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6086 /* If an identity-zero op is commutative, check whether there
6087 would be a match if we swapped the operands. */
6088 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6089 || GET_CODE (t
) == XOR
)
6090 && rtx_equal_p (XEXP (t
, 1), f
))
6091 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6092 else if (GET_CODE (t
) == SIGN_EXTEND
6093 && (GET_CODE (XEXP (t
, 0)) == PLUS
6094 || GET_CODE (XEXP (t
, 0)) == MINUS
6095 || GET_CODE (XEXP (t
, 0)) == IOR
6096 || GET_CODE (XEXP (t
, 0)) == XOR
6097 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6098 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6099 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6100 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6101 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6102 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6103 && (num_sign_bit_copies (f
, GET_MODE (f
))
6105 (GET_MODE_PRECISION (mode
)
6106 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6108 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6109 extend_op
= SIGN_EXTEND
;
6110 m
= GET_MODE (XEXP (t
, 0));
6112 else if (GET_CODE (t
) == SIGN_EXTEND
6113 && (GET_CODE (XEXP (t
, 0)) == PLUS
6114 || GET_CODE (XEXP (t
, 0)) == IOR
6115 || GET_CODE (XEXP (t
, 0)) == XOR
)
6116 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6117 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6118 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6119 && (num_sign_bit_copies (f
, GET_MODE (f
))
6121 (GET_MODE_PRECISION (mode
)
6122 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6124 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6125 extend_op
= SIGN_EXTEND
;
6126 m
= GET_MODE (XEXP (t
, 0));
6128 else if (GET_CODE (t
) == ZERO_EXTEND
6129 && (GET_CODE (XEXP (t
, 0)) == PLUS
6130 || GET_CODE (XEXP (t
, 0)) == MINUS
6131 || GET_CODE (XEXP (t
, 0)) == IOR
6132 || GET_CODE (XEXP (t
, 0)) == XOR
6133 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6134 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6135 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6136 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6137 && HWI_COMPUTABLE_MODE_P (mode
)
6138 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6139 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6140 && ((nonzero_bits (f
, GET_MODE (f
))
6141 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6144 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6145 extend_op
= ZERO_EXTEND
;
6146 m
= GET_MODE (XEXP (t
, 0));
6148 else if (GET_CODE (t
) == ZERO_EXTEND
6149 && (GET_CODE (XEXP (t
, 0)) == PLUS
6150 || GET_CODE (XEXP (t
, 0)) == IOR
6151 || GET_CODE (XEXP (t
, 0)) == XOR
)
6152 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6153 && HWI_COMPUTABLE_MODE_P (mode
)
6154 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6155 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6156 && ((nonzero_bits (f
, GET_MODE (f
))
6157 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6160 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6161 extend_op
= ZERO_EXTEND
;
6162 m
= GET_MODE (XEXP (t
, 0));
6167 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6168 cond_op0
, cond_op1
),
6169 pc_rtx
, pc_rtx
, 0, 0, 0);
6170 temp
= simplify_gen_binary (MULT
, m
, temp
,
6171 simplify_gen_binary (MULT
, m
, c1
,
6173 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6174 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6176 if (extend_op
!= UNKNOWN
)
6177 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6183 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6184 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6185 negation of a single bit, we can convert this operation to a shift. We
6186 can actually do this more generally, but it doesn't seem worth it. */
6188 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6189 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6190 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6191 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6192 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6193 == GET_MODE_PRECISION (mode
))
6194 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6196 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6197 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6199 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6200 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6201 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6202 && GET_MODE (XEXP (cond
, 0)) == mode
6203 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6204 == nonzero_bits (XEXP (cond
, 0), mode
)
6205 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6206 return XEXP (cond
, 0);
6211 /* Simplify X, a SET expression. Return the new expression. */
6214 simplify_set (rtx x
)
6216 rtx src
= SET_SRC (x
);
6217 rtx dest
= SET_DEST (x
);
6218 enum machine_mode mode
6219 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6223 /* (set (pc) (return)) gets written as (return). */
6224 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6227 /* Now that we know for sure which bits of SRC we are using, see if we can
6228 simplify the expression for the object knowing that we only need the
6231 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6233 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6234 SUBST (SET_SRC (x
), src
);
6237 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6238 the comparison result and try to simplify it unless we already have used
6239 undobuf.other_insn. */
6240 if ((GET_MODE_CLASS (mode
) == MODE_CC
6241 || GET_CODE (src
) == COMPARE
6243 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6244 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6245 && COMPARISON_P (*cc_use
)
6246 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6248 enum rtx_code old_code
= GET_CODE (*cc_use
);
6249 enum rtx_code new_code
;
6251 int other_changed
= 0;
6252 rtx inner_compare
= NULL_RTX
;
6253 enum machine_mode compare_mode
= GET_MODE (dest
);
6255 if (GET_CODE (src
) == COMPARE
)
6257 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6258 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6260 inner_compare
= op0
;
6261 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6265 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6267 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6270 new_code
= old_code
;
6271 else if (!CONSTANT_P (tmp
))
6273 new_code
= GET_CODE (tmp
);
6274 op0
= XEXP (tmp
, 0);
6275 op1
= XEXP (tmp
, 1);
6279 rtx pat
= PATTERN (other_insn
);
6280 undobuf
.other_insn
= other_insn
;
6281 SUBST (*cc_use
, tmp
);
6283 /* Attempt to simplify CC user. */
6284 if (GET_CODE (pat
) == SET
)
6286 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6287 if (new_rtx
!= NULL_RTX
)
6288 SUBST (SET_SRC (pat
), new_rtx
);
6291 /* Convert X into a no-op move. */
6292 SUBST (SET_DEST (x
), pc_rtx
);
6293 SUBST (SET_SRC (x
), pc_rtx
);
6297 /* Simplify our comparison, if possible. */
6298 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6300 #ifdef SELECT_CC_MODE
6301 /* If this machine has CC modes other than CCmode, check to see if we
6302 need to use a different CC mode here. */
6303 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6304 compare_mode
= GET_MODE (op0
);
6305 else if (inner_compare
6306 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6307 && new_code
== old_code
6308 && op0
== XEXP (inner_compare
, 0)
6309 && op1
== XEXP (inner_compare
, 1))
6310 compare_mode
= GET_MODE (inner_compare
);
6312 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6315 /* If the mode changed, we have to change SET_DEST, the mode in the
6316 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6317 a hard register, just build new versions with the proper mode. If it
6318 is a pseudo, we lose unless it is only time we set the pseudo, in
6319 which case we can safely change its mode. */
6320 if (compare_mode
!= GET_MODE (dest
))
6322 if (can_change_dest_mode (dest
, 0, compare_mode
))
6324 unsigned int regno
= REGNO (dest
);
6327 if (regno
< FIRST_PSEUDO_REGISTER
)
6328 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6331 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6332 new_dest
= regno_reg_rtx
[regno
];
6335 SUBST (SET_DEST (x
), new_dest
);
6336 SUBST (XEXP (*cc_use
, 0), new_dest
);
6343 #endif /* SELECT_CC_MODE */
6345 /* If the code changed, we have to build a new comparison in
6346 undobuf.other_insn. */
6347 if (new_code
!= old_code
)
6349 int other_changed_previously
= other_changed
;
6350 unsigned HOST_WIDE_INT mask
;
6351 rtx old_cc_use
= *cc_use
;
6353 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6357 /* If the only change we made was to change an EQ into an NE or
6358 vice versa, OP0 has only one bit that might be nonzero, and OP1
6359 is zero, check if changing the user of the condition code will
6360 produce a valid insn. If it won't, we can keep the original code
6361 in that insn by surrounding our operation with an XOR. */
6363 if (((old_code
== NE
&& new_code
== EQ
)
6364 || (old_code
== EQ
&& new_code
== NE
))
6365 && ! other_changed_previously
&& op1
== const0_rtx
6366 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6367 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6369 rtx pat
= PATTERN (other_insn
), note
= 0;
6371 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6372 && ! check_asm_operands (pat
)))
6374 *cc_use
= old_cc_use
;
6377 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6378 op0
, GEN_INT (mask
));
6384 undobuf
.other_insn
= other_insn
;
6386 /* Otherwise, if we didn't previously have a COMPARE in the
6387 correct mode, we need one. */
6388 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6390 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6393 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6395 SUBST (SET_SRC (x
), op0
);
6398 /* Otherwise, update the COMPARE if needed. */
6399 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6401 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6407 /* Get SET_SRC in a form where we have placed back any
6408 compound expressions. Then do the checks below. */
6409 src
= make_compound_operation (src
, SET
);
6410 SUBST (SET_SRC (x
), src
);
6413 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6414 and X being a REG or (subreg (reg)), we may be able to convert this to
6415 (set (subreg:m2 x) (op)).
6417 We can always do this if M1 is narrower than M2 because that means that
6418 we only care about the low bits of the result.
6420 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6421 perform a narrower operation than requested since the high-order bits will
6422 be undefined. On machine where it is defined, this transformation is safe
6423 as long as M1 and M2 have the same number of words. */
6425 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6426 && !OBJECT_P (SUBREG_REG (src
))
6427 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6429 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6430 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6431 #ifndef WORD_REGISTER_OPERATIONS
6432 && (GET_MODE_SIZE (GET_MODE (src
))
6433 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6435 #ifdef CANNOT_CHANGE_MODE_CLASS
6436 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6437 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6438 GET_MODE (SUBREG_REG (src
)),
6442 || (GET_CODE (dest
) == SUBREG
6443 && REG_P (SUBREG_REG (dest
)))))
6445 SUBST (SET_DEST (x
),
6446 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6448 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6450 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6454 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6457 && GET_CODE (src
) == SUBREG
6458 && subreg_lowpart_p (src
)
6459 && (GET_MODE_PRECISION (GET_MODE (src
))
6460 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6462 rtx inner
= SUBREG_REG (src
);
6463 enum machine_mode inner_mode
= GET_MODE (inner
);
6465 /* Here we make sure that we don't have a sign bit on. */
6466 if (val_signbit_known_clear_p (GET_MODE (src
),
6467 nonzero_bits (inner
, inner_mode
)))
6469 SUBST (SET_SRC (x
), inner
);
6475 #ifdef LOAD_EXTEND_OP
6476 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6477 would require a paradoxical subreg. Replace the subreg with a
6478 zero_extend to avoid the reload that would otherwise be required. */
6480 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6481 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6482 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6483 && SUBREG_BYTE (src
) == 0
6484 && paradoxical_subreg_p (src
)
6485 && MEM_P (SUBREG_REG (src
)))
6488 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6489 GET_MODE (src
), SUBREG_REG (src
)));
6495 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6496 are comparing an item known to be 0 or -1 against 0, use a logical
6497 operation instead. Check for one of the arms being an IOR of the other
6498 arm with some value. We compute three terms to be IOR'ed together. In
6499 practice, at most two will be nonzero. Then we do the IOR's. */
6501 if (GET_CODE (dest
) != PC
6502 && GET_CODE (src
) == IF_THEN_ELSE
6503 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6504 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6505 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6506 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6507 #ifdef HAVE_conditional_move
6508 && ! can_conditionally_move_p (GET_MODE (src
))
6510 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6511 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6512 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6513 && ! side_effects_p (src
))
6515 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6516 ? XEXP (src
, 1) : XEXP (src
, 2));
6517 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6518 ? XEXP (src
, 2) : XEXP (src
, 1));
6519 rtx term1
= const0_rtx
, term2
, term3
;
6521 if (GET_CODE (true_rtx
) == IOR
6522 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6523 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6524 else if (GET_CODE (true_rtx
) == IOR
6525 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6526 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6527 else if (GET_CODE (false_rtx
) == IOR
6528 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6529 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6530 else if (GET_CODE (false_rtx
) == IOR
6531 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6532 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6534 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6535 XEXP (XEXP (src
, 0), 0), true_rtx
);
6536 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6537 simplify_gen_unary (NOT
, GET_MODE (src
),
6538 XEXP (XEXP (src
, 0), 0),
6543 simplify_gen_binary (IOR
, GET_MODE (src
),
6544 simplify_gen_binary (IOR
, GET_MODE (src
),
6551 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6552 whole thing fail. */
6553 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6555 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6558 /* Convert this into a field assignment operation, if possible. */
6559 return make_field_assignment (x
);
6562 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6566 simplify_logical (rtx x
)
6568 enum machine_mode mode
= GET_MODE (x
);
6569 rtx op0
= XEXP (x
, 0);
6570 rtx op1
= XEXP (x
, 1);
6572 switch (GET_CODE (x
))
6575 /* We can call simplify_and_const_int only if we don't lose
6576 any (sign) bits when converting INTVAL (op1) to
6577 "unsigned HOST_WIDE_INT". */
6578 if (CONST_INT_P (op1
)
6579 && (HWI_COMPUTABLE_MODE_P (mode
)
6580 || INTVAL (op1
) > 0))
6582 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6583 if (GET_CODE (x
) != AND
)
6590 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6591 apply the distributive law and then the inverse distributive
6592 law to see if things simplify. */
6593 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6595 rtx result
= distribute_and_simplify_rtx (x
, 0);
6599 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6601 rtx result
= distribute_and_simplify_rtx (x
, 1);
6608 /* If we have (ior (and A B) C), apply the distributive law and then
6609 the inverse distributive law to see if things simplify. */
6611 if (GET_CODE (op0
) == AND
)
6613 rtx result
= distribute_and_simplify_rtx (x
, 0);
6618 if (GET_CODE (op1
) == AND
)
6620 rtx result
= distribute_and_simplify_rtx (x
, 1);
6633 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6634 operations" because they can be replaced with two more basic operations.
6635 ZERO_EXTEND is also considered "compound" because it can be replaced with
6636 an AND operation, which is simpler, though only one operation.
6638 The function expand_compound_operation is called with an rtx expression
6639 and will convert it to the appropriate shifts and AND operations,
6640 simplifying at each stage.
6642 The function make_compound_operation is called to convert an expression
6643 consisting of shifts and ANDs into the equivalent compound expression.
6644 It is the inverse of this function, loosely speaking. */
6647 expand_compound_operation (rtx x
)
6649 unsigned HOST_WIDE_INT pos
= 0, len
;
6651 unsigned int modewidth
;
6654 switch (GET_CODE (x
))
6659 /* We can't necessarily use a const_int for a multiword mode;
6660 it depends on implicitly extending the value.
6661 Since we don't know the right way to extend it,
6662 we can't tell whether the implicit way is right.
6664 Even for a mode that is no wider than a const_int,
6665 we can't win, because we need to sign extend one of its bits through
6666 the rest of it, and we don't know which bit. */
6667 if (CONST_INT_P (XEXP (x
, 0)))
6670 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6671 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6672 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6673 reloaded. If not for that, MEM's would very rarely be safe.
6675 Reject MODEs bigger than a word, because we might not be able
6676 to reference a two-register group starting with an arbitrary register
6677 (and currently gen_lowpart might crash for a SUBREG). */
6679 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6682 /* Reject MODEs that aren't scalar integers because turning vector
6683 or complex modes into shifts causes problems. */
6685 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6688 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6689 /* If the inner object has VOIDmode (the only way this can happen
6690 is if it is an ASM_OPERANDS), we can't do anything since we don't
6691 know how much masking to do. */
6700 /* ... fall through ... */
6703 /* If the operand is a CLOBBER, just return it. */
6704 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6707 if (!CONST_INT_P (XEXP (x
, 1))
6708 || !CONST_INT_P (XEXP (x
, 2))
6709 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6712 /* Reject MODEs that aren't scalar integers because turning vector
6713 or complex modes into shifts causes problems. */
6715 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6718 len
= INTVAL (XEXP (x
, 1));
6719 pos
= INTVAL (XEXP (x
, 2));
6721 /* This should stay within the object being extracted, fail otherwise. */
6722 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6725 if (BITS_BIG_ENDIAN
)
6726 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6733 /* Convert sign extension to zero extension, if we know that the high
6734 bit is not set, as this is easier to optimize. It will be converted
6735 back to cheaper alternative in make_extraction. */
6736 if (GET_CODE (x
) == SIGN_EXTEND
6737 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6738 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6739 & ~(((unsigned HOST_WIDE_INT
)
6740 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6744 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6745 rtx temp2
= expand_compound_operation (temp
);
6747 /* Make sure this is a profitable operation. */
6748 if (set_src_cost (x
, optimize_this_for_speed_p
)
6749 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6751 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6752 > set_src_cost (temp
, optimize_this_for_speed_p
))
6758 /* We can optimize some special cases of ZERO_EXTEND. */
6759 if (GET_CODE (x
) == ZERO_EXTEND
)
6761 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6762 know that the last value didn't have any inappropriate bits
6764 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6765 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6766 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6767 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6768 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6769 return XEXP (XEXP (x
, 0), 0);
6771 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6772 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6773 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6774 && subreg_lowpart_p (XEXP (x
, 0))
6775 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6776 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6777 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6778 return SUBREG_REG (XEXP (x
, 0));
6780 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6781 is a comparison and STORE_FLAG_VALUE permits. This is like
6782 the first case, but it works even when GET_MODE (x) is larger
6783 than HOST_WIDE_INT. */
6784 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6785 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6786 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6787 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6788 <= HOST_BITS_PER_WIDE_INT
)
6789 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6790 return XEXP (XEXP (x
, 0), 0);
6792 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6793 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6794 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6795 && subreg_lowpart_p (XEXP (x
, 0))
6796 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6797 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6798 <= HOST_BITS_PER_WIDE_INT
)
6799 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6800 return SUBREG_REG (XEXP (x
, 0));
6804 /* If we reach here, we want to return a pair of shifts. The inner
6805 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6806 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6807 logical depending on the value of UNSIGNEDP.
6809 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6810 converted into an AND of a shift.
6812 We must check for the case where the left shift would have a negative
6813 count. This can happen in a case like (x >> 31) & 255 on machines
6814 that can't shift by a constant. On those machines, we would first
6815 combine the shift with the AND to produce a variable-position
6816 extraction. Then the constant of 31 would be substituted in
6817 to produce such a position. */
6819 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6820 if (modewidth
>= pos
+ len
)
6822 enum machine_mode mode
= GET_MODE (x
);
6823 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6824 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6826 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6827 tem
, modewidth
- pos
- len
);
6828 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6829 mode
, tem
, modewidth
- len
);
6831 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6832 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6833 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6836 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6838 /* Any other cases we can't handle. */
6841 /* If we couldn't do this for some reason, return the original
6843 if (GET_CODE (tem
) == CLOBBER
)
6849 /* X is a SET which contains an assignment of one object into
6850 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6851 or certain SUBREGS). If possible, convert it into a series of
6854 We half-heartedly support variable positions, but do not at all
6855 support variable lengths. */
6858 expand_field_assignment (const_rtx x
)
6861 rtx pos
; /* Always counts from low bit. */
6863 rtx mask
, cleared
, masked
;
6864 enum machine_mode compute_mode
;
6866 /* Loop until we find something we can't simplify. */
6869 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6870 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6872 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6873 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6874 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6876 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6877 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6879 inner
= XEXP (SET_DEST (x
), 0);
6880 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6881 pos
= XEXP (SET_DEST (x
), 2);
6883 /* A constant position should stay within the width of INNER. */
6884 if (CONST_INT_P (pos
)
6885 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6888 if (BITS_BIG_ENDIAN
)
6890 if (CONST_INT_P (pos
))
6891 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6893 else if (GET_CODE (pos
) == MINUS
6894 && CONST_INT_P (XEXP (pos
, 1))
6895 && (INTVAL (XEXP (pos
, 1))
6896 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6897 /* If position is ADJUST - X, new position is X. */
6898 pos
= XEXP (pos
, 0);
6900 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6901 GEN_INT (GET_MODE_PRECISION (
6908 /* A SUBREG between two modes that occupy the same numbers of words
6909 can be done by moving the SUBREG to the source. */
6910 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6911 /* We need SUBREGs to compute nonzero_bits properly. */
6912 && nonzero_sign_valid
6913 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6914 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6915 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6916 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6918 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6920 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6927 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6928 inner
= SUBREG_REG (inner
);
6930 compute_mode
= GET_MODE (inner
);
6932 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6933 if (! SCALAR_INT_MODE_P (compute_mode
))
6935 enum machine_mode imode
;
6937 /* Don't do anything for vector or complex integral types. */
6938 if (! FLOAT_MODE_P (compute_mode
))
6941 /* Try to find an integral mode to pun with. */
6942 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6943 if (imode
== BLKmode
)
6946 compute_mode
= imode
;
6947 inner
= gen_lowpart (imode
, inner
);
6950 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6951 if (len
>= HOST_BITS_PER_WIDE_INT
)
6954 /* Now compute the equivalent expression. Make a copy of INNER
6955 for the SET_DEST in case it is a MEM into which we will substitute;
6956 we don't want shared RTL in that case. */
6957 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6958 cleared
= simplify_gen_binary (AND
, compute_mode
,
6959 simplify_gen_unary (NOT
, compute_mode
,
6960 simplify_gen_binary (ASHIFT
,
6965 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6966 simplify_gen_binary (
6968 gen_lowpart (compute_mode
, SET_SRC (x
)),
6972 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6973 simplify_gen_binary (IOR
, compute_mode
,
6980 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6981 it is an RTX that represents the (variable) starting position; otherwise,
6982 POS is the (constant) starting bit position. Both are counted from the LSB.
6984 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6986 IN_DEST is nonzero if this is a reference in the destination of a SET.
6987 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6988 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6991 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6992 ZERO_EXTRACT should be built even for bits starting at bit 0.
6994 MODE is the desired mode of the result (if IN_DEST == 0).
6996 The result is an RTX for the extraction or NULL_RTX if the target
7000 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7001 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7002 int in_dest
, int in_compare
)
7004 /* This mode describes the size of the storage area
7005 to fetch the overall value from. Within that, we
7006 ignore the POS lowest bits, etc. */
7007 enum machine_mode is_mode
= GET_MODE (inner
);
7008 enum machine_mode inner_mode
;
7009 enum machine_mode wanted_inner_mode
;
7010 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7011 enum machine_mode pos_mode
= word_mode
;
7012 enum machine_mode extraction_mode
= word_mode
;
7013 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7015 rtx orig_pos_rtx
= pos_rtx
;
7016 HOST_WIDE_INT orig_pos
;
7018 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7019 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7021 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7023 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7024 consider just the QI as the memory to extract from.
7025 The subreg adds or removes high bits; its mode is
7026 irrelevant to the meaning of this extraction,
7027 since POS and LEN count from the lsb. */
7028 if (MEM_P (SUBREG_REG (inner
)))
7029 is_mode
= GET_MODE (SUBREG_REG (inner
));
7030 inner
= SUBREG_REG (inner
);
7032 else if (GET_CODE (inner
) == ASHIFT
7033 && CONST_INT_P (XEXP (inner
, 1))
7034 && pos_rtx
== 0 && pos
== 0
7035 && len
> UINTVAL (XEXP (inner
, 1)))
7037 /* We're extracting the least significant bits of an rtx
7038 (ashift X (const_int C)), where LEN > C. Extract the
7039 least significant (LEN - C) bits of X, giving an rtx
7040 whose mode is MODE, then shift it left C times. */
7041 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7042 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7043 unsignedp
, in_dest
, in_compare
);
7045 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7047 else if (GET_CODE (inner
) == TRUNCATE
)
7048 inner
= XEXP (inner
, 0);
7050 inner_mode
= GET_MODE (inner
);
7052 /* See if this can be done without an extraction. We never can if the
7053 width of the field is not the same as that of some integer mode. For
7054 registers, we can only avoid the extraction if the position is at the
7055 low-order bit and this is either not in the destination or we have the
7056 appropriate STRICT_LOW_PART operation available.
7058 For MEM, we can avoid an extract if the field starts on an appropriate
7059 boundary and we can change the mode of the memory reference. */
7061 if (tmode
!= BLKmode
7062 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7064 && (inner_mode
== tmode
7066 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7067 || reg_truncated_to_mode (tmode
, inner
))
7070 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7071 || (MEM_P (inner
) && pos_rtx
== 0
7073 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7074 : BITS_PER_UNIT
)) == 0
7075 /* We can't do this if we are widening INNER_MODE (it
7076 may not be aligned, for one thing). */
7077 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7078 && (inner_mode
== tmode
7079 || (! mode_dependent_address_p (XEXP (inner
, 0),
7080 MEM_ADDR_SPACE (inner
))
7081 && ! MEM_VOLATILE_P (inner
))))))
7083 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7084 field. If the original and current mode are the same, we need not
7085 adjust the offset. Otherwise, we do if bytes big endian.
7087 If INNER is not a MEM, get a piece consisting of just the field
7088 of interest (in this case POS % BITS_PER_WORD must be 0). */
7092 HOST_WIDE_INT offset
;
7094 /* POS counts from lsb, but make OFFSET count in memory order. */
7095 if (BYTES_BIG_ENDIAN
)
7096 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7098 offset
= pos
/ BITS_PER_UNIT
;
7100 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7102 else if (REG_P (inner
))
7104 if (tmode
!= inner_mode
)
7106 /* We can't call gen_lowpart in a DEST since we
7107 always want a SUBREG (see below) and it would sometimes
7108 return a new hard register. */
7111 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7113 if (WORDS_BIG_ENDIAN
7114 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7115 final_word
= ((GET_MODE_SIZE (inner_mode
)
7116 - GET_MODE_SIZE (tmode
))
7117 / UNITS_PER_WORD
) - final_word
;
7119 final_word
*= UNITS_PER_WORD
;
7120 if (BYTES_BIG_ENDIAN
&&
7121 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7122 final_word
+= (GET_MODE_SIZE (inner_mode
)
7123 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7125 /* Avoid creating invalid subregs, for example when
7126 simplifying (x>>32)&255. */
7127 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7130 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7133 new_rtx
= gen_lowpart (tmode
, inner
);
7139 new_rtx
= force_to_mode (inner
, tmode
,
7140 len
>= HOST_BITS_PER_WIDE_INT
7141 ? ~(unsigned HOST_WIDE_INT
) 0
7142 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7145 /* If this extraction is going into the destination of a SET,
7146 make a STRICT_LOW_PART unless we made a MEM. */
7149 return (MEM_P (new_rtx
) ? new_rtx
7150 : (GET_CODE (new_rtx
) != SUBREG
7151 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7152 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7157 if (CONST_SCALAR_INT_P (new_rtx
))
7158 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7159 mode
, new_rtx
, tmode
);
7161 /* If we know that no extraneous bits are set, and that the high
7162 bit is not set, convert the extraction to the cheaper of
7163 sign and zero extension, that are equivalent in these cases. */
7164 if (flag_expensive_optimizations
7165 && (HWI_COMPUTABLE_MODE_P (tmode
)
7166 && ((nonzero_bits (new_rtx
, tmode
)
7167 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7170 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7171 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7173 /* Prefer ZERO_EXTENSION, since it gives more information to
7175 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7176 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7181 /* Otherwise, sign- or zero-extend unless we already are in the
7184 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7188 /* Unless this is a COMPARE or we have a funny memory reference,
7189 don't do anything with zero-extending field extracts starting at
7190 the low-order bit since they are simple AND operations. */
7191 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7192 && ! in_compare
&& unsignedp
)
7195 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7196 if the position is not a constant and the length is not 1. In all
7197 other cases, we would only be going outside our object in cases when
7198 an original shift would have been undefined. */
7200 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7201 || (pos_rtx
!= 0 && len
!= 1)))
7204 enum extraction_pattern pattern
= (in_dest
? EP_insv
7205 : unsignedp
? EP_extzv
: EP_extv
);
7207 /* If INNER is not from memory, we want it to have the mode of a register
7208 extraction pattern's structure operand, or word_mode if there is no
7209 such pattern. The same applies to extraction_mode and pos_mode
7210 and their respective operands.
7212 For memory, assume that the desired extraction_mode and pos_mode
7213 are the same as for a register operation, since at present we don't
7214 have named patterns for aligned memory structures. */
7215 struct extraction_insn insn
;
7216 if (get_best_reg_extraction_insn (&insn
, pattern
,
7217 GET_MODE_BITSIZE (inner_mode
), mode
))
7219 wanted_inner_reg_mode
= insn
.struct_mode
;
7220 pos_mode
= insn
.pos_mode
;
7221 extraction_mode
= insn
.field_mode
;
7224 /* Never narrow an object, since that might not be safe. */
7226 if (mode
!= VOIDmode
7227 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7228 extraction_mode
= mode
;
7231 wanted_inner_mode
= wanted_inner_reg_mode
;
7234 /* Be careful not to go beyond the extracted object and maintain the
7235 natural alignment of the memory. */
7236 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7237 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7238 > GET_MODE_BITSIZE (wanted_inner_mode
))
7240 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7241 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7247 if (BITS_BIG_ENDIAN
)
7249 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7250 BITS_BIG_ENDIAN style. If position is constant, compute new
7251 position. Otherwise, build subtraction.
7252 Note that POS is relative to the mode of the original argument.
7253 If it's a MEM we need to recompute POS relative to that.
7254 However, if we're extracting from (or inserting into) a register,
7255 we want to recompute POS relative to wanted_inner_mode. */
7256 int width
= (MEM_P (inner
)
7257 ? GET_MODE_BITSIZE (is_mode
)
7258 : GET_MODE_BITSIZE (wanted_inner_mode
));
7261 pos
= width
- len
- pos
;
7264 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7265 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7267 /* POS may be less than 0 now, but we check for that below.
7268 Note that it can only be less than 0 if !MEM_P (inner). */
7271 /* If INNER has a wider mode, and this is a constant extraction, try to
7272 make it smaller and adjust the byte to point to the byte containing
7274 if (wanted_inner_mode
!= VOIDmode
7275 && inner_mode
!= wanted_inner_mode
7277 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7279 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7280 && ! MEM_VOLATILE_P (inner
))
7284 /* The computations below will be correct if the machine is big
7285 endian in both bits and bytes or little endian in bits and bytes.
7286 If it is mixed, we must adjust. */
7288 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7289 adjust OFFSET to compensate. */
7290 if (BYTES_BIG_ENDIAN
7291 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7292 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7294 /* We can now move to the desired byte. */
7295 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7296 * GET_MODE_SIZE (wanted_inner_mode
);
7297 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7299 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7300 && is_mode
!= wanted_inner_mode
)
7301 offset
= (GET_MODE_SIZE (is_mode
)
7302 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7304 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7307 /* If INNER is not memory, get it into the proper mode. If we are changing
7308 its mode, POS must be a constant and smaller than the size of the new
7310 else if (!MEM_P (inner
))
7312 /* On the LHS, don't create paradoxical subregs implicitely truncating
7313 the register unless TRULY_NOOP_TRUNCATION. */
7315 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7319 if (GET_MODE (inner
) != wanted_inner_mode
7321 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7327 inner
= force_to_mode (inner
, wanted_inner_mode
,
7329 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7330 ? ~(unsigned HOST_WIDE_INT
) 0
7331 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7336 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7337 have to zero extend. Otherwise, we can just use a SUBREG. */
7339 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7341 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7342 GET_MODE (pos_rtx
));
7344 /* If we know that no extraneous bits are set, and that the high
7345 bit is not set, convert extraction to cheaper one - either
7346 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7348 if (flag_expensive_optimizations
7349 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7350 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7351 & ~(((unsigned HOST_WIDE_INT
)
7352 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7356 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7357 GET_MODE (pos_rtx
));
7359 /* Prefer ZERO_EXTENSION, since it gives more information to
7361 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7362 < set_src_cost (temp
, optimize_this_for_speed_p
))
7368 /* Make POS_RTX unless we already have it and it is correct. If we don't
7369 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7371 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7372 pos_rtx
= orig_pos_rtx
;
7374 else if (pos_rtx
== 0)
7375 pos_rtx
= GEN_INT (pos
);
7377 /* Make the required operation. See if we can use existing rtx. */
7378 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7379 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7381 new_rtx
= gen_lowpart (mode
, new_rtx
);
7386 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7387 with any other operations in X. Return X without that shift if so. */
7390 extract_left_shift (rtx x
, int count
)
7392 enum rtx_code code
= GET_CODE (x
);
7393 enum machine_mode mode
= GET_MODE (x
);
7399 /* This is the shift itself. If it is wide enough, we will return
7400 either the value being shifted if the shift count is equal to
7401 COUNT or a shift for the difference. */
7402 if (CONST_INT_P (XEXP (x
, 1))
7403 && INTVAL (XEXP (x
, 1)) >= count
)
7404 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7405 INTVAL (XEXP (x
, 1)) - count
);
7409 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7410 return simplify_gen_unary (code
, mode
, tem
, mode
);
7414 case PLUS
: case IOR
: case XOR
: case AND
:
7415 /* If we can safely shift this constant and we find the inner shift,
7416 make a new operation. */
7417 if (CONST_INT_P (XEXP (x
, 1))
7418 && (UINTVAL (XEXP (x
, 1))
7419 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7420 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7421 return simplify_gen_binary (code
, mode
, tem
,
7422 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7433 /* Look at the expression rooted at X. Look for expressions
7434 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7435 Form these expressions.
7437 Return the new rtx, usually just X.
7439 Also, for machines like the VAX that don't have logical shift insns,
7440 try to convert logical to arithmetic shift operations in cases where
7441 they are equivalent. This undoes the canonicalizations to logical
7442 shifts done elsewhere.
7444 We try, as much as possible, to re-use rtl expressions to save memory.
7446 IN_CODE says what kind of expression we are processing. Normally, it is
7447 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7448 being kludges), it is MEM. When processing the arguments of a comparison
7449 or a COMPARE against zero, it is COMPARE. */
7452 make_compound_operation (rtx x
, enum rtx_code in_code
)
7454 enum rtx_code code
= GET_CODE (x
);
7455 enum machine_mode mode
= GET_MODE (x
);
7456 int mode_width
= GET_MODE_PRECISION (mode
);
7458 enum rtx_code next_code
;
7464 /* Select the code to be used in recursive calls. Once we are inside an
7465 address, we stay there. If we have a comparison, set to COMPARE,
7466 but once inside, go back to our default of SET. */
7468 next_code
= (code
== MEM
? MEM
7469 : ((code
== PLUS
|| code
== MINUS
)
7470 && SCALAR_INT_MODE_P (mode
)) ? MEM
7471 : ((code
== COMPARE
|| COMPARISON_P (x
))
7472 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7473 : in_code
== COMPARE
? SET
: in_code
);
7475 /* Process depending on the code of this operation. If NEW is set
7476 nonzero, it will be returned. */
7481 /* Convert shifts by constants into multiplications if inside
7483 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7484 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7485 && INTVAL (XEXP (x
, 1)) >= 0
7486 && SCALAR_INT_MODE_P (mode
))
7488 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7489 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7491 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7492 if (GET_CODE (new_rtx
) == NEG
)
7494 new_rtx
= XEXP (new_rtx
, 0);
7497 multval
= trunc_int_for_mode (multval
, mode
);
7498 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7505 lhs
= make_compound_operation (lhs
, next_code
);
7506 rhs
= make_compound_operation (rhs
, next_code
);
7507 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7508 && SCALAR_INT_MODE_P (mode
))
7510 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7512 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7514 else if (GET_CODE (lhs
) == MULT
7515 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7517 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7518 simplify_gen_unary (NEG
, mode
,
7521 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7525 SUBST (XEXP (x
, 0), lhs
);
7526 SUBST (XEXP (x
, 1), rhs
);
7529 x
= gen_lowpart (mode
, new_rtx
);
7535 lhs
= make_compound_operation (lhs
, next_code
);
7536 rhs
= make_compound_operation (rhs
, next_code
);
7537 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7538 && SCALAR_INT_MODE_P (mode
))
7540 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7542 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7544 else if (GET_CODE (rhs
) == MULT
7545 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7547 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7548 simplify_gen_unary (NEG
, mode
,
7551 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7555 SUBST (XEXP (x
, 0), lhs
);
7556 SUBST (XEXP (x
, 1), rhs
);
7559 return gen_lowpart (mode
, new_rtx
);
7562 /* If the second operand is not a constant, we can't do anything
7564 if (!CONST_INT_P (XEXP (x
, 1)))
7567 /* If the constant is a power of two minus one and the first operand
7568 is a logical right shift, make an extraction. */
7569 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7570 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7572 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7573 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7574 0, in_code
== COMPARE
);
7577 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7578 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7579 && subreg_lowpart_p (XEXP (x
, 0))
7580 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7581 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7583 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7585 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7586 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7587 0, in_code
== COMPARE
);
7589 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7590 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7591 || GET_CODE (XEXP (x
, 0)) == IOR
)
7592 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7593 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7594 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7596 /* Apply the distributive law, and then try to make extractions. */
7597 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7598 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7600 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7602 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7605 /* If we are have (and (rotate X C) M) and C is larger than the number
7606 of bits in M, this is an extraction. */
7608 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7609 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7610 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7611 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7613 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7614 new_rtx
= make_extraction (mode
, new_rtx
,
7615 (GET_MODE_PRECISION (mode
)
7616 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7617 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7620 /* On machines without logical shifts, if the operand of the AND is
7621 a logical shift and our mask turns off all the propagated sign
7622 bits, we can replace the logical shift with an arithmetic shift. */
7623 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7624 && !have_insn_for (LSHIFTRT
, mode
)
7625 && have_insn_for (ASHIFTRT
, mode
)
7626 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7627 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7628 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7629 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7631 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7633 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7634 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7636 gen_rtx_ASHIFTRT (mode
,
7637 make_compound_operation
7638 (XEXP (XEXP (x
, 0), 0), next_code
),
7639 XEXP (XEXP (x
, 0), 1)));
7642 /* If the constant is one less than a power of two, this might be
7643 representable by an extraction even if no shift is present.
7644 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7645 we are in a COMPARE. */
7646 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7647 new_rtx
= make_extraction (mode
,
7648 make_compound_operation (XEXP (x
, 0),
7650 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7652 /* If we are in a comparison and this is an AND with a power of two,
7653 convert this into the appropriate bit extract. */
7654 else if (in_code
== COMPARE
7655 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7656 new_rtx
= make_extraction (mode
,
7657 make_compound_operation (XEXP (x
, 0),
7659 i
, NULL_RTX
, 1, 1, 0, 1);
7664 /* If the sign bit is known to be zero, replace this with an
7665 arithmetic shift. */
7666 if (have_insn_for (ASHIFTRT
, mode
)
7667 && ! have_insn_for (LSHIFTRT
, mode
)
7668 && mode_width
<= HOST_BITS_PER_WIDE_INT
7669 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7671 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7672 make_compound_operation (XEXP (x
, 0),
7678 /* ... fall through ... */
7684 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7685 this is a SIGN_EXTRACT. */
7686 if (CONST_INT_P (rhs
)
7687 && GET_CODE (lhs
) == ASHIFT
7688 && CONST_INT_P (XEXP (lhs
, 1))
7689 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7690 && INTVAL (XEXP (lhs
, 1)) >= 0
7691 && INTVAL (rhs
) < mode_width
)
7693 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7694 new_rtx
= make_extraction (mode
, new_rtx
,
7695 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7696 NULL_RTX
, mode_width
- INTVAL (rhs
),
7697 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7701 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7702 If so, try to merge the shifts into a SIGN_EXTEND. We could
7703 also do this for some cases of SIGN_EXTRACT, but it doesn't
7704 seem worth the effort; the case checked for occurs on Alpha. */
7707 && ! (GET_CODE (lhs
) == SUBREG
7708 && (OBJECT_P (SUBREG_REG (lhs
))))
7709 && CONST_INT_P (rhs
)
7710 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7711 && INTVAL (rhs
) < mode_width
7712 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7713 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7714 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7715 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7720 /* Call ourselves recursively on the inner expression. If we are
7721 narrowing the object and it has a different RTL code from
7722 what it originally did, do this SUBREG as a force_to_mode. */
7724 rtx inner
= SUBREG_REG (x
), simplified
;
7725 enum rtx_code subreg_code
= in_code
;
7727 /* If in_code is COMPARE, it isn't always safe to pass it through
7728 to the recursive make_compound_operation call. */
7729 if (subreg_code
== COMPARE
7730 && (!subreg_lowpart_p (x
)
7731 || GET_CODE (inner
) == SUBREG
7732 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7733 is (const_int 0), rather than
7734 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7735 || (GET_CODE (inner
) == AND
7736 && CONST_INT_P (XEXP (inner
, 1))
7737 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7738 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7739 >= GET_MODE_BITSIZE (mode
))))
7742 tem
= make_compound_operation (inner
, subreg_code
);
7745 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7749 if (GET_CODE (tem
) != GET_CODE (inner
)
7750 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7751 && subreg_lowpart_p (x
))
7754 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7756 /* If we have something other than a SUBREG, we might have
7757 done an expansion, so rerun ourselves. */
7758 if (GET_CODE (newer
) != SUBREG
)
7759 newer
= make_compound_operation (newer
, in_code
);
7761 /* force_to_mode can expand compounds. If it just re-expanded the
7762 compound, use gen_lowpart to convert to the desired mode. */
7763 if (rtx_equal_p (newer
, x
)
7764 /* Likewise if it re-expanded the compound only partially.
7765 This happens for SUBREG of ZERO_EXTRACT if they extract
7766 the same number of bits. */
7767 || (GET_CODE (newer
) == SUBREG
7768 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7769 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7770 && GET_CODE (inner
) == AND
7771 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7772 return gen_lowpart (GET_MODE (x
), tem
);
7788 x
= gen_lowpart (mode
, new_rtx
);
7789 code
= GET_CODE (x
);
7792 /* Now recursively process each operand of this operation. We need to
7793 handle ZERO_EXTEND specially so that we don't lose track of the
7795 if (GET_CODE (x
) == ZERO_EXTEND
)
7797 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7798 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7799 new_rtx
, GET_MODE (XEXP (x
, 0)));
7802 SUBST (XEXP (x
, 0), new_rtx
);
7806 fmt
= GET_RTX_FORMAT (code
);
7807 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7810 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7811 SUBST (XEXP (x
, i
), new_rtx
);
7813 else if (fmt
[i
] == 'E')
7814 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7816 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7817 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7821 /* If this is a commutative operation, the changes to the operands
7822 may have made it noncanonical. */
7823 if (COMMUTATIVE_ARITH_P (x
)
7824 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7827 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7828 SUBST (XEXP (x
, 1), tem
);
7834 /* Given M see if it is a value that would select a field of bits
7835 within an item, but not the entire word. Return -1 if not.
7836 Otherwise, return the starting position of the field, where 0 is the
7839 *PLEN is set to the length of the field. */
7842 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7844 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7845 int pos
= m
? ctz_hwi (m
) : -1;
7849 /* Now shift off the low-order zero bits and see if we have a
7850 power of two minus 1. */
7851 len
= exact_log2 ((m
>> pos
) + 1);
7860 /* If X refers to a register that equals REG in value, replace these
7861 references with REG. */
7863 canon_reg_for_combine (rtx x
, rtx reg
)
7870 enum rtx_code code
= GET_CODE (x
);
7871 switch (GET_RTX_CLASS (code
))
7874 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7875 if (op0
!= XEXP (x
, 0))
7876 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7881 case RTX_COMM_ARITH
:
7882 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7883 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7884 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7885 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7889 case RTX_COMM_COMPARE
:
7890 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7891 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7892 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7893 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7894 GET_MODE (op0
), op0
, op1
);
7898 case RTX_BITFIELD_OPS
:
7899 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7900 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7901 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7902 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7903 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7904 GET_MODE (op0
), op0
, op1
, op2
);
7909 if (rtx_equal_p (get_last_value (reg
), x
)
7910 || rtx_equal_p (reg
, get_last_value (x
)))
7919 fmt
= GET_RTX_FORMAT (code
);
7921 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7924 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7925 if (op
!= XEXP (x
, i
))
7935 else if (fmt
[i
] == 'E')
7938 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7940 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7941 if (op
!= XVECEXP (x
, i
, j
))
7948 XVECEXP (x
, i
, j
) = op
;
7959 /* Return X converted to MODE. If the value is already truncated to
7960 MODE we can just return a subreg even though in the general case we
7961 would need an explicit truncation. */
7964 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7966 if (!CONST_INT_P (x
)
7967 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7968 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
7969 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7971 /* Bit-cast X into an integer mode. */
7972 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7973 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7974 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7978 return gen_lowpart (mode
, x
);
7981 /* See if X can be simplified knowing that we will only refer to it in
7982 MODE and will only refer to those bits that are nonzero in MASK.
7983 If other bits are being computed or if masking operations are done
7984 that select a superset of the bits in MASK, they can sometimes be
7987 Return a possibly simplified expression, but always convert X to
7988 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7990 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7991 are all off in X. This is used when X will be complemented, by either
7992 NOT, NEG, or XOR. */
7995 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7998 enum rtx_code code
= GET_CODE (x
);
7999 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8000 enum machine_mode op_mode
;
8001 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8004 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8005 code below will do the wrong thing since the mode of such an
8006 expression is VOIDmode.
8008 Also do nothing if X is a CLOBBER; this can happen if X was
8009 the return value from a call to gen_lowpart. */
8010 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8013 /* We want to perform the operation is its present mode unless we know
8014 that the operation is valid in MODE, in which case we do the operation
8016 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8017 && have_insn_for (code
, mode
))
8018 ? mode
: GET_MODE (x
));
8020 /* It is not valid to do a right-shift in a narrower mode
8021 than the one it came in with. */
8022 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8023 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8024 op_mode
= GET_MODE (x
);
8026 /* Truncate MASK to fit OP_MODE. */
8028 mask
&= GET_MODE_MASK (op_mode
);
8030 /* When we have an arithmetic operation, or a shift whose count we
8031 do not know, we need to assume that all bits up to the highest-order
8032 bit in MASK will be needed. This is how we form such a mask. */
8033 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8034 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8036 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8039 /* Determine what bits of X are guaranteed to be (non)zero. */
8040 nonzero
= nonzero_bits (x
, mode
);
8042 /* If none of the bits in X are needed, return a zero. */
8043 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8046 /* If X is a CONST_INT, return a new one. Do this here since the
8047 test below will fail. */
8048 if (CONST_INT_P (x
))
8050 if (SCALAR_INT_MODE_P (mode
))
8051 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8054 x
= GEN_INT (INTVAL (x
) & mask
);
8055 return gen_lowpart_common (mode
, x
);
8059 /* If X is narrower than MODE and we want all the bits in X's mode, just
8060 get X in the proper mode. */
8061 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8062 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8063 return gen_lowpart (mode
, x
);
8065 /* We can ignore the effect of a SUBREG if it narrows the mode or
8066 if the constant masks to zero all the bits the mode doesn't have. */
8067 if (GET_CODE (x
) == SUBREG
8068 && subreg_lowpart_p (x
)
8069 && ((GET_MODE_SIZE (GET_MODE (x
))
8070 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8072 & GET_MODE_MASK (GET_MODE (x
))
8073 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8074 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8076 /* The arithmetic simplifications here only work for scalar integer modes. */
8077 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8078 return gen_lowpart_or_truncate (mode
, x
);
8083 /* If X is a (clobber (const_int)), return it since we know we are
8084 generating something that won't match. */
8091 x
= expand_compound_operation (x
);
8092 if (GET_CODE (x
) != code
)
8093 return force_to_mode (x
, mode
, mask
, next_select
);
8097 /* Similarly for a truncate. */
8098 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8101 /* If this is an AND with a constant, convert it into an AND
8102 whose constant is the AND of that constant with MASK. If it
8103 remains an AND of MASK, delete it since it is redundant. */
8105 if (CONST_INT_P (XEXP (x
, 1)))
8107 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8108 mask
& INTVAL (XEXP (x
, 1)));
8110 /* If X is still an AND, see if it is an AND with a mask that
8111 is just some low-order bits. If so, and it is MASK, we don't
8114 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8115 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8119 /* If it remains an AND, try making another AND with the bits
8120 in the mode mask that aren't in MASK turned on. If the
8121 constant in the AND is wide enough, this might make a
8122 cheaper constant. */
8124 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8125 && GET_MODE_MASK (GET_MODE (x
)) != mask
8126 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8128 unsigned HOST_WIDE_INT cval
8129 = UINTVAL (XEXP (x
, 1))
8130 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8131 int width
= GET_MODE_PRECISION (GET_MODE (x
));
8134 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8135 number, sign extend it. */
8136 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8137 && (cval
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8138 cval
|= HOST_WIDE_INT_M1U
<< width
;
8140 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8141 XEXP (x
, 0), GEN_INT (cval
));
8142 if (set_src_cost (y
, optimize_this_for_speed_p
)
8143 < set_src_cost (x
, optimize_this_for_speed_p
))
8153 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8154 low-order bits (as in an alignment operation) and FOO is already
8155 aligned to that boundary, mask C1 to that boundary as well.
8156 This may eliminate that PLUS and, later, the AND. */
8159 unsigned int width
= GET_MODE_PRECISION (mode
);
8160 unsigned HOST_WIDE_INT smask
= mask
;
8162 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8163 number, sign extend it. */
8165 if (width
< HOST_BITS_PER_WIDE_INT
8166 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8167 smask
|= HOST_WIDE_INT_M1U
<< width
;
8169 if (CONST_INT_P (XEXP (x
, 1))
8170 && exact_log2 (- smask
) >= 0
8171 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8172 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8173 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8174 (INTVAL (XEXP (x
, 1)) & smask
)),
8175 mode
, smask
, next_select
);
8178 /* ... fall through ... */
8181 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8182 most significant bit in MASK since carries from those bits will
8183 affect the bits we are interested in. */
8188 /* If X is (minus C Y) where C's least set bit is larger than any bit
8189 in the mask, then we may replace with (neg Y). */
8190 if (CONST_INT_P (XEXP (x
, 0))
8191 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8192 & -INTVAL (XEXP (x
, 0))))
8195 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8197 return force_to_mode (x
, mode
, mask
, next_select
);
8200 /* Similarly, if C contains every bit in the fuller_mask, then we may
8201 replace with (not Y). */
8202 if (CONST_INT_P (XEXP (x
, 0))
8203 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8205 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8206 XEXP (x
, 1), GET_MODE (x
));
8207 return force_to_mode (x
, mode
, mask
, next_select
);
8215 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8216 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8217 operation which may be a bitfield extraction. Ensure that the
8218 constant we form is not wider than the mode of X. */
8220 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8221 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8222 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8223 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8224 && CONST_INT_P (XEXP (x
, 1))
8225 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8226 + floor_log2 (INTVAL (XEXP (x
, 1))))
8227 < GET_MODE_PRECISION (GET_MODE (x
)))
8228 && (UINTVAL (XEXP (x
, 1))
8229 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8231 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8232 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8233 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8234 XEXP (XEXP (x
, 0), 0), temp
);
8235 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8236 XEXP (XEXP (x
, 0), 1));
8237 return force_to_mode (x
, mode
, mask
, next_select
);
8241 /* For most binary operations, just propagate into the operation and
8242 change the mode if we have an operation of that mode. */
8244 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8245 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8247 /* If we ended up truncating both operands, truncate the result of the
8248 operation instead. */
8249 if (GET_CODE (op0
) == TRUNCATE
8250 && GET_CODE (op1
) == TRUNCATE
)
8252 op0
= XEXP (op0
, 0);
8253 op1
= XEXP (op1
, 0);
8256 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8257 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8259 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8260 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8264 /* For left shifts, do the same, but just for the first operand.
8265 However, we cannot do anything with shifts where we cannot
8266 guarantee that the counts are smaller than the size of the mode
8267 because such a count will have a different meaning in a
8270 if (! (CONST_INT_P (XEXP (x
, 1))
8271 && INTVAL (XEXP (x
, 1)) >= 0
8272 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8273 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8274 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8275 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8278 /* If the shift count is a constant and we can do arithmetic in
8279 the mode of the shift, refine which bits we need. Otherwise, use the
8280 conservative form of the mask. */
8281 if (CONST_INT_P (XEXP (x
, 1))
8282 && INTVAL (XEXP (x
, 1)) >= 0
8283 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8284 && HWI_COMPUTABLE_MODE_P (op_mode
))
8285 mask
>>= INTVAL (XEXP (x
, 1));
8289 op0
= gen_lowpart_or_truncate (op_mode
,
8290 force_to_mode (XEXP (x
, 0), op_mode
,
8291 mask
, next_select
));
8293 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8294 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8298 /* Here we can only do something if the shift count is a constant,
8299 this shift constant is valid for the host, and we can do arithmetic
8302 if (CONST_INT_P (XEXP (x
, 1))
8303 && INTVAL (XEXP (x
, 1)) >= 0
8304 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8305 && HWI_COMPUTABLE_MODE_P (op_mode
))
8307 rtx inner
= XEXP (x
, 0);
8308 unsigned HOST_WIDE_INT inner_mask
;
8310 /* Select the mask of the bits we need for the shift operand. */
8311 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8313 /* We can only change the mode of the shift if we can do arithmetic
8314 in the mode of the shift and INNER_MASK is no wider than the
8315 width of X's mode. */
8316 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8317 op_mode
= GET_MODE (x
);
8319 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8321 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8322 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8325 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8326 shift and AND produces only copies of the sign bit (C2 is one less
8327 than a power of two), we can do this with just a shift. */
8329 if (GET_CODE (x
) == LSHIFTRT
8330 && CONST_INT_P (XEXP (x
, 1))
8331 /* The shift puts one of the sign bit copies in the least significant
8333 && ((INTVAL (XEXP (x
, 1))
8334 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8335 >= GET_MODE_PRECISION (GET_MODE (x
)))
8336 && exact_log2 (mask
+ 1) >= 0
8337 /* Number of bits left after the shift must be more than the mask
8339 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8340 <= GET_MODE_PRECISION (GET_MODE (x
)))
8341 /* Must be more sign bit copies than the mask needs. */
8342 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8343 >= exact_log2 (mask
+ 1)))
8344 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8345 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8346 - exact_log2 (mask
+ 1)));
8351 /* If we are just looking for the sign bit, we don't need this shift at
8352 all, even if it has a variable count. */
8353 if (val_signbit_p (GET_MODE (x
), mask
))
8354 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8356 /* If this is a shift by a constant, get a mask that contains those bits
8357 that are not copies of the sign bit. We then have two cases: If
8358 MASK only includes those bits, this can be a logical shift, which may
8359 allow simplifications. If MASK is a single-bit field not within
8360 those bits, we are requesting a copy of the sign bit and hence can
8361 shift the sign bit to the appropriate location. */
8363 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8364 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8368 /* If the considered data is wider than HOST_WIDE_INT, we can't
8369 represent a mask for all its bits in a single scalar.
8370 But we only care about the lower bits, so calculate these. */
8372 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8374 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8376 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8377 is the number of bits a full-width mask would have set.
8378 We need only shift if these are fewer than nonzero can
8379 hold. If not, we must keep all bits set in nonzero. */
8381 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8382 < HOST_BITS_PER_WIDE_INT
)
8383 nonzero
>>= INTVAL (XEXP (x
, 1))
8384 + HOST_BITS_PER_WIDE_INT
8385 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8389 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8390 nonzero
>>= INTVAL (XEXP (x
, 1));
8393 if ((mask
& ~nonzero
) == 0)
8395 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8396 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8397 if (GET_CODE (x
) != ASHIFTRT
)
8398 return force_to_mode (x
, mode
, mask
, next_select
);
8401 else if ((i
= exact_log2 (mask
)) >= 0)
8403 x
= simplify_shift_const
8404 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8405 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8407 if (GET_CODE (x
) != ASHIFTRT
)
8408 return force_to_mode (x
, mode
, mask
, next_select
);
8412 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8413 even if the shift count isn't a constant. */
8415 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8416 XEXP (x
, 0), XEXP (x
, 1));
8420 /* If this is a zero- or sign-extension operation that just affects bits
8421 we don't care about, remove it. Be sure the call above returned
8422 something that is still a shift. */
8424 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8425 && CONST_INT_P (XEXP (x
, 1))
8426 && INTVAL (XEXP (x
, 1)) >= 0
8427 && (INTVAL (XEXP (x
, 1))
8428 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8429 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8430 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8431 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8438 /* If the shift count is constant and we can do computations
8439 in the mode of X, compute where the bits we care about are.
8440 Otherwise, we can't do anything. Don't change the mode of
8441 the shift or propagate MODE into the shift, though. */
8442 if (CONST_INT_P (XEXP (x
, 1))
8443 && INTVAL (XEXP (x
, 1)) >= 0)
8445 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8446 GET_MODE (x
), GEN_INT (mask
),
8448 if (temp
&& CONST_INT_P (temp
))
8450 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8451 INTVAL (temp
), next_select
));
8456 /* If we just want the low-order bit, the NEG isn't needed since it
8457 won't change the low-order bit. */
8459 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8461 /* We need any bits less significant than the most significant bit in
8462 MASK since carries from those bits will affect the bits we are
8468 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8469 same as the XOR case above. Ensure that the constant we form is not
8470 wider than the mode of X. */
8472 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8473 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8474 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8475 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8476 < GET_MODE_PRECISION (GET_MODE (x
)))
8477 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8479 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8481 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8482 XEXP (XEXP (x
, 0), 0), temp
);
8483 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8484 temp
, XEXP (XEXP (x
, 0), 1));
8486 return force_to_mode (x
, mode
, mask
, next_select
);
8489 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8490 use the full mask inside the NOT. */
8494 op0
= gen_lowpart_or_truncate (op_mode
,
8495 force_to_mode (XEXP (x
, 0), mode
, mask
,
8497 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8498 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8502 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8503 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8504 which is equal to STORE_FLAG_VALUE. */
8505 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8506 && XEXP (x
, 1) == const0_rtx
8507 && GET_MODE (XEXP (x
, 0)) == mode
8508 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8509 && (nonzero_bits (XEXP (x
, 0), mode
)
8510 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8511 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8516 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8517 written in a narrower mode. We play it safe and do not do so. */
8520 gen_lowpart_or_truncate (GET_MODE (x
),
8521 force_to_mode (XEXP (x
, 1), mode
,
8522 mask
, next_select
)));
8524 gen_lowpart_or_truncate (GET_MODE (x
),
8525 force_to_mode (XEXP (x
, 2), mode
,
8526 mask
, next_select
)));
8533 /* Ensure we return a value of the proper mode. */
8534 return gen_lowpart_or_truncate (mode
, x
);
8537 /* Return nonzero if X is an expression that has one of two values depending on
8538 whether some other value is zero or nonzero. In that case, we return the
8539 value that is being tested, *PTRUE is set to the value if the rtx being
8540 returned has a nonzero value, and *PFALSE is set to the other alternative.
8542 If we return zero, we set *PTRUE and *PFALSE to X. */
8545 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8547 enum machine_mode mode
= GET_MODE (x
);
8548 enum rtx_code code
= GET_CODE (x
);
8549 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8550 unsigned HOST_WIDE_INT nz
;
8552 /* If we are comparing a value against zero, we are done. */
8553 if ((code
== NE
|| code
== EQ
)
8554 && XEXP (x
, 1) == const0_rtx
)
8556 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8557 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8561 /* If this is a unary operation whose operand has one of two values, apply
8562 our opcode to compute those values. */
8563 else if (UNARY_P (x
)
8564 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8566 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8567 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8568 GET_MODE (XEXP (x
, 0)));
8572 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8573 make can't possibly match and would suppress other optimizations. */
8574 else if (code
== COMPARE
)
8577 /* If this is a binary operation, see if either side has only one of two
8578 values. If either one does or if both do and they are conditional on
8579 the same value, compute the new true and false values. */
8580 else if (BINARY_P (x
))
8582 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8583 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8585 if ((cond0
!= 0 || cond1
!= 0)
8586 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8588 /* If if_then_else_cond returned zero, then true/false are the
8589 same rtl. We must copy one of them to prevent invalid rtl
8592 true0
= copy_rtx (true0
);
8593 else if (cond1
== 0)
8594 true1
= copy_rtx (true1
);
8596 if (COMPARISON_P (x
))
8598 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8600 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8605 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8606 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8609 return cond0
? cond0
: cond1
;
8612 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8613 operands is zero when the other is nonzero, and vice-versa,
8614 and STORE_FLAG_VALUE is 1 or -1. */
8616 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8617 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8619 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8621 rtx op0
= XEXP (XEXP (x
, 0), 1);
8622 rtx op1
= XEXP (XEXP (x
, 1), 1);
8624 cond0
= XEXP (XEXP (x
, 0), 0);
8625 cond1
= XEXP (XEXP (x
, 1), 0);
8627 if (COMPARISON_P (cond0
)
8628 && COMPARISON_P (cond1
)
8629 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8630 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8631 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8632 || ((swap_condition (GET_CODE (cond0
))
8633 == reversed_comparison_code (cond1
, NULL
))
8634 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8635 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8636 && ! side_effects_p (x
))
8638 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8639 *pfalse
= simplify_gen_binary (MULT
, mode
,
8641 ? simplify_gen_unary (NEG
, mode
,
8649 /* Similarly for MULT, AND and UMIN, except that for these the result
8651 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8652 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8653 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8655 cond0
= XEXP (XEXP (x
, 0), 0);
8656 cond1
= XEXP (XEXP (x
, 1), 0);
8658 if (COMPARISON_P (cond0
)
8659 && COMPARISON_P (cond1
)
8660 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8661 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8662 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8663 || ((swap_condition (GET_CODE (cond0
))
8664 == reversed_comparison_code (cond1
, NULL
))
8665 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8666 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8667 && ! side_effects_p (x
))
8669 *ptrue
= *pfalse
= const0_rtx
;
8675 else if (code
== IF_THEN_ELSE
)
8677 /* If we have IF_THEN_ELSE already, extract the condition and
8678 canonicalize it if it is NE or EQ. */
8679 cond0
= XEXP (x
, 0);
8680 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8681 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8682 return XEXP (cond0
, 0);
8683 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8685 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8686 return XEXP (cond0
, 0);
8692 /* If X is a SUBREG, we can narrow both the true and false values
8693 if the inner expression, if there is a condition. */
8694 else if (code
== SUBREG
8695 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8698 true0
= simplify_gen_subreg (mode
, true0
,
8699 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8700 false0
= simplify_gen_subreg (mode
, false0
,
8701 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8702 if (true0
&& false0
)
8710 /* If X is a constant, this isn't special and will cause confusions
8711 if we treat it as such. Likewise if it is equivalent to a constant. */
8712 else if (CONSTANT_P (x
)
8713 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8716 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8717 will be least confusing to the rest of the compiler. */
8718 else if (mode
== BImode
)
8720 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8724 /* If X is known to be either 0 or -1, those are the true and
8725 false values when testing X. */
8726 else if (x
== constm1_rtx
|| x
== const0_rtx
8727 || (mode
!= VOIDmode
8728 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8730 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8734 /* Likewise for 0 or a single bit. */
8735 else if (HWI_COMPUTABLE_MODE_P (mode
)
8736 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8738 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8742 /* Otherwise fail; show no condition with true and false values the same. */
8743 *ptrue
= *pfalse
= x
;
8747 /* Return the value of expression X given the fact that condition COND
8748 is known to be true when applied to REG as its first operand and VAL
8749 as its second. X is known to not be shared and so can be modified in
8752 We only handle the simplest cases, and specifically those cases that
8753 arise with IF_THEN_ELSE expressions. */
8756 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8758 enum rtx_code code
= GET_CODE (x
);
8763 if (side_effects_p (x
))
8766 /* If either operand of the condition is a floating point value,
8767 then we have to avoid collapsing an EQ comparison. */
8769 && rtx_equal_p (x
, reg
)
8770 && ! FLOAT_MODE_P (GET_MODE (x
))
8771 && ! FLOAT_MODE_P (GET_MODE (val
)))
8774 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8777 /* If X is (abs REG) and we know something about REG's relationship
8778 with zero, we may be able to simplify this. */
8780 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8783 case GE
: case GT
: case EQ
:
8786 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8788 GET_MODE (XEXP (x
, 0)));
8793 /* The only other cases we handle are MIN, MAX, and comparisons if the
8794 operands are the same as REG and VAL. */
8796 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8798 if (rtx_equal_p (XEXP (x
, 0), val
))
8799 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8801 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8803 if (COMPARISON_P (x
))
8805 if (comparison_dominates_p (cond
, code
))
8806 return const_true_rtx
;
8808 code
= reversed_comparison_code (x
, NULL
);
8810 && comparison_dominates_p (cond
, code
))
8815 else if (code
== SMAX
|| code
== SMIN
8816 || code
== UMIN
|| code
== UMAX
)
8818 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8820 /* Do not reverse the condition when it is NE or EQ.
8821 This is because we cannot conclude anything about
8822 the value of 'SMAX (x, y)' when x is not equal to y,
8823 but we can when x equals y. */
8824 if ((code
== SMAX
|| code
== UMAX
)
8825 && ! (cond
== EQ
|| cond
== NE
))
8826 cond
= reverse_condition (cond
);
8831 return unsignedp
? x
: XEXP (x
, 1);
8833 return unsignedp
? x
: XEXP (x
, 0);
8835 return unsignedp
? XEXP (x
, 1) : x
;
8837 return unsignedp
? XEXP (x
, 0) : x
;
8844 else if (code
== SUBREG
)
8846 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8847 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8849 if (SUBREG_REG (x
) != r
)
8851 /* We must simplify subreg here, before we lose track of the
8852 original inner_mode. */
8853 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8854 inner_mode
, SUBREG_BYTE (x
));
8858 SUBST (SUBREG_REG (x
), r
);
8863 /* We don't have to handle SIGN_EXTEND here, because even in the
8864 case of replacing something with a modeless CONST_INT, a
8865 CONST_INT is already (supposed to be) a valid sign extension for
8866 its narrower mode, which implies it's already properly
8867 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8868 story is different. */
8869 else if (code
== ZERO_EXTEND
)
8871 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8872 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8874 if (XEXP (x
, 0) != r
)
8876 /* We must simplify the zero_extend here, before we lose
8877 track of the original inner_mode. */
8878 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8883 SUBST (XEXP (x
, 0), r
);
8889 fmt
= GET_RTX_FORMAT (code
);
8890 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8893 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8894 else if (fmt
[i
] == 'E')
8895 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8896 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8903 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8904 assignment as a field assignment. */
8907 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8909 if (x
== y
|| rtx_equal_p (x
, y
))
8912 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8915 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8916 Note that all SUBREGs of MEM are paradoxical; otherwise they
8917 would have been rewritten. */
8918 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8919 && MEM_P (SUBREG_REG (y
))
8920 && rtx_equal_p (SUBREG_REG (y
),
8921 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8924 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8925 && MEM_P (SUBREG_REG (x
))
8926 && rtx_equal_p (SUBREG_REG (x
),
8927 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8930 /* We used to see if get_last_value of X and Y were the same but that's
8931 not correct. In one direction, we'll cause the assignment to have
8932 the wrong destination and in the case, we'll import a register into this
8933 insn that might have already have been dead. So fail if none of the
8934 above cases are true. */
8938 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8939 Return that assignment if so.
8941 We only handle the most common cases. */
8944 make_field_assignment (rtx x
)
8946 rtx dest
= SET_DEST (x
);
8947 rtx src
= SET_SRC (x
);
8952 unsigned HOST_WIDE_INT len
;
8954 enum machine_mode mode
;
8956 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8957 a clear of a one-bit field. We will have changed it to
8958 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8961 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8962 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8963 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8964 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8966 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8969 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8973 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8974 && subreg_lowpart_p (XEXP (src
, 0))
8975 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8976 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8977 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8978 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8979 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8980 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8982 assign
= make_extraction (VOIDmode
, dest
, 0,
8983 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8986 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8990 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8992 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8993 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8994 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8996 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8999 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9003 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9004 SRC is an AND with all bits of that field set, then we can discard
9006 if (GET_CODE (dest
) == ZERO_EXTRACT
9007 && CONST_INT_P (XEXP (dest
, 1))
9008 && GET_CODE (src
) == AND
9009 && CONST_INT_P (XEXP (src
, 1)))
9011 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9012 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9013 unsigned HOST_WIDE_INT ze_mask
;
9015 if (width
>= HOST_BITS_PER_WIDE_INT
)
9018 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9020 /* Complete overlap. We can remove the source AND. */
9021 if ((and_mask
& ze_mask
) == ze_mask
)
9022 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9024 /* Partial overlap. We can reduce the source AND. */
9025 if ((and_mask
& ze_mask
) != and_mask
)
9027 mode
= GET_MODE (src
);
9028 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9029 gen_int_mode (and_mask
& ze_mask
, mode
));
9030 return gen_rtx_SET (VOIDmode
, dest
, src
);
9034 /* The other case we handle is assignments into a constant-position
9035 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9036 a mask that has all one bits except for a group of zero bits and
9037 OTHER is known to have zeros where C1 has ones, this is such an
9038 assignment. Compute the position and length from C1. Shift OTHER
9039 to the appropriate position, force it to the required mode, and
9040 make the extraction. Check for the AND in both operands. */
9042 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9045 rhs
= expand_compound_operation (XEXP (src
, 0));
9046 lhs
= expand_compound_operation (XEXP (src
, 1));
9048 if (GET_CODE (rhs
) == AND
9049 && CONST_INT_P (XEXP (rhs
, 1))
9050 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9051 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9052 else if (GET_CODE (lhs
) == AND
9053 && CONST_INT_P (XEXP (lhs
, 1))
9054 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9055 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9059 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9060 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9061 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9062 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9065 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9069 /* The mode to use for the source is the mode of the assignment, or of
9070 what is inside a possible STRICT_LOW_PART. */
9071 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9072 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9074 /* Shift OTHER right POS places and make it the source, restricting it
9075 to the proper length and mode. */
9077 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9081 src
= force_to_mode (src
, mode
,
9082 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9083 ? ~(unsigned HOST_WIDE_INT
) 0
9084 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9087 /* If SRC is masked by an AND that does not make a difference in
9088 the value being stored, strip it. */
9089 if (GET_CODE (assign
) == ZERO_EXTRACT
9090 && CONST_INT_P (XEXP (assign
, 1))
9091 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9092 && GET_CODE (src
) == AND
9093 && CONST_INT_P (XEXP (src
, 1))
9094 && UINTVAL (XEXP (src
, 1))
9095 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9096 src
= XEXP (src
, 0);
9098 return gen_rtx_SET (VOIDmode
, assign
, src
);
9101 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9105 apply_distributive_law (rtx x
)
9107 enum rtx_code code
= GET_CODE (x
);
9108 enum rtx_code inner_code
;
9109 rtx lhs
, rhs
, other
;
9112 /* Distributivity is not true for floating point as it can change the
9113 value. So we don't do it unless -funsafe-math-optimizations. */
9114 if (FLOAT_MODE_P (GET_MODE (x
))
9115 && ! flag_unsafe_math_optimizations
)
9118 /* The outer operation can only be one of the following: */
9119 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9120 && code
!= PLUS
&& code
!= MINUS
)
9126 /* If either operand is a primitive we can't do anything, so get out
9128 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9131 lhs
= expand_compound_operation (lhs
);
9132 rhs
= expand_compound_operation (rhs
);
9133 inner_code
= GET_CODE (lhs
);
9134 if (inner_code
!= GET_CODE (rhs
))
9137 /* See if the inner and outer operations distribute. */
9144 /* These all distribute except over PLUS. */
9145 if (code
== PLUS
|| code
== MINUS
)
9150 if (code
!= PLUS
&& code
!= MINUS
)
9155 /* This is also a multiply, so it distributes over everything. */
9158 /* This used to handle SUBREG, but this turned out to be counter-
9159 productive, since (subreg (op ...)) usually is not handled by
9160 insn patterns, and this "optimization" therefore transformed
9161 recognizable patterns into unrecognizable ones. Therefore the
9162 SUBREG case was removed from here.
9164 It is possible that distributing SUBREG over arithmetic operations
9165 leads to an intermediate result than can then be optimized further,
9166 e.g. by moving the outer SUBREG to the other side of a SET as done
9167 in simplify_set. This seems to have been the original intent of
9168 handling SUBREGs here.
9170 However, with current GCC this does not appear to actually happen,
9171 at least on major platforms. If some case is found where removing
9172 the SUBREG case here prevents follow-on optimizations, distributing
9173 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9179 /* Set LHS and RHS to the inner operands (A and B in the example
9180 above) and set OTHER to the common operand (C in the example).
9181 There is only one way to do this unless the inner operation is
9183 if (COMMUTATIVE_ARITH_P (lhs
)
9184 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9185 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9186 else if (COMMUTATIVE_ARITH_P (lhs
)
9187 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9188 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9189 else if (COMMUTATIVE_ARITH_P (lhs
)
9190 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9191 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9192 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9193 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9197 /* Form the new inner operation, seeing if it simplifies first. */
9198 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9200 /* There is one exception to the general way of distributing:
9201 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9202 if (code
== XOR
&& inner_code
== IOR
)
9205 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9208 /* We may be able to continuing distributing the result, so call
9209 ourselves recursively on the inner operation before forming the
9210 outer operation, which we return. */
9211 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9212 apply_distributive_law (tem
), other
);
9215 /* See if X is of the form (* (+ A B) C), and if so convert to
9216 (+ (* A C) (* B C)) and try to simplify.
9218 Most of the time, this results in no change. However, if some of
9219 the operands are the same or inverses of each other, simplifications
9222 For example, (and (ior A B) (not B)) can occur as the result of
9223 expanding a bit field assignment. When we apply the distributive
9224 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9225 which then simplifies to (and (A (not B))).
9227 Note that no checks happen on the validity of applying the inverse
9228 distributive law. This is pointless since we can do it in the
9229 few places where this routine is called.
9231 N is the index of the term that is decomposed (the arithmetic operation,
9232 i.e. (+ A B) in the first example above). !N is the index of the term that
9233 is distributed, i.e. of C in the first example above. */
9235 distribute_and_simplify_rtx (rtx x
, int n
)
9237 enum machine_mode mode
;
9238 enum rtx_code outer_code
, inner_code
;
9239 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9241 /* Distributivity is not true for floating point as it can change the
9242 value. So we don't do it unless -funsafe-math-optimizations. */
9243 if (FLOAT_MODE_P (GET_MODE (x
))
9244 && ! flag_unsafe_math_optimizations
)
9247 decomposed
= XEXP (x
, n
);
9248 if (!ARITHMETIC_P (decomposed
))
9251 mode
= GET_MODE (x
);
9252 outer_code
= GET_CODE (x
);
9253 distributed
= XEXP (x
, !n
);
9255 inner_code
= GET_CODE (decomposed
);
9256 inner_op0
= XEXP (decomposed
, 0);
9257 inner_op1
= XEXP (decomposed
, 1);
9259 /* Special case (and (xor B C) (not A)), which is equivalent to
9260 (xor (ior A B) (ior A C)) */
9261 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9263 distributed
= XEXP (distributed
, 0);
9269 /* Distribute the second term. */
9270 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9271 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9275 /* Distribute the first term. */
9276 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9277 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9280 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9282 if (GET_CODE (tmp
) != outer_code
9283 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9284 < set_src_cost (x
, optimize_this_for_speed_p
)))
9290 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9291 in MODE. Return an equivalent form, if different from (and VAROP
9292 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9295 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9296 unsigned HOST_WIDE_INT constop
)
9298 unsigned HOST_WIDE_INT nonzero
;
9299 unsigned HOST_WIDE_INT orig_constop
;
9304 orig_constop
= constop
;
9305 if (GET_CODE (varop
) == CLOBBER
)
9308 /* Simplify VAROP knowing that we will be only looking at some of the
9311 Note by passing in CONSTOP, we guarantee that the bits not set in
9312 CONSTOP are not significant and will never be examined. We must
9313 ensure that is the case by explicitly masking out those bits
9314 before returning. */
9315 varop
= force_to_mode (varop
, mode
, constop
, 0);
9317 /* If VAROP is a CLOBBER, we will fail so return it. */
9318 if (GET_CODE (varop
) == CLOBBER
)
9321 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9322 to VAROP and return the new constant. */
9323 if (CONST_INT_P (varop
))
9324 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9326 /* See what bits may be nonzero in VAROP. Unlike the general case of
9327 a call to nonzero_bits, here we don't care about bits outside
9330 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9332 /* Turn off all bits in the constant that are known to already be zero.
9333 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9334 which is tested below. */
9338 /* If we don't have any bits left, return zero. */
9342 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9343 a power of two, we can replace this with an ASHIFT. */
9344 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9345 && (i
= exact_log2 (constop
)) >= 0)
9346 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9348 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9349 or XOR, then try to apply the distributive law. This may eliminate
9350 operations if either branch can be simplified because of the AND.
9351 It may also make some cases more complex, but those cases probably
9352 won't match a pattern either with or without this. */
9354 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9358 apply_distributive_law
9359 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9360 simplify_and_const_int (NULL_RTX
,
9364 simplify_and_const_int (NULL_RTX
,
9369 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9370 the AND and see if one of the operands simplifies to zero. If so, we
9371 may eliminate it. */
9373 if (GET_CODE (varop
) == PLUS
9374 && exact_log2 (constop
+ 1) >= 0)
9378 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9379 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9380 if (o0
== const0_rtx
)
9382 if (o1
== const0_rtx
)
9386 /* Make a SUBREG if necessary. If we can't make it, fail. */
9387 varop
= gen_lowpart (mode
, varop
);
9388 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9391 /* If we are only masking insignificant bits, return VAROP. */
9392 if (constop
== nonzero
)
9395 if (varop
== orig_varop
&& constop
== orig_constop
)
9398 /* Otherwise, return an AND. */
9399 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9403 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9406 Return an equivalent form, if different from X. Otherwise, return X. If
9407 X is zero, we are to always construct the equivalent form. */
9410 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9411 unsigned HOST_WIDE_INT constop
)
9413 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9418 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9419 gen_int_mode (constop
, mode
));
9420 if (GET_MODE (x
) != mode
)
9421 x
= gen_lowpart (mode
, x
);
9425 /* Given a REG, X, compute which bits in X can be nonzero.
9426 We don't care about bits outside of those defined in MODE.
9428 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9429 a shift, AND, or zero_extract, we can do better. */
9432 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9433 const_rtx known_x ATTRIBUTE_UNUSED
,
9434 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9435 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9436 unsigned HOST_WIDE_INT
*nonzero
)
9441 /* If X is a register whose nonzero bits value is current, use it.
9442 Otherwise, if X is a register whose value we can find, use that
9443 value. Otherwise, use the previously-computed global nonzero bits
9444 for this register. */
9446 rsp
= ®_stat
[REGNO (x
)];
9447 if (rsp
->last_set_value
!= 0
9448 && (rsp
->last_set_mode
== mode
9449 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9450 && GET_MODE_CLASS (mode
) == MODE_INT
))
9451 && ((rsp
->last_set_label
>= label_tick_ebb_start
9452 && rsp
->last_set_label
< label_tick
)
9453 || (rsp
->last_set_label
== label_tick
9454 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9455 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9456 && REG_N_SETS (REGNO (x
)) == 1
9458 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9460 *nonzero
&= rsp
->last_set_nonzero_bits
;
9464 tem
= get_last_value (x
);
9468 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9469 /* If X is narrower than MODE and TEM is a non-negative
9470 constant that would appear negative in the mode of X,
9471 sign-extend it for use in reg_nonzero_bits because some
9472 machines (maybe most) will actually do the sign-extension
9473 and this is the conservative approach.
9475 ??? For 2.5, try to tighten up the MD files in this regard
9476 instead of this kludge. */
9478 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9479 && CONST_INT_P (tem
)
9481 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9482 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9486 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9488 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9490 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9491 /* We don't know anything about the upper bits. */
9492 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9499 /* Return the number of bits at the high-order end of X that are known to
9500 be equal to the sign bit. X will be used in mode MODE; if MODE is
9501 VOIDmode, X will be used in its own mode. The returned value will always
9502 be between 1 and the number of bits in MODE. */
9505 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9506 const_rtx known_x ATTRIBUTE_UNUSED
,
9507 enum machine_mode known_mode
9509 unsigned int known_ret ATTRIBUTE_UNUSED
,
9510 unsigned int *result
)
9515 rsp
= ®_stat
[REGNO (x
)];
9516 if (rsp
->last_set_value
!= 0
9517 && rsp
->last_set_mode
== mode
9518 && ((rsp
->last_set_label
>= label_tick_ebb_start
9519 && rsp
->last_set_label
< label_tick
)
9520 || (rsp
->last_set_label
== label_tick
9521 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9522 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9523 && REG_N_SETS (REGNO (x
)) == 1
9525 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9527 *result
= rsp
->last_set_sign_bit_copies
;
9531 tem
= get_last_value (x
);
9535 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9536 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9537 *result
= rsp
->sign_bit_copies
;
9542 /* Return the number of "extended" bits there are in X, when interpreted
9543 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9544 unsigned quantities, this is the number of high-order zero bits.
9545 For signed quantities, this is the number of copies of the sign bit
9546 minus 1. In both case, this function returns the number of "spare"
9547 bits. For example, if two quantities for which this function returns
9548 at least 1 are added, the addition is known not to overflow.
9550 This function will always return 0 unless called during combine, which
9551 implies that it must be called from a define_split. */
9554 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9556 if (nonzero_sign_valid
== 0)
9560 ? (HWI_COMPUTABLE_MODE_P (mode
)
9561 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9562 - floor_log2 (nonzero_bits (x
, mode
)))
9564 : num_sign_bit_copies (x
, mode
) - 1);
9567 /* This function is called from `simplify_shift_const' to merge two
9568 outer operations. Specifically, we have already found that we need
9569 to perform operation *POP0 with constant *PCONST0 at the outermost
9570 position. We would now like to also perform OP1 with constant CONST1
9571 (with *POP0 being done last).
9573 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9574 the resulting operation. *PCOMP_P is set to 1 if we would need to
9575 complement the innermost operand, otherwise it is unchanged.
9577 MODE is the mode in which the operation will be done. No bits outside
9578 the width of this mode matter. It is assumed that the width of this mode
9579 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9581 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9582 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9583 result is simply *PCONST0.
9585 If the resulting operation cannot be expressed as one operation, we
9586 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9589 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9591 enum rtx_code op0
= *pop0
;
9592 HOST_WIDE_INT const0
= *pconst0
;
9594 const0
&= GET_MODE_MASK (mode
);
9595 const1
&= GET_MODE_MASK (mode
);
9597 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9601 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9604 if (op1
== UNKNOWN
|| op0
== SET
)
9607 else if (op0
== UNKNOWN
)
9608 op0
= op1
, const0
= const1
;
9610 else if (op0
== op1
)
9634 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9635 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9638 /* If the two constants aren't the same, we can't do anything. The
9639 remaining six cases can all be done. */
9640 else if (const0
!= const1
)
9648 /* (a & b) | b == b */
9650 else /* op1 == XOR */
9651 /* (a ^ b) | b == a | b */
9657 /* (a & b) ^ b == (~a) & b */
9658 op0
= AND
, *pcomp_p
= 1;
9659 else /* op1 == IOR */
9660 /* (a | b) ^ b == a & ~b */
9661 op0
= AND
, const0
= ~const0
;
9666 /* (a | b) & b == b */
9668 else /* op1 == XOR */
9669 /* (a ^ b) & b) == (~a) & b */
9676 /* Check for NO-OP cases. */
9677 const0
&= GET_MODE_MASK (mode
);
9679 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9681 else if (const0
== 0 && op0
== AND
)
9683 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9689 /* ??? Slightly redundant with the above mask, but not entirely.
9690 Moving this above means we'd have to sign-extend the mode mask
9691 for the final test. */
9692 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9693 *pconst0
= trunc_int_for_mode (const0
, mode
);
9698 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9699 the shift in. The original shift operation CODE is performed on OP in
9700 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9701 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9702 result of the shift is subject to operation OUTER_CODE with operand
9705 static enum machine_mode
9706 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9707 enum machine_mode orig_mode
, enum machine_mode mode
,
9708 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9710 if (orig_mode
== mode
)
9712 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9714 /* In general we can't perform in wider mode for right shift and rotate. */
9718 /* We can still widen if the bits brought in from the left are identical
9719 to the sign bit of ORIG_MODE. */
9720 if (num_sign_bit_copies (op
, mode
)
9721 > (unsigned) (GET_MODE_PRECISION (mode
)
9722 - GET_MODE_PRECISION (orig_mode
)))
9727 /* Similarly here but with zero bits. */
9728 if (HWI_COMPUTABLE_MODE_P (mode
)
9729 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9732 /* We can also widen if the bits brought in will be masked off. This
9733 operation is performed in ORIG_MODE. */
9734 if (outer_code
== AND
)
9736 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9739 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9755 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9756 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9757 if we cannot simplify it. Otherwise, return a simplified value.
9759 The shift is normally computed in the widest mode we find in VAROP, as
9760 long as it isn't a different number of words than RESULT_MODE. Exceptions
9761 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9764 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9765 rtx varop
, int orig_count
)
9767 enum rtx_code orig_code
= code
;
9768 rtx orig_varop
= varop
;
9770 enum machine_mode mode
= result_mode
;
9771 enum machine_mode shift_mode
, tmode
;
9772 unsigned int mode_words
9773 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9774 /* We form (outer_op (code varop count) (outer_const)). */
9775 enum rtx_code outer_op
= UNKNOWN
;
9776 HOST_WIDE_INT outer_const
= 0;
9777 int complement_p
= 0;
9780 /* Make sure and truncate the "natural" shift on the way in. We don't
9781 want to do this inside the loop as it makes it more difficult to
9783 if (SHIFT_COUNT_TRUNCATED
)
9784 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9786 /* If we were given an invalid count, don't do anything except exactly
9787 what was requested. */
9789 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9794 /* Unless one of the branches of the `if' in this loop does a `continue',
9795 we will `break' the loop after the `if'. */
9799 /* If we have an operand of (clobber (const_int 0)), fail. */
9800 if (GET_CODE (varop
) == CLOBBER
)
9803 /* Convert ROTATERT to ROTATE. */
9804 if (code
== ROTATERT
)
9806 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9808 if (VECTOR_MODE_P (result_mode
))
9809 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9811 count
= bitsize
- count
;
9814 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9815 mode
, outer_op
, outer_const
);
9817 /* Handle cases where the count is greater than the size of the mode
9818 minus 1. For ASHIFT, use the size minus one as the count (this can
9819 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9820 take the count modulo the size. For other shifts, the result is
9823 Since these shifts are being produced by the compiler by combining
9824 multiple operations, each of which are defined, we know what the
9825 result is supposed to be. */
9827 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9829 if (code
== ASHIFTRT
)
9830 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9831 else if (code
== ROTATE
|| code
== ROTATERT
)
9832 count
%= GET_MODE_PRECISION (shift_mode
);
9835 /* We can't simply return zero because there may be an
9843 /* If we discovered we had to complement VAROP, leave. Making a NOT
9844 here would cause an infinite loop. */
9848 /* An arithmetic right shift of a quantity known to be -1 or 0
9850 if (code
== ASHIFTRT
9851 && (num_sign_bit_copies (varop
, shift_mode
)
9852 == GET_MODE_PRECISION (shift_mode
)))
9858 /* If we are doing an arithmetic right shift and discarding all but
9859 the sign bit copies, this is equivalent to doing a shift by the
9860 bitsize minus one. Convert it into that shift because it will often
9861 allow other simplifications. */
9863 if (code
== ASHIFTRT
9864 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9865 >= GET_MODE_PRECISION (shift_mode
)))
9866 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9868 /* We simplify the tests below and elsewhere by converting
9869 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9870 `make_compound_operation' will convert it to an ASHIFTRT for
9871 those machines (such as VAX) that don't have an LSHIFTRT. */
9872 if (code
== ASHIFTRT
9873 && val_signbit_known_clear_p (shift_mode
,
9874 nonzero_bits (varop
, shift_mode
)))
9877 if (((code
== LSHIFTRT
9878 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9879 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9881 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9882 && !((nonzero_bits (varop
, shift_mode
) << count
)
9883 & GET_MODE_MASK (shift_mode
))))
9884 && !side_effects_p (varop
))
9887 switch (GET_CODE (varop
))
9893 new_rtx
= expand_compound_operation (varop
);
9894 if (new_rtx
!= varop
)
9902 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9903 minus the width of a smaller mode, we can do this with a
9904 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9905 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9906 && ! mode_dependent_address_p (XEXP (varop
, 0),
9907 MEM_ADDR_SPACE (varop
))
9908 && ! MEM_VOLATILE_P (varop
)
9909 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9910 MODE_INT
, 1)) != BLKmode
)
9912 new_rtx
= adjust_address_nv (varop
, tmode
,
9913 BYTES_BIG_ENDIAN
? 0
9914 : count
/ BITS_PER_UNIT
);
9916 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9917 : ZERO_EXTEND
, mode
, new_rtx
);
9924 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9925 the same number of words as what we've seen so far. Then store
9926 the widest mode in MODE. */
9927 if (subreg_lowpart_p (varop
)
9928 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9929 > GET_MODE_SIZE (GET_MODE (varop
)))
9930 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9931 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9933 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9934 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9936 varop
= SUBREG_REG (varop
);
9937 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9938 mode
= GET_MODE (varop
);
9944 /* Some machines use MULT instead of ASHIFT because MULT
9945 is cheaper. But it is still better on those machines to
9946 merge two shifts into one. */
9947 if (CONST_INT_P (XEXP (varop
, 1))
9948 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9951 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9953 GEN_INT (exact_log2 (
9954 UINTVAL (XEXP (varop
, 1)))));
9960 /* Similar, for when divides are cheaper. */
9961 if (CONST_INT_P (XEXP (varop
, 1))
9962 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9965 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9967 GEN_INT (exact_log2 (
9968 UINTVAL (XEXP (varop
, 1)))));
9974 /* If we are extracting just the sign bit of an arithmetic
9975 right shift, that shift is not needed. However, the sign
9976 bit of a wider mode may be different from what would be
9977 interpreted as the sign bit in a narrower mode, so, if
9978 the result is narrower, don't discard the shift. */
9979 if (code
== LSHIFTRT
9980 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9981 && (GET_MODE_BITSIZE (result_mode
)
9982 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9984 varop
= XEXP (varop
, 0);
9988 /* ... fall through ... */
9993 /* Here we have two nested shifts. The result is usually the
9994 AND of a new shift with a mask. We compute the result below. */
9995 if (CONST_INT_P (XEXP (varop
, 1))
9996 && INTVAL (XEXP (varop
, 1)) >= 0
9997 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
9998 && HWI_COMPUTABLE_MODE_P (result_mode
)
9999 && HWI_COMPUTABLE_MODE_P (mode
)
10000 && !VECTOR_MODE_P (result_mode
))
10002 enum rtx_code first_code
= GET_CODE (varop
);
10003 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10004 unsigned HOST_WIDE_INT mask
;
10007 /* We have one common special case. We can't do any merging if
10008 the inner code is an ASHIFTRT of a smaller mode. However, if
10009 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10010 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10011 we can convert it to
10012 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10013 This simplifies certain SIGN_EXTEND operations. */
10014 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10015 && count
== (GET_MODE_PRECISION (result_mode
)
10016 - GET_MODE_PRECISION (GET_MODE (varop
))))
10018 /* C3 has the low-order C1 bits zero. */
10020 mask
= GET_MODE_MASK (mode
)
10021 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10023 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10024 XEXP (varop
, 0), mask
);
10025 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10027 count
= first_count
;
10032 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10033 than C1 high-order bits equal to the sign bit, we can convert
10034 this to either an ASHIFT or an ASHIFTRT depending on the
10037 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10039 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10040 && GET_MODE (varop
) == shift_mode
10041 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10044 varop
= XEXP (varop
, 0);
10045 count
-= first_count
;
10055 /* There are some cases we can't do. If CODE is ASHIFTRT,
10056 we can only do this if FIRST_CODE is also ASHIFTRT.
10058 We can't do the case when CODE is ROTATE and FIRST_CODE is
10061 If the mode of this shift is not the mode of the outer shift,
10062 we can't do this if either shift is a right shift or ROTATE.
10064 Finally, we can't do any of these if the mode is too wide
10065 unless the codes are the same.
10067 Handle the case where the shift codes are the same
10070 if (code
== first_code
)
10072 if (GET_MODE (varop
) != result_mode
10073 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10074 || code
== ROTATE
))
10077 count
+= first_count
;
10078 varop
= XEXP (varop
, 0);
10082 if (code
== ASHIFTRT
10083 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10084 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10085 || (GET_MODE (varop
) != result_mode
10086 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10087 || first_code
== ROTATE
10088 || code
== ROTATE
)))
10091 /* To compute the mask to apply after the shift, shift the
10092 nonzero bits of the inner shift the same way the
10093 outer shift will. */
10095 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10098 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10101 /* Give up if we can't compute an outer operation to use. */
10103 || !CONST_INT_P (mask_rtx
)
10104 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10106 result_mode
, &complement_p
))
10109 /* If the shifts are in the same direction, we add the
10110 counts. Otherwise, we subtract them. */
10111 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10112 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10113 count
+= first_count
;
10115 count
-= first_count
;
10117 /* If COUNT is positive, the new shift is usually CODE,
10118 except for the two exceptions below, in which case it is
10119 FIRST_CODE. If the count is negative, FIRST_CODE should
10122 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10123 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10125 else if (count
< 0)
10126 code
= first_code
, count
= -count
;
10128 varop
= XEXP (varop
, 0);
10132 /* If we have (A << B << C) for any shift, we can convert this to
10133 (A << C << B). This wins if A is a constant. Only try this if
10134 B is not a constant. */
10136 else if (GET_CODE (varop
) == code
10137 && CONST_INT_P (XEXP (varop
, 0))
10138 && !CONST_INT_P (XEXP (varop
, 1)))
10140 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10143 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10150 if (VECTOR_MODE_P (mode
))
10153 /* Make this fit the case below. */
10154 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10160 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10161 with C the size of VAROP - 1 and the shift is logical if
10162 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10163 we have an (le X 0) operation. If we have an arithmetic shift
10164 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10165 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10167 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10168 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10169 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10170 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10171 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10172 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10175 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10178 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10179 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10184 /* If we have (shift (logical)), move the logical to the outside
10185 to allow it to possibly combine with another logical and the
10186 shift to combine with another shift. This also canonicalizes to
10187 what a ZERO_EXTRACT looks like. Also, some machines have
10188 (and (shift)) insns. */
10190 if (CONST_INT_P (XEXP (varop
, 1))
10191 /* We can't do this if we have (ashiftrt (xor)) and the
10192 constant has its sign bit set in shift_mode. */
10193 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10194 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10196 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10198 GEN_INT (count
))) != 0
10199 && CONST_INT_P (new_rtx
)
10200 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10201 INTVAL (new_rtx
), result_mode
, &complement_p
))
10203 varop
= XEXP (varop
, 0);
10207 /* If we can't do that, try to simplify the shift in each arm of the
10208 logical expression, make a new logical expression, and apply
10209 the inverse distributive law. This also can't be done
10210 for some (ashiftrt (xor)). */
10211 if (CONST_INT_P (XEXP (varop
, 1))
10212 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10213 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10216 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10217 XEXP (varop
, 0), count
);
10218 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10219 XEXP (varop
, 1), count
);
10221 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10223 varop
= apply_distributive_law (varop
);
10231 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10232 says that the sign bit can be tested, FOO has mode MODE, C is
10233 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10234 that may be nonzero. */
10235 if (code
== LSHIFTRT
10236 && XEXP (varop
, 1) == const0_rtx
10237 && GET_MODE (XEXP (varop
, 0)) == result_mode
10238 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10239 && HWI_COMPUTABLE_MODE_P (result_mode
)
10240 && STORE_FLAG_VALUE
== -1
10241 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10242 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10245 varop
= XEXP (varop
, 0);
10252 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10253 than the number of bits in the mode is equivalent to A. */
10254 if (code
== LSHIFTRT
10255 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10256 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10258 varop
= XEXP (varop
, 0);
10263 /* NEG commutes with ASHIFT since it is multiplication. Move the
10264 NEG outside to allow shifts to combine. */
10266 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10269 varop
= XEXP (varop
, 0);
10275 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10276 is one less than the number of bits in the mode is
10277 equivalent to (xor A 1). */
10278 if (code
== LSHIFTRT
10279 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10280 && XEXP (varop
, 1) == constm1_rtx
10281 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10282 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10286 varop
= XEXP (varop
, 0);
10290 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10291 that might be nonzero in BAR are those being shifted out and those
10292 bits are known zero in FOO, we can replace the PLUS with FOO.
10293 Similarly in the other operand order. This code occurs when
10294 we are computing the size of a variable-size array. */
10296 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10297 && count
< HOST_BITS_PER_WIDE_INT
10298 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10299 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10300 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10302 varop
= XEXP (varop
, 0);
10305 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10306 && count
< HOST_BITS_PER_WIDE_INT
10307 && HWI_COMPUTABLE_MODE_P (result_mode
)
10308 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10310 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10311 & nonzero_bits (XEXP (varop
, 1),
10314 varop
= XEXP (varop
, 1);
10318 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10320 && CONST_INT_P (XEXP (varop
, 1))
10321 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10323 GEN_INT (count
))) != 0
10324 && CONST_INT_P (new_rtx
)
10325 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10326 INTVAL (new_rtx
), result_mode
, &complement_p
))
10328 varop
= XEXP (varop
, 0);
10332 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10333 signbit', and attempt to change the PLUS to an XOR and move it to
10334 the outer operation as is done above in the AND/IOR/XOR case
10335 leg for shift(logical). See details in logical handling above
10336 for reasoning in doing so. */
10337 if (code
== LSHIFTRT
10338 && CONST_INT_P (XEXP (varop
, 1))
10339 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10340 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10342 GEN_INT (count
))) != 0
10343 && CONST_INT_P (new_rtx
)
10344 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10345 INTVAL (new_rtx
), result_mode
, &complement_p
))
10347 varop
= XEXP (varop
, 0);
10354 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10355 with C the size of VAROP - 1 and the shift is logical if
10356 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10357 we have a (gt X 0) operation. If the shift is arithmetic with
10358 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10359 we have a (neg (gt X 0)) operation. */
10361 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10362 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10363 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10364 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10365 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10366 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10367 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10370 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10373 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10374 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10381 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10382 if the truncate does not affect the value. */
10383 if (code
== LSHIFTRT
10384 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10385 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10386 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10387 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10388 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10390 rtx varop_inner
= XEXP (varop
, 0);
10393 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10394 XEXP (varop_inner
, 0),
10396 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10397 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10410 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10411 outer_op
, outer_const
);
10413 /* We have now finished analyzing the shift. The result should be
10414 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10415 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10416 to the result of the shift. OUTER_CONST is the relevant constant,
10417 but we must turn off all bits turned off in the shift. */
10419 if (outer_op
== UNKNOWN
10420 && orig_code
== code
&& orig_count
== count
10421 && varop
== orig_varop
10422 && shift_mode
== GET_MODE (varop
))
10425 /* Make a SUBREG if necessary. If we can't make it, fail. */
10426 varop
= gen_lowpart (shift_mode
, varop
);
10427 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10430 /* If we have an outer operation and we just made a shift, it is
10431 possible that we could have simplified the shift were it not
10432 for the outer operation. So try to do the simplification
10435 if (outer_op
!= UNKNOWN
)
10436 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10441 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10443 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10444 turn off all the bits that the shift would have turned off. */
10445 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10446 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10447 GET_MODE_MASK (result_mode
) >> orig_count
);
10449 /* Do the remainder of the processing in RESULT_MODE. */
10450 x
= gen_lowpart_or_truncate (result_mode
, x
);
10452 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10455 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10457 if (outer_op
!= UNKNOWN
)
10459 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10460 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10461 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10463 if (outer_op
== AND
)
10464 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10465 else if (outer_op
== SET
)
10467 /* This means that we have determined that the result is
10468 equivalent to a constant. This should be rare. */
10469 if (!side_effects_p (x
))
10470 x
= GEN_INT (outer_const
);
10472 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10473 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10475 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10476 GEN_INT (outer_const
));
10482 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10483 The result of the shift is RESULT_MODE. If we cannot simplify it,
10484 return X or, if it is NULL, synthesize the expression with
10485 simplify_gen_binary. Otherwise, return a simplified value.
10487 The shift is normally computed in the widest mode we find in VAROP, as
10488 long as it isn't a different number of words than RESULT_MODE. Exceptions
10489 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10492 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10493 rtx varop
, int count
)
10495 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10500 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10501 if (GET_MODE (x
) != result_mode
)
10502 x
= gen_lowpart (result_mode
, x
);
10507 /* Like recog, but we receive the address of a pointer to a new pattern.
10508 We try to match the rtx that the pointer points to.
10509 If that fails, we may try to modify or replace the pattern,
10510 storing the replacement into the same pointer object.
10512 Modifications include deletion or addition of CLOBBERs.
10514 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10515 the CLOBBERs are placed.
10517 The value is the final insn code from the pattern ultimately matched,
10521 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10523 rtx pat
= *pnewpat
;
10524 rtx pat_without_clobbers
;
10525 int insn_code_number
;
10526 int num_clobbers_to_add
= 0;
10528 rtx notes
= NULL_RTX
;
10529 rtx old_notes
, old_pat
;
10532 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10533 we use to indicate that something didn't match. If we find such a
10534 thing, force rejection. */
10535 if (GET_CODE (pat
) == PARALLEL
)
10536 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10537 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10538 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10541 old_pat
= PATTERN (insn
);
10542 old_notes
= REG_NOTES (insn
);
10543 PATTERN (insn
) = pat
;
10544 REG_NOTES (insn
) = NULL_RTX
;
10546 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10547 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10549 if (insn_code_number
< 0)
10550 fputs ("Failed to match this instruction:\n", dump_file
);
10552 fputs ("Successfully matched this instruction:\n", dump_file
);
10553 print_rtl_single (dump_file
, pat
);
10556 /* If it isn't, there is the possibility that we previously had an insn
10557 that clobbered some register as a side effect, but the combined
10558 insn doesn't need to do that. So try once more without the clobbers
10559 unless this represents an ASM insn. */
10561 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10562 && GET_CODE (pat
) == PARALLEL
)
10566 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10567 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10570 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10574 SUBST_INT (XVECLEN (pat
, 0), pos
);
10577 pat
= XVECEXP (pat
, 0, 0);
10579 PATTERN (insn
) = pat
;
10580 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10581 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10583 if (insn_code_number
< 0)
10584 fputs ("Failed to match this instruction:\n", dump_file
);
10586 fputs ("Successfully matched this instruction:\n", dump_file
);
10587 print_rtl_single (dump_file
, pat
);
10591 pat_without_clobbers
= pat
;
10593 PATTERN (insn
) = old_pat
;
10594 REG_NOTES (insn
) = old_notes
;
10596 /* Recognize all noop sets, these will be killed by followup pass. */
10597 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10598 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10600 /* If we had any clobbers to add, make a new pattern than contains
10601 them. Then check to make sure that all of them are dead. */
10602 if (num_clobbers_to_add
)
10604 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10605 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10606 ? (XVECLEN (pat
, 0)
10607 + num_clobbers_to_add
)
10608 : num_clobbers_to_add
+ 1));
10610 if (GET_CODE (pat
) == PARALLEL
)
10611 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10612 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10614 XVECEXP (newpat
, 0, 0) = pat
;
10616 add_clobbers (newpat
, insn_code_number
);
10618 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10619 i
< XVECLEN (newpat
, 0); i
++)
10621 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10622 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10624 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10626 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10627 notes
= alloc_reg_note (REG_UNUSED
,
10628 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10634 if (insn_code_number
>= 0
10635 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10637 old_pat
= PATTERN (insn
);
10638 old_notes
= REG_NOTES (insn
);
10639 old_icode
= INSN_CODE (insn
);
10640 PATTERN (insn
) = pat
;
10641 REG_NOTES (insn
) = notes
;
10643 /* Allow targets to reject combined insn. */
10644 if (!targetm
.legitimate_combined_insn (insn
))
10646 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10647 fputs ("Instruction not appropriate for target.",
10650 /* Callers expect recog_for_combine to strip
10651 clobbers from the pattern on failure. */
10652 pat
= pat_without_clobbers
;
10655 insn_code_number
= -1;
10658 PATTERN (insn
) = old_pat
;
10659 REG_NOTES (insn
) = old_notes
;
10660 INSN_CODE (insn
) = old_icode
;
10666 return insn_code_number
;
10669 /* Like gen_lowpart_general but for use by combine. In combine it
10670 is not possible to create any new pseudoregs. However, it is
10671 safe to create invalid memory addresses, because combine will
10672 try to recognize them and all they will do is make the combine
10675 If for some reason this cannot do its job, an rtx
10676 (clobber (const_int 0)) is returned.
10677 An insn containing that will not be recognized. */
10680 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10682 enum machine_mode imode
= GET_MODE (x
);
10683 unsigned int osize
= GET_MODE_SIZE (omode
);
10684 unsigned int isize
= GET_MODE_SIZE (imode
);
10687 if (omode
== imode
)
10690 /* We can only support MODE being wider than a word if X is a
10691 constant integer or has a mode the same size. */
10692 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10693 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10696 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10697 won't know what to do. So we will strip off the SUBREG here and
10698 process normally. */
10699 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10701 x
= SUBREG_REG (x
);
10703 /* For use in case we fall down into the address adjustments
10704 further below, we need to adjust the known mode and size of
10705 x; imode and isize, since we just adjusted x. */
10706 imode
= GET_MODE (x
);
10708 if (imode
== omode
)
10711 isize
= GET_MODE_SIZE (imode
);
10714 result
= gen_lowpart_common (omode
, x
);
10723 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10725 if (MEM_VOLATILE_P (x
)
10726 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10729 /* If we want to refer to something bigger than the original memref,
10730 generate a paradoxical subreg instead. That will force a reload
10731 of the original memref X. */
10733 return gen_rtx_SUBREG (omode
, x
, 0);
10735 if (WORDS_BIG_ENDIAN
)
10736 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10738 /* Adjust the address so that the address-after-the-data is
10740 if (BYTES_BIG_ENDIAN
)
10741 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10743 return adjust_address_nv (x
, omode
, offset
);
10746 /* If X is a comparison operator, rewrite it in a new mode. This
10747 probably won't match, but may allow further simplifications. */
10748 else if (COMPARISON_P (x
))
10749 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10751 /* If we couldn't simplify X any other way, just enclose it in a
10752 SUBREG. Normally, this SUBREG won't match, but some patterns may
10753 include an explicit SUBREG or we may simplify it further in combine. */
10759 offset
= subreg_lowpart_offset (omode
, imode
);
10760 if (imode
== VOIDmode
)
10762 imode
= int_mode_for_mode (omode
);
10763 x
= gen_lowpart_common (imode
, x
);
10767 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10773 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10776 /* Try to simplify a comparison between OP0 and a constant OP1,
10777 where CODE is the comparison code that will be tested, into a
10778 (CODE OP0 const0_rtx) form.
10780 The result is a possibly different comparison code to use.
10781 *POP1 may be updated. */
10783 static enum rtx_code
10784 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10786 enum machine_mode mode
= GET_MODE (op0
);
10787 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10788 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10790 /* Get the constant we are comparing against and turn off all bits
10791 not on in our mode. */
10792 if (mode
!= VOIDmode
)
10793 const_op
= trunc_int_for_mode (const_op
, mode
);
10795 /* If we are comparing against a constant power of two and the value
10796 being compared can only have that single bit nonzero (e.g., it was
10797 `and'ed with that bit), we can replace this with a comparison
10800 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10801 || code
== LT
|| code
== LTU
)
10802 && mode_width
<= HOST_BITS_PER_WIDE_INT
10803 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10804 && (nonzero_bits (op0
, mode
)
10805 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10807 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10811 /* Similarly, if we are comparing a value known to be either -1 or
10812 0 with -1, change it to the opposite comparison against zero. */
10814 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10815 || code
== GEU
|| code
== LTU
)
10816 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10818 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10822 /* Do some canonicalizations based on the comparison code. We prefer
10823 comparisons against zero and then prefer equality comparisons.
10824 If we can reduce the size of a constant, we will do that too. */
10828 /* < C is equivalent to <= (C - 1) */
10833 /* ... fall through to LE case below. */
10839 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10846 /* If we are doing a <= 0 comparison on a value known to have
10847 a zero sign bit, we can replace this with == 0. */
10848 else if (const_op
== 0
10849 && mode_width
<= HOST_BITS_PER_WIDE_INT
10850 && (nonzero_bits (op0
, mode
)
10851 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10857 /* >= C is equivalent to > (C - 1). */
10862 /* ... fall through to GT below. */
10868 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10875 /* If we are doing a > 0 comparison on a value known to have
10876 a zero sign bit, we can replace this with != 0. */
10877 else if (const_op
== 0
10878 && mode_width
<= HOST_BITS_PER_WIDE_INT
10879 && (nonzero_bits (op0
, mode
)
10880 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10886 /* < C is equivalent to <= (C - 1). */
10891 /* ... fall through ... */
10893 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10894 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10895 && (unsigned HOST_WIDE_INT
) const_op
10896 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10906 /* unsigned <= 0 is equivalent to == 0 */
10909 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10910 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10911 && (unsigned HOST_WIDE_INT
) const_op
10912 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10920 /* >= C is equivalent to > (C - 1). */
10925 /* ... fall through ... */
10928 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10929 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10930 && (unsigned HOST_WIDE_INT
) const_op
10931 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10941 /* unsigned > 0 is equivalent to != 0 */
10944 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10945 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10946 && (unsigned HOST_WIDE_INT
) const_op
10947 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10958 *pop1
= GEN_INT (const_op
);
10962 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10963 comparison code that will be tested.
10965 The result is a possibly different comparison code to use. *POP0 and
10966 *POP1 may be updated.
10968 It is possible that we might detect that a comparison is either always
10969 true or always false. However, we do not perform general constant
10970 folding in combine, so this knowledge isn't useful. Such tautologies
10971 should have been detected earlier. Hence we ignore all such cases. */
10973 static enum rtx_code
10974 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10980 enum machine_mode mode
, tmode
;
10982 /* Try a few ways of applying the same transformation to both operands. */
10985 #ifndef WORD_REGISTER_OPERATIONS
10986 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10987 so check specially. */
10988 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10989 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10990 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10991 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10992 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10993 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10994 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10995 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10996 && CONST_INT_P (XEXP (op0
, 1))
10997 && XEXP (op0
, 1) == XEXP (op1
, 1)
10998 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10999 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11000 && (INTVAL (XEXP (op0
, 1))
11001 == (GET_MODE_PRECISION (GET_MODE (op0
))
11002 - (GET_MODE_PRECISION
11003 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11005 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11006 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11010 /* If both operands are the same constant shift, see if we can ignore the
11011 shift. We can if the shift is a rotate or if the bits shifted out of
11012 this shift are known to be zero for both inputs and if the type of
11013 comparison is compatible with the shift. */
11014 if (GET_CODE (op0
) == GET_CODE (op1
)
11015 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0
))
11016 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11017 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11018 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11019 || (GET_CODE (op0
) == ASHIFTRT
11020 && (code
!= GTU
&& code
!= LTU
11021 && code
!= GEU
&& code
!= LEU
)))
11022 && CONST_INT_P (XEXP (op0
, 1))
11023 && INTVAL (XEXP (op0
, 1)) >= 0
11024 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11025 && XEXP (op0
, 1) == XEXP (op1
, 1))
11027 enum machine_mode mode
= GET_MODE (op0
);
11028 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11029 int shift_count
= INTVAL (XEXP (op0
, 1));
11031 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11032 mask
&= (mask
>> shift_count
) << shift_count
;
11033 else if (GET_CODE (op0
) == ASHIFT
)
11034 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11036 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11037 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11038 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11043 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11044 SUBREGs are of the same mode, and, in both cases, the AND would
11045 be redundant if the comparison was done in the narrower mode,
11046 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11047 and the operand's possibly nonzero bits are 0xffffff01; in that case
11048 if we only care about QImode, we don't need the AND). This case
11049 occurs if the output mode of an scc insn is not SImode and
11050 STORE_FLAG_VALUE == 1 (e.g., the 386).
11052 Similarly, check for a case where the AND's are ZERO_EXTEND
11053 operations from some narrower mode even though a SUBREG is not
11056 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11057 && CONST_INT_P (XEXP (op0
, 1))
11058 && CONST_INT_P (XEXP (op1
, 1)))
11060 rtx inner_op0
= XEXP (op0
, 0);
11061 rtx inner_op1
= XEXP (op1
, 0);
11062 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11063 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11066 if (paradoxical_subreg_p (inner_op0
)
11067 && GET_CODE (inner_op1
) == SUBREG
11068 && (GET_MODE (SUBREG_REG (inner_op0
))
11069 == GET_MODE (SUBREG_REG (inner_op1
)))
11070 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11071 <= HOST_BITS_PER_WIDE_INT
)
11072 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11073 GET_MODE (SUBREG_REG (inner_op0
)))))
11074 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11075 GET_MODE (SUBREG_REG (inner_op1
))))))
11077 op0
= SUBREG_REG (inner_op0
);
11078 op1
= SUBREG_REG (inner_op1
);
11080 /* The resulting comparison is always unsigned since we masked
11081 off the original sign bit. */
11082 code
= unsigned_condition (code
);
11088 for (tmode
= GET_CLASS_NARROWEST_MODE
11089 (GET_MODE_CLASS (GET_MODE (op0
)));
11090 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11091 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11093 op0
= gen_lowpart (tmode
, inner_op0
);
11094 op1
= gen_lowpart (tmode
, inner_op1
);
11095 code
= unsigned_condition (code
);
11104 /* If both operands are NOT, we can strip off the outer operation
11105 and adjust the comparison code for swapped operands; similarly for
11106 NEG, except that this must be an equality comparison. */
11107 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11108 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11109 && (code
== EQ
|| code
== NE
)))
11110 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11116 /* If the first operand is a constant, swap the operands and adjust the
11117 comparison code appropriately, but don't do this if the second operand
11118 is already a constant integer. */
11119 if (swap_commutative_operands_p (op0
, op1
))
11121 tem
= op0
, op0
= op1
, op1
= tem
;
11122 code
= swap_condition (code
);
11125 /* We now enter a loop during which we will try to simplify the comparison.
11126 For the most part, we only are concerned with comparisons with zero,
11127 but some things may really be comparisons with zero but not start
11128 out looking that way. */
11130 while (CONST_INT_P (op1
))
11132 enum machine_mode mode
= GET_MODE (op0
);
11133 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11134 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11135 int equality_comparison_p
;
11136 int sign_bit_comparison_p
;
11137 int unsigned_comparison_p
;
11138 HOST_WIDE_INT const_op
;
11140 /* We only want to handle integral modes. This catches VOIDmode,
11141 CCmode, and the floating-point modes. An exception is that we
11142 can handle VOIDmode if OP0 is a COMPARE or a comparison
11145 if (GET_MODE_CLASS (mode
) != MODE_INT
11146 && ! (mode
== VOIDmode
11147 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11150 /* Try to simplify the compare to constant, possibly changing the
11151 comparison op, and/or changing op1 to zero. */
11152 code
= simplify_compare_const (code
, op0
, &op1
);
11153 const_op
= INTVAL (op1
);
11155 /* Compute some predicates to simplify code below. */
11157 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11158 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11159 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11162 /* If this is a sign bit comparison and we can do arithmetic in
11163 MODE, say that we will only be needing the sign bit of OP0. */
11164 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11165 op0
= force_to_mode (op0
, mode
,
11166 (unsigned HOST_WIDE_INT
) 1
11167 << (GET_MODE_PRECISION (mode
) - 1),
11170 /* Now try cases based on the opcode of OP0. If none of the cases
11171 does a "continue", we exit this loop immediately after the
11174 switch (GET_CODE (op0
))
11177 /* If we are extracting a single bit from a variable position in
11178 a constant that has only a single bit set and are comparing it
11179 with zero, we can convert this into an equality comparison
11180 between the position and the location of the single bit. */
11181 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11182 have already reduced the shift count modulo the word size. */
11183 if (!SHIFT_COUNT_TRUNCATED
11184 && CONST_INT_P (XEXP (op0
, 0))
11185 && XEXP (op0
, 1) == const1_rtx
11186 && equality_comparison_p
&& const_op
== 0
11187 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11189 if (BITS_BIG_ENDIAN
)
11190 i
= BITS_PER_WORD
- 1 - i
;
11192 op0
= XEXP (op0
, 2);
11196 /* Result is nonzero iff shift count is equal to I. */
11197 code
= reverse_condition (code
);
11201 /* ... fall through ... */
11204 tem
= expand_compound_operation (op0
);
11213 /* If testing for equality, we can take the NOT of the constant. */
11214 if (equality_comparison_p
11215 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11217 op0
= XEXP (op0
, 0);
11222 /* If just looking at the sign bit, reverse the sense of the
11224 if (sign_bit_comparison_p
)
11226 op0
= XEXP (op0
, 0);
11227 code
= (code
== GE
? LT
: GE
);
11233 /* If testing for equality, we can take the NEG of the constant. */
11234 if (equality_comparison_p
11235 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11237 op0
= XEXP (op0
, 0);
11242 /* The remaining cases only apply to comparisons with zero. */
11246 /* When X is ABS or is known positive,
11247 (neg X) is < 0 if and only if X != 0. */
11249 if (sign_bit_comparison_p
11250 && (GET_CODE (XEXP (op0
, 0)) == ABS
11251 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11252 && (nonzero_bits (XEXP (op0
, 0), mode
)
11253 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11256 op0
= XEXP (op0
, 0);
11257 code
= (code
== LT
? NE
: EQ
);
11261 /* If we have NEG of something whose two high-order bits are the
11262 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11263 if (num_sign_bit_copies (op0
, mode
) >= 2)
11265 op0
= XEXP (op0
, 0);
11266 code
= swap_condition (code
);
11272 /* If we are testing equality and our count is a constant, we
11273 can perform the inverse operation on our RHS. */
11274 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11275 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11276 op1
, XEXP (op0
, 1))) != 0)
11278 op0
= XEXP (op0
, 0);
11283 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11284 a particular bit. Convert it to an AND of a constant of that
11285 bit. This will be converted into a ZERO_EXTRACT. */
11286 if (const_op
== 0 && sign_bit_comparison_p
11287 && CONST_INT_P (XEXP (op0
, 1))
11288 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11290 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11291 ((unsigned HOST_WIDE_INT
) 1
11293 - INTVAL (XEXP (op0
, 1)))));
11294 code
= (code
== LT
? NE
: EQ
);
11298 /* Fall through. */
11301 /* ABS is ignorable inside an equality comparison with zero. */
11302 if (const_op
== 0 && equality_comparison_p
)
11304 op0
= XEXP (op0
, 0);
11310 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11311 (compare FOO CONST) if CONST fits in FOO's mode and we
11312 are either testing inequality or have an unsigned
11313 comparison with ZERO_EXTEND or a signed comparison with
11314 SIGN_EXTEND. But don't do it if we don't have a compare
11315 insn of the given mode, since we'd have to revert it
11316 later on, and then we wouldn't know whether to sign- or
11318 mode
= GET_MODE (XEXP (op0
, 0));
11319 if (GET_MODE_CLASS (mode
) == MODE_INT
11320 && ! unsigned_comparison_p
11321 && HWI_COMPUTABLE_MODE_P (mode
)
11322 && trunc_int_for_mode (const_op
, mode
) == const_op
11323 && have_insn_for (COMPARE
, mode
))
11325 op0
= XEXP (op0
, 0);
11331 /* Check for the case where we are comparing A - C1 with C2, that is
11333 (subreg:MODE (plus (A) (-C1))) op (C2)
11335 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11336 comparison in the wider mode. One of the following two conditions
11337 must be true in order for this to be valid:
11339 1. The mode extension results in the same bit pattern being added
11340 on both sides and the comparison is equality or unsigned. As
11341 C2 has been truncated to fit in MODE, the pattern can only be
11344 2. The mode extension results in the sign bit being copied on
11347 The difficulty here is that we have predicates for A but not for
11348 (A - C1) so we need to check that C1 is within proper bounds so
11349 as to perturbate A as little as possible. */
11351 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11352 && subreg_lowpart_p (op0
)
11353 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11354 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11355 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11357 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11358 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11359 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11362 && (unsigned HOST_WIDE_INT
) c1
11363 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11364 && (equality_comparison_p
|| unsigned_comparison_p
)
11365 /* (A - C1) zero-extends if it is positive and sign-extends
11366 if it is negative, C2 both zero- and sign-extends. */
11367 && ((0 == (nonzero_bits (a
, inner_mode
)
11368 & ~GET_MODE_MASK (mode
))
11370 /* (A - C1) sign-extends if it is positive and 1-extends
11371 if it is negative, C2 both sign- and 1-extends. */
11372 || (num_sign_bit_copies (a
, inner_mode
)
11373 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11376 || ((unsigned HOST_WIDE_INT
) c1
11377 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11378 /* (A - C1) always sign-extends, like C2. */
11379 && num_sign_bit_copies (a
, inner_mode
)
11380 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11381 - (mode_width
- 1))))
11383 op0
= SUBREG_REG (op0
);
11388 /* If the inner mode is narrower and we are extracting the low part,
11389 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11390 if (subreg_lowpart_p (op0
)
11391 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11392 /* Fall through */ ;
11396 /* ... fall through ... */
11399 mode
= GET_MODE (XEXP (op0
, 0));
11400 if (GET_MODE_CLASS (mode
) == MODE_INT
11401 && (unsigned_comparison_p
|| equality_comparison_p
)
11402 && HWI_COMPUTABLE_MODE_P (mode
)
11403 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11405 && have_insn_for (COMPARE
, mode
))
11407 op0
= XEXP (op0
, 0);
11413 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11414 this for equality comparisons due to pathological cases involving
11416 if (equality_comparison_p
11417 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11418 op1
, XEXP (op0
, 1))))
11420 op0
= XEXP (op0
, 0);
11425 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11426 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11427 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11429 op0
= XEXP (XEXP (op0
, 0), 0);
11430 code
= (code
== LT
? EQ
: NE
);
11436 /* We used to optimize signed comparisons against zero, but that
11437 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11438 arrive here as equality comparisons, or (GEU, LTU) are
11439 optimized away. No need to special-case them. */
11441 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11442 (eq B (minus A C)), whichever simplifies. We can only do
11443 this for equality comparisons due to pathological cases involving
11445 if (equality_comparison_p
11446 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11447 XEXP (op0
, 1), op1
)))
11449 op0
= XEXP (op0
, 0);
11454 if (equality_comparison_p
11455 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11456 XEXP (op0
, 0), op1
)))
11458 op0
= XEXP (op0
, 1);
11463 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11464 of bits in X minus 1, is one iff X > 0. */
11465 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11466 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11467 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11468 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11470 op0
= XEXP (op0
, 1);
11471 code
= (code
== GE
? LE
: GT
);
11477 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11478 if C is zero or B is a constant. */
11479 if (equality_comparison_p
11480 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11481 XEXP (op0
, 1), op1
)))
11483 op0
= XEXP (op0
, 0);
11490 case UNEQ
: case LTGT
:
11491 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11492 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11493 case UNORDERED
: case ORDERED
:
11494 /* We can't do anything if OP0 is a condition code value, rather
11495 than an actual data value. */
11497 || CC0_P (XEXP (op0
, 0))
11498 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11501 /* Get the two operands being compared. */
11502 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11503 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11505 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11507 /* Check for the cases where we simply want the result of the
11508 earlier test or the opposite of that result. */
11509 if (code
== NE
|| code
== EQ
11510 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11511 && (code
== LT
|| code
== GE
)))
11513 enum rtx_code new_code
;
11514 if (code
== LT
|| code
== NE
)
11515 new_code
= GET_CODE (op0
);
11517 new_code
= reversed_comparison_code (op0
, NULL
);
11519 if (new_code
!= UNKNOWN
)
11530 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11532 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11533 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11534 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11536 op0
= XEXP (op0
, 1);
11537 code
= (code
== GE
? GT
: LE
);
11543 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11544 will be converted to a ZERO_EXTRACT later. */
11545 if (const_op
== 0 && equality_comparison_p
11546 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11547 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11549 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11550 XEXP (XEXP (op0
, 0), 1));
11551 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11555 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11556 zero and X is a comparison and C1 and C2 describe only bits set
11557 in STORE_FLAG_VALUE, we can compare with X. */
11558 if (const_op
== 0 && equality_comparison_p
11559 && mode_width
<= HOST_BITS_PER_WIDE_INT
11560 && CONST_INT_P (XEXP (op0
, 1))
11561 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11562 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11563 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11564 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11566 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11567 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11568 if ((~STORE_FLAG_VALUE
& mask
) == 0
11569 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11570 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11571 && COMPARISON_P (tem
))))
11573 op0
= XEXP (XEXP (op0
, 0), 0);
11578 /* If we are doing an equality comparison of an AND of a bit equal
11579 to the sign bit, replace this with a LT or GE comparison of
11580 the underlying value. */
11581 if (equality_comparison_p
11583 && CONST_INT_P (XEXP (op0
, 1))
11584 && mode_width
<= HOST_BITS_PER_WIDE_INT
11585 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11586 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11588 op0
= XEXP (op0
, 0);
11589 code
= (code
== EQ
? GE
: LT
);
11593 /* If this AND operation is really a ZERO_EXTEND from a narrower
11594 mode, the constant fits within that mode, and this is either an
11595 equality or unsigned comparison, try to do this comparison in
11600 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11601 -> (ne:DI (reg:SI 4) (const_int 0))
11603 unless TRULY_NOOP_TRUNCATION allows it or the register is
11604 known to hold a value of the required mode the
11605 transformation is invalid. */
11606 if ((equality_comparison_p
|| unsigned_comparison_p
)
11607 && CONST_INT_P (XEXP (op0
, 1))
11608 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11609 & GET_MODE_MASK (mode
))
11611 && const_op
>> i
== 0
11612 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11613 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11614 || (REG_P (XEXP (op0
, 0))
11615 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11617 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11621 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11622 fits in both M1 and M2 and the SUBREG is either paradoxical
11623 or represents the low part, permute the SUBREG and the AND
11625 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11627 unsigned HOST_WIDE_INT c1
;
11628 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11629 /* Require an integral mode, to avoid creating something like
11631 if (SCALAR_INT_MODE_P (tmode
)
11632 /* It is unsafe to commute the AND into the SUBREG if the
11633 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11634 not defined. As originally written the upper bits
11635 have a defined value due to the AND operation.
11636 However, if we commute the AND inside the SUBREG then
11637 they no longer have defined values and the meaning of
11638 the code has been changed. */
11640 #ifdef WORD_REGISTER_OPERATIONS
11641 || (mode_width
> GET_MODE_PRECISION (tmode
)
11642 && mode_width
<= BITS_PER_WORD
)
11644 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11645 && subreg_lowpart_p (XEXP (op0
, 0))))
11646 && CONST_INT_P (XEXP (op0
, 1))
11647 && mode_width
<= HOST_BITS_PER_WIDE_INT
11648 && HWI_COMPUTABLE_MODE_P (tmode
)
11649 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11650 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11652 && c1
!= GET_MODE_MASK (tmode
))
11654 op0
= simplify_gen_binary (AND
, tmode
,
11655 SUBREG_REG (XEXP (op0
, 0)),
11656 gen_int_mode (c1
, tmode
));
11657 op0
= gen_lowpart (mode
, op0
);
11662 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11663 if (const_op
== 0 && equality_comparison_p
11664 && XEXP (op0
, 1) == const1_rtx
11665 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11667 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11668 XEXP (XEXP (op0
, 0), 0), 1);
11669 code
= (code
== NE
? EQ
: NE
);
11673 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11674 (eq (and (lshiftrt X) 1) 0).
11675 Also handle the case where (not X) is expressed using xor. */
11676 if (const_op
== 0 && equality_comparison_p
11677 && XEXP (op0
, 1) == const1_rtx
11678 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11680 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11681 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11683 if (GET_CODE (shift_op
) == NOT
11684 || (GET_CODE (shift_op
) == XOR
11685 && CONST_INT_P (XEXP (shift_op
, 1))
11686 && CONST_INT_P (shift_count
)
11687 && HWI_COMPUTABLE_MODE_P (mode
)
11688 && (UINTVAL (XEXP (shift_op
, 1))
11689 == (unsigned HOST_WIDE_INT
) 1
11690 << INTVAL (shift_count
))))
11693 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11694 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11695 code
= (code
== NE
? EQ
: NE
);
11702 /* If we have (compare (ashift FOO N) (const_int C)) and
11703 the high order N bits of FOO (N+1 if an inequality comparison)
11704 are known to be zero, we can do this by comparing FOO with C
11705 shifted right N bits so long as the low-order N bits of C are
11707 if (CONST_INT_P (XEXP (op0
, 1))
11708 && INTVAL (XEXP (op0
, 1)) >= 0
11709 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11710 < HOST_BITS_PER_WIDE_INT
)
11711 && (((unsigned HOST_WIDE_INT
) const_op
11712 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11714 && mode_width
<= HOST_BITS_PER_WIDE_INT
11715 && (nonzero_bits (XEXP (op0
, 0), mode
)
11716 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11717 + ! equality_comparison_p
))) == 0)
11719 /* We must perform a logical shift, not an arithmetic one,
11720 as we want the top N bits of C to be zero. */
11721 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11723 temp
>>= INTVAL (XEXP (op0
, 1));
11724 op1
= gen_int_mode (temp
, mode
);
11725 op0
= XEXP (op0
, 0);
11729 /* If we are doing a sign bit comparison, it means we are testing
11730 a particular bit. Convert it to the appropriate AND. */
11731 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11732 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11734 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11735 ((unsigned HOST_WIDE_INT
) 1
11737 - INTVAL (XEXP (op0
, 1)))));
11738 code
= (code
== LT
? NE
: EQ
);
11742 /* If this an equality comparison with zero and we are shifting
11743 the low bit to the sign bit, we can convert this to an AND of the
11745 if (const_op
== 0 && equality_comparison_p
11746 && CONST_INT_P (XEXP (op0
, 1))
11747 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11749 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11755 /* If this is an equality comparison with zero, we can do this
11756 as a logical shift, which might be much simpler. */
11757 if (equality_comparison_p
&& const_op
== 0
11758 && CONST_INT_P (XEXP (op0
, 1)))
11760 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11762 INTVAL (XEXP (op0
, 1)));
11766 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11767 do the comparison in a narrower mode. */
11768 if (! unsigned_comparison_p
11769 && CONST_INT_P (XEXP (op0
, 1))
11770 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11771 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11772 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11773 MODE_INT
, 1)) != BLKmode
11774 && (((unsigned HOST_WIDE_INT
) const_op
11775 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11776 <= GET_MODE_MASK (tmode
)))
11778 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11782 /* Likewise if OP0 is a PLUS of a sign extension with a
11783 constant, which is usually represented with the PLUS
11784 between the shifts. */
11785 if (! unsigned_comparison_p
11786 && CONST_INT_P (XEXP (op0
, 1))
11787 && GET_CODE (XEXP (op0
, 0)) == PLUS
11788 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11789 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11790 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11791 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11792 MODE_INT
, 1)) != BLKmode
11793 && (((unsigned HOST_WIDE_INT
) const_op
11794 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11795 <= GET_MODE_MASK (tmode
)))
11797 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11798 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11799 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11800 add_const
, XEXP (op0
, 1));
11802 op0
= simplify_gen_binary (PLUS
, tmode
,
11803 gen_lowpart (tmode
, inner
),
11808 /* ... fall through ... */
11810 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11811 the low order N bits of FOO are known to be zero, we can do this
11812 by comparing FOO with C shifted left N bits so long as no
11813 overflow occurs. Even if the low order N bits of FOO aren't known
11814 to be zero, if the comparison is >= or < we can use the same
11815 optimization and for > or <= by setting all the low
11816 order N bits in the comparison constant. */
11817 if (CONST_INT_P (XEXP (op0
, 1))
11818 && INTVAL (XEXP (op0
, 1)) > 0
11819 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11820 && mode_width
<= HOST_BITS_PER_WIDE_INT
11821 && (((unsigned HOST_WIDE_INT
) const_op
11822 + (GET_CODE (op0
) != LSHIFTRT
11823 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11826 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11828 unsigned HOST_WIDE_INT low_bits
11829 = (nonzero_bits (XEXP (op0
, 0), mode
)
11830 & (((unsigned HOST_WIDE_INT
) 1
11831 << INTVAL (XEXP (op0
, 1))) - 1));
11832 if (low_bits
== 0 || !equality_comparison_p
)
11834 /* If the shift was logical, then we must make the condition
11836 if (GET_CODE (op0
) == LSHIFTRT
)
11837 code
= unsigned_condition (code
);
11839 const_op
<<= INTVAL (XEXP (op0
, 1));
11841 && (code
== GT
|| code
== GTU
11842 || code
== LE
|| code
== LEU
))
11844 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11845 op1
= GEN_INT (const_op
);
11846 op0
= XEXP (op0
, 0);
11851 /* If we are using this shift to extract just the sign bit, we
11852 can replace this with an LT or GE comparison. */
11854 && (equality_comparison_p
|| sign_bit_comparison_p
)
11855 && CONST_INT_P (XEXP (op0
, 1))
11856 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11858 op0
= XEXP (op0
, 0);
11859 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11871 /* Now make any compound operations involved in this comparison. Then,
11872 check for an outmost SUBREG on OP0 that is not doing anything or is
11873 paradoxical. The latter transformation must only be performed when
11874 it is known that the "extra" bits will be the same in op0 and op1 or
11875 that they don't matter. There are three cases to consider:
11877 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11878 care bits and we can assume they have any convenient value. So
11879 making the transformation is safe.
11881 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11882 In this case the upper bits of op0 are undefined. We should not make
11883 the simplification in that case as we do not know the contents of
11886 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11887 UNKNOWN. In that case we know those bits are zeros or ones. We must
11888 also be sure that they are the same as the upper bits of op1.
11890 We can never remove a SUBREG for a non-equality comparison because
11891 the sign bit is in a different place in the underlying object. */
11893 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11894 op1
= make_compound_operation (op1
, SET
);
11896 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11897 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11898 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11899 && (code
== NE
|| code
== EQ
))
11901 if (paradoxical_subreg_p (op0
))
11903 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11905 if (REG_P (SUBREG_REG (op0
)))
11907 op0
= SUBREG_REG (op0
);
11908 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11911 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11912 <= HOST_BITS_PER_WIDE_INT
)
11913 && (nonzero_bits (SUBREG_REG (op0
),
11914 GET_MODE (SUBREG_REG (op0
)))
11915 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11917 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11919 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11920 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11921 op0
= SUBREG_REG (op0
), op1
= tem
;
11925 /* We now do the opposite procedure: Some machines don't have compare
11926 insns in all modes. If OP0's mode is an integer mode smaller than a
11927 word and we can't do a compare in that mode, see if there is a larger
11928 mode for which we can do the compare. There are a number of cases in
11929 which we can use the wider mode. */
11931 mode
= GET_MODE (op0
);
11932 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11933 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11934 && ! have_insn_for (COMPARE
, mode
))
11935 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11936 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
11937 tmode
= GET_MODE_WIDER_MODE (tmode
))
11938 if (have_insn_for (COMPARE
, tmode
))
11942 /* If this is a test for negative, we can make an explicit
11943 test of the sign bit. Test this first so we can use
11944 a paradoxical subreg to extend OP0. */
11946 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11947 && HWI_COMPUTABLE_MODE_P (mode
))
11949 op0
= simplify_gen_binary (AND
, tmode
,
11950 gen_lowpart (tmode
, op0
),
11951 GEN_INT ((unsigned HOST_WIDE_INT
) 1
11952 << (GET_MODE_BITSIZE (mode
)
11954 code
= (code
== LT
) ? NE
: EQ
;
11958 /* If the only nonzero bits in OP0 and OP1 are those in the
11959 narrower mode and this is an equality or unsigned comparison,
11960 we can use the wider mode. Similarly for sign-extended
11961 values, in which case it is true for all comparisons. */
11962 zero_extended
= ((code
== EQ
|| code
== NE
11963 || code
== GEU
|| code
== GTU
11964 || code
== LEU
|| code
== LTU
)
11965 && (nonzero_bits (op0
, tmode
)
11966 & ~GET_MODE_MASK (mode
)) == 0
11967 && ((CONST_INT_P (op1
)
11968 || (nonzero_bits (op1
, tmode
)
11969 & ~GET_MODE_MASK (mode
)) == 0)));
11972 || ((num_sign_bit_copies (op0
, tmode
)
11973 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11974 - GET_MODE_PRECISION (mode
)))
11975 && (num_sign_bit_copies (op1
, tmode
)
11976 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11977 - GET_MODE_PRECISION (mode
)))))
11979 /* If OP0 is an AND and we don't have an AND in MODE either,
11980 make a new AND in the proper mode. */
11981 if (GET_CODE (op0
) == AND
11982 && !have_insn_for (AND
, mode
))
11983 op0
= simplify_gen_binary (AND
, tmode
,
11984 gen_lowpart (tmode
,
11986 gen_lowpart (tmode
,
11992 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11993 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11997 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11998 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12005 /* We may have changed the comparison operands. Re-canonicalize. */
12006 if (swap_commutative_operands_p (op0
, op1
))
12008 tem
= op0
, op0
= op1
, op1
= tem
;
12009 code
= swap_condition (code
);
12012 /* If this machine only supports a subset of valid comparisons, see if we
12013 can convert an unsupported one into a supported one. */
12014 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12022 /* Utility function for record_value_for_reg. Count number of
12027 enum rtx_code code
= GET_CODE (x
);
12031 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12032 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12034 rtx x0
= XEXP (x
, 0);
12035 rtx x1
= XEXP (x
, 1);
12038 return 1 + 2 * count_rtxs (x0
);
12040 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12041 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12042 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12043 return 2 + 2 * count_rtxs (x0
)
12044 + count_rtxs (x
== XEXP (x1
, 0)
12045 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12047 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12048 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12049 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12050 return 2 + 2 * count_rtxs (x1
)
12051 + count_rtxs (x
== XEXP (x0
, 0)
12052 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12055 fmt
= GET_RTX_FORMAT (code
);
12056 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12058 ret
+= count_rtxs (XEXP (x
, i
));
12059 else if (fmt
[i
] == 'E')
12060 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12061 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12066 /* Utility function for following routine. Called when X is part of a value
12067 being stored into last_set_value. Sets last_set_table_tick
12068 for each register mentioned. Similar to mention_regs in cse.c */
12071 update_table_tick (rtx x
)
12073 enum rtx_code code
= GET_CODE (x
);
12074 const char *fmt
= GET_RTX_FORMAT (code
);
12079 unsigned int regno
= REGNO (x
);
12080 unsigned int endregno
= END_REGNO (x
);
12083 for (r
= regno
; r
< endregno
; r
++)
12085 reg_stat_type
*rsp
= ®_stat
[r
];
12086 rsp
->last_set_table_tick
= label_tick
;
12092 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12095 /* Check for identical subexpressions. If x contains
12096 identical subexpression we only have to traverse one of
12098 if (i
== 0 && ARITHMETIC_P (x
))
12100 /* Note that at this point x1 has already been
12102 rtx x0
= XEXP (x
, 0);
12103 rtx x1
= XEXP (x
, 1);
12105 /* If x0 and x1 are identical then there is no need to
12110 /* If x0 is identical to a subexpression of x1 then while
12111 processing x1, x0 has already been processed. Thus we
12112 are done with x. */
12113 if (ARITHMETIC_P (x1
)
12114 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12117 /* If x1 is identical to a subexpression of x0 then we
12118 still have to process the rest of x0. */
12119 if (ARITHMETIC_P (x0
)
12120 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12122 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12127 update_table_tick (XEXP (x
, i
));
12129 else if (fmt
[i
] == 'E')
12130 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12131 update_table_tick (XVECEXP (x
, i
, j
));
12134 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12135 are saying that the register is clobbered and we no longer know its
12136 value. If INSN is zero, don't update reg_stat[].last_set; this is
12137 only permitted with VALUE also zero and is used to invalidate the
12141 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12143 unsigned int regno
= REGNO (reg
);
12144 unsigned int endregno
= END_REGNO (reg
);
12146 reg_stat_type
*rsp
;
12148 /* If VALUE contains REG and we have a previous value for REG, substitute
12149 the previous value. */
12150 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12154 /* Set things up so get_last_value is allowed to see anything set up to
12156 subst_low_luid
= DF_INSN_LUID (insn
);
12157 tem
= get_last_value (reg
);
12159 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12160 it isn't going to be useful and will take a lot of time to process,
12161 so just use the CLOBBER. */
12165 if (ARITHMETIC_P (tem
)
12166 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12167 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12168 tem
= XEXP (tem
, 0);
12169 else if (count_occurrences (value
, reg
, 1) >= 2)
12171 /* If there are two or more occurrences of REG in VALUE,
12172 prevent the value from growing too much. */
12173 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12174 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12177 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12181 /* For each register modified, show we don't know its value, that
12182 we don't know about its bitwise content, that its value has been
12183 updated, and that we don't know the location of the death of the
12185 for (i
= regno
; i
< endregno
; i
++)
12187 rsp
= ®_stat
[i
];
12190 rsp
->last_set
= insn
;
12192 rsp
->last_set_value
= 0;
12193 rsp
->last_set_mode
= VOIDmode
;
12194 rsp
->last_set_nonzero_bits
= 0;
12195 rsp
->last_set_sign_bit_copies
= 0;
12196 rsp
->last_death
= 0;
12197 rsp
->truncated_to_mode
= VOIDmode
;
12200 /* Mark registers that are being referenced in this value. */
12202 update_table_tick (value
);
12204 /* Now update the status of each register being set.
12205 If someone is using this register in this block, set this register
12206 to invalid since we will get confused between the two lives in this
12207 basic block. This makes using this register always invalid. In cse, we
12208 scan the table to invalidate all entries using this register, but this
12209 is too much work for us. */
12211 for (i
= regno
; i
< endregno
; i
++)
12213 rsp
= ®_stat
[i
];
12214 rsp
->last_set_label
= label_tick
;
12216 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12217 rsp
->last_set_invalid
= 1;
12219 rsp
->last_set_invalid
= 0;
12222 /* The value being assigned might refer to X (like in "x++;"). In that
12223 case, we must replace it with (clobber (const_int 0)) to prevent
12225 rsp
= ®_stat
[regno
];
12226 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12228 value
= copy_rtx (value
);
12229 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12233 /* For the main register being modified, update the value, the mode, the
12234 nonzero bits, and the number of sign bit copies. */
12236 rsp
->last_set_value
= value
;
12240 enum machine_mode mode
= GET_MODE (reg
);
12241 subst_low_luid
= DF_INSN_LUID (insn
);
12242 rsp
->last_set_mode
= mode
;
12243 if (GET_MODE_CLASS (mode
) == MODE_INT
12244 && HWI_COMPUTABLE_MODE_P (mode
))
12245 mode
= nonzero_bits_mode
;
12246 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12247 rsp
->last_set_sign_bit_copies
12248 = num_sign_bit_copies (value
, GET_MODE (reg
));
12252 /* Called via note_stores from record_dead_and_set_regs to handle one
12253 SET or CLOBBER in an insn. DATA is the instruction in which the
12254 set is occurring. */
12257 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12259 rtx record_dead_insn
= (rtx
) data
;
12261 if (GET_CODE (dest
) == SUBREG
)
12262 dest
= SUBREG_REG (dest
);
12264 if (!record_dead_insn
)
12267 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12273 /* If we are setting the whole register, we know its value. Otherwise
12274 show that we don't know the value. We can handle SUBREG in
12276 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12277 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12278 else if (GET_CODE (setter
) == SET
12279 && GET_CODE (SET_DEST (setter
)) == SUBREG
12280 && SUBREG_REG (SET_DEST (setter
)) == dest
12281 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12282 && subreg_lowpart_p (SET_DEST (setter
)))
12283 record_value_for_reg (dest
, record_dead_insn
,
12284 gen_lowpart (GET_MODE (dest
),
12285 SET_SRC (setter
)));
12287 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12289 else if (MEM_P (dest
)
12290 /* Ignore pushes, they clobber nothing. */
12291 && ! push_operand (dest
, GET_MODE (dest
)))
12292 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12295 /* Update the records of when each REG was most recently set or killed
12296 for the things done by INSN. This is the last thing done in processing
12297 INSN in the combiner loop.
12299 We update reg_stat[], in particular fields last_set, last_set_value,
12300 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12301 last_death, and also the similar information mem_last_set (which insn
12302 most recently modified memory) and last_call_luid (which insn was the
12303 most recent subroutine call). */
12306 record_dead_and_set_regs (rtx insn
)
12311 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12313 if (REG_NOTE_KIND (link
) == REG_DEAD
12314 && REG_P (XEXP (link
, 0)))
12316 unsigned int regno
= REGNO (XEXP (link
, 0));
12317 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12319 for (i
= regno
; i
< endregno
; i
++)
12321 reg_stat_type
*rsp
;
12323 rsp
= ®_stat
[i
];
12324 rsp
->last_death
= insn
;
12327 else if (REG_NOTE_KIND (link
) == REG_INC
)
12328 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12333 hard_reg_set_iterator hrsi
;
12334 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12336 reg_stat_type
*rsp
;
12338 rsp
= ®_stat
[i
];
12339 rsp
->last_set_invalid
= 1;
12340 rsp
->last_set
= insn
;
12341 rsp
->last_set_value
= 0;
12342 rsp
->last_set_mode
= VOIDmode
;
12343 rsp
->last_set_nonzero_bits
= 0;
12344 rsp
->last_set_sign_bit_copies
= 0;
12345 rsp
->last_death
= 0;
12346 rsp
->truncated_to_mode
= VOIDmode
;
12349 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12351 /* We can't combine into a call pattern. Remember, though, that
12352 the return value register is set at this LUID. We could
12353 still replace a register with the return value from the
12354 wrong subroutine call! */
12355 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12358 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12361 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12362 register present in the SUBREG, so for each such SUBREG go back and
12363 adjust nonzero and sign bit information of the registers that are
12364 known to have some zero/sign bits set.
12366 This is needed because when combine blows the SUBREGs away, the
12367 information on zero/sign bits is lost and further combines can be
12368 missed because of that. */
12371 record_promoted_value (rtx insn
, rtx subreg
)
12373 struct insn_link
*links
;
12375 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12376 enum machine_mode mode
= GET_MODE (subreg
);
12378 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12381 for (links
= LOG_LINKS (insn
); links
;)
12383 reg_stat_type
*rsp
;
12385 insn
= links
->insn
;
12386 set
= single_set (insn
);
12388 if (! set
|| !REG_P (SET_DEST (set
))
12389 || REGNO (SET_DEST (set
)) != regno
12390 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12392 links
= links
->next
;
12396 rsp
= ®_stat
[regno
];
12397 if (rsp
->last_set
== insn
)
12399 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12400 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12403 if (REG_P (SET_SRC (set
)))
12405 regno
= REGNO (SET_SRC (set
));
12406 links
= LOG_LINKS (insn
);
12413 /* Check if X, a register, is known to contain a value already
12414 truncated to MODE. In this case we can use a subreg to refer to
12415 the truncated value even though in the generic case we would need
12416 an explicit truncation. */
12419 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12421 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12422 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12425 || rsp
->truncation_label
< label_tick_ebb_start
)
12427 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12429 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12434 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12435 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12436 might be able to turn a truncate into a subreg using this information.
12437 Return -1 if traversing *P is complete or 0 otherwise. */
12440 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12443 enum machine_mode truncated_mode
;
12444 reg_stat_type
*rsp
;
12446 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12448 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12449 truncated_mode
= GET_MODE (x
);
12451 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12454 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12457 x
= SUBREG_REG (x
);
12459 /* ??? For hard-regs we now record everything. We might be able to
12460 optimize this using last_set_mode. */
12461 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12462 truncated_mode
= GET_MODE (x
);
12466 rsp
= ®_stat
[REGNO (x
)];
12467 if (rsp
->truncated_to_mode
== 0
12468 || rsp
->truncation_label
< label_tick_ebb_start
12469 || (GET_MODE_SIZE (truncated_mode
)
12470 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12472 rsp
->truncated_to_mode
= truncated_mode
;
12473 rsp
->truncation_label
= label_tick
;
12479 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12480 the modes they are used in. This can help truning TRUNCATEs into
12484 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12486 for_each_rtx (x
, record_truncated_value
, NULL
);
12489 /* Scan X for promoted SUBREGs. For each one found,
12490 note what it implies to the registers used in it. */
12493 check_promoted_subreg (rtx insn
, rtx x
)
12495 if (GET_CODE (x
) == SUBREG
12496 && SUBREG_PROMOTED_VAR_P (x
)
12497 && REG_P (SUBREG_REG (x
)))
12498 record_promoted_value (insn
, x
);
12501 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12504 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12508 check_promoted_subreg (insn
, XEXP (x
, i
));
12512 if (XVEC (x
, i
) != 0)
12513 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12514 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12520 /* Verify that all the registers and memory references mentioned in *LOC are
12521 still valid. *LOC was part of a value set in INSN when label_tick was
12522 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12523 the invalid references with (clobber (const_int 0)) and return 1. This
12524 replacement is useful because we often can get useful information about
12525 the form of a value (e.g., if it was produced by a shift that always
12526 produces -1 or 0) even though we don't know exactly what registers it
12527 was produced from. */
12530 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12533 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12534 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12539 unsigned int regno
= REGNO (x
);
12540 unsigned int endregno
= END_REGNO (x
);
12543 for (j
= regno
; j
< endregno
; j
++)
12545 reg_stat_type
*rsp
= ®_stat
[j
];
12546 if (rsp
->last_set_invalid
12547 /* If this is a pseudo-register that was only set once and not
12548 live at the beginning of the function, it is always valid. */
12549 || (! (regno
>= FIRST_PSEUDO_REGISTER
12550 && REG_N_SETS (regno
) == 1
12551 && (!REGNO_REG_SET_P
12552 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12553 && rsp
->last_set_label
> tick
))
12556 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12563 /* If this is a memory reference, make sure that there were no stores after
12564 it that might have clobbered the value. We don't have alias info, so we
12565 assume any store invalidates it. Moreover, we only have local UIDs, so
12566 we also assume that there were stores in the intervening basic blocks. */
12567 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12568 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12571 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12575 for (i
= 0; i
< len
; i
++)
12579 /* Check for identical subexpressions. If x contains
12580 identical subexpression we only have to traverse one of
12582 if (i
== 1 && ARITHMETIC_P (x
))
12584 /* Note that at this point x0 has already been checked
12585 and found valid. */
12586 rtx x0
= XEXP (x
, 0);
12587 rtx x1
= XEXP (x
, 1);
12589 /* If x0 and x1 are identical then x is also valid. */
12593 /* If x1 is identical to a subexpression of x0 then
12594 while checking x0, x1 has already been checked. Thus
12595 it is valid and so as x. */
12596 if (ARITHMETIC_P (x0
)
12597 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12600 /* If x0 is identical to a subexpression of x1 then x is
12601 valid iff the rest of x1 is valid. */
12602 if (ARITHMETIC_P (x1
)
12603 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12605 get_last_value_validate (&XEXP (x1
,
12606 x0
== XEXP (x1
, 0) ? 1 : 0),
12607 insn
, tick
, replace
);
12610 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12614 else if (fmt
[i
] == 'E')
12615 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12616 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12617 insn
, tick
, replace
) == 0)
12621 /* If we haven't found a reason for it to be invalid, it is valid. */
12625 /* Get the last value assigned to X, if known. Some registers
12626 in the value may be replaced with (clobber (const_int 0)) if their value
12627 is known longer known reliably. */
12630 get_last_value (const_rtx x
)
12632 unsigned int regno
;
12634 reg_stat_type
*rsp
;
12636 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12637 then convert it to the desired mode. If this is a paradoxical SUBREG,
12638 we cannot predict what values the "extra" bits might have. */
12639 if (GET_CODE (x
) == SUBREG
12640 && subreg_lowpart_p (x
)
12641 && !paradoxical_subreg_p (x
)
12642 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12643 return gen_lowpart (GET_MODE (x
), value
);
12649 rsp
= ®_stat
[regno
];
12650 value
= rsp
->last_set_value
;
12652 /* If we don't have a value, or if it isn't for this basic block and
12653 it's either a hard register, set more than once, or it's a live
12654 at the beginning of the function, return 0.
12656 Because if it's not live at the beginning of the function then the reg
12657 is always set before being used (is never used without being set).
12658 And, if it's set only once, and it's always set before use, then all
12659 uses must have the same last value, even if it's not from this basic
12663 || (rsp
->last_set_label
< label_tick_ebb_start
12664 && (regno
< FIRST_PSEUDO_REGISTER
12665 || REG_N_SETS (regno
) != 1
12667 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12670 /* If the value was set in a later insn than the ones we are processing,
12671 we can't use it even if the register was only set once. */
12672 if (rsp
->last_set_label
== label_tick
12673 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12676 /* If the value has all its registers valid, return it. */
12677 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12680 /* Otherwise, make a copy and replace any invalid register with
12681 (clobber (const_int 0)). If that fails for some reason, return 0. */
12683 value
= copy_rtx (value
);
12684 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12690 /* Return nonzero if expression X refers to a REG or to memory
12691 that is set in an instruction more recent than FROM_LUID. */
12694 use_crosses_set_p (const_rtx x
, int from_luid
)
12698 enum rtx_code code
= GET_CODE (x
);
12702 unsigned int regno
= REGNO (x
);
12703 unsigned endreg
= END_REGNO (x
);
12705 #ifdef PUSH_ROUNDING
12706 /* Don't allow uses of the stack pointer to be moved,
12707 because we don't know whether the move crosses a push insn. */
12708 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12711 for (; regno
< endreg
; regno
++)
12713 reg_stat_type
*rsp
= ®_stat
[regno
];
12715 && rsp
->last_set_label
== label_tick
12716 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12722 if (code
== MEM
&& mem_last_set
> from_luid
)
12725 fmt
= GET_RTX_FORMAT (code
);
12727 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12732 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12733 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12736 else if (fmt
[i
] == 'e'
12737 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12743 /* Define three variables used for communication between the following
12746 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12747 static int reg_dead_flag
;
12749 /* Function called via note_stores from reg_dead_at_p.
12751 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12752 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12755 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12757 unsigned int regno
, endregno
;
12762 regno
= REGNO (dest
);
12763 endregno
= END_REGNO (dest
);
12764 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12765 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12768 /* Return nonzero if REG is known to be dead at INSN.
12770 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12771 referencing REG, it is dead. If we hit a SET referencing REG, it is
12772 live. Otherwise, see if it is live or dead at the start of the basic
12773 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12774 must be assumed to be always live. */
12777 reg_dead_at_p (rtx reg
, rtx insn
)
12782 /* Set variables for reg_dead_at_p_1. */
12783 reg_dead_regno
= REGNO (reg
);
12784 reg_dead_endregno
= END_REGNO (reg
);
12788 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12789 we allow the machine description to decide whether use-and-clobber
12790 patterns are OK. */
12791 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12793 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12794 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12798 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12799 beginning of basic block. */
12800 block
= BLOCK_FOR_INSN (insn
);
12805 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12807 return reg_dead_flag
== 1 ? 1 : 0;
12809 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12813 if (insn
== BB_HEAD (block
))
12816 insn
= PREV_INSN (insn
);
12819 /* Look at live-in sets for the basic block that we were in. */
12820 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12821 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12827 /* Note hard registers in X that are used. */
12830 mark_used_regs_combine (rtx x
)
12832 RTX_CODE code
= GET_CODE (x
);
12833 unsigned int regno
;
12844 case ADDR_DIFF_VEC
:
12847 /* CC0 must die in the insn after it is set, so we don't need to take
12848 special note of it here. */
12854 /* If we are clobbering a MEM, mark any hard registers inside the
12855 address as used. */
12856 if (MEM_P (XEXP (x
, 0)))
12857 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12862 /* A hard reg in a wide mode may really be multiple registers.
12863 If so, mark all of them just like the first. */
12864 if (regno
< FIRST_PSEUDO_REGISTER
)
12866 /* None of this applies to the stack, frame or arg pointers. */
12867 if (regno
== STACK_POINTER_REGNUM
12868 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12869 || regno
== HARD_FRAME_POINTER_REGNUM
12871 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12872 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12874 || regno
== FRAME_POINTER_REGNUM
)
12877 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12883 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12885 rtx testreg
= SET_DEST (x
);
12887 while (GET_CODE (testreg
) == SUBREG
12888 || GET_CODE (testreg
) == ZERO_EXTRACT
12889 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12890 testreg
= XEXP (testreg
, 0);
12892 if (MEM_P (testreg
))
12893 mark_used_regs_combine (XEXP (testreg
, 0));
12895 mark_used_regs_combine (SET_SRC (x
));
12903 /* Recursively scan the operands of this expression. */
12906 const char *fmt
= GET_RTX_FORMAT (code
);
12908 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12911 mark_used_regs_combine (XEXP (x
, i
));
12912 else if (fmt
[i
] == 'E')
12916 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12917 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12923 /* Remove register number REGNO from the dead registers list of INSN.
12925 Return the note used to record the death, if there was one. */
12928 remove_death (unsigned int regno
, rtx insn
)
12930 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12933 remove_note (insn
, note
);
12938 /* For each register (hardware or pseudo) used within expression X, if its
12939 death is in an instruction with luid between FROM_LUID (inclusive) and
12940 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12941 list headed by PNOTES.
12943 That said, don't move registers killed by maybe_kill_insn.
12945 This is done when X is being merged by combination into TO_INSN. These
12946 notes will then be distributed as needed. */
12949 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12954 enum rtx_code code
= GET_CODE (x
);
12958 unsigned int regno
= REGNO (x
);
12959 rtx where_dead
= reg_stat
[regno
].last_death
;
12961 /* Don't move the register if it gets killed in between from and to. */
12962 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12963 && ! reg_referenced_p (x
, maybe_kill_insn
))
12967 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12968 && DF_INSN_LUID (where_dead
) >= from_luid
12969 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12971 rtx note
= remove_death (regno
, where_dead
);
12973 /* It is possible for the call above to return 0. This can occur
12974 when last_death points to I2 or I1 that we combined with.
12975 In that case make a new note.
12977 We must also check for the case where X is a hard register
12978 and NOTE is a death note for a range of hard registers
12979 including X. In that case, we must put REG_DEAD notes for
12980 the remaining registers in place of NOTE. */
12982 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12983 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12984 > GET_MODE_SIZE (GET_MODE (x
))))
12986 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12987 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12988 unsigned int ourend
= END_HARD_REGNO (x
);
12991 for (i
= deadregno
; i
< deadend
; i
++)
12992 if (i
< regno
|| i
>= ourend
)
12993 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12996 /* If we didn't find any note, or if we found a REG_DEAD note that
12997 covers only part of the given reg, and we have a multi-reg hard
12998 register, then to be safe we must check for REG_DEAD notes
12999 for each register other than the first. They could have
13000 their own REG_DEAD notes lying around. */
13001 else if ((note
== 0
13003 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13004 < GET_MODE_SIZE (GET_MODE (x
)))))
13005 && regno
< FIRST_PSEUDO_REGISTER
13006 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13008 unsigned int ourend
= END_HARD_REGNO (x
);
13009 unsigned int i
, offset
;
13013 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13017 for (i
= regno
+ offset
; i
< ourend
; i
++)
13018 move_deaths (regno_reg_rtx
[i
],
13019 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13022 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13024 XEXP (note
, 1) = *pnotes
;
13028 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13034 else if (GET_CODE (x
) == SET
)
13036 rtx dest
= SET_DEST (x
);
13038 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13040 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13041 that accesses one word of a multi-word item, some
13042 piece of everything register in the expression is used by
13043 this insn, so remove any old death. */
13044 /* ??? So why do we test for equality of the sizes? */
13046 if (GET_CODE (dest
) == ZERO_EXTRACT
13047 || GET_CODE (dest
) == STRICT_LOW_PART
13048 || (GET_CODE (dest
) == SUBREG
13049 && (((GET_MODE_SIZE (GET_MODE (dest
))
13050 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13051 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13052 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13054 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13058 /* If this is some other SUBREG, we know it replaces the entire
13059 value, so use that as the destination. */
13060 if (GET_CODE (dest
) == SUBREG
)
13061 dest
= SUBREG_REG (dest
);
13063 /* If this is a MEM, adjust deaths of anything used in the address.
13064 For a REG (the only other possibility), the entire value is
13065 being replaced so the old value is not used in this insn. */
13068 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13073 else if (GET_CODE (x
) == CLOBBER
)
13076 len
= GET_RTX_LENGTH (code
);
13077 fmt
= GET_RTX_FORMAT (code
);
13079 for (i
= 0; i
< len
; i
++)
13084 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13085 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13088 else if (fmt
[i
] == 'e')
13089 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13093 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13094 pattern of an insn. X must be a REG. */
13097 reg_bitfield_target_p (rtx x
, rtx body
)
13101 if (GET_CODE (body
) == SET
)
13103 rtx dest
= SET_DEST (body
);
13105 unsigned int regno
, tregno
, endregno
, endtregno
;
13107 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13108 target
= XEXP (dest
, 0);
13109 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13110 target
= SUBREG_REG (XEXP (dest
, 0));
13114 if (GET_CODE (target
) == SUBREG
)
13115 target
= SUBREG_REG (target
);
13117 if (!REG_P (target
))
13120 tregno
= REGNO (target
), regno
= REGNO (x
);
13121 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13122 return target
== x
;
13124 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13125 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13127 return endregno
> tregno
&& regno
< endtregno
;
13130 else if (GET_CODE (body
) == PARALLEL
)
13131 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13132 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13138 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13139 as appropriate. I3 and I2 are the insns resulting from the combination
13140 insns including FROM (I2 may be zero).
13142 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13143 not need REG_DEAD notes because they are being substituted for. This
13144 saves searching in the most common cases.
13146 Each note in the list is either ignored or placed on some insns, depending
13147 on the type of note. */
13150 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13151 rtx elim_i1
, rtx elim_i0
)
13153 rtx note
, next_note
;
13156 for (note
= notes
; note
; note
= next_note
)
13158 rtx place
= 0, place2
= 0;
13160 next_note
= XEXP (note
, 1);
13161 switch (REG_NOTE_KIND (note
))
13165 /* Doesn't matter much where we put this, as long as it's somewhere.
13166 It is preferable to keep these notes on branches, which is most
13167 likely to be i3. */
13171 case REG_NON_LOCAL_GOTO
:
13176 gcc_assert (i2
&& JUMP_P (i2
));
13181 case REG_EH_REGION
:
13182 /* These notes must remain with the call or trapping instruction. */
13185 else if (i2
&& CALL_P (i2
))
13189 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13190 if (may_trap_p (i3
))
13192 else if (i2
&& may_trap_p (i2
))
13194 /* ??? Otherwise assume we've combined things such that we
13195 can now prove that the instructions can't trap. Drop the
13196 note in this case. */
13200 case REG_ARGS_SIZE
:
13201 /* ??? How to distribute between i3-i1. Assume i3 contains the
13202 entire adjustment. Assert i3 contains at least some adjust. */
13203 if (!noop_move_p (i3
))
13205 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13206 /* fixup_args_size_notes looks at REG_NORETURN note,
13207 so ensure the note is placed there first. */
13211 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13212 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13216 XEXP (n
, 1) = REG_NOTES (i3
);
13217 REG_NOTES (i3
) = n
;
13221 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13222 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13223 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13224 gcc_assert (old_size
!= args_size
13226 && !ACCUMULATE_OUTGOING_ARGS
13227 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13234 /* These notes must remain with the call. It should not be
13235 possible for both I2 and I3 to be a call. */
13240 gcc_assert (i2
&& CALL_P (i2
));
13246 /* Any clobbers for i3 may still exist, and so we must process
13247 REG_UNUSED notes from that insn.
13249 Any clobbers from i2 or i1 can only exist if they were added by
13250 recog_for_combine. In that case, recog_for_combine created the
13251 necessary REG_UNUSED notes. Trying to keep any original
13252 REG_UNUSED notes from these insns can cause incorrect output
13253 if it is for the same register as the original i3 dest.
13254 In that case, we will notice that the register is set in i3,
13255 and then add a REG_UNUSED note for the destination of i3, which
13256 is wrong. However, it is possible to have REG_UNUSED notes from
13257 i2 or i1 for register which were both used and clobbered, so
13258 we keep notes from i2 or i1 if they will turn into REG_DEAD
13261 /* If this register is set or clobbered in I3, put the note there
13262 unless there is one already. */
13263 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13265 if (from_insn
!= i3
)
13268 if (! (REG_P (XEXP (note
, 0))
13269 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13270 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13273 /* Otherwise, if this register is used by I3, then this register
13274 now dies here, so we must put a REG_DEAD note here unless there
13276 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13277 && ! (REG_P (XEXP (note
, 0))
13278 ? find_regno_note (i3
, REG_DEAD
,
13279 REGNO (XEXP (note
, 0)))
13280 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13282 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13290 /* These notes say something about results of an insn. We can
13291 only support them if they used to be on I3 in which case they
13292 remain on I3. Otherwise they are ignored.
13294 If the note refers to an expression that is not a constant, we
13295 must also ignore the note since we cannot tell whether the
13296 equivalence is still true. It might be possible to do
13297 slightly better than this (we only have a problem if I2DEST
13298 or I1DEST is present in the expression), but it doesn't
13299 seem worth the trouble. */
13301 if (from_insn
== i3
13302 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13307 /* These notes say something about how a register is used. They must
13308 be present on any use of the register in I2 or I3. */
13309 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13312 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13321 case REG_LABEL_TARGET
:
13322 case REG_LABEL_OPERAND
:
13323 /* This can show up in several ways -- either directly in the
13324 pattern, or hidden off in the constant pool with (or without?)
13325 a REG_EQUAL note. */
13326 /* ??? Ignore the without-reg_equal-note problem for now. */
13327 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13328 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13329 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13330 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13334 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13335 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13336 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13337 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13345 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13346 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13348 if (place
&& JUMP_P (place
)
13349 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13350 && (JUMP_LABEL (place
) == NULL
13351 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13353 rtx label
= JUMP_LABEL (place
);
13356 JUMP_LABEL (place
) = XEXP (note
, 0);
13357 else if (LABEL_P (label
))
13358 LABEL_NUSES (label
)--;
13361 if (place2
&& JUMP_P (place2
)
13362 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13363 && (JUMP_LABEL (place2
) == NULL
13364 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13366 rtx label
= JUMP_LABEL (place2
);
13369 JUMP_LABEL (place2
) = XEXP (note
, 0);
13370 else if (LABEL_P (label
))
13371 LABEL_NUSES (label
)--;
13377 /* This note says something about the value of a register prior
13378 to the execution of an insn. It is too much trouble to see
13379 if the note is still correct in all situations. It is better
13380 to simply delete it. */
13384 /* If we replaced the right hand side of FROM_INSN with a
13385 REG_EQUAL note, the original use of the dying register
13386 will not have been combined into I3 and I2. In such cases,
13387 FROM_INSN is guaranteed to be the first of the combined
13388 instructions, so we simply need to search back before
13389 FROM_INSN for the previous use or set of this register,
13390 then alter the notes there appropriately.
13392 If the register is used as an input in I3, it dies there.
13393 Similarly for I2, if it is nonzero and adjacent to I3.
13395 If the register is not used as an input in either I3 or I2
13396 and it is not one of the registers we were supposed to eliminate,
13397 there are two possibilities. We might have a non-adjacent I2
13398 or we might have somehow eliminated an additional register
13399 from a computation. For example, we might have had A & B where
13400 we discover that B will always be zero. In this case we will
13401 eliminate the reference to A.
13403 In both cases, we must search to see if we can find a previous
13404 use of A and put the death note there. */
13407 && from_insn
== i2mod
13408 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13413 && CALL_P (from_insn
)
13414 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13416 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13418 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13419 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13421 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13423 && reg_overlap_mentioned_p (XEXP (note
, 0),
13425 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13426 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13433 basic_block bb
= this_basic_block
;
13435 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13437 if (!NONDEBUG_INSN_P (tem
))
13439 if (tem
== BB_HEAD (bb
))
13444 /* If the register is being set at TEM, see if that is all
13445 TEM is doing. If so, delete TEM. Otherwise, make this
13446 into a REG_UNUSED note instead. Don't delete sets to
13447 global register vars. */
13448 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13449 || !global_regs
[REGNO (XEXP (note
, 0))])
13450 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13452 rtx set
= single_set (tem
);
13453 rtx inner_dest
= 0;
13455 rtx cc0_setter
= NULL_RTX
;
13459 for (inner_dest
= SET_DEST (set
);
13460 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13461 || GET_CODE (inner_dest
) == SUBREG
13462 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13463 inner_dest
= XEXP (inner_dest
, 0))
13466 /* Verify that it was the set, and not a clobber that
13467 modified the register.
13469 CC0 targets must be careful to maintain setter/user
13470 pairs. If we cannot delete the setter due to side
13471 effects, mark the user with an UNUSED note instead
13474 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13475 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13477 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13478 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13479 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13483 /* Move the notes and links of TEM elsewhere.
13484 This might delete other dead insns recursively.
13485 First set the pattern to something that won't use
13487 rtx old_notes
= REG_NOTES (tem
);
13489 PATTERN (tem
) = pc_rtx
;
13490 REG_NOTES (tem
) = NULL
;
13492 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13493 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13494 distribute_links (LOG_LINKS (tem
));
13496 SET_INSN_DELETED (tem
);
13501 /* Delete the setter too. */
13504 PATTERN (cc0_setter
) = pc_rtx
;
13505 old_notes
= REG_NOTES (cc0_setter
);
13506 REG_NOTES (cc0_setter
) = NULL
;
13508 distribute_notes (old_notes
, cc0_setter
,
13509 cc0_setter
, NULL_RTX
,
13510 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13511 distribute_links (LOG_LINKS (cc0_setter
));
13513 SET_INSN_DELETED (cc0_setter
);
13514 if (cc0_setter
== i2
)
13521 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13523 /* If there isn't already a REG_UNUSED note, put one
13524 here. Do not place a REG_DEAD note, even if
13525 the register is also used here; that would not
13526 match the algorithm used in lifetime analysis
13527 and can cause the consistency check in the
13528 scheduler to fail. */
13529 if (! find_regno_note (tem
, REG_UNUSED
,
13530 REGNO (XEXP (note
, 0))))
13535 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13537 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13541 /* If we are doing a 3->2 combination, and we have a
13542 register which formerly died in i3 and was not used
13543 by i2, which now no longer dies in i3 and is used in
13544 i2 but does not die in i2, and place is between i2
13545 and i3, then we may need to move a link from place to
13547 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13549 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13550 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13552 struct insn_link
*links
= LOG_LINKS (place
);
13553 LOG_LINKS (place
) = NULL
;
13554 distribute_links (links
);
13559 if (tem
== BB_HEAD (bb
))
13565 /* If the register is set or already dead at PLACE, we needn't do
13566 anything with this note if it is still a REG_DEAD note.
13567 We check here if it is set at all, not if is it totally replaced,
13568 which is what `dead_or_set_p' checks, so also check for it being
13571 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13573 unsigned int regno
= REGNO (XEXP (note
, 0));
13574 reg_stat_type
*rsp
= ®_stat
[regno
];
13576 if (dead_or_set_p (place
, XEXP (note
, 0))
13577 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13579 /* Unless the register previously died in PLACE, clear
13580 last_death. [I no longer understand why this is
13582 if (rsp
->last_death
!= place
)
13583 rsp
->last_death
= 0;
13587 rsp
->last_death
= place
;
13589 /* If this is a death note for a hard reg that is occupying
13590 multiple registers, ensure that we are still using all
13591 parts of the object. If we find a piece of the object
13592 that is unused, we must arrange for an appropriate REG_DEAD
13593 note to be added for it. However, we can't just emit a USE
13594 and tag the note to it, since the register might actually
13595 be dead; so we recourse, and the recursive call then finds
13596 the previous insn that used this register. */
13598 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13599 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13601 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13602 bool all_used
= true;
13605 for (i
= regno
; i
< endregno
; i
++)
13606 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13607 && ! find_regno_fusage (place
, USE
, i
))
13608 || dead_or_set_regno_p (place
, i
))
13616 /* Put only REG_DEAD notes for pieces that are
13617 not already dead or set. */
13619 for (i
= regno
; i
< endregno
;
13620 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13622 rtx piece
= regno_reg_rtx
[i
];
13623 basic_block bb
= this_basic_block
;
13625 if (! dead_or_set_p (place
, piece
)
13626 && ! reg_bitfield_target_p (piece
,
13629 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13632 distribute_notes (new_note
, place
, place
,
13633 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13636 else if (! refers_to_regno_p (i
, i
+ 1,
13637 PATTERN (place
), 0)
13638 && ! find_regno_fusage (place
, USE
, i
))
13639 for (tem
= PREV_INSN (place
); ;
13640 tem
= PREV_INSN (tem
))
13642 if (!NONDEBUG_INSN_P (tem
))
13644 if (tem
== BB_HEAD (bb
))
13648 if (dead_or_set_p (tem
, piece
)
13649 || reg_bitfield_target_p (piece
,
13652 add_reg_note (tem
, REG_UNUSED
, piece
);
13665 /* Any other notes should not be present at this point in the
13667 gcc_unreachable ();
13672 XEXP (note
, 1) = REG_NOTES (place
);
13673 REG_NOTES (place
) = note
;
13677 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13681 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13682 I3, I2, and I1 to new locations. This is also called to add a link
13683 pointing at I3 when I3's destination is changed. */
13686 distribute_links (struct insn_link
*links
)
13688 struct insn_link
*link
, *next_link
;
13690 for (link
= links
; link
; link
= next_link
)
13696 next_link
= link
->next
;
13698 /* If the insn that this link points to is a NOTE or isn't a single
13699 set, ignore it. In the latter case, it isn't clear what we
13700 can do other than ignore the link, since we can't tell which
13701 register it was for. Such links wouldn't be used by combine
13704 It is not possible for the destination of the target of the link to
13705 have been changed by combine. The only potential of this is if we
13706 replace I3, I2, and I1 by I3 and I2. But in that case the
13707 destination of I2 also remains unchanged. */
13709 if (NOTE_P (link
->insn
)
13710 || (set
= single_set (link
->insn
)) == 0)
13713 reg
= SET_DEST (set
);
13714 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13715 || GET_CODE (reg
) == STRICT_LOW_PART
)
13716 reg
= XEXP (reg
, 0);
13718 /* A LOG_LINK is defined as being placed on the first insn that uses
13719 a register and points to the insn that sets the register. Start
13720 searching at the next insn after the target of the link and stop
13721 when we reach a set of the register or the end of the basic block.
13723 Note that this correctly handles the link that used to point from
13724 I3 to I2. Also note that not much searching is typically done here
13725 since most links don't point very far away. */
13727 for (insn
= NEXT_INSN (link
->insn
);
13728 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13729 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13730 insn
= NEXT_INSN (insn
))
13731 if (DEBUG_INSN_P (insn
))
13733 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13735 if (reg_referenced_p (reg
, PATTERN (insn
)))
13739 else if (CALL_P (insn
)
13740 && find_reg_fusage (insn
, USE
, reg
))
13745 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13748 /* If we found a place to put the link, place it there unless there
13749 is already a link to the same insn as LINK at that point. */
13753 struct insn_link
*link2
;
13755 FOR_EACH_LOG_LINK (link2
, place
)
13756 if (link2
->insn
== link
->insn
)
13761 link
->next
= LOG_LINKS (place
);
13762 LOG_LINKS (place
) = link
;
13764 /* Set added_links_insn to the earliest insn we added a
13766 if (added_links_insn
== 0
13767 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13768 added_links_insn
= place
;
13774 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13775 Check whether the expression pointer to by LOC is a register or
13776 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13777 Otherwise return zero. */
13780 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13785 && (REG_P (x
) || MEM_P (x
))
13786 && ! reg_mentioned_p (x
, (rtx
) expr
))
13791 /* Check for any register or memory mentioned in EQUIV that is not
13792 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13793 of EXPR where some registers may have been replaced by constants. */
13796 unmentioned_reg_p (rtx equiv
, rtx expr
)
13798 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13801 DEBUG_FUNCTION
void
13802 dump_combine_stats (FILE *file
)
13806 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13807 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13811 dump_combine_total_stats (FILE *file
)
13815 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13816 total_attempts
, total_merges
, total_extras
, total_successes
);
13820 gate_handle_combine (void)
13822 return (optimize
> 0);
13825 /* Try combining insns through substitution. */
13826 static unsigned int
13827 rest_of_handle_combine (void)
13829 int rebuild_jump_labels_after_combine
;
13831 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13832 df_note_add_problem ();
13835 regstat_init_n_sets_and_refs ();
13837 rebuild_jump_labels_after_combine
13838 = combine_instructions (get_insns (), max_reg_num ());
13840 /* Combining insns may have turned an indirect jump into a
13841 direct jump. Rebuild the JUMP_LABEL fields of jumping
13843 if (rebuild_jump_labels_after_combine
)
13845 timevar_push (TV_JUMP
);
13846 rebuild_jump_labels (get_insns ());
13848 timevar_pop (TV_JUMP
);
13851 regstat_free_n_sets_and_refs ();
13857 const pass_data pass_data_combine
=
13859 RTL_PASS
, /* type */
13860 "combine", /* name */
13861 OPTGROUP_NONE
, /* optinfo_flags */
13862 true, /* has_gate */
13863 true, /* has_execute */
13864 TV_COMBINE
, /* tv_id */
13865 PROP_cfglayout
, /* properties_required */
13866 0, /* properties_provided */
13867 0, /* properties_destroyed */
13868 0, /* todo_flags_start */
13869 ( TODO_df_finish
| TODO_verify_rtl_sharing
), /* todo_flags_finish */
13872 class pass_combine
: public rtl_opt_pass
13875 pass_combine(gcc::context
*ctxt
)
13876 : rtl_opt_pass(pass_data_combine
, ctxt
)
13879 /* opt_pass methods: */
13880 bool gate () { return gate_handle_combine (); }
13881 unsigned int execute () { return rest_of_handle_combine (); }
13883 }; // class pass_combine
13885 } // anon namespace
13888 make_pass_combine (gcc::context
*ctxt
)
13890 return new pass_combine (ctxt
);