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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* And similarly, for notes. */
309 /* Basic block in which we are performing combines. */
313 \f
314 /* Length of the currently allocated uid_insn_cost array. */
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
330 };
336 {
340 }
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
352 /* Allocate a link. */
356 {
364 }
366 /* Incremented for each basic block. */
370 /* Reset to label_tick for each extended basic block in scanning order. */
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
383 in a loop. */
387 \f
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
393 struct undo
394 {
399 };
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
407 struct undobuf
408 {
412 };
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
422 scalar_int_mode,
425 scalar_int_mode,
497 \f
499 /* It is not safe to use ordinary gen_lowpart in combine.
500 See comments in gen_lowpart_for_combine. */
501 #undef RTL_HOOKS_GEN_LOWPART
502 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504 /* Our implementation of gen_lowpart never emits a new pseudo. */
505 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
506 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
509 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
512 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
515 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
519 \f
520 /* Convenience wrapper for the canonicalize_comparison target hook.
521 Target hooks cannot use enum rtx_code. */
525 {
529 }
531 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
532 PATTERN can not be split. Otherwise, it returns an insn sequence.
533 This is a wrapper around split_insns which ensures that the
534 reg_stat vector is made larger if the splitter creates a new
535 register. */
539 {
548 }
550 /* This is used by find_single_use to locate an rtx in LOC that
551 contains exactly one use of DEST, which is typically either a REG
552 or CC0. It returns a pointer to the innermost rtx expression
553 containing DEST. Appearances of DEST that are being used to
554 totally replace it are not counted. */
558 {
567 {
571 CASE_CONST_ANY:
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
597 }
599 /* If it wasn't one of the common cases above, check each expression and
600 vector of this code. Look for a unique usage of DEST. */
604 {
606 {
611 else
617 /* Duplicate usage. */
619 }
621 {
625 {
631 else
638 }
639 }
640 }
643 }
646 /* See if DEST, produced in INSN, is used only a single time in the
647 sequel. If so, return a pointer to the innermost rtx expression in which
648 it is used.
650 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
653 care about REG_DEAD notes or LOG_LINKS.
655 Otherwise, we find the single use by finding an insn that has a
656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
657 only referenced once in that insn, we know that it must be the first
658 and last insn referencing DEST. */
662 {
663 basic_block bb;
669 {
679 }
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 static void
822 {
831 else
840 }
842 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 \f
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
852 static bool
855 {
860 /* Lookup the original insn_costs. */
865 {
868 {
872 }
873 else
874 {
878 }
879 }
880 else
881 {
884 }
886 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 correct that. */
892 /* Calculate the replacement insn_costs. */
901 {
911 }
912 else
913 {
916 }
919 {
928 optimize_this_for_speed_p);
932 {
935 }
936 else
938 }
940 /* Disallow this combination if both new_cost and old_cost are greater than
941 zero, and new_cost is greater than old cost. */
945 {
964 else
966 }
971 /* Update the uid_insn_cost array with the replacement costs. */
975 {
979 }
982 }
985 /* Delete any insns that copy a register to itself. */
987 static void
989 {
991 basic_block bb;
994 {
996 {
999 {
1004 }
1005 }
1006 }
1007 }
1009 \f
1010 /* Return false if we do not want to (or cannot) combine DEF. */
1011 static bool
1013 {
1014 /* Do not consider if it is pre/post modification in MEM. */
1020 /* Do not combine frame pointer adjustments. */
1023 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1031 }
1033 /* Return false if we do not want to (or cannot) combine USE. */
1034 static bool
1036 {
1037 /* Do not consider the usage of the stack pointer by function call. */
1042 }
1044 /* Fill in log links field for all insns. */
1046 static void
1048 {
1049 basic_block bb;
1056 /* Pass through each block from the end, recording the uses of each
1057 register and establishing log links when def is encountered.
1058 Note that we do not clear next_use array in order to save time,
1059 so we have to test whether the use is in the same basic block as def.
1061 There are a few cases below when we do not consider the definition or
1062 usage -- these are taken from original flow.c did. Don't ask me why it is
1063 done this way; I don't know and if it works, I don't want to know. */
1066 {
1068 {
1072 /* Log links are created only once. */
1076 {
1092 /* flow.c claimed:
1094 We don't build a LOG_LINK for hard registers contained
1095 in ASM_OPERANDs. If these registers get replaced,
1096 we might wind up changing the semantics of the insn,
1097 even if reload can make what appear to be valid
1098 assignments later. */
1103 /* Don't add duplicate links between instructions. */
1112 }
1117 }
1118 }
1121 }
1123 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1124 true if we found a LOG_LINK that proves that A feeds B. This only works
1125 if there are no instructions between A and B which could have a link
1126 depending on A, since in that case we would not record a link for B.
1127 We also check the implicit dependency created by a cc0 setter/user
1128 pair. */
1130 static bool
1132 {
1140 }
1141 \f
1142 /* Main entry point for combiner. F is the first insn of the function.
1143 NREGS is the first unused pseudo-reg number.
1145 Return nonzero if the combiner has turned an indirect jump
1146 instruction into a direct jump. */
1147 static int
1149 {
1154 basic_block last_bb;
1174 /* Allocate array for insn info. */
1182 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1183 problems when, for example, we have j <<= 1 in a loop. */
1188 /* Scan all SETs and see if we can deduce anything about what
1189 bits are known to be zero for some registers and how many copies
1190 of the sign bit are known to exist for those registers.
1192 Also set any known values so that we can use it while searching
1193 for what bits are known to be set. */
1196 /* Allow the entry block and the first block to fall into the same EBB.
1197 Conceptually the incoming promotions are assigned to the entry block. */
1202 {
1207 label_tick++;
1215 {
1216 rtx links;
1222 insn);
1229 insn);
1231 /* Record the current insn_cost of this instruction. */
1235 {
1238 }
1239 }
1240 }
1244 /* Now scan all the insns in forward order. */
1252 {
1255 /* Ignore instruction combination in basic blocks that are going to
1256 be removed as unreachable anyway. See PR82386. */
1264 label_tick++;
1274 {
1288 /* See if we know about function return values before this
1289 insn based upon SUBREG flags. */
1292 /* See if we can find hardregs and subreg of pseudos in
1293 narrower modes. This could help turning TRUNCATEs
1294 into SUBREGs. */
1297 /* Try this insn with each insn it links back to. */
1303 {
1306 }
1308 /* Try each sequence of three linked insns ending with this one. */
1312 {
1315 /* If the linked insn has been replaced by a note, then there
1316 is no point in pursuing this chain any further. */
1324 {
1327 }
1328 }
1330 /* Try to combine a jump insn that uses CC0
1331 with a preceding insn that sets CC0, and maybe with its
1332 logical predecessor as well.
1333 This is how we make decrement-and-branch insns.
1334 We need this special code because data flow connections
1335 via CC0 do not get entered in LOG_LINKS. */
1342 {
1353 }
1355 /* Do the same for an insn that explicitly references CC0. */
1362 {
1373 }
1375 /* Finally, see if any of the insns that this insn links to
1376 explicitly references CC0. If so, try this insn, that insn,
1377 and its predecessor if it sets CC0. */
1379 {
1391 }
1393 /* Try combining an insn with two different insns whose results it
1394 uses. */
1404 {
1407 }
1409 /* Try four-instruction combinations. */
1412 {
1416 /* If the linked insn has been replaced by a note, then there
1417 is no point in pursuing this chain any further. */
1422 {
1426 /* I0 -> I1 -> I2 -> I3. */
1432 {
1435 }
1436 /* I0, I1 -> I2, I2 -> I3. */
1443 {
1446 }
1447 }
1450 {
1454 /* I0 -> I2; I1, I2 -> I3. */
1460 {
1463 }
1464 /* I0 -> I1; I1, I2 -> I3. */
1470 {
1473 }
1474 }
1475 }
1477 /* Try this insn with each REG_EQUAL note it links back to. */
1479 {
1485 /* Avoid using a register that may already been marked
1486 dead by an earlier instruction. */
1494 {
1495 /* Temporarily replace the set's source with the
1496 contents of the REG_EQUAL note. The insn will
1497 be deleted or recognized by try_combine. */
1508 last_combined_insn);
1511 {
1514 }
1517 }
1518 }
1523 retry:
1524 ;
1525 }
1526 }
1533 /* Clean up. */
1539 {
1542 {
1545 }
1547 }
1557 /* Make recognizer allow volatile MEMs again. */
1561 }
1563 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 static void
1567 {
1573 }
1574 \f
1575 /* Set up any promoted values for incoming argument registers. */
1577 static void
1579 {
1580 tree arg;
1585 {
1590 /* Only continue if the incoming argument is in a register. */
1594 /* Determine, if possible, whether all call sites of the current
1595 function lie within the current compilation unit. (This does
1596 take into account the exporting of a function via taking its
1597 address, and so forth.) */
1600 /* The mode and signedness of the argument before any promotions happen
1601 (equal to the mode of the pseudo holding it at that stage). */
1605 /* The mode and signedness of the argument after any source language and
1606 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1610 /* The mode and signedness of the argument as it is actually passed,
1611 see assign_parm_setup_reg in function.c. */
1615 /* The mode of the register in which the argument is being passed. */
1618 /* Eliminate sign extensions in the callee when:
1619 (a) A mode promotion has occurred; */
1622 /* (b) The mode of the register is the same as the mode of
1623 the argument as it is passed; */
1626 /* (c) There's no language level extension; */
1628 ;
1629 /* (c.1) All callers are from the current compilation unit. If that's
1630 the case we don't have to rely on an ABI, we only have to know
1631 what we're generating right now, and we know that we will do the
1632 mode1 to mode2 promotion with the given sign. */
1635 /* (c.2) The combination of the two promotions is useful. This is
1636 true when the signs match, or if the first promotion is unsigned.
1637 In the later case, (sign_extend (zero_extend x)) is the same as
1638 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1644 /* Record that the value was promoted from mode1 to mode3,
1645 so that any sign extension at the head of the current
1646 function may be eliminated. */
1650 }
1651 }
1653 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1654 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1655 because some machines (maybe most) will actually do the sign-extension and
1656 this is the conservative approach.
1658 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1659 kludge. */
1661 static rtx
1663 {
1664 scalar_int_mode int_mode;
1673 }
1675 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1676 and SET. */
1678 static void
1680 rtx x)
1681 {
1691 {
1695 }
1697 /* Don't call nonzero_bits if it cannot change anything. */
1699 {
1704 }
1706 /* Don't call num_sign_bit_copies if it cannot change anything. */
1708 {
1711 {
1715 }
1718 }
1719 }
1721 /* Called via note_stores. If X is a pseudo that is narrower than
1722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1724 If we are setting only a portion of X and we can't figure out what
1725 portion, assume all bits will be used since we don't know what will
1726 be happening.
1728 Similarly, set how many bits of X are known to be copies of the sign bit
1729 at all locations in the function. This is the smallest number implied
1730 by any set of X. */
1732 static void
1734 {
1736 scalar_int_mode mode;
1740 /* If this register is undefined at the start of the file, we can't
1741 say what its contents were. */
1742 && ! REGNO_REG_SET_P
1746 {
1750 {
1754 }
1756 /* Should not happen as we only using pseduo registers. */
1759 /* If this register is being initialized using itself, and the
1760 register is uninitialized in this basic block, and there are
1761 no LOG_LINKS which set the register, then part of the
1762 register is uninitialized. In that case we can't assume
1763 anything about the number of nonzero bits.
1765 ??? We could do better if we checked this in
1766 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1767 could avoid making assumptions about the insn which initially
1768 sets the register, while still using the information in other
1769 insns. We would have to be careful to check every insn
1770 involved in the combination. */
1776 {
1783 {
1787 }
1788 }
1790 /* If this is a complex assignment, see if we can convert it into a
1791 simple assignment. */
1794 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1795 set what we know about X. */
1801 else
1802 {
1805 }
1806 }
1807 }
1808 \f
1809 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1810 optionally insns that were previously combined into I3 or that will be
1811 combined into the merger of INSN and I3. The order is PRED, PRED2,
1812 INSN, SUCC, SUCC2, I3.
1814 Return 0 if the combination is not allowed for any reason.
1816 If the combination is allowed, *PDEST will be set to the single
1817 destination of INSN and *PSRC to the single source, and this function
1818 will return 1. */
1820 static int
1824 {
1829 rtx link;
1834 {
1836 {
1841 }
1846 }
1850 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1851 or a PARALLEL consisting of such a SET and CLOBBERs.
1853 If INSN has CLOBBER parallel parts, ignore them for our processing.
1854 By definition, these happen during the execution of the insn. When it
1855 is merged with another insn, all bets are off. If they are, in fact,
1856 needed and aren't also supplied in I3, they may be added by
1857 recog_for_combine. Otherwise, it won't match.
1859 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1860 note.
1862 Get the source and destination of INSN. If more than one, can't
1863 combine. */
1869 {
1871 {
1875 {
1876 /* This is important to combine floating point insns
1877 for the SH4 port. */
1879 /* Combining an isolated USE doesn't make sense.
1880 We depend here on combinable_i3pat to reject them. */
1881 /* The code below this loop only verifies that the inputs of
1882 the SET in INSN do not change. We call reg_set_between_p
1883 to verify that the REG in the USE does not change between
1884 I3 and INSN.
1885 If the USE in INSN was for a pseudo register, the matching
1886 insn pattern will likely match any register; combining this
1887 with any other USE would only be safe if we knew that the
1888 used registers have identical values, or if there was
1889 something to tell them apart, e.g. different modes. For
1890 now, we forgo such complicated tests and simply disallow
1891 combining of USES of pseudo registers with any other USE. */
1894 {
1899 do
1900 {
1910 }
1912 }
1915 /* We can ignore CLOBBERs. */
1921 /* Ignore SETs whose result isn't used but not those that
1922 have side-effects. */
1928 /* If we have already found a SET, this is a second one and
1929 so we cannot combine with this insn. */
1937 /* Anything else means we can't combine. */
1939 }
1940 }
1943 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1944 so don't do anything with it. */
1947 }
1948 else
1954 /* The simplification in expand_field_assignment may call back to
1955 get_last_value, so set safe guard here. */
1961 /* Do not eliminate user-specified register if it is in an
1962 asm input because we may break the register asm usage defined
1963 in GCC manual if allow to do so.
1964 Be aware that this may cover more cases than we expect but this
1965 should be harmless. */
1970 /* Don't eliminate a store in the stack pointer. */
1972 /* Don't combine with an insn that sets a register to itself if it has
1973 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1975 /* Can't merge an ASM_OPERANDS. */
1977 /* Can't merge a function call. */
1979 /* Don't eliminate a function call argument. */
1985 /* Don't substitute into an incremented register. */
1989 /* Don't substitute into a non-local goto, this confuses CFG. */
1991 /* Make sure that DEST is not used after INSN but before SUCC, or
1992 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1993 || (!all_adjacent
1994 && ((succ2
1999 || (succ
2000 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2001 that case SUCC is not in the insn stream, so use SUCC2
2002 instead for this test. */
2004 succ2
2007 /* Make sure that the value that is to be substituted for the register
2008 does not use any registers whose values alter in between. However,
2009 If the insns are adjacent, a use can't cross a set even though we
2010 think it might (this can happen for a sequence of insns each setting
2011 the same destination; last_set of that register might point to
2012 a NOTE). If INSN has a REG_EQUIV note, the register is always
2013 equivalent to the memory so the substitution is valid even if there
2014 are intervening stores. Also, don't move a volatile asm or
2015 UNSPEC_VOLATILE across any other insns. */
2016 || (! all_adjacent
2022 /* Don't combine across a CALL_INSN, because that would possibly
2023 change whether the life span of some REGs crosses calls or not,
2024 and it is a pain to update that information.
2025 Exception: if source is a constant, moving it later can't hurt.
2026 Accept that as a special case. */
2030 /* DEST must either be a REG or CC0. */
2032 {
2033 /* If register alignment is being enforced for multi-word items in all
2034 cases except for parameters, it is possible to have a register copy
2035 insn referencing a hard register that is not allowed to contain the
2036 mode being copied and which would not be valid as an operand of most
2037 insns. Eliminate this problem by not combining with such an insn.
2039 Also, on some machines we don't want to extend the life of a hard
2040 register. */
2045 /* Don't extend the life of a hard register unless it is
2046 user variable (if we have few registers) or it can't
2047 fit into the desired register (meaning something special
2048 is going on).
2049 Also avoid substituting a return register into I3, because
2050 reload can't handle a conflict with constraints of other
2051 inputs. */
2056 }
2064 {
2067 /* If the clobber represents an earlyclobber operand, we must not
2068 substitute an expression containing the clobbered register.
2069 As we do not analyze the constraint strings here, we have to
2070 make the conservative assumption. However, if the register is
2071 a fixed hard reg, the clobber cannot represent any operand;
2072 we leave it up to the machine description to either accept or
2073 reject use-and-clobber patterns. */
2079 }
2081 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2082 or not), reject, unless nothing volatile comes between it and I3 */
2085 {
2086 /* Make sure neither succ nor succ2 contains a volatile reference. */
2091 /* We'll check insns between INSN and I3 below. */
2092 }
2094 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2095 to be an explicit register variable, and was chosen for a reason. */
2101 /* If INSN contains volatile references (specifically volatile MEMs),
2102 we cannot combine across any other volatile references.
2103 Even if INSN doesn't contain volatile references, any intervening
2104 volatile insn might affect machine state. */
2107 ? volatile_refs_p
2114 /* If INSN contains an autoincrement or autodecrement, make sure that
2115 register is not used between there and I3, and not already used in
2116 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2117 Also insist that I3 not be a jump; if it were one
2118 and the incremented register were spilled, we would lose. */
2136 /* Don't combine an insn that follows a CC0-setting insn.
2137 An insn that uses CC0 must not be separated from the one that sets it.
2138 We do, however, allow I2 to follow a CC0-setting insn if that insn
2139 is passed as I1; in that case it will be deleted also.
2140 We also allow combining in this case if all the insns are adjacent
2141 because that would leave the two CC0 insns adjacent as well.
2142 It would be more logical to test whether CC0 occurs inside I1 or I2,
2143 but that would be much slower, and this ought to be equivalent. */
2146 {
2151 }
2153 /* If we get here, we have passed all the tests and the combination is
2154 to be allowed. */
2160 }
2161 \f
2162 /* LOC is the location within I3 that contains its pattern or the component
2163 of a PARALLEL of the pattern. We validate that it is valid for combining.
2165 One problem is if I3 modifies its output, as opposed to replacing it
2166 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2167 doing so would produce an insn that is not equivalent to the original insns.
2169 Consider:
2171 (set (reg:DI 101) (reg:DI 100))
2172 (set (subreg:SI (reg:DI 101) 0) <foo>)
2174 This is NOT equivalent to:
2176 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2177 (set (reg:DI 101) (reg:DI 100))])
2179 Not only does this modify 100 (in which case it might still be valid
2180 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2182 We can also run into a problem if I2 sets a register that I1
2183 uses and I1 gets directly substituted into I3 (not via I2). In that
2184 case, we would be getting the wrong value of I2DEST into I3, so we
2185 must reject the combination. This case occurs when I2 and I1 both
2186 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2187 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2188 of a SET must prevent combination from occurring. The same situation
2189 can occur for I0, in which case I0_NOT_IN_SRC is set.
2191 Before doing the above check, we first try to expand a field assignment
2192 into a set of logical operations.
2194 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2195 we place a register that is both set and used within I3. If more than one
2196 such register is detected, we fail.
2198 Return 1 if the combination is valid, zero otherwise. */
2200 static int
2203 {
2207 {
2212 rtx subdest;
2219 /* Check for the case where I3 modifies its output, as discussed
2220 above. We don't want to prevent pseudos from being combined
2221 into the address of a MEM, so only prevent the combination if
2222 i1 or i2 set the same MEM. */
2232 /* This is the same test done in can_combine_p except we can't test
2233 all_adjacent; we don't have to, since this instruction will stay
2234 in place, thus we are not considering increasing the lifetime of
2235 INNER_DEST.
2237 Also, if this insn sets a function argument, combining it with
2238 something that might need a spill could clobber a previous
2239 function argument; the all_adjacent test in can_combine_p also
2240 checks this; here, we do a more specific test for this case. */
2250 /* If DEST is used in I3, it is being killed in this insn, so
2251 record that for later. We have to consider paradoxical
2252 subregs here, since they kill the whole register, but we
2253 ignore partial subregs, STRICT_LOW_PART, etc.
2254 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2255 STACK_POINTER_REGNUM, since these are always considered to be
2256 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2264 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2270 {
2275 }
2276 }
2279 {
2286 }
2289 }
2290 \f
2291 /* Return 1 if X is an arithmetic expression that contains a multiplication
2292 and division. We don't count multiplications by powers of two here. */
2294 static int
2296 {
2298 {
2314 }
2315 }
2316 \f
2317 /* Determine whether INSN can be used in a combination. Return nonzero if
2318 not. This is used in try_combine to detect early some cases where we
2319 can't perform combinations. */
2321 static int
2323 {
2324 rtx set;
2327 /* If this isn't really an insn, we can't do anything.
2328 This can occur when flow deletes an insn that it has merged into an
2329 auto-increment address. */
2333 /* Never combine loads and stores involving hard regs that are likely
2334 to be spilled. The register allocator can usually handle such
2335 reg-reg moves by tying. If we allow the combiner to make
2336 substitutions of likely-spilled regs, reload might die.
2337 As an exception, we allow combinations involving fixed regs; these are
2338 not available to the register allocator so there's no risk involved. */
2359 }
2361 struct likely_spilled_retval_info
2362 {
2365 };
2367 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2368 hard registers that are known to be written to / clobbered in full. */
2369 static void
2371 {
2388 else
2391 }
2393 /* Return nonzero iff part of the return value is live during INSN, and
2394 it is likely spilled. This can happen when more than one insn is needed
2395 to copy the return value, e.g. when we consider to combine into the
2396 second copy insn for a complex value. */
2398 static int
2400 {
2402 rtx reg;
2405 /* We assume here that no machine mode needs more than
2406 32 hard registers when the value overlaps with a register
2407 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2422 /* Disregard parts of the return value that are set later. */
2431 /* Check if any of the (probably) live return value registers is
2432 likely spilled. */
2433 nregs --;
2434 do
2435 {
2441 }
2443 /* Adjust INSN after we made a change to its destination.
2445 Changing the destination can invalidate notes that say something about
2446 the results of the insn and a LOG_LINK pointing to the insn. */
2448 static void
2450 {
2451 /* For notes, be conservative and simply remove them. */
2454 /* The new insn will have a destination that was previously the destination
2455 of an insn just above it. Call distribute_links to make a LOG_LINK from
2456 the next use of that destination. */
2472 }
2474 /* Return TRUE if combine can reuse reg X in mode MODE.
2475 ADDED_SETS is nonzero if the original set is still required. */
2476 static bool
2478 {
2484 /* Don't change between modes with different underlying register sizes,
2485 since this could lead to invalid subregs. */
2491 /* Allow hard registers if the new mode is legal, and occupies no more
2492 registers than the old mode. */
2497 /* Or a pseudo that is only used once. */
2500 && !added_sets
2502 }
2505 /* Check whether X, the destination of a set, refers to part of
2506 the register specified by REG. */
2508 static bool
2510 {
2511 /* Check that reg is an integer mode register. */
2522 }
2524 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2525 Note that the INSN should be deleted *after* removing dead edges, so
2526 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2527 but not for a (set (pc) (label_ref FOO)). */
2529 static void
2531 {
2539 {
2544 /* Remove barriers from the footer if there are any. */
2547 {
2550 else
2554 }
2557 }
2558 }
2560 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2561 by an arbitrary number of CLOBBERs. */
2562 static bool
2564 {
2579 {
2588 }
2590 }
2592 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2593 CLOBBERs), can be split into individual SETs in that order, without
2594 changing semantics. */
2595 static bool
2597 {
2605 {
2614 }
2617 }
2619 /* Return whether X is just a single set, with the source
2620 a general_operand. */
2621 static bool
2623 {
2628 }
2630 /* Try to combine the insns I0, I1 and I2 into I3.
2631 Here I0, I1 and I2 appear earlier than I3.
2632 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2633 I3.
2635 If we are combining more than two insns and the resulting insn is not
2636 recognized, try splitting it into two insns. If that happens, I2 and I3
2637 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2638 Otherwise, I0, I1 and I2 are pseudo-deleted.
2640 Return 0 if the combination does not work. Then nothing is changed.
2641 If we did the combination, return the insn at which combine should
2642 resume scanning.
2644 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2645 new direct jump instruction.
2647 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2648 been I3 passed to an earlier try_combine within the same basic
2649 block. */
2654 {
2655 /* New patterns for I3 and I2, respectively. */
2659 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2660 dead. */
2662 /* Total number of SETs to put into I3. */
2664 /* Nonzero if I2's or I1's body now appears in I3. */
2666 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2668 /* Contains I3 if the destination of I3 is used in its source, which means
2669 that the old life of I3 is being killed. If that usage is placed into
2670 I2 and not in I3, a REG_DEAD note must be made. */
2672 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2674 /* Copy of SET_SRC of I1 and I0, if needed. */
2676 /* Set if I2DEST was reused as a scratch register. */
2678 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2680 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2685 /* Notes that must be added to REG_NOTES in I3 and I2. */
2687 /* Notes that we substituted I3 into I2 instead of the normal case. */
2689 /* Notes that I1, I2 or I3 is a MULT operation. */
2698 rtx temp_expr;
2701 rtx new_other_notes;
2705 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2706 never be). */
2710 /* Only try four-insn combinations when there's high likelihood of
2711 success. Look for simple insns, such as loads of constants or
2712 binary operations involving a constant. */
2714 {
2724 {
2727 rtx src;
2732 {
2735 }
2737 ngood++;
2740 nshift++;
2741 }
2743 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2744 are likely manipulating its value. Ideally we'll be able to combine
2745 all four insns into a bitfield insertion of some kind.
2747 Note the source in I0 might be inside a sign/zero extension and the
2748 memory modes in I0 and I3 might be different. So extract the address
2749 from the destination of I3 and search for it in the source of I0.
2751 In the event that there's a match but the source/dest do not actually
2752 refer to the same memory, the worst that happens is we try some
2753 combinations that we wouldn't have otherwise. */
2755 /* Ensure the source of SET0 is a MEM, possibly buried inside
2756 an extension. */
2762 /* Ensure the destination of SET3 is a MEM. */
2764 /* Would it be better to extract the base address for the MEM
2765 in SET3 and look for that? I don't have cases where it matters
2766 but I could envision such cases. */
2772 }
2774 /* Exit early if one of the insns involved can't be used for
2775 combinations. */
2786 combine_attempts++;
2789 /* Reset the hard register usage information. */
2793 {
2800 else
2810 }
2812 /* If multiple insns feed into one of I2 or I3, they can be in any
2813 order. To simplify the code below, reorder them in sequence. */
2824 /* First check for one important special case that the code below will
2825 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2826 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2827 we may be able to replace that destination with the destination of I3.
2828 This occurs in the common code where we compute both a quotient and
2829 remainder into a structure, in which case we want to do the computation
2830 directly into the structure to avoid register-register copies.
2832 Note that this case handles both multiple sets in I2 and also cases
2833 where I2 has a number of CLOBBERs inside the PARALLEL.
2835 We make very conservative checks below and only try to handle the
2836 most common cases of this. For example, we only handle the case
2837 where I2 and I3 are adjacent to avoid making difficult register
2838 usage tests. */
2846 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2847 below would need to check what is inside (and reg_overlap_mentioned_p
2848 doesn't support those codes anyway). Don't allow those destinations;
2849 the resulting insn isn't likely to be recognized anyway. */
2855 {
2858 /* Make sure that the destination of I3,
2859 which we are going to substitute into one output of I2,
2860 is not used within another output of I2. We must avoid making this:
2861 (parallel [(set (mem (reg 69)) ...)
2862 (set (reg 69) ...)])
2863 which is not well-defined as to order of actions.
2864 (Besides, reload can't handle output reloads for this.)
2866 The problem can also happen if the dest of I3 is a memory ref,
2867 if another dest in I2 is an indirect memory ref.
2869 Neither can this PARALLEL be an asm. We do not allow combining
2870 that usually (see can_combine_p), so do not here either. */
2873 {
2883 }
2889 {
2890 combine_merges++;
2900 /* Replace the dest in I2 with our dest and make the resulting
2901 insn the new pattern for I3. Then skip to where we validate
2902 the pattern. Everything was set up above. */
2907 }
2908 }
2910 /* If I2 is setting a pseudo to a constant and I3 is setting some
2911 sub-part of it to another constant, merge them by making a new
2912 constant. */
2920 {
2927 {
2932 {
2938 }
2939 }
2940 else
2941 {
2945 {
2948 }
2949 }
2952 {
2953 /* If this is the low part, we're done. */
2955 ;
2956 /* Handle the case where inner is twice the size of outer. */
2960 /* Otherwise give up for now. */
2961 else
2963 }
2966 {
2974 combine_merges++;
2981 /* Replace the source in I2 with the new constant and make the
2982 resulting insn the new pattern for I3. Then skip to where we
2983 validate the pattern. Everything was set up above. */
2989 /* The dest of I3 has been replaced with the dest of I2. */
2992 }
2993 }
2995 /* If we have no I1 and I2 looks like:
2996 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2997 (set Y OP)])
2998 make up a dummy I1 that is
2999 (set Y OP)
3000 and change I2 to be
3001 (set (reg:CC X) (compare:CC Y (const_int 0)))
3003 (We can ignore any trailing CLOBBERs.)
3005 This undoes a previous combination and allows us to match a branch-and-
3006 decrement insn. */
3018 {
3019 /* We make I1 with the same INSN_UID as I2. This gives it
3020 the same DF_INSN_LUID for value tracking. Our fake I1 will
3021 never appear in the insn stream so giving it the same INSN_UID
3022 as I2 will not cause a problem. */
3035 }
3037 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3038 make those two SETs separate I1 and I2 insns, and make an I0 that is
3039 the original I1. */
3047 {
3048 /* If there is no I1, there is no I0 either. */
3051 /* We make I1 with the same INSN_UID as I2. This gives it
3052 the same DF_INSN_LUID for value tracking. Our fake I1 will
3053 never appear in the insn stream so giving it the same INSN_UID
3054 as I2 will not cause a problem. */
3062 }
3064 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3066 {
3071 }
3073 {
3078 }
3080 {
3085 }
3087 /* Record whether i2 and i3 are trivial moves. */
3091 /* Record whether I2DEST is used in I2SRC and similarly for the other
3092 cases. Knowing this will help in register status updating below. */
3103 /* For the earlier insns, determine which of the subsequent ones they
3104 feed. */
3111 /* Ensure that I3's pattern can be the destination of combines. */
3117 {
3120 }
3122 /* See if any of the insns is a MULT operation. Unless one is, we will
3123 reject a combination that is, since it must be slower. Be conservative
3124 here. */
3132 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3133 We used to do this EXCEPT in one case: I3 has a post-inc in an
3134 output operand. However, that exception can give rise to insns like
3135 mov r3,(r3)+
3136 which is a famous insn on the PDP-11 where the value of r3 used as the
3137 source was model-dependent. Avoid this sort of thing. */
3139 #if 0
3145 /* It's not the exception. */
3146 #endif
3148 {
3149 rtx link;
3155 {
3158 }
3159 }
3161 /* See if the SETs in I1 or I2 need to be kept around in the merged
3162 instruction: whenever the value set there is still needed past I3.
3163 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3165 For the SET in I1, we have two cases: if I1 and I2 independently feed
3166 into I3, the set in I1 needs to be kept around unless I1DEST dies
3167 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3168 in I1 needs to be kept around unless I1DEST dies or is set in either
3169 I2 or I3. The same considerations apply to I0. */
3176 else
3184 else
3187 /* We are about to copy insns for the case where they need to be kept
3188 around. Check that they can be copied in the merged instruction. */
3194 {
3197 }
3199 /* If the set in I2 needs to be kept around, we must make a copy of
3200 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3201 PATTERN (I2), we are only substituting for the original I1DEST, not into
3202 an already-substituted copy. This also prevents making self-referential
3203 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3204 I2DEST. */
3207 {
3210 else
3212 }
3215 {
3218 else
3220 }
3223 {
3226 else
3228 }
3230 combine_merges++;
3232 /* Substitute in the latest insn for the regs set by the earlier ones. */
3238 /* Many machines that don't use CC0 have insns that can both perform an
3239 arithmetic operation and set the condition code. These operations will
3240 be represented as a PARALLEL with the first element of the vector
3241 being a COMPARE of an arithmetic operation with the constant zero.
3242 The second element of the vector will set some pseudo to the result
3243 of the same arithmetic operation. If we simplify the COMPARE, we won't
3244 match such a pattern and so will generate an extra insn. Here we test
3245 for this case, where both the comparison and the operation result are
3246 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3247 I2SRC. Later we will make the PARALLEL that contains I2. */
3253 {
3254 rtx newpat_dest;
3260 scalar_int_mode mode;
3269 {
3275 }
3277 /* Do the rest only if op1 is const0_rtx, which may be the
3278 result of simplification. */
3280 {
3281 /* If a single use of the CC is found, prepare to modify it
3282 when SELECT_CC_MODE returns a new CC-class mode, or when
3283 the above simplify_compare_const() returned a new comparison
3284 operator. undobuf.other_insn is assigned the CC use insn
3285 when modifying it. */
3287 {
3288 #ifdef SELECT_CC_MODE
3289 machine_mode new_mode
3294 {
3299 else
3300 {
3303 }
3304 }
3305 #endif
3306 /* Cases for modifying the CC-using comparison. */
3308 /* ??? Do we need to verify the zero rtx? */
3310 {
3311 /* Replace cc_use_loc with entire new RTX. */
3316 }
3318 {
3319 /* Just replace the CC reg with a new mode. */
3322 }
3323 }
3325 /* Now we modify the current newpat:
3326 First, SET_DEST(newpat) is updated if the CC mode has been
3327 altered. For targets without SELECT_CC_MODE, this should be
3328 optimized away. */
3331 /* This is always done to propagate i2src into newpat. */
3334 /* Create new version of i2pat if needed; the below PARALLEL
3335 creation needs this to work correctly. */
3339 }
3340 }
3343 {
3344 /* It is possible that the source of I2 or I1 may be performing
3345 an unneeded operation, such as a ZERO_EXTEND of something
3346 that is known to have the high part zero. Handle that case
3347 by letting subst look at the inner insns.
3349 Another way to do this would be to have a function that tries
3350 to simplify a single insn instead of merging two or more
3351 insns. We don't do this because of the potential of infinite
3352 loops and because of the potential extra memory required.
3353 However, doing it the way we are is a bit of a kludge and
3354 doesn't catch all cases.
3356 But only do this if -fexpensive-optimizations since it slows
3357 things down and doesn't usually win.
3359 This is not done in the COMPARE case above because the
3360 unmodified I2PAT is used in the PARALLEL and so a pattern
3361 with a modified I2SRC would not match. */
3364 {
3365 /* Pass pc_rtx so no substitutions are done, just
3366 simplifications. */
3368 {
3371 }
3375 }
3380 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3381 copy of I2SRC each time we substitute it, in order to avoid creating
3382 self-referential RTL when we will be substituting I1SRC for I1DEST
3383 later. Likewise if I0 feeds into I2, either directly or indirectly
3384 through I1, and I0DEST is in I0SRC. */
3391 /* Record whether I2's body now appears within I3's body. */
3393 }
3395 /* If we already got a failure, don't try to do more. Otherwise, try to
3396 substitute I1 if we have it. */
3399 {
3400 /* Check that an autoincrement side-effect on I1 has not been lost.
3401 This happens if I1DEST is mentioned in I2 and dies there, and
3402 has disappeared from the new pattern. */
3404 && i1_feeds_i2_n
3407 /* Before we can do this substitution, we must redo the test done
3408 above (see detailed comments there) that ensures I1DEST isn't
3409 mentioned in any SETs in NEWPAT that are field assignments. */
3412 {
3415 }
3420 /* If the following substitution will modify I1SRC, make a copy of it
3421 for the case where it is substituted for I1DEST in I2PAT later. */
3425 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3426 copy of I1SRC each time we substitute it, in order to avoid creating
3427 self-referential RTL when we will be substituting I0SRC for I0DEST
3428 later. */
3433 /* Record whether I1's body now appears within I3's body. */
3435 }
3437 /* Likewise for I0 if we have it. */
3440 {
3447 {
3450 }
3452 /* If the following substitution will modify I0SRC, make a copy of it
3453 for the case where it is substituted for I0DEST in I1PAT later. */
3456 /* And a copy for I0DEST in I2PAT substitution. */
3465 }
3467 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3468 to count all the ways that I2SRC and I1SRC can be used. */
3479 /* Fail if we tried to make a new register. */
3481 /* Fail if we couldn't do something and have a CLOBBER. */
3483 /* Fail if this new pattern is a MULT and we didn't have one before
3484 at the outer level. */
3487 {
3490 }
3492 /* If the actions of the earlier insns must be kept
3493 in addition to substituting them into the latest one,
3494 we must make a new PARALLEL for the latest insn
3495 to hold additional the SETs. */
3498 {
3500 combine_extras++;
3503 {
3509 }
3510 else
3511 {
3516 }
3522 {
3528 }
3530 {
3539 }
3540 }
3542 validate_replacement:
3544 /* Note which hard regs this insn has as inputs. */
3547 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3548 consider splitting this pattern, we might need these clobbers. */
3551 {
3557 }
3559 /* We have recognized nothing yet. */
3562 /* See if this is a PARALLEL of two SETs where one SET's destination is
3563 a register that is unused and this isn't marked as an instruction that
3564 might trap in an EH region. In that case, we just need the other SET.
3565 We prefer this over the PARALLEL.
3567 This can occur when simplifying a divmod insn. We *must* test for this
3568 case here because the code below that splits two independent SETs doesn't
3569 handle this case correctly when it updates the register status.
3571 It's pointless doing this if we originally had two sets, one from
3572 i3, and one from i2. Combining then splitting the parallel results
3573 in the original i2 again plus an invalid insn (which we delete).
3574 The net effect is only to move instructions around, which makes
3575 debug info less accurate.
3577 If the remaining SET came from I2 its destination should not be used
3578 between I2 and I3. See PR82024. */
3583 {
3594 {
3597 }
3606 {
3611 {
3617 }
3618 }
3622 }
3624 /* Is the result of combination a valid instruction? */
3628 /* If we were combining three insns and the result is a simple SET
3629 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3630 insns. There are two ways to do this. It can be split using a
3631 machine-specific method (like when you have an addition of a large
3632 constant) or by combine in the function find_split_point. */
3636 {
3640 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3641 use I2DEST as a scratch register will help. In the latter case,
3642 convert I2DEST to the mode of the source of NEWPAT if we can. */
3646 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3647 inputs of NEWPAT. */
3649 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3650 possible to try that as a scratch reg. This would require adding
3651 more code to make it work though. */
3654 {
3657 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3658 (temporarily, until we are committed to this instruction
3659 combination) does not work: for example, any call to nonzero_bits
3660 on the register (from a splitter in the MD file, for example)
3661 will get the old information, which is invalid.
3663 Since nowadays we can create registers during combine just fine,
3664 we should just create a new one here, not reuse i2dest. */
3666 /* First try to split using the original register as a
3667 scratch register. */
3671 i2dest)));
3674 /* If that didn't work, try changing the mode of I2DEST if
3675 we can. */
3680 {
3682 rtx ni2dest;
3686 else
3687 {
3690 }
3692 parallel = (gen_rtx_PARALLEL
3696 ni2dest))));
3701 {
3709 }
3710 }
3713 }
3715 /* If recog_for_combine has discarded clobbers, try to use them
3716 again for the split. */
3718 {
3721 }
3724 {
3729 }
3733 {
3743 /* If I2 or I3 has multiple SETs, we won't know how to track
3744 register status, so don't use these insns. If I2's destination
3745 is used between I2 and I3, we also can't use these insns. */
3755 /* It is possible that both insns now set the destination of I3.
3756 If so, we must show an extra use of it. */
3759 {
3778 }
3779 }
3781 /* If we can split it and use I2DEST, go ahead and see if that
3782 helps things be recognized. Verify that none of the registers
3783 are set between I2 and I3. */
3787 /* We need I2DEST in the proper mode. If it is a hard register
3788 or the only use of a pseudo, we can change its mode.
3789 Make sure we don't change a hard register to have a mode that
3790 isn't valid for it, or change the number of registers. */
3797 /* We can't overwrite I2DEST if its value is still used by
3798 NEWPAT. */
3800 {
3809 /* *SPLIT may be part of I2SRC, so make sure we have the
3810 original expression around for later debug processing.
3811 We should not need I2SRC any more in other cases. */
3814 else
3817 /* Get NEWDEST as a register in the proper mode. We have already
3818 validated that we can do this. */
3820 {
3823 else
3824 {
3827 }
3828 }
3830 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3831 an ASHIFT. This can occur if it was inside a PLUS and hence
3832 appeared to be a memory address. This is a kludge. */
3837 {
3841 /* Update split_code because we may not have a multiply
3842 anymore. */
3844 }
3846 /* Similarly for (plus (mult FOO (const_int pow2))). */
3852 {
3857 i_rtx));
3858 /* Update split_code because we may not have a multiply
3859 anymore. */
3861 }
3863 #ifdef INSN_SCHEDULING
3864 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3865 be written as a ZERO_EXTEND. */
3867 {
3868 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3869 what it really is. */
3874 else
3877 }
3878 #endif
3880 /* Attempt to split binary operators using arithmetic identities. */
3884 {
3891 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3893 {
3898 }
3899 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3906 {
3912 /* Split both "((X op Y) op X) op Y" and
3913 "((X op Y) op Y) op X" as "T op T" where T is
3914 "X op Y". */
3917 {
3922 }
3923 /* Split "((X op X) op Y) op Y)" as "T op T" where
3924 T is "X op Y". */
3926 {
3932 }
3933 }
3934 }
3937 {
3940 }
3944 /* recog_for_combine might have added CLOBBERs to newi2pat.
3945 Make sure NEWPAT does not depend on the clobbered regs. */
3949 {
3952 {
3955 }
3956 }
3958 /* If the split point was a MULT and we didn't have one before,
3959 don't use one now. */
3962 }
3963 }
3965 /* Check for a case where we loaded from memory in a narrow mode and
3966 then sign extended it, but we need both registers. In that case,
3967 we have a PARALLEL with both loads from the same memory location.
3968 We can split this into a load from memory followed by a register-register
3969 copy. This saves at least one insn, more if register allocation can
3970 eliminate the copy.
3972 We cannot do this if the destination of the first assignment is a
3973 condition code register or cc0. We eliminate this case by making sure
3974 the SET_DEST and SET_SRC have the same mode.
3976 We cannot do this if the destination of the second assignment is
3977 a register that we have already assumed is zero-extended. Similarly
3978 for a SUBREG of such a register. */
3997 BITS_PER_WORD)
3999 HOST_BITS_PER_INT)
4007 BITS_PER_WORD)
4009 HOST_BITS_PER_INT)
4016 {
4017 rtx ni2dest;
4031 }
4033 /* Similarly, check for a case where we have a PARALLEL of two independent
4034 SETs but we started with three insns. In this case, we can do the sets
4035 as two separate insns. This case occurs when some SET allows two
4036 other insns to combine, but the destination of that SET is still live.
4038 Also do this if we started with two insns and (at least) one of the
4039 resulting sets is a noop; this noop will be deleted later. */
4046 && (i1
4060 {
4064 /* Normally, it doesn't matter which of the two is done first,
4065 but the one that references cc0 can't be the second, and
4066 one which uses any regs/memory set in between i2 and i3 can't
4067 be first. The PARALLEL might also have been pre-existing in i3,
4068 so we need to make sure that we won't wrongly hoist a SET to i2
4069 that would conflict with a death note present in there. */
4077 /* If I3 is a jump, ensure that set0 is a jump so that
4078 we do not create invalid RTL. */
4080 )
4081 {
4084 }
4092 /* If I3 is a jump, ensure that set1 is a jump so that
4093 we do not create invalid RTL. */
4095 )
4096 {
4099 }
4100 else
4101 {
4104 }
4109 {
4110 /* recog_for_combine might have added CLOBBERs to newi2pat.
4111 Make sure NEWPAT does not depend on the clobbered regs. */
4113 {
4116 {
4119 {
4122 }
4123 }
4124 }
4130 }
4131 }
4133 /* If it still isn't recognized, fail and change things back the way they
4134 were. */
4136 /* Is the result a reasonable ASM_OPERANDS? */
4138 {
4141 }
4143 /* If we had to change another insn, make sure it is valid also. */
4145 {
4153 {
4156 }
4157 }
4159 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4160 they are adjacent to each other or not. */
4162 {
4166 {
4169 }
4170 }
4172 /* Only allow this combination if insn_cost reports that the
4173 replacement instructions are cheaper than the originals. */
4175 {
4178 }
4181 {
4186 {
4191 /* Temporarily revert mode back. */
4195 {
4196 /* If we used i2dest as a scratch register with a
4197 different mode, substitute it for the original
4198 i2src while its original mode is temporarily
4199 restored, and then clear i2scratch so that we don't
4200 do it again later. */
4202 this_basic_block);
4204 /* Put back the new mode. */
4206 }
4207 else
4208 {
4213 {
4216 }
4217 else
4218 {
4225 }
4227 /* We're dealing with a reg that changed mode but not
4228 meaning, so we want to turn it into a subreg for
4229 the new mode. However, because of REG sharing and
4230 because its mode had already changed, we have to do
4231 it in two steps. First, replace any debug uses of
4232 reg, with its original mode temporarily restored,
4233 with this copy we have created; then, replace the
4234 copy with the SUBREG of the original shared reg,
4235 once again changed to the new mode. */
4237 this_basic_block);
4241 this_basic_block);
4242 }
4243 }
4244 }
4246 /* If we will be able to accept this, we have made a
4247 change to the destination of I3. This requires us to
4248 do a few adjustments. */
4251 {
4254 }
4256 /* We now know that we can do this combination. Merge the insns and
4257 update the status of registers and LOG_LINKS. */
4260 {
4265 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4266 ensure that they are still valid. Then add any non-duplicate
4267 notes added by recog_for_combine. */
4269 {
4278 /* Simply drop equal note since it may be no longer valid
4279 for other_insn. It may be possible to record that CC
4280 register is changed and only discard those notes, but
4281 in practice it's unnecessary complication and doesn't
4282 give any meaningful improvement.
4284 See PR78559. */
4288 }
4292 NULL_RTX);
4293 }
4296 {
4297 /* I3 now uses what used to be its destination and which is now
4298 I2's destination. This requires us to do a few adjustments. */
4301 }
4304 {
4305 /* We might need a LOG_LINK from I3 to I2. But then we used to
4306 have one, so we still will.
4308 However, some later insn might be using I2's dest and have
4309 a LOG_LINK pointing at I3. We should change it to point at
4310 I2 instead. */
4312 /* newi2pat is usually a SET here; however, recog_for_combine might
4313 have added some clobbers. */
4318 /* It can only be a SET of a REG or of a SUBREG of a REG. */
4323 !done
4324 && insn
4328 {
4332 {
4336 }
4337 }
4338 }
4340 {
4345 /* Compute which registers we expect to eliminate. newi2pat may be setting
4346 either i3dest or i2dest, so we must check it. */
4349 || !i2dest_killed
4351 /* For i1, we need to compute both local elimination and global
4352 elimination information with respect to newi2pat because i1dest
4353 may be the same as i3dest, in which case newi2pat may be setting
4354 i1dest. Global information is used when distributing REG_DEAD
4355 note for i2 and i3, in which case it does matter if newi2pat sets
4356 i1dest or not.
4358 Local information is used when distributing REG_DEAD note for i1,
4359 in which case it doesn't matter if newi2pat sets i1dest or not.
4360 See PR62151, if we have four insns combination:
4361 i0: r0 <- i0src
4362 i1: r1 <- i1src (using r0)
4363 REG_DEAD (r0)
4364 i2: r0 <- i2src (using r1)
4365 i3: r3 <- i3src (using r0)
4366 ix: using r0
4367 From i1's point of view, r0 is eliminated, no matter if it is set
4368 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4369 should be discarded.
4371 Note local information only affects cases in forms like "I1->I2->I3",
4372 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4373 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4374 i0dest anyway. */
4376 || !i1dest_killed
4381 /* Same case as i1. */
4388 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4389 clear them. */
4397 /* Ensure that we do not have something that should not be shared but
4398 occurs multiple times in the new insns. Check this by first
4399 resetting all the `used' flags and then copying anything is shared. */
4423 {
4426 {
4428 {
4429 /* I2SRC must still be meaningful at this point. Some
4430 splitting operations can invalidate I2SRC, but those
4431 operations do not apply to calls. */
4435 }
4442 }
4443 }
4448 /* We had one special case above where I2 had more than one set and
4449 we replaced a destination of one of those sets with the destination
4450 of I3. In that case, we have to update LOG_LINKS of insns later
4451 in this basic block. Note that this (expensive) case is rare.
4453 Also, in this case, we must pretend that all REG_NOTEs for I2
4454 actually came from I3, so that REG_UNUSED notes from I2 will be
4455 properly handled. */
4458 {
4467 temp_insn
4477 {
4482 }
4483 else
4486 }
4494 {
4497 this_basic_block);
4500 }
4501 else
4502 {
4505 this_basic_block);
4507 }
4510 {
4515 this_basic_block);
4517 }
4520 {
4525 this_basic_block);
4527 }
4529 /* Get death notes for everything that is now used in either I3 or
4530 I2 and used to die in a previous insn. If we built two new
4531 patterns, move from I1 to I2 then I2 to I3 so that we get the
4532 proper movement on registers that I2 modifies. */
4538 else
4544 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4561 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4562 know these are REG_UNUSED and want them to go to the desired insn,
4563 so we always pass it as i3. */
4567 NULL_RTX);
4571 NULL_RTX);
4573 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4574 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4575 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4576 in that case, it might delete I2. Similarly for I2 and I1.
4577 Show an additional death due to the REG_DEAD note we make here. If
4578 we discard it in distribute_notes, we will decrement it again. */
4581 {
4586 else
4589 }
4592 {
4597 else
4600 }
4603 {
4608 else
4611 }
4614 {
4619 else
4622 }
4630 {
4635 /* The insn that used to set this register doesn't exist, and
4636 this life of the register may not exist either. See if one of
4637 I3's links points to an insn that sets I2DEST. If it does,
4638 that is now the last known value for I2DEST. If we don't update
4639 this and I2 set the register to a value that depended on its old
4640 contents, we will get confused. If this insn is used, thing
4641 will be set correctly in combine_instructions. */
4649 /* If the reg formerly set in I2 died only once and that was in I3,
4650 zero its use count so it won't make `reload' do any work. */
4653 && ! i2dest_in_i2src
4656 }
4659 {
4672 && ! i1dest_in_i1src
4675 }
4678 {
4691 && ! i0dest_in_i0src
4694 }
4696 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4697 been made to this insn. The order is important, because newi2pat
4698 can affect nonzero_bits of newpat. */
4702 }
4705 {
4707 {
4710 }
4712 }
4715 {
4717 {
4720 }
4722 }
4725 {
4727 {
4730 }
4732 }
4735 {
4737 {
4740 }
4742 }
4745 {
4747 {
4750 }
4752 }
4754 /* Set new_direct_jump_p if a new return or simple jump instruction
4755 has been created. Adjust the CFG accordingly. */
4757 {
4761 }
4766 {
4769 }
4773 {
4779 }
4784 {
4790 }
4792 /* A noop might also need cleaning up of CFG, if it comes from the
4793 simplification of a jump. */
4798 {
4801 }
4808 {
4811 }
4813 combine_successes++;
4823 }
4824 \f
4825 /* Get a marker for undoing to the current state. */
4829 {
4831 }
4833 /* Undo the modifications up to the marker. */
4835 static void
4837 {
4841 {
4846 {
4861 }
4865 }
4868 }
4870 /* Undo all the modifications recorded in undobuf. */
4872 static void
4874 {
4876 }
4878 /* We've committed to accepting the changes we made. Move all
4879 of the undos to the free list. */
4881 static void
4883 {
4887 {
4891 }
4893 }
4894 \f
4895 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4896 where we have an arithmetic expression and return that point. LOC will
4897 be inside INSN.
4899 try_combine will call this function to see if an insn can be split into
4900 two insns. */
4904 {
4914 /* First special-case some codes. */
4916 {
4918 #ifdef INSN_SCHEDULING
4919 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4920 point. */
4923 #endif
4927 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4928 using LO_SUM and HIGH. */
4931 {
4939 }
4941 /* If we have a PLUS whose second operand is a constant and the
4942 address is not valid, perhaps will can split it up using
4943 the machine-specific way to split large constants. We use
4944 the first pseudo-reg (one of the virtual regs) as a placeholder;
4945 it will not remain in the result. */
4950 {
4953 subst_insn);
4955 /* This should have produced two insns, each of which sets our
4956 placeholder. If the source of the second is a valid address,
4957 we can make put both sources together and make a split point
4958 in the middle. */
4971 && memory_address_addr_space_p
4974 {
4978 /* Replace the placeholder in SRC2 with SRC1. If we can
4979 find where in SRC2 it was placed, that can become our
4980 split point and we can replace this address with SRC2.
4981 Just try two obvious places. */
4992 {
4995 }
4996 }
4998 /* If that didn't work, perhaps the first operand is complex and
4999 needs to be computed separately, so make a split point there.
5000 This will occur on machines that just support REG + CONST
5001 and have a constant moved through some previous computation. */
5007 }
5009 /* If we have a PLUS whose first operand is complex, try computing it
5010 separately by making a split there. */
5021 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5022 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5023 we need to put the operand into a register. So split at that
5024 point. */
5034 /* See if we can split SET_SRC as it stands. */
5039 /* See if we can split SET_DEST as it stands. */
5044 /* See if this is a bitfield assignment with everything constant. If
5045 so, this is an IOR of an AND, so split it into that. */
5057 {
5062 unsigned HOST_WIDE_INT mask
5064 rtx or_mask;
5073 else
5074 {
5080 or_mask));
5081 }
5088 }
5090 /* Otherwise, see if this is an operation that we can split into two.
5091 If so, try to split that. */
5095 {
5097 /* If we are AND'ing with a large constant that is only a single
5098 bit and the result is only being used in a context where we
5099 need to know if it is zero or nonzero, replace it with a bit
5100 extraction. This will avoid the large constant, which might
5101 have taken more than one insn to make. If the constant were
5102 not a valid argument to the AND but took only one insn to make,
5103 this is no worse, but if it took more than one insn, it will
5104 be better. */
5114 {
5119 {
5122 }
5123 }
5127 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5128 is known to be on, this can be converted into a NEG of a shift. */
5134 {
5141 pos_rtx)));
5146 }
5152 /* We can't optimize if either mode is a partial integer
5153 mode as we don't know how many bits are significant
5154 in those modes. */
5170 {
5178 }
5183 }
5189 {
5190 /* For unsigned, we have a choice of a shift followed by an
5191 AND or two shifts. Use two shifts for field sizes where the
5192 constant might be too large. We assume here that we can
5193 always at least get 8-bit constants in an AND insn, which is
5194 true for every current RISC. */
5197 {
5198 unsigned HOST_WIDE_INT mask
5203 gen_rtx_LSHIFTRT
5210 }
5211 else
5212 {
5216 gen_rtx_fmt_ee
5226 }
5227 }
5229 /* See if this is a simple operation with a constant as the second
5230 operand. It might be that this constant is out of range and hence
5231 could be used as a split point. */
5239 /* Finally, see if this is a simple operation with its first operand
5240 not in a register. The operation might require this operand in a
5241 register, so return it as a split point. We can always do this
5242 because if the first operand were another operation, we would have
5243 already found it as a split point. */
5252 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5253 it is better to write this as (not (ior A B)) so we can split it.
5254 Similarly for IOR. */
5256 {
5264 }
5266 /* Many RISC machines have a large set of logical insns. If the
5267 second operand is a NOT, put it first so we will try to split the
5268 other operand first. */
5270 {
5274 }
5279 /* Canonicalization can produce (minus A (mult B C)), where C is a
5280 constant. It may be better to try splitting (plus (mult B -C) A)
5281 instead if this isn't a multiply by a power of two. */
5285 {
5293 mode)),
5296 }
5298 /* Split at a multiply-accumulate instruction. However if this is
5299 the SET_SRC, we likely do not have such an instruction and it's
5300 worthless to try this split. */
5309 }
5311 /* Otherwise, select our actions depending on our rtx class. */
5313 {
5319 /* fall through */
5327 /* fall through */
5329 /* Some machines have (and (shift ...) ...) insns. If X is not
5330 an AND, but XEXP (X, 0) is, use it as our split point. */
5340 /* Otherwise, we don't have a split point. */
5342 }
5343 }
5344 \f
5345 /* Throughout X, replace FROM with TO, and return the result.
5346 The result is TO if X is FROM;
5347 otherwise the result is X, but its contents may have been modified.
5348 If they were modified, a record was made in undobuf so that
5349 undo_all will (among other things) return X to its original state.
5351 If the number of changes necessary is too much to record to undo,
5352 the excess changes are not made, so the result is invalid.
5353 The changes already made can still be undone.
5354 undobuf.num_undo is incremented for such changes, so by testing that
5355 the caller can tell whether the result is valid.
5357 `n_occurrences' is incremented each time FROM is replaced.
5359 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5361 IN_COND is nonzero if we are at the top level of a condition.
5363 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5364 by copying if `n_occurrences' is nonzero. */
5366 static rtx
5368 {
5373 rtx new_rtx;
5375 /* Two expressions are equal if they are identical copies of a shared
5376 RTX or if they are both registers with the same register number
5377 and mode. */
5379 #define COMBINE_RTX_EQUAL_P(X,Y) \
5380 ((X) == (Y) \
5381 || (REG_P (X) && REG_P (Y) \
5382 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5384 /* Do not substitute into clobbers of regs -- this will never result in
5385 valid RTL. */
5390 {
5391 n_occurrences++;
5393 }
5395 /* If X and FROM are the same register but different modes, they
5396 will not have been seen as equal above. However, the log links code
5397 will make a LOG_LINKS entry for that case. If we do nothing, we
5398 will try to rerecognize our original insn and, when it succeeds,
5399 we will delete the feeding insn, which is incorrect.
5401 So force this insn not to match in this (rare) case. */
5406 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5407 of which may contain things that can be combined. */
5411 /* It is possible to have a subexpression appear twice in the insn.
5412 Suppose that FROM is a register that appears within TO.
5413 Then, after that subexpression has been scanned once by `subst',
5414 the second time it is scanned, TO may be found. If we were
5415 to scan TO here, we would find FROM within it and create a
5416 self-referent rtl structure which is completely wrong. */
5420 /* Parallel asm_operands need special attention because all of the
5421 inputs are shared across the arms. Furthermore, unsharing the
5422 rtl results in recognition failures. Failure to handle this case
5423 specially can result in circular rtl.
5425 Solve this by doing a normal pass across the first entry of the
5426 parallel, and only processing the SET_DESTs of the subsequent
5427 entries. Ug. */
5432 {
5435 /* If this substitution failed, this whole thing fails. */
5443 {
5449 {
5452 /* If this substitution failed, this whole thing fails. */
5458 }
5459 }
5460 }
5461 else
5462 {
5466 /* We don't need to process a SET_DEST that is a register, CC0,
5467 or PC, so set up to skip this common case. All other cases
5468 where we want to suppress replacing something inside a
5469 SET_SRC are handled via the IN_DEST operand. */
5476 /* Trying to simplify the operands of a widening MULT is not likely
5477 to create RTL matching a machine insn. */
5489 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5490 constant. */
5495 {
5497 {
5500 {
5502 {
5505 n_occurrences++;
5506 }
5507 else
5508 {
5510 unique_copy);
5512 /* If this substitution failed, this whole thing
5513 fails. */
5517 }
5520 }
5521 }
5523 {
5524 /* If this is a register being set, ignore it. */
5531 ;
5534 {
5535 /* In general, don't install a subreg involving two
5536 modes not tieable. It can worsen register
5537 allocation, and can even make invalid reload
5538 insns, since the reg inside may need to be copied
5539 from in the outside mode, and that may be invalid
5540 if it is an fp reg copied in integer mode.
5542 We allow two exceptions to this: It is valid if
5543 it is inside another SUBREG and the mode of that
5544 SUBREG and the mode of the inside of TO is
5545 tieable and it is valid if X is a SET that copies
5546 FROM to CC0. */
5554 && (!HAVE_cc0
5569 n_occurrences++;
5570 }
5571 else
5572 /* If we are in a SET_DEST, suppress most cases unless we
5573 have gone inside a MEM, in which case we want to
5574 simplify the address. We assume here that things that
5575 are actually part of the destination have their inner
5576 parts in the first expression. This is true for SUBREG,
5577 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5578 things aside from REG and MEM that should appear in a
5579 SET_DEST. */
5581 (((in_dest
5587 unique_copy);
5589 /* If we found that we will have to reject this combination,
5590 indicate that by returning the CLOBBER ourselves, rather than
5591 an expression containing it. This will speed things up as
5592 well as prevent accidents where two CLOBBERs are considered
5593 to be equal, thus producing an incorrect simplification. */
5599 {
5607 }
5612 {
5614 new_rtx,
5618 }
5619 else
5621 }
5622 }
5623 }
5625 /* Check if we are loading something from the constant pool via float
5626 extension; in this case we would undo compress_float_constant
5627 optimization and degenerate constant load to an immediate value. */
5631 {
5635 }
5637 /* Try to simplify X. If the simplification changed the code, it is likely
5638 that further simplification will help, so loop, but limit the number
5639 of repetitions that will be performed. */
5642 {
5643 /* If X is sufficiently simple, don't bother trying to do anything
5644 with it. */
5653 /* We no longer know the original mode of operand 0 since we
5654 have changed the form of X) */
5656 }
5659 }
5660 \f
5661 /* If X is a commutative operation whose operands are not in the canonical
5662 order, use substitutions to swap them. */
5664 static void
5666 {
5669 {
5673 }
5674 }
5676 /* Simplify X, a piece of RTL. We just operate on the expression at the
5677 outer level; call `subst' to simplify recursively. Return the new
5678 expression.
5680 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5681 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5682 of a condition. */
5684 static rtx
5687 {
5690 scalar_int_mode int_mode;
5691 rtx temp;
5694 /* If this is a commutative operation, put a constant last and a complex
5695 expression first. We don't need to do this for comparisons here. */
5698 /* Try to fold this expression in case we have constants that weren't
5699 present before. */
5702 {
5710 {
5713 {
5717 }
5720 }
5733 }
5736 {
5741 }
5743 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5744 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5745 things. Check for cases where both arms are testing the same
5746 condition.
5748 Don't do anything if all operands are very simple. */
5761 {
5766 /* If everything is a comparison, what we have is highly unlikely
5767 to be simpler, so don't use it. */
5770 /* Similarly, if we end up with one of the expressions the same
5771 as the original, it is certainly not simpler. */
5774 {
5781 /* Simplify the alternative arms; this may collapse the true and
5782 false arms to store-flag values. Be careful to use copy_rtx
5783 here since true_rtx or false_rtx might share RTL with x as a
5784 result of the if_then_else_cond call above. */
5788 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5789 is unlikely to be simpler. */
5792 {
5795 /* Restarting if we generate a store-flag expression will cause
5796 us to loop. Just drop through in this case. */
5798 /* If the result values are STORE_FLAG_VALUE and zero, we can
5799 just make the comparison operation. */
5810 /* Likewise, we can make the negate of a comparison operation
5811 if the result values are - STORE_FLAG_VALUE and zero. */
5819 mode);
5830 mode);
5831 else
5834 mode,
5835 VOIDmode,
5836 cond,
5837 cop1),
5842 }
5843 }
5844 }
5846 /* First see if we can apply the inverse distributive law. */
5849 {
5853 }
5855 /* If CODE is an associative operation not otherwise handled, see if we
5856 can associate some operands. This can win if they are constants or
5857 if they are logically related (i.e. (a & b) & a). */
5863 {
5865 {
5869 rtx inner;
5871 /* Make sure we pass the constant operand if any as the second
5872 one if this is a commutative operation. */
5880 /* For commutative operations, try the other pair if that one
5881 didn't simplify. */
5883 {
5888 }
5892 }
5893 }
5895 /* A little bit of algebraic simplification here. */
5897 {
5899 /* Ensure that our address has any ASHIFTs converted to MULT in case
5900 address-recognizing predicates are called later. */
5909 /* See if this can be moved to simplify_subreg. */
5912 /* Don't call gen_lowpart if the inner mode
5913 is VOIDmode and we cannot simplify it, as SUBREG without
5914 inner mode is invalid. */
5921 {
5922 rtx temp;
5928 /* If op is known to have all lower bits zero, the result is zero. */
5941 }
5943 /* Don't change the mode of the MEM if that would change the meaning
5944 of the address. */
5951 /* Note that we cannot do any narrowing for non-constants since
5952 we might have been counting on using the fact that some bits were
5953 zero. We now do this in the SET. */
5960 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5961 replaced by (lshiftrt X C). This will convert
5962 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5970 /* If X has only a single bit that might be nonzero, say, bit I, convert
5971 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5972 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5973 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5974 or a SUBREG of one since we'd be making the expression more
5975 complex if it was just a register. */
5982 {
5983 rtx temp1 = simplify_shift_const
5989 /* If all we did was surround TEMP with the two shifts, we
5990 haven't improved anything, so don't use it. Otherwise,
5991 we are better off with TEMP1. */
5996 }
6000 /* We can't handle truncation to a partial integer mode here
6001 because we don't know the real bitsize of the partial
6002 integer mode. */
6011 /* We can truncate a constant value and return it. */
6012 {
6013 poly_int64 c;
6016 }
6018 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6019 whose value is a comparison can be replaced with a subreg if
6020 STORE_FLAG_VALUE permits. */
6029 /* (const (const X)) can become (const X). Do it this way rather than
6030 returning the inner CONST since CONST can be shared with a
6031 REG_EQUAL note. */
6037 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6038 can add in an offset. find_split_point will split this address up
6039 again if it doesn't match. */
6046 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6047 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6048 bit-field and can be replaced by either a sign_extend or a
6049 sign_extract. The `and' may be a zero_extend and the two
6050 <c>, -<c> constants may be reversed. */
6067 return simplify_shift_const
6074 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6075 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6076 the bitsize of the mode - 1. This allows simplification of
6077 "a = (b & 8) == 0;" */
6084 return simplify_shift_const
6088 const1_rtx),
6092 /* If we are adding two things that have no bits in common, convert
6093 the addition into an IOR. This will often be further simplified,
6094 for example in cases like ((a & 1) + (a & 2)), which can
6095 become a & 3. */
6100 {
6101 /* Try to simplify the expression further. */
6105 /* If we could, great. If not, do not go ahead with the IOR
6106 replacement, since PLUS appears in many special purpose
6107 address arithmetic instructions. */
6115 }
6117 /* Canonicalize x + x into x << 1. */
6126 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6127 (and <foo> (const_int pow2-1)) */
6138 /* If we have (mult (plus A B) C), apply the distributive law and then
6139 the inverse distributive law to see if things simplify. This
6140 occurs mostly in addresses, often when unrolling loops. */
6143 {
6147 }
6149 /* Try simplify a*(b/c) as (a*b)/c. */
6152 {
6158 }
6162 /* If this is a divide by a power of two, treat it as a shift if
6163 its first operand is a shift. */
6183 /* If the first operand is a condition code, we can't do anything
6184 with it. */
6188 {
6196 /* Simplify our comparison, if possible. */
6199 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6200 if only the low-order bit is possibly nonzero in X (such as when
6201 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6202 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6203 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6204 (plus X 1).
6206 Remove any ZERO_EXTRACT we made when thinking this was a
6207 comparison. It may now be simpler to use, e.g., an AND. If a
6208 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6209 the call to make_compound_operation in the SET case.
6211 Don't apply these optimizations if the caller would
6212 prefer a comparison rather than a value.
6213 E.g., for the condition in an IF_THEN_ELSE most targets need
6214 an explicit comparison. */
6217 ;
6235 {
6239 int_mode);
6240 }
6248 {
6252 const1_rtx);
6253 }
6262 {
6265 }
6267 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6268 those above. */
6270 ;
6287 {
6291 int_mode);
6292 }
6301 {
6305 int_mode);
6306 }
6308 /* If X is 0/1, (eq X 0) is X-1. */
6315 {
6318 }
6320 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6321 one bit that might be nonzero, we can convert (ne x 0) to
6322 (ashift x c) where C puts the bit in the sign bit. Remove any
6323 AND with STORE_FLAG_VALUE when we are done, since we are only
6324 going to test the sign bit. */
6332 {
6338 else
6340 }
6342 /* If the code changed, return a whole new comparison.
6343 We also need to avoid using SUBST in cases where
6344 simplify_comparison has widened a comparison with a CONST_INT,
6345 since in that case the wider CONST_INT may fail the sanity
6346 checks in do_SUBST. */
6353 /* Otherwise, keep this operation, but maybe change its operands.
6354 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6357 }
6367 /* If we are processing SET_DEST, we are done. */
6385 /* If this is a shift by a constant amount, simplify it. */
6393 (HOST_WIDE_INT_1U
6402 }
6405 }
6406 \f
6407 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6409 static rtx
6411 {
6418 rtx temp;
6421 rtx reversed;
6424 /* Simplify storing of the truth value. */
6429 /* Also when the truth value has to be reversed. */
6435 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6436 in it is being compared against certain values. Get the true and false
6437 comparisons and see if that says anything about the value of each arm. */
6443 {
6444 HOST_WIDE_INT nzb;
6450 /* If FALSE_CODE is EQ, swap the codes and arms. */
6453 {
6456 }
6458 scalar_int_mode from_mode;
6460 {
6461 /* If we are comparing against zero and the expression being
6462 tested has only a single bit that might be nonzero, that is
6463 its value when it is not equal to zero. Similarly if it is
6464 known to be -1 or 0. */
6468 {
6471 }
6476 {
6479 }
6480 }
6482 /* Now simplify an arm if we know the value of the register in the
6483 branch and it is used in the arm. Be careful due to the potential
6484 of locally-shared RTL. */
6501 }
6503 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6504 reversed, do so to avoid needing two sets of patterns for
6505 subtract-and-branch insns. Similarly if we have a constant in the true
6506 arm, the false arm is the same as the first operand of the comparison, or
6507 the false arm is more complicated than the true arm. */
6520 {
6529 /* It is possible that the conditional has been simplified out. */
6532 }
6534 /* If the two arms are identical, we don't need the comparison. */
6539 /* Convert a == b ? b : a to "a". */
6551 /* Look for cases where we have (abs x) or (neg (abs X)). */
6554 && comparison_p
6561 {
6567 return
6570 mode);
6573 }
6575 /* Look for MIN or MAX. */
6578 && comparison_p
6583 {
6598 }
6600 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6601 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6602 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6603 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6604 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6605 neither 1 or -1, but it isn't worth checking for. */
6608 && comparison_p
6611 {
6627 /* If an identity-zero op is commutative, check whether there
6628 would be a match if we swapped the operands. */
6649 {
6653 }
6666 {
6670 }
6687 {
6691 }
6704 {
6708 }
6711 {
6721 const_true_rtx));
6729 }
6730 }
6732 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6733 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6734 negation of a single bit, we can convert this operation to a shift. We
6735 can actually do this more generally, but it doesn't seem worth it. */
6747 return
6751 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6752 non-zero bit in A is C1. */
6760 {
6766 }
6769 }
6770 \f
6771 /* Simplify X, a SET expression. Return the new expression. */
6773 static rtx
6775 {
6778 machine_mode mode
6782 scalar_int_mode int_mode;
6784 /* (set (pc) (return)) gets written as (return). */
6788 /* Now that we know for sure which bits of SRC we are using, see if we can
6789 simplify the expression for the object knowing that we only need the
6790 low-order bits. */
6793 {
6796 }
6798 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6799 the comparison result and try to simplify it unless we already have used
6800 undobuf.other_insn. */
6808 {
6817 {
6820 {
6823 }
6824 }
6825 else
6833 {
6837 }
6838 else
6839 {
6844 /* Attempt to simplify CC user. */
6846 {
6850 }
6852 /* Convert X into a no-op move. */
6856 }
6858 /* Simplify our comparison, if possible. */
6861 #ifdef SELECT_CC_MODE
6862 /* If this machine has CC modes other than CCmode, check to see if we
6863 need to use a different CC mode here. */
6872 else
6875 /* If the mode changed, we have to change SET_DEST, the mode in the
6876 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6877 a hard register, just build new versions with the proper mode. If it
6878 is a pseudo, we lose unless it is only time we set the pseudo, in
6879 which case we can safely change its mode. */
6881 {
6883 {
6885 rtx new_dest;
6889 else
6890 {
6893 }
6900 }
6901 }
6904 /* If the code changed, we have to build a new comparison in
6905 undobuf.other_insn. */
6907 {
6916 /* If the only change we made was to change an EQ into an NE or
6917 vice versa, OP0 has only one bit that might be nonzero, and OP1
6918 is zero, check if changing the user of the condition code will
6919 produce a valid insn. If it won't, we can keep the original code
6920 in that insn by surrounding our operation with an XOR. */
6927 {
6932 {
6939 }
6940 }
6941 }
6946 /* Don't generate a compare of a CC with 0, just use that CC. */
6948 {
6951 }
6952 /* Otherwise, if we didn't previously have the same COMPARE we
6953 want, create it from scratch. */
6956 {
6959 }
6960 }
6961 else
6962 {
6963 /* Get SET_SRC in a form where we have placed back any
6964 compound expressions. Then do the checks below. */
6967 }
6969 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6970 and X being a REG or (subreg (reg)), we may be able to convert this to
6971 (set (subreg:m2 x) (op)).
6973 We can always do this if M1 is narrower than M2 because that means that
6974 we only care about the low bits of the result.
6976 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6977 perform a narrower operation than requested since the high-order bits will
6978 be undefined. On machine where it is defined, this transformation is safe
6979 as long as M1 and M2 have the same number of words. */
6983 && (known_equal_after_align_up
6986 UNITS_PER_WORD))
6995 {
6998 dest));
7002 }
7004 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7005 in SRC. */
7009 {
7013 /* Here we make sure that we don't have a sign bit on. */
7016 {
7019 }
7020 }
7022 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7023 would require a paradoxical subreg. Replace the subreg with a
7024 zero_extend to avoid the reload that would otherwise be required.
7025 Don't do this unless we have a scalar integer mode, otherwise the
7026 transformation is incorrect. */
7033 {
7038 }
7040 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7041 are comparing an item known to be 0 or -1 against 0, use a logical
7042 operation instead. Check for one of the arms being an IOR of the other
7043 arm with some value. We compute three terms to be IOR'ed together. In
7044 practice, at most two will be nonzero. Then we do the IOR's. */
7052 && (!HAVE_conditional_move
7057 {
7082 int_mode),
7083 false_rtx);
7089 term3));
7092 }
7094 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7095 whole thing fail. */
7100 else
7101 /* Convert this into a field assignment operation, if possible. */
7103 }
7104 \f
7105 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7106 result. */
7108 static rtx
7110 {
7113 scalar_int_mode mode;
7116 {
7118 /* We can call simplify_and_const_int only if we don't lose
7119 any (sign) bits when converting INTVAL (op1) to
7120 "unsigned HOST_WIDE_INT". */
7125 {
7132 }
7134 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7135 apply the distributive law and then the inverse distributive
7136 law to see if things simplify. */
7138 {
7142 }
7144 {
7148 }
7152 /* If we have (ior (and A B) C), apply the distributive law and then
7153 the inverse distributive law to see if things simplify. */
7156 {
7160 }
7163 {
7167 }
7172 }
7175 }
7176 \f
7177 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7178 operations" because they can be replaced with two more basic operations.
7179 ZERO_EXTEND is also considered "compound" because it can be replaced with
7180 an AND operation, which is simpler, though only one operation.
7182 The function expand_compound_operation is called with an rtx expression
7183 and will convert it to the appropriate shifts and AND operations,
7184 simplifying at each stage.
7186 The function make_compound_operation is called to convert an expression
7187 consisting of shifts and ANDs into the equivalent compound expression.
7188 It is the inverse of this function, loosely speaking. */
7190 static rtx
7192 {
7196 rtx tem;
7197 scalar_int_mode inner_mode;
7200 {
7203 /* FALLTHRU */
7205 /* We can't necessarily use a const_int for a multiword mode;
7206 it depends on implicitly extending the value.
7207 Since we don't know the right way to extend it,
7208 we can't tell whether the implicit way is right.
7210 Even for a mode that is no wider than a const_int,
7211 we can't win, because we need to sign extend one of its bits through
7212 the rest of it, and we don't know which bit. */
7216 /* Reject modes that aren't scalar integers because turning vector
7217 or complex modes into shifts causes problems. */
7221 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7222 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7223 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7224 reloaded. If not for that, MEM's would very rarely be safe.
7226 Reject modes bigger than a word, because we might not be able
7227 to reference a two-register group starting with an arbitrary register
7228 (and currently gen_lowpart might crash for a SUBREG). */
7234 /* If the inner object has VOIDmode (the only way this can happen
7235 is if it is an ASM_OPERANDS), we can't do anything since we don't
7236 know how much masking to do. */
7245 /* fall through */
7248 /* If the operand is a CLOBBER, just return it. */
7256 /* Reject modes that aren't scalar integers because turning vector
7257 or complex modes into shifts causes problems. */
7264 /* This should stay within the object being extracted, fail otherwise. */
7275 }
7277 /* We've rejected non-scalar operations by now. */
7280 /* Convert sign extension to zero extension, if we know that the high
7281 bit is not set, as this is easier to optimize. It will be converted
7282 back to cheaper alternative in make_extraction. */
7288 {
7292 /* Make sure this is a profitable operation. */
7299 else
7301 }
7303 /* We can optimize some special cases of ZERO_EXTEND. */
7305 {
7306 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7307 know that the last value didn't have any inappropriate bits
7308 set. */
7316 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7325 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7326 is a comparison and STORE_FLAG_VALUE permits. This is like
7327 the first case, but it works even when MODE is larger
7328 than HOST_WIDE_INT. */
7336 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7345 }
7347 /* If we reach here, we want to return a pair of shifts. The inner
7348 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7349 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7350 logical depending on the value of UNSIGNEDP.
7352 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7353 converted into an AND of a shift.
7355 We must check for the case where the left shift would have a negative
7356 count. This can happen in a case like (x >> 31) & 255 on machines
7357 that can't shift by a constant. On those machines, we would first
7358 combine the shift with the AND to produce a variable-position
7359 extraction. Then the constant of 31 would be substituted in
7360 to produce such a position. */
7364 {
7372 }
7377 pos),
7379 else
7380 /* Any other cases we can't handle. */
7383 /* If we couldn't do this for some reason, return the original
7384 expression. */
7389 }
7390 \f
7391 /* X is a SET which contains an assignment of one object into
7392 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7393 or certain SUBREGS). If possible, convert it into a series of
7394 logical operations.
7396 We half-heartedly support variable positions, but do not at all
7397 support variable lengths. */
7399 static const_rtx
7401 {
7402 rtx inner;
7406 scalar_int_mode compute_mode;
7408 /* Loop until we find something we can't simplify. */
7410 {
7413 {
7419 MAX_MODE_INT);
7420 }
7423 {
7431 /* A constant position should stay within the width of INNER. */
7436 {
7442 /* If position is ADJUST - X, new position is X. */
7444 else
7448 pos);
7449 }
7450 }
7452 /* If the destination is a subreg that overwrites the whole of the inner
7453 register, we can move the subreg to the source. */
7455 /* We need SUBREGs to compute nonzero_bits properly. */
7456 && nonzero_sign_valid
7458 {
7460 gen_lowpart
7464 }
7465 else
7471 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7473 {
7474 /* Don't do anything for vector or complex integral types. */
7478 /* Try to find an integral mode to pun with. */
7484 }
7486 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7490 /* Don't try to compute in too wide unsupported modes. */
7494 /* Now compute the equivalent expression. Make a copy of INNER
7495 for the SET_DEST in case it is a MEM into which we will substitute;
7496 we don't want shared RTL in that case. */
7498 compute_mode);
7502 compute_mode,
7504 compute_mode),
7505 inner);
7510 mask),
7511 pos);
7516 }
7519 }
7520 \f
7521 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7522 it is an RTX that represents the (variable) starting position; otherwise,
7523 POS is the (constant) starting bit position. Both are counted from the LSB.
7525 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7527 IN_DEST is nonzero if this is a reference in the destination of a SET.
7528 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7529 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7530 be used.
7532 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7533 ZERO_EXTRACT should be built even for bits starting at bit 0.
7535 MODE is the desired mode of the result (if IN_DEST == 0).
7537 The result is an RTX for the extraction or NULL_RTX if the target
7538 can't handle it. */
7540 static rtx
7544 {
7545 /* This mode describes the size of the storage area
7546 to fetch the overall value from. Within that, we
7547 ignore the POS lowest bits, etc. */
7549 machine_mode inner_mode;
7550 scalar_int_mode wanted_inner_mode;
7556 HOST_WIDE_INT orig_pos;
7564 /* If trying or potentionally trying to extract
7565 bits outside of is_mode, don't look through
7566 non-paradoxical SUBREGs. See PR82192. */
7569 {
7570 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7571 consider just the QI as the memory to extract from.
7572 The subreg adds or removes high bits; its mode is
7573 irrelevant to the meaning of this extraction,
7574 since POS and LEN count from the lsb. */
7578 }
7583 {
7584 /* We're extracting the least significant bits of an rtx
7585 (ashift X (const_int C)), where LEN > C. Extract the
7586 least significant (LEN - C) bits of X, giving an rtx
7587 whose mode is MODE, then shift it left C times. */
7593 }
7595 /* If trying or potentionally trying to extract
7596 bits outside of is_mode, don't look through
7597 TRUNCATE. See PR82192. */
7604 /* See if this can be done without an extraction. We never can if the
7605 width of the field is not the same as that of some integer mode. For
7606 registers, we can only avoid the extraction if the position is at the
7607 low-order bit and this is either not in the destination or we have the
7608 appropriate STRICT_LOW_PART operation available.
7610 For MEM, we can avoid an extract if the field starts on an appropriate
7611 boundary and we can change the mode of the memory reference. */
7613 scalar_int_mode tmode;
7622 && (! in_dest
7626 && (pos
7629 /* We can't do this if we are widening INNER_MODE (it
7630 may not be aligned, for one thing). */
7636 {
7637 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7638 field. If the original and current mode are the same, we need not
7639 adjust the offset. Otherwise, we do if bytes big endian.
7641 If INNER is not a MEM, get a piece consisting of just the field
7642 of interest (in this case POS % BITS_PER_WORD must be 0). */
7645 {
7646 poly_int64 offset;
7648 /* POS counts from lsb, but make OFFSET count in memory order. */
7652 else
7656 }
7658 {
7660 {
7661 /* We can't call gen_lowpart in a DEST since we
7662 always want a SUBREG (see below) and it would sometimes
7663 return a new hard register. */
7665 {
7666 poly_uint64 offset
7669 /* Avoid creating invalid subregs, for example when
7670 simplifying (x>>32)&255. */
7675 }
7676 else
7678 }
7679 else
7681 }
7682 else
7684 len >= HOST_BITS_PER_WIDE_INT
7685 ? HOST_WIDE_INT_M1U
7688 /* If this extraction is going into the destination of a SET,
7689 make a STRICT_LOW_PART unless we made a MEM. */
7704 /* If we know that no extraneous bits are set, and that the high
7705 bit is not set, convert the extraction to the cheaper of
7706 sign and zero extension, that are equivalent in these cases. */
7712 {
7716 /* Prefer ZERO_EXTENSION, since it gives more information to
7717 backends. */
7722 }
7724 /* Otherwise, sign- or zero-extend unless we already are in the
7725 proper mode. */
7729 }
7731 /* Unless this is a COMPARE or we have a funny memory reference,
7732 don't do anything with zero-extending field extracts starting at
7733 the low-order bit since they are simple AND operations. */
7738 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7739 if the position is not a constant and the length is not 1. In all
7740 other cases, we would only be going outside our object in cases when
7741 an original shift would have been undefined. */
7750 /* If INNER is not from memory, we want it to have the mode of a register
7751 extraction pattern's structure operand, or word_mode if there is no
7752 such pattern. The same applies to extraction_mode and pos_mode
7753 and their respective operands.
7755 For memory, assume that the desired extraction_mode and pos_mode
7756 are the same as for a register operation, since at present we don't
7757 have named patterns for aligned memory structures. */
7762 {
7766 }
7768 /* Never narrow an object, since that might not be safe. */
7776 else
7777 {
7778 /* Be careful not to go beyond the extracted object and maintain the
7779 natural alignment of the memory. */
7784 }
7789 {
7790 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7791 BITS_BIG_ENDIAN style. If position is constant, compute new
7792 position. Otherwise, build subtraction.
7793 Note that POS is relative to the mode of the original argument.
7794 If it's a MEM we need to recompute POS relative to that.
7795 However, if we're extracting from (or inserting into) a register,
7796 we want to recompute POS relative to wanted_inner_mode. */
7805 else
7806 pos_rtx
7809 pos_rtx);
7810 /* POS may be less than 0 now, but we check for that below.
7811 Note that it can only be less than 0 if !MEM_P (inner). */
7812 }
7814 /* If INNER has a wider mode, and this is a constant extraction, try to
7815 make it smaller and adjust the byte to point to the byte containing
7816 the value. */
7819 && ! pos_rtx
7824 {
7827 /* The computations below will be correct if the machine is big
7828 endian in both bits and bytes or little endian in bits and bytes.
7829 If it is mixed, we must adjust. */
7831 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7832 adjust OFFSET to compensate. */
7837 /* We can now move to the desired byte. */
7848 }
7850 /* If INNER is not memory, get it into the proper mode. If we are changing
7851 its mode, POS must be a constant and smaller than the size of the new
7852 mode. */
7854 {
7855 /* On the LHS, don't create paradoxical subregs implicitely truncating
7856 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7859 wanted_inner_mode))
7871 pos_rtx
7873 ? HOST_WIDE_INT_M1U
7877 }
7879 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7880 have to zero extend. Otherwise, we can just use a SUBREG.
7882 We dealt with constant rtxes earlier, so pos_rtx cannot
7883 have VOIDmode at this point. */
7887 {
7891 /* If we know that no extraneous bits are set, and that the high
7892 bit is not set, convert extraction to cheaper one - either
7893 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7894 cases. */
7902 {
7906 /* Prefer ZERO_EXTENSION, since it gives more information to
7907 backends. */
7911 }
7913 }
7915 /* Make POS_RTX unless we already have it and it is correct. If we don't
7916 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7917 be a CONST_INT. */
7924 /* Make the required operation. See if we can use existing rtx. */
7931 }
7932 \f
7933 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7934 can be commuted with any other operations in X. Return X without
7935 that shift if so. */
7937 static rtx
7939 {
7941 rtx tem;
7944 {
7946 /* This is the shift itself. If it is wide enough, we will return
7947 either the value being shifted if the shift count is equal to
7948 COUNT or a shift for the difference. */
7962 /* If we can safely shift this constant and we find the inner shift,
7963 make a new operation. */
7968 {
7972 }
7977 }
7980 }
7981 \f
7982 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7983 level of the expression and MODE is its mode. IN_CODE is as for
7984 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7985 that should be used when recursing on operands of *X_PTR.
7987 There are two possible actions:
7989 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7990 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7992 - Return a new rtx, which the caller returns directly. */
7994 static rtx
7998 {
8006 rtx tem;
8007 scalar_int_mode inner_mode;
8011 {
8014 }
8016 /* Process depending on the code of this operation. If NEW is set
8017 nonzero, it will be returned. */
8020 {
8022 /* Convert shifts by constants into multiplications if inside
8023 an address. */
8027 {
8033 {
8036 }
8039 }
8048 {
8052 }
8055 {
8059 mode));
8061 }
8062 else
8063 {
8066 }
8076 {
8080 }
8083 {
8087 mode));
8089 }
8090 else
8091 {
8095 }
8098 /* If the second operand is not a constant, we can't do anything
8099 with it. */
8103 /* If the constant is a power of two minus one and the first operand
8104 is a logical right shift, make an extraction. */
8107 {
8111 }
8113 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8120 {
8127 /* If we narrowed the mode when dropping the subreg, then we lose. */
8131 /* If that didn't give anything, see if the AND simplifies on
8132 its own. */
8134 {
8138 }
8139 }
8140 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8146 {
8147 /* Apply the distributive law, and then try to make extractions. */
8154 }
8156 /* If we are have (and (rotate X C) M) and C is larger than the number
8157 of bits in M, this is an extraction. */
8163 {
8169 }
8171 /* On machines without logical shifts, if the operand of the AND is
8172 a logical shift and our mask turns off all the propagated sign
8173 bits, we can replace the logical shift with an arithmetic shift. */
8181 {
8191 next_code),
8193 }
8195 /* If the constant is one less than a power of two, this might be
8196 representable by an extraction even if no shift is present.
8197 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8198 we are in a COMPARE. */
8202 next_code),
8205 /* If we are in a comparison and this is an AND with a power of two,
8206 convert this into the appropriate bit extract. */
8212 next_code),
8215 /* If the one operand is a paradoxical subreg of a register or memory and
8216 the constant (limited to the smaller mode) has only zero bits where
8217 the sub expression has known zero bits, this can be expressed as
8218 a zero_extend. */
8220 {
8221 rtx sub;
8229 {
8233 /* original AND constant with all the known zero bits set */
8236 {
8240 }
8241 }
8242 }
8247 /* If the sign bit is known to be zero, replace this with an
8248 arithmetic shift. */
8253 {
8256 next_code),
8259 }
8261 /* fall through */
8267 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8268 this is a SIGN_EXTRACT. */
8275 {
8282 }
8284 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8285 If so, try to merge the shifts into a SIGN_EXTEND. We could
8286 also do this for some cases of SIGN_EXTRACT, but it doesn't
8287 seem worth the effort; the case checked for occurs on Alpha. */
8298 next_code),
8305 /* Call ourselves recursively on the inner expression. If we are
8306 narrowing the object and it has a different RTL code from
8307 what it originally did, do this SUBREG as a force_to_mode. */
8308 {
8312 /* If the SUBREG is masking of a logical right shift,
8313 make an extraction. */
8320 {
8329 }
8331 /* If in_code is COMPARE, it isn't always safe to pass it through
8332 to the recursive make_compound_operation call. */
8336 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8337 is (const_int 0), rather than
8338 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8339 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8340 for non-equality comparisons against 0 is not equivalent
8341 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8351 simplified
8359 {
8360 rtx newer
8363 /* If we have something other than a SUBREG, we might have
8364 done an expansion, so rerun ourselves. */
8368 /* force_to_mode can expand compounds. If it just re-expanded
8369 the compound, use gen_lowpart to convert to the desired
8370 mode. */
8372 /* Likewise if it re-expanded the compound only partially.
8373 This happens for SUBREG of ZERO_EXTRACT if they extract
8374 the same number of bits. */
8383 }
8387 }
8392 }
8398 }
8400 /* Look at the expression rooted at X. Look for expressions
8401 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8402 Form these expressions.
8404 Return the new rtx, usually just X.
8406 Also, for machines like the VAX that don't have logical shift insns,
8407 try to convert logical to arithmetic shift operations in cases where
8408 they are equivalent. This undoes the canonicalizations to logical
8409 shifts done elsewhere.
8411 We try, as much as possible, to re-use rtl expressions to save memory.
8413 IN_CODE says what kind of expression we are processing. Normally, it is
8414 SET. In a memory address it is MEM. When processing the arguments of
8415 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8416 precisely it is an equality comparison against zero. */
8418 rtx
8420 {
8427 /* Select the code to be used in recursive calls. Once we are inside an
8428 address, we stay there. If we have a comparison, set to COMPARE,
8429 but once inside, go back to our default of SET. */
8436 scalar_int_mode mode;
8438 {
8444 }
8446 /* Now recursively process each operand of this operation. We need to
8447 handle ZERO_EXTEND specially so that we don't lose track of the
8448 inner mode. */
8450 {
8458 }
8463 {
8466 }
8469 {
8472 }
8476 }
8477 \f
8478 /* Given M see if it is a value that would select a field of bits
8479 within an item, but not the entire word. Return -1 if not.
8480 Otherwise, return the starting position of the field, where 0 is the
8481 low-order bit.
8483 *PLEN is set to the length of the field. */
8485 static int
8487 {
8488 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8493 /* Now shift off the low-order zero bits and see if we have a
8494 power of two minus 1. */
8502 }
8503 \f
8504 /* If X refers to a register that equals REG in value, replace these
8505 references with REG. */
8506 static rtx
8508 {
8516 {
8549 /* FALLTHRU */
8553 {
8557 else
8559 }
8561 /* fall through */
8568 {
8571 {
8573 {
8576 }
8578 }
8579 }
8581 {
8584 {
8587 {
8589 {
8592 }
8594 }
8595 }
8596 }
8599 }
8602 }
8604 /* Return X converted to MODE. If the value is already truncated to
8605 MODE we can just return a subreg even though in the general case we
8606 would need an explicit truncation. */
8608 static rtx
8610 {
8615 {
8616 /* Bit-cast X into an integer mode. */
8621 }
8624 }
8626 /* See if X can be simplified knowing that we will only refer to it in
8627 MODE and will only refer to those bits that are nonzero in MASK.
8628 If other bits are being computed or if masking operations are done
8629 that select a superset of the bits in MASK, they can sometimes be
8630 ignored.
8632 Return a possibly simplified expression, but always convert X to
8633 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8635 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8636 are all off in X. This is used when X will be complemented, by either
8637 NOT, NEG, or XOR. */
8639 static rtx
8642 {
8645 machine_mode op_mode;
8648 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8649 code below will do the wrong thing since the mode of such an
8650 expression is VOIDmode.
8652 Also do nothing if X is a CLOBBER; this can happen if X was
8653 the return value from a call to gen_lowpart. */
8657 /* We want to perform the operation in its present mode unless we know
8658 that the operation is valid in MODE, in which case we do the operation
8659 in MODE. */
8664 /* It is not valid to do a right-shift in a narrower mode
8665 than the one it came in with. */
8670 /* Truncate MASK to fit OP_MODE. */
8674 /* Determine what bits of X are guaranteed to be (non)zero. */
8677 /* If none of the bits in X are needed, return a zero. */
8681 /* If X is a CONST_INT, return a new one. Do this here since the
8682 test below will fail. */
8684 {
8687 else
8688 {
8691 }
8692 }
8694 /* If X is narrower than MODE and we want all the bits in X's mode, just
8695 get X in the proper mode. */
8700 /* We can ignore the effect of a SUBREG if it narrows the mode or
8701 if the constant masks to zero all the bits the mode doesn't have. */
8705 || (mask
8713 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8714 integer too. */
8720 }
8722 /* Subroutine of force_to_mode that handles cases in which both X and
8723 the result are scalar integers. MODE is the mode of the result,
8724 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8725 is preferred for simplified versions of X. The other arguments
8726 are as for force_to_mode. */
8728 static rtx
8732 {
8737 poly_int64 const_op0;
8739 /* When we have an arithmetic operation, or a shift whose count we
8740 do not know, we need to assume that all bits up to the highest-order
8741 bit in MASK will be needed. This is how we form such a mask. */
8744 else
8749 {
8751 /* If X is a (clobber (const_int)), return it since we know we are
8752 generating something that won't match. */
8765 /* Similarly for a truncate. */
8769 /* If this is an AND with a constant, convert it into an AND
8770 whose constant is the AND of that constant with MASK. If it
8771 remains an AND of MASK, delete it since it is redundant. */
8774 {
8779 /* If X is still an AND, see if it is an AND with a mask that
8780 is just some low-order bits. If so, and it is MASK, we don't
8781 need it. */
8787 /* If it remains an AND, try making another AND with the bits
8788 in the mode mask that aren't in MASK turned on. If the
8789 constant in the AND is wide enough, this might make a
8790 cheaper constant. */
8795 {
8796 unsigned HOST_WIDE_INT cval
8798 rtx y;
8805 }
8808 }
8813 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8814 low-order bits (as in an alignment operation) and FOO is already
8815 aligned to that boundary, mask C1 to that boundary as well.
8816 This may eliminate that PLUS and, later, the AND. */
8818 {
8822 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8823 number, sign extend it. */
8836 }
8838 /* fall through */
8841 /* Substituting into the operands of a widening MULT is not likely to
8842 create RTL matching a machine insn. */
8852 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8853 most significant bit in MASK since carries from those bits will
8854 affect the bits we are interested in. */
8859 /* If X is (minus C Y) where C's least set bit is larger than any bit
8860 in the mask, then we may replace with (neg Y). */
8863 {
8866 }
8868 /* Similarly, if C contains every bit in the fuller_mask, then we may
8869 replace with (not Y). */
8872 {
8875 }
8882 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8883 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8884 operation which may be a bitfield extraction. Ensure that the
8885 constant we form is not wider than the mode of X. */
8897 {
8900 xmode);
8906 }
8908 binop:
8909 /* For most binary operations, just propagate into the operation and
8910 change the mode if we have an operation of that mode. */
8915 /* If we ended up truncating both operands, truncate the result of the
8916 operation instead. */
8919 {
8922 }
8928 {
8931 }
8935 /* For left shifts, do the same, but just for the first operand.
8936 However, we cannot do anything with shifts where we cannot
8937 guarantee that the counts are smaller than the size of the mode
8938 because such a count will have a different meaning in a
8939 wider mode. */
8949 /* If the shift count is a constant and we can do arithmetic in
8950 the mode of the shift, refine which bits we need. Otherwise, use the
8951 conservative form of the mask. */
8957 else
8965 {
8968 }
8972 /* Here we can only do something if the shift count is a constant,
8973 this shift constant is valid for the host, and we can do arithmetic
8974 in OP_MODE. */
8980 {
8984 /* Select the mask of the bits we need for the shift operand. */
8987 /* We can only change the mode of the shift if we can do arithmetic
8988 in the mode of the shift and INNER_MASK is no wider than the
8989 width of X's mode. */
8996 {
8999 }
9000 }
9002 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9003 shift and AND produces only copies of the sign bit (C2 is one less
9004 than a power of two), we can do this with just a shift. */
9008 /* The shift puts one of the sign bit copies in the least significant
9009 bit. */
9014 /* Number of bits left after the shift must be more than the mask
9015 needs. */
9018 /* Must be more sign bit copies than the mask needs. */
9021 {
9025 }
9029 /* If we are just looking for the sign bit, we don't need this shift at
9030 all, even if it has a variable count. */
9034 /* If this is a shift by a constant, get a mask that contains those bits
9035 that are not copies of the sign bit. We then have two cases: If
9036 MASK only includes those bits, this can be a logical shift, which may
9037 allow simplifications. If MASK is a single-bit field not within
9038 those bits, we are requesting a copy of the sign bit and hence can
9039 shift the sign bit to the appropriate location. */
9043 {
9047 /* If the considered data is wider than HOST_WIDE_INT, we can't
9048 represent a mask for all its bits in a single scalar.
9049 But we only care about the lower bits, so calculate these. */
9052 {
9055 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9056 is the number of bits a full-width mask would have set.
9057 We need only shift if these are fewer than nonzero can
9058 hold. If not, we must keep all bits set in nonzero. */
9063 + HOST_BITS_PER_WIDE_INT
9065 }
9066 else
9067 {
9070 }
9073 {
9078 }
9081 {
9082 x = simplify_shift_const
9088 }
9089 }
9091 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9092 even if the shift count isn't a constant. */
9096 shiftrt:
9098 /* If this is a zero- or sign-extension operation that just affects bits
9099 we don't care about, remove it. Be sure the call above returned
9100 something that is still a shift. */
9110 next_select);
9116 /* If the shift count is constant and we can do computations
9117 in the mode of X, compute where the bits we care about are.
9118 Otherwise, we can't do anything. Don't change the mode of
9119 the shift or propagate MODE into the shift, though. */
9122 {
9131 }
9135 /* If we just want the low-order bit, the NEG isn't needed since it
9136 won't change the low-order bit. */
9140 /* We need any bits less significant than the most significant bit in
9141 MASK since carries from those bits will affect the bits we are
9142 interested in. */
9147 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9148 same as the XOR case above. Ensure that the constant we form is not
9149 wider than the mode of X. */
9157 {
9164 }
9166 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9167 use the full mask inside the NOT. */
9170 unop:
9173 next_select));
9175 {
9178 }
9182 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9183 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9184 which is equal to STORE_FLAG_VALUE. */
9196 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9197 written in a narrower mode. We play it safe and do not do so. */
9213 }
9215 /* Ensure we return a value of the proper mode. */
9217 }
9218 \f
9219 /* Return nonzero if X is an expression that has one of two values depending on
9220 whether some other value is zero or nonzero. In that case, we return the
9221 value that is being tested, *PTRUE is set to the value if the rtx being
9222 returned has a nonzero value, and *PFALSE is set to the other alternative.
9224 If we return zero, we set *PTRUE and *PFALSE to X. */
9226 static rtx
9228 {
9233 scalar_int_mode int_mode;
9235 /* If we are comparing a value against zero, we are done. */
9238 {
9242 }
9244 /* If this is a unary operation whose operand has one of two values, apply
9245 our opcode to compute those values. */
9248 {
9253 }
9255 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9256 make can't possibly match and would suppress other optimizations. */
9258 ;
9260 /* If this is a binary operation, see if either side has only one of two
9261 values. If either one does or if both do and they are conditional on
9262 the same value, compute the new true and false values. */
9264 {
9272 {
9273 /* Try to enable a simplification by undoing work done by
9274 if_then_else_cond if it converted a REG into something more
9275 complex. */
9277 {
9280 }
9281 else
9282 {
9285 }
9286 }
9290 {
9291 /* If if_then_else_cond returned zero, then true/false are the
9292 same rtl. We must copy one of them to prevent invalid rtl
9293 sharing. */
9300 {
9305 }
9306 else
9307 {
9310 }
9313 }
9315 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9316 operands is zero when the other is nonzero, and vice-versa,
9317 and STORE_FLAG_VALUE is 1 or -1. */
9323 {
9340 {
9347 const_true_rtx);
9349 }
9350 }
9352 /* Similarly for MULT, AND and UMIN, except that for these the result
9353 is always zero. */
9357 {
9371 {
9374 }
9375 }
9376 }
9379 {
9380 /* If we have IF_THEN_ELSE already, extract the condition and
9381 canonicalize it if it is NE or EQ. */
9387 {
9390 }
9391 else
9393 }
9395 /* If X is a SUBREG, we can narrow both the true and false values
9396 if the inner expression, if there is a condition. */
9400 {
9406 {
9410 }
9411 }
9413 /* If X is a constant, this isn't special and will cause confusions
9414 if we treat it as such. Likewise if it is equivalent to a constant. */
9417 ;
9419 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9420 will be least confusing to the rest of the compiler. */
9422 {
9425 }
9427 /* If X is known to be either 0 or -1, those are the true and
9428 false values when testing X. */
9433 {
9436 }
9438 /* Likewise for 0 or a single bit. */
9441 {
9444 }
9446 /* Otherwise fail; show no condition with true and false values the same. */
9449 }
9450 \f
9451 /* Return the value of expression X given the fact that condition COND
9452 is known to be true when applied to REG as its first operand and VAL
9453 as its second. X is known to not be shared and so can be modified in
9454 place.
9456 We only handle the simplest cases, and specifically those cases that
9457 arise with IF_THEN_ELSE expressions. */
9459 static rtx
9461 {
9469 /* If either operand of the condition is a floating point value,
9470 then we have to avoid collapsing an EQ comparison. */
9480 /* If X is (abs REG) and we know something about REG's relationship
9481 with zero, we may be able to simplify this. */
9485 {
9494 }
9496 /* The only other cases we handle are MIN, MAX, and comparisons if the
9497 operands are the same as REG and VAL. */
9500 {
9502 {
9505 }
9508 {
9510 {
9518 else
9520 }
9523 {
9526 /* Do not reverse the condition when it is NE or EQ.
9527 This is because we cannot conclude anything about
9528 the value of 'SMAX (x, y)' when x is not equal to y,
9529 but we can when x equals y. */
9535 {
9546 }
9547 }
9548 }
9549 }
9551 {
9556 {
9557 /* We must simplify subreg here, before we lose track of the
9558 original inner_mode. */
9563 else
9565 }
9568 }
9569 /* We don't have to handle SIGN_EXTEND here, because even in the
9570 case of replacing something with a modeless CONST_INT, a
9571 CONST_INT is already (supposed to be) a valid sign extension for
9572 its narrower mode, which implies it's already properly
9573 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9574 story is different. */
9576 {
9581 {
9582 /* We must simplify the zero_extend here, before we lose
9583 track of the original inner_mode. */
9588 else
9590 }
9593 }
9597 {
9604 }
9607 }
9608 \f
9609 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9610 assignment as a field assignment. */
9612 static int
9614 {
9616 {
9624 }
9632 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9633 Note that all SUBREGs of MEM are paradoxical; otherwise they
9634 would have been rewritten. */
9647 /* We used to see if get_last_value of X and Y were the same but that's
9648 not correct. In one direction, we'll cause the assignment to have
9649 the wrong destination and in the case, we'll import a register into this
9650 insn that might have already have been dead. So fail if none of the
9651 above cases are true. */
9653 }
9654 \f
9655 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9656 Return that assignment if so.
9658 We only handle the most common cases. */
9660 static rtx
9662 {
9665 rtx assign;
9667 HOST_WIDE_INT c1;
9668 HOST_WIDE_INT pos;
9670 rtx other;
9672 /* All the rules in this function are specific to scalar integers. */
9673 scalar_int_mode mode;
9677 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9678 a clear of a one-bit field. We will have changed it to
9679 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9680 for a SUBREG. */
9686 {
9692 }
9701 {
9708 }
9710 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9711 one-bit field. */
9715 {
9721 }
9723 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9724 SRC is an AND with all bits of that field set, then we can discard
9725 the AND. */
9730 {
9737 else
9740 /* Complete overlap. We can remove the source AND. */
9744 /* Partial overlap. We can reduce the source AND. */
9746 {
9750 }
9751 }
9753 /* The other case we handle is assignments into a constant-position
9754 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9755 a mask that has all one bits except for a group of zero bits and
9756 OTHER is known to have zeros where C1 has ones, this is such an
9757 assignment. Compute the position and length from C1. Shift OTHER
9758 to the appropriate position, force it to the required mode, and
9759 make the extraction. Check for the AND in both operands. */
9761 /* One or more SUBREGs might obscure the constant-position field
9762 assignment. The first one we are likely to encounter is an outer
9763 narrowing SUBREG, which we can just strip for the purposes of
9764 identifying the constant-field assignment. */
9781 /* The second SUBREG that might get in the way is a paradoxical
9782 SUBREG around the first operand of the AND. We want to
9783 pretend the operand is as wide as the destination here. We
9784 do this by adjusting the MEM to wider mode for the sole
9785 purpose of the call to rtx_equal_for_field_assignment_p. Also
9786 note this trick only works for MEMs. */
9798 /* The second SUBREG that might get in the way is a paradoxical
9799 SUBREG around the first operand of the AND. We want to
9800 pretend the operand is as wide as the destination here. We
9801 do this by adjusting the MEM to wider mode for the sole
9802 purpose of the call to rtx_equal_for_field_assignment_p. Also
9803 note this trick only works for MEMs. */
9811 else
9825 /* The mode to use for the source is the mode of the assignment, or of
9826 what is inside a possible STRICT_LOW_PART. */
9830 /* Shift OTHER right POS places and make it the source, restricting it
9831 to the proper length and mode. */
9835 dest);
9837 len >= HOST_BITS_PER_WIDE_INT
9838 ? HOST_WIDE_INT_M1U
9842 /* If SRC is masked by an AND that does not make a difference in
9843 the value being stored, strip it. */
9854 }
9855 \f
9856 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9857 if so. */
9859 static rtx
9861 {
9865 rtx tem;
9867 /* Distributivity is not true for floating point as it can change the
9868 value. So we don't do it unless -funsafe-math-optimizations. */
9873 /* The outer operation can only be one of the following: */
9881 /* If either operand is a primitive we can't do anything, so get out
9882 fast. */
9892 /* See if the inner and outer operations distribute. */
9894 {
9899 /* These all distribute except over PLUS. */
9910 /* This is also a multiply, so it distributes over everything. */
9913 /* This used to handle SUBREG, but this turned out to be counter-
9914 productive, since (subreg (op ...)) usually is not handled by
9915 insn patterns, and this "optimization" therefore transformed
9916 recognizable patterns into unrecognizable ones. Therefore the
9917 SUBREG case was removed from here.
9919 It is possible that distributing SUBREG over arithmetic operations
9920 leads to an intermediate result than can then be optimized further,
9921 e.g. by moving the outer SUBREG to the other side of a SET as done
9922 in simplify_set. This seems to have been the original intent of
9923 handling SUBREGs here.
9925 However, with current GCC this does not appear to actually happen,
9926 at least on major platforms. If some case is found where removing
9927 the SUBREG case here prevents follow-on optimizations, distributing
9928 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9932 }
9934 /* Set LHS and RHS to the inner operands (A and B in the example
9935 above) and set OTHER to the common operand (C in the example).
9936 There is only one way to do this unless the inner operation is
9937 commutative. */
9949 else
9952 /* Form the new inner operation, seeing if it simplifies first. */
9955 /* There is one exception to the general way of distributing:
9956 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9958 {
9961 }
9963 /* We may be able to continuing distributing the result, so call
9964 ourselves recursively on the inner operation before forming the
9965 outer operation, which we return. */
9968 }
9970 /* See if X is of the form (* (+ A B) C), and if so convert to
9971 (+ (* A C) (* B C)) and try to simplify.
9973 Most of the time, this results in no change. However, if some of
9974 the operands are the same or inverses of each other, simplifications
9975 will result.
9977 For example, (and (ior A B) (not B)) can occur as the result of
9978 expanding a bit field assignment. When we apply the distributive
9979 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9980 which then simplifies to (and (A (not B))).
9982 Note that no checks happen on the validity of applying the inverse
9983 distributive law. This is pointless since we can do it in the
9984 few places where this routine is called.
9986 N is the index of the term that is decomposed (the arithmetic operation,
9987 i.e. (+ A B) in the first example above). !N is the index of the term that
9988 is distributed, i.e. of C in the first example above. */
9989 static rtx
9991 {
9992 machine_mode mode;
9996 /* Distributivity is not true for floating point as it can change the
9997 value. So we don't do it unless -funsafe-math-optimizations. */
10014 /* Special case (and (xor B C) (not A)), which is equivalent to
10015 (xor (ior A B) (ior A C)) */
10017 {
10020 }
10023 {
10024 /* Distribute the second term. */
10027 }
10028 else
10029 {
10030 /* Distribute the first term. */
10033 }
10043 }
10044 \f
10045 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10046 in MODE. Return an equivalent form, if different from (and VAROP
10047 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10049 static rtx
10052 {
10055 rtx orig_varop;
10063 /* Simplify VAROP knowing that we will be only looking at some of the
10064 bits in it.
10066 Note by passing in CONSTOP, we guarantee that the bits not set in
10067 CONSTOP are not significant and will never be examined. We must
10068 ensure that is the case by explicitly masking out those bits
10069 before returning. */
10072 /* If VAROP is a CLOBBER, we will fail so return it. */
10076 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10077 to VAROP and return the new constant. */
10081 /* See what bits may be nonzero in VAROP. Unlike the general case of
10082 a call to nonzero_bits, here we don't care about bits outside
10083 MODE. */
10087 /* Turn off all bits in the constant that are known to already be zero.
10088 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10089 which is tested below. */
10093 /* If we don't have any bits left, return zero. */
10097 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10098 a power of two, we can replace this with an ASHIFT. */
10103 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10104 or XOR, then try to apply the distributive law. This may eliminate
10105 operations if either branch can be simplified because of the AND.
10106 It may also make some cases more complex, but those cases probably
10107 won't match a pattern either with or without this. */
10110 {
10112 return
10113 gen_lowpart
10115 apply_distributive_law
10119 constop),
10122 constop))));
10123 }
10125 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10126 the AND and see if one of the operands simplifies to zero. If so, we
10127 may eliminate it. */
10131 {
10140 }
10142 /* Make a SUBREG if necessary. If we can't make it, fail. */
10147 /* If we are only masking insignificant bits, return VAROP. */
10154 /* Otherwise, return an AND. */
10156 }
10159 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10160 in MODE.
10162 Return an equivalent form, if different from X. Otherwise, return X. If
10163 X is zero, we are to always construct the equivalent form. */
10165 static rtx
10168 {
10179 }
10180 \f
10181 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10182 We don't care about bits outside of those defined in MODE.
10184 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10185 a shift, AND, or zero_extract, we can do better. */
10187 static rtx
10189 scalar_int_mode mode,
10191 {
10192 rtx tem;
10195 /* If X is a register whose nonzero bits value is current, use it.
10196 Otherwise, if X is a register whose value we can find, use that
10197 value. Otherwise, use the previously-computed global nonzero bits
10198 for this register. */
10213 && !REGNO_REG_SET_P
10216 {
10217 /* Note that, even if the precision of last_set_mode is lower than that
10218 of mode, record_value_for_reg invoked nonzero_bits on the register
10219 with nonzero_bits_mode (because last_set_mode is necessarily integral
10220 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10221 are all valid, hence in mode too since nonzero_bits_mode is defined
10222 to the largest HWI_COMPUTABLE_MODE_P mode. */
10225 }
10229 {
10234 }
10237 {
10241 /* We don't know anything about the upper bits. */
10245 }
10248 }
10250 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10251 end of X that are known to be equal to the sign bit. X will be used
10252 in mode MODE; the returned value will always be between 1 and the
10253 number of bits in MODE. */
10255 static rtx
10257 scalar_int_mode mode,
10259 {
10260 rtx tem;
10273 && !REGNO_REG_SET_P
10276 {
10279 }
10290 }
10291 \f
10292 /* Return the number of "extended" bits there are in X, when interpreted
10293 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10294 unsigned quantities, this is the number of high-order zero bits.
10295 For signed quantities, this is the number of copies of the sign bit
10296 minus 1. In both case, this function returns the number of "spare"
10297 bits. For example, if two quantities for which this function returns
10298 at least 1 are added, the addition is known not to overflow.
10300 This function will always return 0 unless called during combine, which
10301 implies that it must be called from a define_split. */
10303 unsigned int
10305 {
10309 scalar_int_mode int_mode;
10317 }
10319 /* This function is called from `simplify_shift_const' to merge two
10320 outer operations. Specifically, we have already found that we need
10321 to perform operation *POP0 with constant *PCONST0 at the outermost
10322 position. We would now like to also perform OP1 with constant CONST1
10323 (with *POP0 being done last).
10325 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10326 the resulting operation. *PCOMP_P is set to 1 if we would need to
10327 complement the innermost operand, otherwise it is unchanged.
10329 MODE is the mode in which the operation will be done. No bits outside
10330 the width of this mode matter. It is assumed that the width of this mode
10331 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10333 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10334 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10335 result is simply *PCONST0.
10337 If the resulting operation cannot be expressed as one operation, we
10338 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10340 static int
10341 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10342 {
10349 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10353 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10354 if OP0 is SET. */
10363 {
10365 {
10383 }
10384 }
10386 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10390 /* If the two constants aren't the same, we can't do anything. The
10391 remaining six cases can all be done. */
10395 else
10397 {
10400 /* (a & b) | b == b */
10403 /* (a ^ b) | b == a | b */
10404 {;}
10409 /* (a & b) ^ b == (~a) & b */
10412 /* (a | b) ^ b == a & ~b */
10418 /* (a | b) & b == b */
10421 /* (a ^ b) & b) == (~a) & b */
10426 }
10428 /* Check for NO-OP cases. */
10441 /* ??? Slightly redundant with the above mask, but not entirely.
10442 Moving this above means we'd have to sign-extend the mode mask
10443 for the final test. */
10448 }
10449 \f
10450 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10451 the shift in. The original shift operation CODE is performed on OP in
10452 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10453 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10454 result of the shift is subject to operation OUTER_CODE with operand
10455 OUTER_CONST. */
10457 static scalar_int_mode
10461 {
10464 /* In general we can't perform in wider mode for right shift and rotate. */
10466 {
10468 /* We can still widen if the bits brought in from the left are identical
10469 to the sign bit of ORIG_MODE. */
10477 /* Similarly here but with zero bits. */
10482 /* We can also widen if the bits brought in will be masked off. This
10483 operation is performed in ORIG_MODE. */
10485 {
10491 }
10492 /* fall through */
10502 }
10503 }
10505 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10506 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10507 if we cannot simplify it. Otherwise, return a simplified value.
10509 The shift is normally computed in the widest mode we find in VAROP, as
10510 long as it isn't a different number of words than RESULT_MODE. Exceptions
10511 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10513 static rtx
10516 {
10521 machine_mode shift_mode;
10523 /* We form (outer_op (code varop count) (outer_const)). */
10529 /* Make sure and truncate the "natural" shift on the way in. We don't
10530 want to do this inside the loop as it makes it more difficult to
10531 combine shifts. */
10535 /* If we were given an invalid count, don't do anything except exactly
10536 what was requested. */
10543 /* Unless one of the branches of the `if' in this loop does a `continue',
10544 we will `break' the loop after the `if'. */
10547 {
10548 /* If we have an operand of (clobber (const_int 0)), fail. */
10552 /* Convert ROTATERT to ROTATE. */
10554 {
10558 }
10562 {
10563 /* We only change the modes of scalar shifts. */
10569 }
10571 scalar_int_mode shift_unit_mode
10574 /* Handle cases where the count is greater than the size of the mode
10575 minus 1. For ASHIFT, use the size minus one as the count (this can
10576 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10577 take the count modulo the size. For other shifts, the result is
10578 zero.
10580 Since these shifts are being produced by the compiler by combining
10581 multiple operations, each of which are defined, we know what the
10582 result is supposed to be. */
10585 {
10590 else
10591 {
10592 /* We can't simply return zero because there may be an
10593 outer op. */
10597 }
10598 }
10600 /* If we discovered we had to complement VAROP, leave. Making a NOT
10601 here would cause an infinite loop. */
10606 {
10607 /* An arithmetic right shift of a quantity known to be -1 or 0
10608 is a no-op. */
10612 {
10615 }
10617 /* If we are doing an arithmetic right shift and discarding all but
10618 the sign bit copies, this is equivalent to doing a shift by the
10619 bitsize minus one. Convert it into that shift because it will
10620 often allow other simplifications. */
10627 /* We simplify the tests below and elsewhere by converting
10628 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10629 `make_compound_operation' will convert it to an ASHIFTRT for
10630 those machines (such as VAX) that don't have an LSHIFTRT. */
10635 shift_unit_mode)))
10647 }
10650 {
10657 {
10660 }
10664 /* The following rules apply only to scalars. */
10669 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10670 minus the width of a smaller mode, we can do this with a
10671 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10678 {
10687 }
10691 /* The following rules apply only to scalars. */
10697 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10698 the same number of words as what we've seen so far. Then store
10699 the widest mode in MODE. */
10706 {
10711 }
10715 /* Some machines use MULT instead of ASHIFT because MULT
10716 is cheaper. But it is still better on those machines to
10717 merge two shifts into one. */
10720 {
10725 }
10729 /* Similar, for when divides are cheaper. */
10732 {
10737 }
10741 /* If we are extracting just the sign bit of an arithmetic
10742 right shift, that shift is not needed. However, the sign
10743 bit of a wider mode may be different from what would be
10744 interpreted as the sign bit in a narrower mode, so, if
10745 the result is narrower, don't discard the shift. */
10750 {
10753 }
10755 /* fall through */
10760 /* The following rules apply only to scalars. */
10767 /* Here we have two nested shifts. The result is usually the
10768 AND of a new shift with a mask. We compute the result below. */
10774 {
10778 rtx mask_rtx;
10780 /* We have one common special case. We can't do any merging if
10781 the inner code is an ASHIFTRT of a smaller mode. However, if
10782 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10783 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10784 we can convert it to
10785 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10786 This simplifies certain SIGN_EXTEND operations. */
10790 {
10791 /* C3 has the low-order C1 bits zero. */
10803 }
10805 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10806 than C1 high-order bits equal to the sign bit, we can convert
10807 this to either an ASHIFT or an ASHIFTRT depending on the
10808 two counts.
10810 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10816 {
10820 {
10823 }
10826 }
10828 /* There are some cases we can't do. If CODE is ASHIFTRT,
10829 we can only do this if FIRST_CODE is also ASHIFTRT.
10831 We can't do the case when CODE is ROTATE and FIRST_CODE is
10832 ASHIFTRT.
10834 If the mode of this shift is not the mode of the outer shift,
10835 we can't do this if either shift is a right shift or ROTATE.
10837 Finally, we can't do any of these if the mode is too wide
10838 unless the codes are the same.
10840 Handle the case where the shift codes are the same
10841 first. */
10844 {
10853 }
10864 /* To compute the mask to apply after the shift, shift the
10865 nonzero bits of the inner shift the same way the
10866 outer shift will. */
10869 int_result_mode);
10871 mask_rtx
10875 /* Give up if we can't compute an outer operation to use. */
10883 /* If the shifts are in the same direction, we add the
10884 counts. Otherwise, we subtract them. */
10888 else
10891 /* If COUNT is positive, the new shift is usually CODE,
10892 except for the two exceptions below, in which case it is
10893 FIRST_CODE. If the count is negative, FIRST_CODE should
10894 always be used */
10904 }
10906 /* If we have (A << B << C) for any shift, we can convert this to
10907 (A << C << B). This wins if A is a constant. Only try this if
10908 B is not a constant. */
10913 {
10914 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10915 sure the result will be masked. See PR70222. */
10923 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10924 up outer sign extension (often left and right shift) is
10925 hardly more efficient than the original. See PR70429. */
10932 count_rtx);
10936 }
10940 /* The following rules apply only to scalars. */
10944 /* Make this fit the case below. */
10951 /* The following rules apply only to scalars. */
10957 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10958 with C the size of VAROP - 1 and the shift is logical if
10959 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10960 we have an (le X 0) operation. If we have an arithmetic shift
10961 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10962 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10970 {
10973 const0_rtx);
10979 }
10981 /* If we have (shift (logical)), move the logical to the outside
10982 to allow it to possibly combine with another logical and the
10983 shift to combine with another shift. This also canonicalizes to
10984 what a ZERO_EXTRACT looks like. Also, some machines have
10985 (and (shift)) insns. */
10988 /* We can't do this if we have (ashiftrt (xor)) and the
10989 constant has its sign bit set in shift_unit_mode with
10990 shift_unit_mode wider than result_mode. */
11003 {
11006 }
11008 /* If we can't do that, try to simplify the shift in each arm of the
11009 logical expression, make a new logical expression, and apply
11010 the inverse distributive law. This also can't be done for
11011 (ashiftrt (xor)) where we've widened the shift and the constant
11012 changes the sign bit. */
11018 {
11030 }
11034 /* The following rules apply only to scalars. */
11039 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11040 says that the sign bit can be tested, FOO has mode MODE, C is
11041 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11042 that may be nonzero. */
11052 {
11056 }
11060 /* The following rules apply only to scalars. */
11065 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11066 than the number of bits in the mode is equivalent to A. */
11070 {
11074 }
11076 /* NEG commutes with ASHIFT since it is multiplication. Move the
11077 NEG outside to allow shifts to combine. */
11081 {
11084 }
11088 /* The following rules apply only to scalars. */
11093 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11094 is one less than the number of bits in the mode is
11095 equivalent to (xor A 1). */
11102 {
11106 }
11108 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11109 that might be nonzero in BAR are those being shifted out and those
11110 bits are known zero in FOO, we can replace the PLUS with FOO.
11111 Similarly in the other operand order. This code occurs when
11112 we are computing the size of a variable-size array. */
11119 {
11122 }
11130 {
11133 }
11135 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11146 {
11149 }
11151 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11152 signbit', and attempt to change the PLUS to an XOR and move it to
11153 the outer operation as is done above in the AND/IOR/XOR case
11154 leg for shift(logical). See details in logical handling above
11155 for reasoning in doing so. */
11167 {
11170 }
11175 /* The following rules apply only to scalars. */
11180 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11181 with C the size of VAROP - 1 and the shift is logical if
11182 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11183 we have a (gt X 0) operation. If the shift is arithmetic with
11184 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11185 we have a (neg (gt X 0)) operation. */
11194 {
11197 const0_rtx);
11203 }
11207 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11208 if the truncate does not affect the value. */
11215 {
11219 new_count);
11222 new_count_rtx);
11226 }
11231 }
11234 }
11238 {
11239 /* We only change the modes of scalar shifts. */
11244 }
11246 /* We have now finished analyzing the shift. The result should be
11247 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11248 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11249 to the result of the shift. OUTER_CONST is the relevant constant,
11250 but we must turn off all bits turned off in the shift. */
11258 /* Make a SUBREG if necessary. If we can't make it, fail. */
11263 /* If we have an outer operation and we just made a shift, it is
11264 possible that we could have simplified the shift were it not
11265 for the outer operation. So try to do the simplification
11266 recursively. */
11270 else
11277 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11278 turn off all the bits that the shift would have turned off. */
11280 /* We only change the modes of scalar shifts. */
11284 /* Do the remainder of the processing in RESULT_MODE. */
11287 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11288 operation. */
11293 {
11303 {
11304 /* This means that we have determined that the result is
11305 equivalent to a constant. This should be rare. */
11308 }
11311 else
11314 }
11317 }
11319 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11320 The result of the shift is RESULT_MODE. If we cannot simplify it,
11321 return X or, if it is NULL, synthesize the expression with
11322 simplify_gen_binary. Otherwise, return a simplified value.
11324 The shift is normally computed in the widest mode we find in VAROP, as
11325 long as it isn't a different number of words than RESULT_MODE. Exceptions
11326 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11328 static rtx
11331 {
11342 }
11344 \f
11345 /* A subroutine of recog_for_combine. See there for arguments and
11346 return value. */
11348 static int
11350 {
11352 rtx pat_without_clobbers;
11360 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11361 we use to indicate that something didn't match. If we find such a
11362 thing, force rejection. */
11376 {
11379 else
11382 }
11384 /* If it isn't, there is the possibility that we previously had an insn
11385 that clobbered some register as a side effect, but the combined
11386 insn doesn't need to do that. So try once more without the clobbers
11387 unless this represents an ASM insn. */
11391 {
11396 {
11399 pos++;
11400 }
11410 {
11413 else
11416 }
11417 }
11424 /* Recognize all noop sets, these will be killed by followup pass. */
11428 /* If we had any clobbers to add, make a new pattern than contains
11429 them. Then check to make sure that all of them are dead. */
11431 {
11441 else
11448 {
11453 {
11457 }
11458 }
11460 }
11464 {
11472 /* Allow targets to reject combined insn. */
11474 {
11477 dump_file);
11479 /* Callers expect recog_for_combine to strip
11480 clobbers from the pattern on failure. */
11485 }
11490 }
11496 }
11498 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11499 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11500 Return whether anything was so changed. */
11502 static bool
11504 {
11510 {
11522 {
11532 else
11536 {
11542 }
11543 }
11549 {
11554 {
11560 }
11561 }
11566 {
11570 }
11571 else
11577 {
11580 }
11584 }
11591 scalar_int_mode mode;
11597 {
11611 else
11619 }
11622 }
11624 /* Like recog, but we receive the address of a pointer to a new pattern.
11625 We try to match the rtx that the pointer points to.
11626 If that fails, we may try to modify or replace the pattern,
11627 storing the replacement into the same pointer object.
11629 Modifications include deletion or addition of CLOBBERs. If the
11630 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11631 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11632 (and undo if that fails).
11634 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11635 the CLOBBERs are placed.
11637 The value is the final insn code from the pattern ultimately matched,
11638 or -1. */
11640 static int
11642 {
11654 {
11657 {
11661 }
11662 }
11665 {
11670 }
11673 }
11674 \f
11675 /* Like gen_lowpart_general but for use by combine. In combine it
11676 is not possible to create any new pseudoregs. However, it is
11677 safe to create invalid memory addresses, because combine will
11678 try to recognize them and all they will do is make the combine
11679 attempt fail.
11681 If for some reason this cannot do its job, an rtx
11682 (clobber (const_int 0)) is returned.
11683 An insn containing that will not be recognized. */
11685 static rtx
11687 {
11689 rtx result;
11694 /* We can only support MODE being wider than a word if X is a
11695 constant integer or has a mode the same size. */
11701 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11702 won't know what to do. So we will strip off the SUBREG here and
11703 process normally. */
11705 {
11708 /* For use in case we fall down into the address adjustments
11709 further below, we need to adjust the known mode and size of
11710 x; imode and isize, since we just adjusted x. */
11715 }
11723 {
11724 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11725 address. */
11730 /* If we want to refer to something bigger than the original memref,
11731 generate a paradoxical subreg instead. That will force a reload
11732 of the original memref X. */
11738 }
11740 /* If X is a comparison operator, rewrite it in a new mode. This
11741 probably won't match, but may allow further simplifications. */
11745 /* If we couldn't simplify X any other way, just enclose it in a
11746 SUBREG. Normally, this SUBREG won't match, but some patterns may
11747 include an explicit SUBREG or we may simplify it further in combine. */
11748 else
11749 {
11750 rtx res;
11753 {
11758 }
11762 }
11764 fail:
11766 }
11767 \f
11768 /* Try to simplify a comparison between OP0 and a constant OP1,
11769 where CODE is the comparison code that will be tested, into a
11770 (CODE OP0 const0_rtx) form.
11772 The result is a possibly different comparison code to use.
11773 *POP1 may be updated. */
11775 static enum rtx_code
11778 {
11779 scalar_int_mode int_mode;
11782 /* Get the constant we are comparing against and turn off all bits
11783 not on in our mode. */
11787 /* If we are comparing against a constant power of two and the value
11788 being compared can only have that single bit nonzero (e.g., it was
11789 `and'ed with that bit), we can replace this with a comparison
11790 with zero. */
11799 {
11802 }
11804 /* Similarly, if we are comparing a value known to be either -1 or
11805 0 with -1, change it to the opposite comparison against zero. */
11811 {
11814 }
11816 /* Do some canonicalizations based on the comparison code. We prefer
11817 comparisons against zero and then prefer equality comparisons.
11818 If we can reduce the size of a constant, we will do that too. */
11820 {
11822 /* < C is equivalent to <= (C - 1) */
11824 {
11827 /* ... fall through to LE case below. */
11829 }
11830 else
11834 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11836 {
11839 }
11841 /* If we are doing a <= 0 comparison on a value known to have
11842 a zero sign bit, we can replace this with == 0. */
11853 /* >= C is equivalent to > (C - 1). */
11855 {
11858 /* ... fall through to GT below. */
11860 }
11861 else
11865 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11867 {
11870 }
11872 /* If we are doing a > 0 comparison on a value known to have
11873 a zero sign bit, we can replace this with != 0. */
11884 /* < C is equivalent to <= (C - 1). */
11886 {
11889 /* ... fall through ... */
11891 }
11892 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11897 {
11901 }
11902 else
11906 /* unsigned <= 0 is equivalent to == 0 */
11909 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11913 == ((HOST_WIDE_INT_1U
11915 {
11918 }
11922 /* >= C is equivalent to > (C - 1). */
11924 {
11927 /* ... fall through ... */
11929 }
11931 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11936 {
11940 }
11941 else
11945 /* unsigned > 0 is equivalent to != 0 */
11948 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11952 == (HOST_WIDE_INT_1U
11954 {
11957 }
11962 }
11966 }
11967 \f
11968 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11969 comparison code that will be tested.
11971 The result is a possibly different comparison code to use. *POP0 and
11972 *POP1 may be updated.
11974 It is possible that we might detect that a comparison is either always
11975 true or always false. However, we do not perform general constant
11976 folding in combine, so this knowledge isn't useful. Such tautologies
11977 should have been detected earlier. Hence we ignore all such cases. */
11979 static enum rtx_code
11981 {
11987 opt_scalar_int_mode tmode_iter;
11989 /* Try a few ways of applying the same transformation to both operands. */
11991 {
11992 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11993 so check specially. */
12012 {
12015 }
12017 /* If both operands are the same constant shift, see if we can ignore the
12018 shift. We can if the shift is a rotate or if the bits shifted out of
12019 this shift are known to be zero for both inputs and if the type of
12020 comparison is compatible with the shift. */
12033 {
12046 else
12048 }
12050 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12051 SUBREGs are of the same mode, and, in both cases, the AND would
12052 be redundant if the comparison was done in the narrower mode,
12053 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12054 and the operand's possibly nonzero bits are 0xffffff01; in that case
12055 if we only care about QImode, we don't need the AND). This case
12056 occurs if the output mode of an scc insn is not SImode and
12057 STORE_FLAG_VALUE == 1 (e.g., the 386).
12059 Similarly, check for a case where the AND's are ZERO_EXTEND
12060 operations from some narrower mode even though a SUBREG is not
12061 present. */
12066 {
12082 {
12086 /* The resulting comparison is always unsigned since we masked
12087 off the original sign bit. */
12091 }
12097 {
12103 }
12107 }
12109 /* If both operands are NOT, we can strip off the outer operation
12110 and adjust the comparison code for swapped operands; similarly for
12111 NEG, except that this must be an equality comparison. */
12117 else
12119 }
12121 /* If the first operand is a constant, swap the operands and adjust the
12122 comparison code appropriately, but don't do this if the second operand
12123 is already a constant integer. */
12125 {
12128 }
12130 /* We now enter a loop during which we will try to simplify the comparison.
12131 For the most part, we only are concerned with comparisons with zero,
12132 but some things may really be comparisons with zero but not start
12133 out looking that way. */
12136 {
12138 scalar_int_mode int_mode;
12142 HOST_WIDE_INT const_op;
12144 /* We only want to handle integral modes. This catches VOIDmode,
12145 CCmode, and the floating-point modes. An exception is that we
12146 can handle VOIDmode if OP0 is a COMPARE or a comparison
12147 operation. */
12154 /* Try to simplify the compare to constant, possibly changing the
12155 comparison op, and/or changing op1 to zero. */
12159 /* Compute some predicates to simplify code below. */
12166 /* If this is a sign bit comparison and we can do arithmetic in
12167 MODE, say that we will only be needing the sign bit of OP0. */
12172 HOST_WIDE_INT_1U
12177 {
12178 /* We can't do anything if OP0 is a condition code value, rather
12179 than an actual data value. */
12185 /* Get the two operands being compared. */
12188 else
12191 /* Check for the cases where we simply want the result of the
12192 earlier test or the opposite of that result. */
12196 {
12200 else
12204 {
12209 }
12210 }
12212 }
12218 /* Now try cases based on the opcode of OP0. If none of the cases
12219 does a "continue", we exit this loop immediately after the
12220 switch. */
12225 {
12227 /* If we are extracting a single bit from a variable position in
12228 a constant that has only a single bit set and are comparing it
12229 with zero, we can convert this into an equality comparison
12230 between the position and the location of the single bit. */
12231 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12232 have already reduced the shift count modulo the word size. */
12238 {
12246 /* Result is nonzero iff shift count is equal to I. */
12249 }
12251 /* fall through */
12256 {
12259 }
12263 /* If testing for equality, we can take the NOT of the constant. */
12266 {
12270 }
12272 /* If just looking at the sign bit, reverse the sense of the
12273 comparison. */
12275 {
12279 }
12283 /* If testing for equality, we can take the NEG of the constant. */
12286 {
12290 }
12292 /* The remaining cases only apply to comparisons with zero. */
12296 /* When X is ABS or is known positive,
12297 (neg X) is < 0 if and only if X != 0. */
12305 {
12309 }
12311 /* If we have NEG of something whose two high-order bits are the
12312 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12314 {
12318 }
12322 /* If we are testing equality and our count is a constant, we
12323 can perform the inverse operation on our RHS. */
12327 {
12331 }
12333 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12334 a particular bit. Convert it to an AND of a constant of that
12335 bit. This will be converted into a ZERO_EXTRACT. */
12339 {
12341 (HOST_WIDE_INT_1U
12346 }
12348 /* Fall through. */
12351 /* ABS is ignorable inside an equality comparison with zero. */
12353 {
12356 }
12360 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12361 (compare FOO CONST) if CONST fits in FOO's mode and we
12362 are either testing inequality or have an unsigned
12363 comparison with ZERO_EXTEND or a signed comparison with
12364 SIGN_EXTEND. But don't do it if we don't have a compare
12365 insn of the given mode, since we'd have to revert it
12366 later on, and then we wouldn't know whether to sign- or
12367 zero-extend. */
12369 && ! unsigned_comparison_p
12373 {
12376 }
12380 /* Check for the case where we are comparing A - C1 with C2, that is
12382 (subreg:MODE (plus (A) (-C1))) op (C2)
12384 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12385 comparison in the wider mode. One of the following two conditions
12386 must be true in order for this to be valid:
12388 1. The mode extension results in the same bit pattern being added
12389 on both sides and the comparison is equality or unsigned. As
12390 C2 has been truncated to fit in MODE, the pattern can only be
12391 all 0s or all 1s.
12393 2. The mode extension results in the sign bit being copied on
12394 each side.
12396 The difficulty here is that we have predicates for A but not for
12397 (A - C1) so we need to check that C1 is within proper bounds so
12398 as to perturbate A as little as possible. */
12407 {
12415 /* (A - C1) zero-extends if it is positive and sign-extends
12416 if it is negative, C2 both zero- and sign-extends. */
12420 /* (A - C1) sign-extends if it is positive and 1-extends
12421 if it is negative, C2 both sign- and 1-extends. */
12428 /* (A - C1) always sign-extends, like C2. */
12432 {
12435 }
12436 }
12438 /* If the inner mode is narrower and we are extracting the low part,
12439 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12441 ;
12450 {
12451 /* Remove outer subregs that don't do anything. */
12456 {
12460 }
12462 }
12463 else
12466 /* FALLTHROUGH */
12475 {
12478 }
12482 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12483 this for equality comparisons due to pathological cases involving
12484 overflows. */
12488 {
12492 }
12494 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12497 {
12501 }
12505 /* We used to optimize signed comparisons against zero, but that
12506 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12507 arrive here as equality comparisons, or (GEU, LTU) are
12508 optimized away. No need to special-case them. */
12510 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12511 (eq B (minus A C)), whichever simplifies. We can only do
12512 this for equality comparisons due to pathological cases involving
12513 overflows. */
12517 {
12521 }
12526 {
12530 }
12532 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12533 of bits in X minus 1, is one iff X > 0. */
12538 {
12542 }
12546 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12547 if C is zero or B is a constant. */
12551 {
12555 }
12560 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12561 iff X <= 0. */
12565 {
12569 }
12573 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12574 will be converted to a ZERO_EXTRACT later. */
12578 {
12583 }
12585 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12586 zero and X is a comparison and C1 and C2 describe only bits set
12587 in STORE_FLAG_VALUE, we can compare with X. */
12595 {
12602 {
12605 }
12606 }
12608 /* If we are doing an equality comparison of an AND of a bit equal
12609 to the sign bit, replace this with a LT or GE comparison of
12610 the underlying value. */
12617 {
12621 }
12623 /* If this AND operation is really a ZERO_EXTEND from a narrower
12624 mode, the constant fits within that mode, and this is either an
12625 equality or unsigned comparison, try to do this comparison in
12626 the narrower mode.
12628 Note that in:
12630 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12631 -> (ne:DI (reg:SI 4) (const_int 0))
12633 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12634 known to hold a value of the required mode the
12635 transformation is invalid. */
12643 {
12646 }
12648 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12649 fits in both M1 and M2 and the SUBREG is either paradoxical
12650 or represents the low part, permute the SUBREG and the AND
12651 and try again. */
12654 {
12656 /* Require an integral mode, to avoid creating something like
12657 (AND:SF ...). */
12660 /* It is unsafe to commute the AND into the SUBREG if the
12661 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12662 not defined. As originally written the upper bits
12663 have a defined value due to the AND operation.
12664 However, if we commute the AND inside the SUBREG then
12665 they no longer have defined values and the meaning of
12666 the code has been changed.
12667 Also C1 should not change value in the smaller mode,
12668 see PR67028 (a positive C1 can become negative in the
12669 smaller mode, so that the AND does no longer mask the
12670 upper bits). */
12671 && ((WORD_REGISTER_OPERATIONS
12683 {
12689 }
12690 }
12692 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12696 {
12701 }
12703 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12704 (eq (and (lshiftrt X) 1) 0).
12705 Also handle the case where (not X) is expressed using xor. */
12709 {
12719 == HOST_WIDE_INT_1U
12721 {
12722 op0
12727 }
12728 }
12732 /* If we have (compare (ashift FOO N) (const_int C)) and
12733 the high order N bits of FOO (N+1 if an inequality comparison)
12734 are known to be zero, we can do this by comparing FOO with C
12735 shifted right N bits so long as the low-order N bits of C are
12736 zero. */
12748 {
12749 /* We must perform a logical shift, not an arithmetic one,
12750 as we want the top N bits of C to be zero. */
12757 }
12759 /* If we are doing a sign bit comparison, it means we are testing
12760 a particular bit. Convert it to the appropriate AND. */
12763 {
12765 (HOST_WIDE_INT_1U
12770 }
12772 /* If this an equality comparison with zero and we are shifting
12773 the low bit to the sign bit, we can convert this to an AND of the
12774 low-order bit. */
12778 {
12781 }
12785 /* If this is an equality comparison with zero, we can do this
12786 as a logical shift, which might be much simpler. */
12789 {
12794 }
12796 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12797 do the comparison in a narrower mode. */
12807 {
12810 }
12812 /* Likewise if OP0 is a PLUS of a sign extension with a
12813 constant, which is usually represented with the PLUS
12814 between the shifts. */
12826 {
12834 new_const);
12836 }
12838 /* FALLTHROUGH */
12840 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12841 the low order N bits of FOO are known to be zero, we can do this
12842 by comparing FOO with C shifted left N bits so long as no
12843 overflow occurs. Even if the low order N bits of FOO aren't known
12844 to be zero, if the comparison is >= or < we can use the same
12845 optimization and for > or <= by setting all the low
12846 order N bits in the comparison constant. */
12857 {
12858 unsigned HOST_WIDE_INT low_bits
12860 & ((HOST_WIDE_INT_1U
12863 {
12864 /* If the shift was logical, then we must make the condition
12865 unsigned. */
12874 const_op
12879 }
12880 }
12882 /* If we are using this shift to extract just the sign bit, we
12883 can replace this with an LT or GE comparison. */
12888 {
12892 }
12897 }
12900 }
12902 /* Now make any compound operations involved in this comparison. Then,
12903 check for an outmost SUBREG on OP0 that is not doing anything or is
12904 paradoxical. The latter transformation must only be performed when
12905 it is known that the "extra" bits will be the same in op0 and op1 or
12906 that they don't matter. There are three cases to consider:
12908 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12909 care bits and we can assume they have any convenient value. So
12910 making the transformation is safe.
12912 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12913 In this case the upper bits of op0 are undefined. We should not make
12914 the simplification in that case as we do not know the contents of
12915 those bits.
12917 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12918 In that case we know those bits are zeros or ones. We must also be
12919 sure that they are the same as the upper bits of op1.
12921 We can never remove a SUBREG for a non-equality comparison because
12922 the sign bit is in a different place in the underlying object. */
12935 {
12937 {
12938 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12939 implemented. */
12941 {
12944 }
12945 }
12949 {
12954 }
12955 }
12957 /* We now do the opposite procedure: Some machines don't have compare
12958 insns in all modes. If OP0's mode is an integer mode smaller than a
12959 word and we can't do a compare in that mode, see if there is a larger
12960 mode for which we can do the compare. There are a number of cases in
12961 which we can use the wider mode. */
12967 {
12972 {
12975 /* If this is a test for negative, we can make an explicit
12976 test of the sign bit. Test this first so we can use
12977 a paradoxical subreg to extend OP0. */
12981 {
12982 unsigned HOST_WIDE_INT sign
12989 }
12991 /* If the only nonzero bits in OP0 and OP1 are those in the
12992 narrower mode and this is an equality or unsigned comparison,
12993 we can use the wider mode. Similarly for sign-extended
12994 values, in which case it is true for all comparisons. */
13011 {
13012 /* If OP0 is an AND and we don't have an AND in MODE either,
13013 make a new AND in the proper mode. */
13021 else
13022 {
13024 {
13029 }
13030 else
13031 {
13036 }
13038 }
13039 }
13040 }
13041 }
13043 /* We may have changed the comparison operands. Re-canonicalize. */
13045 {
13048 }
13050 /* If this machine only supports a subset of valid comparisons, see if we
13051 can convert an unsupported one into a supported one. */
13058 }
13059 \f
13060 /* Utility function for record_value_for_reg. Count number of
13061 rtxs in X. */
13062 static int
13064 {
13071 {
13091 }
13102 }
13103 \f
13104 /* Utility function for following routine. Called when X is part of a value
13105 being stored into last_set_value. Sets last_set_table_tick
13106 for each register mentioned. Similar to mention_regs in cse.c */
13108 static void
13110 {
13116 {
13122 {
13125 }
13128 }
13132 {
13133 /* Check for identical subexpressions. If x contains
13134 identical subexpression we only have to traverse one of
13135 them. */
13137 {
13138 /* Note that at this point x1 has already been
13139 processed. */
13143 /* If x0 and x1 are identical then there is no need to
13144 process x0. */
13148 /* If x0 is identical to a subexpression of x1 then while
13149 processing x1, x0 has already been processed. Thus we
13150 are done with x. */
13155 /* If x1 is identical to a subexpression of x0 then we
13156 still have to process the rest of x0. */
13159 {
13162 }
13163 }
13166 }
13170 }
13172 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13173 are saying that the register is clobbered and we no longer know its
13174 value. If INSN is zero, don't update reg_stat[].last_set; this is
13175 only permitted with VALUE also zero and is used to invalidate the
13176 register. */
13178 static void
13180 {
13186 /* If VALUE contains REG and we have a previous value for REG, substitute
13187 the previous value. */
13189 {
13190 rtx tem;
13192 /* Set things up so get_last_value is allowed to see anything set up to
13193 our insn. */
13197 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13198 it isn't going to be useful and will take a lot of time to process,
13199 so just use the CLOBBER. */
13202 {
13208 {
13209 /* If there are two or more occurrences of REG in VALUE,
13210 prevent the value from growing too much. */
13213 }
13216 }
13217 }
13219 /* For each register modified, show we don't know its value, that
13220 we don't know about its bitwise content, that its value has been
13221 updated, and that we don't know the location of the death of the
13222 register. */
13224 {
13236 }
13238 /* Mark registers that are being referenced in this value. */
13242 /* Now update the status of each register being set.
13243 If someone is using this register in this block, set this register
13244 to invalid since we will get confused between the two lives in this
13245 basic block. This makes using this register always invalid. In cse, we
13246 scan the table to invalidate all entries using this register, but this
13247 is too much work for us. */
13250 {
13256 else
13258 }
13260 /* The value being assigned might refer to X (like in "x++;"). In that
13261 case, we must replace it with (clobber (const_int 0)) to prevent
13262 infinite loops. */
13265 {
13269 }
13271 /* For the main register being modified, update the value, the mode, the
13272 nonzero bits, and the number of sign bit copies. */
13277 {
13285 rsp->last_set_sign_bit_copies
13287 }
13288 }
13290 /* Called via note_stores from record_dead_and_set_regs to handle one
13291 SET or CLOBBER in an insn. DATA is the instruction in which the
13292 set is occurring. */
13294 static void
13296 {
13303 {
13307 }
13310 {
13311 /* If we are setting the whole register, we know its value. Otherwise
13312 show that we don't know the value. We can handle a SUBREG if it's
13313 the low part, but we must be careful with paradoxical SUBREGs on
13314 RISC architectures because we cannot strip e.g. an extension around
13315 a load and record the naked load since the RTL middle-end considers
13316 that the upper bits are defined according to LOAD_EXTEND_OP. */
13323 BITS_PER_WORD)
13326 WORD_REGISTER_OPERATIONS
13332 {
13335 && reg_is_clobbered_by_clobber_high
13339 }
13340 else
13342 }
13344 /* Ignore pushes, they clobber nothing. */
13347 }
13349 /* Update the records of when each REG was most recently set or killed
13350 for the things done by INSN. This is the last thing done in processing
13351 INSN in the combiner loop.
13353 We update reg_stat[], in particular fields last_set, last_set_value,
13354 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13355 last_death, and also the similar information mem_last_set (which insn
13356 most recently modified memory) and last_call_luid (which insn was the
13357 most recent subroutine call). */
13359 static void
13361 {
13362 rtx link;
13366 {
13369 {
13374 {
13379 }
13380 }
13383 }
13386 {
13387 hard_reg_set_iterator hrsi;
13389 {
13401 }
13405 /* We can't combine into a call pattern. Remember, though, that
13406 the return value register is set at this LUID. We could
13407 still replace a register with the return value from the
13408 wrong subroutine call! */
13410 }
13411 else
13413 }
13415 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13416 register present in the SUBREG, so for each such SUBREG go back and
13417 adjust nonzero and sign bit information of the registers that are
13418 known to have some zero/sign bits set.
13420 This is needed because when combine blows the SUBREGs away, the
13421 information on zero/sign bits is lost and further combines can be
13422 missed because of that. */
13424 static void
13426 {
13428 rtx set;
13436 {
13445 {
13448 }
13452 {
13455 }
13458 {
13461 }
13462 else
13464 }
13465 }
13467 /* Check if X, a register, is known to contain a value already
13468 truncated to MODE. In this case we can use a subreg to refer to
13469 the truncated value even though in the generic case we would need
13470 an explicit truncation. */
13472 static bool
13474 {
13486 }
13488 /* If X is a hard reg or a subreg record the mode that the register is
13489 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13490 able to turn a truncate into a subreg using this information. Return true
13491 if traversing X is complete. */
13493 static bool
13495 {
13496 machine_mode truncated_mode;
13500 {
13512 }
13513 /* ??? For hard-regs we now record everything. We might be able to
13514 optimize this using last_set_mode. */
13517 else
13524 {
13527 }
13530 }
13532 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13533 the modes they are used in. This can help truning TRUNCATEs into
13534 SUBREGs. */
13536 static void
13538 {
13543 }
13545 /* Scan X for promoted SUBREGs. For each one found,
13546 note what it implies to the registers used in it. */
13548 static void
13550 {
13555 else
13556 {
13562 {
13572 }
13573 }
13574 }
13575 \f
13576 /* Verify that all the registers and memory references mentioned in *LOC are
13577 still valid. *LOC was part of a value set in INSN when label_tick was
13578 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13579 the invalid references with (clobber (const_int 0)) and return 1. This
13580 replacement is useful because we often can get useful information about
13581 the form of a value (e.g., if it was produced by a shift that always
13582 produces -1 or 0) even though we don't know exactly what registers it
13583 was produced from. */
13585 static int
13587 {
13594 {
13600 {
13603 /* If this is a pseudo-register that was only set once and not
13604 live at the beginning of the function, it is always valid. */
13608 && (!REGNO_REG_SET_P
13610 regno)))
13612 {
13616 }
13617 }
13620 }
13621 /* If this is a memory reference, make sure that there were no stores after
13622 it that might have clobbered the value. We don't have alias info, so we
13623 assume any store invalidates it. Moreover, we only have local UIDs, so
13624 we also assume that there were stores in the intervening basic blocks. */
13627 {
13631 }
13634 {
13636 {
13637 /* Check for identical subexpressions. If x contains
13638 identical subexpression we only have to traverse one of
13639 them. */
13641 {
13642 /* Note that at this point x0 has already been checked
13643 and found valid. */
13647 /* If x0 and x1 are identical then x is also valid. */
13651 /* If x1 is identical to a subexpression of x0 then
13652 while checking x0, x1 has already been checked. Thus
13653 it is valid and so as x. */
13658 /* If x0 is identical to a subexpression of x1 then x is
13659 valid iff the rest of x1 is valid. */
13662 return
13666 }
13671 }
13677 }
13679 /* If we haven't found a reason for it to be invalid, it is valid. */
13681 }
13683 /* Get the last value assigned to X, if known. Some registers
13684 in the value may be replaced with (clobber (const_int 0)) if their value
13685 is known longer known reliably. */
13687 static rtx
13689 {
13691 rtx value;
13694 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13695 then convert it to the desired mode. If this is a paradoxical SUBREG,
13696 we cannot predict what values the "extra" bits might have. */
13710 /* If we don't have a value, or if it isn't for this basic block and
13711 it's either a hard register, set more than once, or it's a live
13712 at the beginning of the function, return 0.
13714 Because if it's not live at the beginning of the function then the reg
13715 is always set before being used (is never used without being set).
13716 And, if it's set only once, and it's always set before use, then all
13717 uses must have the same last value, even if it's not from this basic
13718 block. */
13725 || REGNO_REG_SET_P
13729 /* If the value was set in a later insn than the ones we are processing,
13730 we can't use it even if the register was only set once. */
13735 /* If fewer bits were set than what we are asked for now, we cannot use
13736 the value. */
13741 /* If the value has all its registers valid, return it. */
13745 /* Otherwise, make a copy and replace any invalid register with
13746 (clobber (const_int 0)). If that fails for some reason, return 0. */
13753 }
13754 \f
13755 /* Define three variables used for communication between the following
13756 routines. */
13760 rtx reg_dead_reg;
13762 /* Function called via note_stores from reg_dead_at_p.
13764 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13765 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13767 static void
13769 {
13783 }
13785 /* Return nonzero if REG is known to be dead at INSN.
13787 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13788 referencing REG, it is dead. If we hit a SET referencing REG, it is
13789 live. Otherwise, see if it is live or dead at the start of the basic
13790 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13791 must be assumed to be always live. */
13793 static int
13795 {
13796 basic_block block;
13799 /* Set variables for reg_dead_at_p_1. */
13806 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13807 we allow the machine description to decide whether use-and-clobber
13808 patterns are OK. */
13810 {
13814 }
13816 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13817 beginning of basic block. */
13820 {
13822 {
13832 }
13838 }
13840 /* Look at live-in sets for the basic block that we were in. */
13846 }
13847 \f
13848 /* Note hard registers in X that are used. */
13850 static void
13852 {
13858 {
13862 CASE_CONST_ANY:
13867 /* CC0 must die in the insn after it is set, so we don't need to take
13868 special note of it here. */
13873 /* If we are clobbering a MEM, mark any hard registers inside the
13874 address as used. */
13881 /* A hard reg in a wide mode may really be multiple registers.
13882 If so, mark all of them just like the first. */
13884 {
13885 /* None of this applies to the stack, frame or arg pointers. */
13887 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13895 }
13899 {
13900 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13901 the address. */
13913 }
13918 }
13920 /* Recursively scan the operands of this expression. */
13922 {
13926 {
13930 {
13935 }
13936 }
13937 }
13938 }
13939 \f
13940 /* Remove register number REGNO from the dead registers list of INSN.
13942 Return the note used to record the death, if there was one. */
13944 rtx
13946 {
13953 }
13955 /* For each register (hardware or pseudo) used within expression X, if its
13956 death is in an instruction with luid between FROM_LUID (inclusive) and
13957 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13958 list headed by PNOTES.
13960 That said, don't move registers killed by maybe_kill_insn.
13962 This is done when X is being merged by combination into TO_INSN. These
13963 notes will then be distributed as needed. */
13965 static void
13968 {
13974 {
13978 /* If we do not know where the register died, it may still die between
13979 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13981 {
13986 {
13988 {
13992 }
13995 }
13996 }
13998 /* Don't move the register if it gets killed in between from and to. */
14007 {
14010 /* It is possible for the call above to return 0. This can occur
14011 when last_death points to I2 or I1 that we combined with.
14012 In that case make a new note.
14014 We must also check for the case where X is a hard register
14015 and NOTE is a death note for a range of hard registers
14016 including X. In that case, we must put REG_DEAD notes for
14017 the remaining registers in place of NOTE. */
14021 {
14030 }
14032 /* If we didn't find any note, or if we found a REG_DEAD note that
14033 covers only part of the given reg, and we have a multi-reg hard
14034 register, then to be safe we must check for REG_DEAD notes
14035 for each register other than the first. They could have
14036 their own REG_DEAD notes lying around. */
14043 {
14050 else
14056 }
14059 {
14062 }
14063 else
14065 }
14068 }
14071 {
14076 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14077 that accesses one word of a multi-word item, some
14078 piece of everything register in the expression is used by
14079 this insn, so remove any old death. */
14080 /* ??? So why do we test for equality of the sizes? */
14086 {
14089 }
14091 /* If this is some other SUBREG, we know it replaces the entire
14092 value, so use that as the destination. */
14096 /* If this is a MEM, adjust deaths of anything used in the address.
14097 For a REG (the only other possibility), the entire value is
14098 being replaced so the old value is not used in this insn. */
14104 }
14113 {
14115 {
14120 }
14123 }
14124 }
14125 \f
14126 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14127 pattern of an insn. X must be a REG. */
14129 static int
14131 {
14135 {
14137 rtx target;
14144 else
14161 }
14169 }
14170 \f
14171 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14172 as appropriate. I3 and I2 are the insns resulting from the combination
14173 insns including FROM (I2 may be zero).
14175 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14176 not need REG_DEAD notes because they are being substituted for. This
14177 saves searching in the most common cases.
14179 Each note in the list is either ignored or placed on some insns, depending
14180 on the type of note. */
14182 static void
14185 {
14187 rtx tem_note;
14191 {
14196 {
14199 /* Doesn't matter much where we put this, as long as it's somewhere.
14200 It is preferable to keep these notes on branches, which is most
14201 likely to be i3. */
14208 else
14209 {
14212 }
14216 /* These notes must remain with the call or trapping instruction. */
14221 else
14222 {
14228 /* ??? Otherwise assume we've combined things such that we
14229 can now prove that the instructions can't trap. Drop the
14230 note in this case. */
14231 }
14235 /* ??? How to distribute between i3-i1. Assume i3 contains the
14236 entire adjustment. Assert i3 contains at least some adjust. */
14238 {
14240 /* fixup_args_size_notes looks at REG_NORETURN note,
14241 so ensure the note is placed there first. */
14243 {
14247 {
14253 }
14254 }
14256 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14257 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14260 && !ACCUMULATE_OUTGOING_ARGS
14262 }
14270 /* These notes must remain with the call. It should not be
14271 possible for both I2 and I3 to be a call. */
14274 else
14275 {
14278 }
14282 /* Any clobbers for i3 may still exist, and so we must process
14283 REG_UNUSED notes from that insn.
14285 Any clobbers from i2 or i1 can only exist if they were added by
14286 recog_for_combine. In that case, recog_for_combine created the
14287 necessary REG_UNUSED notes. Trying to keep any original
14288 REG_UNUSED notes from these insns can cause incorrect output
14289 if it is for the same register as the original i3 dest.
14290 In that case, we will notice that the register is set in i3,
14291 and then add a REG_UNUSED note for the destination of i3, which
14292 is wrong. However, it is possible to have REG_UNUSED notes from
14293 i2 or i1 for register which were both used and clobbered, so
14294 we keep notes from i2 or i1 if they will turn into REG_DEAD
14295 notes. */
14297 /* If this register is set or clobbered in I3, put the note there
14298 unless there is one already. */
14300 {
14308 }
14309 /* Otherwise, if this register is used by I3, then this register
14310 now dies here, so we must put a REG_DEAD note here unless there
14311 is one already. */
14317 {
14320 }
14322 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14323 but we can't tell which at this point. We must reset any
14324 expectations we had about the value that was previously
14325 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14326 and, if appropriate, restore its previous value, but we
14327 don't have enough information for that at this point. */
14328 else
14329 {
14332 /* Otherwise, if this register is now referenced in i2
14333 then the register used to be modified in one of the
14334 original insns. If it was i3 (say, in an unused
14335 parallel), it's now completely gone, so the note can
14336 be discarded. But if it was modified in i2, i1 or i0
14337 and we still reference it in i2, then we're
14338 referencing the previous value, and since the
14339 register was modified and REG_UNUSED, we know that
14340 the previous value is now dead. So, if we only
14341 reference the register in i2, we change the note to
14342 REG_DEAD, to reflect the previous value. However, if
14343 we're also setting or clobbering the register as
14344 scratch, we know (because the register was not
14345 referenced in i3) that it's unused, just as it was
14346 unused before, and we place the note in i2. */
14349 {
14358 }
14359 }
14366 /* These notes say something about results of an insn. We can
14367 only support them if they used to be on I3 in which case they
14368 remain on I3. Otherwise they are ignored.
14370 If the note refers to an expression that is not a constant, we
14371 must also ignore the note since we cannot tell whether the
14372 equivalence is still true. It might be possible to do
14373 slightly better than this (we only have a problem if I2DEST
14374 or I1DEST is present in the expression), but it doesn't
14375 seem worth the trouble. */
14383 /* These notes say something about how a register is used. They must
14384 be present on any use of the register in I2 or I3. */
14389 {
14392 else
14394 }
14399 /* This can show up in several ways -- either directly in the
14400 pattern, or hidden off in the constant pool with (or without?)
14401 a REG_EQUAL note. */
14402 /* ??? Ignore the without-reg_equal-note problem for now. */
14414 {
14417 else
14419 }
14421 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14422 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14423 there. */
14428 {
14435 }
14441 {
14449 }
14453 /* This note says something about the value of a register prior
14454 to the execution of an insn. It is too much trouble to see
14455 if the note is still correct in all situations. It is better
14456 to simply delete it. */
14460 /* If we replaced the right hand side of FROM_INSN with a
14461 REG_EQUAL note, the original use of the dying register
14462 will not have been combined into I3 and I2. In such cases,
14463 FROM_INSN is guaranteed to be the first of the combined
14464 instructions, so we simply need to search back before
14465 FROM_INSN for the previous use or set of this register,
14466 then alter the notes there appropriately.
14468 If the register is used as an input in I3, it dies there.
14469 Similarly for I2, if it is nonzero and adjacent to I3.
14471 If the register is not used as an input in either I3 or I2
14472 and it is not one of the registers we were supposed to eliminate,
14473 there are two possibilities. We might have a non-adjacent I2
14474 or we might have somehow eliminated an additional register
14475 from a computation. For example, we might have had A & B where
14476 we discover that B will always be zero. In this case we will
14477 eliminate the reference to A.
14479 In both cases, we must search to see if we can find a previous
14480 use of A and put the death note there. */
14486 else
14487 {
14493 {
14494 /* If the new I2 sets the same register that is marked
14495 dead in the note, we do not in general know where to
14496 put the note. One important case we _can_ handle is
14497 when the note comes from I3. */
14500 else
14502 }
14509 && !(i2mod
14511 i2mod_old_rhs)))
14516 }
14519 {
14523 {
14525 {
14529 }
14531 /* If the register is being set at TEM_INSN, see if that is all
14532 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14533 into a REG_UNUSED note instead. Don't delete sets to
14534 global register vars. */
14538 {
14549 ;
14551 /* Verify that it was the set, and not a clobber that
14552 modified the register.
14554 CC0 targets must be careful to maintain setter/user
14555 pairs. If we cannot delete the setter due to side
14556 effects, mark the user with an UNUSED note instead
14557 of deleting it. */
14561 && (!HAVE_cc0
14565 {
14566 /* Move the notes and links of TEM_INSN elsewhere.
14567 This might delete other dead insns recursively.
14568 First set the pattern to something that won't use
14569 any register. */
14588 /* Delete the setter too. */
14590 {
14603 }
14604 }
14605 else
14606 {
14609 /* If there isn't already a REG_UNUSED note, put one
14610 here. Do not place a REG_DEAD note, even if
14611 the register is also used here; that would not
14612 match the algorithm used in lifetime analysis
14613 and can cause the consistency check in the
14614 scheduler to fail. */
14619 }
14620 }
14624 {
14627 /* If we are doing a 3->2 combination, and we have a
14628 register which formerly died in i3 and was not used
14629 by i2, which now no longer dies in i3 and is used in
14630 i2 but does not die in i2, and place is between i2
14631 and i3, then we may need to move a link from place to
14632 i2. */
14634 && from_insn
14637 {
14641 }
14643 }
14647 }
14649 }
14651 /* If the register is set or already dead at PLACE, we needn't do
14652 anything with this note if it is still a REG_DEAD note.
14653 We check here if it is set at all, not if is it totally replaced,
14654 which is what `dead_or_set_p' checks, so also check for it being
14655 set partially. */
14658 {
14664 {
14665 /* Unless the register previously died in PLACE, clear
14666 last_death. [I no longer understand why this is
14667 being done.] */
14671 }
14672 else
14675 /* If this is a death note for a hard reg that is occupying
14676 multiple registers, ensure that we are still using all
14677 parts of the object. If we find a piece of the object
14678 that is unused, we must arrange for an appropriate REG_DEAD
14679 note to be added for it. However, we can't just emit a USE
14680 and tag the note to it, since the register might actually
14681 be dead; so we recourse, and the recursive call then finds
14682 the previous insn that used this register. */
14685 {
14694 {
14697 }
14700 {
14701 /* Put only REG_DEAD notes for pieces that are
14702 not already dead or set. */
14706 {
14713 {
14715 NULL_RTX);
14719 NULL_RTX);
14720 }
14725 {
14727 {
14731 }
14735 {
14738 }
14739 }
14740 }
14743 }
14744 }
14745 }
14749 /* Any other notes should not be present at this point in the
14750 compilation. */
14752 }
14755 {
14759 /* Set added_notes_insn to the earliest insn we added a note to. */
14763 }
14766 {
14769 /* Set added_notes_insn to the earliest insn we added a note to. */
14773 }
14774 }
14775 }
14776 \f
14777 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14778 I3, I2, and I1 to new locations. This is also called to add a link
14779 pointing at I3 when I3's destination is changed. */
14781 static void
14783 {
14787 {
14794 /* If the insn that this link points to is a NOTE, ignore it. */
14803 {
14806 {
14822 }
14825 }
14826 else
14839 /* A LOG_LINK is defined as being placed on the first insn that uses
14840 a register and points to the insn that sets the register. Start
14841 searching at the next insn after the target of the link and stop
14842 when we reach a set of the register or the end of the basic block.
14844 Note that this correctly handles the link that used to point from
14845 I3 to I2. Also note that not much searching is typically done here
14846 since most links don't point very far away. */
14855 {
14859 }
14862 {
14865 }
14869 /* If we found a place to put the link, place it there unless there
14870 is already a link to the same insn as LINK at that point. */
14873 {
14881 {
14885 /* Set added_links_insn to the earliest insn we added a
14886 link to. */
14890 }
14891 }
14892 }
14893 }
14894 \f
14895 /* Check for any register or memory mentioned in EQUIV that is not
14896 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14897 of EXPR where some registers may have been replaced by constants. */
14899 static bool
14901 {
14904 {
14909 }
14911 }
14912 \f
14913 DEBUG_FUNCTION void
14915 {
14916 fprintf
14918 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14920 }
14922 void
14924 {
14925 fprintf
14927 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14929 }
14930 \f
14931 /* Try combining insns through substitution. */
14932 static unsigned int
14934 {
14944 rebuild_jump_labels_after_combine
14947 /* Combining insns may have turned an indirect jump into a
14948 direct jump. Rebuild the JUMP_LABEL fields of jumping
14949 instructions. */
14951 {
14958 }
14962 }
14967 {
14977 };
14980 {
14984 {}
14986 /* opt_pass methods: */
14989 {
14991 }
14997 rtl_opt_pass *
14999 {
15001 }