1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
105 #include "coretypes.h"
112 #include "memmodel.h"
120 #include "cfgbuild.h"
123 #include "print-rtl.h"
125 /* Dump bitmap SET with TITLE and BB INDEX. */
127 lra_dump_bitmap_with_title (const char *title
, bitmap set
, int index
)
132 static const int max_nums_on_line
= 10;
134 if (bitmap_empty_p (set
))
136 fprintf (lra_dump_file
, " %s %d:", title
, index
);
137 fprintf (lra_dump_file
, "\n");
138 count
= max_nums_on_line
+ 1;
139 EXECUTE_IF_SET_IN_BITMAP (set
, 0, i
, bi
)
141 if (count
> max_nums_on_line
)
143 fprintf (lra_dump_file
, "\n ");
146 fprintf (lra_dump_file
, " %4u", i
);
149 fprintf (lra_dump_file
, "\n");
152 /* Hard registers currently not available for allocation. It can
153 changed after some hard registers become not eliminable. */
154 HARD_REG_SET lra_no_alloc_regs
;
156 static int get_new_reg_value (void);
157 static void expand_reg_info (void);
158 static void invalidate_insn_recog_data (int);
159 static int get_insn_freq (rtx_insn
*);
160 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
163 /* Expand all regno related info needed for LRA. */
165 expand_reg_data (int old
)
169 ira_expand_reg_equiv ();
170 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
171 lra_change_class (i
, ALL_REGS
, " Set", true);
174 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
175 or of VOIDmode, use MD_MODE for the new reg. Initialize its
176 register class to RCLASS. Print message about assigning class
177 RCLASS containing new register name TITLE unless it is NULL. Use
178 attributes of ORIGINAL if it is a register. The created register
179 will have unique held value. */
181 lra_create_new_reg_with_unique_value (machine_mode md_mode
, rtx original
,
182 enum reg_class rclass
, const char *title
)
187 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
189 lra_assert (mode
!= VOIDmode
);
190 new_reg
= gen_reg_rtx (mode
);
191 if (original
== NULL_RTX
|| ! REG_P (original
))
193 if (lra_dump_file
!= NULL
)
194 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
198 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
199 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
200 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
201 REG_POINTER (new_reg
) = REG_POINTER (original
);
202 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
203 if (lra_dump_file
!= NULL
)
204 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
205 REGNO (new_reg
), REGNO (original
));
207 if (lra_dump_file
!= NULL
)
210 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
211 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
212 title
, REGNO (new_reg
));
213 fprintf (lra_dump_file
, "\n");
215 expand_reg_data (max_reg_num ());
216 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
220 /* Analogous to the previous function but also inherits value of
223 lra_create_new_reg (machine_mode md_mode
, rtx original
,
224 enum reg_class rclass
, const char *title
)
229 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
230 if (original
!= NULL_RTX
&& REG_P (original
))
231 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
235 /* Set up for REGNO unique hold value. */
237 lra_set_regno_unique_value (int regno
)
239 lra_reg_info
[regno
].val
= get_new_reg_value ();
242 /* Invalidate INSN related info used by LRA. The info should never be
245 lra_invalidate_insn_data (rtx_insn
*insn
)
247 lra_invalidate_insn_regno_info (insn
);
248 invalidate_insn_recog_data (INSN_UID (insn
));
251 /* Mark INSN deleted and invalidate the insn related info used by
254 lra_set_insn_deleted (rtx_insn
*insn
)
256 lra_invalidate_insn_data (insn
);
257 SET_INSN_DELETED (insn
);
260 /* Delete an unneeded INSN and any previous insns who sole purpose is
261 loading data that is dead in INSN. */
263 lra_delete_dead_insn (rtx_insn
*insn
)
265 rtx_insn
*prev
= prev_real_insn (insn
);
268 /* If the previous insn sets a register that dies in our insn,
270 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
271 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
272 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
273 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
274 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
275 lra_delete_dead_insn (prev
);
277 lra_set_insn_deleted (insn
);
280 /* Emit insn x = y + z. Return NULL if we failed to do it.
281 Otherwise, return the insn. We don't use gen_add3_insn as it might
284 emit_add3_insn (rtx x
, rtx y
, rtx z
)
288 last
= get_last_insn ();
290 if (have_addptr3_insn (x
, y
, z
))
292 rtx_insn
*insn
= gen_addptr3_insn (x
, y
, z
);
294 /* If the target provides an "addptr" pattern it hopefully does
295 for a reason. So falling back to the normal add would be
297 lra_assert (insn
!= NULL_RTX
);
302 rtx_insn
*insn
= emit_insn (gen_rtx_SET (x
, gen_rtx_PLUS (GET_MODE (y
),
304 if (recog_memoized (insn
) < 0)
306 delete_insns_since (last
);
312 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
315 emit_add2_insn (rtx x
, rtx y
)
317 rtx_insn
*insn
= emit_add3_insn (x
, x
, y
);
318 if (insn
== NULL_RTX
)
320 insn
= gen_add2_insn (x
, y
);
321 if (insn
!= NULL_RTX
)
327 /* Target checks operands through operand predicates to recognize an
328 insn. We should have a special precaution to generate add insns
329 which are frequent results of elimination.
331 Emit insns for x = y + z. X can be used to store intermediate
332 values and should be not in Y and Z when we use X to store an
333 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
334 + disp] where base and index are registers, disp and scale are
335 constants. Y should contain base if it is present, Z should
336 contain disp if any. index[*scale] can be part of Y or Z. */
338 lra_emit_add (rtx x
, rtx y
, rtx z
)
342 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
345 rtx_insn
*add3_insn
= emit_add3_insn (x
, y
, z
);
346 old
= max_reg_num ();
347 if (add3_insn
!= NULL
)
351 disp
= a2
= NULL_RTX
;
352 if (GET_CODE (y
) == PLUS
)
366 index_scale
= scale
= NULL_RTX
;
367 if (GET_CODE (a1
) == MULT
)
370 index
= XEXP (a1
, 0);
371 scale
= XEXP (a1
, 1);
374 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
377 index
= XEXP (a2
, 0);
378 scale
= XEXP (a2
, 1);
386 if ((base
!= NULL_RTX
&& ! (REG_P (base
) || GET_CODE (base
) == SUBREG
))
387 || (index
!= NULL_RTX
388 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
389 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
390 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
392 /* Probably we have no 3 op add. Last chance is to use 2-op
393 add insn. To succeed, don't move Z to X as an address
394 segment always comes in Y. Otherwise, we might fail when
395 adding the address segment to register. */
396 lra_assert (x
!= y
&& x
!= z
);
397 emit_move_insn (x
, y
);
398 rtx_insn
*insn
= emit_add2_insn (x
, z
);
399 lra_assert (insn
!= NULL_RTX
);
403 if (index_scale
== NULL_RTX
)
405 if (disp
== NULL_RTX
)
407 /* Generate x = index_scale; x = x + base. */
408 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
409 emit_move_insn (x
, index_scale
);
410 rtx_insn
*insn
= emit_add2_insn (x
, base
);
411 lra_assert (insn
!= NULL_RTX
);
413 else if (scale
== NULL_RTX
)
415 /* Try x = base + disp. */
416 lra_assert (base
!= NULL_RTX
);
417 last
= get_last_insn ();
418 rtx_insn
*move_insn
=
419 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
420 if (recog_memoized (move_insn
) < 0)
422 delete_insns_since (last
);
423 /* Generate x = disp; x = x + base. */
424 emit_move_insn (x
, disp
);
425 rtx_insn
*add2_insn
= emit_add2_insn (x
, base
);
426 lra_assert (add2_insn
!= NULL_RTX
);
428 /* Generate x = x + index. */
429 if (index
!= NULL_RTX
)
431 rtx_insn
*insn
= emit_add2_insn (x
, index
);
432 lra_assert (insn
!= NULL_RTX
);
437 /* Try x = index_scale; x = x + disp; x = x + base. */
438 last
= get_last_insn ();
439 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
441 if (recog_memoized (move_insn
) >= 0)
443 rtx_insn
*insn
= emit_add2_insn (x
, disp
);
444 if (insn
!= NULL_RTX
)
446 if (base
== NULL_RTX
)
450 insn
= emit_add2_insn (x
, base
);
451 if (insn
!= NULL_RTX
)
460 delete_insns_since (last
);
461 /* Generate x = disp; x = x + base; x = x + index_scale. */
462 emit_move_insn (x
, disp
);
463 if (base
!= NULL_RTX
)
465 insn
= emit_add2_insn (x
, base
);
466 lra_assert (insn
!= NULL_RTX
);
468 insn
= emit_add2_insn (x
, index_scale
);
469 lra_assert (insn
!= NULL_RTX
);
474 /* Functions emit_... can create pseudos -- so expand the pseudo
476 if (old
!= max_reg_num ())
477 expand_reg_data (old
);
480 /* The number of emitted reload insns so far. */
481 int lra_curr_reload_num
;
483 /* Emit x := y, processing special case when y = u + v or y = u + v *
484 scale + w through emit_add (Y can be an address which is base +
485 index reg * scale + displacement in general case). X may be used
486 as intermediate result therefore it should be not in Y. */
488 lra_emit_move (rtx x
, rtx y
)
492 if (GET_CODE (y
) != PLUS
)
494 if (rtx_equal_p (x
, y
))
496 old
= max_reg_num ();
497 emit_move_insn (x
, y
);
499 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
500 /* Function emit_move can create pseudos -- so expand the pseudo
502 if (old
!= max_reg_num ())
503 expand_reg_data (old
);
506 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
509 /* Update insn operands which are duplication of operands whose
510 numbers are in array of NOPS (with end marker -1). The insn is
511 represented by its LRA internal representation ID. */
513 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
516 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
518 for (i
= 0; i
< static_id
->n_dups
; i
++)
519 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
520 if (static_id
->dup_num
[i
] == nop
)
521 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
526 /* This page contains code dealing with info about registers in the
529 /* Pools for insn reg info. */
530 object_allocator
<lra_insn_reg
> lra_insn_reg_pool ("insn regs");
532 /* Create LRA insn related info about a reference to REGNO in INSN
533 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
534 is reference through subreg (SUBREG_P), flag that is early
535 clobbered in the insn (EARLY_CLOBBER), and reference to the next
536 insn reg info (NEXT). If REGNO can be early clobbered,
537 alternatives in which it can be early clobbered are given by
538 EARLY_CLOBBER_ALTS. */
539 static struct lra_insn_reg
*
540 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
542 bool subreg_p
, bool early_clobber
,
543 alternative_mask early_clobber_alts
,
544 struct lra_insn_reg
*next
)
546 lra_insn_reg
*ir
= lra_insn_reg_pool
.allocate ();
548 ir
->biggest_mode
= mode
;
549 if (NONDEBUG_INSN_P (insn
)
550 && partial_subreg_p (lra_reg_info
[regno
].biggest_mode
, mode
))
551 lra_reg_info
[regno
].biggest_mode
= mode
;
552 ir
->subreg_p
= subreg_p
;
553 ir
->early_clobber
= early_clobber
;
554 ir
->early_clobber_alts
= early_clobber_alts
;
560 /* Free insn reg info list IR. */
562 free_insn_regs (struct lra_insn_reg
*ir
)
564 struct lra_insn_reg
*next_ir
;
566 for (; ir
!= NULL
; ir
= next_ir
)
569 lra_insn_reg_pool
.remove (ir
);
573 /* Finish pool for insn reg info. */
575 finish_insn_regs (void)
577 lra_insn_reg_pool
.release ();
582 /* This page contains code dealing LRA insn info (or in other words
583 LRA internal insn representation). */
585 /* Map INSN_CODE -> the static insn data. This info is valid during
586 all translation unit. */
587 struct lra_static_insn_data
*insn_code_data
[NUM_INSN_CODES
];
589 /* Debug insns are represented as a special insn with one input
590 operand which is RTL expression in var_location. */
592 /* The following data are used as static insn operand data for all
593 debug insns. If structure lra_operand_data is changed, the
594 initializer should be changed too. */
595 static struct lra_operand_data debug_operand_data
=
597 NULL
, /* alternative */
598 0, /* early_clobber_alts */
599 E_VOIDmode
, /* We are not interesting in the operand mode. */
604 /* The following data are used as static insn data for all debug
605 bind insns. If structure lra_static_insn_data is changed, the
606 initializer should be changed too. */
607 static struct lra_static_insn_data debug_bind_static_data
=
610 0, /* Duplication operands #. */
611 -1, /* Commutative operand #. */
612 1, /* Operands #. There is only one operand which is debug RTL
614 0, /* Duplications #. */
615 0, /* Alternatives #. We are not interesting in alternatives
616 because we does not proceed debug_insns for reloads. */
617 NULL
, /* Hard registers referenced in machine description. */
618 NULL
/* Descriptions of operands in alternatives. */
621 /* The following data are used as static insn data for all debug
622 marker insns. If structure lra_static_insn_data is changed, the
623 initializer should be changed too. */
624 static struct lra_static_insn_data debug_marker_static_data
=
627 0, /* Duplication operands #. */
628 -1, /* Commutative operand #. */
629 0, /* Operands #. There isn't any operand. */
630 0, /* Duplications #. */
631 0, /* Alternatives #. We are not interesting in alternatives
632 because we does not proceed debug_insns for reloads. */
633 NULL
, /* Hard registers referenced in machine description. */
634 NULL
/* Descriptions of operands in alternatives. */
637 /* Called once per compiler work to initialize some LRA data related
640 init_insn_code_data_once (void)
642 memset (insn_code_data
, 0, sizeof (insn_code_data
));
645 /* Called once per compiler work to finalize some LRA data related to
648 finish_insn_code_data_once (void)
650 for (unsigned int i
= 0; i
< NUM_INSN_CODES
; i
++)
652 if (insn_code_data
[i
] != NULL
)
653 free (insn_code_data
[i
]);
657 /* Return static insn data, allocate and setup if necessary. Although
658 dup_num is static data (it depends only on icode), to set it up we
659 need to extract insn first. So recog_data should be valid for
660 normal insn (ICODE >= 0) before the call. */
661 static struct lra_static_insn_data
*
662 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
664 struct lra_static_insn_data
*data
;
667 lra_assert (icode
< (int) NUM_INSN_CODES
);
668 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
670 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
671 n_bytes
= sizeof (struct lra_static_insn_data
)
672 + sizeof (struct lra_operand_data
) * nop
673 + sizeof (int) * ndup
;
674 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
675 data
->operand_alternative
= NULL
;
676 data
->n_operands
= nop
;
678 data
->n_alternatives
= nalt
;
679 data
->operand
= ((struct lra_operand_data
*)
680 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
681 data
->dup_num
= ((int *) ((char *) data
->operand
682 + sizeof (struct lra_operand_data
) * nop
));
687 insn_code_data
[icode
] = data
;
688 for (i
= 0; i
< nop
; i
++)
690 data
->operand
[i
].constraint
691 = insn_data
[icode
].operand
[i
].constraint
;
692 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
693 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
694 data
->operand
[i
].is_operator
695 = insn_data
[icode
].operand
[i
].is_operator
;
696 data
->operand
[i
].type
697 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
698 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
700 data
->operand
[i
].is_address
= false;
702 for (i
= 0; i
< ndup
; i
++)
703 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
708 /* The current length of the following array. */
709 int lra_insn_recog_data_len
;
711 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
712 lra_insn_recog_data_t
*lra_insn_recog_data
;
714 /* Initialize LRA data about insns. */
716 init_insn_recog_data (void)
718 lra_insn_recog_data_len
= 0;
719 lra_insn_recog_data
= NULL
;
722 /* Expand, if necessary, LRA data about insns. */
724 check_and_expand_insn_recog_data (int index
)
728 if (lra_insn_recog_data_len
> index
)
730 old
= lra_insn_recog_data_len
;
731 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
732 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
734 lra_insn_recog_data_len
);
735 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
736 lra_insn_recog_data
[i
] = NULL
;
739 /* Finish LRA DATA about insn. */
741 free_insn_recog_data (lra_insn_recog_data_t data
)
743 if (data
->operand_loc
!= NULL
)
744 free (data
->operand_loc
);
745 if (data
->dup_loc
!= NULL
)
746 free (data
->dup_loc
);
747 if (data
->arg_hard_regs
!= NULL
)
748 free (data
->arg_hard_regs
);
749 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
751 if (data
->insn_static_data
->operand_alternative
!= NULL
)
752 free (const_cast <operand_alternative
*>
753 (data
->insn_static_data
->operand_alternative
));
754 free_insn_regs (data
->insn_static_data
->hard_regs
);
755 free (data
->insn_static_data
);
757 free_insn_regs (data
->regs
);
762 /* Pools for copies. */
763 static object_allocator
<lra_copy
> lra_copy_pool ("lra copies");
765 /* Finish LRA data about all insns. */
767 finish_insn_recog_data (void)
770 lra_insn_recog_data_t data
;
772 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
773 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
774 free_insn_recog_data (data
);
776 lra_copy_pool
.release ();
777 lra_insn_reg_pool
.release ();
778 free (lra_insn_recog_data
);
781 /* Setup info about operands in alternatives of LRA DATA of insn. */
783 setup_operand_alternative (lra_insn_recog_data_t data
,
784 const operand_alternative
*op_alt
)
787 int icode
= data
->icode
;
788 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
790 static_data
->commutative
= -1;
791 nop
= static_data
->n_operands
;
792 nalt
= static_data
->n_alternatives
;
793 static_data
->operand_alternative
= op_alt
;
794 for (i
= 0; i
< nop
; i
++)
796 static_data
->operand
[i
].early_clobber_alts
= 0;
797 static_data
->operand
[i
].early_clobber
= false;
798 static_data
->operand
[i
].is_address
= false;
799 if (static_data
->operand
[i
].constraint
[0] == '%')
801 /* We currently only support one commutative pair of operands. */
802 if (static_data
->commutative
< 0)
803 static_data
->commutative
= i
;
805 lra_assert (icode
< 0); /* Asm */
806 /* The last operand should not be marked commutative. */
807 lra_assert (i
!= nop
- 1);
810 for (j
= 0; j
< nalt
; j
++)
811 for (i
= 0; i
< nop
; i
++, op_alt
++)
813 static_data
->operand
[i
].early_clobber
|= op_alt
->earlyclobber
;
814 if (op_alt
->earlyclobber
)
815 static_data
->operand
[i
].early_clobber_alts
|= (alternative_mask
) 1 << j
;
816 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
820 /* Recursively process X and collect info about registers, which are
821 not the insn operands, in X with TYPE (in/out/inout) and flag that
822 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
823 to LIST. X is a part of insn given by DATA. Return the result
825 static struct lra_insn_reg
*
826 collect_non_operand_hard_regs (rtx_insn
*insn
, rtx
*x
,
827 lra_insn_recog_data_t data
,
828 struct lra_insn_reg
*list
,
829 enum op_type type
, bool early_clobber
)
831 int i
, j
, regno
, last
;
834 struct lra_insn_reg
*curr
;
836 enum rtx_code code
= GET_CODE (op
);
837 const char *fmt
= GET_RTX_FORMAT (code
);
839 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
840 if (! data
->insn_static_data
->operand
[i
].is_operator
841 && x
== data
->operand_loc
[i
])
842 /* It is an operand loc. Stop here. */
844 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
845 if (x
== data
->dup_loc
[i
])
846 /* It is a dup loc. Stop here. */
848 mode
= GET_MODE (op
);
852 mode
= wider_subreg_mode (op
);
853 if (read_modify_subreg_p (op
))
855 op
= SUBREG_REG (op
);
856 code
= GET_CODE (op
);
860 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
862 /* Process all regs even unallocatable ones as we need info
863 about all regs for rematerialization pass. */
864 for (last
= end_hard_regno (mode
, regno
); regno
< last
; regno
++)
866 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
867 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
868 && curr
->biggest_mode
== mode
)
870 if (curr
->type
!= type
)
871 curr
->type
= OP_INOUT
;
874 curr
->early_clobber
= true;
875 curr
->early_clobber_alts
= ALL_ALTERNATIVES
;
881 /* This is a new hard regno or the info can not be
882 integrated into the found structure. */
886 /* This clobber is to inform popping floating
888 && ! (FIRST_STACK_REG
<= regno
889 && regno
<= LAST_STACK_REG
));
891 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
893 early_clobber
? ALL_ALTERNATIVES
: 0, list
);
901 list
= collect_non_operand_hard_regs (insn
, &SET_DEST (op
), data
,
902 list
, OP_OUT
, false);
903 list
= collect_non_operand_hard_regs (insn
, &SET_SRC (op
), data
,
907 /* We treat clobber of non-operand hard registers as early clobber. */
908 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 0), data
,
911 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
912 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 0), data
,
913 list
, OP_INOUT
, false);
915 case PRE_MODIFY
: case POST_MODIFY
:
916 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 0), data
,
917 list
, OP_INOUT
, false);
918 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 1), data
,
922 fmt
= GET_RTX_FORMAT (code
);
923 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
926 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, i
), data
,
928 else if (fmt
[i
] == 'E')
929 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
930 list
= collect_non_operand_hard_regs (insn
, &XVECEXP (op
, i
, j
),
931 data
, list
, OP_IN
, false);
937 /* Set up and return info about INSN. Set up the info if it is not set up
939 lra_insn_recog_data_t
940 lra_set_insn_recog_data (rtx_insn
*insn
)
942 lra_insn_recog_data_t data
;
945 unsigned int uid
= INSN_UID (insn
);
946 struct lra_static_insn_data
*insn_static_data
;
948 check_and_expand_insn_recog_data (uid
);
949 if (DEBUG_INSN_P (insn
))
953 icode
= INSN_CODE (insn
);
955 /* It might be a new simple insn which is not recognized yet. */
956 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
958 data
= XNEW (struct lra_insn_recog_data
);
959 lra_insn_recog_data
[uid
] = data
;
961 data
->used_insn_alternative
= -1;
964 if (DEBUG_INSN_P (insn
))
966 data
->dup_loc
= NULL
;
967 data
->arg_hard_regs
= NULL
;
968 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
969 if (DEBUG_BIND_INSN_P (insn
))
971 data
->insn_static_data
= &debug_bind_static_data
;
972 data
->operand_loc
= XNEWVEC (rtx
*, 1);
973 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
975 else if (DEBUG_MARKER_INSN_P (insn
))
977 data
->insn_static_data
= &debug_marker_static_data
;
978 data
->operand_loc
= NULL
;
985 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
986 const char *constraints
[MAX_RECOG_OPERANDS
];
988 nop
= asm_noperands (PATTERN (insn
));
989 data
->operand_loc
= data
->dup_loc
= NULL
;
993 /* It is a special insn like USE or CLOBBER. We should
994 recognize any regular insn otherwise LRA can do nothing
996 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
997 || GET_CODE (PATTERN (insn
)) == CLOBBER
998 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
999 data
->insn_static_data
= insn_static_data
1000 = get_static_insn_data (-1, 0, 0, nalt
);
1004 /* expand_asm_operands makes sure there aren't too many
1006 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
1008 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
1009 /* Now get the operand values and constraints out of the
1011 decode_asm_operands (PATTERN (insn
), NULL
,
1013 constraints
, operand_mode
, NULL
);
1016 const char *p
= recog_data
.constraints
[0];
1018 for (p
= constraints
[0]; *p
; p
++)
1021 data
->insn_static_data
= insn_static_data
1022 = get_static_insn_data (-1, nop
, 0, nalt
);
1023 for (i
= 0; i
< nop
; i
++)
1025 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1026 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1027 insn_static_data
->operand
[i
].strict_low
= false;
1028 insn_static_data
->operand
[i
].is_operator
= false;
1029 insn_static_data
->operand
[i
].is_address
= false;
1032 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1033 insn_static_data
->operand
[i
].type
1034 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1035 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1037 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
1040 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
1042 preprocess_constraints (nop
, nalt
, constraints
, op_alt
);
1043 setup_operand_alternative (data
, op_alt
);
1048 insn_extract (insn
);
1049 data
->insn_static_data
= insn_static_data
1050 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1051 insn_data
[icode
].n_dups
,
1052 insn_data
[icode
].n_alternatives
);
1053 n
= insn_static_data
->n_operands
;
1058 locs
= XNEWVEC (rtx
*, n
);
1059 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1061 data
->operand_loc
= locs
;
1062 n
= insn_static_data
->n_dups
;
1067 locs
= XNEWVEC (rtx
*, n
);
1068 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1070 data
->dup_loc
= locs
;
1071 data
->preferred_alternatives
= get_preferred_alternatives (insn
);
1072 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1073 if (!insn_static_data
->operand_alternative
)
1074 setup_operand_alternative (data
, op_alt
);
1075 else if (op_alt
!= insn_static_data
->operand_alternative
)
1076 insn_static_data
->operand_alternative
= op_alt
;
1078 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1079 insn_static_data
->hard_regs
= NULL
;
1081 insn_static_data
->hard_regs
1082 = collect_non_operand_hard_regs (insn
, &PATTERN (insn
), data
,
1083 NULL
, OP_IN
, false);
1084 data
->arg_hard_regs
= NULL
;
1089 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1092 /* Finding implicit hard register usage. We believe it will be
1093 not changed whatever transformations are used. Call insns
1094 are such example. */
1095 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1097 link
= XEXP (link
, 1))
1098 if (((use_p
= GET_CODE (XEXP (link
, 0)) == USE
)
1099 || GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1100 && REG_P (XEXP (XEXP (link
, 0), 0)))
1102 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1103 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1104 /* It is an argument register. */
1105 for (i
= REG_NREGS (XEXP (XEXP (link
, 0), 0)) - 1; i
>= 0; i
--)
1106 arg_hard_regs
[n_hard_regs
++]
1107 = regno
+ i
+ (use_p
? 0 : FIRST_PSEUDO_REGISTER
);
1109 if (n_hard_regs
!= 0)
1111 arg_hard_regs
[n_hard_regs
++] = -1;
1112 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1113 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1114 sizeof (int) * n_hard_regs
);
1117 /* Some output operand can be recognized only from the context not
1118 from the constraints which are empty in this case. Call insn may
1119 contain a hard register in set destination with empty constraint
1120 and extract_insn treats them as an input. */
1121 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1125 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1127 /* ??? Should we treat 'X' the same way. It looks to me that
1128 'X' means anything and empty constraint means we do not
1130 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1131 || operand
->is_operator
)
1133 pat
= PATTERN (insn
);
1134 if (GET_CODE (pat
) == SET
)
1136 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1139 else if (GET_CODE (pat
) == PARALLEL
)
1141 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1143 set
= XVECEXP (PATTERN (insn
), 0, j
);
1144 if (GET_CODE (set
) == SET
1145 && &SET_DEST (set
) == data
->operand_loc
[i
])
1153 operand
->type
= OP_OUT
;
1158 /* Return info about insn give by UID. The info should be already set
1160 static lra_insn_recog_data_t
1161 get_insn_recog_data_by_uid (int uid
)
1163 lra_insn_recog_data_t data
;
1165 data
= lra_insn_recog_data
[uid
];
1166 lra_assert (data
!= NULL
);
1170 /* Invalidate all info about insn given by its UID. */
1172 invalidate_insn_recog_data (int uid
)
1174 lra_insn_recog_data_t data
;
1176 data
= lra_insn_recog_data
[uid
];
1177 lra_assert (data
!= NULL
);
1178 free_insn_recog_data (data
);
1179 lra_insn_recog_data
[uid
] = NULL
;
1182 /* Update all the insn info about INSN. It is usually called when
1183 something in the insn was changed. Return the updated info. */
1184 lra_insn_recog_data_t
1185 lra_update_insn_recog_data (rtx_insn
*insn
)
1187 lra_insn_recog_data_t data
;
1189 unsigned int uid
= INSN_UID (insn
);
1190 struct lra_static_insn_data
*insn_static_data
;
1191 poly_int64 sp_offset
= 0;
1193 check_and_expand_insn_recog_data (uid
);
1194 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1195 && data
->icode
!= INSN_CODE (insn
))
1197 sp_offset
= data
->sp_offset
;
1198 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1199 invalidate_insn_recog_data (uid
);
1204 data
= lra_get_insn_recog_data (insn
);
1205 /* Initiate or restore SP offset. */
1206 data
->sp_offset
= sp_offset
;
1209 insn_static_data
= data
->insn_static_data
;
1210 data
->used_insn_alternative
= -1;
1211 if (DEBUG_INSN_P (insn
))
1213 if (data
->icode
< 0)
1216 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1217 const char *constraints
[MAX_RECOG_OPERANDS
];
1219 nop
= asm_noperands (PATTERN (insn
));
1222 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1223 /* Now get the operand values and constraints out of the
1225 decode_asm_operands (PATTERN (insn
), NULL
,
1227 constraints
, operand_mode
, NULL
);
1230 for (int i
= 0; i
< nop
; i
++)
1232 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1233 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1234 && ! insn_static_data
->operand
[i
].is_operator
);
1238 for (int i
= 0; i
< insn_static_data
->n_operands
; i
++)
1240 (insn_static_data
->operand
[i
].type
1241 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1242 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1247 insn_extract (insn
);
1248 n
= insn_static_data
->n_operands
;
1250 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1251 n
= insn_static_data
->n_dups
;
1253 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1254 lra_assert (check_bool_attrs (insn
));
1259 /* Set up that INSN is using alternative ALT now. */
1261 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1263 lra_insn_recog_data_t data
;
1265 data
= lra_get_insn_recog_data (insn
);
1266 data
->used_insn_alternative
= alt
;
1269 /* Set up that insn with UID is using alternative ALT now. The insn
1270 info should be already set up. */
1272 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1274 lra_insn_recog_data_t data
;
1276 check_and_expand_insn_recog_data (uid
);
1277 data
= lra_insn_recog_data
[uid
];
1278 lra_assert (data
!= NULL
);
1279 data
->used_insn_alternative
= alt
;
1284 /* This page contains code dealing with common register info and
1287 /* The size of the following array. */
1288 static int reg_info_size
;
1289 /* Common info about each register. */
1290 struct lra_reg
*lra_reg_info
;
1292 /* Last register value. */
1293 static int last_reg_value
;
1295 /* Return new register value. */
1297 get_new_reg_value (void)
1299 return ++last_reg_value
;
1302 /* Vec referring to pseudo copies. */
1303 static vec
<lra_copy_t
> copy_vec
;
1305 /* Initialize I-th element of lra_reg_info. */
1307 initialize_lra_reg_info_element (int i
)
1309 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1311 lra_reg_info
[i
].no_stack_p
= false;
1313 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1314 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1315 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1316 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1317 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1318 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1319 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1320 lra_reg_info
[i
].live_ranges
= NULL
;
1321 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1322 lra_reg_info
[i
].last_reload
= 0;
1323 lra_reg_info
[i
].restore_rtx
= NULL_RTX
;
1324 lra_reg_info
[i
].val
= get_new_reg_value ();
1325 lra_reg_info
[i
].offset
= 0;
1326 lra_reg_info
[i
].copies
= NULL
;
1329 /* Initialize common reg info and copies. */
1331 init_reg_info (void)
1336 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1337 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1338 for (i
= 0; i
< reg_info_size
; i
++)
1339 initialize_lra_reg_info_element (i
);
1340 copy_vec
.truncate (0);
1344 /* Finish common reg info and copies. */
1346 finish_reg_info (void)
1350 for (i
= 0; i
< reg_info_size
; i
++)
1351 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1352 free (lra_reg_info
);
1356 /* Expand common reg info if it is necessary. */
1358 expand_reg_info (void)
1360 int i
, old
= reg_info_size
;
1362 if (reg_info_size
> max_reg_num ())
1364 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1365 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1366 for (i
= old
; i
< reg_info_size
; i
++)
1367 initialize_lra_reg_info_element (i
);
1370 /* Free all copies. */
1372 lra_free_copies (void)
1376 while (copy_vec
.length () != 0)
1378 cp
= copy_vec
.pop ();
1379 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1380 lra_copy_pool
.remove (cp
);
1384 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1385 frequency is FREQ. */
1387 lra_create_copy (int regno1
, int regno2
, int freq
)
1392 lra_assert (regno1
!= regno2
);
1393 regno1_dest_p
= true;
1394 if (regno1
> regno2
)
1396 std::swap (regno1
, regno2
);
1397 regno1_dest_p
= false;
1399 cp
= lra_copy_pool
.allocate ();
1400 copy_vec
.safe_push (cp
);
1401 cp
->regno1_dest_p
= regno1_dest_p
;
1403 cp
->regno1
= regno1
;
1404 cp
->regno2
= regno2
;
1405 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1406 lra_reg_info
[regno1
].copies
= cp
;
1407 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1408 lra_reg_info
[regno2
].copies
= cp
;
1409 if (lra_dump_file
!= NULL
)
1410 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1411 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1414 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1417 lra_get_copy (int n
)
1419 if (n
>= (int) copy_vec
.length ())
1426 /* This page contains code dealing with info about registers in
1429 /* Process X of INSN recursively and add info (operand type is
1430 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1431 about registers in X to the insn DATA. If X can be early clobbered,
1432 alternatives in which it can be early clobbered are given by
1433 EARLY_CLOBBER_ALTS. */
1435 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
,
1437 enum op_type type
, bool early_clobber
,
1438 alternative_mask early_clobber_alts
)
1445 struct lra_insn_reg
*curr
;
1447 code
= GET_CODE (x
);
1448 mode
= GET_MODE (x
);
1450 if (GET_CODE (x
) == SUBREG
)
1452 mode
= wider_subreg_mode (x
);
1453 if (read_modify_subreg_p (x
))
1456 code
= GET_CODE (x
);
1461 /* Process all regs even unallocatable ones as we need info about
1462 all regs for rematerialization pass. */
1464 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, INSN_UID (insn
)))
1466 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1467 early_clobber
, early_clobber_alts
,
1473 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1474 if (curr
->regno
== regno
)
1476 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1477 /* The info can not be integrated into the found
1479 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1480 subreg_p
, early_clobber
,
1481 early_clobber_alts
, data
->regs
);
1484 if (curr
->type
!= type
)
1485 curr
->type
= OP_INOUT
;
1486 if (curr
->early_clobber
!= early_clobber
)
1487 curr
->early_clobber
= true;
1488 curr
->early_clobber_alts
|= early_clobber_alts
;
1499 add_regs_to_insn_regno_info (data
, SET_DEST (x
), insn
, OP_OUT
, false, 0);
1500 add_regs_to_insn_regno_info (data
, SET_SRC (x
), insn
, OP_IN
, false, 0);
1503 /* We treat clobber of non-operand hard registers as early
1505 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), insn
, OP_OUT
,
1506 true, ALL_ALTERNATIVES
);
1508 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1509 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), insn
, OP_INOUT
, false, 0);
1511 case PRE_MODIFY
: case POST_MODIFY
:
1512 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), insn
, OP_INOUT
, false, 0);
1513 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), insn
, OP_IN
, false, 0);
1516 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1517 /* Some targets place small structures in registers for return
1518 values of functions, and those registers are wrapped in
1519 PARALLEL that we may see as the destination of a SET. Here
1522 (call_insn 13 12 14 2 (set (parallel:BLK [
1523 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1525 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1526 (const_int 8 [0x8]))
1528 (call (mem:QI (symbol_ref:DI (... */
1530 fmt
= GET_RTX_FORMAT (code
);
1531 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1534 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), insn
, type
, false, 0);
1535 else if (fmt
[i
] == 'E')
1537 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1538 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), insn
,
1545 /* Return execution frequency of INSN. */
1547 get_insn_freq (rtx_insn
*insn
)
1549 basic_block bb
= BLOCK_FOR_INSN (insn
);
1551 gcc_checking_assert (bb
!= NULL
);
1552 return REG_FREQ_FROM_BB (bb
);
1555 /* Invalidate all reg info of INSN with DATA and execution frequency
1556 FREQ. Update common info about the invalidated registers. */
1558 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1564 struct lra_insn_reg
*ir
, *next_ir
;
1566 uid
= INSN_UID (insn
);
1567 debug_p
= DEBUG_INSN_P (insn
);
1568 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1572 lra_insn_reg_pool
.remove (ir
);
1573 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1574 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1576 lra_reg_info
[i
].nrefs
--;
1577 lra_reg_info
[i
].freq
-= freq
;
1578 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1584 /* Invalidate all reg info of INSN. Update common info about the
1585 invalidated registers. */
1587 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1589 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1590 get_insn_freq (insn
));
1593 /* Update common reg info from reg info of insn given by its DATA and
1594 execution frequency FREQ. */
1596 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1599 struct lra_insn_reg
*ir
;
1601 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1602 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1604 lra_reg_info
[i
].nrefs
++;
1605 lra_reg_info
[i
].freq
+= freq
;
1609 /* Set up insn reg info of INSN. Update common reg info from reg info
1612 lra_update_insn_regno_info (rtx_insn
*insn
)
1615 lra_insn_recog_data_t data
;
1616 struct lra_static_insn_data
*static_data
;
1620 if (! INSN_P (insn
))
1622 data
= lra_get_insn_recog_data (insn
);
1623 static_data
= data
->insn_static_data
;
1624 freq
= NONDEBUG_INSN_P (insn
) ? get_insn_freq (insn
) : 0;
1625 invalidate_insn_data_regno_info (data
, insn
, freq
);
1626 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1627 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], insn
,
1628 static_data
->operand
[i
].type
,
1629 static_data
->operand
[i
].early_clobber
,
1630 static_data
->operand
[i
].early_clobber_alts
);
1631 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1632 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), insn
,
1633 code
== USE
? OP_IN
: OP_OUT
, false, 0);
1635 /* On some targets call insns can refer to pseudos in memory in
1636 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1637 consider their occurrences in calls for different
1638 transformations (e.g. inheritance) with given pseudos. */
1639 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1641 link
= XEXP (link
, 1))
1642 if (((code
= GET_CODE (XEXP (link
, 0))) == USE
|| code
== CLOBBER
)
1643 && MEM_P (XEXP (XEXP (link
, 0), 0)))
1644 add_regs_to_insn_regno_info (data
, XEXP (XEXP (link
, 0), 0), insn
,
1645 code
== USE
? OP_IN
: OP_OUT
, false, 0);
1646 if (NONDEBUG_INSN_P (insn
))
1647 setup_insn_reg_info (data
, freq
);
1650 /* Return reg info of insn given by it UID. */
1651 struct lra_insn_reg
*
1652 lra_get_insn_regs (int uid
)
1654 lra_insn_recog_data_t data
;
1656 data
= get_insn_recog_data_by_uid (uid
);
1662 /* Recursive hash function for RTL X. */
1664 lra_rtx_hash (rtx x
)
1674 code
= GET_CODE (x
);
1675 val
+= (int) code
+ 4095;
1677 /* Some RTL can be compared nonrecursively. */
1681 return val
+ REGNO (x
);
1684 return iterative_hash_object (XEXP (x
, 0), val
);
1687 return iterative_hash_object (XSTR (x
, 0), val
);
1699 /* Hash the elements. */
1700 fmt
= GET_RTX_FORMAT (code
);
1701 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1706 val
+= XWINT (x
, i
);
1716 val
+= XVECLEN (x
, i
);
1718 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1719 val
+= lra_rtx_hash (XVECEXP (x
, i
, j
));
1723 val
+= lra_rtx_hash (XEXP (x
, i
));
1728 val
+= htab_hash_string (XSTR (x
, i
));
1736 /* It is believed that rtx's at this level will never
1737 contain anything but integers and other rtx's, except for
1738 within LABEL_REFs and SYMBOL_REFs. */
1748 /* This page contains code dealing with stack of the insns which
1749 should be processed by the next constraint pass. */
1751 /* Bitmap used to put an insn on the stack only in one exemplar. */
1752 static sbitmap lra_constraint_insn_stack_bitmap
;
1754 /* The stack itself. */
1755 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1757 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1758 info for INSN, otherwise only update it if INSN is not already on the
1761 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1763 unsigned int uid
= INSN_UID (insn
);
1765 lra_update_insn_regno_info (insn
);
1766 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1767 lra_constraint_insn_stack_bitmap
=
1768 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1769 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1771 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1772 if (! always_update
)
1773 lra_update_insn_regno_info (insn
);
1774 lra_constraint_insn_stack
.safe_push (insn
);
1777 /* Put INSN on the stack. */
1779 lra_push_insn (rtx_insn
*insn
)
1781 lra_push_insn_1 (insn
, false);
1784 /* Put INSN on the stack and update its reg info. */
1786 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1788 lra_push_insn_1 (insn
, true);
1791 /* Put insn with UID on the stack. */
1793 lra_push_insn_by_uid (unsigned int uid
)
1795 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1798 /* Take the last-inserted insns off the stack and return it. */
1802 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1803 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1807 /* Return the current size of the insn stack. */
1809 lra_insn_stack_length (void)
1811 return lra_constraint_insn_stack
.length ();
1814 /* Push insns FROM to TO (excluding it) going in reverse order. */
1816 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1820 if (from
== NULL_RTX
)
1822 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1824 lra_push_insn (insn
);
1827 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1828 taken from the next BB insn after LAST or zero if there in such
1831 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1833 rtx_insn
*before
= next_nonnote_nondebug_insn_bb (last
);
1834 poly_int64 offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1835 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1837 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1838 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1841 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1842 insns onto the stack. Print about emitting the insns with
1845 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1850 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1852 if (lra_dump_file
!= NULL
)
1854 dump_insn_slim (lra_dump_file
, insn
);
1855 if (before
!= NULL_RTX
)
1857 fprintf (lra_dump_file
," %s before:\n", title
);
1858 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1860 if (after
!= NULL_RTX
)
1862 fprintf (lra_dump_file
, " %s after:\n", title
);
1863 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1865 fprintf (lra_dump_file
, "\n");
1867 if (before
!= NULL_RTX
)
1869 if (cfun
->can_throw_non_call_exceptions
)
1870 copy_reg_eh_region_note_forward (insn
, before
, NULL
);
1871 emit_insn_before (before
, insn
);
1872 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1873 setup_sp_offset (before
, PREV_INSN (insn
));
1875 if (after
!= NULL_RTX
)
1877 if (cfun
->can_throw_non_call_exceptions
)
1878 copy_reg_eh_region_note_forward (insn
, after
, NULL
);
1879 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1881 emit_insn_after (after
, insn
);
1882 push_insns (last
, insn
);
1883 setup_sp_offset (after
, last
);
1885 if (cfun
->can_throw_non_call_exceptions
)
1887 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
1888 if (note
&& !insn_could_throw_p (insn
))
1889 remove_note (insn
, note
);
1894 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1895 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1896 DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any
1899 lra_substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
, bool subreg_p
,
1903 bool result
= false;
1911 code
= GET_CODE (x
);
1912 if (code
== SUBREG
&& subreg_p
)
1914 rtx subst
, inner
= SUBREG_REG (x
);
1915 /* Transform subreg of constant while we still have inner mode
1916 of the subreg. The subreg internal should not be an insn
1918 if (REG_P (inner
) && (int) REGNO (inner
) == old_regno
1919 && CONSTANT_P (new_reg
)
1920 && (subst
= simplify_subreg (GET_MODE (x
), new_reg
, GET_MODE (inner
),
1921 SUBREG_BYTE (x
))) != NULL_RTX
)
1928 else if (code
== REG
&& (int) REGNO (x
) == old_regno
)
1930 machine_mode mode
= GET_MODE (x
);
1931 machine_mode inner_mode
= GET_MODE (new_reg
);
1933 if (mode
!= inner_mode
1934 && ! (CONST_INT_P (new_reg
) && SCALAR_INT_MODE_P (mode
)))
1936 poly_uint64 offset
= 0;
1937 if (partial_subreg_p (mode
, inner_mode
)
1938 && SCALAR_INT_MODE_P (inner_mode
))
1939 offset
= subreg_lowpart_offset (mode
, inner_mode
);
1941 new_reg
= gen_rtx_raw_SUBREG (mode
, new_reg
, offset
);
1943 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, offset
);
1949 /* Scan all the operand sub-expressions. */
1950 fmt
= GET_RTX_FORMAT (code
);
1951 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1955 if (lra_substitute_pseudo (&XEXP (x
, i
), old_regno
,
1956 new_reg
, subreg_p
, debug_p
))
1959 else if (fmt
[i
] == 'E')
1961 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1962 if (lra_substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
,
1963 new_reg
, subreg_p
, debug_p
))
1970 /* Call lra_substitute_pseudo within an insn. Try to simplify subreg
1971 of constant if SUBREG_P. This won't update the insn ptr, just the
1972 contents of the insn. */
1974 lra_substitute_pseudo_within_insn (rtx_insn
*insn
, int old_regno
,
1975 rtx new_reg
, bool subreg_p
)
1978 return lra_substitute_pseudo (&loc
, old_regno
, new_reg
, subreg_p
,
1979 DEBUG_INSN_P (insn
));
1984 /* This page contains code dealing with scratches (changing them onto
1985 pseudos and restoring them from the pseudos).
1987 We change scratches into pseudos at the beginning of LRA to
1988 simplify dealing with them (conflicts, hard register assignments).
1990 If the pseudo denoting scratch was spilled it means that we do need
1991 a hard register for it. Such pseudos are transformed back to
1992 scratches at the end of LRA. */
1994 /* Description of location of a former scratch operand. */
1997 rtx_insn
*insn
; /* Insn where the scratch was. */
1998 int nop
; /* Number of the operand which was a scratch. */
2001 typedef struct sloc
*sloc_t
;
2003 /* Locations of the former scratches. */
2004 static vec
<sloc_t
> scratches
;
2006 /* Bitmap of scratch regnos. */
2007 static bitmap_head scratch_bitmap
;
2009 /* Bitmap of scratch operands. */
2010 static bitmap_head scratch_operand_bitmap
;
2012 /* Return true if pseudo REGNO is made of SCRATCH. */
2014 lra_former_scratch_p (int regno
)
2016 return bitmap_bit_p (&scratch_bitmap
, regno
);
2019 /* Return true if the operand NOP of INSN is a former scratch. */
2021 lra_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
2023 return bitmap_bit_p (&scratch_operand_bitmap
,
2024 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
2027 /* Register operand NOP in INSN as a former scratch. It will be
2028 changed to scratch back, if it is necessary, at the LRA end. */
2030 lra_register_new_scratch_op (rtx_insn
*insn
, int nop
)
2032 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
2033 rtx op
= *id
->operand_loc
[nop
];
2034 sloc_t loc
= XNEW (struct sloc
);
2035 lra_assert (REG_P (op
));
2038 scratches
.safe_push (loc
);
2039 bitmap_set_bit (&scratch_bitmap
, REGNO (op
));
2040 bitmap_set_bit (&scratch_operand_bitmap
,
2041 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
);
2042 add_reg_note (insn
, REG_UNUSED
, op
);
2045 /* Change scratches onto pseudos and save their location. */
2047 remove_scratches (void)
2050 bool insn_changed_p
;
2054 lra_insn_recog_data_t id
;
2055 struct lra_static_insn_data
*static_id
;
2057 scratches
.create (get_max_uid ());
2058 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
2059 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
2060 FOR_EACH_BB_FN (bb
, cfun
)
2061 FOR_BB_INSNS (bb
, insn
)
2064 id
= lra_get_insn_recog_data (insn
);
2065 static_id
= id
->insn_static_data
;
2066 insn_changed_p
= false;
2067 for (i
= 0; i
< static_id
->n_operands
; i
++)
2068 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
2069 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
2071 insn_changed_p
= true;
2072 *id
->operand_loc
[i
] = reg
2073 = lra_create_new_reg (static_id
->operand
[i
].mode
,
2074 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
2075 lra_register_new_scratch_op (insn
, i
);
2076 if (lra_dump_file
!= NULL
)
2077 fprintf (lra_dump_file
,
2078 "Removing SCRATCH in insn #%u (nop %d)\n",
2079 INSN_UID (insn
), i
);
2082 /* Because we might use DF right after caller-saves sub-pass
2083 we need to keep DF info up to date. */
2084 df_insn_rescan (insn
);
2088 /* Changes pseudos created by function remove_scratches onto scratches. */
2090 restore_scratches (void)
2095 rtx_insn
*last
= NULL
;
2096 lra_insn_recog_data_t id
= NULL
;
2098 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2100 /* Ignore already deleted insns. */
2101 if (NOTE_P (loc
->insn
)
2102 && NOTE_KIND (loc
->insn
) == NOTE_INSN_DELETED
)
2104 if (last
!= loc
->insn
)
2107 id
= lra_get_insn_recog_data (last
);
2109 if (REG_P (*id
->operand_loc
[loc
->nop
])
2110 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
2111 >= FIRST_PSEUDO_REGISTER
)
2112 && lra_get_regno_hard_regno (regno
) < 0)
2114 /* It should be only case when scratch register with chosen
2115 constraint 'X' did not get memory or hard register. */
2116 lra_assert (lra_former_scratch_p (regno
));
2117 *id
->operand_loc
[loc
->nop
]
2118 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
2119 lra_update_dup (id
, loc
->nop
);
2120 if (lra_dump_file
!= NULL
)
2121 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
2122 INSN_UID (loc
->insn
), loc
->nop
);
2125 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2127 scratches
.release ();
2128 bitmap_clear (&scratch_bitmap
);
2129 bitmap_clear (&scratch_operand_bitmap
);
2134 /* Function checks RTL for correctness. If FINAL_P is true, it is
2135 done at the end of LRA and the check is more rigorous. */
2137 check_rtl (bool final_p
)
2142 lra_assert (! final_p
|| reload_completed
);
2143 FOR_EACH_BB_FN (bb
, cfun
)
2144 FOR_BB_INSNS (bb
, insn
)
2145 if (NONDEBUG_INSN_P (insn
)
2146 && GET_CODE (PATTERN (insn
)) != USE
2147 && GET_CODE (PATTERN (insn
)) != CLOBBER
2148 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2152 extract_constrain_insn (insn
);
2155 /* LRA code is based on assumption that all addresses can be
2156 correctly decomposed. LRA can generate reloads for
2157 decomposable addresses. The decomposition code checks the
2158 correctness of the addresses. So we don't need to check
2159 the addresses here. Don't call insn_invalid_p here, it can
2160 change the code at this stage. */
2161 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
2162 fatal_insn_not_found (insn
);
2166 /* Determine if the current function has an exception receiver block
2167 that reaches the exit block via non-exceptional edges */
2169 has_nonexceptional_receiver (void)
2173 basic_block
*tos
, *worklist
, bb
;
2175 /* If we're not optimizing, then just err on the safe side. */
2179 /* First determine which blocks can reach exit via normal paths. */
2180 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2182 FOR_EACH_BB_FN (bb
, cfun
)
2183 bb
->flags
&= ~BB_REACHABLE
;
2185 /* Place the exit block on our worklist. */
2186 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2187 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2189 /* Iterate: find everything reachable from what we've already seen. */
2190 while (tos
!= worklist
)
2194 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2195 if (e
->flags
& EDGE_ABNORMAL
)
2202 basic_block src
= e
->src
;
2204 if (!(src
->flags
& BB_REACHABLE
))
2206 src
->flags
|= BB_REACHABLE
;
2212 /* No exceptional block reached exit unexceptionally. */
2217 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2219 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
2221 enum rtx_code code
= GET_CODE (x
);
2225 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2227 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2231 /* Scan all X sub-expressions. */
2232 fmt
= GET_RTX_FORMAT (code
);
2233 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2236 add_auto_inc_notes (insn
, XEXP (x
, i
));
2237 else if (fmt
[i
] == 'E')
2238 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2239 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2244 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2245 We change pseudos by hard registers without notification of DF and
2246 that can make the notes obsolete. DF-infrastructure does not deal
2247 with REG_INC notes -- so we should regenerate them here. */
2249 update_inc_notes (void)
2255 FOR_EACH_BB_FN (bb
, cfun
)
2256 FOR_BB_INSNS (bb
, insn
)
2257 if (NONDEBUG_INSN_P (insn
))
2259 pnote
= ®_NOTES (insn
);
2262 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2263 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2264 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2265 *pnote
= XEXP (*pnote
, 1);
2267 pnote
= &XEXP (*pnote
, 1);
2271 add_auto_inc_notes (insn
, PATTERN (insn
));
2275 /* Set to 1 while in lra. */
2276 int lra_in_progress
;
2278 /* Start of pseudo regnos before the LRA. */
2279 int lra_new_regno_start
;
2281 /* Start of reload pseudo regnos before the new spill pass. */
2282 int lra_constraint_new_regno_start
;
2284 /* Avoid spilling pseudos with regno more than the following value if
2286 int lra_bad_spill_regno_start
;
2288 /* Inheritance pseudo regnos before the new spill pass. */
2289 bitmap_head lra_inheritance_pseudos
;
2291 /* Split regnos before the new spill pass. */
2292 bitmap_head lra_split_regs
;
2294 /* Reload pseudo regnos before the new assignment pass which still can
2295 be spilled after the assignment pass as memory is also accepted in
2296 insns for the reload pseudos. */
2297 bitmap_head lra_optional_reload_pseudos
;
2299 /* Pseudo regnos used for subreg reloads before the new assignment
2300 pass. Such pseudos still can be spilled after the assignment
2302 bitmap_head lra_subreg_reload_pseudos
;
2304 /* File used for output of LRA debug information. */
2305 FILE *lra_dump_file
;
2307 /* True if we should try spill into registers of different classes
2308 instead of memory. */
2309 bool lra_reg_spill_p
;
2311 /* Set up value LRA_REG_SPILL_P. */
2313 setup_reg_spill_flag (void)
2317 if (targetm
.spill_class
!= NULL
)
2318 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2319 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2320 if (targetm
.spill_class ((enum reg_class
) cl
,
2321 (machine_mode
) mode
) != NO_REGS
)
2323 lra_reg_spill_p
= true;
2326 lra_reg_spill_p
= false;
2329 /* True if the current function is too big to use regular algorithms
2330 in LRA. In other words, we should use simpler and faster algorithms
2331 in LRA. It also means we should not worry about generation code
2332 for caller saves. The value is set up in IRA. */
2335 /* Major LRA entry function. F is a file should be used to dump LRA
2341 bool live_p
, inserted_p
;
2345 timevar_push (TV_LRA
);
2347 /* Make sure that the last insn is a note. Some subsequent passes
2349 emit_note (NOTE_INSN_DELETED
);
2351 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2356 init_insn_recog_data ();
2358 /* Some quick check on RTL generated by previous passes. */
2362 lra_in_progress
= 1;
2364 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2365 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2366 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2367 lra_rematerialization_iter
= 0;
2369 setup_reg_spill_flag ();
2371 /* Function remove_scratches can creates new pseudos for clobbers --
2372 so set up lra_constraint_new_regno_start before its call to
2373 permit changing reg classes for pseudos created by this
2375 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2376 lra_bad_spill_regno_start
= INT_MAX
;
2377 remove_scratches ();
2379 /* A function that has a non-local label that can reach the exit
2380 block via non-exceptional paths must save all call-saved
2382 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2383 crtl
->saves_all_registers
= 1;
2385 if (crtl
->saves_all_registers
)
2386 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2387 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2388 df_set_regs_ever_live (i
, true);
2390 /* We don't DF from now and avoid its using because it is to
2391 expensive when a lot of RTL changes are made. */
2392 df_set_flags (DF_NO_INSN_RESCAN
);
2393 lra_constraint_insn_stack
.create (get_max_uid ());
2394 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2395 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2396 lra_live_ranges_init ();
2397 lra_constraints_init ();
2398 lra_curr_reload_num
= 0;
2399 push_insns (get_last_insn (), NULL
);
2400 /* It is needed for the 1st coalescing. */
2401 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2402 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2403 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2404 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2406 if (maybe_ne (get_frame_size (), 0) && crtl
->stack_alignment_needed
)
2407 /* If we have a stack frame, we must align it now. The stack size
2408 may be a part of the offset computation for register
2410 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2416 bool reloads_p
= lra_constraints (lra_constraint_iter
== 0);
2417 /* Constraint transformations may result in that eliminable
2418 hard regs become uneliminable and pseudos which use them
2419 should be spilled. It is better to do it before pseudo
2422 For example, rs6000 can make
2423 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2424 to use a constant pool. */
2425 lra_eliminate (false, false);
2426 /* We should try to assign hard registers to scratches even
2427 if there were no RTL transformations in lra_constraints.
2428 Also we should check IRA assignments on the first
2429 iteration as they can be wrong because of early clobbers
2430 operands which are ignored in IRA. */
2431 if (! reloads_p
&& lra_constraint_iter
> 1)
2433 /* Stack is not empty here only when there are changes
2434 during the elimination sub-pass. */
2435 if (bitmap_empty_p (lra_constraint_insn_stack_bitmap
))
2438 /* If there are no reloads but changing due
2439 elimination, restart the constraint sub-pass
2443 /* Do inheritance only for regular algorithms. */
2449 lra_clear_live_ranges ();
2450 /* As a side-effect of lra_create_live_ranges, we calculate
2451 actual_call_used_reg_set, which is needed during
2453 lra_create_live_ranges (true, true);
2459 lra_clear_live_ranges ();
2460 /* We need live ranges for lra_assign -- so build them. But
2461 don't remove dead insns or change global live info as we
2462 can undo inheritance transformations after inheritance
2463 pseudo assigning. */
2464 lra_create_live_ranges (true, false);
2466 /* If we don't spill non-reload and non-inheritance pseudos,
2467 there is no sense to run memory-memory move coalescing.
2468 If inheritance pseudos were spilled, the memory-memory
2469 moves involving them will be removed by pass undoing
2475 bool spill_p
= !lra_assign ();
2477 if (lra_undo_inheritance ())
2483 lra_create_live_ranges (true, true);
2486 if (lra_coalesce ())
2490 lra_clear_live_ranges ();
2493 /* Don't clear optional reloads bitmap until all constraints are
2494 satisfied as we need to differ them from regular reloads. */
2495 bitmap_clear (&lra_optional_reload_pseudos
);
2496 bitmap_clear (&lra_subreg_reload_pseudos
);
2497 bitmap_clear (&lra_inheritance_pseudos
);
2498 bitmap_clear (&lra_split_regs
);
2501 /* We need full live info for spilling pseudos into
2502 registers instead of memory. */
2503 lra_create_live_ranges (lra_reg_spill_p
, true);
2506 /* We should check necessity for spilling here as the above live
2507 range pass can remove spilled pseudos. */
2508 if (! lra_need_for_spills_p ())
2510 /* Now we know what pseudos should be spilled. Try to
2511 rematerialize them first. */
2514 /* We need full live info -- see the comment above. */
2515 lra_create_live_ranges (lra_reg_spill_p
, true);
2517 if (! lra_need_for_spills_p ())
2521 /* Assignment of stack slots changes elimination offsets for
2522 some eliminations. So update the offsets here. */
2523 lra_eliminate (false, false);
2524 lra_constraint_new_regno_start
= max_reg_num ();
2525 if (lra_bad_spill_regno_start
== INT_MAX
2526 && lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
2527 && lra_rematerialization_iter
> LRA_MAX_REMATERIALIZATION_PASSES
)
2528 /* After switching off inheritance and rematerialization
2529 passes, avoid spilling reload pseudos will be created to
2530 prevent LRA cycling in some complicated cases. */
2531 lra_bad_spill_regno_start
= lra_constraint_new_regno_start
;
2532 lra_assignment_iter_after_spill
= 0;
2534 restore_scratches ();
2535 lra_eliminate (true, false);
2536 lra_final_code_change ();
2537 lra_in_progress
= 0;
2539 lra_clear_live_ranges ();
2540 lra_live_ranges_finish ();
2541 lra_constraints_finish ();
2543 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2544 lra_constraint_insn_stack
.release ();
2545 finish_insn_recog_data ();
2546 regstat_free_n_sets_and_refs ();
2548 reload_completed
= 1;
2549 update_inc_notes ();
2551 inserted_p
= fixup_abnormal_edges ();
2553 /* We've possibly turned single trapping insn into multiple ones. */
2554 if (cfun
->can_throw_non_call_exceptions
)
2556 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
2557 bitmap_ones (blocks
);
2558 find_many_sub_basic_blocks (blocks
);
2562 commit_edge_insertions ();
2564 /* Replacing pseudos with their memory equivalents might have
2565 created shared rtx. Subsequent passes would get confused
2566 by this, so unshare everything here. */
2567 unshare_all_rtl_again (get_insns ());
2572 timevar_pop (TV_LRA
);
2575 /* Called once per compiler to initialize LRA data once. */
2577 lra_init_once (void)
2579 init_insn_code_data_once ();
2582 /* Called once per compiler to finish LRA data which are initialize
2585 lra_finish_once (void)
2587 finish_insn_code_data_once ();