1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
53 #define FRV_INLINE inline
56 /* Temporary register allocation support structure. */
57 typedef struct frv_tmp_reg_struct
59 HARD_REG_SET regs
; /* possible registers to allocate */
60 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
64 /* Register state information for VLIW re-packing phase. These values must fit
65 within an unsigned char. */
66 #define REGSTATE_DEAD 0x00 /* register is currently dead */
67 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
68 #define REGSTATE_LIVE 0x08 /* register is live */
69 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
70 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
71 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
72 #define REGSTATE_UNUSED 0x80 /* bit for hire */
73 #define REGSTATE_MASK 0xff /* mask for the bits to set */
75 /* conditional expression used */
76 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
78 /* The following is not sure in the reg_state bytes, so can have a larger value
80 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
82 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
90 /* Information required by frv_frame_access. */
93 /* This field is FRV_LOAD if registers are to be loaded from the stack and
94 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
95 the move is being done by the prologue code while FRV_LOAD implies it
96 is being done by the epilogue. */
99 /* The base register to use when accessing the stack. This may be the
100 frame pointer, stack pointer, or a temporary. The choice of register
101 depends on which part of the frame is being accessed and how big the
105 /* The offset of BASE from the bottom of the current frame, in bytes. */
107 } frv_frame_accessor_t
;
109 /* Define the information needed to generate branch and scc insns. This is
110 stored from the compare operation. */
114 /* Conditional execution support gathered together in one structure. */
117 /* Linked list of insns to add if the conditional execution conversion was
118 successful. Each link points to an EXPR_LIST which points to the pattern
119 of the insn to add, and the insn to be inserted before. */
120 rtx added_insns_list
;
122 /* Identify which registers are safe to allocate for if conversions to
123 conditional execution. We keep the last allocated register in the
124 register classes between COND_EXEC statements. This will mean we allocate
125 different registers for each different COND_EXEC group if we can. This
126 might allow the scheduler to intermix two different COND_EXEC sections. */
127 frv_tmp_reg_t tmp_reg
;
129 /* For nested IFs, identify which CC registers are used outside of setting
130 via a compare isnsn, and using via a check insn. This will allow us to
131 know if we can rewrite the register to use a different register that will
132 be paired with the CR register controlling the nested IF-THEN blocks. */
133 HARD_REG_SET nested_cc_ok_rewrite
;
135 /* Temporary registers allocated to hold constants during conditional
137 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
139 /* Current number of temp registers available. */
140 int cur_scratch_regs
;
142 /* Number of nested conditional execution blocks. */
143 int num_nested_cond_exec
;
145 /* Map of insns that set up constants in scratch registers. */
146 bitmap scratch_insns_bitmap
;
148 /* Conditional execution test register (CC0..CC7). */
151 /* Conditional execution compare register that is paired with cr_reg, so that
152 nested compares can be done. The csubcc and caddcc instructions don't
153 have enough bits to specify both a CC register to be set and a CR register
154 to do the test on, so the same bit number is used for both. Needless to
155 say, this is rather inconvenient for GCC. */
158 /* Extra CR registers used for &&, ||. */
162 /* Previous CR used in nested if, to make sure we are dealing with the same
163 nested if as the previous statement. */
164 rtx last_nested_if_cr
;
168 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
170 /* Map register number to smallest register class. */
171 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
173 /* Map class letter into register class. */
174 enum reg_class reg_class_from_letter
[256];
176 /* Cached value of frv_stack_info. */
177 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
179 /* -mbranch-cost= support */
180 const char *frv_branch_cost_string
;
181 int frv_branch_cost_int
= DEFAULT_BRANCH_COST
;
184 const char *frv_cpu_string
; /* -mcpu= option */
185 frv_cpu_t frv_cpu_type
= CPU_TYPE
; /* value of -mcpu= */
187 /* -mcond-exec-insns= support */
188 const char *frv_condexec_insns_str
; /* -mcond-exec-insns= option */
189 int frv_condexec_insns
= DEFAULT_CONDEXEC_INSNS
; /* value of -mcond-exec-insns*/
191 /* -mcond-exec-temps= support */
192 const char *frv_condexec_temps_str
; /* -mcond-exec-temps= option */
193 int frv_condexec_temps
= DEFAULT_CONDEXEC_TEMPS
; /* value of -mcond-exec-temps*/
195 /* -msched-lookahead=n */
196 const char *frv_sched_lookahead_str
; /* -msched-lookahead=n */
197 int frv_sched_lookahead
= 4; /* -msched-lookahead=n */
199 /* Forward references */
200 static int frv_default_flags_for_cpu (void);
201 static int frv_string_begins_with (tree
, const char *);
202 static FRV_INLINE
int const_small_data_p (rtx
);
203 static FRV_INLINE
int plus_small_data_p (rtx
, rtx
);
204 static void frv_print_operand_memory_reference_reg
206 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
207 static int frv_print_operand_jump_hint (rtx
);
208 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
209 static rtx
single_set_pattern (rtx
);
210 static int frv_function_contains_far_jump (void);
211 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
215 static rtx
frv_frame_offset_rtx (int);
216 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
217 static rtx
frv_dwarf_store (rtx
, int);
218 static void frv_frame_insn (rtx
, rtx
);
219 static void frv_frame_access (frv_frame_accessor_t
*,
221 static void frv_frame_access_multi (frv_frame_accessor_t
*,
223 static void frv_frame_access_standard_regs (enum frv_stack_op
,
225 static struct machine_function
*frv_init_machine_status (void);
226 static int frv_legitimate_memory_operand (rtx
, enum machine_mode
, int);
227 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
228 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
229 static rtx
frv_read_argument (tree
*);
230 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
231 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
232 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
233 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
234 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
235 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
236 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
237 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
238 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
239 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
240 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
241 static rtx
frv_expand_mclracc_builtin (tree
);
242 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
243 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
244 static rtx
frv_expand_noargs_builtin (enum insn_code
);
245 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
246 static int frv_clear_registers_used (rtx
*, void *);
247 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
248 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
249 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
250 static void frv_registers_update (rtx
, unsigned char [],
252 static int frv_registers_used_p (rtx
, unsigned char [], int);
253 static int frv_registers_set_p (rtx
, unsigned char [], int);
254 static int frv_issue_rate (void);
255 static int frv_use_dfa_pipeline_interface (void);
256 static void frv_pack_insns (void);
257 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
258 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
259 static bool frv_assemble_integer (rtx
, unsigned, int);
260 static void frv_init_builtins (void);
261 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
262 static void frv_init_libfuncs (void);
263 static bool frv_in_small_data_p (tree
);
264 static void frv_asm_output_mi_thunk
265 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
266 static rtx
frv_expand_builtin_saveregs (void);
267 static bool frv_rtx_costs (rtx
, int, int, int*);
268 static void frv_asm_out_constructor (rtx
, int);
269 static void frv_asm_out_destructor (rtx
, int);
270 static rtx
frv_struct_value_rtx (tree
, int);
272 /* Initialize the GCC target structure. */
273 #undef TARGET_ASM_FUNCTION_PROLOGUE
274 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
275 #undef TARGET_ASM_FUNCTION_EPILOGUE
276 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
277 #undef TARGET_ASM_INTEGER
278 #define TARGET_ASM_INTEGER frv_assemble_integer
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS frv_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
283 #undef TARGET_INIT_LIBFUNCS
284 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
285 #undef TARGET_IN_SMALL_DATA_P
286 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
287 #undef TARGET_RTX_COSTS
288 #define TARGET_RTX_COSTS frv_rtx_costs
289 #undef TARGET_ASM_CONSTRUCTOR
290 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
291 #undef TARGET_ASM_DESTRUCTOR
292 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
294 #undef TARGET_ASM_OUTPUT_MI_THUNK
295 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
296 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
297 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
299 #undef TARGET_SCHED_ISSUE_RATE
300 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
301 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
302 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE frv_use_dfa_pipeline_interface
304 #undef TARGET_STRUCT_VALUE_RTX
305 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
307 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
308 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
310 struct gcc_target targetm
= TARGET_INITIALIZER
;
312 /* Given a CONST, return true if the symbol_ref points to small data. */
314 static FRV_INLINE
int
315 const_small_data_p (rtx x
)
319 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
322 x0
= XEXP (XEXP (x
, 0), 0);
323 if (GET_CODE (x0
) != SYMBOL_REF
|| !SYMBOL_REF_SMALL_P (x0
))
326 x1
= XEXP (XEXP (x
, 0), 1);
327 if (GET_CODE (x1
) != CONST_INT
328 || !IN_RANGE_P (INTVAL (x1
), -2048, 2047))
334 /* Given a PLUS, return true if this is a small data reference. */
336 static FRV_INLINE
int
337 plus_small_data_p (rtx op0
, rtx op1
)
339 if (GET_MODE (op0
) == SImode
340 && GET_CODE (op0
) == REG
341 && REGNO (op0
) == SDA_BASE_REG
)
343 if (GET_CODE (op1
) == SYMBOL_REF
)
344 return SYMBOL_REF_SMALL_P (op1
);
346 if (GET_CODE (op1
) == CONST
)
347 return const_small_data_p (op1
);
355 frv_default_flags_for_cpu (void)
357 switch (frv_cpu_type
)
359 case FRV_CPU_GENERIC
:
360 return MASK_DEFAULT_FRV
;
364 return MASK_DEFAULT_FR500
;
367 return MASK_DEFAULT_FR400
;
371 return MASK_DEFAULT_SIMPLE
;
376 /* Sometimes certain combinations of command options do not make
377 sense on a particular target machine. You can define a macro
378 `OVERRIDE_OPTIONS' to take account of this. This macro, if
379 defined, is executed once just after all the command options have
382 Don't use this macro to turn on various extra optimizations for
383 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
386 frv_override_options (void)
390 /* Set the cpu type. */
393 if (strcmp (frv_cpu_string
, "simple") == 0)
394 frv_cpu_type
= FRV_CPU_SIMPLE
;
396 else if (strcmp (frv_cpu_string
, "tomcat") == 0)
397 frv_cpu_type
= FRV_CPU_TOMCAT
;
399 else if (strncmp (frv_cpu_string
, "fr", sizeof ("fr")-1) != 0)
400 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
404 const char *p
= frv_cpu_string
+ sizeof ("fr") - 1;
405 if (strcmp (p
, "500") == 0)
406 frv_cpu_type
= FRV_CPU_FR500
;
408 else if (strcmp (p
, "400") == 0)
409 frv_cpu_type
= FRV_CPU_FR400
;
411 else if (strcmp (p
, "300") == 0)
412 frv_cpu_type
= FRV_CPU_FR300
;
414 else if (strcmp (p
, "v") == 0)
415 frv_cpu_type
= FRV_CPU_GENERIC
;
418 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
422 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
424 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
425 linker about linking pic and non-pic code. */
428 if (!flag_pic
) /* -fPIC */
431 if (! g_switch_set
) /* -G0 */
438 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
440 if (write_symbols
== DWARF_DEBUG
&& flag_pic
)
441 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
443 /* Change the branch cost value. */
444 if (frv_branch_cost_string
)
445 frv_branch_cost_int
= atoi (frv_branch_cost_string
);
447 /* Change the # of insns to be converted to conditional execution. */
448 if (frv_condexec_insns_str
)
449 frv_condexec_insns
= atoi (frv_condexec_insns_str
);
451 /* Change # of temporary registers used to hold integer constants. */
452 if (frv_condexec_temps_str
)
453 frv_condexec_temps
= atoi (frv_condexec_temps_str
);
455 /* Change scheduling look ahead. */
456 if (frv_sched_lookahead_str
)
457 frv_sched_lookahead
= atoi (frv_sched_lookahead_str
);
459 /* A C expression whose value is a register class containing hard
460 register REGNO. In general there is more than one such class;
461 choose a class which is "minimal", meaning that no smaller class
462 also contains the register. */
464 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
466 enum reg_class
class;
470 int gpr_reg
= regno
- GPR_FIRST
;
471 if ((gpr_reg
& 3) == 0)
474 else if ((gpr_reg
& 1) == 0)
481 else if (FPR_P (regno
))
483 int fpr_reg
= regno
- GPR_FIRST
;
484 if ((fpr_reg
& 3) == 0)
485 class = QUAD_FPR_REGS
;
487 else if ((fpr_reg
& 1) == 0)
494 else if (regno
== LR_REGNO
)
497 else if (regno
== LCR_REGNO
)
500 else if (ICC_P (regno
))
503 else if (FCC_P (regno
))
506 else if (ICR_P (regno
))
509 else if (FCR_P (regno
))
512 else if (ACC_P (regno
))
514 int r
= regno
- ACC_FIRST
;
516 class = QUAD_ACC_REGS
;
517 else if ((r
& 1) == 0)
518 class = EVEN_ACC_REGS
;
523 else if (ACCG_P (regno
))
529 regno_reg_class
[regno
] = class;
532 /* Check for small data option */
534 g_switch_value
= SDATA_DEFAULT_SIZE
;
536 /* A C expression which defines the machine-dependent operand
537 constraint letters for register classes. If CHAR is such a
538 letter, the value should be the register class corresponding to
539 it. Otherwise, the value should be `NO_REGS'. The register
540 letter `r', corresponding to class `GENERAL_REGS', will not be
541 passed to this macro; you do not need to handle it.
543 The following letters are unavailable, due to being used as
548 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
549 'Q', 'R', 'S', 'T', 'U'
551 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
553 for (i
= 0; i
< 256; i
++)
554 reg_class_from_letter
[i
] = NO_REGS
;
556 reg_class_from_letter
['a'] = ACC_REGS
;
557 reg_class_from_letter
['b'] = EVEN_ACC_REGS
;
558 reg_class_from_letter
['c'] = CC_REGS
;
559 reg_class_from_letter
['d'] = GPR_REGS
;
560 reg_class_from_letter
['e'] = EVEN_REGS
;
561 reg_class_from_letter
['f'] = FPR_REGS
;
562 reg_class_from_letter
['h'] = FEVEN_REGS
;
563 reg_class_from_letter
['l'] = LR_REG
;
564 reg_class_from_letter
['q'] = QUAD_REGS
;
565 reg_class_from_letter
['t'] = ICC_REGS
;
566 reg_class_from_letter
['u'] = FCC_REGS
;
567 reg_class_from_letter
['v'] = ICR_REGS
;
568 reg_class_from_letter
['w'] = FCR_REGS
;
569 reg_class_from_letter
['x'] = QUAD_FPR_REGS
;
570 reg_class_from_letter
['y'] = LCR_REG
;
571 reg_class_from_letter
['z'] = SPR_REGS
;
572 reg_class_from_letter
['A'] = QUAD_ACC_REGS
;
573 reg_class_from_letter
['B'] = ACCG_REGS
;
574 reg_class_from_letter
['C'] = CR_REGS
;
576 /* There is no single unaligned SI op for PIC code. Sometimes we
577 need to use ".4byte" and sometimes we need to use ".picptr".
578 See frv_assemble_integer for details. */
580 targetm
.asm_out
.unaligned_op
.si
= 0;
582 init_machine_status
= frv_init_machine_status
;
586 /* Some machines may desire to change what optimizations are performed for
587 various optimization levels. This macro, if defined, is executed once just
588 after the optimization level is determined and before the remainder of the
589 command options have been parsed. Values set in this macro are used as the
590 default values for the other command line options.
592 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
593 `-O' is specified, and 0 if neither is specified.
595 SIZE is nonzero if `-Os' is specified, 0 otherwise.
597 You should not use this macro to change options that are not
598 machine-specific. These should uniformly selected by the same optimization
599 level on all supported machines. Use this macro to enable machbine-specific
602 *Do not examine `write_symbols' in this macro!* The debugging options are
603 *not supposed to alter the generated code. */
605 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
606 scheduling pass at the current time. */
608 frv_optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
612 #ifdef DISABLE_SCHED2
613 flag_schedule_insns_after_reload
= 0;
622 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
625 frv_string_begins_with (tree name
, const char *prefix
)
627 int prefix_len
= strlen (prefix
);
629 /* Remember: NAME's length includes the null terminator. */
630 return (TREE_STRING_LENGTH (name
) > prefix_len
631 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
634 /* Zero or more C statements that may conditionally modify two variables
635 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
636 been initialized from the two preceding macros.
638 This is necessary in case the fixed or call-clobbered registers depend on
641 You need not define this macro if it has no work to do.
643 If the usage of an entire class of registers depends on the target flags,
644 you may indicate this to GCC by using this macro to modify `fixed_regs' and
645 `call_used_regs' to 1 for each of the registers in the classes which should
646 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
647 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
649 (However, if this class is not included in `GENERAL_REGS' and all of the
650 insn patterns whose constraints permit this class are controlled by target
651 switches, then GCC will automatically avoid using these registers when the
652 target switches are opposed to them.) */
655 frv_conditional_register_usage (void)
659 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
660 fixed_regs
[i
] = call_used_regs
[i
] = 1;
662 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
663 fixed_regs
[i
] = call_used_regs
[i
] = 1;
665 for (i
= ACC_FIRST
+ NUM_ACCS
; i
<= ACC_LAST
; i
++)
666 fixed_regs
[i
] = call_used_regs
[i
] = 1;
668 for (i
= ACCG_FIRST
+ NUM_ACCS
; i
<= ACCG_LAST
; i
++)
669 fixed_regs
[i
] = call_used_regs
[i
] = 1;
671 /* Reserve the registers used for conditional execution. At present, we need
672 1 ICC and 1 ICR register. */
673 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
674 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
678 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
679 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
680 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
681 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
685 /* If -fpic, SDA_BASE_REG is the PIC register. */
686 if (g_switch_value
== 0 && !flag_pic
)
687 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
690 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
696 * Compute the stack frame layout
699 * +---------------+-----------------------+-----------------------+
700 * |Register |type |caller-save/callee-save|
701 * +---------------+-----------------------+-----------------------+
702 * |GR0 |Zero register | - |
703 * |GR1 |Stack pointer(SP) | - |
704 * |GR2 |Frame pointer(FP) | - |
705 * |GR3 |Hidden parameter | caller save |
706 * |GR4-GR7 | - | caller save |
707 * |GR8-GR13 |Argument register | caller save |
708 * |GR14-GR15 | - | caller save |
709 * |GR16-GR31 | - | callee save |
710 * |GR32-GR47 | - | caller save |
711 * |GR48-GR63 | - | callee save |
712 * |FR0-FR15 | - | caller save |
713 * |FR16-FR31 | - | callee save |
714 * |FR32-FR47 | - | caller save |
715 * |FR48-FR63 | - | callee save |
716 * +---------------+-----------------------+-----------------------+
720 * SP-> |-----------------------------------|
722 * |-----------------------------------|
723 * | Register save area |
724 * |-----------------------------------|
725 * | Local variable save area |
726 * FP-> |-----------------------------------|
728 * |-----------------------------------|
729 * | Hidden parameter save area |
730 * |-----------------------------------|
731 * | Return address(LR) storage area |
732 * |-----------------------------------|
733 * | Padding for alignment |
734 * |-----------------------------------|
735 * | Register argument area |
736 * OLD SP-> |-----------------------------------|
738 * |-----------------------------------|
741 * Argument area/Parameter area:
743 * When a function is called, this area is used for argument transfer. When
744 * the argument is set up by the caller function, this area is referred to as
745 * the argument area. When the argument is referenced by the callee function,
746 * this area is referred to as the parameter area. The area is allocated when
747 * all arguments cannot be placed on the argument register at the time of
750 * Register save area:
752 * This is a register save area that must be guaranteed for the caller
753 * function. This area is not secured when the register save operation is not
756 * Local variable save area:
758 * This is the area for local variables and temporary variables.
762 * This area stores the FP value of the caller function.
764 * Hidden parameter save area:
766 * This area stores the start address of the return value storage
767 * area for a struct/union return function.
768 * When a struct/union is used as the return value, the caller
769 * function stores the return value storage area start address in
770 * register GR3 and passes it to the caller function.
771 * The callee function interprets the address stored in the GR3
772 * as the return value storage area start address.
773 * When register GR3 needs to be saved into memory, the callee
774 * function saves it in the hidden parameter save area. This
775 * area is not secured when the save operation is not needed.
777 * Return address(LR) storage area:
779 * This area saves the LR. The LR stores the address of a return to the caller
780 * function for the purpose of function calling.
782 * Argument register area:
784 * This area saves the argument register. This area is not secured when the
785 * save operation is not needed.
789 * Arguments, the count of which equals the count of argument registers (6
790 * words), are positioned in registers GR8 to GR13 and delivered to the callee
791 * function. When a struct/union return function is called, the return value
792 * area address is stored in register GR3. Arguments not placed in the
793 * argument registers will be stored in the stack argument area for transfer
794 * purposes. When an 8-byte type argument is to be delivered using registers,
795 * it is divided into two and placed in two registers for transfer. When
796 * argument registers must be saved to memory, the callee function secures an
797 * argument register save area in the stack. In this case, a continuous
798 * argument register save area must be established in the parameter area. The
799 * argument register save area must be allocated as needed to cover the size of
800 * the argument register to be saved. If the function has a variable count of
801 * arguments, it saves all argument registers in the argument register save
804 * Argument Extension Format:
806 * When an argument is to be stored in the stack, its type is converted to an
807 * extended type in accordance with the individual argument type. The argument
808 * is freed by the caller function after the return from the callee function is
811 * +-----------------------+---------------+------------------------+
812 * | Argument Type |Extended Type |Stack Storage Size(byte)|
813 * +-----------------------+---------------+------------------------+
815 * |signed char |int | 4 |
816 * |unsigned char |int | 4 |
817 * |[signed] short int |int | 4 |
818 * |unsigned short int |int | 4 |
819 * |[signed] int |No extension | 4 |
820 * |unsigned int |No extension | 4 |
821 * |[signed] long int |No extension | 4 |
822 * |unsigned long int |No extension | 4 |
823 * |[signed] long long int |No extension | 8 |
824 * |unsigned long long int |No extension | 8 |
825 * |float |double | 8 |
826 * |double |No extension | 8 |
827 * |long double |No extension | 8 |
828 * |pointer |No extension | 4 |
829 * |struct/union |- | 4 (*1) |
830 * +-----------------------+---------------+------------------------+
832 * When a struct/union is to be delivered as an argument, the caller copies it
833 * to the local variable area and delivers the address of that area.
837 * +-------------------------------+----------------------+
838 * |Return Value Type |Return Value Interface|
839 * +-------------------------------+----------------------+
841 * |[signed|unsigned] char |GR8 |
842 * |[signed|unsigned] short int |GR8 |
843 * |[signed|unsigned] int |GR8 |
844 * |[signed|unsigned] long int |GR8 |
846 * |[signed|unsigned] long long int|GR8 & GR9 |
848 * |double |GR8 & GR9 |
849 * |long double |GR8 & GR9 |
850 * |struct/union |(*1) |
851 * +-------------------------------+----------------------+
853 * When a struct/union is used as the return value, the caller function stores
854 * the start address of the return value storage area into GR3 and then passes
855 * it to the callee function. The callee function interprets GR3 as the start
856 * address of the return value storage area. When this address needs to be
857 * saved in memory, the callee function secures the hidden parameter save area
858 * and saves the address in that area.
862 frv_stack_info (void)
864 static frv_stack_t info
, zero_info
;
865 frv_stack_t
*info_ptr
= &info
;
866 tree fndecl
= current_function_decl
;
874 /* If we've already calculated the values and reload is complete,
877 return frv_stack_cache
;
879 /* Zero all fields. */
882 /* Set up the register range information. */
883 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
884 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
885 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
886 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
888 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
889 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
890 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
891 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
893 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
894 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
895 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
896 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
898 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
899 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
900 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
901 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
903 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
904 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
905 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
907 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
908 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
909 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
910 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
911 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
913 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
914 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
915 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
916 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
918 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
919 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
920 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
921 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
923 /* Determine if this is a stdarg function. If so, allocate space to store
930 /* Find the last argument, and see if it is __builtin_va_alist. */
931 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
933 next_arg
= TREE_CHAIN (cur_arg
);
934 if (next_arg
== (tree
)0)
936 if (DECL_NAME (cur_arg
)
937 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
945 /* Iterate over all of the register ranges. */
946 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
948 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
949 int first
= reg_ptr
->first
;
950 int last
= reg_ptr
->last
;
955 /* Calculate which registers need to be saved & save area size. */
959 for (regno
= first
; regno
<= last
; regno
++)
961 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
962 || (current_function_calls_eh_return
963 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
964 || (flag_pic
&& cfun
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
966 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
967 size_1word
+= UNITS_PER_WORD
;
972 /* Calculate whether we need to create a frame after everything else
973 has been processed. */
978 if (regs_ever_live
[LR_REGNO
]
980 || frame_pointer_needed
981 || (flag_pic
&& cfun
->uses_pic_offset_table
))
983 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
984 size_1word
+= UNITS_PER_WORD
;
988 case STACK_REGS_STDARG
:
991 /* If this is a stdarg function with a non varardic
992 argument split between registers and the stack,
993 adjust the saved registers downward. */
994 last
-= (ADDR_ALIGN (cfun
->pretend_args_size
, UNITS_PER_WORD
)
997 for (regno
= first
; regno
<= last
; regno
++)
999 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1000 size_1word
+= UNITS_PER_WORD
;
1003 info_ptr
->stdarg_size
= size_1word
;
1007 case STACK_REGS_STRUCT
:
1008 if (cfun
->returns_struct
)
1010 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1011 size_1word
+= UNITS_PER_WORD
;
1019 /* If this is a field, it only takes one word. */
1020 if (reg_ptr
->field_p
)
1021 size_1word
= UNITS_PER_WORD
;
1023 /* Determine which register pairs can be saved together. */
1024 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1026 for (regno
= first
; regno
< last
; regno
+= 2)
1028 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1030 size_2words
+= 2 * UNITS_PER_WORD
;
1031 size_1word
-= 2 * UNITS_PER_WORD
;
1032 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1033 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1038 reg_ptr
->size_1word
= size_1word
;
1039 reg_ptr
->size_2words
= size_2words
;
1041 if (! reg_ptr
->special_p
)
1043 info_ptr
->regs_size_1word
+= size_1word
;
1044 info_ptr
->regs_size_2words
+= size_2words
;
1049 /* Set up the sizes of each each field in the frame body, making the sizes
1050 of each be divisible by the size of a dword if dword operations might
1051 be used, or the size of a word otherwise. */
1052 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1054 info_ptr
->parameter_size
= ADDR_ALIGN (cfun
->outgoing_args_size
, alignment
);
1055 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1056 + info_ptr
->regs_size_1word
,
1058 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1060 info_ptr
->pretend_size
= cfun
->pretend_args_size
;
1062 /* Work out the size of the frame, excluding the header. Both the frame
1063 body and register parameter area will be dword-aligned. */
1064 info_ptr
->total_size
1065 = (ADDR_ALIGN (info_ptr
->parameter_size
1066 + info_ptr
->regs_size
1067 + info_ptr
->vars_size
,
1069 + ADDR_ALIGN (info_ptr
->pretend_size
1070 + info_ptr
->stdarg_size
,
1071 2 * UNITS_PER_WORD
));
1073 /* See if we need to create a frame at all, if so add header area. */
1074 if (info_ptr
->total_size
> 0
1075 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1076 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1078 offset
= info_ptr
->parameter_size
;
1079 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1080 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1082 /* Calculate the offsets to save normal register pairs. */
1083 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1085 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1086 if (! reg_ptr
->special_p
)
1088 int first
= reg_ptr
->first
;
1089 int last
= reg_ptr
->last
;
1092 for (regno
= first
; regno
<= last
; regno
++)
1093 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1094 && regno
!= FRAME_POINTER_REGNUM
1095 && (regno
< FIRST_ARG_REGNUM
1096 || regno
> LAST_ARG_REGNUM
))
1098 info_ptr
->reg_offset
[regno
] = offset
;
1099 offset
+= 2 * UNITS_PER_WORD
;
1104 /* Calculate the offsets to save normal single registers. */
1105 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1107 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1108 if (! reg_ptr
->special_p
)
1110 int first
= reg_ptr
->first
;
1111 int last
= reg_ptr
->last
;
1114 for (regno
= first
; regno
<= last
; regno
++)
1115 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1116 && regno
!= FRAME_POINTER_REGNUM
1117 && (regno
< FIRST_ARG_REGNUM
1118 || regno
> LAST_ARG_REGNUM
))
1120 info_ptr
->reg_offset
[regno
] = offset
;
1121 offset
+= UNITS_PER_WORD
;
1126 /* Calculate the offset to save the local variables at. */
1127 offset
= ADDR_ALIGN (offset
, alignment
);
1128 if (info_ptr
->vars_size
)
1130 info_ptr
->vars_offset
= offset
;
1131 offset
+= info_ptr
->vars_size
;
1134 /* Align header to a dword-boundary. */
1135 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1137 /* Calculate the offsets in the fixed frame. */
1138 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1139 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1140 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1142 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1143 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1144 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1146 if (cfun
->returns_struct
)
1148 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1149 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1150 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1153 /* Calculate the offsets to store the arguments passed in registers
1154 for stdarg functions. The register pairs are first and the single
1155 register if any is last. The register save area starts on a
1157 if (info_ptr
->stdarg_size
)
1159 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1160 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1163 /* Skip the header. */
1164 offset
+= 4 * UNITS_PER_WORD
;
1165 for (regno
= first
; regno
<= last
; regno
++)
1167 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1169 info_ptr
->reg_offset
[regno
] = offset
;
1170 offset
+= 2 * UNITS_PER_WORD
;
1172 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1174 info_ptr
->reg_offset
[regno
] = offset
;
1175 offset
+= UNITS_PER_WORD
;
1181 if (reload_completed
)
1182 frv_stack_cache
= info_ptr
;
1188 /* Print the information about the frv stack offsets, etc. when debugging. */
1191 frv_debug_stack (frv_stack_t
*info
)
1196 info
= frv_stack_info ();
1198 fprintf (stderr
, "\nStack information for function %s:\n",
1199 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1200 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1203 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1204 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1205 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1206 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1207 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1209 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1210 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1211 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1212 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1214 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1216 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1217 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1219 int first
= regs
->first
;
1220 int last
= regs
->last
;
1223 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1224 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1225 regs
->size_1word
, regs
->size_2words
);
1227 for (regno
= first
; regno
<= last
; regno
++)
1229 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1230 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1231 info
->reg_offset
[regno
]);
1233 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1234 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1235 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1238 fputc ('\n', stderr
);
1248 /* The following variable value is TRUE if the next output insn should
1249 finish cpu cycle. In order words the insn will have packing bit
1250 (which means absence of asm code suffix `.p' on assembler. */
1252 static int frv_insn_packing_flag
;
1254 /* True if the current function contains a far jump. */
1257 frv_function_contains_far_jump (void)
1259 rtx insn
= get_insns ();
1261 && !(GET_CODE (insn
) == JUMP_INSN
1262 /* Ignore tablejump patterns. */
1263 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1264 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1265 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1266 insn
= NEXT_INSN (insn
);
1267 return (insn
!= NULL
);
1270 /* For the FRV, this function makes sure that a function with far jumps
1271 will return correctly. It also does the VLIW packing. */
1274 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1276 /* If no frame was created, check whether the function uses a call
1277 instruction to implement a far jump. If so, save the link in gr3 and
1278 replace all returns to LR with returns to GR3. GR3 is used because it
1279 is call-clobbered, because is not available to the register allocator,
1280 and because all functions that take a hidden argument pointer will have
1282 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1286 /* Just to check that the above comment is true. */
1287 if (regs_ever_live
[GPR_FIRST
+ 3])
1290 /* Generate the instruction that saves the link register. */
1291 fprintf (file
, "\tmovsg lr,gr3\n");
1293 /* Replace the LR with GR3 in *return_internal patterns. The insn
1294 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1295 simply emit a different assembly directive because bralr and jmpl
1296 execute in different units. */
1297 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1298 if (GET_CODE (insn
) == JUMP_INSN
)
1300 rtx pattern
= PATTERN (insn
);
1301 if (GET_CODE (pattern
) == PARALLEL
1302 && XVECLEN (pattern
, 0) >= 2
1303 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1304 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1306 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1307 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1308 REGNO (address
) = GPR_FIRST
+ 3;
1314 frv_insn_packing_flag
= TRUE
;
1318 /* Return the next available temporary register in a given class. */
1321 frv_alloc_temp_reg (
1322 frv_tmp_reg_t
*info
, /* which registers are available */
1323 enum reg_class
class, /* register class desired */
1324 enum machine_mode mode
, /* mode to allocate register with */
1325 int mark_as_used
, /* register not available after allocation */
1326 int no_abort
) /* return NULL instead of aborting */
1328 int regno
= info
->next_reg
[ (int)class ];
1329 int orig_regno
= regno
;
1330 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)class ];
1335 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1336 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1339 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1341 if (regno
== orig_regno
)
1350 nr
= HARD_REGNO_NREGS (regno
, mode
);
1351 info
->next_reg
[ (int)class ] = regno
+ nr
;
1354 for (i
= 0; i
< nr
; i
++)
1355 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1357 return gen_rtx_REG (mode
, regno
);
1361 /* Return an rtx with the value OFFSET, which will either be a register or a
1362 signed 12-bit integer. It can be used as the second operand in an "add"
1363 instruction, or as the index in a load or store.
1365 The function returns a constant rtx if OFFSET is small enough, otherwise
1366 it loads the constant into register OFFSET_REGNO and returns that. */
1368 frv_frame_offset_rtx (int offset
)
1370 rtx offset_rtx
= GEN_INT (offset
);
1371 if (IN_RANGE_P (offset
, -2048, 2047))
1375 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1376 if (IN_RANGE_P (offset
, -32768, 32767))
1377 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1380 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1381 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1387 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1388 prologue and epilogue uses such expressions to access the stack. */
1390 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1392 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1394 frv_frame_offset_rtx (offset
)));
1397 /* Generate a frame-related expression:
1399 (set REG (mem (plus (sp) (const_int OFFSET)))).
1401 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1402 instructions. Marking the expressions as frame-related is superfluous if
1403 the note contains just a single set. But if the note contains a PARALLEL
1404 or SEQUENCE that has several sets, each set must be individually marked
1405 as frame-related. */
1407 frv_dwarf_store (rtx reg
, int offset
)
1409 rtx set
= gen_rtx_SET (VOIDmode
,
1410 gen_rtx_MEM (GET_MODE (reg
),
1411 plus_constant (stack_pointer_rtx
,
1414 RTX_FRAME_RELATED_P (set
) = 1;
1418 /* Emit a frame-related instruction whose pattern is PATTERN. The
1419 instruction is the last in a sequence that cumulatively performs the
1420 operation described by DWARF_PATTERN. The instruction is marked as
1421 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1424 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1426 rtx insn
= emit_insn (pattern
);
1427 RTX_FRAME_RELATED_P (insn
) = 1;
1428 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1433 /* Emit instructions that transfer REG to or from the memory location (sp +
1434 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1435 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1436 function to store registers and only the epilogue uses it to load them.
1438 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1439 The generated instruction will use BASE as its base register. BASE may
1440 simply be the stack pointer, but if several accesses are being made to a
1441 region far away from the stack pointer, it may be more efficient to set
1442 up a temporary instead.
1444 Store instructions will be frame-related and will be annotated with the
1445 overall effect of the store. Load instructions will be followed by a
1446 (use) to prevent later optimizations from zapping them.
1448 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1449 as a temporary in such cases. */
1451 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1453 enum machine_mode mode
= GET_MODE (reg
);
1454 rtx mem
= frv_frame_mem (mode
,
1456 stack_offset
- accessor
->base_offset
);
1458 if (accessor
->op
== FRV_LOAD
)
1460 if (SPR_P (REGNO (reg
)))
1462 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1463 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1464 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1467 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1468 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
1472 if (SPR_P (REGNO (reg
)))
1474 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1475 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1476 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1477 frv_dwarf_store (reg
, stack_offset
));
1479 else if (GET_MODE (reg
) == DImode
)
1481 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1482 with a separate save for each register. */
1483 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1484 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1485 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1486 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1487 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1488 gen_rtx_PARALLEL (VOIDmode
,
1489 gen_rtvec (2, set1
, set2
)));
1492 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1493 frv_dwarf_store (reg
, stack_offset
));
1497 /* A function that uses frv_frame_access to transfer a group of registers to
1498 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1499 is the stack information generated by frv_stack_info, and REG_SET is the
1500 number of the register set to transfer. */
1502 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1506 frv_stack_regs_t
*regs_info
;
1509 regs_info
= &info
->regs
[reg_set
];
1510 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1511 if (info
->save_p
[regno
])
1512 frv_frame_access (accessor
,
1513 info
->save_p
[regno
] == REG_SAVE_2WORDS
1514 ? gen_rtx_REG (DImode
, regno
)
1515 : gen_rtx_REG (SImode
, regno
),
1516 info
->reg_offset
[regno
]);
1519 /* Save or restore callee-saved registers that are kept outside the frame
1520 header. The function saves the registers if OP is FRV_STORE and restores
1521 them if OP is FRV_LOAD. INFO is the stack information generated by
1524 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1526 frv_frame_accessor_t accessor
;
1529 accessor
.base
= stack_pointer_rtx
;
1530 accessor
.base_offset
= 0;
1531 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1532 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1533 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1537 /* Called after register allocation to add any instructions needed for the
1538 prologue. Using a prologue insn is favored compared to putting all of the
1539 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1540 it allows the scheduler to intermix instructions with the saves of
1541 the caller saved registers. In some cases, it might be necessary
1542 to emit a barrier instruction as the last insn to prevent such
1545 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1546 so that the debug info generation code can handle them properly. */
1548 frv_expand_prologue (void)
1550 frv_stack_t
*info
= frv_stack_info ();
1551 rtx sp
= stack_pointer_rtx
;
1552 rtx fp
= frame_pointer_rtx
;
1553 frv_frame_accessor_t accessor
;
1555 if (TARGET_DEBUG_STACK
)
1556 frv_debug_stack (info
);
1558 if (info
->total_size
== 0)
1561 /* We're interested in three areas of the frame here:
1563 A: the register save area
1565 C: the header after B
1567 If the frame pointer isn't used, we'll have to set up A, B and C
1568 using the stack pointer. If the frame pointer is used, we'll access
1572 B: set up using sp or a temporary (see below)
1575 We set up B using the stack pointer if the frame is small enough.
1576 Otherwise, it's more efficient to copy the old stack pointer into a
1577 temporary and use that.
1579 Note that it's important to make sure the prologue and epilogue use the
1580 same registers to access A and C, since doing otherwise will confuse
1581 the aliasing code. */
1583 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1584 isn't used, the same method will serve for C. */
1585 accessor
.op
= FRV_STORE
;
1586 if (frame_pointer_needed
&& info
->total_size
> 2048)
1590 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1591 accessor
.base_offset
= info
->total_size
;
1592 insn
= emit_insn (gen_movsi (accessor
.base
, sp
));
1596 accessor
.base
= stack_pointer_rtx
;
1597 accessor
.base_offset
= 0;
1600 /* Allocate the stack space. */
1602 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1603 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1605 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1608 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1611 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1612 and point the new one to that location. */
1613 if (frame_pointer_needed
)
1615 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1617 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1618 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1620 rtx asm_src
= plus_constant (accessor
.base
,
1621 fp_offset
- accessor
.base_offset
);
1622 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1624 /* Store the old frame pointer at (sp + FP_OFFSET). */
1625 frv_frame_access (&accessor
, fp
, fp_offset
);
1627 /* Set up the new frame pointer. */
1628 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1629 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1631 /* Access region C from the frame pointer. */
1633 accessor
.base_offset
= fp_offset
;
1636 /* Set up region C. */
1637 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1638 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1639 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1641 /* Set up region A. */
1642 frv_frame_access_standard_regs (FRV_STORE
, info
);
1644 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1645 scheduler from moving loads before the stores saving the registers. */
1646 if (info
->stdarg_size
> 0)
1647 emit_insn (gen_blockage ());
1649 /* Set up pic register/small data register for this function. */
1650 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1651 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1652 gen_rtx_REG (Pmode
, LR_REGNO
),
1653 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1657 /* Under frv, all of the work is done via frv_expand_epilogue, but
1658 this function provides a convenient place to do cleanup. */
1661 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1662 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1664 frv_stack_cache
= (frv_stack_t
*)0;
1666 /* Zap last used registers for conditional execution. */
1667 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1669 /* Release the bitmap of created insns. */
1670 BITMAP_XFREE (frv_ifcvt
.scratch_insns_bitmap
);
1674 /* Called after register allocation to add any instructions needed for the
1675 epilogue. Using an epilogue insn is favored compared to putting all of the
1676 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1677 it allows the scheduler to intermix instructions with the saves of
1678 the caller saved registers. In some cases, it might be necessary
1679 to emit a barrier instruction as the last insn to prevent such
1682 If SIBCALL_P is true, the final branch back to the calling function is
1683 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1684 we must not clobber any arguments used for parameter passing or any stack
1685 slots for arguments passed to the current function. */
1688 frv_expand_epilogue (int sibcall_p
)
1690 frv_stack_t
*info
= frv_stack_info ();
1691 rtx fp
= frame_pointer_rtx
;
1692 rtx sp
= stack_pointer_rtx
;
1696 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1698 /* Restore the stack pointer to its original value if alloca or the like
1700 if (! current_function_sp_is_unchanging
)
1701 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1703 /* Restore the callee-saved registers that were used in this function. */
1704 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1706 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1707 no return instruction should be emitted. */
1710 else if (info
->save_p
[LR_REGNO
])
1715 /* Use the same method to access the link register's slot as we did in
1716 the prologue. In other words, use the frame pointer if available,
1717 otherwise use the stack pointer.
1719 LR_OFFSET is the offset of the link register's slot from the start
1720 of the frame and MEM is a memory rtx for it. */
1721 lr_offset
= info
->reg_offset
[LR_REGNO
];
1722 if (frame_pointer_needed
)
1723 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1725 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1727 /* Load the old link register into a GPR. */
1728 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1729 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1732 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1734 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1735 the load is preserved. */
1736 if (frame_pointer_needed
)
1738 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1739 emit_insn (gen_rtx_USE (VOIDmode
, fp
));
1742 /* Deallocate the stack frame. */
1743 if (info
->total_size
!= 0)
1745 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1746 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1749 /* If this function uses eh_return, add the final stack adjustment now. */
1750 if (current_function_calls_eh_return
)
1751 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1754 emit_jump_insn (gen_epilogue_return (return_addr
));
1758 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1761 frv_asm_output_mi_thunk (FILE *file
,
1762 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1763 HOST_WIDE_INT delta
,
1764 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1767 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1768 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1769 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1770 const char *parallel
= ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1772 /* Do the add using an addi if possible. */
1773 if (IN_RANGE_P (delta
, -2048, 2047))
1774 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1777 const char *const name_add
= reg_names
[TEMP_REGNO
];
1778 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1779 parallel
, delta
, name_add
);
1780 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1782 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1787 fprintf (file
, "\tsethi%s #hi(", parallel
);
1788 assemble_name (file
, name_func
);
1789 fprintf (file
, "),%s\n", name_jmp
);
1791 fprintf (file
, "\tsetlo #lo(");
1792 assemble_name (file
, name_func
);
1793 fprintf (file
, "),%s\n", name_jmp
);
1797 /* Use JUMP_REGNO as a temporary PIC register. */
1798 const char *name_lr
= reg_names
[LR_REGNO
];
1799 const char *name_gppic
= name_jmp
;
1800 const char *name_tmp
= reg_names
[TEMP_REGNO
];
1802 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
1803 fprintf (file
, "\tcall 1f\n");
1804 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
1805 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
1806 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
1807 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
1808 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
1810 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
1811 assemble_name (file
, name_func
);
1812 fprintf (file
, "),%s\n", name_tmp
);
1814 fprintf (file
, "\tsetlo #gprello(");
1815 assemble_name (file
, name_func
);
1816 fprintf (file
, "),%s\n", name_tmp
);
1818 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
1821 /* Jump to the function address. */
1822 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
1826 /* A C expression which is nonzero if a function must have and use a frame
1827 pointer. This expression is evaluated in the reload pass. If its value is
1828 nonzero the function will have a frame pointer.
1830 The expression can in principle examine the current function and decide
1831 according to the facts, but on most machines the constant 0 or the constant
1832 1 suffices. Use 0 when the machine allows code to be generated with no
1833 frame pointer, and doing so saves some time or space. Use 1 when there is
1834 no possible advantage to avoiding a frame pointer.
1836 In certain cases, the compiler does not know how to produce valid code
1837 without a frame pointer. The compiler recognizes those cases and
1838 automatically gives the function a frame pointer regardless of what
1839 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1841 In a function that does not require a frame pointer, the frame pointer
1842 register can be allocated for ordinary usage, unless you mark it as a fixed
1843 register. See `FIXED_REGISTERS' for more information. */
1845 /* On frv, create a frame whenever we need to create stack. */
1848 frv_frame_pointer_required (void)
1850 if (! current_function_is_leaf
)
1853 if (get_frame_size () != 0)
1859 if (!current_function_sp_is_unchanging
)
1862 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1868 if (cfun
->machine
->frame_needed
)
1875 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1876 initial difference between the specified pair of registers. This macro must
1877 be defined if `ELIMINABLE_REGS' is defined. */
1879 /* See frv_stack_info for more details on the frv stack frame. */
1882 frv_initial_elimination_offset (int from
, int to
)
1884 frv_stack_t
*info
= frv_stack_info ();
1887 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
1888 ret
= info
->total_size
- info
->pretend_size
;
1890 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
1891 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1893 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
1894 ret
= (info
->total_size
1895 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
1896 - info
->pretend_size
);
1901 if (TARGET_DEBUG_STACK
)
1902 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
1903 reg_names
[from
], reg_names
[to
], ret
);
1909 /* Worker function for SETUP_INCOMING_VARARGS. */
1912 frv_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
1913 enum machine_mode mode
,
1914 tree type ATTRIBUTE_UNUSED
,
1918 if (TARGET_DEBUG_ARG
)
1920 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
1921 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
1925 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
1928 frv_expand_builtin_saveregs (void)
1930 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
1932 if (TARGET_DEBUG_ARG
)
1933 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
1936 return gen_rtx (PLUS
, Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
1940 /* Expand __builtin_va_start to do the va_start macro. */
1943 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
1946 int num
= cfun
->args_info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
1948 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
1949 GEN_INT (UNITS_PER_WORD
* num
));
1951 if (TARGET_DEBUG_ARG
)
1953 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
1954 cfun
->args_info
, num
);
1956 debug_rtx (nextarg
);
1959 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
1960 make_tree (ptr_type_node
, nextarg
));
1961 TREE_SIDE_EFFECTS (t
) = 1;
1963 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1967 /* Expand __builtin_va_arg to do the va_arg macro. */
1970 frv_expand_builtin_va_arg (tree valist
, tree type
)
1976 if (TARGET_DEBUG_ARG
)
1978 fprintf (stderr
, "va_arg:\n");
1982 if (! AGGREGATE_TYPE_P (type
))
1983 return std_expand_builtin_va_arg (valist
, type
);
1985 addr
= std_expand_builtin_va_arg (valist
, ptr_type_node
);
1986 mem
= gen_rtx_MEM (Pmode
, addr
);
1987 reg
= gen_reg_rtx (Pmode
);
1989 set_mem_alias_set (mem
, get_varargs_alias_set ());
1990 emit_move_insn (reg
, mem
);
1996 /* Expand a block move operation, and return 1 if successful. Return 0
1997 if we should let the compiler generate normal code.
1999 operands[0] is the destination
2000 operands[1] is the source
2001 operands[2] is the length
2002 operands[3] is the alignment */
2004 /* Maximum number of loads to do before doing the stores */
2005 #ifndef MAX_MOVE_REG
2006 #define MAX_MOVE_REG 4
2009 /* Maximum number of total loads to do. */
2010 #ifndef TOTAL_MOVE_REG
2011 #define TOTAL_MOVE_REG 8
2015 frv_expand_block_move (rtx operands
[])
2017 rtx orig_dest
= operands
[0];
2018 rtx orig_src
= operands
[1];
2019 rtx bytes_rtx
= operands
[2];
2020 rtx align_rtx
= operands
[3];
2021 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2034 rtx stores
[MAX_MOVE_REG
];
2036 enum machine_mode mode
;
2038 /* If this is not a fixed size move, just call memcpy. */
2042 /* If this is not a fixed size alignment, abort. */
2043 if (GET_CODE (align_rtx
) != CONST_INT
)
2046 align
= INTVAL (align_rtx
);
2048 /* Anything to move? */
2049 bytes
= INTVAL (bytes_rtx
);
2053 /* Don't support real large moves. */
2054 if (bytes
> TOTAL_MOVE_REG
*align
)
2057 /* Move the address into scratch registers. */
2058 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2059 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2061 num_reg
= offset
= 0;
2062 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2064 /* Calculate the correct offset for src/dest. */
2068 dest_addr
= dest_reg
;
2072 src_addr
= plus_constant (src_reg
, offset
);
2073 dest_addr
= plus_constant (dest_reg
, offset
);
2076 /* Generate the appropriate load and store, saving the stores
2078 if (bytes
>= 4 && align
>= 4)
2080 else if (bytes
>= 2 && align
>= 2)
2085 move_bytes
= GET_MODE_SIZE (mode
);
2086 tmp_reg
= gen_reg_rtx (mode
);
2087 src_mem
= change_address (orig_src
, mode
, src_addr
);
2088 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2089 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2090 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2092 if (num_reg
>= MAX_MOVE_REG
)
2094 for (i
= 0; i
< num_reg
; i
++)
2095 emit_insn (stores
[i
]);
2100 for (i
= 0; i
< num_reg
; i
++)
2101 emit_insn (stores
[i
]);
2107 /* Expand a block clear operation, and return 1 if successful. Return 0
2108 if we should let the compiler generate normal code.
2110 operands[0] is the destination
2111 operands[1] is the length
2112 operands[2] is the alignment */
2115 frv_expand_block_clear (rtx operands
[])
2117 rtx orig_dest
= operands
[0];
2118 rtx bytes_rtx
= operands
[1];
2119 rtx align_rtx
= operands
[2];
2120 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2129 enum machine_mode mode
;
2131 /* If this is not a fixed size move, just call memcpy. */
2135 /* If this is not a fixed size alignment, abort. */
2136 if (GET_CODE (align_rtx
) != CONST_INT
)
2139 align
= INTVAL (align_rtx
);
2141 /* Anything to move? */
2142 bytes
= INTVAL (bytes_rtx
);
2146 /* Don't support real large clears. */
2147 if (bytes
> TOTAL_MOVE_REG
*align
)
2150 /* Move the address into a scratch register. */
2151 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2153 num_reg
= offset
= 0;
2154 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2156 /* Calculate the correct offset for src/dest. */
2157 dest_addr
= ((offset
== 0)
2159 : plus_constant (dest_reg
, offset
));
2161 /* Generate the appropriate store of gr0. */
2162 if (bytes
>= 4 && align
>= 4)
2164 else if (bytes
>= 2 && align
>= 2)
2169 clear_bytes
= GET_MODE_SIZE (mode
);
2170 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2171 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2178 /* The following variable is used to output modifiers of assembler
2179 code of the current output insn. */
2181 static rtx
*frv_insn_operands
;
2183 /* The following function is used to add assembler insn code suffix .p
2184 if it is necessary. */
2187 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2191 if (! PACKING_FLAG_USED_P())
2194 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2197 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2198 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2200 int letter
= *ptr
++;
2203 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2204 while ((c
= *ptr
) >= '0' && c
<= '9')
2211 if (!frv_insn_packing_flag
)
2217 /* The following function sets up the packing bit for the current
2218 output insn. Remember that the function is not called for asm
2222 frv_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands ATTRIBUTE_UNUSED
)
2224 if (! PACKING_FLAG_USED_P())
2230 frv_insn_operands
= opvec
;
2232 /* Look for the next printable instruction. frv_pack_insns () has set
2233 things up so that any printable instruction will have TImode if it
2234 starts a new packet and VOIDmode if it should be packed with the
2235 previous instruction.
2237 Printable instructions will be asm_operands or match one of the .md
2238 patterns. Since asm instructions cannot be packed -- and will
2239 therefore have TImode -- this loop terminates on any recognizable
2240 instruction, and on any unrecognizable instruction with TImode. */
2241 for (insn
= NEXT_INSN (insn
); insn
; insn
= NEXT_INSN (insn
))
2245 else if (!INSN_P (insn
))
2247 else if (GET_MODE (insn
) == TImode
|| INSN_CODE (insn
) != -1)
2251 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2252 be packed with this one. Set it to TRUE otherwise. If the next
2253 instruction is an asm instruction, this statement will set the
2254 flag to TRUE, and that value will still hold when the asm operands
2255 themselves are printed. */
2256 frv_insn_packing_flag
= ! (insn
&& INSN_P (insn
)
2257 && GET_MODE (insn
) != TImode
);
2262 /* A C expression whose value is RTL representing the address in a stack frame
2263 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2264 an RTL expression for the address of the stack frame itself.
2266 If you don't define this macro, the default is to return the value of
2267 FRAMEADDR--that is, the stack frame address is also the address of the stack
2268 word that points to the previous frame. */
2270 /* The default is correct, but we need to make sure the frame gets created. */
2272 frv_dynamic_chain_address (rtx frame
)
2274 cfun
->machine
->frame_needed
= 1;
2279 /* A C expression whose value is RTL representing the value of the return
2280 address for the frame COUNT steps up from the current frame, after the
2281 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2282 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2285 The value of the expression must always be the correct address when COUNT is
2286 zero, but may be `NULL_RTX' if there is not way to determine the return
2287 address of other frames. */
2290 frv_return_addr_rtx (int count ATTRIBUTE_UNUSED
, rtx frame
)
2292 cfun
->machine
->frame_needed
= 1;
2293 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2296 /* Given a memory reference MEMREF, interpret the referenced memory as
2297 an array of MODE values, and return a reference to the element
2298 specified by INDEX. Assume that any pre-modification implicit in
2299 MEMREF has already happened.
2301 MEMREF must be a legitimate operand for modes larger than SImode.
2302 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2303 this function cannot handle. */
2305 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2307 rtx base
= XEXP (memref
, 0);
2308 if (GET_CODE (base
) == PRE_MODIFY
)
2309 base
= XEXP (base
, 0);
2310 return change_address (memref
, mode
,
2311 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2315 /* Print a memory address as an operand to reference that memory location. */
2317 frv_print_operand_address (FILE * stream
, rtx x
)
2319 if (GET_CODE (x
) == MEM
)
2322 switch (GET_CODE (x
))
2325 fputs (reg_names
[ REGNO (x
)], stream
);
2329 fprintf (stream
, "%ld", (long) INTVAL (x
));
2333 assemble_name (stream
, XSTR (x
, 0));
2338 output_addr_const (stream
, x
);
2345 fatal_insn ("Bad insn to frv_print_operand_address:", x
);
2350 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2352 int regno
= true_regnum (x
);
2354 fputs (reg_names
[regno
], stream
);
2356 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x
);
2359 /* Print a memory reference suitable for the ld/st instructions. */
2362 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2367 switch (GET_CODE (x
))
2374 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2376 x1
= XEXP (XEXP (x
, 1), 1);
2386 if (GET_CODE (x0
) == CONST_INT
)
2394 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2403 else if (GET_CODE (x1
) != CONST_INT
)
2404 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2407 fputs ("@(", stream
);
2409 fputs (reg_names
[GPR_R0
], stream
);
2410 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2411 frv_print_operand_memory_reference_reg (stream
, x0
);
2413 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2415 fputs (",", stream
);
2417 fputs (reg_names
[GPR_R0
], stream
);
2421 switch (GET_CODE (x1
))
2425 frv_print_operand_memory_reference_reg (stream
, x1
);
2429 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2433 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2434 && SYMBOL_REF_SMALL_P (x1
))
2436 fputs ("#gprel12(", stream
);
2437 assemble_name (stream
, XSTR (x1
, 0));
2438 fputs (")", stream
);
2441 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2445 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2446 && const_small_data_p (x1
))
2448 fputs ("#gprel12(", stream
);
2449 assemble_name (stream
, XSTR (XEXP (XEXP (x1
, 0), 0), 0));
2450 fprintf (stream
, "+"HOST_WIDE_INT_PRINT_DEC
")",
2451 INTVAL (XEXP (XEXP (x1
, 0), 1)));
2454 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2458 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2462 fputs (")", stream
);
2466 /* Return 2 for likely branches and 0 for non-likely branches */
2468 #define FRV_JUMP_LIKELY 2
2469 #define FRV_JUMP_NOT_LIKELY 0
2472 frv_print_operand_jump_hint (rtx insn
)
2477 HOST_WIDE_INT prob
= -1;
2478 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2480 if (GET_CODE (insn
) != JUMP_INSN
)
2483 /* Assume any non-conditional jump is likely. */
2484 if (! any_condjump_p (insn
))
2485 ret
= FRV_JUMP_LIKELY
;
2489 labelref
= condjump_label (insn
);
2492 rtx label
= XEXP (labelref
, 0);
2493 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2498 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2500 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2504 prob
= INTVAL (XEXP (note
, 0));
2505 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2507 : FRV_JUMP_NOT_LIKELY
);
2519 case UNKNOWN
: direction
= "unknown jump direction"; break;
2520 case BACKWARD
: direction
= "jump backward"; break;
2521 case FORWARD
: direction
= "jump forward"; break;
2525 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2526 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2527 (long)INSN_UID (insn
), direction
, (long)prob
,
2528 (long)REG_BR_PROB_BASE
, ret
);
2536 /* Print an operand to an assembler instruction.
2538 `%' followed by a letter and a digit says to output an operand in an
2539 alternate fashion. Four letters have standard, built-in meanings described
2540 below. The machine description macro `PRINT_OPERAND' can define additional
2541 letters with nonstandard meanings.
2543 `%cDIGIT' can be used to substitute an operand that is a constant value
2544 without the syntax that normally indicates an immediate operand.
2546 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2549 `%aDIGIT' can be used to substitute an operand as if it were a memory
2550 reference, with the actual operand treated as the address. This may be
2551 useful when outputting a "load address" instruction, because often the
2552 assembler syntax for such an instruction requires you to write the operand
2553 as if it were a memory reference.
2555 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2557 `%=' outputs a number which is unique to each instruction in the entire
2558 compilation. This is useful for making local labels to be referred to more
2559 than once in a single template that generates multiple assembler
2562 `%' followed by a punctuation character specifies a substitution that does
2563 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2564 assembler code. Other nonstandard cases can be defined in the
2565 `PRINT_OPERAND' macro. You must also define which punctuation characters
2566 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2569 frv_print_operand (FILE * file
, rtx x
, int code
)
2571 HOST_WIDE_INT value
;
2574 if (code
!= 0 && !isalpha (code
))
2577 else if (GET_CODE (x
) == CONST_INT
)
2580 else if (GET_CODE (x
) == CONST_DOUBLE
)
2582 if (GET_MODE (x
) == SFmode
)
2587 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2588 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2592 else if (GET_MODE (x
) == VOIDmode
)
2593 value
= CONST_DOUBLE_LOW (x
);
2596 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x
);
2607 fputs (reg_names
[GPR_R0
], file
);
2611 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2615 /* Output small data area base register (gr16). */
2616 fputs (reg_names
[SDA_BASE_REG
], file
);
2620 /* Output pic register (gr17). */
2621 fputs (reg_names
[PIC_REGNO
], file
);
2625 /* Output the temporary integer CCR register. */
2626 fputs (reg_names
[ICR_TEMP
], file
);
2630 /* Output the temporary integer CC register. */
2631 fputs (reg_names
[ICC_TEMP
], file
);
2634 /* case 'a': print an address. */
2637 /* Print appropriate test for integer branch false operation. */
2638 switch (GET_CODE (x
))
2641 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x
);
2643 case EQ
: fputs ("ne", file
); break;
2644 case NE
: fputs ("eq", file
); break;
2645 case LT
: fputs ("ge", file
); break;
2646 case LE
: fputs ("gt", file
); break;
2647 case GT
: fputs ("le", file
); break;
2648 case GE
: fputs ("lt", file
); break;
2649 case LTU
: fputs ("nc", file
); break;
2650 case LEU
: fputs ("hi", file
); break;
2651 case GTU
: fputs ("ls", file
); break;
2652 case GEU
: fputs ("c", file
); break;
2656 /* case 'c': print a constant without the constant prefix. If
2657 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2660 /* Print appropriate test for integer branch true operation. */
2661 switch (GET_CODE (x
))
2664 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x
);
2666 case EQ
: fputs ("eq", file
); break;
2667 case NE
: fputs ("ne", file
); break;
2668 case LT
: fputs ("lt", file
); break;
2669 case LE
: fputs ("le", file
); break;
2670 case GT
: fputs ("gt", file
); break;
2671 case GE
: fputs ("ge", file
); break;
2672 case LTU
: fputs ("c", file
); break;
2673 case LEU
: fputs ("ls", file
); break;
2674 case GTU
: fputs ("hi", file
); break;
2675 case GEU
: fputs ("nc", file
); break;
2680 /* Print 1 for a NE and 0 for an EQ to give the final argument
2681 for a conditional instruction. */
2682 if (GET_CODE (x
) == NE
)
2685 else if (GET_CODE (x
) == EQ
)
2689 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x
);
2693 /* Print appropriate test for floating point branch false operation. */
2694 switch (GET_CODE (x
))
2697 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x
);
2699 case EQ
: fputs ("ne", file
); break;
2700 case NE
: fputs ("eq", file
); break;
2701 case LT
: fputs ("uge", file
); break;
2702 case LE
: fputs ("ug", file
); break;
2703 case GT
: fputs ("ule", file
); break;
2704 case GE
: fputs ("ul", file
); break;
2709 /* Print appropriate test for floating point branch true operation. */
2710 switch (GET_CODE (x
))
2713 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x
);
2715 case EQ
: fputs ("eq", file
); break;
2716 case NE
: fputs ("ne", file
); break;
2717 case LT
: fputs ("lt", file
); break;
2718 case LE
: fputs ("le", file
); break;
2719 case GT
: fputs ("gt", file
); break;
2720 case GE
: fputs ("ge", file
); break;
2725 /* Print 'i' if the operand is a constant, or is a memory reference that
2727 if (GET_CODE (x
) == MEM
)
2728 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2729 ? XEXP (XEXP (x
, 0), 1)
2732 switch (GET_CODE (x
))
2746 /* For jump instructions, print 'i' if the operand is a constant or
2747 is an expression that adds a constant. */
2748 if (GET_CODE (x
) == CONST_INT
)
2753 if (GET_CODE (x
) == CONST_INT
2754 || (GET_CODE (x
) == PLUS
2755 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2756 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2762 /* Print the lower register of a double word register pair */
2763 if (GET_CODE (x
) == REG
)
2764 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2766 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x
);
2769 /* case 'l': print a LABEL_REF. */
2773 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2774 for the second word of double memory operations. */
2775 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2776 switch (GET_CODE (x
))
2779 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x
);
2782 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2790 frv_print_operand_memory_reference (file
, x
, offset
);
2796 /* Print the opcode of a command. */
2797 switch (GET_CODE (x
))
2800 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x
);
2802 case PLUS
: fputs ("add", file
); break;
2803 case MINUS
: fputs ("sub", file
); break;
2804 case AND
: fputs ("and", file
); break;
2805 case IOR
: fputs ("or", file
); break;
2806 case XOR
: fputs ("xor", file
); break;
2807 case ASHIFT
: fputs ("sll", file
); break;
2808 case ASHIFTRT
: fputs ("sra", file
); break;
2809 case LSHIFTRT
: fputs ("srl", file
); break;
2813 /* case 'n': negate and print a constant int. */
2816 /* Print PIC label using operand as the number. */
2817 if (GET_CODE (x
) != CONST_INT
)
2818 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x
);
2820 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2824 /* Print 'u' if the operand is a update load/store. */
2825 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2830 /* If value is 0, print gr0, otherwise it must be a register. */
2831 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2832 fputs (reg_names
[GPR_R0
], file
);
2834 else if (GET_CODE (x
) == REG
)
2835 fputs (reg_names
[REGNO (x
)], file
);
2838 fatal_insn ("Bad insn in frv_print_operand, z case", x
);
2842 /* Print constant in hex. */
2843 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2845 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
2852 if (GET_CODE (x
) == REG
)
2853 fputs (reg_names
[REGNO (x
)], file
);
2855 else if (GET_CODE (x
) == CONST_INT
2856 || GET_CODE (x
) == CONST_DOUBLE
)
2857 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
2859 else if (GET_CODE (x
) == MEM
)
2860 frv_print_operand_address (file
, XEXP (x
, 0));
2862 else if (CONSTANT_ADDRESS_P (x
))
2863 frv_print_operand_address (file
, x
);
2866 fatal_insn ("Bad insn in frv_print_operand, 0 case", x
);
2871 fatal_insn ("frv_print_operand: unknown code", x
);
2879 /* A C statement (sans semicolon) for initializing the variable CUM for the
2880 state at the beginning of the argument list. The variable has type
2881 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
2882 of the function which will receive the args, or 0 if the args are to a
2883 compiler support library function. The value of INDIRECT is nonzero when
2884 processing an indirect call, for example a call through a function pointer.
2885 The value of INDIRECT is zero for a call to an explicitly named function, a
2886 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
2887 arguments for the function being compiled.
2889 When processing a call to a compiler support library function, LIBNAME
2890 identifies which one. It is a `symbol_ref' rtx which contains the name of
2891 the function, as a string. LIBNAME is 0 when an ordinary C function call is
2892 being processed. Thus, each time this macro is called, either LIBNAME or
2893 FNTYPE is nonzero, but never both of them at once. */
2896 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
2902 *cum
= FIRST_ARG_REGNUM
;
2904 if (TARGET_DEBUG_ARG
)
2906 fprintf (stderr
, "\ninit_cumulative_args:");
2907 if (!fndecl
&& fntype
)
2908 fputs (" indirect", stderr
);
2911 fputs (" incoming", stderr
);
2915 tree ret_type
= TREE_TYPE (fntype
);
2916 fprintf (stderr
, " return=%s,",
2917 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2920 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
2921 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
2923 if (cfun
->returns_struct
)
2924 fprintf (stderr
, " return-struct");
2926 putc ('\n', stderr
);
2931 /* If defined, a C expression that gives the alignment boundary, in bits, of an
2932 argument with the specified mode and type. If it is not defined,
2933 `PARM_BOUNDARY' is used for all arguments. */
2936 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
2937 tree type ATTRIBUTE_UNUSED
)
2939 return BITS_PER_WORD
;
2943 /* A C expression that controls whether a function argument is passed in a
2944 register, and which register.
2946 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
2947 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
2948 arguments so far passed in registers; MODE, the machine mode of the argument;
2949 TYPE, the data type of the argument as a tree node or 0 if that is not known
2950 (which happens for C support library functions); and NAMED, which is 1 for an
2951 ordinary argument and 0 for nameless arguments that correspond to `...' in the
2952 called function's prototype.
2954 The value of the expression should either be a `reg' RTX for the hard
2955 register in which to pass the argument, or zero to pass the argument on the
2958 For machines like the VAX and 68000, where normally all arguments are
2959 pushed, zero suffices as a definition.
2961 The usual way to make the ANSI library `stdarg.h' work on a machine where
2962 some arguments are usually passed in registers, is to cause nameless
2963 arguments to be passed on the stack instead. This is done by making
2964 `FUNCTION_ARG' return 0 whenever NAMED is 0.
2966 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
2967 this macro to determine if this argument is of a type that must be passed in
2968 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
2969 returns nonzero for such an argument, the compiler will abort. If
2970 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
2971 stack and then loaded into a register. */
2974 frv_function_arg (CUMULATIVE_ARGS
*cum
,
2975 enum machine_mode mode
,
2976 tree type ATTRIBUTE_UNUSED
,
2978 int incoming ATTRIBUTE_UNUSED
)
2980 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
2985 /* Return a marker for use in the call instruction. */
2986 if (xmode
== VOIDmode
)
2992 else if (arg_num
<= LAST_ARG_REGNUM
)
2994 ret
= gen_rtx (REG
, xmode
, arg_num
);
2995 debstr
= reg_names
[arg_num
];
3004 if (TARGET_DEBUG_ARG
)
3006 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3007 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3013 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3014 advance past an argument in the argument list. The values MODE, TYPE and
3015 NAMED describe that argument. Once this is done, the variable CUM is
3016 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3018 This macro need not do anything if the argument in question was passed on
3019 the stack. The compiler knows how to track the amount of stack space used
3020 for arguments without any special help. */
3023 frv_function_arg_advance (CUMULATIVE_ARGS
*cum
,
3024 enum machine_mode mode
,
3025 tree type ATTRIBUTE_UNUSED
,
3028 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3029 int bytes
= GET_MODE_SIZE (xmode
);
3030 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3033 *cum
= arg_num
+ words
;
3035 if (TARGET_DEBUG_ARG
)
3037 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3038 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3042 /* A C expression for the number of words, at the beginning of an argument,
3043 must be put in registers. The value must be zero for arguments that are
3044 passed entirely in registers or that are entirely pushed on the stack.
3046 On some machines, certain arguments must be passed partially in registers
3047 and partially in memory. On these machines, typically the first N words of
3048 arguments are passed in registers, and the rest on the stack. If a
3049 multi-word argument (a `double' or a structure) crosses that boundary, its
3050 first few words must be passed in registers and the rest must be pushed.
3051 This macro tells the compiler when this occurs, and how many of the words
3052 should go in registers.
3054 `FUNCTION_ARG' for these arguments should return the first register to be
3055 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3056 the called function. */
3059 frv_function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
,
3060 enum machine_mode mode
,
3061 tree type ATTRIBUTE_UNUSED
,
3062 int named ATTRIBUTE_UNUSED
)
3064 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3065 int bytes
= GET_MODE_SIZE (xmode
);
3066 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3070 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3071 ? LAST_ARG_REGNUM
- arg_num
+ 1
3074 if (TARGET_DEBUG_ARG
&& ret
)
3075 fprintf (stderr
, "function_arg_partial_nregs: %d\n", ret
);
3083 /* A C expression that indicates when an argument must be passed by reference.
3084 If nonzero for an argument, a copy of that argument is made in memory and a
3085 pointer to the argument is passed instead of the argument itself. The
3086 pointer is passed in whatever way is appropriate for passing a pointer to
3089 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3090 definition of this macro might be
3091 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3092 MUST_PASS_IN_STACK (MODE, TYPE) */
3095 frv_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3096 enum machine_mode mode
,
3098 int named ATTRIBUTE_UNUSED
)
3100 return MUST_PASS_IN_STACK (mode
, type
);
3103 /* If defined, a C expression that indicates when it is the called function's
3104 responsibility to make a copy of arguments passed by invisible reference.
3105 Normally, the caller makes a copy and passes the address of the copy to the
3106 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3107 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3108 the "live" value. The called function must not modify this value. If it
3109 can be determined that the value won't be modified, it need not make a copy;
3110 otherwise a copy must be made. */
3113 frv_function_arg_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3114 enum machine_mode mode ATTRIBUTE_UNUSED
,
3115 tree type ATTRIBUTE_UNUSED
,
3116 int named ATTRIBUTE_UNUSED
)
3121 /* If defined, a C expression that indicates when it is more desirable to keep
3122 an argument passed by invisible reference as a reference, rather than
3123 copying it to a pseudo register. */
3126 frv_function_arg_keep_as_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3127 enum machine_mode mode ATTRIBUTE_UNUSED
,
3128 tree type ATTRIBUTE_UNUSED
,
3129 int named ATTRIBUTE_UNUSED
)
3135 /* Return true if a register is ok to use as a base or index register. */
3137 static FRV_INLINE
int
3138 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3144 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3146 if (regno
== ARG_POINTER_REGNUM
)
3149 return (regno
>= FIRST_PSEUDO_REGISTER
);
3153 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3154 RTX) is a legitimate memory address on the target machine for a memory
3155 operand of mode MODE.
3157 It usually pays to define several simpler macros to serve as subroutines for
3158 this one. Otherwise it may be too complicated to understand.
3160 This macro must exist in two variants: a strict variant and a non-strict
3161 one. The strict variant is used in the reload pass. It must be defined so
3162 that any pseudo-register that has not been allocated a hard register is
3163 considered a memory reference. In contexts where some kind of register is
3164 required, a pseudo-register with no hard register must be rejected.
3166 The non-strict variant is used in other passes. It must be defined to
3167 accept all pseudo-registers in every context where some kind of register is
3170 Compiler source files that want to use the strict variant of this macro
3171 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3172 conditional to define the strict variant in that case and the non-strict
3175 Subroutines to check for acceptable registers for various purposes (one for
3176 base registers, one for index registers, and so on) are typically among the
3177 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3178 subroutine macros need have two variants; the higher levels of macros may be
3179 the same whether strict or not.
3181 Normally, constant addresses which are the sum of a `symbol_ref' and an
3182 integer are stored inside a `const' RTX to mark them as constant.
3183 Therefore, there is no need to recognize such sums specifically as
3184 legitimate addresses. Normally you would simply recognize any `const' as
3187 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3188 are not marked with `const'. It assumes that a naked `plus' indicates
3189 indexing. If so, then you *must* reject such naked constant sums as
3190 illegitimate addresses, so that none of them will be given to
3191 `PRINT_OPERAND_ADDRESS'.
3193 On some machines, whether a symbolic address is legitimate depends on the
3194 section that the address refers to. On these machines, define the macro
3195 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3196 then check for it here. When you see a `const', you will have to look
3197 inside it to find the `symbol_ref' in order to determine the section.
3199 The best way to modify the name string is by adding text to the beginning,
3200 with suitable punctuation to prevent any ambiguity. Allocate the new name
3201 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3202 remove and decode the added text and output the name accordingly, and define
3203 `(* targetm.strip_name_encoding)' to access the original name string.
3205 You can check the information stored here into the `symbol_ref' in the
3206 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3207 `PRINT_OPERAND_ADDRESS'. */
3210 frv_legitimate_address_p (enum machine_mode mode
,
3217 HOST_WIDE_INT value
;
3220 switch (GET_CODE (x
))
3227 if (GET_CODE (x
) != REG
)
3233 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3239 if (GET_CODE (x0
) != REG
3240 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3241 || GET_CODE (x1
) != PLUS
3242 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3243 || GET_CODE (XEXP (x1
, 1)) != REG
3244 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3251 /* 12 bit immediate */
3256 ret
= IN_RANGE_P (INTVAL (x
), -2048, 2047);
3258 /* If we can't use load/store double operations, make sure we can
3259 address the second word. */
3260 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3261 ret
= IN_RANGE_P (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3270 if (GET_CODE (x0
) == SUBREG
)
3271 x0
= SUBREG_REG (x0
);
3273 if (GET_CODE (x0
) != REG
)
3276 regno0
= REGNO (x0
);
3277 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3280 switch (GET_CODE (x1
))
3286 x1
= SUBREG_REG (x1
);
3287 if (GET_CODE (x1
) != REG
)
3293 /* Do not allow reg+reg addressing for modes > 1 word if we
3294 can't depend on having move double instructions. */
3295 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3298 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3302 /* 12 bit immediate */
3307 value
= INTVAL (x1
);
3308 ret
= IN_RANGE_P (value
, -2048, 2047);
3310 /* If we can't use load/store double operations, make sure we can
3311 address the second word. */
3312 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3313 ret
= IN_RANGE_P (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3319 && regno0
== SDA_BASE_REG
3320 && SYMBOL_REF_SMALL_P (x1
))
3325 if (!condexec_p
&& regno0
== SDA_BASE_REG
&& const_small_data_p (x1
))
3333 if (TARGET_DEBUG_ADDR
)
3335 fprintf (stderr
, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3336 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3337 (condexec_p
) ? ", inside conditional code" : "");
3345 /* A C compound statement that attempts to replace X with a valid memory
3346 address for an operand of mode MODE. WIN will be a C statement label
3347 elsewhere in the code; the macro definition may use
3349 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3351 to avoid further processing if the address has become legitimate.
3353 X will always be the result of a call to `break_out_memory_refs', and OLDX
3354 will be the operand that was given to that function to produce X.
3356 The code generated by this macro should not alter the substructure of X. If
3357 it transforms X into a more legitimate form, it should assign X (which will
3358 always be a C variable) a new value.
3360 It is not necessary for this macro to come up with a legitimate address.
3361 The compiler has standard ways of doing so in all cases. In fact, it is
3362 safe for this macro to do nothing. But often a machine-dependent strategy
3363 can generate better code. */
3366 frv_legitimize_address (rtx x
,
3367 rtx oldx ATTRIBUTE_UNUSED
,
3368 enum machine_mode mode ATTRIBUTE_UNUSED
)
3372 /* Don't try to legitimize addresses if we are not optimizing, since the
3373 address we generate is not a general operand, and will horribly mess
3374 things up when force_reg is called to try and put it in a register because
3375 we aren't optimizing. */
3377 && ((GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (x
))
3378 || (GET_CODE (x
) == CONST
&& const_small_data_p (x
))))
3380 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, SDA_BASE_REG
), x
);
3382 cfun
->uses_pic_offset_table
= TRUE
;
3385 if (TARGET_DEBUG_ADDR
&& ret
!= NULL_RTX
)
3387 fprintf (stderr
, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3388 GET_MODE_NAME (mode
));
3395 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3396 the operand is used by a predicated instruction. */
3399 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3401 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3402 && GET_CODE (op
) == MEM
3403 && frv_legitimate_address_p (mode
, XEXP (op
, 0),
3404 reload_completed
, condexec_p
));
3408 /* Return 1 is OP is a memory operand, or will be turned into one by
3412 frv_load_operand (rtx op
, enum machine_mode mode
)
3414 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3417 if (reload_in_progress
)
3420 if (GET_CODE (tmp
) == SUBREG
)
3421 tmp
= SUBREG_REG (tmp
);
3422 if (GET_CODE (tmp
) == REG
3423 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
3424 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
3427 return op
&& memory_operand (op
, mode
);
3431 /* Return 1 if operand is a GPR register or a FPR register. */
3434 gpr_or_fpr_operand (rtx op
, enum machine_mode mode
)
3438 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3441 if (GET_CODE (op
) == SUBREG
)
3443 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3444 return register_operand (op
, mode
);
3446 op
= SUBREG_REG (op
);
3449 if (GET_CODE (op
) != REG
)
3453 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3459 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3462 gpr_or_int12_operand (rtx op
, enum machine_mode mode
)
3464 if (GET_CODE (op
) == CONST_INT
)
3465 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3467 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3470 if (GET_CODE (op
) == SUBREG
)
3472 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3473 return register_operand (op
, mode
);
3475 op
= SUBREG_REG (op
);
3478 if (GET_CODE (op
) != REG
)
3481 return GPR_OR_PSEUDO_P (REGNO (op
));
3484 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3485 signed immediate. */
3488 gpr_fpr_or_int12_operand (rtx op
, enum machine_mode mode
)
3492 if (GET_CODE (op
) == CONST_INT
)
3493 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3495 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3498 if (GET_CODE (op
) == SUBREG
)
3500 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3501 return register_operand (op
, mode
);
3503 op
= SUBREG_REG (op
);
3506 if (GET_CODE (op
) != REG
)
3510 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3516 /* Return 1 if operand is a register or 6 bit signed immediate. */
3519 fpr_or_int6_operand (rtx op
, enum machine_mode mode
)
3521 if (GET_CODE (op
) == CONST_INT
)
3522 return IN_RANGE_P (INTVAL (op
), -32, 31);
3524 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3527 if (GET_CODE (op
) == SUBREG
)
3529 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3530 return register_operand (op
, mode
);
3532 op
= SUBREG_REG (op
);
3535 if (GET_CODE (op
) != REG
)
3538 return FPR_OR_PSEUDO_P (REGNO (op
));
3541 /* Return 1 if operand is a register or 10 bit signed immediate. */
3544 gpr_or_int10_operand (rtx op
, enum machine_mode mode
)
3546 if (GET_CODE (op
) == CONST_INT
)
3547 return IN_RANGE_P (INTVAL (op
), -512, 511);
3549 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3552 if (GET_CODE (op
) == SUBREG
)
3554 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3555 return register_operand (op
, mode
);
3557 op
= SUBREG_REG (op
);
3560 if (GET_CODE (op
) != REG
)
3563 return GPR_OR_PSEUDO_P (REGNO (op
));
3566 /* Return 1 if operand is a register or an integer immediate. */
3569 gpr_or_int_operand (rtx op
, enum machine_mode mode
)
3571 if (GET_CODE (op
) == CONST_INT
)
3574 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3577 if (GET_CODE (op
) == SUBREG
)
3579 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3580 return register_operand (op
, mode
);
3582 op
= SUBREG_REG (op
);
3585 if (GET_CODE (op
) != REG
)
3588 return GPR_OR_PSEUDO_P (REGNO (op
));
3591 /* Return 1 if operand is a 12 bit signed immediate. */
3594 int12_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3596 if (GET_CODE (op
) != CONST_INT
)
3599 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3602 /* Return 1 if operand is a 6 bit signed immediate. */
3605 int6_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3607 if (GET_CODE (op
) != CONST_INT
)
3610 return IN_RANGE_P (INTVAL (op
), -32, 31);
3613 /* Return 1 if operand is a 5 bit signed immediate. */
3616 int5_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3618 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), -16, 15);
3621 /* Return 1 if operand is a 5 bit unsigned immediate. */
3624 uint5_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3626 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 31);
3629 /* Return 1 if operand is a 4 bit unsigned immediate. */
3632 uint4_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3634 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 15);
3637 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3640 uint1_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3642 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 1);
3645 /* Return 1 if operand is an integer constant that takes 2 instructions
3646 to load up and can be split into sethi/setlo instructions.. */
3649 int_2word_operand(rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3651 HOST_WIDE_INT value
;
3655 switch (GET_CODE (op
))
3661 return (flag_pic
== 0);
3664 /* small data references are already 1 word */
3665 return (flag_pic
== 0) && (! const_small_data_p (op
));
3668 /* small data references are already 1 word */
3669 return (flag_pic
== 0) && (! SYMBOL_REF_SMALL_P (op
));
3672 return ! IN_RANGE_P (INTVAL (op
), -32768, 32767);
3675 if (GET_MODE (op
) == SFmode
)
3677 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
3678 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
3680 return ! IN_RANGE_P (value
, -32768, 32767);
3682 else if (GET_MODE (op
) == VOIDmode
)
3684 value
= CONST_DOUBLE_LOW (op
);
3685 return ! IN_RANGE_P (value
, -32768, 32767);
3693 /* Return 1 if operand is the pic address register. */
3695 pic_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3700 if (GET_CODE (op
) != REG
)
3703 if (REGNO (op
) != PIC_REGNO
)
3709 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3710 that takes 3 separate instructions to form. */
3713 pic_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3718 switch (GET_CODE (op
))
3727 /* small data references are already 1 word */
3728 return ! SYMBOL_REF_SMALL_P (op
);
3731 /* small data references are already 1 word */
3732 return ! const_small_data_p (op
);
3738 /* Return 1 if operand is the small data register. */
3740 small_data_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3742 if (GET_CODE (op
) != REG
)
3745 if (REGNO (op
) != SDA_BASE_REG
)
3751 /* Return 1 if operand is a symbolic reference to a small data area static or
3755 small_data_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3757 switch (GET_CODE (op
))
3763 return const_small_data_p (op
);
3766 return SYMBOL_REF_SMALL_P (op
);
3772 /* Return 1 if operand is a 16 bit unsigned immediate. */
3775 uint16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3777 if (GET_CODE (op
) != CONST_INT
)
3780 return IN_RANGE_P (INTVAL (op
), 0, 0xffff);
3783 /* Return 1 if operand is an integer constant with the bottom 16 bits
3787 upper_int16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3789 if (GET_CODE (op
) != CONST_INT
)
3792 return ((INTVAL (op
) & 0xffff) == 0);
3795 /* Return true if operand is a GPR register. */
3798 integer_register_operand (rtx op
, enum machine_mode mode
)
3800 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3803 if (GET_CODE (op
) == SUBREG
)
3805 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3806 return register_operand (op
, mode
);
3808 op
= SUBREG_REG (op
);
3811 if (GET_CODE (op
) != REG
)
3814 return GPR_OR_PSEUDO_P (REGNO (op
));
3817 /* Return true if operand is a GPR register. Do not allow SUBREG's
3818 here, in order to prevent a combine bug. */
3821 gpr_no_subreg_operand (rtx op
, enum machine_mode mode
)
3823 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3826 if (GET_CODE (op
) != REG
)
3829 return GPR_OR_PSEUDO_P (REGNO (op
));
3832 /* Return true if operand is a FPR register. */
3835 fpr_operand (rtx op
, enum machine_mode mode
)
3837 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3840 if (GET_CODE (op
) == SUBREG
)
3842 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3843 return register_operand (op
, mode
);
3845 op
= SUBREG_REG (op
);
3848 if (GET_CODE (op
) != REG
)
3851 return FPR_OR_PSEUDO_P (REGNO (op
));
3854 /* Return true if operand is an even GPR or FPR register. */
3857 even_reg_operand (rtx op
, enum machine_mode mode
)
3861 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3864 if (GET_CODE (op
) == SUBREG
)
3866 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3867 return register_operand (op
, mode
);
3869 op
= SUBREG_REG (op
);
3872 if (GET_CODE (op
) != REG
)
3876 if (regno
>= FIRST_PSEUDO_REGISTER
)
3880 return (((regno
- GPR_FIRST
) & 1) == 0);
3883 return (((regno
- FPR_FIRST
) & 1) == 0);
3888 /* Return true if operand is an odd GPR register. */
3891 odd_reg_operand (rtx op
, enum machine_mode mode
)
3895 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3898 if (GET_CODE (op
) == SUBREG
)
3900 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3901 return register_operand (op
, mode
);
3903 op
= SUBREG_REG (op
);
3906 if (GET_CODE (op
) != REG
)
3910 /* Assume that reload will give us an even register. */
3911 if (regno
>= FIRST_PSEUDO_REGISTER
)
3915 return (((regno
- GPR_FIRST
) & 1) != 0);
3918 return (((regno
- FPR_FIRST
) & 1) != 0);
3923 /* Return true if operand is an even GPR register. */
3926 even_gpr_operand (rtx op
, enum machine_mode mode
)
3930 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3933 if (GET_CODE (op
) == SUBREG
)
3935 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3936 return register_operand (op
, mode
);
3938 op
= SUBREG_REG (op
);
3941 if (GET_CODE (op
) != REG
)
3945 if (regno
>= FIRST_PSEUDO_REGISTER
)
3948 if (! GPR_P (regno
))
3951 return (((regno
- GPR_FIRST
) & 1) == 0);
3954 /* Return true if operand is an odd GPR register. */
3957 odd_gpr_operand (rtx op
, enum machine_mode mode
)
3961 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3964 if (GET_CODE (op
) == SUBREG
)
3966 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3967 return register_operand (op
, mode
);
3969 op
= SUBREG_REG (op
);
3972 if (GET_CODE (op
) != REG
)
3976 /* Assume that reload will give us an even register. */
3977 if (regno
>= FIRST_PSEUDO_REGISTER
)
3980 if (! GPR_P (regno
))
3983 return (((regno
- GPR_FIRST
) & 1) != 0);
3986 /* Return true if operand is a quad aligned FPR register. */
3989 quad_fpr_operand (rtx op
, enum machine_mode mode
)
3993 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3996 if (GET_CODE (op
) == SUBREG
)
3998 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3999 return register_operand (op
, mode
);
4001 op
= SUBREG_REG (op
);
4004 if (GET_CODE (op
) != REG
)
4008 if (regno
>= FIRST_PSEUDO_REGISTER
)
4011 if (! FPR_P (regno
))
4014 return (((regno
- FPR_FIRST
) & 3) == 0);
4017 /* Return true if operand is an even FPR register. */
4020 even_fpr_operand (rtx op
, enum machine_mode mode
)
4024 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4027 if (GET_CODE (op
) == SUBREG
)
4029 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4030 return register_operand (op
, mode
);
4032 op
= SUBREG_REG (op
);
4035 if (GET_CODE (op
) != REG
)
4039 if (regno
>= FIRST_PSEUDO_REGISTER
)
4042 if (! FPR_P (regno
))
4045 return (((regno
- FPR_FIRST
) & 1) == 0);
4048 /* Return true if operand is an odd FPR register. */
4051 odd_fpr_operand (rtx op
, enum machine_mode mode
)
4055 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4058 if (GET_CODE (op
) == SUBREG
)
4060 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4061 return register_operand (op
, mode
);
4063 op
= SUBREG_REG (op
);
4066 if (GET_CODE (op
) != REG
)
4070 /* Assume that reload will give us an even register. */
4071 if (regno
>= FIRST_PSEUDO_REGISTER
)
4074 if (! FPR_P (regno
))
4077 return (((regno
- FPR_FIRST
) & 1) != 0);
4080 /* Return true if operand is a 2 word memory address that can be loaded in one
4081 instruction to load or store. We assume the stack and frame pointers are
4082 suitably aligned, and variables in the small data area. FIXME -- at some we
4083 should recognize other globals and statics. We can't assume that any old
4084 pointer is aligned, given that arguments could be passed on an odd word on
4085 the stack and the address taken and passed through to another function. */
4088 dbl_memory_one_insn_operand (rtx op
, enum machine_mode mode
)
4096 if (GET_CODE (op
) != MEM
)
4099 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4102 addr
= XEXP (op
, 0);
4103 if (GET_CODE (addr
) == REG
)
4106 else if (GET_CODE (addr
) == PLUS
)
4108 rtx addr0
= XEXP (addr
, 0);
4109 rtx addr1
= XEXP (addr
, 1);
4111 if (GET_CODE (addr0
) != REG
)
4114 if (plus_small_data_p (addr0
, addr1
))
4117 if (GET_CODE (addr1
) != CONST_INT
)
4120 if ((INTVAL (addr1
) & 7) != 0)
4129 if (addr_reg
== frame_pointer_rtx
|| addr_reg
== stack_pointer_rtx
)
4135 /* Return true if operand is a 2 word memory address that needs to
4136 use two instructions to load or store. */
4139 dbl_memory_two_insn_operand (rtx op
, enum machine_mode mode
)
4141 if (GET_CODE (op
) != MEM
)
4144 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4150 return ! dbl_memory_one_insn_operand (op
, mode
);
4153 /* Return true if operand is something that can be an output for a move
4157 move_destination_operand (rtx op
, enum machine_mode mode
)
4162 switch (GET_CODE (op
))
4168 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4171 subreg
= SUBREG_REG (op
);
4172 code
= GET_CODE (subreg
);
4174 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4175 reload_completed
, FALSE
);
4177 return (code
== REG
);
4180 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4186 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4189 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4195 /* Return true if operand is something that can be an input for a move
4199 move_source_operand (rtx op
, enum machine_mode mode
)
4204 switch (GET_CODE (op
))
4214 return immediate_operand (op
, mode
);
4217 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4220 subreg
= SUBREG_REG (op
);
4221 code
= GET_CODE (subreg
);
4223 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4224 reload_completed
, FALSE
);
4226 return (code
== REG
);
4229 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4235 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4238 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4244 /* Return true if operand is something that can be an output for a conditional
4248 condexec_dest_operand (rtx op
, enum machine_mode mode
)
4253 switch (GET_CODE (op
))
4259 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4262 subreg
= SUBREG_REG (op
);
4263 code
= GET_CODE (subreg
);
4265 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4266 reload_completed
, TRUE
);
4268 return (code
== REG
);
4271 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4277 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4280 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4286 /* Return true if operand is something that can be an input for a conditional
4290 condexec_source_operand (rtx op
, enum machine_mode mode
)
4295 switch (GET_CODE (op
))
4305 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4308 subreg
= SUBREG_REG (op
);
4309 code
= GET_CODE (subreg
);
4311 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4312 reload_completed
, TRUE
);
4314 return (code
== REG
);
4317 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4323 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4326 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4332 /* Return true if operand is a register of any flavor or a 0 of the
4333 appropriate type. */
4336 reg_or_0_operand (rtx op
, enum machine_mode mode
)
4338 switch (GET_CODE (op
))
4345 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4348 return register_operand (op
, mode
);
4358 /* Return true if operand is the link register. */
4361 lr_operand (rtx op
, enum machine_mode mode
)
4363 if (GET_CODE (op
) != REG
)
4366 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4369 if (REGNO (op
) != LR_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
4375 /* Return true if operand is a gpr register or a valid memory operation. */
4378 gpr_or_memory_operand (rtx op
, enum machine_mode mode
)
4380 return (integer_register_operand (op
, mode
)
4381 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4384 /* Return true if operand is a fpr register or a valid memory operation. */
4387 fpr_or_memory_operand (rtx op
, enum machine_mode mode
)
4389 return (fpr_operand (op
, mode
)
4390 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4393 /* Return true if operand is an icc register. */
4396 icc_operand (rtx op
, enum machine_mode mode
)
4400 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4403 if (GET_CODE (op
) != REG
)
4407 return ICC_OR_PSEUDO_P (regno
);
4410 /* Return true if operand is an fcc register. */
4413 fcc_operand (rtx op
, enum machine_mode mode
)
4417 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4420 if (GET_CODE (op
) != REG
)
4424 return FCC_OR_PSEUDO_P (regno
);
4427 /* Return true if operand is either an fcc or icc register. */
4430 cc_operand (rtx op
, enum machine_mode mode
)
4434 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4437 if (GET_CODE (op
) != REG
)
4441 if (CC_OR_PSEUDO_P (regno
))
4447 /* Return true if operand is an integer CCR register. */
4450 icr_operand (rtx op
, enum machine_mode mode
)
4454 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4457 if (GET_CODE (op
) != REG
)
4461 return ICR_OR_PSEUDO_P (regno
);
4464 /* Return true if operand is an fcc register. */
4467 fcr_operand (rtx op
, enum machine_mode mode
)
4471 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4474 if (GET_CODE (op
) != REG
)
4478 return FCR_OR_PSEUDO_P (regno
);
4481 /* Return true if operand is either an fcc or icc register. */
4484 cr_operand (rtx op
, enum machine_mode mode
)
4488 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4491 if (GET_CODE (op
) != REG
)
4495 if (CR_OR_PSEUDO_P (regno
))
4501 /* Return true if operand is a memory reference suitable for a call. */
4504 call_operand (rtx op
, enum machine_mode mode
)
4506 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
&& GET_CODE (op
) != CONST_INT
)
4509 if (GET_CODE (op
) == SYMBOL_REF
)
4512 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4513 never occur anyway), but prevents reload from not handling the case
4514 properly of a call through a pointer on a function that calls
4515 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4516 return gpr_or_int12_operand (op
, mode
);
4519 /* Return true if operator is a kind of relational operator. */
4522 relational_operator (rtx op
, enum machine_mode mode
)
4528 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4531 switch (GET_CODE (op
))
4550 if (op1
!= const0_rtx
)
4554 if (GET_CODE (op0
) != REG
)
4557 regno
= REGNO (op0
);
4558 switch (GET_MODE (op0
))
4565 return ICC_OR_PSEUDO_P (regno
);
4568 return FCC_OR_PSEUDO_P (regno
);
4571 return CR_OR_PSEUDO_P (regno
);
4577 /* Return true if operator is a signed integer relational operator. */
4580 signed_relational_operator (rtx op
, enum machine_mode mode
)
4586 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4589 switch (GET_CODE (op
))
4604 if (op1
!= const0_rtx
)
4608 if (GET_CODE (op0
) != REG
)
4611 regno
= REGNO (op0
);
4612 if (GET_MODE (op0
) == CCmode
&& ICC_OR_PSEUDO_P (regno
))
4615 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4621 /* Return true if operator is a signed integer relational operator. */
4624 unsigned_relational_operator (rtx op
, enum machine_mode mode
)
4630 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4633 switch (GET_CODE (op
))
4646 if (op1
!= const0_rtx
)
4650 if (GET_CODE (op0
) != REG
)
4653 regno
= REGNO (op0
);
4654 if (GET_MODE (op0
) == CC_UNSmode
&& ICC_OR_PSEUDO_P (regno
))
4657 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4663 /* Return true if operator is a floating point relational operator. */
4666 float_relational_operator (rtx op
, enum machine_mode mode
)
4672 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4675 switch (GET_CODE (op
))
4694 if (op1
!= const0_rtx
)
4698 if (GET_CODE (op0
) != REG
)
4701 regno
= REGNO (op0
);
4702 if (GET_MODE (op0
) == CC_FPmode
&& FCC_OR_PSEUDO_P (regno
))
4705 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4711 /* Return true if operator is EQ/NE of a conditional execution register. */
4714 ccr_eqne_operator (rtx op
, enum machine_mode mode
)
4716 enum machine_mode op_mode
= GET_MODE (op
);
4721 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4724 switch (GET_CODE (op
))
4735 if (op1
!= const0_rtx
)
4739 if (GET_CODE (op0
) != REG
)
4742 regno
= REGNO (op0
);
4743 if (op_mode
== CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4749 /* Return true if operator is a minimum or maximum operator (both signed and
4753 minmax_operator (rtx op
, enum machine_mode mode
)
4755 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4758 switch (GET_CODE (op
))
4770 if (! integer_register_operand (XEXP (op
, 0), mode
))
4773 if (! gpr_or_int10_operand (XEXP (op
, 1), mode
))
4779 /* Return true if operator is an integer binary operator that can executed
4780 conditionally and takes 1 cycle. */
4783 condexec_si_binary_operator (rtx op
, enum machine_mode mode
)
4785 enum machine_mode op_mode
= GET_MODE (op
);
4787 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4790 switch (GET_CODE (op
))
4807 /* Return true if operator is an integer binary operator that can be
4808 executed conditionally by a media instruction. */
4811 condexec_si_media_operator (rtx op
, enum machine_mode mode
)
4813 enum machine_mode op_mode
= GET_MODE (op
);
4815 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4818 switch (GET_CODE (op
))
4830 /* Return true if operator is an integer division operator that can executed
4834 condexec_si_divide_operator (rtx op
, enum machine_mode mode
)
4836 enum machine_mode op_mode
= GET_MODE (op
);
4838 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4841 switch (GET_CODE (op
))
4852 /* Return true if operator is an integer unary operator that can executed
4856 condexec_si_unary_operator (rtx op
, enum machine_mode mode
)
4858 enum machine_mode op_mode
= GET_MODE (op
);
4860 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4863 switch (GET_CODE (op
))
4874 /* Return true if operator is a conversion-type expression that can be
4875 evaluated conditionally by floating-point instructions. */
4878 condexec_sf_conv_operator (rtx op
, enum machine_mode mode
)
4880 enum machine_mode op_mode
= GET_MODE (op
);
4882 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4885 switch (GET_CODE (op
))
4896 /* Return true if operator is an addition or subtraction expression.
4897 Such expressions can be evaluated conditionally by floating-point
4901 condexec_sf_add_operator (rtx op
, enum machine_mode mode
)
4903 enum machine_mode op_mode
= GET_MODE (op
);
4905 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4908 switch (GET_CODE (op
))
4919 /* Return true if the memory operand is one that can be conditionally
4923 condexec_memory_operand (rtx op
, enum machine_mode mode
)
4925 enum machine_mode op_mode
= GET_MODE (op
);
4928 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4943 if (GET_CODE (op
) != MEM
)
4946 addr
= XEXP (op
, 0);
4947 if (GET_CODE (addr
) == ADDRESSOF
)
4950 return frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
);
4953 /* Return true if operator is an integer binary operator that can be combined
4954 with a setcc operation. Do not allow the arithmetic operations that could
4955 potentially overflow since the FR-V sets the condition code based on the
4956 "true" value of the result, not the result after truncating to a 32-bit
4960 intop_compare_operator (rtx op
, enum machine_mode mode
)
4962 enum machine_mode op_mode
= GET_MODE (op
);
4964 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4967 switch (GET_CODE (op
))
4980 if (! integer_register_operand (XEXP (op
, 0), SImode
))
4983 if (! gpr_or_int10_operand (XEXP (op
, 1), SImode
))
4989 /* Return true if operator is an integer binary operator that can be combined
4990 with a setcc operation inside of a conditional execution. */
4993 condexec_intop_cmp_operator (rtx op
, enum machine_mode mode
)
4995 enum machine_mode op_mode
= GET_MODE (op
);
4997 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5000 switch (GET_CODE (op
))
5013 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5016 if (! integer_register_operand (XEXP (op
, 1), SImode
))
5022 /* Return 1 if operand is a valid ACC register number. */
5025 acc_operand (rtx op
, enum machine_mode mode
)
5029 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5032 if (GET_CODE (op
) == SUBREG
)
5034 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5035 return register_operand (op
, mode
);
5037 op
= SUBREG_REG (op
);
5040 if (GET_CODE (op
) != REG
)
5044 return ACC_OR_PSEUDO_P (regno
);
5047 /* Return 1 if operand is a valid even ACC register number. */
5050 even_acc_operand (rtx op
, enum machine_mode mode
)
5054 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5057 if (GET_CODE (op
) == SUBREG
)
5059 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5060 return register_operand (op
, mode
);
5062 op
= SUBREG_REG (op
);
5065 if (GET_CODE (op
) != REG
)
5069 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 1) == 0);
5072 /* Return 1 if operand is zero or four. */
5075 quad_acc_operand (rtx op
, enum machine_mode mode
)
5079 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5082 if (GET_CODE (op
) == SUBREG
)
5084 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5085 return register_operand (op
, mode
);
5087 op
= SUBREG_REG (op
);
5090 if (GET_CODE (op
) != REG
)
5094 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 3) == 0);
5097 /* Return 1 if operand is a valid ACCG register number. */
5100 accg_operand (rtx op
, enum machine_mode mode
)
5102 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5105 if (GET_CODE (op
) == SUBREG
)
5107 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5108 return register_operand (op
, mode
);
5110 op
= SUBREG_REG (op
);
5113 if (GET_CODE (op
) != REG
)
5116 return ACCG_OR_PSEUDO_P (REGNO (op
));
5120 /* Return true if the bare return instruction can be used outside of the
5121 epilog code. For frv, we only do it if there was no stack allocation. */
5124 direct_return_p (void)
5128 if (!reload_completed
)
5131 info
= frv_stack_info ();
5132 return (info
->total_size
== 0);
5136 /* Emit code to handle a MOVSI, adding in the small data register or pic
5137 register if needed to load up addresses. Return TRUE if the appropriate
5138 instructions are emitted. */
5141 frv_emit_movsi (rtx dest
, rtx src
)
5143 int base_regno
= -1;
5145 if (!reload_in_progress
5146 && !reload_completed
5147 && !register_operand (dest
, SImode
)
5148 && (!reg_or_0_operand (src
, SImode
)
5149 /* Virtual registers will almost always be replaced by an
5150 add instruction, so expose this to CSE by copying to
5151 an intermediate register. */
5152 || (GET_CODE (src
) == REG
5153 && IN_RANGE_P (REGNO (src
),
5154 FIRST_VIRTUAL_REGISTER
,
5155 LAST_VIRTUAL_REGISTER
))))
5157 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
5161 /* Explicitly add in the PIC or small data register if needed. */
5162 switch (GET_CODE (src
))
5169 base_regno
= PIC_REGNO
;
5174 if (const_small_data_p (src
))
5175 base_regno
= SDA_BASE_REG
;
5178 base_regno
= PIC_REGNO
;
5183 if (SYMBOL_REF_SMALL_P (src
))
5184 base_regno
= SDA_BASE_REG
;
5187 base_regno
= PIC_REGNO
;
5192 if (base_regno
>= 0)
5194 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
5195 gen_rtx_PLUS (Pmode
,
5196 gen_rtx_REG (Pmode
, base_regno
),
5199 if (base_regno
== PIC_REGNO
)
5200 cfun
->uses_pic_offset_table
= TRUE
;
5209 /* Return a string to output a single word move. */
5212 output_move_single (rtx operands
[], rtx insn
)
5214 rtx dest
= operands
[0];
5215 rtx src
= operands
[1];
5217 if (GET_CODE (dest
) == REG
)
5219 int dest_regno
= REGNO (dest
);
5220 enum machine_mode mode
= GET_MODE (dest
);
5222 if (GPR_P (dest_regno
))
5224 if (GET_CODE (src
) == REG
)
5226 /* gpr <- some sort of register */
5227 int src_regno
= REGNO (src
);
5229 if (GPR_P (src_regno
))
5230 return "mov %1, %0";
5232 else if (FPR_P (src_regno
))
5233 return "movfg %1, %0";
5235 else if (SPR_P (src_regno
))
5236 return "movsg %1, %0";
5239 else if (GET_CODE (src
) == MEM
)
5248 return "ldsb%I1%U1 %M1,%0";
5251 return "ldsh%I1%U1 %M1,%0";
5255 return "ld%I1%U1 %M1, %0";
5259 else if (GET_CODE (src
) == CONST_INT
5260 || GET_CODE (src
) == CONST_DOUBLE
)
5262 /* gpr <- integer/floating constant */
5263 HOST_WIDE_INT value
;
5265 if (GET_CODE (src
) == CONST_INT
)
5266 value
= INTVAL (src
);
5268 else if (mode
== SFmode
)
5273 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
5274 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5279 value
= CONST_DOUBLE_LOW (src
);
5281 if (IN_RANGE_P (value
, -32768, 32767))
5282 return "setlos %1, %0";
5287 else if (GET_CODE (src
) == SYMBOL_REF
5288 || GET_CODE (src
) == LABEL_REF
5289 || GET_CODE (src
) == CONST
)
5291 /* Silently fix up instances where the small data pointer is not
5292 used in the address. */
5293 if (small_data_symbolic_operand (src
, GET_MODE (src
)))
5294 return "addi %@, #gprel12(%1), %0";
5300 else if (FPR_P (dest_regno
))
5302 if (GET_CODE (src
) == REG
)
5304 /* fpr <- some sort of register */
5305 int src_regno
= REGNO (src
);
5307 if (GPR_P (src_regno
))
5308 return "movgf %1, %0";
5310 else if (FPR_P (src_regno
))
5312 if (TARGET_HARD_FLOAT
)
5313 return "fmovs %1, %0";
5315 return "mor %1, %1, %0";
5319 else if (GET_CODE (src
) == MEM
)
5328 return "ldbf%I1%U1 %M1,%0";
5331 return "ldhf%I1%U1 %M1,%0";
5335 return "ldf%I1%U1 %M1, %0";
5339 else if (ZERO_P (src
))
5340 return "movgf %., %0";
5343 else if (SPR_P (dest_regno
))
5345 if (GET_CODE (src
) == REG
)
5347 /* spr <- some sort of register */
5348 int src_regno
= REGNO (src
);
5350 if (GPR_P (src_regno
))
5351 return "movgs %1, %0";
5356 else if (GET_CODE (dest
) == MEM
)
5358 if (GET_CODE (src
) == REG
)
5360 int src_regno
= REGNO (src
);
5361 enum machine_mode mode
= GET_MODE (dest
);
5363 if (GPR_P (src_regno
))
5371 return "stb%I0%U0 %1, %M0";
5374 return "sth%I0%U0 %1, %M0";
5378 return "st%I0%U0 %1, %M0";
5382 else if (FPR_P (src_regno
))
5390 return "stbf%I0%U0 %1, %M0";
5393 return "sthf%I0%U0 %1, %M0";
5397 return "stf%I0%U0 %1, %M0";
5402 else if (ZERO_P (src
))
5404 switch (GET_MODE (dest
))
5410 return "stb%I0%U0 %., %M0";
5413 return "sth%I0%U0 %., %M0";
5417 return "st%I0%U0 %., %M0";
5422 fatal_insn ("Bad output_move_single operand", insn
);
5427 /* Return a string to output a double word move. */
5430 output_move_double (rtx operands
[], rtx insn
)
5432 rtx dest
= operands
[0];
5433 rtx src
= operands
[1];
5434 enum machine_mode mode
= GET_MODE (dest
);
5436 if (GET_CODE (dest
) == REG
)
5438 int dest_regno
= REGNO (dest
);
5440 if (GPR_P (dest_regno
))
5442 if (GET_CODE (src
) == REG
)
5444 /* gpr <- some sort of register */
5445 int src_regno
= REGNO (src
);
5447 if (GPR_P (src_regno
))
5450 else if (FPR_P (src_regno
))
5452 if (((dest_regno
- GPR_FIRST
) & 1) == 0
5453 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5454 return "movfgd %1, %0";
5460 else if (GET_CODE (src
) == MEM
)
5463 if (dbl_memory_one_insn_operand (src
, mode
))
5464 return "ldd%I1%U1 %M1, %0";
5469 else if (GET_CODE (src
) == CONST_INT
5470 || GET_CODE (src
) == CONST_DOUBLE
)
5474 else if (FPR_P (dest_regno
))
5476 if (GET_CODE (src
) == REG
)
5478 /* fpr <- some sort of register */
5479 int src_regno
= REGNO (src
);
5481 if (GPR_P (src_regno
))
5483 if (((dest_regno
- FPR_FIRST
) & 1) == 0
5484 && ((src_regno
- GPR_FIRST
) & 1) == 0)
5485 return "movgfd %1, %0";
5490 else if (FPR_P (src_regno
))
5493 && ((dest_regno
- FPR_FIRST
) & 1) == 0
5494 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5495 return "fmovd %1, %0";
5501 else if (GET_CODE (src
) == MEM
)
5504 if (dbl_memory_one_insn_operand (src
, mode
))
5505 return "lddf%I1%U1 %M1, %0";
5510 else if (ZERO_P (src
))
5515 else if (GET_CODE (dest
) == MEM
)
5517 if (GET_CODE (src
) == REG
)
5519 int src_regno
= REGNO (src
);
5521 if (GPR_P (src_regno
))
5523 if (((src_regno
- GPR_FIRST
) & 1) == 0
5524 && dbl_memory_one_insn_operand (dest
, mode
))
5525 return "std%I0%U0 %1, %M0";
5530 if (FPR_P (src_regno
))
5532 if (((src_regno
- FPR_FIRST
) & 1) == 0
5533 && dbl_memory_one_insn_operand (dest
, mode
))
5534 return "stdf%I0%U0 %1, %M0";
5540 else if (ZERO_P (src
))
5542 if (dbl_memory_one_insn_operand (dest
, mode
))
5543 return "std%I0%U0 %., %M0";
5549 fatal_insn ("Bad output_move_double operand", insn
);
5554 /* Return a string to output a single word conditional move.
5555 Operand0 -- EQ/NE of ccr register and 0
5556 Operand1 -- CCR register
5557 Operand2 -- destination
5558 Operand3 -- source */
5561 output_condmove_single (rtx operands
[], rtx insn
)
5563 rtx dest
= operands
[2];
5564 rtx src
= operands
[3];
5566 if (GET_CODE (dest
) == REG
)
5568 int dest_regno
= REGNO (dest
);
5569 enum machine_mode mode
= GET_MODE (dest
);
5571 if (GPR_P (dest_regno
))
5573 if (GET_CODE (src
) == REG
)
5575 /* gpr <- some sort of register */
5576 int src_regno
= REGNO (src
);
5578 if (GPR_P (src_regno
))
5579 return "cmov %z3, %2, %1, %e0";
5581 else if (FPR_P (src_regno
))
5582 return "cmovfg %3, %2, %1, %e0";
5585 else if (GET_CODE (src
) == MEM
)
5594 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5597 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5601 return "cld%I3%U3 %M3, %2, %1, %e0";
5605 else if (ZERO_P (src
))
5606 return "cmov %., %2, %1, %e0";
5609 else if (FPR_P (dest_regno
))
5611 if (GET_CODE (src
) == REG
)
5613 /* fpr <- some sort of register */
5614 int src_regno
= REGNO (src
);
5616 if (GPR_P (src_regno
))
5617 return "cmovgf %3, %2, %1, %e0";
5619 else if (FPR_P (src_regno
))
5621 if (TARGET_HARD_FLOAT
)
5622 return "cfmovs %3,%2,%1,%e0";
5624 return "cmor %3, %3, %2, %1, %e0";
5628 else if (GET_CODE (src
) == MEM
)
5631 if (mode
== SImode
|| mode
== SFmode
)
5632 return "cldf%I3%U3 %M3, %2, %1, %e0";
5635 else if (ZERO_P (src
))
5636 return "cmovgf %., %2, %1, %e0";
5640 else if (GET_CODE (dest
) == MEM
)
5642 if (GET_CODE (src
) == REG
)
5644 int src_regno
= REGNO (src
);
5645 enum machine_mode mode
= GET_MODE (dest
);
5647 if (GPR_P (src_regno
))
5655 return "cstb%I2%U2 %3, %M2, %1, %e0";
5658 return "csth%I2%U2 %3, %M2, %1, %e0";
5662 return "cst%I2%U2 %3, %M2, %1, %e0";
5666 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
5667 return "cstf%I2%U2 %3, %M2, %1, %e0";
5670 else if (ZERO_P (src
))
5672 enum machine_mode mode
= GET_MODE (dest
);
5679 return "cstb%I2%U2 %., %M2, %1, %e0";
5682 return "csth%I2%U2 %., %M2, %1, %e0";
5686 return "cst%I2%U2 %., %M2, %1, %e0";
5691 fatal_insn ("Bad output_condmove_single operand", insn
);
5696 /* Emit the appropriate code to do a comparison, returning the register the
5697 comparison was done it. */
5700 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
5702 enum machine_mode cc_mode
;
5705 /* Floating point doesn't have comparison against a constant. */
5706 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
5707 op1
= force_reg (GET_MODE (op0
), op1
);
5709 /* Possibly disable using anything but a fixed register in order to work
5710 around cse moving comparisons past function calls. */
5711 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
5712 cc_reg
= ((TARGET_ALLOC_CC
)
5713 ? gen_reg_rtx (cc_mode
)
5714 : gen_rtx_REG (cc_mode
,
5715 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
5717 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
5718 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
5724 /* Emit code for a conditional branch. The comparison operands were previously
5725 stored in frv_compare_op0 and frv_compare_op1.
5727 XXX: I originally wanted to add a clobber of a CCR register to use in
5728 conditional execution, but that confuses the rest of the compiler. */
5731 frv_emit_cond_branch (enum rtx_code test
, rtx label
)
5736 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
5737 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
5739 /* Branches generate:
5741 (if_then_else (<test>, <cc_reg>, (const_int 0))
5742 (label_ref <branch_label>)
5744 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
5745 test_rtx
= gen_rtx (test
, cc_mode
, cc_reg
, const0_rtx
);
5746 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
5747 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
5752 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
5753 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
5756 frv_emit_scc (enum rtx_code test
, rtx target
)
5762 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
5764 /* SCC instructions generate:
5765 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
5766 (clobber (<ccr_reg>))]) */
5767 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
5768 set
= gen_rtx_SET (VOIDmode
, target
, test_rtx
);
5770 cr_reg
= ((TARGET_ALLOC_CC
)
5771 ? gen_reg_rtx (CC_CCRmode
)
5772 : gen_rtx_REG (CC_CCRmode
,
5773 ((GET_MODE (cc_reg
) == CC_FPmode
)
5777 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
5778 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
5783 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
5784 the separate insns. */
5787 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
5793 /* Set the appropriate CCR bit. */
5794 emit_insn (gen_rtx_SET (VOIDmode
,
5796 gen_rtx_fmt_ee (GET_CODE (test
),
5801 /* Move the value into the destination. */
5802 emit_move_insn (dest
, GEN_INT (value
));
5804 /* Move 0 into the destination if the test failed */
5805 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5806 gen_rtx_EQ (GET_MODE (cr_reg
),
5809 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
5811 /* Finish up, return sequence. */
5818 /* Emit the code for a conditional move, return TRUE if we could do the
5822 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
5829 enum rtx_code test
= GET_CODE (test_rtx
);
5830 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
5831 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
5833 /* Conditional move instructions generate:
5834 (parallel [(set <target>
5835 (if_then_else (<test> <cc_reg> (const_int 0))
5838 (clobber (<ccr_reg>))]) */
5840 /* Handle various cases of conditional move involving two constants. */
5841 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
5843 HOST_WIDE_INT value1
= INTVAL (src1
);
5844 HOST_WIDE_INT value2
= INTVAL (src2
);
5846 /* Having 0 as one of the constants can be done by loading the other
5847 constant, and optionally moving in gr0. */
5848 if (value1
== 0 || value2
== 0)
5851 /* If the first value is within an addi range and also the difference
5852 between the two fits in an addi's range, load up the difference, then
5853 conditionally move in 0, and then unconditionally add the first
5855 else if (IN_RANGE_P (value1
, -2048, 2047)
5856 && IN_RANGE_P (value2
- value1
, -2048, 2047))
5859 /* If neither condition holds, just force the constant into a
5863 src1
= force_reg (GET_MODE (dest
), src1
);
5864 src2
= force_reg (GET_MODE (dest
), src2
);
5868 /* If one value is a register, insure the other value is either 0 or a
5872 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
5873 src1
= force_reg (GET_MODE (dest
), src1
);
5875 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5876 src2
= force_reg (GET_MODE (dest
), src2
);
5879 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
5880 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
5882 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
5884 cr_reg
= ((TARGET_ALLOC_CC
)
5885 ? gen_reg_rtx (CC_CCRmode
)
5886 : gen_rtx_REG (CC_CCRmode
,
5887 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
5889 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
5890 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
5895 /* Split a conditional move into constituent parts, returning a SEQUENCE
5896 containing all of the insns. */
5899 frv_split_cond_move (rtx operands
[])
5901 rtx dest
= operands
[0];
5902 rtx test
= operands
[1];
5903 rtx cc_reg
= operands
[2];
5904 rtx src1
= operands
[3];
5905 rtx src2
= operands
[4];
5906 rtx cr_reg
= operands
[5];
5908 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5912 /* Set the appropriate CCR bit. */
5913 emit_insn (gen_rtx_SET (VOIDmode
,
5915 gen_rtx_fmt_ee (GET_CODE (test
),
5920 /* Handle various cases of conditional move involving two constants. */
5921 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
5923 HOST_WIDE_INT value1
= INTVAL (src1
);
5924 HOST_WIDE_INT value2
= INTVAL (src2
);
5926 /* Having 0 as one of the constants can be done by loading the other
5927 constant, and optionally moving in gr0. */
5930 emit_move_insn (dest
, src2
);
5931 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5932 gen_rtx_NE (cr_mode
, cr_reg
,
5934 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5937 else if (value2
== 0)
5939 emit_move_insn (dest
, src1
);
5940 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5941 gen_rtx_EQ (cr_mode
, cr_reg
,
5943 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5946 /* If the first value is within an addi range and also the difference
5947 between the two fits in an addi's range, load up the difference, then
5948 conditionally move in 0, and then unconditionally add the first
5950 else if (IN_RANGE_P (value1
, -2048, 2047)
5951 && IN_RANGE_P (value2
- value1
, -2048, 2047))
5953 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
5955 : gen_rtx_SUBREG (SImode
, dest
, 0));
5957 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
5958 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5959 gen_rtx_NE (cr_mode
, cr_reg
,
5961 gen_rtx_SET (VOIDmode
, dest_si
,
5963 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
5971 /* Emit the conditional move for the test being true if needed. */
5972 if (! rtx_equal_p (dest
, src1
))
5973 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5974 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5975 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5977 /* Emit the conditional move for the test being false if needed. */
5978 if (! rtx_equal_p (dest
, src2
))
5979 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5980 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5981 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5984 /* Finish up, return sequence. */
5991 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5992 memory location that is not known to be dword-aligned. */
5994 frv_split_double_load (rtx dest
, rtx source
)
5996 int regno
= REGNO (dest
);
5997 rtx dest1
= gen_highpart (SImode
, dest
);
5998 rtx dest2
= gen_lowpart (SImode
, dest
);
5999 rtx address
= XEXP (source
, 0);
6001 /* If the address is pre-modified, load the lower-numbered register
6002 first, then load the other register using an integer offset from
6003 the modified base register. This order should always be safe,
6004 since the pre-modification cannot affect the same registers as the
6007 The situation for other loads is more complicated. Loading one
6008 of the registers could affect the value of ADDRESS, so we must
6009 be careful which order we do them in. */
6010 if (GET_CODE (address
) == PRE_MODIFY
6011 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
6013 /* It is safe to load the lower-numbered register first. */
6014 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6015 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6019 /* ADDRESS is not pre-modified and the address depends on the
6020 lower-numbered register. Load the higher-numbered register
6022 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6023 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6027 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6028 and SOURCE is either a double register or the constant zero. */
6030 frv_split_double_store (rtx dest
, rtx source
)
6032 rtx dest1
= change_address (dest
, SImode
, NULL
);
6033 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
6034 if (ZERO_P (source
))
6036 emit_move_insn (dest1
, CONST0_RTX (SImode
));
6037 emit_move_insn (dest2
, CONST0_RTX (SImode
));
6041 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
6042 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
6047 /* Split a min/max operation returning a SEQUENCE containing all of the
6051 frv_split_minmax (rtx operands
[])
6053 rtx dest
= operands
[0];
6054 rtx minmax
= operands
[1];
6055 rtx src1
= operands
[2];
6056 rtx src2
= operands
[3];
6057 rtx cc_reg
= operands
[4];
6058 rtx cr_reg
= operands
[5];
6060 enum rtx_code test_code
;
6061 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6065 /* Figure out which test to use. */
6066 switch (GET_CODE (minmax
))
6071 case SMIN
: test_code
= LT
; break;
6072 case SMAX
: test_code
= GT
; break;
6073 case UMIN
: test_code
= LTU
; break;
6074 case UMAX
: test_code
= GTU
; break;
6077 /* Issue the compare instruction. */
6078 emit_insn (gen_rtx_SET (VOIDmode
,
6080 gen_rtx_COMPARE (GET_MODE (cc_reg
),
6083 /* Set the appropriate CCR bit. */
6084 emit_insn (gen_rtx_SET (VOIDmode
,
6086 gen_rtx_fmt_ee (test_code
,
6091 /* If are taking the min/max of a nonzero constant, load that first, and
6092 then do a conditional move of the other value. */
6093 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6095 if (rtx_equal_p (dest
, src1
))
6098 emit_move_insn (dest
, src2
);
6099 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6100 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6101 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6104 /* Otherwise, do each half of the move. */
6107 /* Emit the conditional move for the test being true if needed. */
6108 if (! rtx_equal_p (dest
, src1
))
6109 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6110 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6111 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6113 /* Emit the conditional move for the test being false if needed. */
6114 if (! rtx_equal_p (dest
, src2
))
6115 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6116 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6117 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6120 /* Finish up, return sequence. */
6127 /* Split an integer abs operation returning a SEQUENCE containing all of the
6131 frv_split_abs (rtx operands
[])
6133 rtx dest
= operands
[0];
6134 rtx src
= operands
[1];
6135 rtx cc_reg
= operands
[2];
6136 rtx cr_reg
= operands
[3];
6141 /* Issue the compare < 0 instruction. */
6142 emit_insn (gen_rtx_SET (VOIDmode
,
6144 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
6146 /* Set the appropriate CCR bit. */
6147 emit_insn (gen_rtx_SET (VOIDmode
,
6149 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
6151 /* Emit the conditional negate if the value is negative. */
6152 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6153 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
6154 gen_negsi2 (dest
, src
)));
6156 /* Emit the conditional move for the test being false if needed. */
6157 if (! rtx_equal_p (dest
, src
))
6158 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6159 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
6160 gen_rtx_SET (VOIDmode
, dest
, src
)));
6162 /* Finish up, return sequence. */
6169 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6170 register used in an insn. */
6173 frv_clear_registers_used (rtx
*ptr
, void *data
)
6175 if (GET_CODE (*ptr
) == REG
)
6177 int regno
= REGNO (*ptr
);
6178 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
6180 if (regno
< FIRST_PSEUDO_REGISTER
)
6182 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
6184 while (regno
< reg_max
)
6186 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
6196 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6198 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6199 initialize the static storage. */
6201 frv_ifcvt_init_extra_fields (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6203 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6204 frv_ifcvt
.cur_scratch_regs
= 0;
6205 frv_ifcvt
.num_nested_cond_exec
= 0;
6206 frv_ifcvt
.cr_reg
= NULL_RTX
;
6207 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
6208 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
6209 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
6210 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
6214 /* Internal function to add a potenial insn to the list of insns to be inserted
6215 if the conditional execution conversion is successful. */
6218 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
6220 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
6222 link
->jump
= before_p
; /* Mark to add this before or after insn. */
6223 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
6224 frv_ifcvt
.added_insns_list
);
6226 if (TARGET_DEBUG_COND_EXEC
)
6229 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6230 (before_p
) ? "before" : "after",
6231 (int)INSN_UID (insn
));
6233 debug_rtx (pattern
);
6238 /* A C expression to modify the code described by the conditional if
6239 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6240 FALSE_EXPR for converting if-then and if-then-else code to conditional
6241 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6242 tests cannot be converted. */
6245 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
6247 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
6248 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
6249 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
6250 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
6251 rtx true_expr
= *p_true
;
6255 enum machine_mode mode
= GET_MODE (true_expr
);
6259 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
6261 rtx sub_cond_exec_reg
;
6263 enum rtx_code code_true
;
6264 enum rtx_code code_false
;
6265 enum reg_class cc_class
;
6266 enum reg_class cr_class
;
6270 /* Make sure we are only dealing with hard registers. Also honor the
6271 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6273 if (!reload_completed
|| TARGET_NO_COND_EXEC
6274 || (TARGET_NO_NESTED_CE
&& ce_info
->pass
> 1))
6277 /* Figure out which registers we can allocate for our own purposes. Only
6278 consider registers that are not preserved across function calls and are
6279 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6280 if we did not need to use them in reloading other registers. */
6281 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
6282 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
6283 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
6284 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
6285 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
6287 /* If this is a nested IF, we need to discover whether the CC registers that
6288 are set/used inside of the block are used anywhere else. If not, we can
6289 change them to be the CC register that is paired with the CR register that
6290 controls the outermost IF block. */
6291 if (ce_info
->pass
> 1)
6293 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
6294 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6295 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6297 if (REGNO_REG_SET_P (then_bb
->global_live_at_start
, j
))
6300 if (else_bb
&& REGNO_REG_SET_P (else_bb
->global_live_at_start
, j
))
6303 if (join_bb
&& REGNO_REG_SET_P (join_bb
->global_live_at_start
, j
))
6306 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
6310 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
6311 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
6313 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6314 frv_ifcvt
.cur_scratch_regs
= 0;
6316 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
6317 * sizeof (basic_block
));
6323 /* Remove anything live at the beginning of the join block from being
6324 available for allocation. */
6325 EXECUTE_IF_SET_IN_REG_SET (join_bb
->global_live_at_start
, 0, regno
,
6327 if (regno
< FIRST_PSEUDO_REGISTER
)
6328 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6332 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6334 if (ce_info
->num_multiple_test_blocks
)
6336 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
6338 while (multiple_test_bb
!= test_bb
)
6340 bb
[num_bb
++] = multiple_test_bb
;
6341 multiple_test_bb
= multiple_test_bb
->pred
->src
;
6345 /* Add in the THEN and ELSE blocks to be scanned. */
6346 bb
[num_bb
++] = then_bb
;
6348 bb
[num_bb
++] = else_bb
;
6350 sub_cond_exec_reg
= NULL_RTX
;
6351 frv_ifcvt
.num_nested_cond_exec
= 0;
6353 /* Scan all of the blocks for registers that must not be allocated. */
6354 for (j
= 0; j
< num_bb
; j
++)
6356 rtx last_insn
= BB_END (bb
[j
]);
6357 rtx insn
= BB_HEAD (bb
[j
]);
6361 fprintf (rtl_dump_file
, "Scanning %s block %d, start %d, end %d\n",
6362 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
6364 (int) INSN_UID (BB_HEAD (bb
[j
])),
6365 (int) INSN_UID (BB_END (bb
[j
])));
6367 /* Anything live at the beginning of the block is obviously unavailable
6369 EXECUTE_IF_SET_IN_REG_SET (bb
[j
]->global_live_at_start
, 0, regno
,
6371 if (regno
< FIRST_PSEUDO_REGISTER
)
6372 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6375 /* Loop through the insns in the block. */
6378 /* Mark any new registers that are created as being unavailable for
6379 allocation. Also see if the CC register used in nested IFs can be
6385 int skip_nested_if
= FALSE
;
6387 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6388 (void *)&tmp_reg
->regs
);
6390 pattern
= PATTERN (insn
);
6391 if (GET_CODE (pattern
) == COND_EXEC
)
6393 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
6395 if (reg
!= sub_cond_exec_reg
)
6397 sub_cond_exec_reg
= reg
;
6398 frv_ifcvt
.num_nested_cond_exec
++;
6402 set
= single_set_pattern (pattern
);
6405 rtx dest
= SET_DEST (set
);
6406 rtx src
= SET_SRC (set
);
6408 if (GET_CODE (dest
) == REG
)
6410 int regno
= REGNO (dest
);
6411 enum rtx_code src_code
= GET_CODE (src
);
6413 if (CC_P (regno
) && src_code
== COMPARE
)
6414 skip_nested_if
= TRUE
;
6416 else if (CR_P (regno
)
6417 && (src_code
== IF_THEN_ELSE
6418 || GET_RTX_CLASS (src_code
) == '<'))
6419 skip_nested_if
= TRUE
;
6423 if (! skip_nested_if
)
6424 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6425 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
6428 if (insn
== last_insn
)
6431 insn
= NEXT_INSN (insn
);
6435 /* If this is a nested if, rewrite the CC registers that are available to
6436 include the ones that can be rewritten, to increase the chance of being
6437 able to allocate a paired CC/CR register combination. */
6438 if (ce_info
->pass
> 1)
6440 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6441 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
6442 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
6444 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
6450 fprintf (rtl_dump_file
, "Available GPRs: ");
6452 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
6453 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6455 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6456 if (++num_gprs
> GPR_TEMP_NUM
+2)
6460 fprintf (rtl_dump_file
, "%s\nAvailable CRs: ",
6461 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
6463 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
6464 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6465 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6467 fputs ("\n", rtl_dump_file
);
6469 if (ce_info
->pass
> 1)
6471 fprintf (rtl_dump_file
, "Modifiable CCs: ");
6472 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6473 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6474 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6476 fprintf (rtl_dump_file
, "\n%d nested COND_EXEC statements\n",
6477 frv_ifcvt
.num_nested_cond_exec
);
6481 /* Allocate the appropriate temporary condition code register. Try to
6482 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6483 that conditional cmp's can be done. */
6484 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6486 cr_class
= ICR_REGS
;
6487 cc_class
= ICC_REGS
;
6488 cc_first
= ICC_FIRST
;
6491 else if (mode
== CC_FPmode
)
6493 cr_class
= FCR_REGS
;
6494 cc_class
= FCC_REGS
;
6495 cc_first
= FCC_FIRST
;
6500 cc_first
= cc_last
= 0;
6501 cr_class
= cc_class
= NO_REGS
;
6504 cc
= XEXP (true_expr
, 0);
6505 nested_cc
= cr
= NULL_RTX
;
6506 if (cc_class
!= NO_REGS
)
6508 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6509 so we can execute a csubcc/caddcc/cfcmps instruction. */
6512 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
6514 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
6516 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
6517 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
6519 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
6520 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
6523 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
6524 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
6534 fprintf (rtl_dump_file
, "Could not allocate a CR temporary register\n");
6540 fprintf (rtl_dump_file
,
6541 "Will use %s for conditional execution, %s for nested comparisons\n",
6542 reg_names
[ REGNO (cr
)],
6543 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
6545 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6546 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6547 bit being true. We don't do this for floating point, because of NaNs. */
6548 code
= GET_CODE (true_expr
);
6549 if (GET_MODE (cc
) != CC_FPmode
)
6551 code
= reverse_condition (code
);
6561 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
6562 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
6564 /* Record the check insn to be inserted later. */
6565 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
6567 /* Update the tests. */
6568 frv_ifcvt
.cr_reg
= cr
;
6569 frv_ifcvt
.nested_cc_reg
= nested_cc
;
6570 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
6571 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
6574 /* Fail, don't do this conditional execution. */
6577 *p_false
= NULL_RTX
;
6579 fprintf (rtl_dump_file
, "Disabling this conditional execution.\n");
6585 /* A C expression to modify the code described by the conditional if
6586 information CE_INFO, for the basic block BB, possibly updating the tests in
6587 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6588 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6589 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6591 /* p_true and p_false are given expressions of the form:
6593 (and (eq:CC_CCR (reg:CC_CCR)
6599 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
6604 rtx old_true
= XEXP (*p_true
, 0);
6605 rtx old_false
= XEXP (*p_false
, 0);
6606 rtx true_expr
= XEXP (*p_true
, 1);
6607 rtx false_expr
= XEXP (*p_false
, 1);
6610 rtx cr
= XEXP (old_true
, 0);
6612 rtx new_cr
= NULL_RTX
;
6613 rtx
*p_new_cr
= (rtx
*)0;
6617 enum reg_class cr_class
;
6618 enum machine_mode mode
= GET_MODE (true_expr
);
6619 rtx (*logical_func
)(rtx
, rtx
, rtx
);
6621 if (TARGET_DEBUG_COND_EXEC
)
6624 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6625 ce_info
->and_and_p
? "&&" : "||");
6627 debug_rtx (*p_true
);
6629 fputs ("\nfalse insn:\n", stderr
);
6630 debug_rtx (*p_false
);
6633 if (TARGET_NO_MULTI_CE
)
6636 if (GET_CODE (cr
) != REG
)
6639 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6641 cr_class
= ICR_REGS
;
6642 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
6644 else if (mode
== CC_FPmode
)
6646 cr_class
= FCR_REGS
;
6647 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
6652 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6653 more &&/|| tests. */
6657 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
6658 CC_CCRmode
, TRUE
, TRUE
);
6663 if (ce_info
->and_and_p
)
6665 old_test
= old_false
;
6666 test_expr
= true_expr
;
6667 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
6668 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
6669 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
6673 old_test
= old_false
;
6674 test_expr
= false_expr
;
6675 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
6676 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
6677 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
6680 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6681 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6683 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
6685 /* Now add the conditional check insn. */
6686 cc
= XEXP (test_expr
, 0);
6687 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
6688 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
6690 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
6692 /* Add the new check insn to the list of check insns that need to be
6694 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
6696 if (TARGET_DEBUG_COND_EXEC
)
6698 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6701 debug_rtx (*p_true
);
6703 fputs ("\nfalse insn:\n", stderr
);
6704 debug_rtx (*p_false
);
6710 *p_true
= *p_false
= NULL_RTX
;
6712 /* If we allocated a CR register, release it. */
6715 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
6716 *p_new_cr
= NULL_RTX
;
6719 if (TARGET_DEBUG_COND_EXEC
)
6720 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
6726 /* Return a register which will be loaded with a value if an IF block is
6727 converted to conditional execution. This is used to rewrite instructions
6728 that use constants to ones that just use registers. */
6731 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
6733 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
6737 /* We know gr0 == 0, so replace any errant uses. */
6738 if (value
== const0_rtx
)
6739 return gen_rtx_REG (SImode
, GPR_FIRST
);
6741 /* First search all registers currently loaded to see if we have an
6742 applicable constant. */
6743 if (CONSTANT_P (value
)
6744 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
6746 for (i
= 0; i
< num_alloc
; i
++)
6748 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
6749 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
6753 /* Have we exhausted the number of registers available? */
6754 if (num_alloc
>= GPR_TEMP_NUM
)
6757 fprintf (rtl_dump_file
, "Too many temporary registers allocated\n");
6762 /* Allocate the new register. */
6763 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
6767 fputs ("Could not find a scratch register\n", rtl_dump_file
);
6772 frv_ifcvt
.cur_scratch_regs
++;
6773 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
6777 if (GET_CODE (value
) == CONST_INT
)
6778 fprintf (rtl_dump_file
, "Register %s will hold %ld\n",
6779 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
6781 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
6782 fprintf (rtl_dump_file
, "Register %s will hold LR\n",
6783 reg_names
[ REGNO (reg
)]);
6786 fprintf (rtl_dump_file
, "Register %s will hold a saved value\n",
6787 reg_names
[ REGNO (reg
)]);
6794 /* Update a MEM used in conditional code that might contain an offset to put
6795 the offset into a scratch register, so that the conditional load/store
6796 operations can be used. This function returns the original pointer if the
6797 MEM is valid to use in conditional code, NULL if we can't load up the offset
6798 into a temporary register, or the new MEM if we were successful. */
6801 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
6803 rtx addr
= XEXP (mem
, 0);
6805 if (!frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
))
6807 if (GET_CODE (addr
) == PLUS
)
6809 rtx addr_op0
= XEXP (addr
, 0);
6810 rtx addr_op1
= XEXP (addr
, 1);
6812 if (plus_small_data_p (addr_op0
, addr_op1
))
6813 addr
= frv_ifcvt_load_value (addr
, insn
);
6815 else if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
6817 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
6821 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
6828 else if (CONSTANT_P (addr
))
6829 addr
= frv_ifcvt_load_value (addr
, insn
);
6834 if (addr
== NULL_RTX
)
6837 else if (XEXP (mem
, 0) != addr
)
6838 return change_address (mem
, mode
, addr
);
6845 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
6846 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
6849 single_set_pattern (rtx pattern
)
6854 if (GET_CODE (pattern
) == COND_EXEC
)
6855 pattern
= COND_EXEC_CODE (pattern
);
6857 if (GET_CODE (pattern
) == SET
)
6860 else if (GET_CODE (pattern
) == PARALLEL
)
6862 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
6864 rtx sub
= XVECEXP (pattern
, 0, i
);
6866 switch (GET_CODE (sub
))
6890 /* A C expression to modify the code described by the conditional if
6891 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
6892 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
6893 insn cannot be converted to be executed conditionally. */
6896 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
6900 rtx orig_ce_pattern
= pattern
;
6906 if (GET_CODE (pattern
) != COND_EXEC
)
6909 test
= COND_EXEC_TEST (pattern
);
6910 if (GET_CODE (test
) == AND
)
6912 rtx cr
= frv_ifcvt
.cr_reg
;
6915 op0
= XEXP (test
, 0);
6916 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
6919 op1
= XEXP (test
, 1);
6920 test_reg
= XEXP (op1
, 0);
6921 if (GET_CODE (test_reg
) != REG
)
6924 /* Is this the first nested if block in this sequence? If so, generate
6925 an andcr or andncr. */
6926 if (! frv_ifcvt
.last_nested_if_cr
)
6930 frv_ifcvt
.last_nested_if_cr
= test_reg
;
6931 if (GET_CODE (op0
) == NE
)
6932 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
6934 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
6936 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
6939 /* If this isn't the first statement in the nested if sequence, see if we
6940 are dealing with the same register. */
6941 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
6944 COND_EXEC_TEST (pattern
) = test
= op1
;
6947 /* If this isn't a nested if, reset state variables. */
6950 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
6953 set
= single_set_pattern (pattern
);
6956 rtx dest
= SET_DEST (set
);
6957 rtx src
= SET_SRC (set
);
6958 enum machine_mode mode
= GET_MODE (dest
);
6960 /* Check for normal binary operators. */
6962 && (GET_RTX_CLASS (GET_CODE (src
)) == '2'
6963 || GET_RTX_CLASS (GET_CODE (src
)) == 'c'))
6965 op0
= XEXP (src
, 0);
6966 op1
= XEXP (src
, 1);
6968 /* Special case load of small data address which looks like:
6970 if (GET_CODE (src
) == PLUS
&& plus_small_data_p (op0
, op1
))
6972 src
= frv_ifcvt_load_value (src
, insn
);
6974 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6979 else if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
6981 op1
= frv_ifcvt_load_value (op1
, insn
);
6983 COND_EXEC_CODE (pattern
)
6984 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
6992 /* For multiply by a constant, we need to handle the sign extending
6993 correctly. Add a USE of the value after the multiply to prevent flow
6994 from cratering because only one register out of the two were used. */
6995 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
6997 op0
= XEXP (src
, 0);
6998 op1
= XEXP (src
, 1);
6999 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
7001 op1
= frv_ifcvt_load_value (op1
, insn
);
7004 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
7005 COND_EXEC_CODE (pattern
)
7006 = gen_rtx_SET (VOIDmode
, dest
,
7007 gen_rtx_MULT (DImode
, op0
, op1
));
7013 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode
, dest
), insn
, FALSE
);
7016 /* If we are just loading a constant created for a nested conditional
7017 execution statement, just load the constant without any conditional
7018 execution, since we know that the constant will not interfere with any
7020 else if (frv_ifcvt
.scratch_insns_bitmap
7021 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
7023 /* We must not unconditionally set a reg set used as
7024 scratch in the THEN branch if the same reg is live
7025 in the ELSE branch. */
7026 && REG_P (SET_DEST (set
))
7027 && (! ce_info
->else_bb
7028 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
7029 || ! (REGNO_REG_SET_P
7030 (ce_info
->else_bb
->global_live_at_start
,
7031 REGNO (SET_DEST (set
))))))
7034 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
7037 int changed_p
= FALSE
;
7039 /* Check for just loading up a constant */
7040 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
7042 src
= frv_ifcvt_load_value (src
, insn
);
7049 /* See if we need to fix up stores */
7050 if (GET_CODE (dest
) == MEM
)
7052 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
7057 else if (new_mem
!= dest
)
7064 /* See if we need to fix up loads */
7065 if (GET_CODE (src
) == MEM
)
7067 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
7072 else if (new_mem
!= src
)
7079 /* If either src or destination changed, redo SET. */
7081 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7084 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7085 rewriting the CC register to be the same as the paired CC/CR register
7087 else if (mode
== CC_CCRmode
&& GET_RTX_CLASS (GET_CODE (src
)) == '<')
7089 int regno
= REGNO (XEXP (src
, 0));
7092 if (ce_info
->pass
> 1
7093 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
7094 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
7096 src
= gen_rtx_fmt_ee (GET_CODE (src
),
7098 frv_ifcvt
.nested_cc_reg
,
7102 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
7103 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
7106 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7107 else if (ce_info
->pass
> 1
7108 && GET_CODE (dest
) == REG
7109 && CC_P (REGNO (dest
))
7110 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
7111 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
7113 && GET_CODE (src
) == COMPARE
)
7115 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
7116 COND_EXEC_CODE (pattern
)
7117 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
7121 if (TARGET_DEBUG_COND_EXEC
)
7123 rtx orig_pattern
= PATTERN (insn
);
7125 PATTERN (insn
) = pattern
;
7127 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7131 PATTERN (insn
) = orig_pattern
;
7137 if (TARGET_DEBUG_COND_EXEC
)
7139 rtx orig_pattern
= PATTERN (insn
);
7141 PATTERN (insn
) = orig_ce_pattern
;
7143 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7147 PATTERN (insn
) = orig_pattern
;
7154 /* A C expression to perform any final machine dependent modifications in
7155 converting code to conditional execution in the code described by the
7156 conditional if information CE_INFO. */
7159 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
7163 rtx p
= frv_ifcvt
.added_insns_list
;
7166 /* Loop inserting the check insns. The last check insn is the first test,
7167 and is the appropriate place to insert constants. */
7173 rtx check_and_insert_insns
= XEXP (p
, 0);
7176 check_insn
= XEXP (check_and_insert_insns
, 0);
7177 existing_insn
= XEXP (check_and_insert_insns
, 1);
7180 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7181 the existing insn, otherwise it is to be inserted AFTER. */
7182 if (check_and_insert_insns
->jump
)
7184 emit_insn_before (check_insn
, existing_insn
);
7185 check_and_insert_insns
->jump
= 0;
7188 emit_insn_after (check_insn
, existing_insn
);
7190 free_EXPR_LIST_node (check_and_insert_insns
);
7191 free_EXPR_LIST_node (old_p
);
7193 while (p
!= NULL_RTX
);
7195 /* Load up any constants needed into temp gprs */
7196 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7198 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
7199 if (! frv_ifcvt
.scratch_insns_bitmap
)
7200 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_XMALLOC ();
7201 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
7202 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7205 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7206 frv_ifcvt
.cur_scratch_regs
= 0;
7210 /* A C expression to cancel any machine dependent modifications in converting
7211 code to conditional execution in the code described by the conditional if
7212 information CE_INFO. */
7215 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
7218 rtx p
= frv_ifcvt
.added_insns_list
;
7220 /* Loop freeing up the EXPR_LIST's allocated. */
7221 while (p
!= NULL_RTX
)
7223 rtx check_and_jump
= XEXP (p
, 0);
7227 free_EXPR_LIST_node (check_and_jump
);
7228 free_EXPR_LIST_node (old_p
);
7231 /* Release any temporary gprs allocated. */
7232 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7233 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7235 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7236 frv_ifcvt
.cur_scratch_regs
= 0;
7240 /* A C expression for the size in bytes of the trampoline, as an integer.
7244 setlo #0, <static_chain>
7246 sethi #0, <static_chain>
7247 jmpl @(gr0,<jmp_reg>) */
7250 frv_trampoline_size (void)
7252 return 5 /* instructions */ * 4 /* instruction size */;
7256 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7257 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7258 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7259 should be passed to the function when it is called.
7264 setlo #0, <static_chain>
7266 sethi #0, <static_chain>
7267 jmpl @(gr0,<jmp_reg>) */
7270 frv_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
7272 rtx sc_reg
= force_reg (Pmode
, static_chain
);
7274 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
7277 GEN_INT (frv_trampoline_size ()), SImode
,
7283 /* Many machines have some registers that cannot be copied directly to or from
7284 memory or even from other types of registers. An example is the `MQ'
7285 register, which on most machines, can only be copied to or from general
7286 registers, but not memory. Some machines allow copying all registers to and
7287 from memory, but require a scratch register for stores to some memory
7288 locations (e.g., those with symbolic address on the RT, and those with
7289 certain symbolic address on the SPARC when compiling PIC). In some cases,
7290 both an intermediate and a scratch register are required.
7292 You should define these macros to indicate to the reload phase that it may
7293 need to allocate at least one register for a reload in addition to the
7294 register to contain the data. Specifically, if copying X to a register
7295 CLASS in MODE requires an intermediate register, you should define
7296 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7297 whose registers can be used as intermediate registers or scratch registers.
7299 If copying a register CLASS in MODE to X requires an intermediate or scratch
7300 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7301 largest register class required. If the requirements for input and output
7302 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7303 instead of defining both macros identically.
7305 The values returned by these macros are often `GENERAL_REGS'. Return
7306 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7307 to or from a register of CLASS in MODE without requiring a scratch register.
7308 Do not define this macro if it would always return `NO_REGS'.
7310 If a scratch register is required (either with or without an intermediate
7311 register), you should define patterns for `reload_inM' or `reload_outM', as
7312 required.. These patterns, which will normally be implemented with a
7313 `define_expand', should be similar to the `movM' patterns, except that
7314 operand 2 is the scratch register.
7316 Define constraints for the reload register and scratch register that contain
7317 a single register class. If the original reload register (whose class is
7318 CLASS) can meet the constraint given in the pattern, the value returned by
7319 these macros is used for the class of the scratch register. Otherwise, two
7320 additional reload registers are required. Their classes are obtained from
7321 the constraints in the insn pattern.
7323 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7324 either be in a hard register or in memory. Use `true_regnum' to find out;
7325 it will return -1 if the pseudo is in memory and the hard register number if
7326 it is in a register.
7328 These macros should not be used in the case where a particular class of
7329 registers can only be copied to memory and not to another class of
7330 registers. In that case, secondary reload registers are not needed and
7331 would not be helpful. Instead, a stack location must be used to perform the
7332 copy and the `movM' pattern should use memory as an intermediate storage.
7333 This case often occurs between floating-point and general registers. */
7336 frv_secondary_reload_class (enum reg_class
class,
7337 enum machine_mode mode ATTRIBUTE_UNUSED
,
7339 int in_p ATTRIBUTE_UNUSED
)
7349 /* Accumulators/Accumulator guard registers need to go through floating
7355 if (x
&& GET_CODE (x
) == REG
)
7357 int regno
= REGNO (x
);
7359 if (ACC_P (regno
) || ACCG_P (regno
))
7364 /* Nonzero constants should be loaded into an FPR through a GPR. */
7368 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
7374 /* All of these types need gpr registers. */
7386 /* The accumulators need fpr registers */
7399 /* A C expression whose value is nonzero if pseudos that have been assigned to
7400 registers of class CLASS would likely be spilled because registers of CLASS
7401 are needed for spill registers.
7403 The default value of this macro returns 1 if CLASS has exactly one register
7404 and zero otherwise. On most machines, this default should be used. Only
7405 define this macro to some other expression if pseudo allocated by
7406 `local-alloc.c' end up in memory because their hard registers were needed
7407 for spill registers. If this macro returns nonzero for those classes, those
7408 pseudos will only be allocated by `global.c', which knows how to reallocate
7409 the pseudo to another register. If there would not be another register
7410 available for reallocation, you should not change the definition of this
7411 macro since the only effect of such a definition would be to slow down
7412 register allocation. */
7415 frv_class_likely_spilled_p (enum reg_class
class)
7442 /* An expression for the alignment of a structure field FIELD if the
7443 alignment computed in the usual way is COMPUTED. GCC uses this
7444 value instead of the value in `BIGGEST_ALIGNMENT' or
7445 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7447 /* The definition type of the bit field data is either char, short, long or
7448 long long. The maximum bit size is the number of bits of its own type.
7450 The bit field data is assigned to a storage unit that has an adequate size
7451 for bit field data retention and is located at the smallest address.
7453 Consecutive bit field data are packed at consecutive bits having the same
7454 storage unit, with regard to the type, beginning with the MSB and continuing
7457 If a field to be assigned lies over a bit field type boundary, its
7458 assignment is completed by aligning it with a boundary suitable for the
7461 When a bit field having a bit length of 0 is declared, it is forcibly
7462 assigned to the next storage unit.
7475 &x 00000000 00000000 00000000 00000000
7478 &x+4 00000000 00000000 00000000 00000000
7481 &x+8 00000000 00000000 00000000 00000000
7484 &x+12 00000000 00000000 00000000 00000000
7490 frv_adjust_field_align (tree field
, int computed
)
7492 /* Make sure that the bitfield is not wider than the type. */
7493 if (DECL_BIT_FIELD (field
)
7494 && !DECL_ARTIFICIAL (field
))
7496 tree parent
= DECL_CONTEXT (field
);
7497 tree prev
= NULL_TREE
;
7500 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= TREE_CHAIN (cur
))
7502 if (TREE_CODE (cur
) != FIELD_DECL
)
7511 /* If this isn't a :0 field and if the previous element is a bitfield
7512 also, see if the type is different, if so, we will need to align the
7513 bit-field to the next boundary. */
7515 && ! DECL_PACKED (field
)
7516 && ! integer_zerop (DECL_SIZE (field
))
7517 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
7519 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
7520 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
7521 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
7529 /* A C expression that is nonzero if it is permissible to store a value of mode
7530 MODE in hard register number REGNO (or in several registers starting with
7531 that one). For a machine where all registers are equivalent, a suitable
7534 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7536 It is not necessary for this macro to check for the numbers of fixed
7537 registers, because the allocation mechanism considers them to be always
7540 On some machines, double-precision values must be kept in even/odd register
7541 pairs. The way to implement that is to define this macro to reject odd
7542 register numbers for such modes.
7544 The minimum requirement for a mode to be OK in a register is that the
7545 `movMODE' instruction pattern support moves between the register and any
7546 other hard register for which the mode is OK; and that moving a value into
7547 the register and back out not alter it.
7549 Since the same instruction used to move `SImode' will work for all narrower
7550 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7551 to distinguish between these modes, provided you define patterns `movhi',
7552 etc., to take advantage of this. This is useful because of the interaction
7553 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7554 all integer modes to be tieable.
7556 Many machines have special registers for floating point arithmetic. Often
7557 people assume that floating point machine modes are allowed only in floating
7558 point registers. This is not true. Any registers that can hold integers
7559 can safely *hold* a floating point machine mode, whether or not floating
7560 arithmetic can be done on it in those registers. Integer move instructions
7561 can be used to move the values.
7563 On some machines, though, the converse is true: fixed-point machine modes
7564 may not go in floating registers. This is true if the floating registers
7565 normalize any value stored in them, because storing a non-floating value
7566 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7567 fixed-point machine modes in floating registers. But if the floating
7568 registers do not automatically normalize, if you can store any bit pattern
7569 in one and retrieve it unchanged without a trap, then any machine mode may
7570 go in a floating register, so you can define this macro to say so.
7572 The primary significance of special floating registers is rather that they
7573 are the registers acceptable in floating point arithmetic instructions.
7574 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7575 writing the proper constraints for those instructions.
7577 On some machines, the floating registers are especially slow to access, so
7578 that it is better to store a value in a stack frame than in such a register
7579 if floating point arithmetic is not being done. As long as the floating
7580 registers are not in class `GENERAL_REGS', they will not be used unless some
7581 pattern's constraint asks for one. */
7584 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
7593 return ICC_P (regno
) || GPR_P (regno
);
7596 return CR_P (regno
) || GPR_P (regno
);
7599 return FCC_P (regno
) || GPR_P (regno
);
7605 /* Set BASE to the first register in REGNO's class. Set MASK to the
7606 bits that must be clear in (REGNO - BASE) for the register to be
7608 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
7612 /* ACCGs store one byte. Two-byte quantities must start in
7613 even-numbered registers, four-byte ones in registers whose
7614 numbers are divisible by four, and so on. */
7616 mask
= GET_MODE_SIZE (mode
) - 1;
7620 /* The other registers store one word. */
7621 if (GPR_P (regno
) || regno
== AP_FIRST
)
7624 else if (FPR_P (regno
))
7627 else if (ACC_P (regno
))
7630 else if (SPR_P (regno
))
7631 return mode
== SImode
;
7633 /* Fill in the table. */
7637 /* Anything smaller than an SI is OK in any word-sized register. */
7638 if (GET_MODE_SIZE (mode
) < 4)
7641 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
7643 return (((regno
- base
) & mask
) == 0);
7650 /* A C expression for the number of consecutive hard registers, starting at
7651 register number REGNO, required to hold a value of mode MODE.
7653 On a machine where all registers are exactly one word, a suitable definition
7656 #define HARD_REGNO_NREGS(REGNO, MODE) \
7657 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7658 / UNITS_PER_WORD)) */
7660 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7661 that we can build the appropriate instructions to properly reload the
7662 values. Also, make the byte-sized accumulator guards use one guard
7666 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
7669 return GET_MODE_SIZE (mode
);
7671 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7675 /* A C expression for the maximum number of consecutive registers of
7676 class CLASS needed to hold a value of mode MODE.
7678 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7679 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7680 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7682 This macro helps control the handling of multiple-word values in
7685 This declaration is required. */
7688 frv_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
7690 if (class == ACCG_REGS
)
7691 /* An N-byte value requires N accumulator guards. */
7692 return GET_MODE_SIZE (mode
);
7694 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7698 /* A C expression that is nonzero if X is a legitimate constant for an
7699 immediate operand on the target machine. You can assume that X satisfies
7700 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
7701 definition for this macro on machines where anything `CONSTANT_P' is valid. */
7704 frv_legitimate_constant_p (rtx x
)
7706 enum machine_mode mode
= GET_MODE (x
);
7708 /* All of the integer constants are ok. */
7709 if (GET_CODE (x
) != CONST_DOUBLE
)
7712 /* double integer constants are ok. */
7713 if (mode
== VOIDmode
|| mode
== DImode
)
7716 /* 0 is always ok. */
7717 if (x
== CONST0_RTX (mode
))
7720 /* If floating point is just emulated, allow any constant, since it will be
7721 constructed in the GPRs. */
7722 if (!TARGET_HAS_FPRS
)
7725 if (mode
== DFmode
&& !TARGET_DOUBLE
)
7728 /* Otherwise store the constant away and do a load. */
7732 /* A C expression for the cost of moving data from a register in class FROM to
7733 one in class TO. The classes are expressed using the enumeration values
7734 such as `GENERAL_REGS'. A value of 4 is the default; other values are
7735 interpreted relative to that.
7737 It is not required that the cost always equal 2 when FROM is the same as TO;
7738 on some machines it is expensive to move between registers if they are not
7741 If reload sees an insn consisting of a single `set' between two hard
7742 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
7743 value of 2, reload does not check to ensure that the constraints of the insn
7744 are met. Setting a cost of other than 2 will allow reload to verify that
7745 the constraints are met. You should do this if the `movM' pattern's
7746 constraints do not allow such copying. */
7748 #define HIGH_COST 40
7749 #define MEDIUM_COST 3
7753 frv_register_move_cost (enum reg_class from
, enum reg_class to
)
7837 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7838 use ".picptr" to generate safe relocations for PIC code. We also
7839 need a fixup entry for aligned (non-debugging) code. */
7842 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
7844 if (flag_pic
&& size
== UNITS_PER_WORD
)
7846 if (GET_CODE (value
) == CONST
7847 || GET_CODE (value
) == SYMBOL_REF
7848 || GET_CODE (value
) == LABEL_REF
)
7852 static int label_num
= 0;
7856 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
7857 p
= (* targetm
.strip_name_encoding
) (buf
);
7859 fprintf (asm_out_file
, "%s:\n", p
);
7860 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
7861 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
7862 fprintf (asm_out_file
, "\t.previous\n");
7864 assemble_integer_with_op ("\t.picptr\t", value
);
7869 /* We've set the unaligned SI op to NULL, so we always have to
7870 handle the unaligned case here. */
7871 assemble_integer_with_op ("\t.4byte\t", value
);
7875 return default_assemble_integer (value
, size
, aligned_p
);
7878 /* Function to set up the backend function structure. */
7880 static struct machine_function
*
7881 frv_init_machine_status (void)
7883 return ggc_alloc_cleared (sizeof (struct machine_function
));
7886 /* Implement TARGET_SCHED_ISSUE_RATE. */
7889 frv_issue_rate (void)
7894 switch (frv_cpu_type
)
7898 case FRV_CPU_SIMPLE
:
7904 case FRV_CPU_GENERIC
:
7906 case FRV_CPU_TOMCAT
:
7912 /* Implement TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. */
7915 frv_use_dfa_pipeline_interface (void)
7920 /* Update the register state information, to know about which registers are set
7924 frv_registers_update (rtx x
,
7925 unsigned char reg_state
[],
7937 switch (GET_CODE (x
))
7942 /* Clobber just modifies a register, it doesn't make it live. */
7944 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
7945 flag
| REGSTATE_MODIFIED
);
7948 /* Pre modify updates the first argument, just references the second. */
7951 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
7952 flag
| REGSTATE_MODIFIED
| REGSTATE_LIVE
);
7953 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
, flag
);
7956 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
7957 statement, but just to be sure, make sure it is the type of cond_exec
7961 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7962 && GET_CODE (XEXP (cond
, 0)) == REG
7963 && CR_P (REGNO (XEXP (cond
, 0)))
7964 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
7965 && INTVAL (XEXP (cond
, 1)) == 0
7966 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
7968 frv_registers_update (cond
, reg_state
, modified
, p_num_mod
, flag
);
7969 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7970 | ((GET_CODE (cond
) == NE
)
7972 : REGSTATE_IF_FALSE
));
7974 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
,
7979 fatal_insn ("frv_registers_update", x
);
7981 /* MEM resets the modification bits. */
7983 flag
&= ~REGSTATE_MODIFIED
;
7986 /* See if we need to set the modified flag. */
7988 reg
= SUBREG_REG (x
);
7989 if (GET_CODE (reg
) == REG
)
7991 regno
= subreg_regno (x
);
7992 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
7999 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8003 if (flag
& REGSTATE_MODIFIED
)
8005 flag
&= REGSTATE_MASK
;
8006 while (regno
< reg_max
)
8008 int rs
= reg_state
[regno
];
8012 if ((rs
& REGSTATE_MODIFIED
) == 0)
8014 modified
[ *p_num_mod
] = regno
;
8018 /* If the previous register state had the register as
8019 modified, possibly in some conditional execution context,
8020 and the current insn modifies in some other context, or
8021 outside of conditional execution, just mark the variable
8024 flag
&= ~(REGSTATE_IF_EITHER
| REGSTATE_CC_MASK
);
8026 reg_state
[regno
] = (rs
| flag
);
8035 length
= GET_RTX_LENGTH (GET_CODE (x
));
8036 format
= GET_RTX_FORMAT (GET_CODE (x
));
8038 for (j
= 0; j
< length
; ++j
)
8043 frv_registers_update (XEXP (x
, j
), reg_state
, modified
, p_num_mod
,
8049 if (XVEC (x
, j
) != 0)
8052 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8053 frv_registers_update (XVECEXP (x
, j
, k
), reg_state
, modified
,
8059 /* Nothing to do. */
8068 /* Return if any registers in a hard register set were used an insn. */
8071 frv_registers_used_p (rtx x
, unsigned char reg_state
[], int flag
)
8082 switch (GET_CODE (x
))
8087 /* Skip clobber, that doesn't use the previous value. */
8091 /* For SET, if a conditional jump has occurred in the same insn, only
8092 allow a set of a CR register if that register is not currently live.
8093 This is because on the FR-V, B0/B1 instructions are always last.
8094 Otherwise, don't look at the result, except within a MEM, but do look
8097 dest
= SET_DEST (x
);
8098 if (flag
& REGSTATE_CONDJUMP
8099 && GET_CODE (dest
) == REG
&& CR_P (REGNO (dest
))
8100 && (reg_state
[ REGNO (dest
) ] & REGSTATE_LIVE
) != 0)
8103 if (GET_CODE (dest
) == MEM
)
8105 result
= frv_registers_used_p (XEXP (dest
, 0), reg_state
, flag
);
8110 return frv_registers_used_p (SET_SRC (x
), reg_state
, flag
);
8112 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8113 statement, but just to be sure, make sure it is the type of cond_exec
8117 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8118 && GET_CODE (XEXP (cond
, 0)) == REG
8119 && CR_P (REGNO (XEXP (cond
, 0)))
8120 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8121 && INTVAL (XEXP (cond
, 1)) == 0
8122 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8124 result
= frv_registers_used_p (cond
, reg_state
, flag
);
8128 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8129 | ((GET_CODE (cond
) == NE
)
8131 : REGSTATE_IF_FALSE
));
8133 return frv_registers_used_p (XEXP (x
, 1), reg_state
, flag
);
8136 fatal_insn ("frv_registers_used_p", x
);
8138 /* See if a register or subreg was modified in the same VLIW insn. */
8140 reg
= SUBREG_REG (x
);
8141 if (GET_CODE (reg
) == REG
)
8143 regno
= subreg_regno (x
);
8144 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8151 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8155 while (regno
< reg_max
)
8157 int rs
= reg_state
[regno
];
8159 if (rs
& REGSTATE_MODIFIED
)
8161 int rs_if
= rs
& REGSTATE_IF_EITHER
;
8162 int flag_if
= flag
& REGSTATE_IF_EITHER
;
8164 /* Simple modification, no conditional execution */
8165 if ((rs
& REGSTATE_IF_EITHER
) == 0)
8168 /* See if the variable is only modified in a conditional
8169 execution expression opposite to the conditional execution
8170 expression that governs this expression (ie, true vs. false
8171 for the same CC register). If this isn't two halves of the
8172 same conditional expression, consider the register
8174 if (((rs_if
== REGSTATE_IF_TRUE
&& flag_if
== REGSTATE_IF_FALSE
)
8175 || (rs_if
== REGSTATE_IF_FALSE
&& flag_if
== REGSTATE_IF_TRUE
))
8176 && ((rs
& REGSTATE_CC_MASK
) == (flag
& REGSTATE_CC_MASK
)))
8188 length
= GET_RTX_LENGTH (GET_CODE (x
));
8189 format
= GET_RTX_FORMAT (GET_CODE (x
));
8191 for (j
= 0; j
< length
; ++j
)
8196 result
= frv_registers_used_p (XEXP (x
, j
), reg_state
, flag
);
8203 if (XVEC (x
, j
) != 0)
8206 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8208 result
= frv_registers_used_p (XVECEXP (x
, j
, k
), reg_state
,
8217 /* Nothing to do. */
8225 /* Return if any registers in a hard register set were set in an insn. */
8228 frv_registers_set_p (rtx x
, unsigned char reg_state
[], int modify_p
)
8237 switch (GET_CODE (x
))
8243 return frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
);
8247 return (frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
)
8248 || frv_registers_set_p (XEXP (x
, 1), reg_state
, FALSE
));
8252 /* Just to be sure, make sure it is the type of cond_exec we
8254 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8255 && GET_CODE (XEXP (cond
, 0)) == REG
8256 && CR_P (REGNO (XEXP (cond
, 0)))
8257 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8258 && INTVAL (XEXP (cond
, 1)) == 0
8260 return frv_registers_set_p (XEXP (x
, 1), reg_state
, modify_p
);
8262 fatal_insn ("frv_registers_set_p", x
);
8264 /* MEM resets the modification bits. */
8269 /* See if we need to set the modified modify_p. */
8271 reg
= SUBREG_REG (x
);
8272 if (GET_CODE (reg
) == REG
)
8274 regno
= subreg_regno (x
);
8275 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8282 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8287 while (regno
< reg_max
)
8289 int rs
= reg_state
[regno
];
8291 if (rs
& REGSTATE_MODIFIED
)
8299 length
= GET_RTX_LENGTH (GET_CODE (x
));
8300 format
= GET_RTX_FORMAT (GET_CODE (x
));
8302 for (j
= 0; j
< length
; ++j
)
8307 if (frv_registers_set_p (XEXP (x
, j
), reg_state
, modify_p
))
8313 if (XVEC (x
, j
) != 0)
8316 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8317 if (frv_registers_set_p (XVECEXP (x
, j
, k
), reg_state
,
8324 /* Nothing to do. */
8333 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8334 conditional branches/calls/jumps, etc. with previous insns where it can. It
8335 does not reorder the instructions. We assume the scheduler left the flow
8336 information in a reasonable state. */
8339 frv_pack_insns (void)
8341 state_t frv_state
; /* frv state machine */
8342 int cur_start_vliw_p
; /* current insn starts a VLIW insn */
8343 int next_start_vliw_p
; /* next insn starts a VLIW insn */
8344 int cur_condjump_p
; /* flag if current insn is a cond jump*/
8345 int next_condjump_p
; /* flag if next insn is a cond jump */
8349 int num_mod
= 0; /* # of modified registers */
8350 int modified
[FIRST_PSEUDO_REGISTER
]; /* registers modified in current VLIW */
8351 /* register state information */
8352 unsigned char reg_state
[FIRST_PSEUDO_REGISTER
];
8354 /* If we weren't going to pack the insns, don't bother with this pass. */
8356 || !flag_schedule_insns_after_reload
8357 || TARGET_NO_VLIW_BRANCH
8358 || frv_issue_rate () == 1)
8361 /* Set up the instruction and register states. */
8363 frv_state
= (state_t
) xmalloc (state_size ());
8364 memset (reg_state
, REGSTATE_DEAD
, sizeof (reg_state
));
8366 /* Go through the insns, and repack the insns. */
8367 state_reset (frv_state
);
8368 cur_start_vliw_p
= FALSE
;
8369 next_start_vliw_p
= TRUE
;
8371 next_condjump_p
= 0;
8373 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
8375 enum rtx_code code
= GET_CODE (insn
);
8376 enum rtx_code pattern_code
;
8378 /* For basic block begin notes redo the live information, and skip other
8382 if (NOTE_LINE_NUMBER (insn
) == (int)NOTE_INSN_BASIC_BLOCK
)
8386 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
8387 reg_state
[j
] &= ~ REGSTATE_LIVE
;
8389 live
= NOTE_BASIC_BLOCK (insn
)->global_live_at_start
;
8390 EXECUTE_IF_SET_IN_REG_SET(live
, 0, j
,
8392 reg_state
[j
] |= REGSTATE_LIVE
;
8399 /* Things like labels reset everything. */
8400 if (GET_RTX_CLASS (code
) != 'i')
8402 next_start_vliw_p
= TRUE
;
8406 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8407 set on the USE insn that precedes the return, and potentially on
8408 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8409 holding the case table labels. */
8410 pattern_code
= GET_CODE (PATTERN (insn
));
8411 if (pattern_code
== USE
|| pattern_code
== CLOBBER
8412 || pattern_code
== ADDR_VEC
|| pattern_code
== ADDR_DIFF_VEC
)
8414 CLEAR_VLIW_START (insn
);
8418 cur_start_vliw_p
= next_start_vliw_p
;
8419 next_start_vliw_p
= FALSE
;
8421 cur_condjump_p
|= next_condjump_p
;
8422 next_condjump_p
= 0;
8424 /* Unconditional branches and calls end the current VLIW insn. */
8425 if (code
== CALL_INSN
)
8427 next_start_vliw_p
= TRUE
;
8429 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8430 if (frv_cpu_type
== FRV_CPU_TOMCAT
)
8431 cur_start_vliw_p
= TRUE
;
8433 else if (code
== JUMP_INSN
)
8435 if (any_condjump_p (insn
))
8436 next_condjump_p
= REGSTATE_CONDJUMP
;
8438 next_start_vliw_p
= TRUE
;
8441 /* Only allow setting a CCR register after a conditional branch. */
8442 else if (((cur_condjump_p
& REGSTATE_CONDJUMP
) != 0)
8443 && get_attr_type (insn
) != TYPE_CCR
)
8444 cur_start_vliw_p
= TRUE
;
8446 /* Determine if we need to start a new VLIW instruction. */
8447 if (cur_start_vliw_p
8448 /* Do not check for register conflicts in a setlo instruction
8449 because any output or true dependencies will be with the
8450 partnering sethi instruction, with which it can be packed.
8452 Although output dependencies are rare they are still
8453 possible. So check output dependencies in VLIW insn. */
8454 || (get_attr_type (insn
) != TYPE_SETLO
8455 && (frv_registers_used_p (PATTERN (insn
),
8458 || frv_registers_set_p (PATTERN (insn
), reg_state
, FALSE
)))
8459 || state_transition (frv_state
, insn
) >= 0)
8461 SET_VLIW_START (insn
);
8462 state_reset (frv_state
);
8463 state_transition (frv_state
, insn
);
8466 /* Update the modified registers. */
8467 for (j
= 0; j
< num_mod
; j
++)
8468 reg_state
[ modified
[j
] ] &= ~(REGSTATE_CC_MASK
8469 | REGSTATE_IF_EITHER
8470 | REGSTATE_MODIFIED
);
8475 CLEAR_VLIW_START (insn
);
8477 /* Record which registers are modified. */
8478 frv_registers_update (PATTERN (insn
), reg_state
, modified
, &num_mod
, 0);
8480 /* Process the death notices. */
8481 for (link
= REG_NOTES (insn
);
8483 link
= XEXP (link
, 1))
8485 rtx reg
= XEXP (link
, 0);
8487 if (REG_NOTE_KIND (link
) == REG_DEAD
&& GET_CODE (reg
) == REG
)
8489 int regno
= REGNO (reg
);
8490 int n
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8491 for (; regno
< n
; regno
++)
8492 reg_state
[regno
] &= ~REGSTATE_LIVE
;
8503 #define def_builtin(name, type, code) \
8504 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8506 struct builtin_description
8508 enum insn_code icode
;
8510 enum frv_builtins code
;
8511 enum rtx_code comparison
;
8515 /* Media intrinsics that take a single, constant argument. */
8517 static struct builtin_description bdesc_set
[] =
8519 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, 0, 0 }
8522 /* Media intrinsics that take just one argument. */
8524 static struct builtin_description bdesc_1arg
[] =
8526 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, 0, 0 },
8527 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, 0, 0 },
8528 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, 0, 0 },
8529 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, 0, 0 },
8530 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, 0, 0 }
8533 /* Media intrinsics that take two arguments. */
8535 static struct builtin_description bdesc_2arg
[] =
8537 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, 0, 0 },
8538 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, 0, 0 },
8539 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, 0, 0 },
8540 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, 0, 0 },
8541 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, 0, 0 },
8542 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, 0, 0 },
8543 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, 0, 0 },
8544 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, 0, 0 },
8545 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, 0, 0 },
8546 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, 0, 0 },
8547 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, 0, 0 },
8548 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, 0, 0 },
8549 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, 0, 0 },
8550 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, 0, 0 },
8551 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, 0, 0 },
8552 { CODE_FOR_mdpackh
, "__MDPACKH", FRV_BUILTIN_MDPACKH
, 0, 0 },
8553 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, 0, 0 },
8554 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, 0, 0 },
8555 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, 0, 0 },
8556 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, 0, 0 }
8559 /* Media intrinsics that take two arguments, the first being an ACC number. */
8561 static struct builtin_description bdesc_cut
[] =
8563 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, 0, 0 },
8564 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, 0, 0 },
8565 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, 0, 0 }
8568 /* Two-argument media intrinsics with an immediate second argument. */
8570 static struct builtin_description bdesc_2argimm
[] =
8572 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, 0, 0 },
8573 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, 0, 0 },
8574 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, 0, 0 },
8575 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, 0, 0 },
8576 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, 0, 0 },
8577 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, 0, 0 },
8578 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, 0, 0 },
8579 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, 0, 0 },
8580 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, 0, 0 },
8581 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, 0, 0 },
8582 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, 0, 0 },
8583 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, 0, 0 },
8584 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, 0, 0 },
8585 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, 0, 0 },
8586 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, 0, 0 }
8589 /* Media intrinsics that take two arguments and return void, the first argument
8590 being a pointer to 4 words in memory. */
8592 static struct builtin_description bdesc_void2arg
[] =
8594 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, 0, 0 },
8595 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, 0, 0 },
8598 /* Media intrinsics that take three arguments, the first being a const_int that
8599 denotes an accumulator, and that return void. */
8601 static struct builtin_description bdesc_void3arg
[] =
8603 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, 0, 0 },
8604 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, 0, 0 },
8605 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, 0, 0 },
8606 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, 0, 0 },
8607 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, 0, 0 },
8608 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, 0, 0 },
8609 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, 0, 0 },
8610 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, 0, 0 },
8611 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, 0, 0 },
8612 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, 0, 0 },
8613 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, 0, 0 },
8614 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, 0, 0 },
8615 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, 0, 0 },
8616 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, 0, 0 },
8617 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, 0, 0 },
8618 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, 0, 0 },
8619 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, 0, 0 },
8620 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, 0, 0 },
8621 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, 0, 0 },
8622 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, 0, 0 },
8623 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, 0, 0 },
8624 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, 0, 0 },
8625 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, 0, 0 },
8626 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, 0, 0 },
8627 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, 0, 0 }
8630 /* Media intrinsics that take two accumulator numbers as argument and
8633 static struct builtin_description bdesc_voidacc
[] =
8635 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, 0, 0 },
8636 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, 0, 0 },
8637 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, 0, 0 },
8638 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, 0, 0 },
8639 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, 0, 0 },
8640 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, 0, 0 }
8643 /* Initialize media builtins. */
8646 frv_init_builtins (void)
8648 tree endlink
= void_list_node
;
8649 tree accumulator
= integer_type_node
;
8650 tree integer
= integer_type_node
;
8651 tree voidt
= void_type_node
;
8652 tree uhalf
= short_unsigned_type_node
;
8653 tree sword1
= long_integer_type_node
;
8654 tree uword1
= long_unsigned_type_node
;
8655 tree sword2
= long_long_integer_type_node
;
8656 tree uword2
= long_long_unsigned_type_node
;
8657 tree uword4
= build_pointer_type (uword1
);
8659 #define UNARY(RET, T1) \
8660 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8662 #define BINARY(RET, T1, T2) \
8663 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8664 tree_cons (NULL_TREE, T2, endlink)))
8666 #define TRINARY(RET, T1, T2, T3) \
8667 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8668 tree_cons (NULL_TREE, T2, \
8669 tree_cons (NULL_TREE, T3, endlink))))
8671 tree void_ftype_void
= build_function_type (voidt
, endlink
);
8673 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8674 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8675 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8676 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8677 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8678 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8679 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8680 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8681 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8683 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8684 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8685 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8686 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8687 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8688 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8689 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8690 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8691 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8692 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8693 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8695 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8696 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8697 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8699 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8700 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8701 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8702 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8703 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8705 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8707 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8708 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8709 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8710 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8711 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8712 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8713 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8714 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8715 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8716 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8717 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8718 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8719 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8720 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8721 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8722 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8723 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8724 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8725 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8726 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8727 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8728 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8729 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8730 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8731 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8732 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8733 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8734 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8735 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8736 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8737 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8738 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8739 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8740 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8741 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8742 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8743 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8744 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8745 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8746 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8747 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8748 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8749 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8750 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8751 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8752 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8753 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8754 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8755 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8756 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MDPACKH
);
8757 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8758 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8759 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8760 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8761 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8762 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8763 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8764 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8765 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8766 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8767 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8768 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8769 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8770 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8771 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8772 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8773 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8774 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8775 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8776 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8777 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8778 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8779 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8780 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8781 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8782 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8783 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8784 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8785 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8786 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8787 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8788 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8789 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8790 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8797 /* Set the names for various arithmetic operations according to the
8800 frv_init_libfuncs (void)
8802 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8803 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8805 set_optab_libfunc (add_optab
, DImode
, "__addll");
8806 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8807 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8808 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8809 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8810 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8811 set_optab_libfunc (and_optab
, DImode
, "__andll");
8812 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8813 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8814 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8816 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8817 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8818 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8819 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8821 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8822 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8823 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8824 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8826 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8827 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8829 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8830 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8831 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8832 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8834 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8835 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8836 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8837 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8839 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8840 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8841 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8842 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8845 /* Convert an integer constant to an accumulator register. ICODE is the
8846 code of the target instruction, OPNUM is the number of the
8847 accumulator operand and OPVAL is the constant integer. Try both
8848 ACC and ACCG registers; only report an error if neither fit the
8852 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8856 if (GET_CODE (opval
) != CONST_INT
)
8858 error ("accumulator is not a constant integer");
8861 if (! IN_RANGE_P (INTVAL (opval
), 0, NUM_ACCS
- 1))
8863 error ("accumulator number is out of bounds");
8867 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8868 ACC_FIRST
+ INTVAL (opval
));
8869 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8870 REGNO (reg
) = ACCG_FIRST
+ INTVAL (opval
);
8872 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8874 error ("inappropriate accumulator for `%s'", insn_data
[icode
].name
);
8880 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8883 static enum machine_mode
8884 frv_matching_accg_mode (enum machine_mode mode
)
8902 /* Return the accumulator guard that should be paired with accumulator
8903 register ACC. The mode of the returned register is in the same
8904 class as ACC, but is four times smaller. */
8907 frv_matching_accg_for_acc (rtx acc
)
8909 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8910 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8913 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
8914 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
8918 frv_read_argument (tree
*arglistptr
)
8920 tree next
= TREE_VALUE (*arglistptr
);
8921 *arglistptr
= TREE_CHAIN (*arglistptr
);
8922 return expand_expr (next
, NULL_RTX
, VOIDmode
, 0);
8925 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8926 The instruction should require a constant operand of some sort. The
8927 function prints an error if OPVAL is not valid. */
8930 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8932 if (GET_CODE (opval
) != CONST_INT
)
8934 error ("`%s' expects a constant argument", insn_data
[icode
].name
);
8937 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8939 error ("constant argument out of range for `%s'", insn_data
[icode
].name
);
8945 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8946 if it's not null, has the right mode, and satisfies operand 0's
8950 frv_legitimize_target (enum insn_code icode
, rtx target
)
8952 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8955 || GET_MODE (target
) != mode
8956 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8957 return gen_reg_rtx (mode
);
8962 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8963 check whether ARG satisfies the operand's constraints. If it doesn't,
8964 copy ARG to a temporary register and return that. Otherwise return ARG
8968 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8970 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8972 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8975 return copy_to_mode_reg (mode
, arg
);
8978 /* Expand builtins that take a single, constant argument. At the moment,
8979 only MHDSETS falls into this category. */
8982 frv_expand_set_builtin (enum insn_code icode
, tree arglist
, rtx target
)
8985 rtx op0
= frv_read_argument (&arglist
);
8987 if (! frv_check_constant_argument (icode
, 1, op0
))
8990 target
= frv_legitimize_target (icode
, target
);
8991 pat
= GEN_FCN (icode
) (target
, op0
);
8999 /* Expand builtins that take one operand. */
9002 frv_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9005 rtx op0
= frv_read_argument (&arglist
);
9007 target
= frv_legitimize_target (icode
, target
);
9008 op0
= frv_legitimize_argument (icode
, 1, op0
);
9009 pat
= GEN_FCN (icode
) (target
, op0
);
9017 /* Expand builtins that take two operands. */
9020 frv_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9023 rtx op0
= frv_read_argument (&arglist
);
9024 rtx op1
= frv_read_argument (&arglist
);
9026 target
= frv_legitimize_target (icode
, target
);
9027 op0
= frv_legitimize_argument (icode
, 1, op0
);
9028 op1
= frv_legitimize_argument (icode
, 2, op1
);
9029 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9037 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9041 frv_expand_cut_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9044 rtx op0
= frv_read_argument (&arglist
);
9045 rtx op1
= frv_read_argument (&arglist
);
9048 target
= frv_legitimize_target (icode
, target
);
9049 op0
= frv_int_to_acc (icode
, 1, op0
);
9053 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
9055 if (! frv_check_constant_argument (icode
, 2, op1
))
9059 op1
= frv_legitimize_argument (icode
, 2, op1
);
9061 op2
= frv_matching_accg_for_acc (op0
);
9062 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
9070 /* Expand builtins that take two operands and the second is immediate. */
9073 frv_expand_binopimm_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9076 rtx op0
= frv_read_argument (&arglist
);
9077 rtx op1
= frv_read_argument (&arglist
);
9079 if (! frv_check_constant_argument (icode
, 2, op1
))
9082 target
= frv_legitimize_target (icode
, target
);
9083 op0
= frv_legitimize_argument (icode
, 1, op0
);
9084 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9092 /* Expand builtins that take two operands, the first operand being a pointer to
9093 ints and return void. */
9096 frv_expand_voidbinop_builtin (enum insn_code icode
, tree arglist
)
9099 rtx op0
= frv_read_argument (&arglist
);
9100 rtx op1
= frv_read_argument (&arglist
);
9101 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
9104 if (GET_CODE (op0
) != MEM
)
9108 if (! offsettable_address_p (0, mode0
, op0
))
9110 reg
= gen_reg_rtx (Pmode
);
9111 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
9114 op0
= gen_rtx_MEM (SImode
, reg
);
9117 addr
= XEXP (op0
, 0);
9118 if (! offsettable_address_p (0, mode0
, addr
))
9119 addr
= copy_to_mode_reg (Pmode
, op0
);
9121 op0
= change_address (op0
, V4SImode
, addr
);
9122 op1
= frv_legitimize_argument (icode
, 1, op1
);
9123 pat
= GEN_FCN (icode
) (op0
, op1
);
9131 /* Expand builtins that take three operands and return void. The first
9132 argument must be a constant that describes a pair or quad accumulators. A
9133 fourth argument is created that is the accumulator guard register that
9134 corresponds to the accumulator. */
9137 frv_expand_voidtriop_builtin (enum insn_code icode
, tree arglist
)
9140 rtx op0
= frv_read_argument (&arglist
);
9141 rtx op1
= frv_read_argument (&arglist
);
9142 rtx op2
= frv_read_argument (&arglist
);
9145 op0
= frv_int_to_acc (icode
, 0, op0
);
9149 op1
= frv_legitimize_argument (icode
, 1, op1
);
9150 op2
= frv_legitimize_argument (icode
, 2, op2
);
9151 op3
= frv_matching_accg_for_acc (op0
);
9152 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9160 /* Expand builtins that perform accumulator-to-accumulator operations.
9161 These builtins take two accumulator numbers as argument and return
9165 frv_expand_voidaccop_builtin (enum insn_code icode
, tree arglist
)
9168 rtx op0
= frv_read_argument (&arglist
);
9169 rtx op1
= frv_read_argument (&arglist
);
9173 op0
= frv_int_to_acc (icode
, 0, op0
);
9177 op1
= frv_int_to_acc (icode
, 1, op1
);
9181 op2
= frv_matching_accg_for_acc (op0
);
9182 op3
= frv_matching_accg_for_acc (op1
);
9183 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9191 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9192 number as argument. */
9195 frv_expand_mclracc_builtin (tree arglist
)
9197 enum insn_code icode
= CODE_FOR_mclracc
;
9199 rtx op0
= frv_read_argument (&arglist
);
9201 op0
= frv_int_to_acc (icode
, 0, op0
);
9205 pat
= GEN_FCN (icode
) (op0
);
9212 /* Expand builtins that take no arguments. */
9215 frv_expand_noargs_builtin (enum insn_code icode
)
9217 rtx pat
= GEN_FCN (icode
) (GEN_INT (0));
9224 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9225 number or accumulator guard number as argument and return an SI integer. */
9228 frv_expand_mrdacc_builtin (enum insn_code icode
, tree arglist
)
9231 rtx target
= gen_reg_rtx (SImode
);
9232 rtx op0
= frv_read_argument (&arglist
);
9234 op0
= frv_int_to_acc (icode
, 1, op0
);
9238 pat
= GEN_FCN (icode
) (target
, op0
);
9246 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9247 accumulator guard as their first argument and an SImode value as their
9251 frv_expand_mwtacc_builtin (enum insn_code icode
, tree arglist
)
9254 rtx op0
= frv_read_argument (&arglist
);
9255 rtx op1
= frv_read_argument (&arglist
);
9257 op0
= frv_int_to_acc (icode
, 0, op0
);
9261 op1
= frv_legitimize_argument (icode
, 1, op1
);
9262 pat
= GEN_FCN (icode
) (op0
, op1
);
9269 /* Expand builtins. */
9272 frv_expand_builtin (tree exp
,
9274 rtx subtarget ATTRIBUTE_UNUSED
,
9275 enum machine_mode mode ATTRIBUTE_UNUSED
,
9276 int ignore ATTRIBUTE_UNUSED
)
9278 tree arglist
= TREE_OPERAND (exp
, 1);
9279 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9280 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9282 struct builtin_description
*d
;
9286 error ("media functions are not available unless -mmedia is used");
9292 case FRV_BUILTIN_MCOP1
:
9293 case FRV_BUILTIN_MCOP2
:
9294 case FRV_BUILTIN_MDUNPACKH
:
9295 case FRV_BUILTIN_MBTOHE
:
9296 if (! TARGET_MEDIA_REV1
)
9298 error ("this media function is only available on the fr500");
9303 case FRV_BUILTIN_MQXMACHS
:
9304 case FRV_BUILTIN_MQXMACXHS
:
9305 case FRV_BUILTIN_MQMACXHS
:
9306 case FRV_BUILTIN_MADDACCS
:
9307 case FRV_BUILTIN_MSUBACCS
:
9308 case FRV_BUILTIN_MASACCS
:
9309 case FRV_BUILTIN_MDADDACCS
:
9310 case FRV_BUILTIN_MDSUBACCS
:
9311 case FRV_BUILTIN_MDASACCS
:
9312 case FRV_BUILTIN_MABSHS
:
9313 case FRV_BUILTIN_MDROTLI
:
9314 case FRV_BUILTIN_MCPLHI
:
9315 case FRV_BUILTIN_MCPLI
:
9316 case FRV_BUILTIN_MDCUTSSI
:
9317 case FRV_BUILTIN_MQSATHS
:
9318 case FRV_BUILTIN_MHSETLOS
:
9319 case FRV_BUILTIN_MHSETLOH
:
9320 case FRV_BUILTIN_MHSETHIS
:
9321 case FRV_BUILTIN_MHSETHIH
:
9322 case FRV_BUILTIN_MHDSETS
:
9323 case FRV_BUILTIN_MHDSETH
:
9324 if (! TARGET_MEDIA_REV2
)
9326 error ("this media function is only available on the fr400");
9335 /* Expand unique builtins. */
9339 case FRV_BUILTIN_MTRAP
:
9340 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9342 case FRV_BUILTIN_MCLRACC
:
9343 return frv_expand_mclracc_builtin (arglist
);
9345 case FRV_BUILTIN_MCLRACCA
:
9347 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9349 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9351 case FRV_BUILTIN_MRDACC
:
9352 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, arglist
);
9354 case FRV_BUILTIN_MRDACCG
:
9355 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, arglist
);
9357 case FRV_BUILTIN_MWTACC
:
9358 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, arglist
);
9360 case FRV_BUILTIN_MWTACCG
:
9361 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, arglist
);
9367 /* Expand groups of builtins. */
9369 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9370 if (d
->code
== fcode
)
9371 return frv_expand_set_builtin (d
->icode
, arglist
, target
);
9373 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9374 if (d
->code
== fcode
)
9375 return frv_expand_unop_builtin (d
->icode
, arglist
, target
);
9377 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9378 if (d
->code
== fcode
)
9379 return frv_expand_binop_builtin (d
->icode
, arglist
, target
);
9381 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9382 if (d
->code
== fcode
)
9383 return frv_expand_cut_builtin (d
->icode
, arglist
, target
);
9385 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9386 if (d
->code
== fcode
)
9387 return frv_expand_binopimm_builtin (d
->icode
, arglist
, target
);
9389 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9390 if (d
->code
== fcode
)
9391 return frv_expand_voidbinop_builtin (d
->icode
, arglist
);
9393 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9394 if (d
->code
== fcode
)
9395 return frv_expand_voidtriop_builtin (d
->icode
, arglist
);
9397 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9398 if (d
->code
== fcode
)
9399 return frv_expand_voidaccop_builtin (d
->icode
, arglist
);
9405 frv_in_small_data_p (tree decl
)
9410 /* Don't apply the -G flag to internal compiler structures. We
9411 should leave such structures in the main data section, partly
9412 for efficiency and partly because the size of some of them
9413 (such as C++ typeinfos) is not known until later. */
9414 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9417 /* If we already know which section the decl should be in, see if
9418 it's a small data section. */
9419 section_name
= DECL_SECTION_NAME (decl
);
9422 if (TREE_CODE (section_name
) != STRING_CST
)
9424 if (frv_string_begins_with (section_name
, ".sdata"))
9426 if (frv_string_begins_with (section_name
, ".sbss"))
9431 size
= int_size_in_bytes (TREE_TYPE (decl
));
9432 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
9439 frv_rtx_costs (rtx x
,
9440 int code ATTRIBUTE_UNUSED
,
9441 int outer_code ATTRIBUTE_UNUSED
,
9447 /* Make 12 bit integers really cheap. */
9448 if (IN_RANGE_P (INTVAL (x
), -2048, 2047))
9459 *total
= COSTS_N_INSNS (2);
9473 if (GET_MODE (x
) == SImode
)
9474 *total
= COSTS_N_INSNS (1);
9475 else if (GET_MODE (x
) == DImode
)
9476 *total
= COSTS_N_INSNS (2);
9478 *total
= COSTS_N_INSNS (3);
9482 if (GET_MODE (x
) == SImode
)
9483 *total
= COSTS_N_INSNS (2);
9485 *total
= COSTS_N_INSNS (6); /* guess */
9492 *total
= COSTS_N_INSNS (18);
9501 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9504 assemble_align (POINTER_SIZE
);
9505 assemble_integer_with_op ("\t.picptr\t", symbol
);
9509 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9512 assemble_align (POINTER_SIZE
);
9513 assemble_integer_with_op ("\t.picptr\t", symbol
);
9516 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9519 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9520 int incoming ATTRIBUTE_UNUSED
)
9522 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);