1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
42 /* The flags is set up every time when we calculate pseudo register
43 classes through function ira_set_pseudo_classes. */
44 static bool pseudo_classes_defined_p
= false;
46 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
47 static bool allocno_p
;
49 /* Number of elements in arrays `in_inc_dec' and `costs'. */
50 static int cost_elements_num
;
52 #ifdef FORBIDDEN_INC_DEC_CLASSES
53 /* Indexed by n, is TRUE if allocno or pseudo with number N is used in
54 an auto-inc or auto-dec context. */
55 static bool *in_inc_dec
;
58 /* The `costs' struct records the cost of using hard registers of each
59 class considered for the calculation and of using memory for each
64 /* Costs for register classes start here. We process only some
65 register classes (cover classes on the 1st cost calculation
66 iteration and important classes on the 2nd iteration). */
70 /* Initialized once. It is a maximal possible size of the allocated
72 static int max_struct_costs_size
;
74 /* Allocated and initialized once, and used to initialize cost values
76 static struct costs
*init_cost
;
78 /* Allocated once, and used for temporary purposes. */
79 static struct costs
*temp_costs
;
81 /* Allocated once, and used for the cost calculation. */
82 static struct costs
*op_costs
[MAX_RECOG_OPERANDS
];
83 static struct costs
*this_op_costs
[MAX_RECOG_OPERANDS
];
85 /* Costs of each class for each allocno or pseudo. */
86 static struct costs
*costs
;
88 /* Accumulated costs of each class for each allocno. */
89 static struct costs
*total_allocno_costs
;
91 /* Classes used for cost calculation. They may be different on
92 different iterations of the cost calculations or in different
93 optimization modes. */
94 static enum reg_class
*cost_classes
;
96 /* The size of the previous array. */
97 static int cost_classes_num
;
99 /* Map: cost class -> order number (they start with 0) of the cost
100 class. The order number is negative for non-cost classes. */
101 static int cost_class_nums
[N_REG_CLASSES
];
103 /* It is the current size of struct costs. */
104 static int struct_costs_size
;
106 /* Return pointer to structure containing costs of allocno or pseudo
107 with given NUM in array ARR. */
108 #define COSTS(arr, num) \
109 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
111 /* Return index in COSTS when processing reg with REGNO. */
112 #define COST_INDEX(regno) (allocno_p \
113 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
116 /* Record register class preferences of each allocno or pseudo. Null
117 value means no preferences. It happens on the 1st iteration of the
119 static enum reg_class
*pref
;
121 /* Allocated buffers for pref. */
122 static enum reg_class
*pref_buffer
;
124 /* Record cover register class of each allocno with the same regno. */
125 static enum reg_class
*regno_cover_class
;
127 /* Record cost gains for not allocating a register with an invariant
129 static int *regno_equiv_gains
;
131 /* Execution frequency of the current insn. */
132 static int frequency
;
136 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
137 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
138 be a pseudo register. */
140 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class rclass
, bool to_p
,
141 secondary_reload_info
*prev_sri
)
143 secondary_reload_info sri
;
144 enum reg_class secondary_class
= NO_REGS
;
146 /* If X is a SCRATCH, there is actually nothing to move since we are
147 assuming optimal allocation. */
148 if (GET_CODE (x
) == SCRATCH
)
151 /* Get the class we will actually use for a reload. */
152 rclass
= PREFERRED_RELOAD_CLASS (x
, rclass
);
154 /* If we need a secondary reload for an intermediate, the cost is
155 that to load the input into the intermediate register, then to
157 sri
.prev_sri
= prev_sri
;
159 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
161 if (secondary_class
!= NO_REGS
)
163 if (!move_cost
[mode
])
164 init_move_cost (mode
);
165 return (move_cost
[mode
][secondary_class
][rclass
] + sri
.extra_cost
166 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
169 /* For memory, use the memory move cost, for (hard) registers, use
170 the cost to move between the register classes, and use 2 for
171 everything else (constants). */
172 if (MEM_P (x
) || rclass
== NO_REGS
)
173 return sri
.extra_cost
+ ira_memory_move_cost
[mode
][rclass
][to_p
!= 0];
176 if (!move_cost
[mode
])
177 init_move_cost (mode
);
178 return (sri
.extra_cost
+ move_cost
[mode
][REGNO_REG_CLASS (REGNO (x
))][rclass
]);
181 /* If this is a constant, we may eventually want to call rtx_cost
183 return sri
.extra_cost
+ COSTS_N_INSNS (1);
188 /* Record the cost of using memory or hard registers of various
189 classes for the operands in INSN.
191 N_ALTS is the number of alternatives.
192 N_OPS is the number of operands.
193 OPS is an array of the operands.
194 MODES are the modes of the operands, in case any are VOIDmode.
195 CONSTRAINTS are the constraints to use for the operands. This array
196 is modified by this procedure.
198 This procedure works alternative by alternative. For each
199 alternative we assume that we will be able to allocate all allocnos
200 to their ideal register class and calculate the cost of using that
201 alternative. Then we compute, for each operand that is a
202 pseudo-register, the cost of having the allocno allocated to each
203 register class and using it in that alternative. To this cost is
204 added the cost of the alternative.
206 The cost of each class for this insn is its lowest cost among all
209 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
210 enum machine_mode
*modes
, const char **constraints
,
211 rtx insn
, struct costs
**op_costs
,
212 enum reg_class
*pref
)
217 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
219 for (i
= 0; i
< n_ops
; i
++)
220 insn_allows_mem
[i
] = 0;
222 /* Process each alternative, each time minimizing an operand's cost
223 with the cost for each operand in that alternative. */
224 for (alt
= 0; alt
< n_alts
; alt
++)
226 enum reg_class classes
[MAX_RECOG_OPERANDS
];
227 int allows_mem
[MAX_RECOG_OPERANDS
];
228 enum reg_class rclass
;
230 int alt_cost
= 0, op_cost_add
;
232 if (!recog_data
.alternative_enabled_p
[alt
])
234 for (i
= 0; i
< recog_data
.n_operands
; i
++)
235 constraints
[i
] = skip_alternative (constraints
[i
]);
240 for (i
= 0; i
< n_ops
; i
++)
243 const char *p
= constraints
[i
];
245 enum machine_mode mode
= modes
[i
];
249 /* Initially show we know nothing about the register class. */
250 classes
[i
] = NO_REGS
;
253 /* If this operand has no constraints at all, we can
254 conclude nothing about it since anything is valid. */
257 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
258 memset (this_op_costs
[i
], 0, struct_costs_size
);
262 /* If this alternative is only relevant when this operand
263 matches a previous operand, we do different things
264 depending on whether this operand is a allocno-reg or not.
265 We must process any modifiers for the operand before we
266 can make this test. */
267 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
270 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
272 /* Copy class and whether memory is allowed from the
273 matching alternative. Then perform any needed cost
274 computations and/or adjustments. */
276 classes
[i
] = classes
[j
];
277 allows_mem
[i
] = allows_mem
[j
];
279 insn_allows_mem
[i
] = 1;
281 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
283 /* If this matches the other operand, we have no
284 added cost and we win. */
285 if (rtx_equal_p (ops
[j
], op
))
287 /* If we can put the other operand into a register,
288 add to the cost of this alternative the cost to
289 copy this operand to the register used for the
291 else if (classes
[j
] != NO_REGS
)
293 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
297 else if (! REG_P (ops
[j
])
298 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
300 /* This op is an allocno but the one it matches is
303 /* If we can't put the other operand into a
304 register, this alternative can't be used. */
306 if (classes
[j
] == NO_REGS
)
308 /* Otherwise, add to the cost of this alternative
309 the cost to copy the other operand to the hard
310 register used for this operand. */
312 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
316 /* The costs of this operand are not the same as the
317 other operand since move costs are not symmetric.
318 Moreover, if we cannot tie them, this alternative
319 needs to do a copy, which is one insn. */
320 struct costs
*pp
= this_op_costs
[i
];
322 for (k
= 0; k
< cost_classes_num
; k
++)
324 rclass
= cost_classes
[k
];
326 = (((recog_data
.operand_type
[i
] != OP_OUT
327 ? ira_get_may_move_cost (mode
, rclass
,
328 classes
[i
], true) : 0)
329 + (recog_data
.operand_type
[i
] != OP_IN
330 ? ira_get_may_move_cost (mode
, classes
[i
],
335 /* If the alternative actually allows memory, make
336 things a bit cheaper since we won't need an extra
339 = ((recog_data
.operand_type
[i
] != OP_IN
340 ? ira_memory_move_cost
[mode
][classes
[i
]][0] : 0)
341 + (recog_data
.operand_type
[i
] != OP_OUT
342 ? ira_memory_move_cost
[mode
][classes
[i
]][1] : 0)
343 - allows_mem
[i
]) * frequency
;
345 /* If we have assigned a class to this allocno in our
346 first pass, add a cost to this alternative
347 corresponding to what we would add if this allocno
348 were not in the appropriate class. We could use
349 cover class here but it is less accurate
353 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
355 if (pref_class
== NO_REGS
)
357 += ((recog_data
.operand_type
[i
] != OP_IN
358 ? ira_memory_move_cost
[mode
][classes
[i
]][0]
360 + (recog_data
.operand_type
[i
] != OP_OUT
361 ? ira_memory_move_cost
[mode
][classes
[i
]][1]
363 else if (ira_reg_class_intersect
364 [pref_class
][classes
[i
]] == NO_REGS
)
365 alt_cost
+= ira_get_register_move_cost (mode
,
369 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
370 && ! find_reg_note (insn
, REG_DEAD
, op
))
373 /* This is in place of ordinary cost computation for
374 this operand, so skip to the end of the
375 alternative (should be just one character). */
376 while (*p
&& *p
++ != ',')
384 /* Scan all the constraint letters. See if the operand
385 matches any of the constraints. Collect the valid
386 register classes and see if this operand accepts
395 /* Ignore the next letter for this pass. */
401 case '!': case '#': case '&':
402 case '0': case '1': case '2': case '3': case '4':
403 case '5': case '6': case '7': case '8': case '9':
408 win
= address_operand (op
, GET_MODE (op
));
409 /* We know this operand is an address, so we want it
410 to be allocated to a register that can be the
411 base of an address, i.e. BASE_REG_CLASS. */
413 = ira_reg_class_union
[classes
[i
]]
414 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
417 case 'm': case 'o': case 'V':
418 /* It doesn't seem worth distinguishing between
419 offsettable and non-offsettable addresses
421 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
428 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
429 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
435 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
436 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
442 if (GET_CODE (op
) == CONST_DOUBLE
443 || (GET_CODE (op
) == CONST_VECTOR
444 && (GET_MODE_CLASS (GET_MODE (op
))
445 == MODE_VECTOR_FLOAT
)))
451 if (GET_CODE (op
) == CONST_DOUBLE
452 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
458 || (GET_CODE (op
) == CONST_DOUBLE
459 && GET_MODE (op
) == VOIDmode
))
464 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
470 || (GET_CODE (op
) == CONST_DOUBLE
471 && GET_MODE (op
) == VOIDmode
))
484 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
495 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
497 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
499 classes
[i
] = ira_reg_class_union
[classes
[i
]][GENERAL_REGS
];
503 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
504 classes
[i
] = ira_reg_class_union
[classes
[i
]]
505 [REG_CLASS_FROM_CONSTRAINT (c
, p
)];
506 #ifdef EXTRA_CONSTRAINT_STR
507 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
510 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
512 /* Every MEM can be reloaded to fit. */
513 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
517 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
519 /* Every address can be reloaded to fit. */
521 if (address_operand (op
, GET_MODE (op
)))
523 /* We know this operand is an address, so we
524 want it to be allocated to a hard register
525 that can be the base of an address,
526 i.e. BASE_REG_CLASS. */
528 = ira_reg_class_union
[classes
[i
]]
529 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
534 p
+= CONSTRAINT_LEN (c
, p
);
541 /* How we account for this operand now depends on whether it
542 is a pseudo register or not. If it is, we first check if
543 any register classes are valid. If not, we ignore this
544 alternative, since we want to assume that all allocnos get
545 allocated for register preferencing. If some register
546 class is valid, compute the costs of moving the allocno
548 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
550 if (classes
[i
] == NO_REGS
)
552 /* We must always fail if the operand is a REG, but
553 we did not find a suitable class.
555 Otherwise we may perform an uninitialized read
556 from this_op_costs after the `continue' statement
562 struct costs
*pp
= this_op_costs
[i
];
564 for (k
= 0; k
< cost_classes_num
; k
++)
566 rclass
= cost_classes
[k
];
568 = (((recog_data
.operand_type
[i
] != OP_OUT
569 ? ira_get_may_move_cost (mode
, rclass
,
570 classes
[i
], true) : 0)
571 + (recog_data
.operand_type
[i
] != OP_IN
572 ? ira_get_may_move_cost (mode
, classes
[i
],
577 /* If the alternative actually allows memory, make
578 things a bit cheaper since we won't need an extra
581 = ((recog_data
.operand_type
[i
] != OP_IN
582 ? ira_memory_move_cost
[mode
][classes
[i
]][0] : 0)
583 + (recog_data
.operand_type
[i
] != OP_OUT
584 ? ira_memory_move_cost
[mode
][classes
[i
]][1] : 0)
585 - allows_mem
[i
]) * frequency
;
586 /* If we have assigned a class to this allocno in our
587 first pass, add a cost to this alternative
588 corresponding to what we would add if this allocno
589 were not in the appropriate class. We could use
590 cover class here but it is less accurate
594 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
596 if (pref_class
== NO_REGS
)
598 += ((recog_data
.operand_type
[i
] != OP_IN
599 ? ira_memory_move_cost
[mode
][classes
[i
]][0]
601 + (recog_data
.operand_type
[i
] != OP_OUT
602 ? ira_memory_move_cost
[mode
][classes
[i
]][1]
604 else if (ira_reg_class_intersect
[pref_class
][classes
[i
]]
606 alt_cost
+= ira_get_register_move_cost (mode
,
613 /* Otherwise, if this alternative wins, either because we
614 have already determined that or if we have a hard
615 register of the proper class, there is no cost for this
617 else if (win
|| (REG_P (op
)
618 && reg_fits_class_p (op
, classes
[i
],
622 /* If registers are valid, the cost of this alternative
623 includes copying the object to and/or from a
625 else if (classes
[i
] != NO_REGS
)
627 if (recog_data
.operand_type
[i
] != OP_OUT
)
628 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
630 if (recog_data
.operand_type
[i
] != OP_IN
)
631 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
633 /* The only other way this alternative can be used is if
634 this is a constant that could be placed into memory. */
635 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
636 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
644 op_cost_add
= alt_cost
* frequency
;
645 /* Finally, update the costs with the information we've
646 calculated about this alternative. */
647 for (i
= 0; i
< n_ops
; i
++)
648 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
650 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
651 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
653 pp
->mem_cost
= MIN (pp
->mem_cost
,
654 (qq
->mem_cost
+ op_cost_add
) * scale
);
656 for (k
= 0; k
< cost_classes_num
; k
++)
658 = MIN (pp
->cost
[k
], (qq
->cost
[k
] + op_cost_add
) * scale
);
663 for (i
= 0; i
< n_ops
; i
++)
668 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
670 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
671 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
672 ALLOCNO_BAD_SPILL_P (a
) = true;
675 /* If this insn is a single set copying operand 1 to operand 0 and
676 one operand is an allocno with the other a hard reg or an allocno
677 that prefers a hard register that is in its own register class
678 then we may want to adjust the cost of that register class to -1.
680 Avoid the adjustment if the source does not die to avoid
681 stressing of register allocator by preferrencing two colliding
682 registers into single class.
684 Also avoid the adjustment if a copy between hard registers of the
685 class is expensive (ten times the cost of a default copy is
686 considered arbitrarily expensive). This avoids losing when the
687 preferred class is very expensive as the source of a copy
689 if ((set
= single_set (insn
)) != 0
690 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
691 && REG_P (ops
[0]) && REG_P (ops
[1])
692 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
693 for (i
= 0; i
<= 1; i
++)
694 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
696 unsigned int regno
= REGNO (ops
[!i
]);
697 enum machine_mode mode
= GET_MODE (ops
[!i
]);
698 enum reg_class rclass
;
701 if (regno
< FIRST_PSEUDO_REGISTER
)
702 for (k
= 0; k
< cost_classes_num
; k
++)
704 rclass
= cost_classes
[k
];
705 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
706 && (reg_class_size
[rclass
]
707 == (unsigned) CLASS_MAX_NREGS (rclass
, mode
)))
709 if (reg_class_size
[rclass
] == 1)
710 op_costs
[i
]->cost
[k
] = -frequency
;
714 nr
< (unsigned) hard_regno_nregs
[regno
][mode
];
716 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
720 if (nr
== (unsigned) hard_regno_nregs
[regno
][mode
])
721 op_costs
[i
]->cost
[k
] = -frequency
;
730 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
732 ok_for_index_p_nonstrict (rtx reg
)
734 unsigned regno
= REGNO (reg
);
736 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
739 /* A version of regno_ok_for_base_p for use here, when all
740 pseudo-registers should count as OK. Arguments as for
741 regno_ok_for_base_p. */
743 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
744 enum rtx_code outer_code
, enum rtx_code index_code
)
746 unsigned regno
= REGNO (reg
);
748 if (regno
>= FIRST_PSEUDO_REGISTER
)
750 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
753 /* Record the pseudo registers we must reload into hard registers in a
754 subexpression of a memory address, X.
756 If CONTEXT is 0, we are looking at the base part of an address,
757 otherwise we are looking at the index part.
759 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
760 give the context that the rtx appears in. These three arguments
761 are passed down to base_reg_class.
763 SCALE is twice the amount to multiply the cost by (it is twice so
764 we can represent half-cost adjustments). */
766 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
767 enum rtx_code outer_code
, enum rtx_code index_code
,
770 enum rtx_code code
= GET_CODE (x
);
771 enum reg_class rclass
;
774 rclass
= INDEX_REG_CLASS
;
776 rclass
= base_reg_class (mode
, outer_code
, index_code
);
789 /* When we have an address that is a sum, we must determine
790 whether registers are "base" or "index" regs. If there is a
791 sum of two registers, we must choose one to be the "base".
792 Luckily, we can use the REG_POINTER to make a good choice
793 most of the time. We only need to do this on machines that
794 can have two registers in an address and where the base and
795 index register classes are different.
797 ??? This code used to set REGNO_POINTER_FLAG in some cases,
798 but that seems bogus since it should only be set when we are
799 sure the register is being used as a pointer. */
801 rtx arg0
= XEXP (x
, 0);
802 rtx arg1
= XEXP (x
, 1);
803 enum rtx_code code0
= GET_CODE (arg0
);
804 enum rtx_code code1
= GET_CODE (arg1
);
806 /* Look inside subregs. */
808 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
810 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
812 /* If this machine only allows one register per address, it
813 must be in the first operand. */
814 if (MAX_REGS_PER_ADDRESS
== 1)
815 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
817 /* If index and base registers are the same on this machine,
818 just record registers in any non-constant operands. We
819 assume here, as well as in the tests below, that all
820 addresses are in canonical form. */
821 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
823 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
824 if (! CONSTANT_P (arg1
))
825 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
828 /* If the second operand is a constant integer, it doesn't
829 change what class the first operand must be. */
830 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
831 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
832 /* If the second operand is a symbolic constant, the first
833 operand must be an index register. */
834 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
835 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
836 /* If both operands are registers but one is already a hard
837 register of index or reg-base class, give the other the
838 class that the hard register is not. */
839 else if (code0
== REG
&& code1
== REG
840 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
841 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
842 || ok_for_index_p_nonstrict (arg0
)))
843 record_address_regs (mode
, arg1
,
844 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
847 else if (code0
== REG
&& code1
== REG
848 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
849 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
850 || ok_for_index_p_nonstrict (arg1
)))
851 record_address_regs (mode
, arg0
,
852 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
855 /* If one operand is known to be a pointer, it must be the
856 base with the other operand the index. Likewise if the
857 other operand is a MULT. */
858 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
860 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
861 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
863 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
865 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
866 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
868 /* Otherwise, count equal chances that each might be a base or
869 index register. This case should be rare. */
872 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
873 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
874 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
875 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
880 /* Double the importance of an allocno that is incremented or
881 decremented, since it would take two extra insns if it ends
882 up in the wrong place. */
885 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
886 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
887 if (REG_P (XEXP (XEXP (x
, 1), 1)))
888 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
896 /* Double the importance of an allocno that is incremented or
897 decremented, since it would take two extra insns if it ends
898 up in the wrong place. If the operand is a pseudo-register,
899 show it is being used in an INC_DEC context. */
900 #ifdef FORBIDDEN_INC_DEC_CLASSES
901 if (REG_P (XEXP (x
, 0))
902 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
903 in_inc_dec
[COST_INDEX (REGNO (XEXP (x
, 0)))] = true;
905 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
914 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
918 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[REGNO (x
)]) = true;
919 pp
= COSTS (costs
, COST_INDEX (REGNO (x
)));
920 pp
->mem_cost
+= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
921 for (k
= 0; k
< cost_classes_num
; k
++)
925 += (ira_get_may_move_cost (Pmode
, i
, rclass
, true) * scale
) / 2;
932 const char *fmt
= GET_RTX_FORMAT (code
);
934 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
936 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
944 /* Calculate the costs of insn operands. */
946 record_operand_costs (rtx insn
, struct costs
**op_costs
, enum reg_class
*pref
)
948 const char *constraints
[MAX_RECOG_OPERANDS
];
949 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
952 for (i
= 0; i
< recog_data
.n_operands
; i
++)
954 constraints
[i
] = recog_data
.constraints
[i
];
955 modes
[i
] = recog_data
.operand_mode
[i
];
958 /* If we get here, we are set up to record the costs of all the
959 operands for this insn. Start by initializing the costs. Then
960 handle any address registers. Finally record the desired classes
961 for any allocnos, doing it twice if some pair of operands are
963 for (i
= 0; i
< recog_data
.n_operands
; i
++)
965 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
967 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
968 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
970 if (MEM_P (recog_data
.operand
[i
]))
971 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
972 XEXP (recog_data
.operand
[i
], 0),
973 0, MEM
, SCRATCH
, frequency
* 2);
974 else if (constraints
[i
][0] == 'p'
975 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0],
977 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
978 SCRATCH
, frequency
* 2);
981 /* Check for commutative in a separate loop so everything will have
982 been initialized. We must do this even if one operand is a
983 constant--see addsi3 in m68k.md. */
984 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
985 if (constraints
[i
][0] == '%')
987 const char *xconstraints
[MAX_RECOG_OPERANDS
];
990 /* Handle commutative operands by swapping the constraints.
991 We assume the modes are the same. */
992 for (j
= 0; j
< recog_data
.n_operands
; j
++)
993 xconstraints
[j
] = constraints
[j
];
995 xconstraints
[i
] = constraints
[i
+1];
996 xconstraints
[i
+1] = constraints
[i
];
997 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
998 recog_data
.operand
, modes
,
999 xconstraints
, insn
, op_costs
, pref
);
1001 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1002 recog_data
.operand
, modes
,
1003 constraints
, insn
, op_costs
, pref
);
1008 /* Process one insn INSN. Scan it and record each time it would save
1009 code to put a certain allocnos in a certain class. Return the last
1010 insn processed, so that the scan can be continued from there. */
1012 scan_one_insn (rtx insn
)
1014 enum rtx_code pat_code
;
1018 if (!NONDEBUG_INSN_P (insn
))
1021 pat_code
= GET_CODE (PATTERN (insn
));
1022 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
1023 || pat_code
== ADDR_VEC
|| pat_code
== ADDR_DIFF_VEC
)
1026 set
= single_set (insn
);
1027 extract_insn (insn
);
1029 /* If this insn loads a parameter from its stack slot, then it
1030 represents a savings, rather than a cost, if the parameter is
1031 stored in memory. Record this fact. */
1032 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1033 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1034 && MEM_P (XEXP (note
, 0)))
1036 enum reg_class cl
= GENERAL_REGS
;
1037 rtx reg
= SET_DEST (set
);
1038 int num
= COST_INDEX (REGNO (reg
));
1042 COSTS (costs
, num
)->mem_cost
1043 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1044 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
1045 0, MEM
, SCRATCH
, frequency
* 2);
1048 record_operand_costs (insn
, op_costs
, pref
);
1050 /* Now add the cost for each operand to the total costs for its
1052 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1053 if (REG_P (recog_data
.operand
[i
])
1054 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1056 int regno
= REGNO (recog_data
.operand
[i
]);
1057 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1058 struct costs
*q
= op_costs
[i
];
1060 p
->mem_cost
+= q
->mem_cost
;
1061 for (k
= 0; k
< cost_classes_num
; k
++)
1062 p
->cost
[k
] += q
->cost
[k
];
1070 /* Print allocnos costs to file F. */
1072 print_allocno_costs (FILE *f
)
1076 ira_allocno_iterator ai
;
1078 ira_assert (allocno_p
);
1080 FOR_EACH_ALLOCNO (a
, ai
)
1084 int regno
= ALLOCNO_REGNO (a
);
1086 i
= ALLOCNO_NUM (a
);
1087 fprintf (f
, " a%d(r%d,", i
, regno
);
1088 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1089 fprintf (f
, "b%d", bb
->index
);
1091 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1092 fprintf (f
, ") costs:");
1093 for (k
= 0; k
< cost_classes_num
; k
++)
1095 rclass
= cost_classes
[k
];
1096 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1097 #ifdef FORBIDDEN_INC_DEC_CLASSES
1098 && (! in_inc_dec
[i
] || ! forbidden_inc_dec_class
[rclass
])
1100 #ifdef CANNOT_CHANGE_MODE_CLASS
1101 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
,
1102 PSEUDO_REGNO_MODE (regno
))
1106 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1107 COSTS (costs
, i
)->cost
[k
]);
1108 if (flag_ira_region
== IRA_REGION_ALL
1109 || flag_ira_region
== IRA_REGION_MIXED
)
1110 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1113 fprintf (f
, " MEM:%i\n", COSTS (costs
, i
)->mem_cost
);
1117 /* Print pseudo costs to file F. */
1119 print_pseudo_costs (FILE *f
)
1124 ira_assert (! allocno_p
);
1126 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1128 if (regno_reg_rtx
[regno
] == NULL_RTX
)
1130 fprintf (f
, " r%d costs:", regno
);
1131 for (k
= 0; k
< cost_classes_num
; k
++)
1133 rclass
= cost_classes
[k
];
1134 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1135 #ifdef FORBIDDEN_INC_DEC_CLASSES
1136 && (! in_inc_dec
[regno
] || ! forbidden_inc_dec_class
[rclass
])
1138 #ifdef CANNOT_CHANGE_MODE_CLASS
1139 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
,
1140 PSEUDO_REGNO_MODE (regno
))
1143 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1144 COSTS (costs
, regno
)->cost
[k
]);
1146 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1150 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1153 process_bb_for_costs (basic_block bb
)
1157 frequency
= REG_FREQ_FROM_BB (bb
);
1160 FOR_BB_INSNS (bb
, insn
)
1161 insn
= scan_one_insn (insn
);
1164 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1167 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1171 bb
= loop_tree_node
->bb
;
1173 process_bb_for_costs (bb
);
1176 /* Find costs of register classes and memory for allocnos or pseudos
1177 and their best costs. Set up preferred, alternative and cover
1178 classes for pseudos. */
1180 find_costs_and_classes (FILE *dump_file
)
1187 #ifdef FORBIDDEN_INC_DEC_CLASSES
1188 in_inc_dec
= ira_allocate (sizeof (bool) * cost_elements_num
);
1189 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1192 if (!resize_reg_info () && allocno_p
&& pseudo_classes_defined_p
)
1195 ira_allocno_iterator ai
;
1198 FOR_EACH_ALLOCNO (a
, ai
)
1199 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1200 if (flag_expensive_optimizations
)
1204 /* Clear the flag for the next compiled function. */
1205 pseudo_classes_defined_p
= false;
1206 /* Normally we scan the insns once and determine the best class to
1207 use for each allocno. However, if -fexpensive-optimizations are
1208 on, we do so twice, the second time using the tentative best
1209 classes to guide the selection. */
1210 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1212 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1214 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1215 /* We could use only cover classes. Unfortunately it does not
1216 work well for some targets where some subclass of cover class
1217 is costly and wrong cover class is chosen. */
1218 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1219 cost_class_nums
[i
] = -1;
1220 for (cost_classes_num
= 0;
1221 cost_classes_num
< ira_important_classes_num
;
1224 cost_classes
[cost_classes_num
]
1225 = ira_important_classes
[cost_classes_num
];
1226 cost_class_nums
[cost_classes
[cost_classes_num
]]
1230 = sizeof (struct costs
) + sizeof (int) * (cost_classes_num
- 1);
1231 /* Zero out our accumulation of the cost of each class for each
1233 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1234 #ifdef FORBIDDEN_INC_DEC_CLASSES
1235 memset (in_inc_dec
, 0, cost_elements_num
* sizeof (bool));
1240 /* Scan the instructions and record each time it would save code
1241 to put a certain allocno in a certain class. */
1242 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1243 process_bb_node_for_costs
, NULL
);
1245 memcpy (total_allocno_costs
, costs
,
1246 max_struct_costs_size
* ira_allocnos_num
);
1253 process_bb_for_costs (bb
);
1259 /* Now for each allocno look at how desirable each class is and
1260 find which class is preferred. */
1261 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1263 ira_allocno_t a
, parent_a
;
1264 int rclass
, a_num
, parent_a_num
;
1265 ira_loop_tree_node_t parent
;
1266 int best_cost
, allocno_cost
;
1267 enum reg_class best
, alt_class
;
1268 #ifdef FORBIDDEN_INC_DEC_CLASSES
1269 int inc_dec_p
= false;
1271 int equiv_savings
= regno_equiv_gains
[i
];
1275 if (regno_reg_rtx
[i
] == NULL_RTX
)
1277 #ifdef FORBIDDEN_INC_DEC_CLASSES
1278 inc_dec_p
= in_inc_dec
[i
];
1280 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1284 if (ira_regno_allocno_map
[i
] == NULL
)
1286 memset (temp_costs
, 0, struct_costs_size
);
1287 /* Find cost of all allocnos with the same regno. */
1288 for (a
= ira_regno_allocno_map
[i
];
1290 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1292 a_num
= ALLOCNO_NUM (a
);
1293 if ((flag_ira_region
== IRA_REGION_ALL
1294 || flag_ira_region
== IRA_REGION_MIXED
)
1295 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1296 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1297 /* There are no caps yet. */
1298 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1299 (a
)->border_allocnos
,
1302 /* Propagate costs to upper levels in the region
1304 parent_a_num
= ALLOCNO_NUM (parent_a
);
1305 for (k
= 0; k
< cost_classes_num
; k
++)
1306 COSTS (total_allocno_costs
, parent_a_num
)->cost
[k
]
1307 += COSTS (total_allocno_costs
, a_num
)->cost
[k
];
1308 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1309 += COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1311 for (k
= 0; k
< cost_classes_num
; k
++)
1312 temp_costs
->cost
[k
] += COSTS (costs
, a_num
)->cost
[k
];
1313 temp_costs
->mem_cost
+= COSTS (costs
, a_num
)->mem_cost
;
1314 #ifdef FORBIDDEN_INC_DEC_CLASSES
1315 if (in_inc_dec
[a_num
])
1320 if (equiv_savings
< 0)
1321 temp_costs
->mem_cost
= -equiv_savings
;
1322 else if (equiv_savings
> 0)
1324 temp_costs
->mem_cost
= 0;
1325 for (k
= 0; k
< cost_classes_num
; k
++)
1326 temp_costs
->cost
[k
] += equiv_savings
;
1329 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1331 alt_class
= NO_REGS
;
1332 /* Find best common class for all allocnos with the same
1334 for (k
= 0; k
< cost_classes_num
; k
++)
1336 rclass
= cost_classes
[k
];
1337 /* Ignore classes that are too small for this operand or
1338 invalid for an operand that was auto-incremented. */
1339 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1340 #ifdef FORBIDDEN_INC_DEC_CLASSES
1341 || (inc_dec_p
&& forbidden_inc_dec_class
[rclass
])
1343 #ifdef CANNOT_CHANGE_MODE_CLASS
1344 || invalid_mode_change_p (i
, (enum reg_class
) rclass
,
1345 PSEUDO_REGNO_MODE (i
))
1349 if (temp_costs
->cost
[k
] < best_cost
)
1351 best_cost
= temp_costs
->cost
[k
];
1352 best
= (enum reg_class
) rclass
;
1354 else if (temp_costs
->cost
[k
] == best_cost
)
1355 best
= ira_reg_class_union
[best
][rclass
];
1356 if (pass
== flag_expensive_optimizations
1357 && temp_costs
->cost
[k
] < temp_costs
->mem_cost
1358 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1359 > reg_class_size
[alt_class
]))
1360 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1362 alt_class
= ira_class_translate
[alt_class
];
1363 if (best_cost
> temp_costs
->mem_cost
)
1364 regno_cover_class
[i
] = NO_REGS
;
1365 else if (flag_ira_algorithm
== IRA_ALGORITHM_PRIORITY
)
1366 /* Make the common class the biggest class of best and
1368 regno_cover_class
[i
] = alt_class
== NO_REGS
? best
: alt_class
;
1370 /* Make the common class a cover class. Remember all
1371 allocnos with the same regno should have the same cover
1373 regno_cover_class
[i
] = ira_class_translate
[best
];
1374 if (pass
== flag_expensive_optimizations
)
1376 if (best_cost
> temp_costs
->mem_cost
)
1377 best
= alt_class
= NO_REGS
;
1378 else if (best
== alt_class
)
1379 alt_class
= NO_REGS
;
1380 setup_reg_classes (i
, best
, alt_class
, regno_cover_class
[i
]);
1381 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1382 && dump_file
!= NULL
)
1384 " r%d: preferred %s, alternative %s, cover %s\n",
1385 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1386 reg_class_names
[regno_cover_class
[i
]]);
1390 pref
[i
] = best_cost
> temp_costs
->mem_cost
? NO_REGS
: best
;
1393 for (a
= ira_regno_allocno_map
[i
];
1395 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1397 a_num
= ALLOCNO_NUM (a
);
1398 if (regno_cover_class
[i
] == NO_REGS
)
1402 /* Finding best class which is subset of the common
1404 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1405 allocno_cost
= best_cost
;
1407 for (k
= 0; k
< cost_classes_num
; k
++)
1409 rclass
= cost_classes
[k
];
1410 if (! ira_class_subset_p
[rclass
][regno_cover_class
[i
]])
1412 /* Ignore classes that are too small for this
1413 operand or invalid for an operand that was
1414 auto-incremented. */
1415 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1416 #ifdef FORBIDDEN_INC_DEC_CLASSES
1417 || (inc_dec_p
&& forbidden_inc_dec_class
[rclass
])
1419 #ifdef CANNOT_CHANGE_MODE_CLASS
1420 || invalid_mode_change_p (i
, (enum reg_class
) rclass
,
1421 PSEUDO_REGNO_MODE (i
))
1425 else if (COSTS (total_allocno_costs
, a_num
)->cost
[k
]
1429 = COSTS (total_allocno_costs
, a_num
)->cost
[k
];
1430 allocno_cost
= COSTS (costs
, a_num
)->cost
[k
];
1431 best
= (enum reg_class
) rclass
;
1433 else if (COSTS (total_allocno_costs
, a_num
)->cost
[k
]
1436 best
= ira_reg_class_union
[best
][rclass
];
1438 = MAX (allocno_cost
, COSTS (costs
, a_num
)->cost
[k
]);
1441 ALLOCNO_COVER_CLASS_COST (a
) = allocno_cost
;
1443 ira_assert (flag_ira_algorithm
== IRA_ALGORITHM_PRIORITY
1444 || ira_class_translate
[best
] == regno_cover_class
[i
]);
1445 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1446 && (pass
== 0 || pref
[a_num
] != best
))
1448 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1449 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1450 fprintf (dump_file
, "b%d", bb
->index
);
1452 fprintf (dump_file
, "l%d",
1453 ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1454 fprintf (dump_file
, ") best %s, cover %s\n",
1455 reg_class_names
[best
],
1456 reg_class_names
[regno_cover_class
[i
]]);
1462 if (internal_flag_ira_verbose
> 4 && dump_file
)
1465 print_allocno_costs (dump_file
);
1467 print_pseudo_costs (dump_file
);
1468 fprintf (dump_file
,"\n");
1471 #ifdef FORBIDDEN_INC_DEC_CLASSES
1472 ira_free (in_inc_dec
);
1478 /* Process moves involving hard regs to modify allocno hard register
1479 costs. We can do this only after determining allocno cover class.
1480 If a hard register forms a register class, than moves with the hard
1481 register are already taken into account in class costs for the
1484 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1486 int i
, freq
, cost
, src_regno
, dst_regno
, hard_regno
;
1489 enum reg_class rclass
, hard_reg_class
;
1490 enum machine_mode mode
;
1492 rtx insn
, set
, src
, dst
;
1494 bb
= loop_tree_node
->bb
;
1497 freq
= REG_FREQ_FROM_BB (bb
);
1500 FOR_BB_INSNS (bb
, insn
)
1502 if (!NONDEBUG_INSN_P (insn
))
1504 set
= single_set (insn
);
1505 if (set
== NULL_RTX
)
1507 dst
= SET_DEST (set
);
1508 src
= SET_SRC (set
);
1509 if (! REG_P (dst
) || ! REG_P (src
))
1511 dst_regno
= REGNO (dst
);
1512 src_regno
= REGNO (src
);
1513 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1514 && src_regno
< FIRST_PSEUDO_REGISTER
)
1516 hard_regno
= src_regno
;
1518 a
= ira_curr_regno_allocno_map
[dst_regno
];
1520 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1521 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1523 hard_regno
= dst_regno
;
1525 a
= ira_curr_regno_allocno_map
[src_regno
];
1529 rclass
= ALLOCNO_COVER_CLASS (a
);
1530 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
1532 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
1535 mode
= ALLOCNO_MODE (a
);
1536 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
1538 = (to_p
? ira_get_register_move_cost (mode
, hard_reg_class
, rclass
)
1539 : ira_get_register_move_cost (mode
, rclass
, hard_reg_class
)) * freq
;
1540 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
1541 ALLOCNO_COVER_CLASS_COST (a
));
1542 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1544 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1545 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1546 ALLOCNO_COVER_CLASS_COST (a
) = MIN (ALLOCNO_COVER_CLASS_COST (a
),
1547 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1551 /* After we find hard register and memory costs for allocnos, define
1552 its cover class and modify hard register cost because insns moving
1553 allocno to/from hard registers. */
1555 setup_allocno_cover_class_and_costs (void)
1557 int i
, j
, n
, regno
, num
;
1559 enum reg_class cover_class
, rclass
;
1561 ira_allocno_iterator ai
;
1563 ira_assert (allocno_p
);
1564 FOR_EACH_ALLOCNO (a
, ai
)
1566 i
= ALLOCNO_NUM (a
);
1567 cover_class
= regno_cover_class
[ALLOCNO_REGNO (a
)];
1568 ira_assert (pref
[i
] == NO_REGS
|| cover_class
!= NO_REGS
);
1569 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
1570 ira_set_allocno_cover_class (a
, cover_class
);
1571 if (cover_class
== NO_REGS
)
1573 ALLOCNO_AVAILABLE_REGS_NUM (a
) = ira_available_class_regs
[cover_class
];
1574 if (optimize
&& ALLOCNO_COVER_CLASS (a
) != pref
[i
])
1576 n
= ira_class_hard_regs_num
[cover_class
];
1577 ALLOCNO_HARD_REG_COSTS (a
)
1578 = reg_costs
= ira_allocate_cost_vector (cover_class
);
1579 for (j
= n
- 1; j
>= 0; j
--)
1581 regno
= ira_class_hard_regs
[cover_class
][j
];
1582 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], regno
))
1583 reg_costs
[j
] = ALLOCNO_COVER_CLASS_COST (a
);
1586 rclass
= REGNO_REG_CLASS (regno
);
1587 num
= cost_class_nums
[rclass
];
1590 /* The hard register class is not a cover class or a
1591 class not fully inside in a cover class -- use
1592 the allocno cover class. */
1593 ira_assert (ira_hard_regno_cover_class
[regno
]
1595 num
= cost_class_nums
[cover_class
];
1597 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
1603 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1604 process_bb_node_for_hard_reg_moves
, NULL
);
1609 /* Function called once during compiler work. */
1611 ira_init_costs_once (void)
1616 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1619 this_op_costs
[i
] = NULL
;
1622 cost_classes
= NULL
;
1625 /* Free allocated temporary cost vectors. */
1627 free_ira_costs (void)
1631 if (init_cost
!= NULL
)
1634 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1636 if (op_costs
[i
] != NULL
)
1638 if (this_op_costs
[i
] != NULL
)
1639 free (this_op_costs
[i
]);
1640 op_costs
[i
] = this_op_costs
[i
] = NULL
;
1642 if (temp_costs
!= NULL
)
1645 if (cost_classes
!= NULL
)
1646 free (cost_classes
);
1647 cost_classes
= NULL
;
1650 /* This is called each time register related information is
1653 ira_init_costs (void)
1658 max_struct_costs_size
1659 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
1660 /* Don't use ira_allocate because vectors live through several IRA calls. */
1661 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
1662 init_cost
->mem_cost
= 1000000;
1663 for (i
= 0; i
< ira_important_classes_num
; i
++)
1664 init_cost
->cost
[i
] = 1000000;
1665 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1667 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
1668 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
1670 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
1671 cost_classes
= (enum reg_class
*) xmalloc (sizeof (enum reg_class
)
1672 * ira_important_classes_num
);
1675 /* Function called once at the end of compiler work. */
1677 ira_finish_costs_once (void)
1684 /* Common initialization function for ira_costs and
1685 ira_set_pseudo_classes. */
1689 init_subregs_of_mode ();
1690 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
1691 * cost_elements_num
);
1693 = (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
1694 * cost_elements_num
);
1696 = (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
1698 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
1699 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
1702 /* Common finalization function for ira_costs and
1703 ira_set_pseudo_classes. */
1707 ira_free (regno_equiv_gains
);
1708 ira_free (regno_cover_class
);
1709 ira_free (pref_buffer
);
1713 /* Entry function which defines cover class, memory and hard register
1714 costs for each allocno. */
1719 cost_elements_num
= ira_allocnos_num
;
1721 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
1722 * ira_allocnos_num
);
1723 calculate_elim_costs_all_insns ();
1724 find_costs_and_classes (ira_dump_file
);
1725 setup_allocno_cover_class_and_costs ();
1727 ira_free (total_allocno_costs
);
1730 /* Entry function which defines classes for pseudos. */
1732 ira_set_pseudo_classes (FILE *dump_file
)
1735 internal_flag_ira_verbose
= flag_ira_verbose
;
1736 cost_elements_num
= max_reg_num ();
1738 find_costs_and_classes (dump_file
);
1739 pseudo_classes_defined_p
= true;
1745 /* Change hard register costs for allocnos which lives through
1746 function calls. This is called only when we found all intersected
1747 calls during building allocno live ranges. */
1749 ira_tune_allocno_costs_and_cover_classes (void)
1752 int cost
, min_cost
, *reg_costs
;
1753 enum reg_class cover_class
, rclass
;
1754 enum machine_mode mode
;
1756 ira_allocno_iterator ai
;
1758 FOR_EACH_ALLOCNO (a
, ai
)
1760 cover_class
= ALLOCNO_COVER_CLASS (a
);
1761 if (cover_class
== NO_REGS
)
1763 mode
= ALLOCNO_MODE (a
);
1764 n
= ira_class_hard_regs_num
[cover_class
];
1766 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0)
1768 ira_allocate_and_set_costs
1769 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1770 ALLOCNO_COVER_CLASS_COST (a
));
1771 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
1772 for (j
= n
- 1; j
>= 0; j
--)
1774 regno
= ira_class_hard_regs
[cover_class
][j
];
1775 rclass
= REGNO_REG_CLASS (regno
);
1777 if (! ira_hard_reg_not_in_set_p (regno
, mode
, call_used_reg_set
)
1778 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
1779 cost
+= (ALLOCNO_CALL_FREQ (a
)
1780 * (ira_memory_move_cost
[mode
][rclass
][0]
1781 + ira_memory_move_cost
[mode
][rclass
][1]));
1782 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
1783 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
1784 + ira_memory_move_cost
[mode
][rclass
][1])
1786 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
1788 reg_costs
[j
] += cost
;
1789 if (min_cost
> reg_costs
[j
])
1790 min_cost
= reg_costs
[j
];
1793 if (min_cost
!= INT_MAX
)
1794 ALLOCNO_COVER_CLASS_COST (a
) = min_cost
;
1796 /* Some targets allow pseudos to be allocated to unaligned
1797 sequences of hard registers. However, selecting an unaligned
1798 sequence can unnecessarily restrict later allocations. So
1799 increase the cost of unaligned hard regs to encourage the use
1800 of aligned hard regs. */
1804 if ((nregs
= ira_reg_class_nregs
[cover_class
][ALLOCNO_MODE (a
)]) > 1)
1806 ira_allocate_and_set_costs
1807 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1808 ALLOCNO_COVER_CLASS_COST (a
));
1809 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
1810 for (j
= n
- 1; j
>= 0; j
--)
1814 regno
= ira_non_ordered_class_hard_regs
[cover_class
][j
];
1815 index
= ira_class_hard_reg_index
[cover_class
][regno
];
1816 ira_assert (index
!= -1);
1817 reg_costs
[index
] += ALLOCNO_FREQ (a
);
1825 /* Add COST to the estimated gain for eliminating REGNO with its
1826 equivalence. If COST is zero, record that no such elimination is
1830 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
1833 regno_equiv_gains
[regno
] = 0;
1835 regno_equiv_gains
[regno
] += cost
;