1 /* Decompose multiword subregs.
2 Copyright (C) 2007, 2008, 2009, 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Richard Henderson <rth@redhat.com>
5 Ian Lance Taylor <iant@google.com>
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "basic-block.h"
41 #include "tree-pass.h"
44 #ifdef STACK_GROWS_DOWNWARD
45 # undef STACK_GROWS_DOWNWARD
46 # define STACK_GROWS_DOWNWARD 1
48 # define STACK_GROWS_DOWNWARD 0
52 DEF_VEC_ALLOC_P (bitmap
,heap
);
54 /* Decompose multi-word pseudo-registers into individual
55 pseudo-registers when possible. This is possible when all the uses
56 of a multi-word register are via SUBREG, or are copies of the
57 register to another location. Breaking apart the register permits
58 more CSE and permits better register allocation. */
60 /* Bit N in this bitmap is set if regno N is used in a context in
61 which we can decompose it. */
62 static bitmap decomposable_context
;
64 /* Bit N in this bitmap is set if regno N is used in a context in
65 which it can not be decomposed. */
66 static bitmap non_decomposable_context
;
68 /* Bit N in this bitmap is set if regno N is used in a subreg
69 which changes the mode but not the size. This typically happens
70 when the register accessed as a floating-point value; we want to
71 avoid generating accesses to its subwords in integer modes. */
72 static bitmap subreg_context
;
74 /* Bit N in the bitmap in element M of this array is set if there is a
75 copy from reg M to reg N. */
76 static VEC(bitmap
,heap
) *reg_copy_graph
;
78 /* Return whether X is a simple object which we can take a word_mode
82 simple_move_operand (rtx x
)
84 if (GET_CODE (x
) == SUBREG
)
90 if (GET_CODE (x
) == LABEL_REF
91 || GET_CODE (x
) == SYMBOL_REF
92 || GET_CODE (x
) == HIGH
93 || GET_CODE (x
) == CONST
)
97 && (MEM_VOLATILE_P (x
)
98 || mode_dependent_address_p (XEXP (x
, 0))))
104 /* If INSN is a single set between two objects, return the single set.
105 Such an insn can always be decomposed. INSN should have been
106 passed to recog and extract_insn before this is called. */
109 simple_move (rtx insn
)
113 enum machine_mode mode
;
115 if (recog_data
.n_operands
!= 2)
118 set
= single_set (insn
);
123 if (x
!= recog_data
.operand
[0] && x
!= recog_data
.operand
[1])
125 if (!simple_move_operand (x
))
129 if (x
!= recog_data
.operand
[0] && x
!= recog_data
.operand
[1])
131 /* For the src we can handle ASM_OPERANDS, and it is beneficial for
132 things like x86 rdtsc which returns a DImode value. */
133 if (GET_CODE (x
) != ASM_OPERANDS
134 && !simple_move_operand (x
))
137 /* We try to decompose in integer modes, to avoid generating
138 inefficient code copying between integer and floating point
139 registers. That means that we can't decompose if this is a
140 non-integer mode for which there is no integer mode of the same
142 mode
= GET_MODE (SET_SRC (set
));
143 if (!SCALAR_INT_MODE_P (mode
)
144 && (mode_for_size (GET_MODE_SIZE (mode
) * BITS_PER_UNIT
, MODE_INT
, 0)
148 /* Reject PARTIAL_INT modes. They are used for processor specific
149 purposes and it's probably best not to tamper with them. */
150 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
156 /* If SET is a copy from one multi-word pseudo-register to another,
157 record that in reg_copy_graph. Return whether it is such a
161 find_pseudo_copy (rtx set
)
163 rtx dest
= SET_DEST (set
);
164 rtx src
= SET_SRC (set
);
168 if (!REG_P (dest
) || !REG_P (src
))
173 if (HARD_REGISTER_NUM_P (rd
) || HARD_REGISTER_NUM_P (rs
))
176 if (GET_MODE_SIZE (GET_MODE (dest
)) <= UNITS_PER_WORD
)
179 b
= VEC_index (bitmap
, reg_copy_graph
, rs
);
182 b
= BITMAP_ALLOC (NULL
);
183 VEC_replace (bitmap
, reg_copy_graph
, rs
, b
);
186 bitmap_set_bit (b
, rd
);
191 /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case
192 where they are copied to another register, add the register to
193 which they are copied to DECOMPOSABLE_CONTEXT. Use
194 NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track
195 copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */
198 propagate_pseudo_copies (void)
200 bitmap queue
, propagate
;
202 queue
= BITMAP_ALLOC (NULL
);
203 propagate
= BITMAP_ALLOC (NULL
);
205 bitmap_copy (queue
, decomposable_context
);
208 bitmap_iterator iter
;
211 bitmap_clear (propagate
);
213 EXECUTE_IF_SET_IN_BITMAP (queue
, 0, i
, iter
)
215 bitmap b
= VEC_index (bitmap
, reg_copy_graph
, i
);
217 bitmap_ior_and_compl_into (propagate
, b
, non_decomposable_context
);
220 bitmap_and_compl (queue
, propagate
, decomposable_context
);
221 bitmap_ior_into (decomposable_context
, propagate
);
223 while (!bitmap_empty_p (queue
));
226 BITMAP_FREE (propagate
);
229 /* A pointer to one of these values is passed to
230 find_decomposable_subregs via for_each_rtx. */
232 enum classify_move_insn
234 /* Not a simple move from one location to another. */
236 /* A simple move from one pseudo-register to another. */
237 SIMPLE_PSEUDO_REG_MOVE
,
238 /* A simple move involving a non-pseudo-register. */
242 /* This is called via for_each_rtx. If we find a SUBREG which we
243 could use to decompose a pseudo-register, set a bit in
244 DECOMPOSABLE_CONTEXT. If we find an unadorned register which is
245 not a simple pseudo-register copy, DATA will point at the type of
246 move, and we set a bit in DECOMPOSABLE_CONTEXT or
247 NON_DECOMPOSABLE_CONTEXT as appropriate. */
250 find_decomposable_subregs (rtx
*px
, void *data
)
252 enum classify_move_insn
*pcmi
= (enum classify_move_insn
*) data
;
258 if (GET_CODE (x
) == SUBREG
)
260 rtx inner
= SUBREG_REG (x
);
261 unsigned int regno
, outer_size
, inner_size
, outer_words
, inner_words
;
266 regno
= REGNO (inner
);
267 if (HARD_REGISTER_NUM_P (regno
))
270 outer_size
= GET_MODE_SIZE (GET_MODE (x
));
271 inner_size
= GET_MODE_SIZE (GET_MODE (inner
));
272 outer_words
= (outer_size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
273 inner_words
= (inner_size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
275 /* We only try to decompose single word subregs of multi-word
276 registers. When we find one, we return -1 to avoid iterating
277 over the inner register.
279 ??? This doesn't allow, e.g., DImode subregs of TImode values
280 on 32-bit targets. We would need to record the way the
281 pseudo-register was used, and only decompose if all the uses
282 were the same number and size of pieces. Hopefully this
283 doesn't happen much. */
285 if (outer_words
== 1 && inner_words
> 1)
287 bitmap_set_bit (decomposable_context
, regno
);
291 /* If this is a cast from one mode to another, where the modes
292 have the same size, and they are not tieable, then mark this
293 register as non-decomposable. If we decompose it we are
294 likely to mess up whatever the backend is trying to do. */
296 && outer_size
== inner_size
297 && !MODES_TIEABLE_P (GET_MODE (x
), GET_MODE (inner
)))
299 bitmap_set_bit (non_decomposable_context
, regno
);
300 bitmap_set_bit (subreg_context
, regno
);
308 /* We will see an outer SUBREG before we see the inner REG, so
309 when we see a plain REG here it means a direct reference to
312 If this is not a simple copy from one location to another,
313 then we can not decompose this register. If this is a simple
314 copy from one pseudo-register to another, and the mode is right
315 then we mark the register as decomposable.
316 Otherwise we don't say anything about this register --
317 it could be decomposed, but whether that would be
318 profitable depends upon how it is used elsewhere.
320 We only set bits in the bitmap for multi-word
321 pseudo-registers, since those are the only ones we care about
322 and it keeps the size of the bitmaps down. */
325 if (!HARD_REGISTER_NUM_P (regno
)
326 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
330 case NOT_SIMPLE_MOVE
:
331 bitmap_set_bit (non_decomposable_context
, regno
);
333 case SIMPLE_PSEUDO_REG_MOVE
:
334 if (MODES_TIEABLE_P (GET_MODE (x
), word_mode
))
335 bitmap_set_bit (decomposable_context
, regno
);
346 enum classify_move_insn cmi_mem
= NOT_SIMPLE_MOVE
;
348 /* Any registers used in a MEM do not participate in a
349 SIMPLE_MOVE or SIMPLE_PSEUDO_REG_MOVE. Do our own recursion
350 here, and return -1 to block the parent's recursion. */
351 for_each_rtx (&XEXP (x
, 0), find_decomposable_subregs
, &cmi_mem
);
358 /* Decompose REGNO into word-sized components. We smash the REG node
359 in place. This ensures that (1) something goes wrong quickly if we
360 fail to make some replacement, and (2) the debug information inside
361 the symbol table is automatically kept up to date. */
364 decompose_register (unsigned int regno
)
367 unsigned int words
, i
;
370 reg
= regno_reg_rtx
[regno
];
372 regno_reg_rtx
[regno
] = NULL_RTX
;
374 words
= GET_MODE_SIZE (GET_MODE (reg
));
375 words
= (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
377 v
= rtvec_alloc (words
);
378 for (i
= 0; i
< words
; ++i
)
379 RTVEC_ELT (v
, i
) = gen_reg_rtx_offset (reg
, word_mode
, i
* UNITS_PER_WORD
);
381 PUT_CODE (reg
, CONCATN
);
386 fprintf (dump_file
, "; Splitting reg %u ->", regno
);
387 for (i
= 0; i
< words
; ++i
)
388 fprintf (dump_file
, " %u", REGNO (XVECEXP (reg
, 0, i
)));
389 fputc ('\n', dump_file
);
393 /* Get a SUBREG of a CONCATN. */
396 simplify_subreg_concatn (enum machine_mode outermode
, rtx op
,
399 unsigned int inner_size
;
400 enum machine_mode innermode
, partmode
;
402 unsigned int final_offset
;
404 gcc_assert (GET_CODE (op
) == CONCATN
);
405 gcc_assert (byte
% GET_MODE_SIZE (outermode
) == 0);
407 innermode
= GET_MODE (op
);
408 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
409 gcc_assert (GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (innermode
));
411 inner_size
= GET_MODE_SIZE (innermode
) / XVECLEN (op
, 0);
412 part
= XVECEXP (op
, 0, byte
/ inner_size
);
413 partmode
= GET_MODE (part
);
415 /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of
416 regular CONST_VECTORs. They have vector or integer modes, depending
417 on the capabilities of the target. Cope with them. */
418 if (partmode
== VOIDmode
&& VECTOR_MODE_P (innermode
))
419 partmode
= GET_MODE_INNER (innermode
);
420 else if (partmode
== VOIDmode
)
422 enum mode_class mclass
= GET_MODE_CLASS (innermode
);
423 partmode
= mode_for_size (inner_size
* BITS_PER_UNIT
, mclass
, 0);
426 final_offset
= byte
% inner_size
;
427 if (final_offset
+ GET_MODE_SIZE (outermode
) > inner_size
)
430 return simplify_gen_subreg (outermode
, part
, partmode
, final_offset
);
433 /* Wrapper around simplify_gen_subreg which handles CONCATN. */
436 simplify_gen_subreg_concatn (enum machine_mode outermode
, rtx op
,
437 enum machine_mode innermode
, unsigned int byte
)
441 /* We have to handle generating a SUBREG of a SUBREG of a CONCATN.
442 If OP is a SUBREG of a CONCATN, then it must be a simple mode
443 change with the same size and offset 0, or it must extract a
444 part. We shouldn't see anything else here. */
445 if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == CONCATN
)
449 if ((GET_MODE_SIZE (GET_MODE (op
))
450 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
451 && SUBREG_BYTE (op
) == 0)
452 return simplify_gen_subreg_concatn (outermode
, SUBREG_REG (op
),
453 GET_MODE (SUBREG_REG (op
)), byte
);
455 op2
= simplify_subreg_concatn (GET_MODE (op
), SUBREG_REG (op
),
459 /* We don't handle paradoxical subregs here. */
460 gcc_assert (GET_MODE_SIZE (outermode
)
461 <= GET_MODE_SIZE (GET_MODE (op
)));
462 gcc_assert (GET_MODE_SIZE (GET_MODE (op
))
463 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))));
464 op2
= simplify_subreg_concatn (outermode
, SUBREG_REG (op
),
465 byte
+ SUBREG_BYTE (op
));
466 gcc_assert (op2
!= NULL_RTX
);
471 gcc_assert (op
!= NULL_RTX
);
472 gcc_assert (innermode
== GET_MODE (op
));
475 if (GET_CODE (op
) == CONCATN
)
476 return simplify_subreg_concatn (outermode
, op
, byte
);
478 ret
= simplify_gen_subreg (outermode
, op
, innermode
, byte
);
480 /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then
481 resolve_simple_move will ask for the high part of the paradoxical
482 subreg, which does not have a value. Just return a zero. */
484 && GET_CODE (op
) == SUBREG
485 && SUBREG_BYTE (op
) == 0
486 && (GET_MODE_SIZE (innermode
)
487 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
)))))
488 return CONST0_RTX (outermode
);
490 gcc_assert (ret
!= NULL_RTX
);
494 /* Return whether we should resolve X into the registers into which it
498 resolve_reg_p (rtx x
)
500 return GET_CODE (x
) == CONCATN
;
503 /* Return whether X is a SUBREG of a register which we need to
507 resolve_subreg_p (rtx x
)
509 if (GET_CODE (x
) != SUBREG
)
511 return resolve_reg_p (SUBREG_REG (x
));
514 /* This is called via for_each_rtx. Look for SUBREGs which need to be
518 resolve_subreg_use (rtx
*px
, void *data
)
520 rtx insn
= (rtx
) data
;
526 if (resolve_subreg_p (x
))
528 x
= simplify_subreg_concatn (GET_MODE (x
), SUBREG_REG (x
),
531 /* It is possible for a note to contain a reference which we can
532 decompose. In this case, return 1 to the caller to indicate
533 that the note must be removed. */
540 validate_change (insn
, px
, x
, 1);
544 if (resolve_reg_p (x
))
546 /* Return 1 to the caller to indicate that we found a direct
547 reference to a register which is being decomposed. This can
548 happen inside notes, multiword shift or zero-extend
556 /* This is called via for_each_rtx. Look for SUBREGs which can be
557 decomposed and decomposed REGs that need copying. */
560 adjust_decomposed_uses (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
567 if (resolve_subreg_p (x
))
569 x
= simplify_subreg_concatn (GET_MODE (x
), SUBREG_REG (x
),
578 if (resolve_reg_p (x
))
584 /* Resolve any decomposed registers which appear in register notes on
588 resolve_reg_notes (rtx insn
)
592 note
= find_reg_equal_equiv_note (insn
);
595 int old_count
= num_validated_changes ();
596 if (for_each_rtx (&XEXP (note
, 0), resolve_subreg_use
, NULL
))
597 remove_note (insn
, note
);
599 if (old_count
!= num_validated_changes ())
600 df_notes_rescan (insn
);
603 pnote
= ®_NOTES (insn
);
604 while (*pnote
!= NULL_RTX
)
609 switch (REG_NOTE_KIND (note
))
613 if (resolve_reg_p (XEXP (note
, 0)))
622 *pnote
= XEXP (note
, 1);
624 pnote
= &XEXP (note
, 1);
628 /* Return whether X can be decomposed into subwords. */
631 can_decompose_p (rtx x
)
635 unsigned int regno
= REGNO (x
);
637 if (HARD_REGISTER_NUM_P (regno
))
639 unsigned int byte
, num_bytes
;
641 num_bytes
= GET_MODE_SIZE (GET_MODE (x
));
642 for (byte
= 0; byte
< num_bytes
; byte
+= UNITS_PER_WORD
)
643 if (simplify_subreg_regno (regno
, GET_MODE (x
), byte
, word_mode
) < 0)
648 return !bitmap_bit_p (subreg_context
, regno
);
654 /* Decompose the registers used in a simple move SET within INSN. If
655 we don't change anything, return INSN, otherwise return the start
656 of the sequence of moves. */
659 resolve_simple_move (rtx set
, rtx insn
)
661 rtx src
, dest
, real_dest
, insns
;
662 enum machine_mode orig_mode
, dest_mode
;
667 dest
= SET_DEST (set
);
668 orig_mode
= GET_MODE (dest
);
670 words
= (GET_MODE_SIZE (orig_mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
676 /* We have to handle copying from a SUBREG of a decomposed reg where
677 the SUBREG is larger than word size. Rather than assume that we
678 can take a word_mode SUBREG of the destination, we copy to a new
679 register and then copy that to the destination. */
681 real_dest
= NULL_RTX
;
683 if (GET_CODE (src
) == SUBREG
684 && resolve_reg_p (SUBREG_REG (src
))
685 && (SUBREG_BYTE (src
) != 0
686 || (GET_MODE_SIZE (orig_mode
)
687 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))))
690 dest
= gen_reg_rtx (orig_mode
);
691 if (REG_P (real_dest
))
692 REG_ATTRS (dest
) = REG_ATTRS (real_dest
);
695 /* Similarly if we are copying to a SUBREG of a decomposed reg where
696 the SUBREG is larger than word size. */
698 if (GET_CODE (dest
) == SUBREG
699 && resolve_reg_p (SUBREG_REG (dest
))
700 && (SUBREG_BYTE (dest
) != 0
701 || (GET_MODE_SIZE (orig_mode
)
702 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
))))))
704 rtx reg
, minsn
, smove
;
706 reg
= gen_reg_rtx (orig_mode
);
707 minsn
= emit_move_insn (reg
, src
);
708 smove
= single_set (minsn
);
709 gcc_assert (smove
!= NULL_RTX
);
710 resolve_simple_move (smove
, minsn
);
714 /* If we didn't have any big SUBREGS of decomposed registers, and
715 neither side of the move is a register we are decomposing, then
716 we don't have to do anything here. */
718 if (src
== SET_SRC (set
)
719 && dest
== SET_DEST (set
)
720 && !resolve_reg_p (src
)
721 && !resolve_subreg_p (src
)
722 && !resolve_reg_p (dest
)
723 && !resolve_subreg_p (dest
))
729 /* It's possible for the code to use a subreg of a decomposed
730 register while forming an address. We need to handle that before
731 passing the address to emit_move_insn. We pass NULL_RTX as the
732 insn parameter to resolve_subreg_use because we can not validate
734 if (MEM_P (src
) || MEM_P (dest
))
739 for_each_rtx (&XEXP (src
, 0), resolve_subreg_use
, NULL_RTX
);
741 for_each_rtx (&XEXP (dest
, 0), resolve_subreg_use
, NULL_RTX
);
742 acg
= apply_change_group ();
746 /* If SRC is a register which we can't decompose, or has side
747 effects, we need to move via a temporary register. */
749 if (!can_decompose_p (src
)
750 || side_effects_p (src
)
751 || GET_CODE (src
) == ASM_OPERANDS
)
755 reg
= gen_reg_rtx (orig_mode
);
756 emit_move_insn (reg
, src
);
760 /* If DEST is a register which we can't decompose, or has side
761 effects, we need to first move to a temporary register. We
762 handle the common case of pushing an operand directly. We also
763 go through a temporary register if it holds a floating point
764 value. This gives us better code on systems which can't move
765 data easily between integer and floating point registers. */
767 dest_mode
= orig_mode
;
768 pushing
= push_operand (dest
, dest_mode
);
769 if (!can_decompose_p (dest
)
770 || (side_effects_p (dest
) && !pushing
)
771 || (!SCALAR_INT_MODE_P (dest_mode
)
772 && !resolve_reg_p (dest
)
773 && !resolve_subreg_p (dest
)))
775 if (real_dest
== NULL_RTX
)
777 if (!SCALAR_INT_MODE_P (dest_mode
))
779 dest_mode
= mode_for_size (GET_MODE_SIZE (dest_mode
) * BITS_PER_UNIT
,
781 gcc_assert (dest_mode
!= BLKmode
);
783 dest
= gen_reg_rtx (dest_mode
);
784 if (REG_P (real_dest
))
785 REG_ATTRS (dest
) = REG_ATTRS (real_dest
);
790 unsigned int i
, j
, jinc
;
792 gcc_assert (GET_MODE_SIZE (orig_mode
) % UNITS_PER_WORD
== 0);
793 gcc_assert (GET_CODE (XEXP (dest
, 0)) != PRE_MODIFY
);
794 gcc_assert (GET_CODE (XEXP (dest
, 0)) != POST_MODIFY
);
796 if (WORDS_BIG_ENDIAN
== STACK_GROWS_DOWNWARD
)
807 for (i
= 0; i
< words
; ++i
, j
+= jinc
)
811 temp
= copy_rtx (XEXP (dest
, 0));
812 temp
= adjust_automodify_address_nv (dest
, word_mode
, temp
,
814 emit_move_insn (temp
,
815 simplify_gen_subreg_concatn (word_mode
, src
,
817 j
* UNITS_PER_WORD
));
824 if (REG_P (dest
) && !HARD_REGISTER_NUM_P (REGNO (dest
)))
827 for (i
= 0; i
< words
; ++i
)
828 emit_move_insn (simplify_gen_subreg_concatn (word_mode
, dest
,
831 simplify_gen_subreg_concatn (word_mode
, src
,
833 i
* UNITS_PER_WORD
));
836 if (real_dest
!= NULL_RTX
)
838 rtx mdest
, minsn
, smove
;
840 if (dest_mode
== orig_mode
)
843 mdest
= simplify_gen_subreg (orig_mode
, dest
, GET_MODE (dest
), 0);
844 minsn
= emit_move_insn (real_dest
, mdest
);
846 smove
= single_set (minsn
);
847 gcc_assert (smove
!= NULL_RTX
);
849 resolve_simple_move (smove
, minsn
);
852 insns
= get_insns ();
855 copy_reg_eh_region_note_forward (insn
, insns
, NULL_RTX
);
857 emit_insn_before (insns
, insn
);
864 /* Change a CLOBBER of a decomposed register into a CLOBBER of the
865 component registers. Return whether we changed something. */
868 resolve_clobber (rtx pat
, rtx insn
)
871 enum machine_mode orig_mode
;
872 unsigned int words
, i
;
876 if (!resolve_reg_p (reg
) && !resolve_subreg_p (reg
))
879 orig_mode
= GET_MODE (reg
);
880 words
= GET_MODE_SIZE (orig_mode
);
881 words
= (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
883 ret
= validate_change (NULL_RTX
, &XEXP (pat
, 0),
884 simplify_gen_subreg_concatn (word_mode
, reg
,
887 df_insn_rescan (insn
);
888 gcc_assert (ret
!= 0);
890 for (i
= words
- 1; i
> 0; --i
)
894 x
= simplify_gen_subreg_concatn (word_mode
, reg
, orig_mode
,
896 x
= gen_rtx_CLOBBER (VOIDmode
, x
);
897 emit_insn_after (x
, insn
);
900 resolve_reg_notes (insn
);
905 /* A USE of a decomposed register is no longer meaningful. Return
906 whether we changed something. */
909 resolve_use (rtx pat
, rtx insn
)
911 if (resolve_reg_p (XEXP (pat
, 0)) || resolve_subreg_p (XEXP (pat
, 0)))
917 resolve_reg_notes (insn
);
922 /* A VAR_LOCATION can be simplified. */
925 resolve_debug (rtx insn
)
927 for_each_rtx (&PATTERN (insn
), adjust_decomposed_uses
, NULL_RTX
);
929 df_insn_rescan (insn
);
931 resolve_reg_notes (insn
);
934 /* Checks if INSN is a decomposable multiword-shift or zero-extend and
935 sets the decomposable_context bitmap accordingly. A non-zero value
936 is returned if a decomposable insn has been found. */
939 find_decomposable_shift_zext (rtx insn
)
945 set
= single_set (insn
);
950 if (GET_CODE (op
) != ASHIFT
951 && GET_CODE (op
) != LSHIFTRT
952 && GET_CODE (op
) != ZERO_EXTEND
)
955 op_operand
= XEXP (op
, 0);
956 if (!REG_P (SET_DEST (set
)) || !REG_P (op_operand
)
957 || HARD_REGISTER_NUM_P (REGNO (SET_DEST (set
)))
958 || HARD_REGISTER_NUM_P (REGNO (op_operand
))
959 || !SCALAR_INT_MODE_P (GET_MODE (op
)))
962 if (GET_CODE (op
) == ZERO_EXTEND
)
964 if (GET_MODE (op_operand
) != word_mode
965 || GET_MODE_BITSIZE (GET_MODE (op
)) != 2 * BITS_PER_WORD
)
968 else /* left or right shift */
970 if (!CONST_INT_P (XEXP (op
, 1))
971 || INTVAL (XEXP (op
, 1)) < BITS_PER_WORD
972 || GET_MODE_BITSIZE (GET_MODE (op_operand
)) != 2 * BITS_PER_WORD
)
976 bitmap_set_bit (decomposable_context
, REGNO (SET_DEST (set
)));
978 if (GET_CODE (op
) != ZERO_EXTEND
)
979 bitmap_set_bit (decomposable_context
, REGNO (op_operand
));
984 /* Decompose a more than word wide shift (in INSN) of a multiword
985 pseudo or a multiword zero-extend of a wordmode pseudo into a move
986 and 'set to zero' insn. Return a pointer to the new insn when a
987 replacement was done. */
990 resolve_shift_zext (rtx insn
)
996 rtx src_reg
, dest_reg
, dest_zero
;
997 int src_reg_num
, dest_reg_num
, offset1
, offset2
, src_offset
;
999 set
= single_set (insn
);
1004 if (GET_CODE (op
) != ASHIFT
1005 && GET_CODE (op
) != LSHIFTRT
1006 && GET_CODE (op
) != ZERO_EXTEND
)
1009 op_operand
= XEXP (op
, 0);
1011 if (!resolve_reg_p (SET_DEST (set
)) && !resolve_reg_p (op_operand
))
1014 /* src_reg_num is the number of the word mode register which we
1015 are operating on. For a left shift and a zero_extend on little
1016 endian machines this is register 0. */
1017 src_reg_num
= GET_CODE (op
) == LSHIFTRT
? 1 : 0;
1019 if (WORDS_BIG_ENDIAN
1020 && GET_MODE_SIZE (GET_MODE (op_operand
)) > UNITS_PER_WORD
)
1021 src_reg_num
= 1 - src_reg_num
;
1023 if (GET_CODE (op
) == ZERO_EXTEND
)
1024 dest_reg_num
= WORDS_BIG_ENDIAN
? 1 : 0;
1026 dest_reg_num
= 1 - src_reg_num
;
1028 offset1
= UNITS_PER_WORD
* dest_reg_num
;
1029 offset2
= UNITS_PER_WORD
* (1 - dest_reg_num
);
1030 src_offset
= UNITS_PER_WORD
* src_reg_num
;
1034 dest_reg
= simplify_gen_subreg_concatn (word_mode
, SET_DEST (set
),
1035 GET_MODE (SET_DEST (set
)),
1037 dest_zero
= simplify_gen_subreg_concatn (word_mode
, SET_DEST (set
),
1038 GET_MODE (SET_DEST (set
)),
1040 src_reg
= simplify_gen_subreg_concatn (word_mode
, op_operand
,
1041 GET_MODE (op_operand
),
1043 if (GET_CODE (op
) != ZERO_EXTEND
)
1045 int shift_count
= INTVAL (XEXP (op
, 1));
1046 if (shift_count
> BITS_PER_WORD
)
1047 src_reg
= expand_shift (GET_CODE (op
) == ASHIFT
?
1048 LSHIFT_EXPR
: RSHIFT_EXPR
,
1050 shift_count
- BITS_PER_WORD
,
1054 if (dest_reg
!= src_reg
)
1055 emit_move_insn (dest_reg
, src_reg
);
1056 emit_move_insn (dest_zero
, CONST0_RTX (word_mode
));
1057 insns
= get_insns ();
1061 emit_insn_before (insns
, insn
);
1066 fprintf (dump_file
, "; Replacing insn: %d with insns: ", INSN_UID (insn
));
1067 for (in
= insns
; in
!= insn
; in
= NEXT_INSN (in
))
1068 fprintf (dump_file
, "%d ", INSN_UID (in
));
1069 fprintf (dump_file
, "\n");
1076 /* Look for registers which are always accessed via word-sized SUBREGs
1077 or via copies. Decompose these registers into several word-sized
1078 pseudo-registers. */
1081 decompose_multiword_subregs (void)
1087 df_set_flags (DF_DEFER_INSN_RESCAN
);
1089 max
= max_reg_num ();
1091 /* First see if there are any multi-word pseudo-registers. If there
1092 aren't, there is nothing we can do. This should speed up this
1093 pass in the normal case, since it should be faster than scanning
1098 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; ++i
)
1100 if (regno_reg_rtx
[i
] != NULL
1101 && GET_MODE_SIZE (GET_MODE (regno_reg_rtx
[i
])) > UNITS_PER_WORD
)
1111 /* FIXME: When the dataflow branch is merged, we can change this
1112 code to look for each multi-word pseudo-register and to find each
1113 insn which sets or uses that register. That should be faster
1114 than scanning all the insns. */
1116 decomposable_context
= BITMAP_ALLOC (NULL
);
1117 non_decomposable_context
= BITMAP_ALLOC (NULL
);
1118 subreg_context
= BITMAP_ALLOC (NULL
);
1120 reg_copy_graph
= VEC_alloc (bitmap
, heap
, max
);
1121 VEC_safe_grow (bitmap
, heap
, reg_copy_graph
, max
);
1122 memset (VEC_address (bitmap
, reg_copy_graph
), 0, sizeof (bitmap
) * max
);
1128 FOR_BB_INSNS (bb
, insn
)
1131 enum classify_move_insn cmi
;
1135 || GET_CODE (PATTERN (insn
)) == CLOBBER
1136 || GET_CODE (PATTERN (insn
)) == USE
)
1139 recog_memoized (insn
);
1141 if (find_decomposable_shift_zext (insn
))
1144 extract_insn (insn
);
1146 set
= simple_move (insn
);
1149 cmi
= NOT_SIMPLE_MOVE
;
1152 if (find_pseudo_copy (set
))
1153 cmi
= SIMPLE_PSEUDO_REG_MOVE
;
1158 n
= recog_data
.n_operands
;
1159 for (i
= 0; i
< n
; ++i
)
1161 for_each_rtx (&recog_data
.operand
[i
],
1162 find_decomposable_subregs
,
1165 /* We handle ASM_OPERANDS as a special case to support
1166 things like x86 rdtsc which returns a DImode value.
1167 We can decompose the output, which will certainly be
1168 operand 0, but not the inputs. */
1170 if (cmi
== SIMPLE_MOVE
1171 && GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1173 gcc_assert (i
== 0);
1174 cmi
= NOT_SIMPLE_MOVE
;
1180 bitmap_and_compl_into (decomposable_context
, non_decomposable_context
);
1181 if (!bitmap_empty_p (decomposable_context
))
1185 sbitmap_iterator sbi
;
1186 bitmap_iterator iter
;
1189 propagate_pseudo_copies ();
1191 sub_blocks
= sbitmap_alloc (last_basic_block
);
1192 sbitmap_zero (sub_blocks
);
1194 EXECUTE_IF_SET_IN_BITMAP (decomposable_context
, 0, regno
, iter
)
1195 decompose_register (regno
);
1201 FOR_BB_INSNS (bb
, insn
)
1208 pat
= PATTERN (insn
);
1209 if (GET_CODE (pat
) == CLOBBER
)
1210 resolve_clobber (pat
, insn
);
1211 else if (GET_CODE (pat
) == USE
)
1212 resolve_use (pat
, insn
);
1213 else if (DEBUG_INSN_P (insn
))
1214 resolve_debug (insn
);
1220 recog_memoized (insn
);
1221 extract_insn (insn
);
1223 set
= simple_move (insn
);
1226 rtx orig_insn
= insn
;
1227 bool cfi
= control_flow_insn_p (insn
);
1229 /* We can end up splitting loads to multi-word pseudos
1230 into separate loads to machine word size pseudos.
1231 When this happens, we first had one load that can
1232 throw, and after resolve_simple_move we'll have a
1233 bunch of loads (at least two). All those loads may
1234 trap if we can have non-call exceptions, so they
1235 all will end the current basic block. We split the
1236 block after the outer loop over all insns, but we
1237 make sure here that we will be able to split the
1238 basic block and still produce the correct control
1239 flow graph for it. */
1241 || (cfun
->can_throw_non_call_exceptions
1242 && can_throw_internal (insn
)));
1244 insn
= resolve_simple_move (set
, insn
);
1245 if (insn
!= orig_insn
)
1247 recog_memoized (insn
);
1248 extract_insn (insn
);
1251 SET_BIT (sub_blocks
, bb
->index
);
1256 rtx decomposed_shift
;
1258 decomposed_shift
= resolve_shift_zext (insn
);
1259 if (decomposed_shift
!= NULL_RTX
)
1261 insn
= decomposed_shift
;
1262 recog_memoized (insn
);
1263 extract_insn (insn
);
1267 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
1268 for_each_rtx (recog_data
.operand_loc
[i
],
1272 resolve_reg_notes (insn
);
1274 if (num_validated_changes () > 0)
1276 for (i
= recog_data
.n_dups
- 1; i
>= 0; --i
)
1278 rtx
*pl
= recog_data
.dup_loc
[i
];
1279 int dup_num
= recog_data
.dup_num
[i
];
1280 rtx
*px
= recog_data
.operand_loc
[dup_num
];
1282 validate_unshare_change (insn
, pl
, *px
, 1);
1285 i
= apply_change_group ();
1292 /* If we had insns to split that caused control flow insns in the middle
1293 of a basic block, split those blocks now. Note that we only handle
1294 the case where splitting a load has caused multiple possibly trapping
1296 EXECUTE_IF_SET_IN_SBITMAP (sub_blocks
, 0, i
, sbi
)
1301 bb
= BASIC_BLOCK (i
);
1302 insn
= BB_HEAD (bb
);
1307 if (control_flow_insn_p (insn
))
1309 /* Split the block after insn. There will be a fallthru
1310 edge, which is OK so we keep it. We have to create the
1311 exception edges ourselves. */
1312 fallthru
= split_block (bb
, insn
);
1313 rtl_make_eh_edge (NULL
, bb
, BB_END (bb
));
1314 bb
= fallthru
->dest
;
1315 insn
= BB_HEAD (bb
);
1318 insn
= NEXT_INSN (insn
);
1322 sbitmap_free (sub_blocks
);
1329 FOR_EACH_VEC_ELT (bitmap
, reg_copy_graph
, i
, b
)
1334 VEC_free (bitmap
, heap
, reg_copy_graph
);
1336 BITMAP_FREE (decomposable_context
);
1337 BITMAP_FREE (non_decomposable_context
);
1338 BITMAP_FREE (subreg_context
);
1341 /* Gate function for lower subreg pass. */
1344 gate_handle_lower_subreg (void)
1346 return flag_split_wide_types
!= 0;
1349 /* Implement first lower subreg pass. */
1352 rest_of_handle_lower_subreg (void)
1354 decompose_multiword_subregs ();
1358 /* Implement second lower subreg pass. */
1361 rest_of_handle_lower_subreg2 (void)
1363 decompose_multiword_subregs ();
1367 struct rtl_opt_pass pass_lower_subreg
=
1371 "subreg1", /* name */
1372 gate_handle_lower_subreg
, /* gate */
1373 rest_of_handle_lower_subreg
, /* execute */
1376 0, /* static_pass_number */
1377 TV_LOWER_SUBREG
, /* tv_id */
1378 0, /* properties_required */
1379 0, /* properties_provided */
1380 0, /* properties_destroyed */
1381 0, /* todo_flags_start */
1383 TODO_verify_flow
/* todo_flags_finish */
1387 struct rtl_opt_pass pass_lower_subreg2
=
1391 "subreg2", /* name */
1392 gate_handle_lower_subreg
, /* gate */
1393 rest_of_handle_lower_subreg2
, /* execute */
1396 0, /* static_pass_number */
1397 TV_LOWER_SUBREG
, /* tv_id */
1398 0, /* properties_required */
1399 0, /* properties_provided */
1400 0, /* properties_destroyed */
1401 0, /* todo_flags_start */
1402 TODO_df_finish
| TODO_verify_rtl_sharing
|
1404 TODO_verify_flow
/* todo_flags_finish */