gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
   4    2011, 2012 Free Software Foundation, Inc.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "diagnostic-core.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105 #include "df.h"
 106 #include "cgraph.h"
 107 #include "obstack.h"
 108
 109 /* Number of attempts to combine instructions in this function.  */
 110
 111 static int combine_attempts;
 112
 113 /* Number of attempts that got as far as substitution in this function.  */
 114
 115 static int combine_merges;
 116
 117 /* Number of instructions combined with added SETs in this function.  */
 118
 119 static int combine_extras;
 120
 121 /* Number of instructions combined in this function.  */
 122
 123 static int combine_successes;
 124
 125 /* Totals over entire compilation.  */
 126
 127 static int total_attempts, total_merges, total_extras, total_successes;
 128
 129 /* combine_instructions may try to replace the right hand side of the
 130    second instruction with the value of an associated REG_EQUAL note
 131    before throwing it at try_combine.  That is problematic when there
 132    is a REG_DEAD note for a register used in the old right hand side
 133    and can cause distribute_notes to do wrong things.  This is the
 134    second instruction if it has been so modified, null otherwise.  */
 135
 136 static rtx i2mod;
 137
 138 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 139
 140 static rtx i2mod_old_rhs;
 141
 142 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 143
 144 static rtx i2mod_new_rhs;
 145 \f
 146 typedef struct reg_stat_struct {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 } reg_stat_type;
 254
 255 DEF_VEC_O(reg_stat_type);
 256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
 257
 258 static VEC(reg_stat_type,heap) *reg_stat;
 259
 260 /* Record the luid of the last insn that invalidated memory
 261    (anything that writes memory, and subroutine calls, but not pushes).  */
 262
 263 static int mem_last_set;
 264
 265 /* Record the luid of the last CALL_INSN
 266    so we can tell whether a potential combination crosses any calls.  */
 267
 268 static int last_call_luid;
 269
 270 /* When `subst' is called, this is the insn that is being modified
 271    (by combining in a previous insn).  The PATTERN of this insn
 272    is still the old pattern partially modified and it should not be
 273    looked at, but this may be used to examine the successors of the insn
 274    to judge whether a simplification is valid.  */
 275
 276 static rtx subst_insn;
 277
 278 /* This is the lowest LUID that `subst' is currently dealing with.
 279    get_last_value will not return a value if the register was set at or
 280    after this LUID.  If not for this mechanism, we could get confused if
 281    I2 or I1 in try_combine were an insn that used the old value of a register
 282    to obtain a new value.  In that case, we might erroneously get the
 283    new value of the register when we wanted the old one.  */
 284
 285 static int subst_low_luid;
 286
 287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 288    must consider all these registers to be always live.  */
 289
 290 static HARD_REG_SET newpat_used_regs;
 291
 292 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 293    insn is the earlier than I2 or I3, combine should rescan starting at
 294    that location.  */
 295
 296 static rtx added_links_insn;
 297
 298 /* Basic block in which we are performing combines.  */
 299 static basic_block this_basic_block;
 300 static bool optimize_this_for_speed_p;
 301
 302 \f
 303 /* Length of the currently allocated uid_insn_cost array.  */
 304
 305 static int max_uid_known;
 306
 307 /* The following array records the insn_rtx_cost for every insn
 308    in the instruction stream.  */
 309
 310 static int *uid_insn_cost;
 311
 312 /* The following array records the LOG_LINKS for every insn in the
 313    instruction stream as struct insn_link pointers.  */
 314
 315 struct insn_link {
 316   rtx insn;
 317   struct insn_link *next;
 318 };
 319
 320 static struct insn_link **uid_log_links;
 321
 322 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 323 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 324
 325 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 326   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 327
 328 /* Links for LOG_LINKS are allocated from this obstack.  */
 329
 330 static struct obstack insn_link_obstack;
 331
 332 /* Allocate a link.  */
 333
 334 static inline struct insn_link *
 335 alloc_insn_link (rtx insn, struct insn_link *next)
 336 {
 337   struct insn_link *l
 338     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 339                                           sizeof (struct insn_link));
 340   l->insn = insn;
 341   l->next = next;
 342   return l;
 343 }
 344
 345 /* Incremented for each basic block.  */
 346
 347 static int label_tick;
 348
 349 /* Reset to label_tick for each extended basic block in scanning order.  */
 350
 351 static int label_tick_ebb_start;
 352
 353 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 354    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 355
 356 static enum machine_mode nonzero_bits_mode;
 357
 358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 359    be safely used.  It is zero while computing them and after combine has
 360    completed.  This former test prevents propagating values based on
 361    previously set values, which can be incorrect if a variable is modified
 362    in a loop.  */
 363
 364 static int nonzero_sign_valid;
 365
 366 \f
 367 /* Record one modification to rtl structure
 368    to be undone by storing old_contents into *where.  */
 369
 370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 371
 372 struct undo
 373 {
 374   struct undo *next;
 375   enum undo_kind kind;
 376   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 377   union { rtx *r; int *i; struct insn_link **l; } where;
 378 };
 379
 380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 381    num_undo says how many are currently recorded.
 382
 383    other_insn is nonzero if we have modified some other insn in the process
 384    of working on subst_insn.  It must be verified too.  */
 385
 386 struct undobuf
 387 {
 388   struct undo *undos;
 389   struct undo *frees;
 390   rtx other_insn;
 391 };
 392
 393 static struct undobuf undobuf;
 394
 395 /* Number of times the pseudo being substituted for
 396    was found and replaced.  */
 397
 398 static int n_occurrences;
 399
 400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                          enum machine_mode,
 402                                          unsigned HOST_WIDE_INT,
 403                                          unsigned HOST_WIDE_INT *);
 404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 405                                                 enum machine_mode,
 406                                                 unsigned int, unsigned int *);
 407 static void do_SUBST (rtx *, rtx);
 408 static void do_SUBST_INT (int *, int);
 409 static void init_reg_last (void);
 410 static void setup_incoming_promotions (rtx);
 411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 412 static int cant_combine_insn_p (rtx);
 413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 415 static int contains_muldiv (rtx);
 416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 417 static void undo_all (void);
 418 static void undo_commit (void);
 419 static rtx *find_split_point (rtx *, rtx, bool);
 420 static rtx subst (rtx, rtx, rtx, int, int, int);
 421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 422 static rtx simplify_if_then_else (rtx);
 423 static rtx simplify_set (rtx);
 424 static rtx simplify_logical (rtx);
 425 static rtx expand_compound_operation (rtx);
 426 static const_rtx expand_field_assignment (const_rtx);
 427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 428                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 429 static rtx extract_left_shift (rtx, int);
 430 static rtx make_compound_operation (rtx, enum rtx_code);
 431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 432                               unsigned HOST_WIDE_INT *);
 433 static rtx canon_reg_for_combine (rtx, rtx);
 434 static rtx force_to_mode (rtx, enum machine_mode,
 435                           unsigned HOST_WIDE_INT, int);
 436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 439 static rtx make_field_assignment (rtx);
 440 static rtx apply_distributive_law (rtx);
 441 static rtx distribute_and_simplify_rtx (rtx, int);
 442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 443                                      unsigned HOST_WIDE_INT);
 444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 445                                    unsigned HOST_WIDE_INT);
 446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 447                             HOST_WIDE_INT, enum machine_mode, int *);
 448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 450                                  int);
 451 static int recog_for_combine (rtx *, rtx, rtx *);
 452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 453 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 454 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 455 static void update_table_tick (rtx);
 456 static void record_value_for_reg (rtx, rtx, rtx);
 457 static void check_promoted_subreg (rtx, rtx);
 458 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 459 static void record_dead_and_set_regs (rtx);
 460 static int get_last_value_validate (rtx *, rtx, int, int);
 461 static rtx get_last_value (const_rtx);
 462 static int use_crosses_set_p (const_rtx, int);
 463 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 464 static int reg_dead_at_p (rtx, rtx);
 465 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 466 static int reg_bitfield_target_p (rtx, rtx);
 467 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 468 static void distribute_links (struct insn_link *);
 469 static void mark_used_regs_combine (rtx);
 470 static void record_promoted_value (rtx, rtx);
 471 static int unmentioned_reg_p_1 (rtx *, void *);
 472 static bool unmentioned_reg_p (rtx, rtx);
 473 static int record_truncated_value (rtx *, void *);
 474 static void record_truncated_values (rtx *, void *);
 475 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 476 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 477 \f
 478
 479 /* It is not safe to use ordinary gen_lowpart in combine.
 480    See comments in gen_lowpart_for_combine.  */
 481 #undef RTL_HOOKS_GEN_LOWPART
 482 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 483
 484 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 487
 488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 489 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 490
 491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 493
 494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 496
 497 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 498
 499 \f
 500 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 501    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 502    This is a wrapper around split_insns which ensures that the
 503    reg_stat vector is made larger if the splitter creates a new
 504    register.  */
 505
 506 static rtx
 507 combine_split_insns (rtx pattern, rtx insn)
 508 {
 509   rtx ret;
 510   unsigned int nregs;
 511
 512   ret = split_insns (pattern, insn);
 513   nregs = max_reg_num ();
 514   if (nregs > VEC_length (reg_stat_type, reg_stat))
 515     VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
 516   return ret;
 517 }
 518
 519 /* This is used by find_single_use to locate an rtx in LOC that
 520    contains exactly one use of DEST, which is typically either a REG
 521    or CC0.  It returns a pointer to the innermost rtx expression
 522    containing DEST.  Appearances of DEST that are being used to
 523    totally replace it are not counted.  */
 524
 525 static rtx *
 526 find_single_use_1 (rtx dest, rtx *loc)
 527 {
 528   rtx x = *loc;
 529   enum rtx_code code = GET_CODE (x);
 530   rtx *result = NULL;
 531   rtx *this_result;
 532   int i;
 533   const char *fmt;
 534
 535   switch (code)
 536     {
 537     case CONST_INT:
 538     case CONST:
 539     case LABEL_REF:
 540     case SYMBOL_REF:
 541     case CONST_DOUBLE:
 542     case CONST_VECTOR:
 543     case CLOBBER:
 544       return 0;
 545
 546     case SET:
 547       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 548          of a REG that occupies all of the REG, the insn uses DEST if
 549          it is mentioned in the destination or the source.  Otherwise, we
 550          need just check the source.  */
 551       if (GET_CODE (SET_DEST (x)) != CC0
 552           && GET_CODE (SET_DEST (x)) != PC
 553           && !REG_P (SET_DEST (x))
 554           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 555                 && REG_P (SUBREG_REG (SET_DEST (x)))
 556                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 557                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 558                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 559                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 560         break;
 561
 562       return find_single_use_1 (dest, &SET_SRC (x));
 563
 564     case MEM:
 565     case SUBREG:
 566       return find_single_use_1 (dest, &XEXP (x, 0));
 567
 568     default:
 569       break;
 570     }
 571
 572   /* If it wasn't one of the common cases above, check each expression and
 573      vector of this code.  Look for a unique usage of DEST.  */
 574
 575   fmt = GET_RTX_FORMAT (code);
 576   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 577     {
 578       if (fmt[i] == 'e')
 579         {
 580           if (dest == XEXP (x, i)
 581               || (REG_P (dest) && REG_P (XEXP (x, i))
 582                   && REGNO (dest) == REGNO (XEXP (x, i))))
 583             this_result = loc;
 584           else
 585             this_result = find_single_use_1 (dest, &XEXP (x, i));
 586
 587           if (result == NULL)
 588             result = this_result;
 589           else if (this_result)
 590             /* Duplicate usage.  */
 591             return NULL;
 592         }
 593       else if (fmt[i] == 'E')
 594         {
 595           int j;
 596
 597           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 598             {
 599               if (XVECEXP (x, i, j) == dest
 600                   || (REG_P (dest)
 601                       && REG_P (XVECEXP (x, i, j))
 602                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 603                 this_result = loc;
 604               else
 605                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 606
 607               if (result == NULL)
 608                 result = this_result;
 609               else if (this_result)
 610                 return NULL;
 611             }
 612         }
 613     }
 614
 615   return result;
 616 }
 617
 618
 619 /* See if DEST, produced in INSN, is used only a single time in the
 620    sequel.  If so, return a pointer to the innermost rtx expression in which
 621    it is used.
 622
 623    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 624
 625    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 626    care about REG_DEAD notes or LOG_LINKS.
 627
 628    Otherwise, we find the single use by finding an insn that has a
 629    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 630    only referenced once in that insn, we know that it must be the first
 631    and last insn referencing DEST.  */
 632
 633 static rtx *
 634 find_single_use (rtx dest, rtx insn, rtx *ploc)
 635 {
 636   basic_block bb;
 637   rtx next;
 638   rtx *result;
 639   struct insn_link *link;
 640
 641 #ifdef HAVE_cc0
 642   if (dest == cc0_rtx)
 643     {
 644       next = NEXT_INSN (insn);
 645       if (next == 0
 646           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 647         return 0;
 648
 649       result = find_single_use_1 (dest, &PATTERN (next));
 650       if (result && ploc)
 651         *ploc = next;
 652       return result;
 653     }
 654 #endif
 655
 656   if (!REG_P (dest))
 657     return 0;
 658
 659   bb = BLOCK_FOR_INSN (insn);
 660   for (next = NEXT_INSN (insn);
 661        next && BLOCK_FOR_INSN (next) == bb;
 662        next = NEXT_INSN (next))
 663     if (INSN_P (next) && dead_or_set_p (next, dest))
 664       {
 665         FOR_EACH_LOG_LINK (link, next)
 666           if (link->insn == insn)
 667             break;
 668
 669         if (link)
 670           {
 671             result = find_single_use_1 (dest, &PATTERN (next));
 672             if (ploc)
 673               *ploc = next;
 674             return result;
 675           }
 676       }
 677
 678   return 0;
 679 }
 680 \f
 681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 682    insn.  The substitution can be undone by undo_all.  If INTO is already
 683    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 684    also call SUBST, we have to compute it before we put anything into
 685    the undo table.  */
 686
 687 static void
 688 do_SUBST (rtx *into, rtx newval)
 689 {
 690   struct undo *buf;
 691   rtx oldval = *into;
 692
 693   if (oldval == newval)
 694     return;
 695
 696   /* We'd like to catch as many invalid transformations here as
 697      possible.  Unfortunately, there are way too many mode changes
 698      that are perfectly valid, so we'd waste too much effort for
 699      little gain doing the checks here.  Focus on catching invalid
 700      transformations involving integer constants.  */
 701   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 702       && CONST_INT_P (newval))
 703     {
 704       /* Sanity check that we're replacing oldval with a CONST_INT
 705          that is a valid sign-extension for the original mode.  */
 706       gcc_assert (INTVAL (newval)
 707                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 708
 709       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 710          CONST_INT is not valid, because after the replacement, the
 711          original mode would be gone.  Unfortunately, we can't tell
 712          when do_SUBST is called to replace the operand thereof, so we
 713          perform this test on oldval instead, checking whether an
 714          invalid replacement took place before we got here.  */
 715       gcc_assert (!(GET_CODE (oldval) == SUBREG
 716                     && CONST_INT_P (SUBREG_REG (oldval))));
 717       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 718                     && CONST_INT_P (XEXP (oldval, 0))));
 719     }
 720
 721   if (undobuf.frees)
 722     buf = undobuf.frees, undobuf.frees = buf->next;
 723   else
 724     buf = XNEW (struct undo);
 725
 726   buf->kind = UNDO_RTX;
 727   buf->where.r = into;
 728   buf->old_contents.r = oldval;
 729   *into = newval;
 730
 731   buf->next = undobuf.undos, undobuf.undos = buf;
 732 }
 733
 734 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 735
 736 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 737    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 738    not safe.  */
 739
 740 static void
 741 do_SUBST_INT (int *into, int newval)
 742 {
 743   struct undo *buf;
 744   int oldval = *into;
 745
 746   if (oldval == newval)
 747     return;
 748
 749   if (undobuf.frees)
 750     buf = undobuf.frees, undobuf.frees = buf->next;
 751   else
 752     buf = XNEW (struct undo);
 753
 754   buf->kind = UNDO_INT;
 755   buf->where.i = into;
 756   buf->old_contents.i = oldval;
 757   *into = newval;
 758
 759   buf->next = undobuf.undos, undobuf.undos = buf;
 760 }
 761
 762 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 763
 764 /* Similar to SUBST, but just substitute the mode.  This is used when
 765    changing the mode of a pseudo-register, so that any other
 766    references to the entry in the regno_reg_rtx array will change as
 767    well.  */
 768
 769 static void
 770 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 771 {
 772   struct undo *buf;
 773   enum machine_mode oldval = GET_MODE (*into);
 774
 775   if (oldval == newval)
 776     return;
 777
 778   if (undobuf.frees)
 779     buf = undobuf.frees, undobuf.frees = buf->next;
 780   else
 781     buf = XNEW (struct undo);
 782
 783   buf->kind = UNDO_MODE;
 784   buf->where.r = into;
 785   buf->old_contents.m = oldval;
 786   adjust_reg_mode (*into, newval);
 787
 788   buf->next = undobuf.undos, undobuf.undos = buf;
 789 }
 790
 791 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 792
 793 #ifndef HAVE_cc0
 794 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 795
 796 static void
 797 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 798 {
 799   struct undo *buf;
 800   struct insn_link * oldval = *into;
 801
 802   if (oldval == newval)
 803     return;
 804
 805   if (undobuf.frees)
 806     buf = undobuf.frees, undobuf.frees = buf->next;
 807   else
 808     buf = XNEW (struct undo);
 809
 810   buf->kind = UNDO_LINKS;
 811   buf->where.l = into;
 812   buf->old_contents.l = oldval;
 813   *into = newval;
 814
 815   buf->next = undobuf.undos, undobuf.undos = buf;
 816 }
 817
 818 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 819 #endif
 820 \f
 821 /* Subroutine of try_combine.  Determine whether the replacement patterns
 822    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 823    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 824    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 825    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 826    of all the instructions can be estimated and the replacements are more
 827    expensive than the original sequence.  */
 828
 829 static bool
 830 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 831                        rtx newi2pat, rtx newotherpat)
 832 {
 833   int i0_cost, i1_cost, i2_cost, i3_cost;
 834   int new_i2_cost, new_i3_cost;
 835   int old_cost, new_cost;
 836
 837   /* Lookup the original insn_rtx_costs.  */
 838   i2_cost = INSN_COST (i2);
 839   i3_cost = INSN_COST (i3);
 840
 841   if (i1)
 842     {
 843       i1_cost = INSN_COST (i1);
 844       if (i0)
 845         {
 846           i0_cost = INSN_COST (i0);
 847           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 848                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 849         }
 850       else
 851         {
 852           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 853                       ? i1_cost + i2_cost + i3_cost : 0);
 854           i0_cost = 0;
 855         }
 856     }
 857   else
 858     {
 859       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 860       i1_cost = i0_cost = 0;
 861     }
 862
 863   /* Calculate the replacement insn_rtx_costs.  */
 864   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 865   if (newi2pat)
 866     {
 867       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 868       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 869                  ? new_i2_cost + new_i3_cost : 0;
 870     }
 871   else
 872     {
 873       new_cost = new_i3_cost;
 874       new_i2_cost = 0;
 875     }
 876
 877   if (undobuf.other_insn)
 878     {
 879       int old_other_cost, new_other_cost;
 880
 881       old_other_cost = INSN_COST (undobuf.other_insn);
 882       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 883       if (old_other_cost > 0 && new_other_cost > 0)
 884         {
 885           old_cost += old_other_cost;
 886           new_cost += new_other_cost;
 887         }
 888       else
 889         old_cost = 0;
 890     }
 891
 892   /* Disallow this combination if both new_cost and old_cost are greater than
 893      zero, and new_cost is greater than old cost.  */
 894   if (old_cost > 0 && new_cost > old_cost)
 895     {
 896       if (dump_file)
 897         {
 898           if (i0)
 899             {
 900               fprintf (dump_file,
 901                        "rejecting combination of insns %d, %d, %d and %d\n",
 902                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 903                        INSN_UID (i3));
 904               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 905                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 906             }
 907           else if (i1)
 908             {
 909               fprintf (dump_file,
 910                        "rejecting combination of insns %d, %d and %d\n",
 911                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 912               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 913                        i1_cost, i2_cost, i3_cost, old_cost);
 914             }
 915           else
 916             {
 917               fprintf (dump_file,
 918                        "rejecting combination of insns %d and %d\n",
 919                        INSN_UID (i2), INSN_UID (i3));
 920               fprintf (dump_file, "original costs %d + %d = %d\n",
 921                        i2_cost, i3_cost, old_cost);
 922             }
 923
 924           if (newi2pat)
 925             {
 926               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 927                        new_i2_cost, new_i3_cost, new_cost);
 928             }
 929           else
 930             fprintf (dump_file, "replacement cost %d\n", new_cost);
 931         }
 932
 933       return false;
 934     }
 935
 936   /* Update the uid_insn_cost array with the replacement costs.  */
 937   INSN_COST (i2) = new_i2_cost;
 938   INSN_COST (i3) = new_i3_cost;
 939   if (i1)
 940     {
 941       INSN_COST (i1) = 0;
 942       if (i0)
 943         INSN_COST (i0) = 0;
 944     }
 945
 946   return true;
 947 }
 948
 949
 950 /* Delete any insns that copy a register to itself.  */
 951
 952 static void
 953 delete_noop_moves (void)
 954 {
 955   rtx insn, next;
 956   basic_block bb;
 957
 958   FOR_EACH_BB (bb)
 959     {
 960       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 961         {
 962           next = NEXT_INSN (insn);
 963           if (INSN_P (insn) && noop_move_p (insn))
 964             {
 965               if (dump_file)
 966                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 967
 968               delete_insn_and_edges (insn);
 969             }
 970         }
 971     }
 972 }
 973
 974 \f
 975 /* Fill in log links field for all insns.  */
 976
 977 static void
 978 create_log_links (void)
 979 {
 980   basic_block bb;
 981   rtx *next_use, insn;
 982   df_ref *def_vec, *use_vec;
 983
 984   next_use = XCNEWVEC (rtx, max_reg_num ());
 985
 986   /* Pass through each block from the end, recording the uses of each
 987      register and establishing log links when def is encountered.
 988      Note that we do not clear next_use array in order to save time,
 989      so we have to test whether the use is in the same basic block as def.
 990
 991      There are a few cases below when we do not consider the definition or
 992      usage -- these are taken from original flow.c did. Don't ask me why it is
 993      done this way; I don't know and if it works, I don't want to know.  */
 994
 995   FOR_EACH_BB (bb)
 996     {
 997       FOR_BB_INSNS_REVERSE (bb, insn)
 998         {
 999           if (!NONDEBUG_INSN_P (insn))
1000             continue;
1001
1002           /* Log links are created only once.  */
1003           gcc_assert (!LOG_LINKS (insn));
1004
1005           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1006             {
1007               df_ref def = *def_vec;
1008               int regno = DF_REF_REGNO (def);
1009               rtx use_insn;
1010
1011               if (!next_use[regno])
1012                 continue;
1013
1014               /* Do not consider if it is pre/post modification in MEM.  */
1015               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1016                 continue;
1017
1018               /* Do not make the log link for frame pointer.  */
1019               if ((regno == FRAME_POINTER_REGNUM
1020                    && (! reload_completed || frame_pointer_needed))
1021 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1022                   || (regno == HARD_FRAME_POINTER_REGNUM
1023                       && (! reload_completed || frame_pointer_needed))
1024 #endif
1025 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1026                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1027 #endif
1028                   )
1029                 continue;
1030
1031               use_insn = next_use[regno];
1032               if (BLOCK_FOR_INSN (use_insn) == bb)
1033                 {
1034                   /* flow.c claimed:
1035
1036                      We don't build a LOG_LINK for hard registers contained
1037                      in ASM_OPERANDs.  If these registers get replaced,
1038                      we might wind up changing the semantics of the insn,
1039                      even if reload can make what appear to be valid
1040                      assignments later.  */
1041                   if (regno >= FIRST_PSEUDO_REGISTER
1042                       || asm_noperands (PATTERN (use_insn)) < 0)
1043                     {
1044                       /* Don't add duplicate links between instructions.  */
1045                       struct insn_link *links;
1046                       FOR_EACH_LOG_LINK (links, use_insn)
1047                         if (insn == links->insn)
1048                           break;
1049
1050                       if (!links)
1051                         LOG_LINKS (use_insn)
1052                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1053                     }
1054                 }
1055               next_use[regno] = NULL_RTX;
1056             }
1057
1058           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1059             {
1060               df_ref use = *use_vec;
1061               int regno = DF_REF_REGNO (use);
1062
1063               /* Do not consider the usage of the stack pointer
1064                  by function call.  */
1065               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1066                 continue;
1067
1068               next_use[regno] = insn;
1069             }
1070         }
1071     }
1072
1073   free (next_use);
1074 }
1075
1076 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1077    true if we found a LOG_LINK that proves that A feeds B.  This only works
1078    if there are no instructions between A and B which could have a link
1079    depending on A, since in that case we would not record a link for B.
1080    We also check the implicit dependency created by a cc0 setter/user
1081    pair.  */
1082
1083 static bool
1084 insn_a_feeds_b (rtx a, rtx b)
1085 {
1086   struct insn_link *links;
1087   FOR_EACH_LOG_LINK (links, b)
1088     if (links->insn == a)
1089       return true;
1090 #ifdef HAVE_cc0
1091   if (sets_cc0_p (a))
1092     return true;
1093 #endif
1094   return false;
1095 }
1096 \f
1097 /* Main entry point for combiner.  F is the first insn of the function.
1098    NREGS is the first unused pseudo-reg number.
1099
1100    Return nonzero if the combiner has turned an indirect jump
1101    instruction into a direct jump.  */
1102 static int
1103 combine_instructions (rtx f, unsigned int nregs)
1104 {
1105   rtx insn, next;
1106 #ifdef HAVE_cc0
1107   rtx prev;
1108 #endif
1109   struct insn_link *links, *nextlinks;
1110   rtx first;
1111   basic_block last_bb;
1112
1113   int new_direct_jump_p = 0;
1114
1115   for (first = f; first && !INSN_P (first); )
1116     first = NEXT_INSN (first);
1117   if (!first)
1118     return 0;
1119
1120   combine_attempts = 0;
1121   combine_merges = 0;
1122   combine_extras = 0;
1123   combine_successes = 0;
1124
1125   rtl_hooks = combine_rtl_hooks;
1126
1127   VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1128
1129   init_recog_no_volatile ();
1130
1131   /* Allocate array for insn info.  */
1132   max_uid_known = get_max_uid ();
1133   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1134   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1135   gcc_obstack_init (&insn_link_obstack);
1136
1137   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1138
1139   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1140      problems when, for example, we have j <<= 1 in a loop.  */
1141
1142   nonzero_sign_valid = 0;
1143   label_tick = label_tick_ebb_start = 1;
1144
1145   /* Scan all SETs and see if we can deduce anything about what
1146      bits are known to be zero for some registers and how many copies
1147      of the sign bit are known to exist for those registers.
1148
1149      Also set any known values so that we can use it while searching
1150      for what bits are known to be set.  */
1151
1152   setup_incoming_promotions (first);
1153   /* Allow the entry block and the first block to fall into the same EBB.
1154      Conceptually the incoming promotions are assigned to the entry block.  */
1155   last_bb = ENTRY_BLOCK_PTR;
1156
1157   create_log_links ();
1158   FOR_EACH_BB (this_basic_block)
1159     {
1160       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1161       last_call_luid = 0;
1162       mem_last_set = -1;
1163
1164       label_tick++;
1165       if (!single_pred_p (this_basic_block)
1166           || single_pred (this_basic_block) != last_bb)
1167         label_tick_ebb_start = label_tick;
1168       last_bb = this_basic_block;
1169
1170       FOR_BB_INSNS (this_basic_block, insn)
1171         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1172           {
1173 #ifdef AUTO_INC_DEC
1174             rtx links;
1175 #endif
1176
1177             subst_low_luid = DF_INSN_LUID (insn);
1178             subst_insn = insn;
1179
1180             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1181                          insn);
1182             record_dead_and_set_regs (insn);
1183
1184 #ifdef AUTO_INC_DEC
1185             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1186               if (REG_NOTE_KIND (links) == REG_INC)
1187                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1188                                                   insn);
1189 #endif
1190
1191             /* Record the current insn_rtx_cost of this instruction.  */
1192             if (NONJUMP_INSN_P (insn))
1193               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1194                                                 optimize_this_for_speed_p);
1195             if (dump_file)
1196               fprintf(dump_file, "insn_cost %d: %d\n",
1197                     INSN_UID (insn), INSN_COST (insn));
1198           }
1199     }
1200
1201   nonzero_sign_valid = 1;
1202
1203   /* Now scan all the insns in forward order.  */
1204   label_tick = label_tick_ebb_start = 1;
1205   init_reg_last ();
1206   setup_incoming_promotions (first);
1207   last_bb = ENTRY_BLOCK_PTR;
1208
1209   FOR_EACH_BB (this_basic_block)
1210     {
1211       rtx last_combined_insn = NULL_RTX;
1212       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1213       last_call_luid = 0;
1214       mem_last_set = -1;
1215
1216       label_tick++;
1217       if (!single_pred_p (this_basic_block)
1218           || single_pred (this_basic_block) != last_bb)
1219         label_tick_ebb_start = label_tick;
1220       last_bb = this_basic_block;
1221
1222       rtl_profile_for_bb (this_basic_block);
1223       for (insn = BB_HEAD (this_basic_block);
1224            insn != NEXT_INSN (BB_END (this_basic_block));
1225            insn = next ? next : NEXT_INSN (insn))
1226         {
1227           next = 0;
1228           if (NONDEBUG_INSN_P (insn))
1229             {
1230               while (last_combined_insn
1231                      && INSN_DELETED_P (last_combined_insn))
1232                 last_combined_insn = PREV_INSN (last_combined_insn);
1233               if (last_combined_insn == NULL_RTX
1234                   || BARRIER_P (last_combined_insn)
1235                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1236                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1237                 last_combined_insn = insn;
1238
1239               /* See if we know about function return values before this
1240                  insn based upon SUBREG flags.  */
1241               check_promoted_subreg (insn, PATTERN (insn));
1242
1243               /* See if we can find hardregs and subreg of pseudos in
1244                  narrower modes.  This could help turning TRUNCATEs
1245                  into SUBREGs.  */
1246               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1247
1248               /* Try this insn with each insn it links back to.  */
1249
1250               FOR_EACH_LOG_LINK (links, insn)
1251                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1252                                          NULL_RTX, &new_direct_jump_p,
1253                                          last_combined_insn)) != 0)
1254                   goto retry;
1255
1256               /* Try each sequence of three linked insns ending with this one.  */
1257
1258               FOR_EACH_LOG_LINK (links, insn)
1259                 {
1260                   rtx link = links->insn;
1261
1262                   /* If the linked insn has been replaced by a note, then there
1263                      is no point in pursuing this chain any further.  */
1264                   if (NOTE_P (link))
1265                     continue;
1266
1267                   FOR_EACH_LOG_LINK (nextlinks, link)
1268                     if ((next = try_combine (insn, link, nextlinks->insn,
1269                                              NULL_RTX, &new_direct_jump_p,
1270                                              last_combined_insn)) != 0)
1271                       goto retry;
1272                 }
1273
1274 #ifdef HAVE_cc0
1275               /* Try to combine a jump insn that uses CC0
1276                  with a preceding insn that sets CC0, and maybe with its
1277                  logical predecessor as well.
1278                  This is how we make decrement-and-branch insns.
1279                  We need this special code because data flow connections
1280                  via CC0 do not get entered in LOG_LINKS.  */
1281
1282               if (JUMP_P (insn)
1283                   && (prev = prev_nonnote_insn (insn)) != 0
1284                   && NONJUMP_INSN_P (prev)
1285                   && sets_cc0_p (PATTERN (prev)))
1286                 {
1287                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1288                                            &new_direct_jump_p,
1289                                            last_combined_insn)) != 0)
1290                     goto retry;
1291
1292                   FOR_EACH_LOG_LINK (nextlinks, prev)
1293                     if ((next = try_combine (insn, prev, nextlinks->insn,
1294                                              NULL_RTX, &new_direct_jump_p,
1295                                              last_combined_insn)) != 0)
1296                       goto retry;
1297                 }
1298
1299               /* Do the same for an insn that explicitly references CC0.  */
1300               if (NONJUMP_INSN_P (insn)
1301                   && (prev = prev_nonnote_insn (insn)) != 0
1302                   && NONJUMP_INSN_P (prev)
1303                   && sets_cc0_p (PATTERN (prev))
1304                   && GET_CODE (PATTERN (insn)) == SET
1305                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1306                 {
1307                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1308                                            &new_direct_jump_p,
1309                                            last_combined_insn)) != 0)
1310                     goto retry;
1311
1312                   FOR_EACH_LOG_LINK (nextlinks, prev)
1313                     if ((next = try_combine (insn, prev, nextlinks->insn,
1314                                              NULL_RTX, &new_direct_jump_p,
1315                                              last_combined_insn)) != 0)
1316                       goto retry;
1317                 }
1318
1319               /* Finally, see if any of the insns that this insn links to
1320                  explicitly references CC0.  If so, try this insn, that insn,
1321                  and its predecessor if it sets CC0.  */
1322               FOR_EACH_LOG_LINK (links, insn)
1323                 if (NONJUMP_INSN_P (links->insn)
1324                     && GET_CODE (PATTERN (links->insn)) == SET
1325                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1326                     && (prev = prev_nonnote_insn (links->insn)) != 0
1327                     && NONJUMP_INSN_P (prev)
1328                     && sets_cc0_p (PATTERN (prev))
1329                     && (next = try_combine (insn, links->insn,
1330                                             prev, NULL_RTX, &new_direct_jump_p,
1331                                             last_combined_insn)) != 0)
1332                   goto retry;
1333 #endif
1334
1335               /* Try combining an insn with two different insns whose results it
1336                  uses.  */
1337               FOR_EACH_LOG_LINK (links, insn)
1338                 for (nextlinks = links->next; nextlinks;
1339                      nextlinks = nextlinks->next)
1340                   if ((next = try_combine (insn, links->insn,
1341                                            nextlinks->insn, NULL_RTX,
1342                                            &new_direct_jump_p,
1343                                            last_combined_insn)) != 0)
1344                     goto retry;
1345
1346               /* Try four-instruction combinations.  */
1347               FOR_EACH_LOG_LINK (links, insn)
1348                 {
1349                   struct insn_link *next1;
1350                   rtx link = links->insn;
1351
1352                   /* If the linked insn has been replaced by a note, then there
1353                      is no point in pursuing this chain any further.  */
1354                   if (NOTE_P (link))
1355                     continue;
1356
1357                   FOR_EACH_LOG_LINK (next1, link)
1358                     {
1359                       rtx link1 = next1->insn;
1360                       if (NOTE_P (link1))
1361                         continue;
1362                       /* I0 -> I1 -> I2 -> I3.  */
1363                       FOR_EACH_LOG_LINK (nextlinks, link1)
1364                         if ((next = try_combine (insn, link, link1,
1365                                                  nextlinks->insn,
1366                                                  &new_direct_jump_p,
1367                                                  last_combined_insn)) != 0)
1368                           goto retry;
1369                       /* I0, I1 -> I2, I2 -> I3.  */
1370                       for (nextlinks = next1->next; nextlinks;
1371                            nextlinks = nextlinks->next)
1372                         if ((next = try_combine (insn, link, link1,
1373                                                  nextlinks->insn,
1374                                                  &new_direct_jump_p,
1375                                                  last_combined_insn)) != 0)
1376                           goto retry;
1377                     }
1378
1379                   for (next1 = links->next; next1; next1 = next1->next)
1380                     {
1381                       rtx link1 = next1->insn;
1382                       if (NOTE_P (link1))
1383                         continue;
1384                       /* I0 -> I2; I1, I2 -> I3.  */
1385                       FOR_EACH_LOG_LINK (nextlinks, link)
1386                         if ((next = try_combine (insn, link, link1,
1387                                                  nextlinks->insn,
1388                                                  &new_direct_jump_p,
1389                                                  last_combined_insn)) != 0)
1390                           goto retry;
1391                       /* I0 -> I1; I1, I2 -> I3.  */
1392                       FOR_EACH_LOG_LINK (nextlinks, link1)
1393                         if ((next = try_combine (insn, link, link1,
1394                                                  nextlinks->insn,
1395                                                  &new_direct_jump_p,
1396                                                  last_combined_insn)) != 0)
1397                           goto retry;
1398                     }
1399                 }
1400
1401               /* Try this insn with each REG_EQUAL note it links back to.  */
1402               FOR_EACH_LOG_LINK (links, insn)
1403                 {
1404                   rtx set, note;
1405                   rtx temp = links->insn;
1406                   if ((set = single_set (temp)) != 0
1407                       && (note = find_reg_equal_equiv_note (temp)) != 0
1408                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1409                       /* Avoid using a register that may already been marked
1410                          dead by an earlier instruction.  */
1411                       && ! unmentioned_reg_p (note, SET_SRC (set))
1412                       && (GET_MODE (note) == VOIDmode
1413                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1414                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1415                     {
1416                       /* Temporarily replace the set's source with the
1417                          contents of the REG_EQUAL note.  The insn will
1418                          be deleted or recognized by try_combine.  */
1419                       rtx orig = SET_SRC (set);
1420                       SET_SRC (set) = note;
1421                       i2mod = temp;
1422                       i2mod_old_rhs = copy_rtx (orig);
1423                       i2mod_new_rhs = copy_rtx (note);
1424                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1425                                           &new_direct_jump_p,
1426                                           last_combined_insn);
1427                       i2mod = NULL_RTX;
1428                       if (next)
1429                         goto retry;
1430                       SET_SRC (set) = orig;
1431                     }
1432                 }
1433
1434               if (!NOTE_P (insn))
1435                 record_dead_and_set_regs (insn);
1436
1437             retry:
1438               ;
1439             }
1440         }
1441     }
1442
1443   default_rtl_profile ();
1444   clear_bb_flags ();
1445   new_direct_jump_p |= purge_all_dead_edges ();
1446   delete_noop_moves ();
1447
1448   /* Clean up.  */
1449   obstack_free (&insn_link_obstack, NULL);
1450   free (uid_log_links);
1451   free (uid_insn_cost);
1452   VEC_free (reg_stat_type, heap, reg_stat);
1453
1454   {
1455     struct undo *undo, *next;
1456     for (undo = undobuf.frees; undo; undo = next)
1457       {
1458         next = undo->next;
1459         free (undo);
1460       }
1461     undobuf.frees = 0;
1462   }
1463
1464   total_attempts += combine_attempts;
1465   total_merges += combine_merges;
1466   total_extras += combine_extras;
1467   total_successes += combine_successes;
1468
1469   nonzero_sign_valid = 0;
1470   rtl_hooks = general_rtl_hooks;
1471
1472   /* Make recognizer allow volatile MEMs again.  */
1473   init_recog ();
1474
1475   return new_direct_jump_p;
1476 }
1477
1478 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1479
1480 static void
1481 init_reg_last (void)
1482 {
1483   unsigned int i;
1484   reg_stat_type *p;
1485
1486   FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1487     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1488 }
1489 \f
1490 /* Set up any promoted values for incoming argument registers.  */
1491
1492 static void
1493 setup_incoming_promotions (rtx first)
1494 {
1495   tree arg;
1496   bool strictly_local = false;
1497
1498   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499        arg = DECL_CHAIN (arg))
1500     {
1501       rtx x, reg = DECL_INCOMING_RTL (arg);
1502       int uns1, uns3;
1503       enum machine_mode mode1, mode2, mode3, mode4;
1504
1505       /* Only continue if the incoming argument is in a register.  */
1506       if (!REG_P (reg))
1507         continue;
1508
1509       /* Determine, if possible, whether all call sites of the current
1510          function lie within the current compilation unit.  (This does
1511          take into account the exporting of a function via taking its
1512          address, and so forth.)  */
1513       strictly_local = cgraph_local_info (current_function_decl)->local;
1514
1515       /* The mode and signedness of the argument before any promotions happen
1516          (equal to the mode of the pseudo holding it at that stage).  */
1517       mode1 = TYPE_MODE (TREE_TYPE (arg));
1518       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1519
1520       /* The mode and signedness of the argument after any source language and
1521          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1522       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1523       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1524
1525       /* The mode and signedness of the argument as it is actually passed,
1526          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1527       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1528                                      TREE_TYPE (cfun->decl), 0);
1529
1530       /* The mode of the register in which the argument is being passed.  */
1531       mode4 = GET_MODE (reg);
1532
1533       /* Eliminate sign extensions in the callee when:
1534          (a) A mode promotion has occurred;  */
1535       if (mode1 == mode3)
1536         continue;
1537       /* (b) The mode of the register is the same as the mode of
1538              the argument as it is passed; */
1539       if (mode3 != mode4)
1540         continue;
1541       /* (c) There's no language level extension;  */
1542       if (mode1 == mode2)
1543         ;
1544       /* (c.1) All callers are from the current compilation unit.  If that's
1545          the case we don't have to rely on an ABI, we only have to know
1546          what we're generating right now, and we know that we will do the
1547          mode1 to mode2 promotion with the given sign.  */
1548       else if (!strictly_local)
1549         continue;
1550       /* (c.2) The combination of the two promotions is useful.  This is
1551          true when the signs match, or if the first promotion is unsigned.
1552          In the later case, (sign_extend (zero_extend x)) is the same as
1553          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1554       else if (uns1)
1555         uns3 = true;
1556       else if (uns3)
1557         continue;
1558
1559       /* Record that the value was promoted from mode1 to mode3,
1560          so that any sign extension at the head of the current
1561          function may be eliminated.  */
1562       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1563       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1564       record_value_for_reg (reg, first, x);
1565     }
1566 }
1567
1568 /* Called via note_stores.  If X is a pseudo that is narrower than
1569    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1570
1571    If we are setting only a portion of X and we can't figure out what
1572    portion, assume all bits will be used since we don't know what will
1573    be happening.
1574
1575    Similarly, set how many bits of X are known to be copies of the sign bit
1576    at all locations in the function.  This is the smallest number implied
1577    by any set of X.  */
1578
1579 static void
1580 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1581 {
1582   rtx insn = (rtx) data;
1583   unsigned int num;
1584
1585   if (REG_P (x)
1586       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1587       /* If this register is undefined at the start of the file, we can't
1588          say what its contents were.  */
1589       && ! REGNO_REG_SET_P
1590            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1591       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1592     {
1593       reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1594
1595       if (set == 0 || GET_CODE (set) == CLOBBER)
1596         {
1597           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1598           rsp->sign_bit_copies = 1;
1599           return;
1600         }
1601
1602       /* If this register is being initialized using itself, and the
1603          register is uninitialized in this basic block, and there are
1604          no LOG_LINKS which set the register, then part of the
1605          register is uninitialized.  In that case we can't assume
1606          anything about the number of nonzero bits.
1607
1608          ??? We could do better if we checked this in
1609          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1610          could avoid making assumptions about the insn which initially
1611          sets the register, while still using the information in other
1612          insns.  We would have to be careful to check every insn
1613          involved in the combination.  */
1614
1615       if (insn
1616           && reg_referenced_p (x, PATTERN (insn))
1617           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1618                                REGNO (x)))
1619         {
1620           struct insn_link *link;
1621
1622           FOR_EACH_LOG_LINK (link, insn)
1623             if (dead_or_set_p (link->insn, x))
1624               break;
1625           if (!link)
1626             {
1627               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1628               rsp->sign_bit_copies = 1;
1629               return;
1630             }
1631         }
1632
1633       /* If this is a complex assignment, see if we can convert it into a
1634          simple assignment.  */
1635       set = expand_field_assignment (set);
1636
1637       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1638          set what we know about X.  */
1639
1640       if (SET_DEST (set) == x
1641           || (paradoxical_subreg_p (SET_DEST (set))
1642               && SUBREG_REG (SET_DEST (set)) == x))
1643         {
1644           rtx src = SET_SRC (set);
1645
1646 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1647           /* If X is narrower than a word and SRC is a non-negative
1648              constant that would appear negative in the mode of X,
1649              sign-extend it for use in reg_stat[].nonzero_bits because some
1650              machines (maybe most) will actually do the sign-extension
1651              and this is the conservative approach.
1652
1653              ??? For 2.5, try to tighten up the MD files in this regard
1654              instead of this kludge.  */
1655
1656           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1657               && CONST_INT_P (src)
1658               && INTVAL (src) > 0
1659               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1660             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1661 #endif
1662
1663           /* Don't call nonzero_bits if it cannot change anything.  */
1664           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1665             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1666           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1667           if (rsp->sign_bit_copies == 0
1668               || rsp->sign_bit_copies > num)
1669             rsp->sign_bit_copies = num;
1670         }
1671       else
1672         {
1673           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1674           rsp->sign_bit_copies = 1;
1675         }
1676     }
1677 }
1678 \f
1679 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1680    optionally insns that were previously combined into I3 or that will be
1681    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1682    INSN, SUCC, SUCC2, I3.
1683
1684    Return 0 if the combination is not allowed for any reason.
1685
1686    If the combination is allowed, *PDEST will be set to the single
1687    destination of INSN and *PSRC to the single source, and this function
1688    will return 1.  */
1689
1690 static int
1691 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1692                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1693                rtx *pdest, rtx *psrc)
1694 {
1695   int i;
1696   const_rtx set = 0;
1697   rtx src, dest;
1698   rtx p;
1699 #ifdef AUTO_INC_DEC
1700   rtx link;
1701 #endif
1702   bool all_adjacent = true;
1703   int (*is_volatile_p) (const_rtx);
1704
1705   if (succ)
1706     {
1707       if (succ2)
1708         {
1709           if (next_active_insn (succ2) != i3)
1710             all_adjacent = false;
1711           if (next_active_insn (succ) != succ2)
1712             all_adjacent = false;
1713         }
1714       else if (next_active_insn (succ) != i3)
1715         all_adjacent = false;
1716       if (next_active_insn (insn) != succ)
1717         all_adjacent = false;
1718     }
1719   else if (next_active_insn (insn) != i3)
1720     all_adjacent = false;
1721
1722   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1723      or a PARALLEL consisting of such a SET and CLOBBERs.
1724
1725      If INSN has CLOBBER parallel parts, ignore them for our processing.
1726      By definition, these happen during the execution of the insn.  When it
1727      is merged with another insn, all bets are off.  If they are, in fact,
1728      needed and aren't also supplied in I3, they may be added by
1729      recog_for_combine.  Otherwise, it won't match.
1730
1731      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1732      note.
1733
1734      Get the source and destination of INSN.  If more than one, can't
1735      combine.  */
1736
1737   if (GET_CODE (PATTERN (insn)) == SET)
1738     set = PATTERN (insn);
1739   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1740            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1741     {
1742       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1743         {
1744           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1745
1746           switch (GET_CODE (elt))
1747             {
1748             /* This is important to combine floating point insns
1749                for the SH4 port.  */
1750             case USE:
1751               /* Combining an isolated USE doesn't make sense.
1752                  We depend here on combinable_i3pat to reject them.  */
1753               /* The code below this loop only verifies that the inputs of
1754                  the SET in INSN do not change.  We call reg_set_between_p
1755                  to verify that the REG in the USE does not change between
1756                  I3 and INSN.
1757                  If the USE in INSN was for a pseudo register, the matching
1758                  insn pattern will likely match any register; combining this
1759                  with any other USE would only be safe if we knew that the
1760                  used registers have identical values, or if there was
1761                  something to tell them apart, e.g. different modes.  For
1762                  now, we forgo such complicated tests and simply disallow
1763                  combining of USES of pseudo registers with any other USE.  */
1764               if (REG_P (XEXP (elt, 0))
1765                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1766                 {
1767                   rtx i3pat = PATTERN (i3);
1768                   int i = XVECLEN (i3pat, 0) - 1;
1769                   unsigned int regno = REGNO (XEXP (elt, 0));
1770
1771                   do
1772                     {
1773                       rtx i3elt = XVECEXP (i3pat, 0, i);
1774
1775                       if (GET_CODE (i3elt) == USE
1776                           && REG_P (XEXP (i3elt, 0))
1777                           && (REGNO (XEXP (i3elt, 0)) == regno
1778                               ? reg_set_between_p (XEXP (elt, 0),
1779                                                    PREV_INSN (insn), i3)
1780                               : regno >= FIRST_PSEUDO_REGISTER))
1781                         return 0;
1782                     }
1783                   while (--i >= 0);
1784                 }
1785               break;
1786
1787               /* We can ignore CLOBBERs.  */
1788             case CLOBBER:
1789               break;
1790
1791             case SET:
1792               /* Ignore SETs whose result isn't used but not those that
1793                  have side-effects.  */
1794               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1795                   && insn_nothrow_p (insn)
1796                   && !side_effects_p (elt))
1797                 break;
1798
1799               /* If we have already found a SET, this is a second one and
1800                  so we cannot combine with this insn.  */
1801               if (set)
1802                 return 0;
1803
1804               set = elt;
1805               break;
1806
1807             default:
1808               /* Anything else means we can't combine.  */
1809               return 0;
1810             }
1811         }
1812
1813       if (set == 0
1814           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1815              so don't do anything with it.  */
1816           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1817         return 0;
1818     }
1819   else
1820     return 0;
1821
1822   if (set == 0)
1823     return 0;
1824
1825   set = expand_field_assignment (set);
1826   src = SET_SRC (set), dest = SET_DEST (set);
1827
1828   /* Don't eliminate a store in the stack pointer.  */
1829   if (dest == stack_pointer_rtx
1830       /* Don't combine with an insn that sets a register to itself if it has
1831          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1832       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1833       /* Can't merge an ASM_OPERANDS.  */
1834       || GET_CODE (src) == ASM_OPERANDS
1835       /* Can't merge a function call.  */
1836       || GET_CODE (src) == CALL
1837       /* Don't eliminate a function call argument.  */
1838       || (CALL_P (i3)
1839           && (find_reg_fusage (i3, USE, dest)
1840               || (REG_P (dest)
1841                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1842                   && global_regs[REGNO (dest)])))
1843       /* Don't substitute into an incremented register.  */
1844       || FIND_REG_INC_NOTE (i3, dest)
1845       || (succ && FIND_REG_INC_NOTE (succ, dest))
1846       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1847       /* Don't substitute into a non-local goto, this confuses CFG.  */
1848       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1849       /* Make sure that DEST is not used after SUCC but before I3.  */
1850       || (!all_adjacent
1851           && ((succ2
1852                && (reg_used_between_p (dest, succ2, i3)
1853                    || reg_used_between_p (dest, succ, succ2)))
1854               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1855       /* Make sure that the value that is to be substituted for the register
1856          does not use any registers whose values alter in between.  However,
1857          If the insns are adjacent, a use can't cross a set even though we
1858          think it might (this can happen for a sequence of insns each setting
1859          the same destination; last_set of that register might point to
1860          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1861          equivalent to the memory so the substitution is valid even if there
1862          are intervening stores.  Also, don't move a volatile asm or
1863          UNSPEC_VOLATILE across any other insns.  */
1864       || (! all_adjacent
1865           && (((!MEM_P (src)
1866                 || ! find_reg_note (insn, REG_EQUIV, src))
1867                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1868               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1869               || GET_CODE (src) == UNSPEC_VOLATILE))
1870       /* Don't combine across a CALL_INSN, because that would possibly
1871          change whether the life span of some REGs crosses calls or not,
1872          and it is a pain to update that information.
1873          Exception: if source is a constant, moving it later can't hurt.
1874          Accept that as a special case.  */
1875       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1876     return 0;
1877
1878   /* DEST must either be a REG or CC0.  */
1879   if (REG_P (dest))
1880     {
1881       /* If register alignment is being enforced for multi-word items in all
1882          cases except for parameters, it is possible to have a register copy
1883          insn referencing a hard register that is not allowed to contain the
1884          mode being copied and which would not be valid as an operand of most
1885          insns.  Eliminate this problem by not combining with such an insn.
1886
1887          Also, on some machines we don't want to extend the life of a hard
1888          register.  */
1889
1890       if (REG_P (src)
1891           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1892                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1893               /* Don't extend the life of a hard register unless it is
1894                  user variable (if we have few registers) or it can't
1895                  fit into the desired register (meaning something special
1896                  is going on).
1897                  Also avoid substituting a return register into I3, because
1898                  reload can't handle a conflict with constraints of other
1899                  inputs.  */
1900               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1901                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1902         return 0;
1903     }
1904   else if (GET_CODE (dest) != CC0)
1905     return 0;
1906
1907
1908   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1909     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1910       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1911         {
1912           /* Don't substitute for a register intended as a clobberable
1913              operand.  */
1914           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1915           if (rtx_equal_p (reg, dest))
1916             return 0;
1917
1918           /* If the clobber represents an earlyclobber operand, we must not
1919              substitute an expression containing the clobbered register.
1920              As we do not analyze the constraint strings here, we have to
1921              make the conservative assumption.  However, if the register is
1922              a fixed hard reg, the clobber cannot represent any operand;
1923              we leave it up to the machine description to either accept or
1924              reject use-and-clobber patterns.  */
1925           if (!REG_P (reg)
1926               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1927               || !fixed_regs[REGNO (reg)])
1928             if (reg_overlap_mentioned_p (reg, src))
1929               return 0;
1930         }
1931
1932   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1933      or not), reject, unless nothing volatile comes between it and I3 */
1934
1935   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1936     {
1937       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1938       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1939         return 0;
1940       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1941         return 0;
1942       /* We'll check insns between INSN and I3 below.  */
1943     }
1944
1945   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1946      to be an explicit register variable, and was chosen for a reason.  */
1947
1948   if (GET_CODE (src) == ASM_OPERANDS
1949       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1950     return 0;
1951
1952   /* If INSN contains volatile references (specifically volatile MEMs),
1953      we cannot combine across any other volatile references.
1954      Even if INSN doesn't contain volatile references, any intervening
1955      volatile insn might affect machine state.  */
1956
1957   is_volatile_p = volatile_refs_p (PATTERN (insn))
1958     ? volatile_refs_p
1959     : volatile_insn_p;
1960
1961   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1962     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1963       return 0;
1964
1965   /* If INSN contains an autoincrement or autodecrement, make sure that
1966      register is not used between there and I3, and not already used in
1967      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1968      Also insist that I3 not be a jump; if it were one
1969      and the incremented register were spilled, we would lose.  */
1970
1971 #ifdef AUTO_INC_DEC
1972   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1973     if (REG_NOTE_KIND (link) == REG_INC
1974         && (JUMP_P (i3)
1975             || reg_used_between_p (XEXP (link, 0), insn, i3)
1976             || (pred != NULL_RTX
1977                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1978             || (pred2 != NULL_RTX
1979                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1980             || (succ != NULL_RTX
1981                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1982             || (succ2 != NULL_RTX
1983                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1984             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1985       return 0;
1986 #endif
1987
1988 #ifdef HAVE_cc0
1989   /* Don't combine an insn that follows a CC0-setting insn.
1990      An insn that uses CC0 must not be separated from the one that sets it.
1991      We do, however, allow I2 to follow a CC0-setting insn if that insn
1992      is passed as I1; in that case it will be deleted also.
1993      We also allow combining in this case if all the insns are adjacent
1994      because that would leave the two CC0 insns adjacent as well.
1995      It would be more logical to test whether CC0 occurs inside I1 or I2,
1996      but that would be much slower, and this ought to be equivalent.  */
1997
1998   p = prev_nonnote_insn (insn);
1999   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2000       && ! all_adjacent)
2001     return 0;
2002 #endif
2003
2004   /* If we get here, we have passed all the tests and the combination is
2005      to be allowed.  */
2006
2007   *pdest = dest;
2008   *psrc = src;
2009
2010   return 1;
2011 }
2012 \f
2013 /* LOC is the location within I3 that contains its pattern or the component
2014    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2015
2016    One problem is if I3 modifies its output, as opposed to replacing it
2017    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2018    doing so would produce an insn that is not equivalent to the original insns.
2019
2020    Consider:
2021
2022          (set (reg:DI 101) (reg:DI 100))
2023          (set (subreg:SI (reg:DI 101) 0) <foo>)
2024
2025    This is NOT equivalent to:
2026
2027          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2028                     (set (reg:DI 101) (reg:DI 100))])
2029
2030    Not only does this modify 100 (in which case it might still be valid
2031    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2032
2033    We can also run into a problem if I2 sets a register that I1
2034    uses and I1 gets directly substituted into I3 (not via I2).  In that
2035    case, we would be getting the wrong value of I2DEST into I3, so we
2036    must reject the combination.  This case occurs when I2 and I1 both
2037    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2038    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2039    of a SET must prevent combination from occurring.  The same situation
2040    can occur for I0, in which case I0_NOT_IN_SRC is set.
2041
2042    Before doing the above check, we first try to expand a field assignment
2043    into a set of logical operations.
2044
2045    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2046    we place a register that is both set and used within I3.  If more than one
2047    such register is detected, we fail.
2048
2049    Return 1 if the combination is valid, zero otherwise.  */
2050
2051 static int
2052 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2053                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2054 {
2055   rtx x = *loc;
2056
2057   if (GET_CODE (x) == SET)
2058     {
2059       rtx set = x ;
2060       rtx dest = SET_DEST (set);
2061       rtx src = SET_SRC (set);
2062       rtx inner_dest = dest;
2063       rtx subdest;
2064
2065       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2066              || GET_CODE (inner_dest) == SUBREG
2067              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2068         inner_dest = XEXP (inner_dest, 0);
2069
2070       /* Check for the case where I3 modifies its output, as discussed
2071          above.  We don't want to prevent pseudos from being combined
2072          into the address of a MEM, so only prevent the combination if
2073          i1 or i2 set the same MEM.  */
2074       if ((inner_dest != dest &&
2075            (!MEM_P (inner_dest)
2076             || rtx_equal_p (i2dest, inner_dest)
2077             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2078             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2079            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2080                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2081                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2082
2083           /* This is the same test done in can_combine_p except we can't test
2084              all_adjacent; we don't have to, since this instruction will stay
2085              in place, thus we are not considering increasing the lifetime of
2086              INNER_DEST.
2087
2088              Also, if this insn sets a function argument, combining it with
2089              something that might need a spill could clobber a previous
2090              function argument; the all_adjacent test in can_combine_p also
2091              checks this; here, we do a more specific test for this case.  */
2092
2093           || (REG_P (inner_dest)
2094               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2095               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2096                                         GET_MODE (inner_dest))))
2097           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2098           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2099         return 0;
2100
2101       /* If DEST is used in I3, it is being killed in this insn, so
2102          record that for later.  We have to consider paradoxical
2103          subregs here, since they kill the whole register, but we
2104          ignore partial subregs, STRICT_LOW_PART, etc.
2105          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2106          STACK_POINTER_REGNUM, since these are always considered to be
2107          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2108       subdest = dest;
2109       if (GET_CODE (subdest) == SUBREG
2110           && (GET_MODE_SIZE (GET_MODE (subdest))
2111               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2112         subdest = SUBREG_REG (subdest);
2113       if (pi3dest_killed
2114           && REG_P (subdest)
2115           && reg_referenced_p (subdest, PATTERN (i3))
2116           && REGNO (subdest) != FRAME_POINTER_REGNUM
2117 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2118           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2119 #endif
2120 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2121           && (REGNO (subdest) != ARG_POINTER_REGNUM
2122               || ! fixed_regs [REGNO (subdest)])
2123 #endif
2124           && REGNO (subdest) != STACK_POINTER_REGNUM)
2125         {
2126           if (*pi3dest_killed)
2127             return 0;
2128
2129           *pi3dest_killed = subdest;
2130         }
2131     }
2132
2133   else if (GET_CODE (x) == PARALLEL)
2134     {
2135       int i;
2136
2137       for (i = 0; i < XVECLEN (x, 0); i++)
2138         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2139                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2140           return 0;
2141     }
2142
2143   return 1;
2144 }
2145 \f
2146 /* Return 1 if X is an arithmetic expression that contains a multiplication
2147    and division.  We don't count multiplications by powers of two here.  */
2148
2149 static int
2150 contains_muldiv (rtx x)
2151 {
2152   switch (GET_CODE (x))
2153     {
2154     case MOD:  case DIV:  case UMOD:  case UDIV:
2155       return 1;
2156
2157     case MULT:
2158       return ! (CONST_INT_P (XEXP (x, 1))
2159                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2160     default:
2161       if (BINARY_P (x))
2162         return contains_muldiv (XEXP (x, 0))
2163             || contains_muldiv (XEXP (x, 1));
2164
2165       if (UNARY_P (x))
2166         return contains_muldiv (XEXP (x, 0));
2167
2168       return 0;
2169     }
2170 }
2171 \f
2172 /* Determine whether INSN can be used in a combination.  Return nonzero if
2173    not.  This is used in try_combine to detect early some cases where we
2174    can't perform combinations.  */
2175
2176 static int
2177 cant_combine_insn_p (rtx insn)
2178 {
2179   rtx set;
2180   rtx src, dest;
2181
2182   /* If this isn't really an insn, we can't do anything.
2183      This can occur when flow deletes an insn that it has merged into an
2184      auto-increment address.  */
2185   if (! INSN_P (insn))
2186     return 1;
2187
2188   /* Never combine loads and stores involving hard regs that are likely
2189      to be spilled.  The register allocator can usually handle such
2190      reg-reg moves by tying.  If we allow the combiner to make
2191      substitutions of likely-spilled regs, reload might die.
2192      As an exception, we allow combinations involving fixed regs; these are
2193      not available to the register allocator so there's no risk involved.  */
2194
2195   set = single_set (insn);
2196   if (! set)
2197     return 0;
2198   src = SET_SRC (set);
2199   dest = SET_DEST (set);
2200   if (GET_CODE (src) == SUBREG)
2201     src = SUBREG_REG (src);
2202   if (GET_CODE (dest) == SUBREG)
2203     dest = SUBREG_REG (dest);
2204   if (REG_P (src) && REG_P (dest)
2205       && ((HARD_REGISTER_P (src)
2206            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2207            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2208           || (HARD_REGISTER_P (dest)
2209               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2210               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2211     return 1;
2212
2213   return 0;
2214 }
2215
2216 struct likely_spilled_retval_info
2217 {
2218   unsigned regno, nregs;
2219   unsigned mask;
2220 };
2221
2222 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2223    hard registers that are known to be written to / clobbered in full.  */
2224 static void
2225 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2226 {
2227   struct likely_spilled_retval_info *const info =
2228     (struct likely_spilled_retval_info *) data;
2229   unsigned regno, nregs;
2230   unsigned new_mask;
2231
2232   if (!REG_P (XEXP (set, 0)))
2233     return;
2234   regno = REGNO (x);
2235   if (regno >= info->regno + info->nregs)
2236     return;
2237   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2238   if (regno + nregs <= info->regno)
2239     return;
2240   new_mask = (2U << (nregs - 1)) - 1;
2241   if (regno < info->regno)
2242     new_mask >>= info->regno - regno;
2243   else
2244     new_mask <<= regno - info->regno;
2245   info->mask &= ~new_mask;
2246 }
2247
2248 /* Return nonzero iff part of the return value is live during INSN, and
2249    it is likely spilled.  This can happen when more than one insn is needed
2250    to copy the return value, e.g. when we consider to combine into the
2251    second copy insn for a complex value.  */
2252
2253 static int
2254 likely_spilled_retval_p (rtx insn)
2255 {
2256   rtx use = BB_END (this_basic_block);
2257   rtx reg, p;
2258   unsigned regno, nregs;
2259   /* We assume here that no machine mode needs more than
2260      32 hard registers when the value overlaps with a register
2261      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2262   unsigned mask;
2263   struct likely_spilled_retval_info info;
2264
2265   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2266     return 0;
2267   reg = XEXP (PATTERN (use), 0);
2268   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2269     return 0;
2270   regno = REGNO (reg);
2271   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2272   if (nregs == 1)
2273     return 0;
2274   mask = (2U << (nregs - 1)) - 1;
2275
2276   /* Disregard parts of the return value that are set later.  */
2277   info.regno = regno;
2278   info.nregs = nregs;
2279   info.mask = mask;
2280   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2281     if (INSN_P (p))
2282       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2283   mask = info.mask;
2284
2285   /* Check if any of the (probably) live return value registers is
2286      likely spilled.  */
2287   nregs --;
2288   do
2289     {
2290       if ((mask & 1 << nregs)
2291           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2292         return 1;
2293     } while (nregs--);
2294   return 0;
2295 }
2296
2297 /* Adjust INSN after we made a change to its destination.
2298
2299    Changing the destination can invalidate notes that say something about
2300    the results of the insn and a LOG_LINK pointing to the insn.  */
2301
2302 static void
2303 adjust_for_new_dest (rtx insn)
2304 {
2305   /* For notes, be conservative and simply remove them.  */
2306   remove_reg_equal_equiv_notes (insn);
2307
2308   /* The new insn will have a destination that was previously the destination
2309      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2310      the next use of that destination.  */
2311   distribute_links (alloc_insn_link (insn, NULL));
2312
2313   df_insn_rescan (insn);
2314 }
2315
2316 /* Return TRUE if combine can reuse reg X in mode MODE.
2317    ADDED_SETS is nonzero if the original set is still required.  */
2318 static bool
2319 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2320 {
2321   unsigned int regno;
2322
2323   if (!REG_P(x))
2324     return false;
2325
2326   regno = REGNO (x);
2327   /* Allow hard registers if the new mode is legal, and occupies no more
2328      registers than the old mode.  */
2329   if (regno < FIRST_PSEUDO_REGISTER)
2330     return (HARD_REGNO_MODE_OK (regno, mode)
2331             && (hard_regno_nregs[regno][GET_MODE (x)]
2332                 >= hard_regno_nregs[regno][mode]));
2333
2334   /* Or a pseudo that is only used once.  */
2335   return (REG_N_SETS (regno) == 1 && !added_sets
2336           && !REG_USERVAR_P (x));
2337 }
2338
2339
2340 /* Check whether X, the destination of a set, refers to part of
2341    the register specified by REG.  */
2342
2343 static bool
2344 reg_subword_p (rtx x, rtx reg)
2345 {
2346   /* Check that reg is an integer mode register.  */
2347   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2348     return false;
2349
2350   if (GET_CODE (x) == STRICT_LOW_PART
2351       || GET_CODE (x) == ZERO_EXTRACT)
2352     x = XEXP (x, 0);
2353
2354   return GET_CODE (x) == SUBREG
2355          && SUBREG_REG (x) == reg
2356          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2357 }
2358
2359 #ifdef AUTO_INC_DEC
2360 /* Replace auto-increment addressing modes with explicit operations to access
2361    the same addresses without modifying the corresponding registers.  */
2362
2363 static rtx
2364 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2365 {
2366   rtx x = src;
2367   const RTX_CODE code = GET_CODE (x);
2368   int i;
2369   const char *fmt;
2370
2371   switch (code)
2372     {
2373     case REG:
2374     case CONST_INT:
2375     case CONST_DOUBLE:
2376     case CONST_FIXED:
2377     case CONST_VECTOR:
2378     case SYMBOL_REF:
2379     case CODE_LABEL:
2380     case PC:
2381     case CC0:
2382     case SCRATCH:
2383       /* SCRATCH must be shared because they represent distinct values.  */
2384       return x;
2385     case CLOBBER:
2386       if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2387         return x;
2388       break;
2389
2390     case CONST:
2391       if (shared_const_p (x))
2392         return x;
2393       break;
2394
2395     case MEM:
2396       mem_mode = GET_MODE (x);
2397       break;
2398
2399     case PRE_INC:
2400     case PRE_DEC:
2401       gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2402       return gen_rtx_PLUS (GET_MODE (x),
2403                            cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2404                            GEN_INT (code == PRE_INC
2405                                     ? GET_MODE_SIZE (mem_mode)
2406                                     : -GET_MODE_SIZE (mem_mode)));
2407
2408     case POST_INC:
2409     case POST_DEC:
2410     case PRE_MODIFY:
2411     case POST_MODIFY:
2412       return cleanup_auto_inc_dec (code == PRE_MODIFY
2413                                    ? XEXP (x, 1) : XEXP (x, 0),
2414                                    mem_mode);
2415
2416     default:
2417       break;
2418     }
2419
2420   /* Copy the various flags, fields, and other information.  We assume
2421      that all fields need copying, and then clear the fields that should
2422      not be copied.  That is the sensible default behavior, and forces
2423      us to explicitly document why we are *not* copying a flag.  */
2424   x = shallow_copy_rtx (x);
2425
2426   /* We do not copy the USED flag, which is used as a mark bit during
2427      walks over the RTL.  */
2428   RTX_FLAG (x, used) = 0;
2429
2430   /* We do not copy FRAME_RELATED for INSNs.  */
2431   if (INSN_P (x))
2432     RTX_FLAG (x, frame_related) = 0;
2433
2434   fmt = GET_RTX_FORMAT (code);
2435   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2436     if (fmt[i] == 'e')
2437       XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2438     else if (fmt[i] == 'E' || fmt[i] == 'V')
2439       {
2440         int j;
2441         XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2442         for (j = 0; j < XVECLEN (x, i); j++)
2443           XVECEXP (x, i, j)
2444             = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2445       }
2446
2447   return x;
2448 }
2449 #endif
2450
2451 /* Auxiliary data structure for propagate_for_debug_stmt.  */
2452
2453 struct rtx_subst_pair
2454 {
2455   rtx to;
2456   bool adjusted;
2457 };
2458
2459 /* DATA points to an rtx_subst_pair.  Return the value that should be
2460    substituted.  */
2461
2462 static rtx
2463 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2464 {
2465   struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2466
2467   if (!rtx_equal_p (from, old_rtx))
2468     return NULL_RTX;
2469   if (!pair->adjusted)
2470     {
2471       pair->adjusted = true;
2472 #ifdef AUTO_INC_DEC
2473       pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2474 #else
2475       pair->to = copy_rtx (pair->to);
2476 #endif
2477       pair->to = make_compound_operation (pair->to, SET);
2478       return pair->to;
2479     }
2480   return copy_rtx (pair->to);
2481 }
2482
2483 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2484    and LAST, not including INSN, but including LAST.  Also stop at the end
2485    of THIS_BASIC_BLOCK.  */
2486
2487 static void
2488 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2489 {
2490   rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2491
2492   struct rtx_subst_pair p;
2493   p.to = src;
2494   p.adjusted = false;
2495
2496   next = NEXT_INSN (insn);
2497   last = NEXT_INSN (last);
2498   while (next != last && next != end)
2499     {
2500       insn = next;
2501       next = NEXT_INSN (insn);
2502       if (DEBUG_INSN_P (insn))
2503         {
2504           loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2505                                          dest, propagate_for_debug_subst, &p);
2506           if (loc == INSN_VAR_LOCATION_LOC (insn))
2507             continue;
2508           INSN_VAR_LOCATION_LOC (insn) = loc;
2509           df_insn_rescan (insn);
2510         }
2511     }
2512 }
2513
2514 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2515    Note that the INSN should be deleted *after* removing dead edges, so
2516    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2517    but not for a (set (pc) (label_ref FOO)).  */
2518
2519 static void
2520 update_cfg_for_uncondjump (rtx insn)
2521 {
2522   basic_block bb = BLOCK_FOR_INSN (insn);
2523   gcc_assert (BB_END (bb) == insn);
2524
2525   purge_dead_edges (bb);
2526
2527   delete_insn (insn);
2528   if (EDGE_COUNT (bb->succs) == 1)
2529     {
2530       rtx insn;
2531
2532       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2533
2534       /* Remove barriers from the footer if there are any.  */
2535       for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2536         if (BARRIER_P (insn))
2537           {
2538             if (PREV_INSN (insn))
2539               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2540             else
2541               bb->il.rtl->footer = NEXT_INSN (insn);
2542             if (NEXT_INSN (insn))
2543               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2544           }
2545         else if (LABEL_P (insn))
2546           break;
2547     }
2548 }
2549
2550 /* Try to combine the insns I0, I1 and I2 into I3.
2551    Here I0, I1 and I2 appear earlier than I3.
2552    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2553    I3.
2554
2555    If we are combining more than two insns and the resulting insn is not
2556    recognized, try splitting it into two insns.  If that happens, I2 and I3
2557    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2558    Otherwise, I0, I1 and I2 are pseudo-deleted.
2559
2560    Return 0 if the combination does not work.  Then nothing is changed.
2561    If we did the combination, return the insn at which combine should
2562    resume scanning.
2563
2564    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2565    new direct jump instruction.
2566
2567    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2568    been I3 passed to an earlier try_combine within the same basic
2569    block.  */
2570
2571 static rtx
2572 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2573              rtx last_combined_insn)
2574 {
2575   /* New patterns for I3 and I2, respectively.  */
2576   rtx newpat, newi2pat = 0;
2577   rtvec newpat_vec_with_clobbers = 0;
2578   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2579   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2580      dead.  */
2581   int added_sets_0, added_sets_1, added_sets_2;
2582   /* Total number of SETs to put into I3.  */
2583   int total_sets;
2584   /* Nonzero if I2's or I1's body now appears in I3.  */
2585   int i2_is_used = 0, i1_is_used = 0;
2586   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2587   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2588   /* Contains I3 if the destination of I3 is used in its source, which means
2589      that the old life of I3 is being killed.  If that usage is placed into
2590      I2 and not in I3, a REG_DEAD note must be made.  */
2591   rtx i3dest_killed = 0;
2592   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2593   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2594   /* Copy of SET_SRC of I1, if needed.  */
2595   rtx i1src_copy = 0;
2596   /* Set if I2DEST was reused as a scratch register.  */
2597   bool i2scratch = false;
2598   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2599   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2600   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2601   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2602   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2603   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2604   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2605   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2606   rtx new_i3_notes, new_i2_notes;
2607   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2608   int i3_subst_into_i2 = 0;
2609   /* Notes that I1, I2 or I3 is a MULT operation.  */
2610   int have_mult = 0;
2611   int swap_i2i3 = 0;
2612   int changed_i3_dest = 0;
2613
2614   int maxreg;
2615   rtx temp;
2616   struct insn_link *link;
2617   rtx other_pat = 0;
2618   rtx new_other_notes;
2619   int i;
2620
2621   /* Only try four-insn combinations when there's high likelihood of
2622      success.  Look for simple insns, such as loads of constants or
2623      binary operations involving a constant.  */
2624   if (i0)
2625     {
2626       int i;
2627       int ngood = 0;
2628       int nshift = 0;
2629
2630       if (!flag_expensive_optimizations)
2631         return 0;
2632
2633       for (i = 0; i < 4; i++)
2634         {
2635           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2636           rtx set = single_set (insn);
2637           rtx src;
2638           if (!set)
2639             continue;
2640           src = SET_SRC (set);
2641           if (CONSTANT_P (src))
2642             {
2643               ngood += 2;
2644               break;
2645             }
2646           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2647             ngood++;
2648           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2649                    || GET_CODE (src) == LSHIFTRT)
2650             nshift++;
2651         }
2652       if (ngood < 2 && nshift < 2)
2653         return 0;
2654     }
2655
2656   /* Exit early if one of the insns involved can't be used for
2657      combinations.  */
2658   if (cant_combine_insn_p (i3)
2659       || cant_combine_insn_p (i2)
2660       || (i1 && cant_combine_insn_p (i1))
2661       || (i0 && cant_combine_insn_p (i0))
2662       || likely_spilled_retval_p (i3))
2663     return 0;
2664
2665   combine_attempts++;
2666   undobuf.other_insn = 0;
2667
2668   /* Reset the hard register usage information.  */
2669   CLEAR_HARD_REG_SET (newpat_used_regs);
2670
2671   if (dump_file && (dump_flags & TDF_DETAILS))
2672     {
2673       if (i0)
2674         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2675                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2676       else if (i1)
2677         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2678                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2679       else
2680         fprintf (dump_file, "\nTrying %d -> %d:\n",
2681                  INSN_UID (i2), INSN_UID (i3));
2682     }
2683
2684   /* If multiple insns feed into one of I2 or I3, they can be in any
2685      order.  To simplify the code below, reorder them in sequence.  */
2686   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2687     temp = i2, i2 = i0, i0 = temp;
2688   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2689     temp = i1, i1 = i0, i0 = temp;
2690   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2691     temp = i1, i1 = i2, i2 = temp;
2692
2693   added_links_insn = 0;
2694
2695   /* First check for one important special case that the code below will
2696      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2697      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2698      we may be able to replace that destination with the destination of I3.
2699      This occurs in the common code where we compute both a quotient and
2700      remainder into a structure, in which case we want to do the computation
2701      directly into the structure to avoid register-register copies.
2702
2703      Note that this case handles both multiple sets in I2 and also cases
2704      where I2 has a number of CLOBBERs inside the PARALLEL.
2705
2706      We make very conservative checks below and only try to handle the
2707      most common cases of this.  For example, we only handle the case
2708      where I2 and I3 are adjacent to avoid making difficult register
2709      usage tests.  */
2710
2711   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2712       && REG_P (SET_SRC (PATTERN (i3)))
2713       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2714       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2715       && GET_CODE (PATTERN (i2)) == PARALLEL
2716       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2717       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2718          below would need to check what is inside (and reg_overlap_mentioned_p
2719          doesn't support those codes anyway).  Don't allow those destinations;
2720          the resulting insn isn't likely to be recognized anyway.  */
2721       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2722       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2723       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2724                                     SET_DEST (PATTERN (i3)))
2725       && next_active_insn (i2) == i3)
2726     {
2727       rtx p2 = PATTERN (i2);
2728
2729       /* Make sure that the destination of I3,
2730          which we are going to substitute into one output of I2,
2731          is not used within another output of I2.  We must avoid making this:
2732          (parallel [(set (mem (reg 69)) ...)
2733                     (set (reg 69) ...)])
2734          which is not well-defined as to order of actions.
2735          (Besides, reload can't handle output reloads for this.)
2736
2737          The problem can also happen if the dest of I3 is a memory ref,
2738          if another dest in I2 is an indirect memory ref.  */
2739       for (i = 0; i < XVECLEN (p2, 0); i++)
2740         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2741              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2742             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2743                                         SET_DEST (XVECEXP (p2, 0, i))))
2744           break;
2745
2746       if (i == XVECLEN (p2, 0))
2747         for (i = 0; i < XVECLEN (p2, 0); i++)
2748           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2749               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2750             {
2751               combine_merges++;
2752
2753               subst_insn = i3;
2754               subst_low_luid = DF_INSN_LUID (i2);
2755
2756               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2757               i2src = SET_SRC (XVECEXP (p2, 0, i));
2758               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2759               i2dest_killed = dead_or_set_p (i2, i2dest);
2760
2761               /* Replace the dest in I2 with our dest and make the resulting
2762                  insn the new pattern for I3.  Then skip to where we validate
2763                  the pattern.  Everything was set up above.  */
2764               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2765               newpat = p2;
2766               i3_subst_into_i2 = 1;
2767               goto validate_replacement;
2768             }
2769     }
2770
2771   /* If I2 is setting a pseudo to a constant and I3 is setting some
2772      sub-part of it to another constant, merge them by making a new
2773      constant.  */
2774   if (i1 == 0
2775       && (temp = single_set (i2)) != 0
2776       && (CONST_INT_P (SET_SRC (temp))
2777           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2778       && GET_CODE (PATTERN (i3)) == SET
2779       && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2780           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2781       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2782     {
2783       rtx dest = SET_DEST (PATTERN (i3));
2784       int offset = -1;
2785       int width = 0;
2786
2787       if (GET_CODE (dest) == ZERO_EXTRACT)
2788         {
2789           if (CONST_INT_P (XEXP (dest, 1))
2790               && CONST_INT_P (XEXP (dest, 2)))
2791             {
2792               width = INTVAL (XEXP (dest, 1));
2793               offset = INTVAL (XEXP (dest, 2));
2794               dest = XEXP (dest, 0);
2795               if (BITS_BIG_ENDIAN)
2796                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2797             }
2798         }
2799       else
2800         {
2801           if (GET_CODE (dest) == STRICT_LOW_PART)
2802             dest = XEXP (dest, 0);
2803           width = GET_MODE_PRECISION (GET_MODE (dest));
2804           offset = 0;
2805         }
2806
2807       if (offset >= 0)
2808         {
2809           /* If this is the low part, we're done.  */
2810           if (subreg_lowpart_p (dest))
2811             ;
2812           /* Handle the case where inner is twice the size of outer.  */
2813           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2814                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2815             offset += GET_MODE_PRECISION (GET_MODE (dest));
2816           /* Otherwise give up for now.  */
2817           else
2818             offset = -1;
2819         }
2820
2821       if (offset >= 0
2822           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2823               <= HOST_BITS_PER_DOUBLE_INT))
2824         {
2825           double_int m, o, i;
2826           rtx inner = SET_SRC (PATTERN (i3));
2827           rtx outer = SET_SRC (temp);
2828
2829           o = rtx_to_double_int (outer);
2830           i = rtx_to_double_int (inner);
2831
2832           m = double_int_mask (width);
2833           i = double_int_and (i, m);
2834           m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2835           i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2836           o = double_int_ior (double_int_and_not (o, m), i);
2837
2838           combine_merges++;
2839           subst_insn = i3;
2840           subst_low_luid = DF_INSN_LUID (i2);
2841           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2842           i2dest = SET_DEST (temp);
2843           i2dest_killed = dead_or_set_p (i2, i2dest);
2844
2845           /* Replace the source in I2 with the new constant and make the
2846              resulting insn the new pattern for I3.  Then skip to where we
2847              validate the pattern.  Everything was set up above.  */
2848           SUBST (SET_SRC (temp),
2849                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2850
2851           newpat = PATTERN (i2);
2852
2853           /* The dest of I3 has been replaced with the dest of I2.  */
2854           changed_i3_dest = 1;
2855           goto validate_replacement;
2856         }
2857     }
2858
2859 #ifndef HAVE_cc0
2860   /* If we have no I1 and I2 looks like:
2861         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2862                    (set Y OP)])
2863      make up a dummy I1 that is
2864         (set Y OP)
2865      and change I2 to be
2866         (set (reg:CC X) (compare:CC Y (const_int 0)))
2867
2868      (We can ignore any trailing CLOBBERs.)
2869
2870      This undoes a previous combination and allows us to match a branch-and-
2871      decrement insn.  */
2872
2873   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2874       && XVECLEN (PATTERN (i2), 0) >= 2
2875       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2876       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2877           == MODE_CC)
2878       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2879       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2880       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2881       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2882       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2883                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2884     {
2885       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2886         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2887           break;
2888
2889       if (i == 1)
2890         {
2891           /* We make I1 with the same INSN_UID as I2.  This gives it
2892              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2893              never appear in the insn stream so giving it the same INSN_UID
2894              as I2 will not cause a problem.  */
2895
2896           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2897                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2898                              INSN_LOCATOR (i2), -1, NULL_RTX);
2899
2900           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2901           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2902                  SET_DEST (PATTERN (i1)));
2903           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2904         }
2905     }
2906 #endif
2907
2908   /* Verify that I2 and I1 are valid for combining.  */
2909   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2910       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2911                                  &i1dest, &i1src))
2912       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2913                                  &i0dest, &i0src)))
2914     {
2915       undo_all ();
2916       return 0;
2917     }
2918
2919   /* Record whether I2DEST is used in I2SRC and similarly for the other
2920      cases.  Knowing this will help in register status updating below.  */
2921   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2922   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2923   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2924   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2925   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2926   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2927   i2dest_killed = dead_or_set_p (i2, i2dest);
2928   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2929   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2930
2931   /* For the earlier insns, determine which of the subsequent ones they
2932      feed.  */
2933   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2934   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2935   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2936                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2937                              && reg_overlap_mentioned_p (i0dest, i2src))));
2938
2939   /* Ensure that I3's pattern can be the destination of combines.  */
2940   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2941                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2942                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2943                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2944                           &i3dest_killed))
2945     {
2946       undo_all ();
2947       return 0;
2948     }
2949
2950   /* See if any of the insns is a MULT operation.  Unless one is, we will
2951      reject a combination that is, since it must be slower.  Be conservative
2952      here.  */
2953   if (GET_CODE (i2src) == MULT
2954       || (i1 != 0 && GET_CODE (i1src) == MULT)
2955       || (i0 != 0 && GET_CODE (i0src) == MULT)
2956       || (GET_CODE (PATTERN (i3)) == SET
2957           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2958     have_mult = 1;
2959
2960   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2961      We used to do this EXCEPT in one case: I3 has a post-inc in an
2962      output operand.  However, that exception can give rise to insns like
2963         mov r3,(r3)+
2964      which is a famous insn on the PDP-11 where the value of r3 used as the
2965      source was model-dependent.  Avoid this sort of thing.  */
2966
2967 #if 0
2968   if (!(GET_CODE (PATTERN (i3)) == SET
2969         && REG_P (SET_SRC (PATTERN (i3)))
2970         && MEM_P (SET_DEST (PATTERN (i3)))
2971         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2972             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2973     /* It's not the exception.  */
2974 #endif
2975 #ifdef AUTO_INC_DEC
2976     {
2977       rtx link;
2978       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2979         if (REG_NOTE_KIND (link) == REG_INC
2980             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2981                 || (i1 != 0
2982                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2983           {
2984             undo_all ();
2985             return 0;
2986           }
2987     }
2988 #endif
2989
2990   /* See if the SETs in I1 or I2 need to be kept around in the merged
2991      instruction: whenever the value set there is still needed past I3.
2992      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2993
2994      For the SET in I1, we have two cases:  If I1 and I2 independently
2995      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2996      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2997      in I1 needs to be kept around unless I1DEST dies or is set in either
2998      I2 or I3.  The same consideration applies to I0.  */
2999
3000   added_sets_2 = !dead_or_set_p (i3, i2dest);
3001
3002   if (i1)
3003     added_sets_1 = !(dead_or_set_p (i3, i1dest)
3004                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3005   else
3006     added_sets_1 = 0;
3007
3008   if (i0)
3009     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
3010                       || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3011                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
3012   else
3013     added_sets_0 = 0;
3014
3015   /* We are about to copy insns for the case where they need to be kept
3016      around.  Check that they can be copied in the merged instruction.  */
3017
3018   if (targetm.cannot_copy_insn_p
3019       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3020           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3021           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3022     {
3023       undo_all ();
3024       return 0;
3025     }
3026
3027   /* If the set in I2 needs to be kept around, we must make a copy of
3028      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3029      PATTERN (I2), we are only substituting for the original I1DEST, not into
3030      an already-substituted copy.  This also prevents making self-referential
3031      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3032      I2DEST.  */
3033
3034   if (added_sets_2)
3035     {
3036       if (GET_CODE (PATTERN (i2)) == PARALLEL)
3037         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3038       else
3039         i2pat = copy_rtx (PATTERN (i2));
3040     }
3041
3042   if (added_sets_1)
3043     {
3044       if (GET_CODE (PATTERN (i1)) == PARALLEL)
3045         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3046       else
3047         i1pat = copy_rtx (PATTERN (i1));
3048     }
3049
3050   if (added_sets_0)
3051     {
3052       if (GET_CODE (PATTERN (i0)) == PARALLEL)
3053         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3054       else
3055         i0pat = copy_rtx (PATTERN (i0));
3056     }
3057
3058   combine_merges++;
3059
3060   /* Substitute in the latest insn for the regs set by the earlier ones.  */
3061
3062   maxreg = max_reg_num ();
3063
3064   subst_insn = i3;
3065
3066 #ifndef HAVE_cc0
3067   /* Many machines that don't use CC0 have insns that can both perform an
3068      arithmetic operation and set the condition code.  These operations will
3069      be represented as a PARALLEL with the first element of the vector
3070      being a COMPARE of an arithmetic operation with the constant zero.
3071      The second element of the vector will set some pseudo to the result
3072      of the same arithmetic operation.  If we simplify the COMPARE, we won't
3073      match such a pattern and so will generate an extra insn.   Here we test
3074      for this case, where both the comparison and the operation result are
3075      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3076      I2SRC.  Later we will make the PARALLEL that contains I2.  */
3077
3078   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3079       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3080       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3081       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3082     {
3083       rtx newpat_dest;
3084       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
3085       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3086       enum machine_mode compare_mode, orig_compare_mode;
3087       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3088
3089       newpat = PATTERN (i3);
3090       newpat_dest = SET_DEST (newpat);
3091       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3092
3093       if (undobuf.other_insn == 0
3094           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3095                                             &cc_use_insn)))
3096         {
3097           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3098           compare_code = simplify_compare_const (compare_code,
3099                                                  op0, &op1);
3100 #ifdef CANONICALIZE_COMPARISON
3101           CANONICALIZE_COMPARISON (compare_code, op0, op1);
3102 #endif
3103         }
3104
3105       /* Do the rest only if op1 is const0_rtx, which may be the
3106          result of simplification.  */
3107       if (op1 == const0_rtx)
3108         {
3109           /* If a single use of the CC is found, prepare to modify it
3110              when SELECT_CC_MODE returns a new CC-class mode, or when
3111              the above simplify_compare_const() returned a new comparison
3112              operator.  undobuf.other_insn is assigned the CC use insn
3113              when modifying it.  */
3114           if (cc_use_loc)
3115             {
3116 #ifdef SELECT_CC_MODE
3117               enum machine_mode new_mode
3118                 = SELECT_CC_MODE (compare_code, op0, op1);
3119               if (new_mode != orig_compare_mode
3120                   && can_change_dest_mode (SET_DEST (newpat),
3121                                            added_sets_2, new_mode))
3122                 {
3123                   unsigned int regno = REGNO (newpat_dest);
3124                   compare_mode = new_mode;
3125                   if (regno < FIRST_PSEUDO_REGISTER)
3126                     newpat_dest = gen_rtx_REG (compare_mode, regno);
3127                   else
3128                     {
3129                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3130                       newpat_dest = regno_reg_rtx[regno];
3131                     }
3132                 }
3133 #endif
3134               /* Cases for modifying the CC-using comparison.  */
3135               if (compare_code != orig_compare_code
3136                   /* ??? Do we need to verify the zero rtx?  */
3137                   && XEXP (*cc_use_loc, 1) == const0_rtx)
3138                 {
3139                   /* Replace cc_use_loc with entire new RTX.  */
3140                   SUBST (*cc_use_loc,
3141                          gen_rtx_fmt_ee (compare_code, compare_mode,
3142                                          newpat_dest, const0_rtx));
3143                   undobuf.other_insn = cc_use_insn;
3144                 }
3145               else if (compare_mode != orig_compare_mode)
3146                 {
3147                   /* Just replace the CC reg with a new mode.  */
3148                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3149                   undobuf.other_insn = cc_use_insn;
3150                 }
3151             }
3152
3153           /* Now we modify the current newpat:
3154              First, SET_DEST(newpat) is updated if the CC mode has been
3155              altered. For targets without SELECT_CC_MODE, this should be
3156              optimized away.  */
3157           if (compare_mode != orig_compare_mode)
3158             SUBST (SET_DEST (newpat), newpat_dest);
3159           /* This is always done to propagate i2src into newpat.  */
3160           SUBST (SET_SRC (newpat),
3161                  gen_rtx_COMPARE (compare_mode, op0, op1));
3162           /* Create new version of i2pat if needed; the below PARALLEL
3163              creation needs this to work correctly.  */
3164           if (! rtx_equal_p (i2src, op0))
3165             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3166           i2_is_used = 1;
3167         }
3168     }
3169 #endif
3170
3171   if (i2_is_used == 0)
3172     {
3173       /* It is possible that the source of I2 or I1 may be performing
3174          an unneeded operation, such as a ZERO_EXTEND of something
3175          that is known to have the high part zero.  Handle that case
3176          by letting subst look at the inner insns.
3177
3178          Another way to do this would be to have a function that tries
3179          to simplify a single insn instead of merging two or more
3180          insns.  We don't do this because of the potential of infinite
3181          loops and because of the potential extra memory required.
3182          However, doing it the way we are is a bit of a kludge and
3183          doesn't catch all cases.
3184
3185          But only do this if -fexpensive-optimizations since it slows
3186          things down and doesn't usually win.
3187
3188          This is not done in the COMPARE case above because the
3189          unmodified I2PAT is used in the PARALLEL and so a pattern
3190          with a modified I2SRC would not match.  */
3191
3192       if (flag_expensive_optimizations)
3193         {
3194           /* Pass pc_rtx so no substitutions are done, just
3195              simplifications.  */
3196           if (i1)
3197             {
3198               subst_low_luid = DF_INSN_LUID (i1);
3199               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3200             }
3201
3202           subst_low_luid = DF_INSN_LUID (i2);
3203           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3204         }
3205
3206       n_occurrences = 0;                /* `subst' counts here */
3207       subst_low_luid = DF_INSN_LUID (i2);
3208
3209       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3210          copy of I2SRC each time we substitute it, in order to avoid creating
3211          self-referential RTL when we will be substituting I1SRC for I1DEST
3212          later.  Likewise if I0 feeds into I2, either directly or indirectly
3213          through I1, and I0DEST is in I0SRC.  */
3214       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3215                       (i1_feeds_i2_n && i1dest_in_i1src)
3216                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3217                           && i0dest_in_i0src));
3218       substed_i2 = 1;
3219
3220       /* Record whether I2's body now appears within I3's body.  */
3221       i2_is_used = n_occurrences;
3222     }
3223
3224   /* If we already got a failure, don't try to do more.  Otherwise, try to
3225      substitute I1 if we have it.  */
3226
3227   if (i1 && GET_CODE (newpat) != CLOBBER)
3228     {
3229       /* Check that an autoincrement side-effect on I1 has not been lost.
3230          This happens if I1DEST is mentioned in I2 and dies there, and
3231          has disappeared from the new pattern.  */
3232       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3233            && i1_feeds_i2_n
3234            && dead_or_set_p (i2, i1dest)
3235            && !reg_overlap_mentioned_p (i1dest, newpat))
3236            /* Before we can do this substitution, we must redo the test done
3237               above (see detailed comments there) that ensures I1DEST isn't
3238               mentioned in any SETs in NEWPAT that are field assignments.  */
3239           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3240                                 0, 0, 0))
3241         {
3242           undo_all ();
3243           return 0;
3244         }
3245
3246       n_occurrences = 0;
3247       subst_low_luid = DF_INSN_LUID (i1);
3248
3249       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3250          copy of I1SRC each time we substitute it, in order to avoid creating
3251          self-referential RTL when we will be substituting I0SRC for I0DEST
3252          later.  */
3253       newpat = subst (newpat, i1dest, i1src, 0, 0,
3254                       i0_feeds_i1_n && i0dest_in_i0src);
3255       substed_i1 = 1;
3256
3257       /* Record whether I1's body now appears within I3's body.  */
3258       i1_is_used = n_occurrences;
3259     }
3260
3261   /* Likewise for I0 if we have it.  */
3262
3263   if (i0 && GET_CODE (newpat) != CLOBBER)
3264     {
3265       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3266            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3267                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3268            && !reg_overlap_mentioned_p (i0dest, newpat))
3269           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3270                                 0, 0, 0))
3271         {
3272           undo_all ();
3273           return 0;
3274         }
3275
3276       /* If the following substitution will modify I1SRC, make a copy of it
3277          for the case where it is substituted for I1DEST in I2PAT later.  */
3278       if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3279         i1src_copy = copy_rtx (i1src);
3280
3281       n_occurrences = 0;
3282       subst_low_luid = DF_INSN_LUID (i0);
3283       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3284       substed_i0 = 1;
3285     }
3286
3287   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3288      to count all the ways that I2SRC and I1SRC can be used.  */
3289   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3290        && i2_is_used + added_sets_2 > 1)
3291       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3292           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3293               > 1))
3294       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3295           && (n_occurrences + added_sets_0
3296               + (added_sets_1 && i0_feeds_i1_n)
3297               + (added_sets_2 && i0_feeds_i2_n)
3298               > 1))
3299       /* Fail if we tried to make a new register.  */
3300       || max_reg_num () != maxreg
3301       /* Fail if we couldn't do something and have a CLOBBER.  */
3302       || GET_CODE (newpat) == CLOBBER
3303       /* Fail if this new pattern is a MULT and we didn't have one before
3304          at the outer level.  */
3305       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3306           && ! have_mult))
3307     {
3308       undo_all ();
3309       return 0;
3310     }
3311
3312   /* If the actions of the earlier insns must be kept
3313      in addition to substituting them into the latest one,
3314      we must make a new PARALLEL for the latest insn
3315      to hold additional the SETs.  */
3316
3317   if (added_sets_0 || added_sets_1 || added_sets_2)
3318     {
3319       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3320       combine_extras++;
3321
3322       if (GET_CODE (newpat) == PARALLEL)
3323         {
3324           rtvec old = XVEC (newpat, 0);
3325           total_sets = XVECLEN (newpat, 0) + extra_sets;
3326           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3327           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3328                   sizeof (old->elem[0]) * old->num_elem);
3329         }
3330       else
3331         {
3332           rtx old = newpat;
3333           total_sets = 1 + extra_sets;
3334           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3335           XVECEXP (newpat, 0, 0) = old;
3336         }
3337
3338       if (added_sets_0)
3339         XVECEXP (newpat, 0, --total_sets) = i0pat;
3340
3341       if (added_sets_1)
3342         {
3343           rtx t = i1pat;
3344           if (i0_feeds_i1_n)
3345             t = subst (t, i0dest, i0src, 0, 0, 0);
3346
3347           XVECEXP (newpat, 0, --total_sets) = t;
3348         }
3349       if (added_sets_2)
3350         {
3351           rtx t = i2pat;
3352           if (i1_feeds_i2_n)
3353             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3354                        i0_feeds_i1_n && i0dest_in_i0src);
3355           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3356             t = subst (t, i0dest, i0src, 0, 0, 0);
3357
3358           XVECEXP (newpat, 0, --total_sets) = t;
3359         }
3360     }
3361
3362  validate_replacement:
3363
3364   /* Note which hard regs this insn has as inputs.  */
3365   mark_used_regs_combine (newpat);
3366
3367   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3368      consider splitting this pattern, we might need these clobbers.  */
3369   if (i1 && GET_CODE (newpat) == PARALLEL
3370       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3371     {
3372       int len = XVECLEN (newpat, 0);
3373
3374       newpat_vec_with_clobbers = rtvec_alloc (len);
3375       for (i = 0; i < len; i++)
3376         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3377     }
3378
3379   /* Is the result of combination a valid instruction?  */
3380   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3381
3382   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3383      the second SET's destination is a register that is unused and isn't
3384      marked as an instruction that might trap in an EH region.  In that case,
3385      we just need the first SET.   This can occur when simplifying a divmod
3386      insn.  We *must* test for this case here because the code below that
3387      splits two independent SETs doesn't handle this case correctly when it
3388      updates the register status.
3389
3390      It's pointless doing this if we originally had two sets, one from
3391      i3, and one from i2.  Combining then splitting the parallel results
3392      in the original i2 again plus an invalid insn (which we delete).
3393      The net effect is only to move instructions around, which makes
3394      debug info less accurate.
3395
3396      Also check the case where the first SET's destination is unused.
3397      That would not cause incorrect code, but does cause an unneeded
3398      insn to remain.  */
3399
3400   if (insn_code_number < 0
3401       && !(added_sets_2 && i1 == 0)
3402       && GET_CODE (newpat) == PARALLEL
3403       && XVECLEN (newpat, 0) == 2
3404       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3405       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3406       && asm_noperands (newpat) < 0)
3407     {
3408       rtx set0 = XVECEXP (newpat, 0, 0);
3409       rtx set1 = XVECEXP (newpat, 0, 1);
3410
3411       if (((REG_P (SET_DEST (set1))
3412             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3413            || (GET_CODE (SET_DEST (set1)) == SUBREG
3414                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3415           && insn_nothrow_p (i3)
3416           && !side_effects_p (SET_SRC (set1)))
3417         {
3418           newpat = set0;
3419           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3420         }
3421
3422       else if (((REG_P (SET_DEST (set0))
3423                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3424                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3425                     && find_reg_note (i3, REG_UNUSED,
3426                                       SUBREG_REG (SET_DEST (set0)))))
3427                && insn_nothrow_p (i3)
3428                && !side_effects_p (SET_SRC (set0)))
3429         {
3430           newpat = set1;
3431           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3432
3433           if (insn_code_number >= 0)
3434             changed_i3_dest = 1;
3435         }
3436     }
3437
3438   /* If we were combining three insns and the result is a simple SET
3439      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3440      insns.  There are two ways to do this.  It can be split using a
3441      machine-specific method (like when you have an addition of a large
3442      constant) or by combine in the function find_split_point.  */
3443
3444   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3445       && asm_noperands (newpat) < 0)
3446     {
3447       rtx parallel, m_split, *split;
3448
3449       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3450          use I2DEST as a scratch register will help.  In the latter case,
3451          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3452
3453       m_split = combine_split_insns (newpat, i3);
3454
3455       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3456          inputs of NEWPAT.  */
3457
3458       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3459          possible to try that as a scratch reg.  This would require adding
3460          more code to make it work though.  */
3461
3462       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3463         {
3464           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3465
3466           /* First try to split using the original register as a
3467              scratch register.  */
3468           parallel = gen_rtx_PARALLEL (VOIDmode,
3469                                        gen_rtvec (2, newpat,
3470                                                   gen_rtx_CLOBBER (VOIDmode,
3471                                                                    i2dest)));
3472           m_split = combine_split_insns (parallel, i3);
3473
3474           /* If that didn't work, try changing the mode of I2DEST if
3475              we can.  */
3476           if (m_split == 0
3477               && new_mode != GET_MODE (i2dest)
3478               && new_mode != VOIDmode
3479               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3480             {
3481               enum machine_mode old_mode = GET_MODE (i2dest);
3482               rtx ni2dest;
3483
3484               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3485                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3486               else
3487                 {
3488                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3489                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3490                 }
3491
3492               parallel = (gen_rtx_PARALLEL
3493                           (VOIDmode,
3494                            gen_rtvec (2, newpat,
3495                                       gen_rtx_CLOBBER (VOIDmode,
3496                                                        ni2dest))));
3497               m_split = combine_split_insns (parallel, i3);
3498
3499               if (m_split == 0
3500                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3501                 {
3502                   struct undo *buf;
3503
3504                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3505                   buf = undobuf.undos;
3506                   undobuf.undos = buf->next;
3507                   buf->next = undobuf.frees;
3508                   undobuf.frees = buf;
3509                 }
3510             }
3511
3512           i2scratch = m_split != 0;
3513         }
3514
3515       /* If recog_for_combine has discarded clobbers, try to use them
3516          again for the split.  */
3517       if (m_split == 0 && newpat_vec_with_clobbers)
3518         {
3519           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3520           m_split = combine_split_insns (parallel, i3);
3521         }
3522
3523       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3524         {
3525           m_split = PATTERN (m_split);
3526           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3527           if (insn_code_number >= 0)
3528             newpat = m_split;
3529         }
3530       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3531                && (next_nonnote_nondebug_insn (i2) == i3
3532                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3533         {
3534           rtx i2set, i3set;
3535           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3536           newi2pat = PATTERN (m_split);
3537
3538           i3set = single_set (NEXT_INSN (m_split));
3539           i2set = single_set (m_split);
3540
3541           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3542
3543           /* If I2 or I3 has multiple SETs, we won't know how to track
3544              register status, so don't use these insns.  If I2's destination
3545              is used between I2 and I3, we also can't use these insns.  */
3546
3547           if (i2_code_number >= 0 && i2set && i3set
3548               && (next_nonnote_nondebug_insn (i2) == i3
3549                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3550             insn_code_number = recog_for_combine (&newi3pat, i3,
3551                                                   &new_i3_notes);
3552           if (insn_code_number >= 0)
3553             newpat = newi3pat;
3554
3555           /* It is possible that both insns now set the destination of I3.
3556              If so, we must show an extra use of it.  */
3557
3558           if (insn_code_number >= 0)
3559             {
3560               rtx new_i3_dest = SET_DEST (i3set);
3561               rtx new_i2_dest = SET_DEST (i2set);
3562
3563               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3564                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3565                      || GET_CODE (new_i3_dest) == SUBREG)
3566                 new_i3_dest = XEXP (new_i3_dest, 0);
3567
3568               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3569                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3570                      || GET_CODE (new_i2_dest) == SUBREG)
3571                 new_i2_dest = XEXP (new_i2_dest, 0);
3572
3573               if (REG_P (new_i3_dest)
3574                   && REG_P (new_i2_dest)
3575                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3576                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3577             }
3578         }
3579
3580       /* If we can split it and use I2DEST, go ahead and see if that
3581          helps things be recognized.  Verify that none of the registers
3582          are set between I2 and I3.  */
3583       if (insn_code_number < 0
3584           && (split = find_split_point (&newpat, i3, false)) != 0
3585 #ifdef HAVE_cc0
3586           && REG_P (i2dest)
3587 #endif
3588           /* We need I2DEST in the proper mode.  If it is a hard register
3589              or the only use of a pseudo, we can change its mode.
3590              Make sure we don't change a hard register to have a mode that
3591              isn't valid for it, or change the number of registers.  */
3592           && (GET_MODE (*split) == GET_MODE (i2dest)
3593               || GET_MODE (*split) == VOIDmode
3594               || can_change_dest_mode (i2dest, added_sets_2,
3595                                        GET_MODE (*split)))
3596           && (next_nonnote_nondebug_insn (i2) == i3
3597               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3598           /* We can't overwrite I2DEST if its value is still used by
3599              NEWPAT.  */
3600           && ! reg_referenced_p (i2dest, newpat))
3601         {
3602           rtx newdest = i2dest;
3603           enum rtx_code split_code = GET_CODE (*split);
3604           enum machine_mode split_mode = GET_MODE (*split);
3605           bool subst_done = false;
3606           newi2pat = NULL_RTX;
3607
3608           i2scratch = true;
3609
3610           /* *SPLIT may be part of I2SRC, so make sure we have the
3611              original expression around for later debug processing.
3612              We should not need I2SRC any more in other cases.  */
3613           if (MAY_HAVE_DEBUG_INSNS)
3614             i2src = copy_rtx (i2src);
3615           else
3616             i2src = NULL;
3617
3618           /* Get NEWDEST as a register in the proper mode.  We have already
3619              validated that we can do this.  */
3620           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3621             {
3622               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3623                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3624               else
3625                 {
3626                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3627                   newdest = regno_reg_rtx[REGNO (i2dest)];
3628                 }
3629             }
3630
3631           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3632              an ASHIFT.  This can occur if it was inside a PLUS and hence
3633              appeared to be a memory address.  This is a kludge.  */
3634           if (split_code == MULT
3635               && CONST_INT_P (XEXP (*split, 1))
3636               && INTVAL (XEXP (*split, 1)) > 0
3637               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3638             {
3639               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3640                                              XEXP (*split, 0), GEN_INT (i)));
3641               /* Update split_code because we may not have a multiply
3642                  anymore.  */
3643               split_code = GET_CODE (*split);
3644             }
3645
3646 #ifdef INSN_SCHEDULING
3647           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3648              be written as a ZERO_EXTEND.  */
3649           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3650             {
3651 #ifdef LOAD_EXTEND_OP
3652               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3653                  what it really is.  */
3654               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3655                   == SIGN_EXTEND)
3656                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3657                                                     SUBREG_REG (*split)));
3658               else
3659 #endif
3660                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3661                                                     SUBREG_REG (*split)));
3662             }
3663 #endif
3664
3665           /* Attempt to split binary operators using arithmetic identities.  */
3666           if (BINARY_P (SET_SRC (newpat))
3667               && split_mode == GET_MODE (SET_SRC (newpat))
3668               && ! side_effects_p (SET_SRC (newpat)))
3669             {
3670               rtx setsrc = SET_SRC (newpat);
3671               enum machine_mode mode = GET_MODE (setsrc);
3672               enum rtx_code code = GET_CODE (setsrc);
3673               rtx src_op0 = XEXP (setsrc, 0);
3674               rtx src_op1 = XEXP (setsrc, 1);
3675
3676               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3677               if (rtx_equal_p (src_op0, src_op1))
3678                 {
3679                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3680                   SUBST (XEXP (setsrc, 0), newdest);
3681                   SUBST (XEXP (setsrc, 1), newdest);
3682                   subst_done = true;
3683                 }
3684               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3685               else if ((code == PLUS || code == MULT)
3686                        && GET_CODE (src_op0) == code
3687                        && GET_CODE (XEXP (src_op0, 0)) == code
3688                        && (INTEGRAL_MODE_P (mode)
3689                            || (FLOAT_MODE_P (mode)
3690                                && flag_unsafe_math_optimizations)))
3691                 {
3692                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3693                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3694                   rtx r = XEXP (src_op0, 1);
3695                   rtx s = src_op1;
3696
3697                   /* Split both "((X op Y) op X) op Y" and
3698                      "((X op Y) op Y) op X" as "T op T" where T is
3699                      "X op Y".  */
3700                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3701                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3702                     {
3703                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3704                                               XEXP (src_op0, 0));
3705                       SUBST (XEXP (setsrc, 0), newdest);
3706                       SUBST (XEXP (setsrc, 1), newdest);
3707                       subst_done = true;
3708                     }
3709                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3710                      T is "X op Y".  */
3711                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3712                     {
3713                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3714                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3715                       SUBST (XEXP (setsrc, 0), newdest);
3716                       SUBST (XEXP (setsrc, 1), newdest);
3717                       subst_done = true;
3718                     }
3719                 }
3720             }
3721
3722           if (!subst_done)
3723             {
3724               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3725               SUBST (*split, newdest);
3726             }
3727
3728           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3729
3730           /* recog_for_combine might have added CLOBBERs to newi2pat.
3731              Make sure NEWPAT does not depend on the clobbered regs.  */
3732           if (GET_CODE (newi2pat) == PARALLEL)
3733             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3734               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3735                 {
3736                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3737                   if (reg_overlap_mentioned_p (reg, newpat))
3738                     {
3739                       undo_all ();
3740                       return 0;
3741                     }
3742                 }
3743
3744           /* If the split point was a MULT and we didn't have one before,
3745              don't use one now.  */
3746           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3747             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3748         }
3749     }
3750
3751   /* Check for a case where we loaded from memory in a narrow mode and
3752      then sign extended it, but we need both registers.  In that case,
3753      we have a PARALLEL with both loads from the same memory location.
3754      We can split this into a load from memory followed by a register-register
3755      copy.  This saves at least one insn, more if register allocation can
3756      eliminate the copy.
3757
3758      We cannot do this if the destination of the first assignment is a
3759      condition code register or cc0.  We eliminate this case by making sure
3760      the SET_DEST and SET_SRC have the same mode.
3761
3762      We cannot do this if the destination of the second assignment is
3763      a register that we have already assumed is zero-extended.  Similarly
3764      for a SUBREG of such a register.  */
3765
3766   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3767            && GET_CODE (newpat) == PARALLEL
3768            && XVECLEN (newpat, 0) == 2
3769            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3770            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3771            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3772                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3773            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3774            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3775                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3776            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3777                                    DF_INSN_LUID (i2))
3778            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3779            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3780            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3781                  (REG_P (temp)
3782                   && VEC_index (reg_stat_type, reg_stat,
3783                                 REGNO (temp))->nonzero_bits != 0
3784                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3785                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3786                   && (VEC_index (reg_stat_type, reg_stat,
3787                                  REGNO (temp))->nonzero_bits
3788                       != GET_MODE_MASK (word_mode))))
3789            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3790                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3791                      (REG_P (temp)
3792                       && VEC_index (reg_stat_type, reg_stat,
3793                                     REGNO (temp))->nonzero_bits != 0
3794                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3795                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3796                       && (VEC_index (reg_stat_type, reg_stat,
3797                                      REGNO (temp))->nonzero_bits
3798                           != GET_MODE_MASK (word_mode)))))
3799            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3800                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3801            && ! find_reg_note (i3, REG_UNUSED,
3802                                SET_DEST (XVECEXP (newpat, 0, 0))))
3803     {
3804       rtx ni2dest;
3805
3806       newi2pat = XVECEXP (newpat, 0, 0);
3807       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3808       newpat = XVECEXP (newpat, 0, 1);
3809       SUBST (SET_SRC (newpat),
3810              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3811       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3812
3813       if (i2_code_number >= 0)
3814         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3815
3816       if (insn_code_number >= 0)
3817         swap_i2i3 = 1;
3818     }
3819
3820   /* Similarly, check for a case where we have a PARALLEL of two independent
3821      SETs but we started with three insns.  In this case, we can do the sets
3822      as two separate insns.  This case occurs when some SET allows two
3823      other insns to combine, but the destination of that SET is still live.  */
3824
3825   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3826            && GET_CODE (newpat) == PARALLEL
3827            && XVECLEN (newpat, 0) == 2
3828            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3829            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3830            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3831            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3832            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3833            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3834            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3835                                   XVECEXP (newpat, 0, 0))
3836            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3837                                   XVECEXP (newpat, 0, 1))
3838            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3839                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3840     {
3841       /* Normally, it doesn't matter which of the two is done first,
3842          but the one that references cc0 can't be the second, and
3843          one which uses any regs/memory set in between i2 and i3 can't
3844          be first.  */
3845       if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3846                               DF_INSN_LUID (i2))
3847 #ifdef HAVE_cc0
3848           && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3849 #endif
3850          )
3851         {
3852           newi2pat = XVECEXP (newpat, 0, 1);
3853           newpat = XVECEXP (newpat, 0, 0);
3854         }
3855       else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3856                                    DF_INSN_LUID (i2))
3857 #ifdef HAVE_cc0
3858                && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3859 #endif
3860               )
3861         {
3862           newi2pat = XVECEXP (newpat, 0, 0);
3863           newpat = XVECEXP (newpat, 0, 1);
3864         }
3865       else
3866         {
3867           undo_all ();
3868           return 0;
3869         }
3870
3871       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3872
3873       if (i2_code_number >= 0)
3874         {
3875           /* recog_for_combine might have added CLOBBERs to newi2pat.
3876              Make sure NEWPAT does not depend on the clobbered regs.  */
3877           if (GET_CODE (newi2pat) == PARALLEL)
3878             {
3879               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3880                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3881                   {
3882                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3883                     if (reg_overlap_mentioned_p (reg, newpat))
3884                       {
3885                         undo_all ();
3886                         return 0;
3887                       }
3888                   }
3889             }
3890
3891           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3892         }
3893     }
3894
3895   /* If it still isn't recognized, fail and change things back the way they
3896      were.  */
3897   if ((insn_code_number < 0
3898        /* Is the result a reasonable ASM_OPERANDS?  */
3899        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3900     {
3901       undo_all ();
3902       return 0;
3903     }
3904
3905   /* If we had to change another insn, make sure it is valid also.  */
3906   if (undobuf.other_insn)
3907     {
3908       CLEAR_HARD_REG_SET (newpat_used_regs);
3909
3910       other_pat = PATTERN (undobuf.other_insn);
3911       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3912                                              &new_other_notes);
3913
3914       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3915         {
3916           undo_all ();
3917           return 0;
3918         }
3919     }
3920
3921 #ifdef HAVE_cc0
3922   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3923      they are adjacent to each other or not.  */
3924   {
3925     rtx p = prev_nonnote_insn (i3);
3926     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3927         && sets_cc0_p (newi2pat))
3928       {
3929         undo_all ();
3930         return 0;
3931       }
3932   }
3933 #endif
3934
3935   /* Only allow this combination if insn_rtx_costs reports that the
3936      replacement instructions are cheaper than the originals.  */
3937   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3938     {
3939       undo_all ();
3940       return 0;
3941     }
3942
3943   if (MAY_HAVE_DEBUG_INSNS)
3944     {
3945       struct undo *undo;
3946
3947       for (undo = undobuf.undos; undo; undo = undo->next)
3948         if (undo->kind == UNDO_MODE)
3949           {
3950             rtx reg = *undo->where.r;
3951             enum machine_mode new_mode = GET_MODE (reg);
3952             enum machine_mode old_mode = undo->old_contents.m;
3953
3954             /* Temporarily revert mode back.  */
3955             adjust_reg_mode (reg, old_mode);
3956
3957             if (reg == i2dest && i2scratch)
3958               {
3959                 /* If we used i2dest as a scratch register with a
3960                    different mode, substitute it for the original
3961                    i2src while its original mode is temporarily
3962                    restored, and then clear i2scratch so that we don't
3963                    do it again later.  */
3964                 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3965                 i2scratch = false;
3966                 /* Put back the new mode.  */
3967                 adjust_reg_mode (reg, new_mode);
3968               }
3969             else
3970               {
3971                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3972                 rtx first, last;
3973
3974                 if (reg == i2dest)
3975                   {
3976                     first = i2;
3977                     last = last_combined_insn;
3978                   }
3979                 else
3980                   {
3981                     first = i3;
3982                     last = undobuf.other_insn;
3983                     gcc_assert (last);
3984                     if (DF_INSN_LUID (last)
3985                         < DF_INSN_LUID (last_combined_insn))
3986                       last = last_combined_insn;
3987                   }
3988
3989                 /* We're dealing with a reg that changed mode but not
3990                    meaning, so we want to turn it into a subreg for
3991                    the new mode.  However, because of REG sharing and
3992                    because its mode had already changed, we have to do
3993                    it in two steps.  First, replace any debug uses of
3994                    reg, with its original mode temporarily restored,
3995                    with this copy we have created; then, replace the
3996                    copy with the SUBREG of the original shared reg,
3997                    once again changed to the new mode.  */
3998                 propagate_for_debug (first, last, reg, tempreg);
3999                 adjust_reg_mode (reg, new_mode);
4000                 propagate_for_debug (first, last, tempreg,
4001                                      lowpart_subreg (old_mode, reg, new_mode));
4002               }
4003           }
4004     }
4005
4006   /* If we will be able to accept this, we have made a
4007      change to the destination of I3.  This requires us to
4008      do a few adjustments.  */
4009
4010   if (changed_i3_dest)
4011     {
4012       PATTERN (i3) = newpat;
4013       adjust_for_new_dest (i3);
4014     }
4015
4016   /* We now know that we can do this combination.  Merge the insns and
4017      update the status of registers and LOG_LINKS.  */
4018
4019   if (undobuf.other_insn)
4020     {
4021       rtx note, next;
4022
4023       PATTERN (undobuf.other_insn) = other_pat;
4024
4025       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4026          are still valid.  Then add any non-duplicate notes added by
4027          recog_for_combine.  */
4028       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4029         {
4030           next = XEXP (note, 1);
4031
4032           if (REG_NOTE_KIND (note) == REG_UNUSED
4033               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4034             remove_note (undobuf.other_insn, note);
4035         }
4036
4037       distribute_notes (new_other_notes, undobuf.other_insn,
4038                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4039                         NULL_RTX);
4040     }
4041
4042   if (swap_i2i3)
4043     {
4044       rtx insn;
4045       struct insn_link *link;
4046       rtx ni2dest;
4047
4048       /* I3 now uses what used to be its destination and which is now
4049          I2's destination.  This requires us to do a few adjustments.  */
4050       PATTERN (i3) = newpat;
4051       adjust_for_new_dest (i3);
4052
4053       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
4054          so we still will.
4055
4056          However, some later insn might be using I2's dest and have
4057          a LOG_LINK pointing at I3.  We must remove this link.
4058          The simplest way to remove the link is to point it at I1,
4059          which we know will be a NOTE.  */
4060
4061       /* newi2pat is usually a SET here; however, recog_for_combine might
4062          have added some clobbers.  */
4063       if (GET_CODE (newi2pat) == PARALLEL)
4064         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4065       else
4066         ni2dest = SET_DEST (newi2pat);
4067
4068       for (insn = NEXT_INSN (i3);
4069            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4070                     || insn != BB_HEAD (this_basic_block->next_bb));
4071            insn = NEXT_INSN (insn))
4072         {
4073           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4074             {
4075               FOR_EACH_LOG_LINK (link, insn)
4076                 if (link->insn == i3)
4077                   link->insn = i1;
4078
4079               break;
4080             }
4081         }
4082     }
4083
4084   {
4085     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4086     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4087     rtx midnotes = 0;
4088     int from_luid;
4089     /* Compute which registers we expect to eliminate.  newi2pat may be setting
4090        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
4091        same as i3dest, in which case newi2pat may be setting i1dest.  */
4092     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4093                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4094                    || !i2dest_killed
4095                    ? 0 : i2dest);
4096     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4097                    || (newi2pat && reg_set_p (i1dest, newi2pat))
4098                    || !i1dest_killed
4099                    ? 0 : i1dest);
4100     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4101                    || (newi2pat && reg_set_p (i0dest, newi2pat))
4102                    || !i0dest_killed
4103                    ? 0 : i0dest);
4104
4105     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4106        clear them.  */
4107     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4108     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4109     if (i1)
4110       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4111     if (i0)
4112       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4113
4114     /* Ensure that we do not have something that should not be shared but
4115        occurs multiple times in the new insns.  Check this by first
4116        resetting all the `used' flags and then copying anything is shared.  */
4117
4118     reset_used_flags (i3notes);
4119     reset_used_flags (i2notes);
4120     reset_used_flags (i1notes);
4121     reset_used_flags (i0notes);
4122     reset_used_flags (newpat);
4123     reset_used_flags (newi2pat);
4124     if (undobuf.other_insn)
4125       reset_used_flags (PATTERN (undobuf.other_insn));
4126
4127     i3notes = copy_rtx_if_shared (i3notes);
4128     i2notes = copy_rtx_if_shared (i2notes);
4129     i1notes = copy_rtx_if_shared (i1notes);
4130     i0notes = copy_rtx_if_shared (i0notes);
4131     newpat = copy_rtx_if_shared (newpat);
4132     newi2pat = copy_rtx_if_shared (newi2pat);
4133     if (undobuf.other_insn)
4134       reset_used_flags (PATTERN (undobuf.other_insn));
4135
4136     INSN_CODE (i3) = insn_code_number;
4137     PATTERN (i3) = newpat;
4138
4139     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4140       {
4141         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4142
4143         reset_used_flags (call_usage);
4144         call_usage = copy_rtx (call_usage);
4145
4146         if (substed_i2)
4147           {
4148             /* I2SRC must still be meaningful at this point.  Some splitting
4149                operations can invalidate I2SRC, but those operations do not
4150                apply to calls.  */
4151             gcc_assert (i2src);
4152             replace_rtx (call_usage, i2dest, i2src);
4153           }
4154
4155         if (substed_i1)
4156           replace_rtx (call_usage, i1dest, i1src);
4157         if (substed_i0)
4158           replace_rtx (call_usage, i0dest, i0src);
4159
4160         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4161       }
4162
4163     if (undobuf.other_insn)
4164       INSN_CODE (undobuf.other_insn) = other_code_number;
4165
4166     /* We had one special case above where I2 had more than one set and
4167        we replaced a destination of one of those sets with the destination
4168        of I3.  In that case, we have to update LOG_LINKS of insns later
4169        in this basic block.  Note that this (expensive) case is rare.
4170
4171        Also, in this case, we must pretend that all REG_NOTEs for I2
4172        actually came from I3, so that REG_UNUSED notes from I2 will be
4173        properly handled.  */
4174
4175     if (i3_subst_into_i2)
4176       {
4177         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4178           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4179                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4180               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4181               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4182               && ! find_reg_note (i2, REG_UNUSED,
4183                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4184             for (temp = NEXT_INSN (i2);
4185                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4186                           || BB_HEAD (this_basic_block) != temp);
4187                  temp = NEXT_INSN (temp))
4188               if (temp != i3 && INSN_P (temp))
4189                 FOR_EACH_LOG_LINK (link, temp)
4190                   if (link->insn == i2)
4191                     link->insn = i3;
4192
4193         if (i3notes)
4194           {
4195             rtx link = i3notes;
4196             while (XEXP (link, 1))
4197               link = XEXP (link, 1);
4198             XEXP (link, 1) = i2notes;
4199           }
4200         else
4201           i3notes = i2notes;
4202         i2notes = 0;
4203       }
4204
4205     LOG_LINKS (i3) = NULL;
4206     REG_NOTES (i3) = 0;
4207     LOG_LINKS (i2) = NULL;
4208     REG_NOTES (i2) = 0;
4209
4210     if (newi2pat)
4211       {
4212         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4213           propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4214         INSN_CODE (i2) = i2_code_number;
4215         PATTERN (i2) = newi2pat;
4216       }
4217     else
4218       {
4219         if (MAY_HAVE_DEBUG_INSNS && i2src)
4220           propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4221         SET_INSN_DELETED (i2);
4222       }
4223
4224     if (i1)
4225       {
4226         LOG_LINKS (i1) = NULL;
4227         REG_NOTES (i1) = 0;
4228         if (MAY_HAVE_DEBUG_INSNS)
4229           propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4230         SET_INSN_DELETED (i1);
4231       }
4232
4233     if (i0)
4234       {
4235         LOG_LINKS (i0) = NULL;
4236         REG_NOTES (i0) = 0;
4237         if (MAY_HAVE_DEBUG_INSNS)
4238           propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4239         SET_INSN_DELETED (i0);
4240       }
4241
4242     /* Get death notes for everything that is now used in either I3 or
4243        I2 and used to die in a previous insn.  If we built two new
4244        patterns, move from I1 to I2 then I2 to I3 so that we get the
4245        proper movement on registers that I2 modifies.  */
4246
4247     if (i0)
4248       from_luid = DF_INSN_LUID (i0);
4249     else if (i1)
4250       from_luid = DF_INSN_LUID (i1);
4251     else
4252       from_luid = DF_INSN_LUID (i2);
4253     if (newi2pat)
4254       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4255     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4256
4257     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4258     if (i3notes)
4259       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4260                         elim_i2, elim_i1, elim_i0);
4261     if (i2notes)
4262       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4263                         elim_i2, elim_i1, elim_i0);
4264     if (i1notes)
4265       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4266                         elim_i2, elim_i1, elim_i0);
4267     if (i0notes)
4268       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4269                         elim_i2, elim_i1, elim_i0);
4270     if (midnotes)
4271       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4272                         elim_i2, elim_i1, elim_i0);
4273
4274     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4275        know these are REG_UNUSED and want them to go to the desired insn,
4276        so we always pass it as i3.  */
4277
4278     if (newi2pat && new_i2_notes)
4279       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4280                         NULL_RTX);
4281
4282     if (new_i3_notes)
4283       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4284                         NULL_RTX);
4285
4286     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4287        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4288        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4289        in that case, it might delete I2.  Similarly for I2 and I1.
4290        Show an additional death due to the REG_DEAD note we make here.  If
4291        we discard it in distribute_notes, we will decrement it again.  */
4292
4293     if (i3dest_killed)
4294       {
4295         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4296           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4297                                             NULL_RTX),
4298                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4299         else
4300           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4301                                             NULL_RTX),
4302                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4303                             elim_i2, elim_i1, elim_i0);
4304       }
4305
4306     if (i2dest_in_i2src)
4307       {
4308         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4309         if (newi2pat && reg_set_p (i2dest, newi2pat))
4310           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4311                             NULL_RTX, NULL_RTX);
4312         else
4313           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4314                             NULL_RTX, NULL_RTX, NULL_RTX);
4315       }
4316
4317     if (i1dest_in_i1src)
4318       {
4319         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4320         if (newi2pat && reg_set_p (i1dest, newi2pat))
4321           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4322                             NULL_RTX, NULL_RTX);
4323         else
4324           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4325                             NULL_RTX, NULL_RTX, NULL_RTX);
4326       }
4327
4328     if (i0dest_in_i0src)
4329       {
4330         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4331         if (newi2pat && reg_set_p (i0dest, newi2pat))
4332           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4333                             NULL_RTX, NULL_RTX);
4334         else
4335           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4336                             NULL_RTX, NULL_RTX, NULL_RTX);
4337       }
4338
4339     distribute_links (i3links);
4340     distribute_links (i2links);
4341     distribute_links (i1links);
4342     distribute_links (i0links);
4343
4344     if (REG_P (i2dest))
4345       {
4346         struct insn_link *link;
4347         rtx i2_insn = 0, i2_val = 0, set;
4348
4349         /* The insn that used to set this register doesn't exist, and
4350            this life of the register may not exist either.  See if one of
4351            I3's links points to an insn that sets I2DEST.  If it does,
4352            that is now the last known value for I2DEST. If we don't update
4353            this and I2 set the register to a value that depended on its old
4354            contents, we will get confused.  If this insn is used, thing
4355            will be set correctly in combine_instructions.  */
4356         FOR_EACH_LOG_LINK (link, i3)
4357           if ((set = single_set (link->insn)) != 0
4358               && rtx_equal_p (i2dest, SET_DEST (set)))
4359             i2_insn = link->insn, i2_val = SET_SRC (set);
4360
4361         record_value_for_reg (i2dest, i2_insn, i2_val);
4362
4363         /* If the reg formerly set in I2 died only once and that was in I3,
4364            zero its use count so it won't make `reload' do any work.  */
4365         if (! added_sets_2
4366             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4367             && ! i2dest_in_i2src)
4368           INC_REG_N_SETS (REGNO (i2dest), -1);
4369       }
4370
4371     if (i1 && REG_P (i1dest))
4372       {
4373         struct insn_link *link;
4374         rtx i1_insn = 0, i1_val = 0, set;
4375
4376         FOR_EACH_LOG_LINK (link, i3)
4377           if ((set = single_set (link->insn)) != 0
4378               && rtx_equal_p (i1dest, SET_DEST (set)))
4379             i1_insn = link->insn, i1_val = SET_SRC (set);
4380
4381         record_value_for_reg (i1dest, i1_insn, i1_val);
4382
4383         if (! added_sets_1 && ! i1dest_in_i1src)
4384           INC_REG_N_SETS (REGNO (i1dest), -1);
4385       }
4386
4387     if (i0 && REG_P (i0dest))
4388       {
4389         struct insn_link *link;
4390         rtx i0_insn = 0, i0_val = 0, set;
4391
4392         FOR_EACH_LOG_LINK (link, i3)
4393           if ((set = single_set (link->insn)) != 0
4394               && rtx_equal_p (i0dest, SET_DEST (set)))
4395             i0_insn = link->insn, i0_val = SET_SRC (set);
4396
4397         record_value_for_reg (i0dest, i0_insn, i0_val);
4398
4399         if (! added_sets_0 && ! i0dest_in_i0src)
4400           INC_REG_N_SETS (REGNO (i0dest), -1);
4401       }
4402
4403     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4404        been made to this insn.  The order of
4405        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4406        can affect nonzero_bits of newpat */
4407     if (newi2pat)
4408       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4409     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4410   }
4411
4412   if (undobuf.other_insn != NULL_RTX)
4413     {
4414       if (dump_file)
4415         {
4416           fprintf (dump_file, "modifying other_insn ");
4417           dump_insn_slim (dump_file, undobuf.other_insn);
4418         }
4419       df_insn_rescan (undobuf.other_insn);
4420     }
4421
4422   if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4423     {
4424       if (dump_file)
4425         {
4426           fprintf (dump_file, "modifying insn i1 ");
4427           dump_insn_slim (dump_file, i0);
4428         }
4429       df_insn_rescan (i0);
4430     }
4431
4432   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4433     {
4434       if (dump_file)
4435         {
4436           fprintf (dump_file, "modifying insn i1 ");
4437           dump_insn_slim (dump_file, i1);
4438         }
4439       df_insn_rescan (i1);
4440     }
4441
4442   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4443     {
4444       if (dump_file)
4445         {
4446           fprintf (dump_file, "modifying insn i2 ");
4447           dump_insn_slim (dump_file, i2);
4448         }
4449       df_insn_rescan (i2);
4450     }
4451
4452   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4453     {
4454       if (dump_file)
4455         {
4456           fprintf (dump_file, "modifying insn i3 ");
4457           dump_insn_slim (dump_file, i3);
4458         }
4459       df_insn_rescan (i3);
4460     }
4461
4462   /* Set new_direct_jump_p if a new return or simple jump instruction
4463      has been created.  Adjust the CFG accordingly.  */
4464
4465   if (returnjump_p (i3) || any_uncondjump_p (i3))
4466     {
4467       *new_direct_jump_p = 1;
4468       mark_jump_label (PATTERN (i3), i3, 0);
4469       update_cfg_for_uncondjump (i3);
4470     }
4471
4472   if (undobuf.other_insn != NULL_RTX
4473       && (returnjump_p (undobuf.other_insn)
4474           || any_uncondjump_p (undobuf.other_insn)))
4475     {
4476       *new_direct_jump_p = 1;
4477       update_cfg_for_uncondjump (undobuf.other_insn);
4478     }
4479
4480   /* A noop might also need cleaning up of CFG, if it comes from the
4481      simplification of a jump.  */
4482   if (JUMP_P (i3)
4483       && GET_CODE (newpat) == SET
4484       && SET_SRC (newpat) == pc_rtx
4485       && SET_DEST (newpat) == pc_rtx)
4486     {
4487       *new_direct_jump_p = 1;
4488       update_cfg_for_uncondjump (i3);
4489     }
4490
4491   if (undobuf.other_insn != NULL_RTX
4492       && JUMP_P (undobuf.other_insn)
4493       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4494       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4495       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4496     {
4497       *new_direct_jump_p = 1;
4498       update_cfg_for_uncondjump (undobuf.other_insn);
4499     }
4500
4501   combine_successes++;
4502   undo_commit ();
4503
4504   if (added_links_insn
4505       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4506       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4507     return added_links_insn;
4508   else
4509     return newi2pat ? i2 : i3;
4510 }
4511 \f
4512 /* Undo all the modifications recorded in undobuf.  */
4513
4514 static void
4515 undo_all (void)
4516 {
4517   struct undo *undo, *next;
4518
4519   for (undo = undobuf.undos; undo; undo = next)
4520     {
4521       next = undo->next;
4522       switch (undo->kind)
4523         {
4524         case UNDO_RTX:
4525           *undo->where.r = undo->old_contents.r;
4526           break;
4527         case UNDO_INT:
4528           *undo->where.i = undo->old_contents.i;
4529           break;
4530         case UNDO_MODE:
4531           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4532           break;
4533         case UNDO_LINKS:
4534           *undo->where.l = undo->old_contents.l;
4535           break;
4536         default:
4537           gcc_unreachable ();
4538         }
4539
4540       undo->next = undobuf.frees;
4541       undobuf.frees = undo;
4542     }
4543
4544   undobuf.undos = 0;
4545 }
4546
4547 /* We've committed to accepting the changes we made.  Move all
4548    of the undos to the free list.  */
4549
4550 static void
4551 undo_commit (void)
4552 {
4553   struct undo *undo, *next;
4554
4555   for (undo = undobuf.undos; undo; undo = next)
4556     {
4557       next = undo->next;
4558       undo->next = undobuf.frees;
4559       undobuf.frees = undo;
4560     }
4561   undobuf.undos = 0;
4562 }
4563 \f
4564 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4565    where we have an arithmetic expression and return that point.  LOC will
4566    be inside INSN.
4567
4568    try_combine will call this function to see if an insn can be split into
4569    two insns.  */
4570
4571 static rtx *
4572 find_split_point (rtx *loc, rtx insn, bool set_src)
4573 {
4574   rtx x = *loc;
4575   enum rtx_code code = GET_CODE (x);
4576   rtx *split;
4577   unsigned HOST_WIDE_INT len = 0;
4578   HOST_WIDE_INT pos = 0;
4579   int unsignedp = 0;
4580   rtx inner = NULL_RTX;
4581
4582   /* First special-case some codes.  */
4583   switch (code)
4584     {
4585     case SUBREG:
4586 #ifdef INSN_SCHEDULING
4587       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4588          point.  */
4589       if (MEM_P (SUBREG_REG (x)))
4590         return loc;
4591 #endif
4592       return find_split_point (&SUBREG_REG (x), insn, false);
4593
4594     case MEM:
4595 #ifdef HAVE_lo_sum
4596       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4597          using LO_SUM and HIGH.  */
4598       if (GET_CODE (XEXP (x, 0)) == CONST
4599           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4600         {
4601           enum machine_mode address_mode
4602             = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4603
4604           SUBST (XEXP (x, 0),
4605                  gen_rtx_LO_SUM (address_mode,
4606                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4607                                  XEXP (x, 0)));
4608           return &XEXP (XEXP (x, 0), 0);
4609         }
4610 #endif
4611
4612       /* If we have a PLUS whose second operand is a constant and the
4613          address is not valid, perhaps will can split it up using
4614          the machine-specific way to split large constants.  We use
4615          the first pseudo-reg (one of the virtual regs) as a placeholder;
4616          it will not remain in the result.  */
4617       if (GET_CODE (XEXP (x, 0)) == PLUS
4618           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4619           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4620                                             MEM_ADDR_SPACE (x)))
4621         {
4622           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4623           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4624                                                       XEXP (x, 0)),
4625                                          subst_insn);
4626
4627           /* This should have produced two insns, each of which sets our
4628              placeholder.  If the source of the second is a valid address,
4629              we can make put both sources together and make a split point
4630              in the middle.  */
4631
4632           if (seq
4633               && NEXT_INSN (seq) != NULL_RTX
4634               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4635               && NONJUMP_INSN_P (seq)
4636               && GET_CODE (PATTERN (seq)) == SET
4637               && SET_DEST (PATTERN (seq)) == reg
4638               && ! reg_mentioned_p (reg,
4639                                     SET_SRC (PATTERN (seq)))
4640               && NONJUMP_INSN_P (NEXT_INSN (seq))
4641               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4642               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4643               && memory_address_addr_space_p
4644                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4645                     MEM_ADDR_SPACE (x)))
4646             {
4647               rtx src1 = SET_SRC (PATTERN (seq));
4648               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4649
4650               /* Replace the placeholder in SRC2 with SRC1.  If we can
4651                  find where in SRC2 it was placed, that can become our
4652                  split point and we can replace this address with SRC2.
4653                  Just try two obvious places.  */
4654
4655               src2 = replace_rtx (src2, reg, src1);
4656               split = 0;
4657               if (XEXP (src2, 0) == src1)
4658                 split = &XEXP (src2, 0);
4659               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4660                        && XEXP (XEXP (src2, 0), 0) == src1)
4661                 split = &XEXP (XEXP (src2, 0), 0);
4662
4663               if (split)
4664                 {
4665                   SUBST (XEXP (x, 0), src2);
4666                   return split;
4667                 }
4668             }
4669
4670           /* If that didn't work, perhaps the first operand is complex and
4671              needs to be computed separately, so make a split point there.
4672              This will occur on machines that just support REG + CONST
4673              and have a constant moved through some previous computation.  */
4674
4675           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4676                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4677                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4678             return &XEXP (XEXP (x, 0), 0);
4679         }
4680
4681       /* If we have a PLUS whose first operand is complex, try computing it
4682          separately by making a split there.  */
4683       if (GET_CODE (XEXP (x, 0)) == PLUS
4684           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4685                                             MEM_ADDR_SPACE (x))
4686           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4687           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4688                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4689         return &XEXP (XEXP (x, 0), 0);
4690       break;
4691
4692     case SET:
4693 #ifdef HAVE_cc0
4694       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4695          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4696          we need to put the operand into a register.  So split at that
4697          point.  */
4698
4699       if (SET_DEST (x) == cc0_rtx
4700           && GET_CODE (SET_SRC (x)) != COMPARE
4701           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4702           && !OBJECT_P (SET_SRC (x))
4703           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4704                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4705         return &SET_SRC (x);
4706 #endif
4707
4708       /* See if we can split SET_SRC as it stands.  */
4709       split = find_split_point (&SET_SRC (x), insn, true);
4710       if (split && split != &SET_SRC (x))
4711         return split;
4712
4713       /* See if we can split SET_DEST as it stands.  */
4714       split = find_split_point (&SET_DEST (x), insn, false);
4715       if (split && split != &SET_DEST (x))
4716         return split;
4717
4718       /* See if this is a bitfield assignment with everything constant.  If
4719          so, this is an IOR of an AND, so split it into that.  */
4720       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4721           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4722           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4723           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4724           && CONST_INT_P (SET_SRC (x))
4725           && ((INTVAL (XEXP (SET_DEST (x), 1))
4726                + INTVAL (XEXP (SET_DEST (x), 2)))
4727               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4728           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4729         {
4730           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4731           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4732           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4733           rtx dest = XEXP (SET_DEST (x), 0);
4734           enum machine_mode mode = GET_MODE (dest);
4735           unsigned HOST_WIDE_INT mask
4736             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4737           rtx or_mask;
4738
4739           if (BITS_BIG_ENDIAN)
4740             pos = GET_MODE_PRECISION (mode) - len - pos;
4741
4742           or_mask = gen_int_mode (src << pos, mode);
4743           if (src == mask)
4744             SUBST (SET_SRC (x),
4745                    simplify_gen_binary (IOR, mode, dest, or_mask));
4746           else
4747             {
4748               rtx negmask = gen_int_mode (~(mask << pos), mode);
4749               SUBST (SET_SRC (x),
4750                      simplify_gen_binary (IOR, mode,
4751                                           simplify_gen_binary (AND, mode,
4752                                                                dest, negmask),
4753                                           or_mask));
4754             }
4755
4756           SUBST (SET_DEST (x), dest);
4757
4758           split = find_split_point (&SET_SRC (x), insn, true);
4759           if (split && split != &SET_SRC (x))
4760             return split;
4761         }
4762
4763       /* Otherwise, see if this is an operation that we can split into two.
4764          If so, try to split that.  */
4765       code = GET_CODE (SET_SRC (x));
4766
4767       switch (code)
4768         {
4769         case AND:
4770           /* If we are AND'ing with a large constant that is only a single
4771              bit and the result is only being used in a context where we
4772              need to know if it is zero or nonzero, replace it with a bit
4773              extraction.  This will avoid the large constant, which might
4774              have taken more than one insn to make.  If the constant were
4775              not a valid argument to the AND but took only one insn to make,
4776              this is no worse, but if it took more than one insn, it will
4777              be better.  */
4778
4779           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4780               && REG_P (XEXP (SET_SRC (x), 0))
4781               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4782               && REG_P (SET_DEST (x))
4783               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4784               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4785               && XEXP (*split, 0) == SET_DEST (x)
4786               && XEXP (*split, 1) == const0_rtx)
4787             {
4788               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4789                                                 XEXP (SET_SRC (x), 0),
4790                                                 pos, NULL_RTX, 1, 1, 0, 0);
4791               if (extraction != 0)
4792                 {
4793                   SUBST (SET_SRC (x), extraction);
4794                   return find_split_point (loc, insn, false);
4795                 }
4796             }
4797           break;
4798
4799         case NE:
4800           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4801              is known to be on, this can be converted into a NEG of a shift.  */
4802           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4803               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4804               && 1 <= (pos = exact_log2
4805                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4806                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4807             {
4808               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4809
4810               SUBST (SET_SRC (x),
4811                      gen_rtx_NEG (mode,
4812                                   gen_rtx_LSHIFTRT (mode,
4813                                                     XEXP (SET_SRC (x), 0),
4814                                                     GEN_INT (pos))));
4815
4816               split = find_split_point (&SET_SRC (x), insn, true);
4817               if (split && split != &SET_SRC (x))
4818                 return split;
4819             }
4820           break;
4821
4822         case SIGN_EXTEND:
4823           inner = XEXP (SET_SRC (x), 0);
4824
4825           /* We can't optimize if either mode is a partial integer
4826              mode as we don't know how many bits are significant
4827              in those modes.  */
4828           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4829               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4830             break;
4831
4832           pos = 0;
4833           len = GET_MODE_PRECISION (GET_MODE (inner));
4834           unsignedp = 0;
4835           break;
4836
4837         case SIGN_EXTRACT:
4838         case ZERO_EXTRACT:
4839           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4840               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4841             {
4842               inner = XEXP (SET_SRC (x), 0);
4843               len = INTVAL (XEXP (SET_SRC (x), 1));
4844               pos = INTVAL (XEXP (SET_SRC (x), 2));
4845
4846               if (BITS_BIG_ENDIAN)
4847                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4848               unsignedp = (code == ZERO_EXTRACT);
4849             }
4850           break;
4851
4852         default:
4853           break;
4854         }
4855
4856       if (len && pos >= 0
4857           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4858         {
4859           enum machine_mode mode = GET_MODE (SET_SRC (x));
4860
4861           /* For unsigned, we have a choice of a shift followed by an
4862              AND or two shifts.  Use two shifts for field sizes where the
4863              constant might be too large.  We assume here that we can
4864              always at least get 8-bit constants in an AND insn, which is
4865              true for every current RISC.  */
4866
4867           if (unsignedp && len <= 8)
4868             {
4869               SUBST (SET_SRC (x),
4870                      gen_rtx_AND (mode,
4871                                   gen_rtx_LSHIFTRT
4872                                   (mode, gen_lowpart (mode, inner),
4873                                    GEN_INT (pos)),
4874                                   GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4875                                            - 1)));
4876
4877               split = find_split_point (&SET_SRC (x), insn, true);
4878               if (split && split != &SET_SRC (x))
4879                 return split;
4880             }
4881           else
4882             {
4883               SUBST (SET_SRC (x),
4884                      gen_rtx_fmt_ee
4885                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4886                       gen_rtx_ASHIFT (mode,
4887                                       gen_lowpart (mode, inner),
4888                                       GEN_INT (GET_MODE_PRECISION (mode)
4889                                                - len - pos)),
4890                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4891
4892               split = find_split_point (&SET_SRC (x), insn, true);
4893               if (split && split != &SET_SRC (x))
4894                 return split;
4895             }
4896         }
4897
4898       /* See if this is a simple operation with a constant as the second
4899          operand.  It might be that this constant is out of range and hence
4900          could be used as a split point.  */
4901       if (BINARY_P (SET_SRC (x))
4902           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4903           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4904               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4905                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4906         return &XEXP (SET_SRC (x), 1);
4907
4908       /* Finally, see if this is a simple operation with its first operand
4909          not in a register.  The operation might require this operand in a
4910          register, so return it as a split point.  We can always do this
4911          because if the first operand were another operation, we would have
4912          already found it as a split point.  */
4913       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4914           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4915         return &XEXP (SET_SRC (x), 0);
4916
4917       return 0;
4918
4919     case AND:
4920     case IOR:
4921       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4922          it is better to write this as (not (ior A B)) so we can split it.
4923          Similarly for IOR.  */
4924       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4925         {
4926           SUBST (*loc,
4927                  gen_rtx_NOT (GET_MODE (x),
4928                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4929                                               GET_MODE (x),
4930                                               XEXP (XEXP (x, 0), 0),
4931                                               XEXP (XEXP (x, 1), 0))));
4932           return find_split_point (loc, insn, set_src);
4933         }
4934
4935       /* Many RISC machines have a large set of logical insns.  If the
4936          second operand is a NOT, put it first so we will try to split the
4937          other operand first.  */
4938       if (GET_CODE (XEXP (x, 1)) == NOT)
4939         {
4940           rtx tem = XEXP (x, 0);
4941           SUBST (XEXP (x, 0), XEXP (x, 1));
4942           SUBST (XEXP (x, 1), tem);
4943         }
4944       break;
4945
4946     case PLUS:
4947     case MINUS:
4948       /* Canonicalization can produce (minus A (mult B C)), where C is a
4949          constant.  It may be better to try splitting (plus (mult B -C) A)
4950          instead if this isn't a multiply by a power of two.  */
4951       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4952           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4953           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4954         {
4955           enum machine_mode mode = GET_MODE (x);
4956           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4957           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4958           SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4959                                                          XEXP (XEXP (x, 1), 0),
4960                                                          GEN_INT (other_int)),
4961                                      XEXP (x, 0)));
4962           return find_split_point (loc, insn, set_src);
4963         }
4964
4965       /* Split at a multiply-accumulate instruction.  However if this is
4966          the SET_SRC, we likely do not have such an instruction and it's
4967          worthless to try this split.  */
4968       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4969         return loc;
4970
4971     default:
4972       break;
4973     }
4974
4975   /* Otherwise, select our actions depending on our rtx class.  */
4976   switch (GET_RTX_CLASS (code))
4977     {
4978     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4979     case RTX_TERNARY:
4980       split = find_split_point (&XEXP (x, 2), insn, false);
4981       if (split)
4982         return split;
4983       /* ... fall through ...  */
4984     case RTX_BIN_ARITH:
4985     case RTX_COMM_ARITH:
4986     case RTX_COMPARE:
4987     case RTX_COMM_COMPARE:
4988       split = find_split_point (&XEXP (x, 1), insn, false);
4989       if (split)
4990         return split;
4991       /* ... fall through ...  */
4992     case RTX_UNARY:
4993       /* Some machines have (and (shift ...) ...) insns.  If X is not
4994          an AND, but XEXP (X, 0) is, use it as our split point.  */
4995       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4996         return &XEXP (x, 0);
4997
4998       split = find_split_point (&XEXP (x, 0), insn, false);
4999       if (split)
5000         return split;
5001       return loc;
5002
5003     default:
5004       /* Otherwise, we don't have a split point.  */
5005       return 0;
5006     }
5007 }
5008 \f
5009 /* Throughout X, replace FROM with TO, and return the result.
5010    The result is TO if X is FROM;
5011    otherwise the result is X, but its contents may have been modified.
5012    If they were modified, a record was made in undobuf so that
5013    undo_all will (among other things) return X to its original state.
5014
5015    If the number of changes necessary is too much to record to undo,
5016    the excess changes are not made, so the result is invalid.
5017    The changes already made can still be undone.
5018    undobuf.num_undo is incremented for such changes, so by testing that
5019    the caller can tell whether the result is valid.
5020
5021    `n_occurrences' is incremented each time FROM is replaced.
5022
5023    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5024
5025    IN_COND is nonzero if we are at the top level of a condition.
5026
5027    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
5028    by copying if `n_occurrences' is nonzero.  */
5029
5030 static rtx
5031 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5032 {
5033   enum rtx_code code = GET_CODE (x);
5034   enum machine_mode op0_mode = VOIDmode;
5035   const char *fmt;
5036   int len, i;
5037   rtx new_rtx;
5038
5039 /* Two expressions are equal if they are identical copies of a shared
5040    RTX or if they are both registers with the same register number
5041    and mode.  */
5042
5043 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
5044   ((X) == (Y)                                           \
5045    || (REG_P (X) && REG_P (Y)   \
5046        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5047
5048   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5049     {
5050       n_occurrences++;
5051       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5052     }
5053
5054   /* If X and FROM are the same register but different modes, they
5055      will not have been seen as equal above.  However, the log links code
5056      will make a LOG_LINKS entry for that case.  If we do nothing, we
5057      will try to rerecognize our original insn and, when it succeeds,
5058      we will delete the feeding insn, which is incorrect.
5059
5060      So force this insn not to match in this (rare) case.  */
5061   if (! in_dest && code == REG && REG_P (from)
5062       && reg_overlap_mentioned_p (x, from))
5063     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5064
5065   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5066      of which may contain things that can be combined.  */
5067   if (code != MEM && code != LO_SUM && OBJECT_P (x))
5068     return x;
5069
5070   /* It is possible to have a subexpression appear twice in the insn.
5071      Suppose that FROM is a register that appears within TO.
5072      Then, after that subexpression has been scanned once by `subst',
5073      the second time it is scanned, TO may be found.  If we were
5074      to scan TO here, we would find FROM within it and create a
5075      self-referent rtl structure which is completely wrong.  */
5076   if (COMBINE_RTX_EQUAL_P (x, to))
5077     return to;
5078
5079   /* Parallel asm_operands need special attention because all of the
5080      inputs are shared across the arms.  Furthermore, unsharing the
5081      rtl results in recognition failures.  Failure to handle this case
5082      specially can result in circular rtl.
5083
5084      Solve this by doing a normal pass across the first entry of the
5085      parallel, and only processing the SET_DESTs of the subsequent
5086      entries.  Ug.  */
5087
5088   if (code == PARALLEL
5089       && GET_CODE (XVECEXP (x, 0, 0)) == SET
5090       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5091     {
5092       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5093
5094       /* If this substitution failed, this whole thing fails.  */
5095       if (GET_CODE (new_rtx) == CLOBBER
5096           && XEXP (new_rtx, 0) == const0_rtx)
5097         return new_rtx;
5098
5099       SUBST (XVECEXP (x, 0, 0), new_rtx);
5100
5101       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5102         {
5103           rtx dest = SET_DEST (XVECEXP (x, 0, i));
5104
5105           if (!REG_P (dest)
5106               && GET_CODE (dest) != CC0
5107               && GET_CODE (dest) != PC)
5108             {
5109               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5110
5111               /* If this substitution failed, this whole thing fails.  */
5112               if (GET_CODE (new_rtx) == CLOBBER
5113                   && XEXP (new_rtx, 0) == const0_rtx)
5114                 return new_rtx;
5115
5116               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5117             }
5118         }
5119     }
5120   else
5121     {
5122       len = GET_RTX_LENGTH (code);
5123       fmt = GET_RTX_FORMAT (code);
5124
5125       /* We don't need to process a SET_DEST that is a register, CC0,
5126          or PC, so set up to skip this common case.  All other cases
5127          where we want to suppress replacing something inside a
5128          SET_SRC are handled via the IN_DEST operand.  */
5129       if (code == SET
5130           && (REG_P (SET_DEST (x))
5131               || GET_CODE (SET_DEST (x)) == CC0
5132               || GET_CODE (SET_DEST (x)) == PC))
5133         fmt = "ie";
5134
5135       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5136          constant.  */
5137       if (fmt[0] == 'e')
5138         op0_mode = GET_MODE (XEXP (x, 0));
5139
5140       for (i = 0; i < len; i++)
5141         {
5142           if (fmt[i] == 'E')
5143             {
5144               int j;
5145               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5146                 {
5147                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5148                     {
5149                       new_rtx = (unique_copy && n_occurrences
5150                              ? copy_rtx (to) : to);
5151                       n_occurrences++;
5152                     }
5153                   else
5154                     {
5155                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5156                                        unique_copy);
5157
5158                       /* If this substitution failed, this whole thing
5159                          fails.  */
5160                       if (GET_CODE (new_rtx) == CLOBBER
5161                           && XEXP (new_rtx, 0) == const0_rtx)
5162                         return new_rtx;
5163                     }
5164
5165                   SUBST (XVECEXP (x, i, j), new_rtx);
5166                 }
5167             }
5168           else if (fmt[i] == 'e')
5169             {
5170               /* If this is a register being set, ignore it.  */
5171               new_rtx = XEXP (x, i);
5172               if (in_dest
5173                   && i == 0
5174                   && (((code == SUBREG || code == ZERO_EXTRACT)
5175                        && REG_P (new_rtx))
5176                       || code == STRICT_LOW_PART))
5177                 ;
5178
5179               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5180                 {
5181                   /* In general, don't install a subreg involving two
5182                      modes not tieable.  It can worsen register
5183                      allocation, and can even make invalid reload
5184                      insns, since the reg inside may need to be copied
5185                      from in the outside mode, and that may be invalid
5186                      if it is an fp reg copied in integer mode.
5187
5188                      We allow two exceptions to this: It is valid if
5189                      it is inside another SUBREG and the mode of that
5190                      SUBREG and the mode of the inside of TO is
5191                      tieable and it is valid if X is a SET that copies
5192                      FROM to CC0.  */
5193
5194                   if (GET_CODE (to) == SUBREG
5195                       && ! MODES_TIEABLE_P (GET_MODE (to),
5196                                             GET_MODE (SUBREG_REG (to)))
5197                       && ! (code == SUBREG
5198                             && MODES_TIEABLE_P (GET_MODE (x),
5199                                                 GET_MODE (SUBREG_REG (to))))
5200 #ifdef HAVE_cc0
5201                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5202 #endif
5203                       )
5204                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5205
5206 #ifdef CANNOT_CHANGE_MODE_CLASS
5207                   if (code == SUBREG
5208                       && REG_P (to)
5209                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5210                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5211                                                    GET_MODE (to),
5212                                                    GET_MODE (x)))
5213                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5214 #endif
5215
5216                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5217                   n_occurrences++;
5218                 }
5219               else
5220                 /* If we are in a SET_DEST, suppress most cases unless we
5221                    have gone inside a MEM, in which case we want to
5222                    simplify the address.  We assume here that things that
5223                    are actually part of the destination have their inner
5224                    parts in the first expression.  This is true for SUBREG,
5225                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5226                    things aside from REG and MEM that should appear in a
5227                    SET_DEST.  */
5228                 new_rtx = subst (XEXP (x, i), from, to,
5229                              (((in_dest
5230                                 && (code == SUBREG || code == STRICT_LOW_PART
5231                                     || code == ZERO_EXTRACT))
5232                                || code == SET)
5233                               && i == 0),
5234                                  code == IF_THEN_ELSE && i == 0,
5235                                  unique_copy);
5236
5237               /* If we found that we will have to reject this combination,
5238                  indicate that by returning the CLOBBER ourselves, rather than
5239                  an expression containing it.  This will speed things up as
5240                  well as prevent accidents where two CLOBBERs are considered
5241                  to be equal, thus producing an incorrect simplification.  */
5242
5243               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5244                 return new_rtx;
5245
5246               if (GET_CODE (x) == SUBREG
5247                   && (CONST_INT_P (new_rtx)
5248                       || GET_CODE (new_rtx) == CONST_DOUBLE))
5249                 {
5250                   enum machine_mode mode = GET_MODE (x);
5251
5252                   x = simplify_subreg (GET_MODE (x), new_rtx,
5253                                        GET_MODE (SUBREG_REG (x)),
5254                                        SUBREG_BYTE (x));
5255                   if (! x)
5256                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5257                 }
5258               else if (CONST_INT_P (new_rtx)
5259                        && GET_CODE (x) == ZERO_EXTEND)
5260                 {
5261                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5262                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5263                   gcc_assert (x);
5264                 }
5265               else
5266                 SUBST (XEXP (x, i), new_rtx);
5267             }
5268         }
5269     }
5270
5271   /* Check if we are loading something from the constant pool via float
5272      extension; in this case we would undo compress_float_constant
5273      optimization and degenerate constant load to an immediate value.  */
5274   if (GET_CODE (x) == FLOAT_EXTEND
5275       && MEM_P (XEXP (x, 0))
5276       && MEM_READONLY_P (XEXP (x, 0)))
5277     {
5278       rtx tmp = avoid_constant_pool_reference (x);
5279       if (x != tmp)
5280         return x;
5281     }
5282
5283   /* Try to simplify X.  If the simplification changed the code, it is likely
5284      that further simplification will help, so loop, but limit the number
5285      of repetitions that will be performed.  */
5286
5287   for (i = 0; i < 4; i++)
5288     {
5289       /* If X is sufficiently simple, don't bother trying to do anything
5290          with it.  */
5291       if (code != CONST_INT && code != REG && code != CLOBBER)
5292         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5293
5294       if (GET_CODE (x) == code)
5295         break;
5296
5297       code = GET_CODE (x);
5298
5299       /* We no longer know the original mode of operand 0 since we
5300          have changed the form of X)  */
5301       op0_mode = VOIDmode;
5302     }
5303
5304   return x;
5305 }
5306 \f
5307 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5308    outer level; call `subst' to simplify recursively.  Return the new
5309    expression.
5310
5311    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5312    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5313    of a condition.  */
5314
5315 static rtx
5316 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5317                       int in_cond)
5318 {
5319   enum rtx_code code = GET_CODE (x);
5320   enum machine_mode mode = GET_MODE (x);
5321   rtx temp;
5322   int i;
5323
5324   /* If this is a commutative operation, put a constant last and a complex
5325      expression first.  We don't need to do this for comparisons here.  */
5326   if (COMMUTATIVE_ARITH_P (x)
5327       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5328     {
5329       temp = XEXP (x, 0);
5330       SUBST (XEXP (x, 0), XEXP (x, 1));
5331       SUBST (XEXP (x, 1), temp);
5332     }
5333
5334   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5335      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5336      things.  Check for cases where both arms are testing the same
5337      condition.
5338
5339      Don't do anything if all operands are very simple.  */
5340
5341   if ((BINARY_P (x)
5342        && ((!OBJECT_P (XEXP (x, 0))
5343             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5344                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5345            || (!OBJECT_P (XEXP (x, 1))
5346                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5347                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5348       || (UNARY_P (x)
5349           && (!OBJECT_P (XEXP (x, 0))
5350                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5351                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5352     {
5353       rtx cond, true_rtx, false_rtx;
5354
5355       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5356       if (cond != 0
5357           /* If everything is a comparison, what we have is highly unlikely
5358              to be simpler, so don't use it.  */
5359           && ! (COMPARISON_P (x)
5360                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5361         {
5362           rtx cop1 = const0_rtx;
5363           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5364
5365           if (cond_code == NE && COMPARISON_P (cond))
5366             return x;
5367
5368           /* Simplify the alternative arms; this may collapse the true and
5369              false arms to store-flag values.  Be careful to use copy_rtx
5370              here since true_rtx or false_rtx might share RTL with x as a
5371              result of the if_then_else_cond call above.  */
5372           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5373           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5374
5375           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5376              is unlikely to be simpler.  */
5377           if (general_operand (true_rtx, VOIDmode)
5378               && general_operand (false_rtx, VOIDmode))
5379             {
5380               enum rtx_code reversed;
5381
5382               /* Restarting if we generate a store-flag expression will cause
5383                  us to loop.  Just drop through in this case.  */
5384
5385               /* If the result values are STORE_FLAG_VALUE and zero, we can
5386                  just make the comparison operation.  */
5387               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5388                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5389                                              cond, cop1);
5390               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5391                        && ((reversed = reversed_comparison_code_parts
5392                                         (cond_code, cond, cop1, NULL))
5393                            != UNKNOWN))
5394                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5395                                              cond, cop1);
5396
5397               /* Likewise, we can make the negate of a comparison operation
5398                  if the result values are - STORE_FLAG_VALUE and zero.  */
5399               else if (CONST_INT_P (true_rtx)
5400                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5401                        && false_rtx == const0_rtx)
5402                 x = simplify_gen_unary (NEG, mode,
5403                                         simplify_gen_relational (cond_code,
5404                                                                  mode, VOIDmode,
5405                                                                  cond, cop1),
5406                                         mode);
5407               else if (CONST_INT_P (false_rtx)
5408                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5409                        && true_rtx == const0_rtx
5410                        && ((reversed = reversed_comparison_code_parts
5411                                         (cond_code, cond, cop1, NULL))
5412                            != UNKNOWN))
5413                 x = simplify_gen_unary (NEG, mode,
5414                                         simplify_gen_relational (reversed,
5415                                                                  mode, VOIDmode,
5416                                                                  cond, cop1),
5417                                         mode);
5418               else
5419                 return gen_rtx_IF_THEN_ELSE (mode,
5420                                              simplify_gen_relational (cond_code,
5421                                                                       mode,
5422                                                                       VOIDmode,
5423                                                                       cond,
5424                                                                       cop1),
5425                                              true_rtx, false_rtx);
5426
5427               code = GET_CODE (x);
5428               op0_mode = VOIDmode;
5429             }
5430         }
5431     }
5432
5433   /* Try to fold this expression in case we have constants that weren't
5434      present before.  */
5435   temp = 0;
5436   switch (GET_RTX_CLASS (code))
5437     {
5438     case RTX_UNARY:
5439       if (op0_mode == VOIDmode)
5440         op0_mode = GET_MODE (XEXP (x, 0));
5441       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5442       break;
5443     case RTX_COMPARE:
5444     case RTX_COMM_COMPARE:
5445       {
5446         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5447         if (cmp_mode == VOIDmode)
5448           {
5449             cmp_mode = GET_MODE (XEXP (x, 1));
5450             if (cmp_mode == VOIDmode)
5451               cmp_mode = op0_mode;
5452           }
5453         temp = simplify_relational_operation (code, mode, cmp_mode,
5454                                               XEXP (x, 0), XEXP (x, 1));
5455       }
5456       break;
5457     case RTX_COMM_ARITH:
5458     case RTX_BIN_ARITH:
5459       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5460       break;
5461     case RTX_BITFIELD_OPS:
5462     case RTX_TERNARY:
5463       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5464                                          XEXP (x, 1), XEXP (x, 2));
5465       break;
5466     default:
5467       break;
5468     }
5469
5470   if (temp)
5471     {
5472       x = temp;
5473       code = GET_CODE (temp);
5474       op0_mode = VOIDmode;
5475       mode = GET_MODE (temp);
5476     }
5477
5478   /* First see if we can apply the inverse distributive law.  */
5479   if (code == PLUS || code == MINUS
5480       || code == AND || code == IOR || code == XOR)
5481     {
5482       x = apply_distributive_law (x);
5483       code = GET_CODE (x);
5484       op0_mode = VOIDmode;
5485     }
5486
5487   /* If CODE is an associative operation not otherwise handled, see if we
5488      can associate some operands.  This can win if they are constants or
5489      if they are logically related (i.e. (a & b) & a).  */
5490   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5491        || code == AND || code == IOR || code == XOR
5492        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5493       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5494           || (flag_associative_math && FLOAT_MODE_P (mode))))
5495     {
5496       if (GET_CODE (XEXP (x, 0)) == code)
5497         {
5498           rtx other = XEXP (XEXP (x, 0), 0);
5499           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5500           rtx inner_op1 = XEXP (x, 1);
5501           rtx inner;
5502
5503           /* Make sure we pass the constant operand if any as the second
5504              one if this is a commutative operation.  */
5505           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5506             {
5507               rtx tem = inner_op0;
5508               inner_op0 = inner_op1;
5509               inner_op1 = tem;
5510             }
5511           inner = simplify_binary_operation (code == MINUS ? PLUS
5512                                              : code == DIV ? MULT
5513                                              : code,
5514                                              mode, inner_op0, inner_op1);
5515
5516           /* For commutative operations, try the other pair if that one
5517              didn't simplify.  */
5518           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5519             {
5520               other = XEXP (XEXP (x, 0), 1);
5521               inner = simplify_binary_operation (code, mode,
5522                                                  XEXP (XEXP (x, 0), 0),
5523                                                  XEXP (x, 1));
5524             }
5525
5526           if (inner)
5527             return simplify_gen_binary (code, mode, other, inner);
5528         }
5529     }
5530
5531   /* A little bit of algebraic simplification here.  */
5532   switch (code)
5533     {
5534     case MEM:
5535       /* Ensure that our address has any ASHIFTs converted to MULT in case
5536          address-recognizing predicates are called later.  */
5537       temp = make_compound_operation (XEXP (x, 0), MEM);
5538       SUBST (XEXP (x, 0), temp);
5539       break;
5540
5541     case SUBREG:
5542       if (op0_mode == VOIDmode)
5543         op0_mode = GET_MODE (SUBREG_REG (x));
5544
5545       /* See if this can be moved to simplify_subreg.  */
5546       if (CONSTANT_P (SUBREG_REG (x))
5547           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5548              /* Don't call gen_lowpart if the inner mode
5549                 is VOIDmode and we cannot simplify it, as SUBREG without
5550                 inner mode is invalid.  */
5551           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5552               || gen_lowpart_common (mode, SUBREG_REG (x))))
5553         return gen_lowpart (mode, SUBREG_REG (x));
5554
5555       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5556         break;
5557       {
5558         rtx temp;
5559         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5560                                 SUBREG_BYTE (x));
5561         if (temp)
5562           return temp;
5563       }
5564
5565       /* Don't change the mode of the MEM if that would change the meaning
5566          of the address.  */
5567       if (MEM_P (SUBREG_REG (x))
5568           && (MEM_VOLATILE_P (SUBREG_REG (x))
5569               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5570         return gen_rtx_CLOBBER (mode, const0_rtx);
5571
5572       /* Note that we cannot do any narrowing for non-constants since
5573          we might have been counting on using the fact that some bits were
5574          zero.  We now do this in the SET.  */
5575
5576       break;
5577
5578     case NEG:
5579       temp = expand_compound_operation (XEXP (x, 0));
5580
5581       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5582          replaced by (lshiftrt X C).  This will convert
5583          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5584
5585       if (GET_CODE (temp) == ASHIFTRT
5586           && CONST_INT_P (XEXP (temp, 1))
5587           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5588         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5589                                      INTVAL (XEXP (temp, 1)));
5590
5591       /* If X has only a single bit that might be nonzero, say, bit I, convert
5592          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5593          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5594          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5595          or a SUBREG of one since we'd be making the expression more
5596          complex if it was just a register.  */
5597
5598       if (!REG_P (temp)
5599           && ! (GET_CODE (temp) == SUBREG
5600                 && REG_P (SUBREG_REG (temp)))
5601           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5602         {
5603           rtx temp1 = simplify_shift_const
5604             (NULL_RTX, ASHIFTRT, mode,
5605              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5606                                    GET_MODE_PRECISION (mode) - 1 - i),
5607              GET_MODE_PRECISION (mode) - 1 - i);
5608
5609           /* If all we did was surround TEMP with the two shifts, we
5610              haven't improved anything, so don't use it.  Otherwise,
5611              we are better off with TEMP1.  */
5612           if (GET_CODE (temp1) != ASHIFTRT
5613               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5614               || XEXP (XEXP (temp1, 0), 0) != temp)
5615             return temp1;
5616         }
5617       break;
5618
5619     case TRUNCATE:
5620       /* We can't handle truncation to a partial integer mode here
5621          because we don't know the real bitsize of the partial
5622          integer mode.  */
5623       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5624         break;
5625
5626       if (HWI_COMPUTABLE_MODE_P (mode))
5627         SUBST (XEXP (x, 0),
5628                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5629                               GET_MODE_MASK (mode), 0));
5630
5631       /* We can truncate a constant value and return it.  */
5632       if (CONST_INT_P (XEXP (x, 0)))
5633         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5634
5635       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5636          whose value is a comparison can be replaced with a subreg if
5637          STORE_FLAG_VALUE permits.  */
5638       if (HWI_COMPUTABLE_MODE_P (mode)
5639           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5640           && (temp = get_last_value (XEXP (x, 0)))
5641           && COMPARISON_P (temp))
5642         return gen_lowpart (mode, XEXP (x, 0));
5643       break;
5644
5645     case CONST:
5646       /* (const (const X)) can become (const X).  Do it this way rather than
5647          returning the inner CONST since CONST can be shared with a
5648          REG_EQUAL note.  */
5649       if (GET_CODE (XEXP (x, 0)) == CONST)
5650         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5651       break;
5652
5653 #ifdef HAVE_lo_sum
5654     case LO_SUM:
5655       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5656          can add in an offset.  find_split_point will split this address up
5657          again if it doesn't match.  */
5658       if (GET_CODE (XEXP (x, 0)) == HIGH
5659           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5660         return XEXP (x, 1);
5661       break;
5662 #endif
5663
5664     case PLUS:
5665       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5666          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5667          bit-field and can be replaced by either a sign_extend or a
5668          sign_extract.  The `and' may be a zero_extend and the two
5669          <c>, -<c> constants may be reversed.  */
5670       if (GET_CODE (XEXP (x, 0)) == XOR
5671           && CONST_INT_P (XEXP (x, 1))
5672           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5673           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5674           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5675               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5676           && HWI_COMPUTABLE_MODE_P (mode)
5677           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5678                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5679                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5680                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5681               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5682                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5683                       == (unsigned int) i + 1))))
5684         return simplify_shift_const
5685           (NULL_RTX, ASHIFTRT, mode,
5686            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5687                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5688                                  GET_MODE_PRECISION (mode) - (i + 1)),
5689            GET_MODE_PRECISION (mode) - (i + 1));
5690
5691       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5692          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5693          the bitsize of the mode - 1.  This allows simplification of
5694          "a = (b & 8) == 0;"  */
5695       if (XEXP (x, 1) == constm1_rtx
5696           && !REG_P (XEXP (x, 0))
5697           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5698                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5699           && nonzero_bits (XEXP (x, 0), mode) == 1)
5700         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5701            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5702                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5703                                  GET_MODE_PRECISION (mode) - 1),
5704            GET_MODE_PRECISION (mode) - 1);
5705
5706       /* If we are adding two things that have no bits in common, convert
5707          the addition into an IOR.  This will often be further simplified,
5708          for example in cases like ((a & 1) + (a & 2)), which can
5709          become a & 3.  */
5710
5711       if (HWI_COMPUTABLE_MODE_P (mode)
5712           && (nonzero_bits (XEXP (x, 0), mode)
5713               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5714         {
5715           /* Try to simplify the expression further.  */
5716           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5717           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5718
5719           /* If we could, great.  If not, do not go ahead with the IOR
5720              replacement, since PLUS appears in many special purpose
5721              address arithmetic instructions.  */
5722           if (GET_CODE (temp) != CLOBBER
5723               && (GET_CODE (temp) != IOR
5724                   || ((XEXP (temp, 0) != XEXP (x, 0)
5725                        || XEXP (temp, 1) != XEXP (x, 1))
5726                       && (XEXP (temp, 0) != XEXP (x, 1)
5727                           || XEXP (temp, 1) != XEXP (x, 0)))))
5728             return temp;
5729         }
5730       break;
5731
5732     case MINUS:
5733       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5734          (and <foo> (const_int pow2-1))  */
5735       if (GET_CODE (XEXP (x, 1)) == AND
5736           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5737           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5738           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5739         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5740                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5741       break;
5742
5743     case MULT:
5744       /* If we have (mult (plus A B) C), apply the distributive law and then
5745          the inverse distributive law to see if things simplify.  This
5746          occurs mostly in addresses, often when unrolling loops.  */
5747
5748       if (GET_CODE (XEXP (x, 0)) == PLUS)
5749         {
5750           rtx result = distribute_and_simplify_rtx (x, 0);
5751           if (result)
5752             return result;
5753         }
5754
5755       /* Try simplify a*(b/c) as (a*b)/c.  */
5756       if (FLOAT_MODE_P (mode) && flag_associative_math
5757           && GET_CODE (XEXP (x, 0)) == DIV)
5758         {
5759           rtx tem = simplify_binary_operation (MULT, mode,
5760                                                XEXP (XEXP (x, 0), 0),
5761                                                XEXP (x, 1));
5762           if (tem)
5763             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5764         }
5765       break;
5766
5767     case UDIV:
5768       /* If this is a divide by a power of two, treat it as a shift if
5769          its first operand is a shift.  */
5770       if (CONST_INT_P (XEXP (x, 1))
5771           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5772           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5773               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5774               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5775               || GET_CODE (XEXP (x, 0)) == ROTATE
5776               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5777         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5778       break;
5779
5780     case EQ:  case NE:
5781     case GT:  case GTU:  case GE:  case GEU:
5782     case LT:  case LTU:  case LE:  case LEU:
5783     case UNEQ:  case LTGT:
5784     case UNGT:  case UNGE:
5785     case UNLT:  case UNLE:
5786     case UNORDERED: case ORDERED:
5787       /* If the first operand is a condition code, we can't do anything
5788          with it.  */
5789       if (GET_CODE (XEXP (x, 0)) == COMPARE
5790           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5791               && ! CC0_P (XEXP (x, 0))))
5792         {
5793           rtx op0 = XEXP (x, 0);
5794           rtx op1 = XEXP (x, 1);
5795           enum rtx_code new_code;
5796
5797           if (GET_CODE (op0) == COMPARE)
5798             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5799
5800           /* Simplify our comparison, if possible.  */
5801           new_code = simplify_comparison (code, &op0, &op1);
5802
5803           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5804              if only the low-order bit is possibly nonzero in X (such as when
5805              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5806              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5807              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5808              (plus X 1).
5809
5810              Remove any ZERO_EXTRACT we made when thinking this was a
5811              comparison.  It may now be simpler to use, e.g., an AND.  If a
5812              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5813              the call to make_compound_operation in the SET case.
5814
5815              Don't apply these optimizations if the caller would
5816              prefer a comparison rather than a value.
5817              E.g., for the condition in an IF_THEN_ELSE most targets need
5818              an explicit comparison.  */
5819
5820           if (in_cond)
5821             ;
5822
5823           else if (STORE_FLAG_VALUE == 1
5824               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5825               && op1 == const0_rtx
5826               && mode == GET_MODE (op0)
5827               && nonzero_bits (op0, mode) == 1)
5828             return gen_lowpart (mode,
5829                                 expand_compound_operation (op0));
5830
5831           else if (STORE_FLAG_VALUE == 1
5832                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5833                    && op1 == const0_rtx
5834                    && mode == GET_MODE (op0)
5835                    && (num_sign_bit_copies (op0, mode)
5836                        == GET_MODE_PRECISION (mode)))
5837             {
5838               op0 = expand_compound_operation (op0);
5839               return simplify_gen_unary (NEG, mode,
5840                                          gen_lowpart (mode, op0),
5841                                          mode);
5842             }
5843
5844           else if (STORE_FLAG_VALUE == 1
5845                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5846                    && op1 == const0_rtx
5847                    && mode == GET_MODE (op0)
5848                    && nonzero_bits (op0, mode) == 1)
5849             {
5850               op0 = expand_compound_operation (op0);
5851               return simplify_gen_binary (XOR, mode,
5852                                           gen_lowpart (mode, op0),
5853                                           const1_rtx);
5854             }
5855
5856           else if (STORE_FLAG_VALUE == 1
5857                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5858                    && op1 == const0_rtx
5859                    && mode == GET_MODE (op0)
5860                    && (num_sign_bit_copies (op0, mode)
5861                        == GET_MODE_PRECISION (mode)))
5862             {
5863               op0 = expand_compound_operation (op0);
5864               return plus_constant (gen_lowpart (mode, op0), 1);
5865             }
5866
5867           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5868              those above.  */
5869           if (in_cond)
5870             ;
5871
5872           else if (STORE_FLAG_VALUE == -1
5873               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5874               && op1 == const0_rtx
5875               && (num_sign_bit_copies (op0, mode)
5876                   == GET_MODE_PRECISION (mode)))
5877             return gen_lowpart (mode,
5878                                 expand_compound_operation (op0));
5879
5880           else if (STORE_FLAG_VALUE == -1
5881                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5882                    && op1 == const0_rtx
5883                    && mode == GET_MODE (op0)
5884                    && nonzero_bits (op0, mode) == 1)
5885             {
5886               op0 = expand_compound_operation (op0);
5887               return simplify_gen_unary (NEG, mode,
5888                                          gen_lowpart (mode, op0),
5889                                          mode);
5890             }
5891
5892           else if (STORE_FLAG_VALUE == -1
5893                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5894                    && op1 == const0_rtx
5895                    && mode == GET_MODE (op0)
5896                    && (num_sign_bit_copies (op0, mode)
5897                        == GET_MODE_PRECISION (mode)))
5898             {
5899               op0 = expand_compound_operation (op0);
5900               return simplify_gen_unary (NOT, mode,
5901                                          gen_lowpart (mode, op0),
5902                                          mode);
5903             }
5904
5905           /* If X is 0/1, (eq X 0) is X-1.  */
5906           else if (STORE_FLAG_VALUE == -1
5907                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5908                    && op1 == const0_rtx
5909                    && mode == GET_MODE (op0)
5910                    && nonzero_bits (op0, mode) == 1)
5911             {
5912               op0 = expand_compound_operation (op0);
5913               return plus_constant (gen_lowpart (mode, op0), -1);
5914             }
5915
5916           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5917              one bit that might be nonzero, we can convert (ne x 0) to
5918              (ashift x c) where C puts the bit in the sign bit.  Remove any
5919              AND with STORE_FLAG_VALUE when we are done, since we are only
5920              going to test the sign bit.  */
5921           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5922               && HWI_COMPUTABLE_MODE_P (mode)
5923               && val_signbit_p (mode, STORE_FLAG_VALUE)
5924               && op1 == const0_rtx
5925               && mode == GET_MODE (op0)
5926               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5927             {
5928               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5929                                         expand_compound_operation (op0),
5930                                         GET_MODE_PRECISION (mode) - 1 - i);
5931               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5932                 return XEXP (x, 0);
5933               else
5934                 return x;
5935             }
5936
5937           /* If the code changed, return a whole new comparison.  */
5938           if (new_code != code)
5939             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5940
5941           /* Otherwise, keep this operation, but maybe change its operands.
5942              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5943           SUBST (XEXP (x, 0), op0);
5944           SUBST (XEXP (x, 1), op1);
5945         }
5946       break;
5947
5948     case IF_THEN_ELSE:
5949       return simplify_if_then_else (x);
5950
5951     case ZERO_EXTRACT:
5952     case SIGN_EXTRACT:
5953     case ZERO_EXTEND:
5954     case SIGN_EXTEND:
5955       /* If we are processing SET_DEST, we are done.  */
5956       if (in_dest)
5957         return x;
5958
5959       return expand_compound_operation (x);
5960
5961     case SET:
5962       return simplify_set (x);
5963
5964     case AND:
5965     case IOR:
5966       return simplify_logical (x);
5967
5968     case ASHIFT:
5969     case LSHIFTRT:
5970     case ASHIFTRT:
5971     case ROTATE:
5972     case ROTATERT:
5973       /* If this is a shift by a constant amount, simplify it.  */
5974       if (CONST_INT_P (XEXP (x, 1)))
5975         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5976                                      INTVAL (XEXP (x, 1)));
5977
5978       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5979         SUBST (XEXP (x, 1),
5980                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5981                               ((unsigned HOST_WIDE_INT) 1
5982                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5983                               - 1,
5984                               0));
5985       break;
5986
5987     default:
5988       break;
5989     }
5990
5991   return x;
5992 }
5993 \f
5994 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5995
5996 static rtx
5997 simplify_if_then_else (rtx x)
5998 {
5999   enum machine_mode mode = GET_MODE (x);
6000   rtx cond = XEXP (x, 0);
6001   rtx true_rtx = XEXP (x, 1);
6002   rtx false_rtx = XEXP (x, 2);
6003   enum rtx_code true_code = GET_CODE (cond);
6004   int comparison_p = COMPARISON_P (cond);
6005   rtx temp;
6006   int i;
6007   enum rtx_code false_code;
6008   rtx reversed;
6009
6010   /* Simplify storing of the truth value.  */
6011   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6012     return simplify_gen_relational (true_code, mode, VOIDmode,
6013                                     XEXP (cond, 0), XEXP (cond, 1));
6014
6015   /* Also when the truth value has to be reversed.  */
6016   if (comparison_p
6017       && true_rtx == const0_rtx && false_rtx == const_true_rtx
6018       && (reversed = reversed_comparison (cond, mode)))
6019     return reversed;
6020
6021   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6022      in it is being compared against certain values.  Get the true and false
6023      comparisons and see if that says anything about the value of each arm.  */
6024
6025   if (comparison_p
6026       && ((false_code = reversed_comparison_code (cond, NULL))
6027           != UNKNOWN)
6028       && REG_P (XEXP (cond, 0)))
6029     {
6030       HOST_WIDE_INT nzb;
6031       rtx from = XEXP (cond, 0);
6032       rtx true_val = XEXP (cond, 1);
6033       rtx false_val = true_val;
6034       int swapped = 0;
6035
6036       /* If FALSE_CODE is EQ, swap the codes and arms.  */
6037
6038       if (false_code == EQ)
6039         {
6040           swapped = 1, true_code = EQ, false_code = NE;
6041           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6042         }
6043
6044       /* If we are comparing against zero and the expression being tested has
6045          only a single bit that might be nonzero, that is its value when it is
6046          not equal to zero.  Similarly if it is known to be -1 or 0.  */
6047
6048       if (true_code == EQ && true_val == const0_rtx
6049           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6050         {
6051           false_code = EQ;
6052           false_val = gen_int_mode (nzb, GET_MODE (from));
6053         }
6054       else if (true_code == EQ && true_val == const0_rtx
6055                && (num_sign_bit_copies (from, GET_MODE (from))
6056                    == GET_MODE_PRECISION (GET_MODE (from))))
6057         {
6058           false_code = EQ;
6059           false_val = constm1_rtx;
6060         }
6061
6062       /* Now simplify an arm if we know the value of the register in the
6063          branch and it is used in the arm.  Be careful due to the potential
6064          of locally-shared RTL.  */
6065
6066       if (reg_mentioned_p (from, true_rtx))
6067         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6068                                       from, true_val),
6069                           pc_rtx, pc_rtx, 0, 0, 0);
6070       if (reg_mentioned_p (from, false_rtx))
6071         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6072                                    from, false_val),
6073                            pc_rtx, pc_rtx, 0, 0, 0);
6074
6075       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6076       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6077
6078       true_rtx = XEXP (x, 1);
6079       false_rtx = XEXP (x, 2);
6080       true_code = GET_CODE (cond);
6081     }
6082
6083   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6084      reversed, do so to avoid needing two sets of patterns for
6085      subtract-and-branch insns.  Similarly if we have a constant in the true
6086      arm, the false arm is the same as the first operand of the comparison, or
6087      the false arm is more complicated than the true arm.  */
6088
6089   if (comparison_p
6090       && reversed_comparison_code (cond, NULL) != UNKNOWN
6091       && (true_rtx == pc_rtx
6092           || (CONSTANT_P (true_rtx)
6093               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6094           || true_rtx == const0_rtx
6095           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6096           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6097               && !OBJECT_P (false_rtx))
6098           || reg_mentioned_p (true_rtx, false_rtx)
6099           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6100     {
6101       true_code = reversed_comparison_code (cond, NULL);
6102       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6103       SUBST (XEXP (x, 1), false_rtx);
6104       SUBST (XEXP (x, 2), true_rtx);
6105
6106       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6107       cond = XEXP (x, 0);
6108
6109       /* It is possible that the conditional has been simplified out.  */
6110       true_code = GET_CODE (cond);
6111       comparison_p = COMPARISON_P (cond);
6112     }
6113
6114   /* If the two arms are identical, we don't need the comparison.  */
6115
6116   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6117     return true_rtx;
6118
6119   /* Convert a == b ? b : a to "a".  */
6120   if (true_code == EQ && ! side_effects_p (cond)
6121       && !HONOR_NANS (mode)
6122       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6123       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6124     return false_rtx;
6125   else if (true_code == NE && ! side_effects_p (cond)
6126            && !HONOR_NANS (mode)
6127            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6128            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6129     return true_rtx;
6130
6131   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6132
6133   if (GET_MODE_CLASS (mode) == MODE_INT
6134       && comparison_p
6135       && XEXP (cond, 1) == const0_rtx
6136       && GET_CODE (false_rtx) == NEG
6137       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6138       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6139       && ! side_effects_p (true_rtx))
6140     switch (true_code)
6141       {
6142       case GT:
6143       case GE:
6144         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6145       case LT:
6146       case LE:
6147         return
6148           simplify_gen_unary (NEG, mode,
6149                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6150                               mode);
6151       default:
6152         break;
6153       }
6154
6155   /* Look for MIN or MAX.  */
6156
6157   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6158       && comparison_p
6159       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6160       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6161       && ! side_effects_p (cond))
6162     switch (true_code)
6163       {
6164       case GE:
6165       case GT:
6166         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6167       case LE:
6168       case LT:
6169         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6170       case GEU:
6171       case GTU:
6172         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6173       case LEU:
6174       case LTU:
6175         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6176       default:
6177         break;
6178       }
6179
6180   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6181      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6182      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6183      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6184      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6185      neither 1 or -1, but it isn't worth checking for.  */
6186
6187   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6188       && comparison_p
6189       && GET_MODE_CLASS (mode) == MODE_INT
6190       && ! side_effects_p (x))
6191     {
6192       rtx t = make_compound_operation (true_rtx, SET);
6193       rtx f = make_compound_operation (false_rtx, SET);
6194       rtx cond_op0 = XEXP (cond, 0);
6195       rtx cond_op1 = XEXP (cond, 1);
6196       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6197       enum machine_mode m = mode;
6198       rtx z = 0, c1 = NULL_RTX;
6199
6200       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6201            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6202            || GET_CODE (t) == ASHIFT
6203            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6204           && rtx_equal_p (XEXP (t, 0), f))
6205         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6206
6207       /* If an identity-zero op is commutative, check whether there
6208          would be a match if we swapped the operands.  */
6209       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6210                 || GET_CODE (t) == XOR)
6211                && rtx_equal_p (XEXP (t, 1), f))
6212         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6213       else if (GET_CODE (t) == SIGN_EXTEND
6214                && (GET_CODE (XEXP (t, 0)) == PLUS
6215                    || GET_CODE (XEXP (t, 0)) == MINUS
6216                    || GET_CODE (XEXP (t, 0)) == IOR
6217                    || GET_CODE (XEXP (t, 0)) == XOR
6218                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6219                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6220                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6221                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6222                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6223                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6224                && (num_sign_bit_copies (f, GET_MODE (f))
6225                    > (unsigned int)
6226                      (GET_MODE_PRECISION (mode)
6227                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6228         {
6229           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6230           extend_op = SIGN_EXTEND;
6231           m = GET_MODE (XEXP (t, 0));
6232         }
6233       else if (GET_CODE (t) == SIGN_EXTEND
6234                && (GET_CODE (XEXP (t, 0)) == PLUS
6235                    || GET_CODE (XEXP (t, 0)) == IOR
6236                    || GET_CODE (XEXP (t, 0)) == XOR)
6237                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6238                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6239                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6240                && (num_sign_bit_copies (f, GET_MODE (f))
6241                    > (unsigned int)
6242                      (GET_MODE_PRECISION (mode)
6243                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6244         {
6245           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6246           extend_op = SIGN_EXTEND;
6247           m = GET_MODE (XEXP (t, 0));
6248         }
6249       else if (GET_CODE (t) == ZERO_EXTEND
6250                && (GET_CODE (XEXP (t, 0)) == PLUS
6251                    || GET_CODE (XEXP (t, 0)) == MINUS
6252                    || GET_CODE (XEXP (t, 0)) == IOR
6253                    || GET_CODE (XEXP (t, 0)) == XOR
6254                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6255                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6256                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6257                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6258                && HWI_COMPUTABLE_MODE_P (mode)
6259                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6260                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6261                && ((nonzero_bits (f, GET_MODE (f))
6262                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6263                    == 0))
6264         {
6265           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6266           extend_op = ZERO_EXTEND;
6267           m = GET_MODE (XEXP (t, 0));
6268         }
6269       else if (GET_CODE (t) == ZERO_EXTEND
6270                && (GET_CODE (XEXP (t, 0)) == PLUS
6271                    || GET_CODE (XEXP (t, 0)) == IOR
6272                    || GET_CODE (XEXP (t, 0)) == XOR)
6273                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6274                && HWI_COMPUTABLE_MODE_P (mode)
6275                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6276                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6277                && ((nonzero_bits (f, GET_MODE (f))
6278                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6279                    == 0))
6280         {
6281           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6282           extend_op = ZERO_EXTEND;
6283           m = GET_MODE (XEXP (t, 0));
6284         }
6285
6286       if (z)
6287         {
6288           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6289                                                  cond_op0, cond_op1),
6290                         pc_rtx, pc_rtx, 0, 0, 0);
6291           temp = simplify_gen_binary (MULT, m, temp,
6292                                       simplify_gen_binary (MULT, m, c1,
6293                                                            const_true_rtx));
6294           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6295           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6296
6297           if (extend_op != UNKNOWN)
6298             temp = simplify_gen_unary (extend_op, mode, temp, m);
6299
6300           return temp;
6301         }
6302     }
6303
6304   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6305      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6306      negation of a single bit, we can convert this operation to a shift.  We
6307      can actually do this more generally, but it doesn't seem worth it.  */
6308
6309   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6310       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6311       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6312            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6313           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6314                == GET_MODE_PRECISION (mode))
6315               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6316     return
6317       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6318                             gen_lowpart (mode, XEXP (cond, 0)), i);
6319
6320   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6321   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6322       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6323       && GET_MODE (XEXP (cond, 0)) == mode
6324       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6325           == nonzero_bits (XEXP (cond, 0), mode)
6326       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6327     return XEXP (cond, 0);
6328
6329   return x;
6330 }
6331 \f
6332 /* Simplify X, a SET expression.  Return the new expression.  */
6333
6334 static rtx
6335 simplify_set (rtx x)
6336 {
6337   rtx src = SET_SRC (x);
6338   rtx dest = SET_DEST (x);
6339   enum machine_mode mode
6340     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6341   rtx other_insn;
6342   rtx *cc_use;
6343
6344   /* (set (pc) (return)) gets written as (return).  */
6345   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6346     return src;
6347
6348   /* Now that we know for sure which bits of SRC we are using, see if we can
6349      simplify the expression for the object knowing that we only need the
6350      low-order bits.  */
6351
6352   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6353     {
6354       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6355       SUBST (SET_SRC (x), src);
6356     }
6357
6358   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6359      the comparison result and try to simplify it unless we already have used
6360      undobuf.other_insn.  */
6361   if ((GET_MODE_CLASS (mode) == MODE_CC
6362        || GET_CODE (src) == COMPARE
6363        || CC0_P (dest))
6364       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6365       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6366       && COMPARISON_P (*cc_use)
6367       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6368     {
6369       enum rtx_code old_code = GET_CODE (*cc_use);
6370       enum rtx_code new_code;
6371       rtx op0, op1, tmp;
6372       int other_changed = 0;
6373       rtx inner_compare = NULL_RTX;
6374       enum machine_mode compare_mode = GET_MODE (dest);
6375
6376       if (GET_CODE (src) == COMPARE)
6377         {
6378           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6379           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6380             {
6381               inner_compare = op0;
6382               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6383             }
6384         }
6385       else
6386         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6387
6388       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6389                                            op0, op1);
6390       if (!tmp)
6391         new_code = old_code;
6392       else if (!CONSTANT_P (tmp))
6393         {
6394           new_code = GET_CODE (tmp);
6395           op0 = XEXP (tmp, 0);
6396           op1 = XEXP (tmp, 1);
6397         }
6398       else
6399         {
6400           rtx pat = PATTERN (other_insn);
6401           undobuf.other_insn = other_insn;
6402           SUBST (*cc_use, tmp);
6403
6404           /* Attempt to simplify CC user.  */
6405           if (GET_CODE (pat) == SET)
6406             {
6407               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6408               if (new_rtx != NULL_RTX)
6409                 SUBST (SET_SRC (pat), new_rtx);
6410             }
6411
6412           /* Convert X into a no-op move.  */
6413           SUBST (SET_DEST (x), pc_rtx);
6414           SUBST (SET_SRC (x), pc_rtx);
6415           return x;
6416         }
6417
6418       /* Simplify our comparison, if possible.  */
6419       new_code = simplify_comparison (new_code, &op0, &op1);
6420
6421 #ifdef SELECT_CC_MODE
6422       /* If this machine has CC modes other than CCmode, check to see if we
6423          need to use a different CC mode here.  */
6424       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6425         compare_mode = GET_MODE (op0);
6426       else if (inner_compare
6427                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6428                && new_code == old_code
6429                && op0 == XEXP (inner_compare, 0)
6430                && op1 == XEXP (inner_compare, 1))
6431         compare_mode = GET_MODE (inner_compare);
6432       else
6433         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6434
6435 #ifndef HAVE_cc0
6436       /* If the mode changed, we have to change SET_DEST, the mode in the
6437          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6438          a hard register, just build new versions with the proper mode.  If it
6439          is a pseudo, we lose unless it is only time we set the pseudo, in
6440          which case we can safely change its mode.  */
6441       if (compare_mode != GET_MODE (dest))
6442         {
6443           if (can_change_dest_mode (dest, 0, compare_mode))
6444             {
6445               unsigned int regno = REGNO (dest);
6446               rtx new_dest;
6447
6448               if (regno < FIRST_PSEUDO_REGISTER)
6449                 new_dest = gen_rtx_REG (compare_mode, regno);
6450               else
6451                 {
6452                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6453                   new_dest = regno_reg_rtx[regno];
6454                 }
6455
6456               SUBST (SET_DEST (x), new_dest);
6457               SUBST (XEXP (*cc_use, 0), new_dest);
6458               other_changed = 1;
6459
6460               dest = new_dest;
6461             }
6462         }
6463 #endif  /* cc0 */
6464 #endif  /* SELECT_CC_MODE */
6465
6466       /* If the code changed, we have to build a new comparison in
6467          undobuf.other_insn.  */
6468       if (new_code != old_code)
6469         {
6470           int other_changed_previously = other_changed;
6471           unsigned HOST_WIDE_INT mask;
6472           rtx old_cc_use = *cc_use;
6473
6474           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6475                                           dest, const0_rtx));
6476           other_changed = 1;
6477
6478           /* If the only change we made was to change an EQ into an NE or
6479              vice versa, OP0 has only one bit that might be nonzero, and OP1
6480              is zero, check if changing the user of the condition code will
6481              produce a valid insn.  If it won't, we can keep the original code
6482              in that insn by surrounding our operation with an XOR.  */
6483
6484           if (((old_code == NE && new_code == EQ)
6485                || (old_code == EQ && new_code == NE))
6486               && ! other_changed_previously && op1 == const0_rtx
6487               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6488               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6489             {
6490               rtx pat = PATTERN (other_insn), note = 0;
6491
6492               if ((recog_for_combine (&pat, other_insn, &note) < 0
6493                    && ! check_asm_operands (pat)))
6494                 {
6495                   *cc_use = old_cc_use;
6496                   other_changed = 0;
6497
6498                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6499                                              op0, GEN_INT (mask));
6500                 }
6501             }
6502         }
6503
6504       if (other_changed)
6505         undobuf.other_insn = other_insn;
6506
6507       /* Otherwise, if we didn't previously have a COMPARE in the
6508          correct mode, we need one.  */
6509       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6510         {
6511           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6512           src = SET_SRC (x);
6513         }
6514       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6515         {
6516           SUBST (SET_SRC (x), op0);
6517           src = SET_SRC (x);
6518         }
6519       /* Otherwise, update the COMPARE if needed.  */
6520       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6521         {
6522           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6523           src = SET_SRC (x);
6524         }
6525     }
6526   else
6527     {
6528       /* Get SET_SRC in a form where we have placed back any
6529          compound expressions.  Then do the checks below.  */
6530       src = make_compound_operation (src, SET);
6531       SUBST (SET_SRC (x), src);
6532     }
6533
6534   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6535      and X being a REG or (subreg (reg)), we may be able to convert this to
6536      (set (subreg:m2 x) (op)).
6537
6538      We can always do this if M1 is narrower than M2 because that means that
6539      we only care about the low bits of the result.
6540
6541      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6542      perform a narrower operation than requested since the high-order bits will
6543      be undefined.  On machine where it is defined, this transformation is safe
6544      as long as M1 and M2 have the same number of words.  */
6545
6546   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6547       && !OBJECT_P (SUBREG_REG (src))
6548       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6549            / UNITS_PER_WORD)
6550           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6551                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6552 #ifndef WORD_REGISTER_OPERATIONS
6553       && (GET_MODE_SIZE (GET_MODE (src))
6554         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6555 #endif
6556 #ifdef CANNOT_CHANGE_MODE_CLASS
6557       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6558             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6559                                          GET_MODE (SUBREG_REG (src)),
6560                                          GET_MODE (src)))
6561 #endif
6562       && (REG_P (dest)
6563           || (GET_CODE (dest) == SUBREG
6564               && REG_P (SUBREG_REG (dest)))))
6565     {
6566       SUBST (SET_DEST (x),
6567              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6568                                       dest));
6569       SUBST (SET_SRC (x), SUBREG_REG (src));
6570
6571       src = SET_SRC (x), dest = SET_DEST (x);
6572     }
6573
6574 #ifdef HAVE_cc0
6575   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6576      in SRC.  */
6577   if (dest == cc0_rtx
6578       && GET_CODE (src) == SUBREG
6579       && subreg_lowpart_p (src)
6580       && (GET_MODE_PRECISION (GET_MODE (src))
6581           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6582     {
6583       rtx inner = SUBREG_REG (src);
6584       enum machine_mode inner_mode = GET_MODE (inner);
6585
6586       /* Here we make sure that we don't have a sign bit on.  */
6587       if (val_signbit_known_clear_p (GET_MODE (src),
6588                                      nonzero_bits (inner, inner_mode)))
6589         {
6590           SUBST (SET_SRC (x), inner);
6591           src = SET_SRC (x);
6592         }
6593     }
6594 #endif
6595
6596 #ifdef LOAD_EXTEND_OP
6597   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6598      would require a paradoxical subreg.  Replace the subreg with a
6599      zero_extend to avoid the reload that would otherwise be required.  */
6600
6601   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6602       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6603       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6604       && SUBREG_BYTE (src) == 0
6605       && paradoxical_subreg_p (src)
6606       && MEM_P (SUBREG_REG (src)))
6607     {
6608       SUBST (SET_SRC (x),
6609              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6610                             GET_MODE (src), SUBREG_REG (src)));
6611
6612       src = SET_SRC (x);
6613     }
6614 #endif
6615
6616   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6617      are comparing an item known to be 0 or -1 against 0, use a logical
6618      operation instead. Check for one of the arms being an IOR of the other
6619      arm with some value.  We compute three terms to be IOR'ed together.  In
6620      practice, at most two will be nonzero.  Then we do the IOR's.  */
6621
6622   if (GET_CODE (dest) != PC
6623       && GET_CODE (src) == IF_THEN_ELSE
6624       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6625       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6626       && XEXP (XEXP (src, 0), 1) == const0_rtx
6627       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6628 #ifdef HAVE_conditional_move
6629       && ! can_conditionally_move_p (GET_MODE (src))
6630 #endif
6631       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6632                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6633           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6634       && ! side_effects_p (src))
6635     {
6636       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6637                       ? XEXP (src, 1) : XEXP (src, 2));
6638       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6639                    ? XEXP (src, 2) : XEXP (src, 1));
6640       rtx term1 = const0_rtx, term2, term3;
6641
6642       if (GET_CODE (true_rtx) == IOR
6643           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6644         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6645       else if (GET_CODE (true_rtx) == IOR
6646                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6647         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6648       else if (GET_CODE (false_rtx) == IOR
6649                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6650         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6651       else if (GET_CODE (false_rtx) == IOR
6652                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6653         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6654
6655       term2 = simplify_gen_binary (AND, GET_MODE (src),
6656                                    XEXP (XEXP (src, 0), 0), true_rtx);
6657       term3 = simplify_gen_binary (AND, GET_MODE (src),
6658                                    simplify_gen_unary (NOT, GET_MODE (src),
6659                                                        XEXP (XEXP (src, 0), 0),
6660                                                        GET_MODE (src)),
6661                                    false_rtx);
6662
6663       SUBST (SET_SRC (x),
6664              simplify_gen_binary (IOR, GET_MODE (src),
6665                                   simplify_gen_binary (IOR, GET_MODE (src),
6666                                                        term1, term2),
6667                                   term3));
6668
6669       src = SET_SRC (x);
6670     }
6671
6672   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6673      whole thing fail.  */
6674   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6675     return src;
6676   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6677     return dest;
6678   else
6679     /* Convert this into a field assignment operation, if possible.  */
6680     return make_field_assignment (x);
6681 }
6682 \f
6683 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6684    result.  */
6685
6686 static rtx
6687 simplify_logical (rtx x)
6688 {
6689   enum machine_mode mode = GET_MODE (x);
6690   rtx op0 = XEXP (x, 0);
6691   rtx op1 = XEXP (x, 1);
6692
6693   switch (GET_CODE (x))
6694     {
6695     case AND:
6696       /* We can call simplify_and_const_int only if we don't lose
6697          any (sign) bits when converting INTVAL (op1) to
6698          "unsigned HOST_WIDE_INT".  */
6699       if (CONST_INT_P (op1)
6700           && (HWI_COMPUTABLE_MODE_P (mode)
6701               || INTVAL (op1) > 0))
6702         {
6703           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6704           if (GET_CODE (x) != AND)
6705             return x;
6706
6707           op0 = XEXP (x, 0);
6708           op1 = XEXP (x, 1);
6709         }
6710
6711       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6712          apply the distributive law and then the inverse distributive
6713          law to see if things simplify.  */
6714       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6715         {
6716           rtx result = distribute_and_simplify_rtx (x, 0);
6717           if (result)
6718             return result;
6719         }
6720       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6721         {
6722           rtx result = distribute_and_simplify_rtx (x, 1);
6723           if (result)
6724             return result;
6725         }
6726       break;
6727
6728     case IOR:
6729       /* If we have (ior (and A B) C), apply the distributive law and then
6730          the inverse distributive law to see if things simplify.  */
6731
6732       if (GET_CODE (op0) == AND)
6733         {
6734           rtx result = distribute_and_simplify_rtx (x, 0);
6735           if (result)
6736             return result;
6737         }
6738
6739       if (GET_CODE (op1) == AND)
6740         {
6741           rtx result = distribute_and_simplify_rtx (x, 1);
6742           if (result)
6743             return result;
6744         }
6745       break;
6746
6747     default:
6748       gcc_unreachable ();
6749     }
6750
6751   return x;
6752 }
6753 \f
6754 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6755    operations" because they can be replaced with two more basic operations.
6756    ZERO_EXTEND is also considered "compound" because it can be replaced with
6757    an AND operation, which is simpler, though only one operation.
6758
6759    The function expand_compound_operation is called with an rtx expression
6760    and will convert it to the appropriate shifts and AND operations,
6761    simplifying at each stage.
6762
6763    The function make_compound_operation is called to convert an expression
6764    consisting of shifts and ANDs into the equivalent compound expression.
6765    It is the inverse of this function, loosely speaking.  */
6766
6767 static rtx
6768 expand_compound_operation (rtx x)
6769 {
6770   unsigned HOST_WIDE_INT pos = 0, len;
6771   int unsignedp = 0;
6772   unsigned int modewidth;
6773   rtx tem;
6774
6775   switch (GET_CODE (x))
6776     {
6777     case ZERO_EXTEND:
6778       unsignedp = 1;
6779     case SIGN_EXTEND:
6780       /* We can't necessarily use a const_int for a multiword mode;
6781          it depends on implicitly extending the value.
6782          Since we don't know the right way to extend it,
6783          we can't tell whether the implicit way is right.
6784
6785          Even for a mode that is no wider than a const_int,
6786          we can't win, because we need to sign extend one of its bits through
6787          the rest of it, and we don't know which bit.  */
6788       if (CONST_INT_P (XEXP (x, 0)))
6789         return x;
6790
6791       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6792          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6793          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6794          reloaded. If not for that, MEM's would very rarely be safe.
6795
6796          Reject MODEs bigger than a word, because we might not be able
6797          to reference a two-register group starting with an arbitrary register
6798          (and currently gen_lowpart might crash for a SUBREG).  */
6799
6800       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6801         return x;
6802
6803       /* Reject MODEs that aren't scalar integers because turning vector
6804          or complex modes into shifts causes problems.  */
6805
6806       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6807         return x;
6808
6809       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6810       /* If the inner object has VOIDmode (the only way this can happen
6811          is if it is an ASM_OPERANDS), we can't do anything since we don't
6812          know how much masking to do.  */
6813       if (len == 0)
6814         return x;
6815
6816       break;
6817
6818     case ZERO_EXTRACT:
6819       unsignedp = 1;
6820
6821       /* ... fall through ...  */
6822
6823     case SIGN_EXTRACT:
6824       /* If the operand is a CLOBBER, just return it.  */
6825       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6826         return XEXP (x, 0);
6827
6828       if (!CONST_INT_P (XEXP (x, 1))
6829           || !CONST_INT_P (XEXP (x, 2))
6830           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6831         return x;
6832
6833       /* Reject MODEs that aren't scalar integers because turning vector
6834          or complex modes into shifts causes problems.  */
6835
6836       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6837         return x;
6838
6839       len = INTVAL (XEXP (x, 1));
6840       pos = INTVAL (XEXP (x, 2));
6841
6842       /* This should stay within the object being extracted, fail otherwise.  */
6843       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6844         return x;
6845
6846       if (BITS_BIG_ENDIAN)
6847         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6848
6849       break;
6850
6851     default:
6852       return x;
6853     }
6854   /* Convert sign extension to zero extension, if we know that the high
6855      bit is not set, as this is easier to optimize.  It will be converted
6856      back to cheaper alternative in make_extraction.  */
6857   if (GET_CODE (x) == SIGN_EXTEND
6858       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6859           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6860                 & ~(((unsigned HOST_WIDE_INT)
6861                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6862                      >> 1))
6863                == 0)))
6864     {
6865       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6866       rtx temp2 = expand_compound_operation (temp);
6867
6868       /* Make sure this is a profitable operation.  */
6869       if (set_src_cost (x, optimize_this_for_speed_p)
6870           > set_src_cost (temp2, optimize_this_for_speed_p))
6871        return temp2;
6872       else if (set_src_cost (x, optimize_this_for_speed_p)
6873                > set_src_cost (temp, optimize_this_for_speed_p))
6874        return temp;
6875       else
6876        return x;
6877     }
6878
6879   /* We can optimize some special cases of ZERO_EXTEND.  */
6880   if (GET_CODE (x) == ZERO_EXTEND)
6881     {
6882       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6883          know that the last value didn't have any inappropriate bits
6884          set.  */
6885       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6886           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6887           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6888           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6889               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6890         return XEXP (XEXP (x, 0), 0);
6891
6892       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6893       if (GET_CODE (XEXP (x, 0)) == SUBREG
6894           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6895           && subreg_lowpart_p (XEXP (x, 0))
6896           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6897           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6898               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6899         return SUBREG_REG (XEXP (x, 0));
6900
6901       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6902          is a comparison and STORE_FLAG_VALUE permits.  This is like
6903          the first case, but it works even when GET_MODE (x) is larger
6904          than HOST_WIDE_INT.  */
6905       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6906           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6907           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6908           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6909               <= HOST_BITS_PER_WIDE_INT)
6910           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6911         return XEXP (XEXP (x, 0), 0);
6912
6913       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6914       if (GET_CODE (XEXP (x, 0)) == SUBREG
6915           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6916           && subreg_lowpart_p (XEXP (x, 0))
6917           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6918           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6919               <= HOST_BITS_PER_WIDE_INT)
6920           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6921         return SUBREG_REG (XEXP (x, 0));
6922
6923     }
6924
6925   /* If we reach here, we want to return a pair of shifts.  The inner
6926      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6927      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6928      logical depending on the value of UNSIGNEDP.
6929
6930      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6931      converted into an AND of a shift.
6932
6933      We must check for the case where the left shift would have a negative
6934      count.  This can happen in a case like (x >> 31) & 255 on machines
6935      that can't shift by a constant.  On those machines, we would first
6936      combine the shift with the AND to produce a variable-position
6937      extraction.  Then the constant of 31 would be substituted in
6938      to produce such a position.  */
6939
6940   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6941   if (modewidth >= pos + len)
6942     {
6943       enum machine_mode mode = GET_MODE (x);
6944       tem = gen_lowpart (mode, XEXP (x, 0));
6945       if (!tem || GET_CODE (tem) == CLOBBER)
6946         return x;
6947       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6948                                   tem, modewidth - pos - len);
6949       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6950                                   mode, tem, modewidth - len);
6951     }
6952   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6953     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6954                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6955                                                         GET_MODE (x),
6956                                                         XEXP (x, 0), pos),
6957                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6958   else
6959     /* Any other cases we can't handle.  */
6960     return x;
6961
6962   /* If we couldn't do this for some reason, return the original
6963      expression.  */
6964   if (GET_CODE (tem) == CLOBBER)
6965     return x;
6966
6967   return tem;
6968 }
6969 \f
6970 /* X is a SET which contains an assignment of one object into
6971    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6972    or certain SUBREGS). If possible, convert it into a series of
6973    logical operations.
6974
6975    We half-heartedly support variable positions, but do not at all
6976    support variable lengths.  */
6977
6978 static const_rtx
6979 expand_field_assignment (const_rtx x)
6980 {
6981   rtx inner;
6982   rtx pos;                      /* Always counts from low bit.  */
6983   int len;
6984   rtx mask, cleared, masked;
6985   enum machine_mode compute_mode;
6986
6987   /* Loop until we find something we can't simplify.  */
6988   while (1)
6989     {
6990       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6991           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6992         {
6993           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6994           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6995           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6996         }
6997       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6998                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6999         {
7000           inner = XEXP (SET_DEST (x), 0);
7001           len = INTVAL (XEXP (SET_DEST (x), 1));
7002           pos = XEXP (SET_DEST (x), 2);
7003
7004           /* A constant position should stay within the width of INNER.  */
7005           if (CONST_INT_P (pos)
7006               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
7007             break;
7008
7009           if (BITS_BIG_ENDIAN)
7010             {
7011               if (CONST_INT_P (pos))
7012                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
7013                                - INTVAL (pos));
7014               else if (GET_CODE (pos) == MINUS
7015                        && CONST_INT_P (XEXP (pos, 1))
7016                        && (INTVAL (XEXP (pos, 1))
7017                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
7018                 /* If position is ADJUST - X, new position is X.  */
7019                 pos = XEXP (pos, 0);
7020               else
7021                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7022                                            GEN_INT (GET_MODE_PRECISION (
7023                                                     GET_MODE (inner))
7024                                                     - len),
7025                                            pos);
7026             }
7027         }
7028
7029       /* A SUBREG between two modes that occupy the same numbers of words
7030          can be done by moving the SUBREG to the source.  */
7031       else if (GET_CODE (SET_DEST (x)) == SUBREG
7032                /* We need SUBREGs to compute nonzero_bits properly.  */
7033                && nonzero_sign_valid
7034                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
7035                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7036                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7037                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7038         {
7039           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
7040                            gen_lowpart
7041                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
7042                             SET_SRC (x)));
7043           continue;
7044         }
7045       else
7046         break;
7047
7048       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7049         inner = SUBREG_REG (inner);
7050
7051       compute_mode = GET_MODE (inner);
7052
7053       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
7054       if (! SCALAR_INT_MODE_P (compute_mode))
7055         {
7056           enum machine_mode imode;
7057
7058           /* Don't do anything for vector or complex integral types.  */
7059           if (! FLOAT_MODE_P (compute_mode))
7060             break;
7061
7062           /* Try to find an integral mode to pun with.  */
7063           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7064           if (imode == BLKmode)
7065             break;
7066
7067           compute_mode = imode;
7068           inner = gen_lowpart (imode, inner);
7069         }
7070
7071       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
7072       if (len >= HOST_BITS_PER_WIDE_INT)
7073         break;
7074
7075       /* Now compute the equivalent expression.  Make a copy of INNER
7076          for the SET_DEST in case it is a MEM into which we will substitute;
7077          we don't want shared RTL in that case.  */
7078       mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7079       cleared = simplify_gen_binary (AND, compute_mode,
7080                                      simplify_gen_unary (NOT, compute_mode,
7081                                        simplify_gen_binary (ASHIFT,
7082                                                             compute_mode,
7083                                                             mask, pos),
7084                                        compute_mode),
7085                                      inner);
7086       masked = simplify_gen_binary (ASHIFT, compute_mode,
7087                                     simplify_gen_binary (
7088                                       AND, compute_mode,
7089                                       gen_lowpart (compute_mode, SET_SRC (x)),
7090                                       mask),
7091                                     pos);
7092
7093       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7094                        simplify_gen_binary (IOR, compute_mode,
7095                                             cleared, masked));
7096     }
7097
7098   return x;
7099 }
7100 \f
7101 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7102    it is an RTX that represents a variable starting position; otherwise,
7103    POS is the (constant) starting bit position (counted from the LSB).
7104
7105    UNSIGNEDP is nonzero for an unsigned reference and zero for a
7106    signed reference.
7107
7108    IN_DEST is nonzero if this is a reference in the destination of a
7109    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7110    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7111    be used.
7112
7113    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7114    ZERO_EXTRACT should be built even for bits starting at bit 0.
7115
7116    MODE is the desired mode of the result (if IN_DEST == 0).
7117
7118    The result is an RTX for the extraction or NULL_RTX if the target
7119    can't handle it.  */
7120
7121 static rtx
7122 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7123                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7124                  int in_dest, int in_compare)
7125 {
7126   /* This mode describes the size of the storage area
7127      to fetch the overall value from.  Within that, we
7128      ignore the POS lowest bits, etc.  */
7129   enum machine_mode is_mode = GET_MODE (inner);
7130   enum machine_mode inner_mode;
7131   enum machine_mode wanted_inner_mode;
7132   enum machine_mode wanted_inner_reg_mode = word_mode;
7133   enum machine_mode pos_mode = word_mode;
7134   enum machine_mode extraction_mode = word_mode;
7135   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7136   rtx new_rtx = 0;
7137   rtx orig_pos_rtx = pos_rtx;
7138   HOST_WIDE_INT orig_pos;
7139
7140   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7141     {
7142       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7143          consider just the QI as the memory to extract from.
7144          The subreg adds or removes high bits; its mode is
7145          irrelevant to the meaning of this extraction,
7146          since POS and LEN count from the lsb.  */
7147       if (MEM_P (SUBREG_REG (inner)))
7148         is_mode = GET_MODE (SUBREG_REG (inner));
7149       inner = SUBREG_REG (inner);
7150     }
7151   else if (GET_CODE (inner) == ASHIFT
7152            && CONST_INT_P (XEXP (inner, 1))
7153            && pos_rtx == 0 && pos == 0
7154            && len > UINTVAL (XEXP (inner, 1)))
7155     {
7156       /* We're extracting the least significant bits of an rtx
7157          (ashift X (const_int C)), where LEN > C.  Extract the
7158          least significant (LEN - C) bits of X, giving an rtx
7159          whose mode is MODE, then shift it left C times.  */
7160       new_rtx = make_extraction (mode, XEXP (inner, 0),
7161                              0, 0, len - INTVAL (XEXP (inner, 1)),
7162                              unsignedp, in_dest, in_compare);
7163       if (new_rtx != 0)
7164         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7165     }
7166
7167   inner_mode = GET_MODE (inner);
7168
7169   if (pos_rtx && CONST_INT_P (pos_rtx))
7170     pos = INTVAL (pos_rtx), pos_rtx = 0;
7171
7172   /* See if this can be done without an extraction.  We never can if the
7173      width of the field is not the same as that of some integer mode. For
7174      registers, we can only avoid the extraction if the position is at the
7175      low-order bit and this is either not in the destination or we have the
7176      appropriate STRICT_LOW_PART operation available.
7177
7178      For MEM, we can avoid an extract if the field starts on an appropriate
7179      boundary and we can change the mode of the memory reference.  */
7180
7181   if (tmode != BLKmode
7182       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7183            && !MEM_P (inner)
7184            && (inner_mode == tmode
7185                || !REG_P (inner)
7186                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7187                || reg_truncated_to_mode (tmode, inner))
7188            && (! in_dest
7189                || (REG_P (inner)
7190                    && have_insn_for (STRICT_LOW_PART, tmode))))
7191           || (MEM_P (inner) && pos_rtx == 0
7192               && (pos
7193                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7194                      : BITS_PER_UNIT)) == 0
7195               /* We can't do this if we are widening INNER_MODE (it
7196                  may not be aligned, for one thing).  */
7197               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7198               && (inner_mode == tmode
7199                   || (! mode_dependent_address_p (XEXP (inner, 0))
7200                       && ! MEM_VOLATILE_P (inner))))))
7201     {
7202       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7203          field.  If the original and current mode are the same, we need not
7204          adjust the offset.  Otherwise, we do if bytes big endian.
7205
7206          If INNER is not a MEM, get a piece consisting of just the field
7207          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7208
7209       if (MEM_P (inner))
7210         {
7211           HOST_WIDE_INT offset;
7212
7213           /* POS counts from lsb, but make OFFSET count in memory order.  */
7214           if (BYTES_BIG_ENDIAN)
7215             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7216           else
7217             offset = pos / BITS_PER_UNIT;
7218
7219           new_rtx = adjust_address_nv (inner, tmode, offset);
7220         }
7221       else if (REG_P (inner))
7222         {
7223           if (tmode != inner_mode)
7224             {
7225               /* We can't call gen_lowpart in a DEST since we
7226                  always want a SUBREG (see below) and it would sometimes
7227                  return a new hard register.  */
7228               if (pos || in_dest)
7229                 {
7230                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7231
7232                   if (WORDS_BIG_ENDIAN
7233                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7234                     final_word = ((GET_MODE_SIZE (inner_mode)
7235                                    - GET_MODE_SIZE (tmode))
7236                                   / UNITS_PER_WORD) - final_word;
7237
7238                   final_word *= UNITS_PER_WORD;
7239                   if (BYTES_BIG_ENDIAN &&
7240                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7241                     final_word += (GET_MODE_SIZE (inner_mode)
7242                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7243
7244                   /* Avoid creating invalid subregs, for example when
7245                      simplifying (x>>32)&255.  */
7246                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7247                     return NULL_RTX;
7248
7249                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7250                 }
7251               else
7252                 new_rtx = gen_lowpart (tmode, inner);
7253             }
7254           else
7255             new_rtx = inner;
7256         }
7257       else
7258         new_rtx = force_to_mode (inner, tmode,
7259                              len >= HOST_BITS_PER_WIDE_INT
7260                              ? ~(unsigned HOST_WIDE_INT) 0
7261                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7262                              0);
7263
7264       /* If this extraction is going into the destination of a SET,
7265          make a STRICT_LOW_PART unless we made a MEM.  */
7266
7267       if (in_dest)
7268         return (MEM_P (new_rtx) ? new_rtx
7269                 : (GET_CODE (new_rtx) != SUBREG
7270                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7271                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7272
7273       if (mode == tmode)
7274         return new_rtx;
7275
7276       if (CONST_INT_P (new_rtx)
7277           || GET_CODE (new_rtx) == CONST_DOUBLE)
7278         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7279                                          mode, new_rtx, tmode);
7280
7281       /* If we know that no extraneous bits are set, and that the high
7282          bit is not set, convert the extraction to the cheaper of
7283          sign and zero extension, that are equivalent in these cases.  */
7284       if (flag_expensive_optimizations
7285           && (HWI_COMPUTABLE_MODE_P (tmode)
7286               && ((nonzero_bits (new_rtx, tmode)
7287                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7288                   == 0)))
7289         {
7290           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7291           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7292
7293           /* Prefer ZERO_EXTENSION, since it gives more information to
7294              backends.  */
7295           if (set_src_cost (temp, optimize_this_for_speed_p)
7296               <= set_src_cost (temp1, optimize_this_for_speed_p))
7297             return temp;
7298           return temp1;
7299         }
7300
7301       /* Otherwise, sign- or zero-extend unless we already are in the
7302          proper mode.  */
7303
7304       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7305                              mode, new_rtx));
7306     }
7307
7308   /* Unless this is a COMPARE or we have a funny memory reference,
7309      don't do anything with zero-extending field extracts starting at
7310      the low-order bit since they are simple AND operations.  */
7311   if (pos_rtx == 0 && pos == 0 && ! in_dest
7312       && ! in_compare && unsignedp)
7313     return 0;
7314
7315   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7316      if the position is not a constant and the length is not 1.  In all
7317      other cases, we would only be going outside our object in cases when
7318      an original shift would have been undefined.  */
7319   if (MEM_P (inner)
7320       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7321           || (pos_rtx != 0 && len != 1)))
7322     return 0;
7323
7324   /* Get the mode to use should INNER not be a MEM, the mode for the position,
7325      and the mode for the result.  */
7326   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7327     {
7328       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7329       pos_mode = mode_for_extraction (EP_insv, 2);
7330       extraction_mode = mode_for_extraction (EP_insv, 3);
7331     }
7332
7333   if (! in_dest && unsignedp
7334       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7335     {
7336       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7337       pos_mode = mode_for_extraction (EP_extzv, 3);
7338       extraction_mode = mode_for_extraction (EP_extzv, 0);
7339     }
7340
7341   if (! in_dest && ! unsignedp
7342       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7343     {
7344       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7345       pos_mode = mode_for_extraction (EP_extv, 3);
7346       extraction_mode = mode_for_extraction (EP_extv, 0);
7347     }
7348
7349   /* Never narrow an object, since that might not be safe.  */
7350
7351   if (mode != VOIDmode
7352       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7353     extraction_mode = mode;
7354
7355   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7356       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7357     pos_mode = GET_MODE (pos_rtx);
7358
7359   /* If this is not from memory, the desired mode is the preferred mode
7360      for an extraction pattern's first input operand, or word_mode if there
7361      is none.  */
7362   if (!MEM_P (inner))
7363     wanted_inner_mode = wanted_inner_reg_mode;
7364   else
7365     {
7366       /* Be careful not to go beyond the extracted object and maintain the
7367          natural alignment of the memory.  */
7368       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7369       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7370              > GET_MODE_BITSIZE (wanted_inner_mode))
7371         {
7372           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7373           gcc_assert (wanted_inner_mode != VOIDmode);
7374         }
7375
7376       /* If we have to change the mode of memory and cannot, the desired mode
7377          is EXTRACTION_MODE.  */
7378       if (inner_mode != wanted_inner_mode
7379           && (mode_dependent_address_p (XEXP (inner, 0))
7380               || MEM_VOLATILE_P (inner)
7381               || pos_rtx))
7382         wanted_inner_mode = extraction_mode;
7383     }
7384
7385   orig_pos = pos;
7386
7387   if (BITS_BIG_ENDIAN)
7388     {
7389       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7390          BITS_BIG_ENDIAN style.  If position is constant, compute new
7391          position.  Otherwise, build subtraction.
7392          Note that POS is relative to the mode of the original argument.
7393          If it's a MEM we need to recompute POS relative to that.
7394          However, if we're extracting from (or inserting into) a register,
7395          we want to recompute POS relative to wanted_inner_mode.  */
7396       int width = (MEM_P (inner)
7397                    ? GET_MODE_BITSIZE (is_mode)
7398                    : GET_MODE_BITSIZE (wanted_inner_mode));
7399
7400       if (pos_rtx == 0)
7401         pos = width - len - pos;
7402       else
7403         pos_rtx
7404           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7405       /* POS may be less than 0 now, but we check for that below.
7406          Note that it can only be less than 0 if !MEM_P (inner).  */
7407     }
7408
7409   /* If INNER has a wider mode, and this is a constant extraction, try to
7410      make it smaller and adjust the byte to point to the byte containing
7411      the value.  */
7412   if (wanted_inner_mode != VOIDmode
7413       && inner_mode != wanted_inner_mode
7414       && ! pos_rtx
7415       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7416       && MEM_P (inner)
7417       && ! mode_dependent_address_p (XEXP (inner, 0))
7418       && ! MEM_VOLATILE_P (inner))
7419     {
7420       int offset = 0;
7421
7422       /* The computations below will be correct if the machine is big
7423          endian in both bits and bytes or little endian in bits and bytes.
7424          If it is mixed, we must adjust.  */
7425
7426       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7427          adjust OFFSET to compensate.  */
7428       if (BYTES_BIG_ENDIAN
7429           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7430         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7431
7432       /* We can now move to the desired byte.  */
7433       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7434                 * GET_MODE_SIZE (wanted_inner_mode);
7435       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7436
7437       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7438           && is_mode != wanted_inner_mode)
7439         offset = (GET_MODE_SIZE (is_mode)
7440                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7441
7442       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7443     }
7444
7445   /* If INNER is not memory, get it into the proper mode.  If we are changing
7446      its mode, POS must be a constant and smaller than the size of the new
7447      mode.  */
7448   else if (!MEM_P (inner))
7449     {
7450       /* On the LHS, don't create paradoxical subregs implicitely truncating
7451          the register unless TRULY_NOOP_TRUNCATION.  */
7452       if (in_dest
7453           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7454                                              wanted_inner_mode))
7455         return NULL_RTX;
7456
7457       if (GET_MODE (inner) != wanted_inner_mode
7458           && (pos_rtx != 0
7459               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7460         return NULL_RTX;
7461
7462       if (orig_pos < 0)
7463         return NULL_RTX;
7464
7465       inner = force_to_mode (inner, wanted_inner_mode,
7466                              pos_rtx
7467                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7468                              ? ~(unsigned HOST_WIDE_INT) 0
7469                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7470                                 << orig_pos),
7471                              0);
7472     }
7473
7474   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7475      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7476   if (pos_rtx != 0
7477       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7478     {
7479       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7480
7481       /* If we know that no extraneous bits are set, and that the high
7482          bit is not set, convert extraction to cheaper one - either
7483          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7484          cases.  */
7485       if (flag_expensive_optimizations
7486           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7487               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7488                    & ~(((unsigned HOST_WIDE_INT)
7489                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7490                        >> 1))
7491                   == 0)))
7492         {
7493           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7494
7495           /* Prefer ZERO_EXTENSION, since it gives more information to
7496              backends.  */
7497           if (set_src_cost (temp1, optimize_this_for_speed_p)
7498               < set_src_cost (temp, optimize_this_for_speed_p))
7499             temp = temp1;
7500         }
7501       pos_rtx = temp;
7502     }
7503   else if (pos_rtx != 0
7504            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7505     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7506
7507   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7508      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7509      be a CONST_INT.  */
7510   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7511     pos_rtx = orig_pos_rtx;
7512
7513   else if (pos_rtx == 0)
7514     pos_rtx = GEN_INT (pos);
7515
7516   /* Make the required operation.  See if we can use existing rtx.  */
7517   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7518                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7519   if (! in_dest)
7520     new_rtx = gen_lowpart (mode, new_rtx);
7521
7522   return new_rtx;
7523 }
7524 \f
7525 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7526    with any other operations in X.  Return X without that shift if so.  */
7527
7528 static rtx
7529 extract_left_shift (rtx x, int count)
7530 {
7531   enum rtx_code code = GET_CODE (x);
7532   enum machine_mode mode = GET_MODE (x);
7533   rtx tem;
7534
7535   switch (code)
7536     {
7537     case ASHIFT:
7538       /* This is the shift itself.  If it is wide enough, we will return
7539          either the value being shifted if the shift count is equal to
7540          COUNT or a shift for the difference.  */
7541       if (CONST_INT_P (XEXP (x, 1))
7542           && INTVAL (XEXP (x, 1)) >= count)
7543         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7544                                      INTVAL (XEXP (x, 1)) - count);
7545       break;
7546
7547     case NEG:  case NOT:
7548       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7549         return simplify_gen_unary (code, mode, tem, mode);
7550
7551       break;
7552
7553     case PLUS:  case IOR:  case XOR:  case AND:
7554       /* If we can safely shift this constant and we find the inner shift,
7555          make a new operation.  */
7556       if (CONST_INT_P (XEXP (x, 1))
7557           && (UINTVAL (XEXP (x, 1))
7558               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7559           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7560         return simplify_gen_binary (code, mode, tem,
7561                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7562
7563       break;
7564
7565     default:
7566       break;
7567     }
7568
7569   return 0;
7570 }
7571 \f
7572 /* Look at the expression rooted at X.  Look for expressions
7573    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7574    Form these expressions.
7575
7576    Return the new rtx, usually just X.
7577
7578    Also, for machines like the VAX that don't have logical shift insns,
7579    try to convert logical to arithmetic shift operations in cases where
7580    they are equivalent.  This undoes the canonicalizations to logical
7581    shifts done elsewhere.
7582
7583    We try, as much as possible, to re-use rtl expressions to save memory.
7584
7585    IN_CODE says what kind of expression we are processing.  Normally, it is
7586    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7587    being kludges), it is MEM.  When processing the arguments of a comparison
7588    or a COMPARE against zero, it is COMPARE.  */
7589
7590 static rtx
7591 make_compound_operation (rtx x, enum rtx_code in_code)
7592 {
7593   enum rtx_code code = GET_CODE (x);
7594   enum machine_mode mode = GET_MODE (x);
7595   int mode_width = GET_MODE_PRECISION (mode);
7596   rtx rhs, lhs;
7597   enum rtx_code next_code;
7598   int i, j;
7599   rtx new_rtx = 0;
7600   rtx tem;
7601   const char *fmt;
7602
7603   /* Select the code to be used in recursive calls.  Once we are inside an
7604      address, we stay there.  If we have a comparison, set to COMPARE,
7605      but once inside, go back to our default of SET.  */
7606
7607   next_code = (code == MEM ? MEM
7608                : ((code == PLUS || code == MINUS)
7609                   && SCALAR_INT_MODE_P (mode)) ? MEM
7610                : ((code == COMPARE || COMPARISON_P (x))
7611                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7612                : in_code == COMPARE ? SET : in_code);
7613
7614   /* Process depending on the code of this operation.  If NEW is set
7615      nonzero, it will be returned.  */
7616
7617   switch (code)
7618     {
7619     case ASHIFT:
7620       /* Convert shifts by constants into multiplications if inside
7621          an address.  */
7622       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7623           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7624           && INTVAL (XEXP (x, 1)) >= 0
7625           && SCALAR_INT_MODE_P (mode))
7626         {
7627           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7628           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7629
7630           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7631           if (GET_CODE (new_rtx) == NEG)
7632             {
7633               new_rtx = XEXP (new_rtx, 0);
7634               multval = -multval;
7635             }
7636           multval = trunc_int_for_mode (multval, mode);
7637           new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7638         }
7639       break;
7640
7641     case PLUS:
7642       lhs = XEXP (x, 0);
7643       rhs = XEXP (x, 1);
7644       lhs = make_compound_operation (lhs, next_code);
7645       rhs = make_compound_operation (rhs, next_code);
7646       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7647           && SCALAR_INT_MODE_P (mode))
7648         {
7649           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7650                                      XEXP (lhs, 1));
7651           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7652         }
7653       else if (GET_CODE (lhs) == MULT
7654                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7655         {
7656           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7657                                      simplify_gen_unary (NEG, mode,
7658                                                          XEXP (lhs, 1),
7659                                                          mode));
7660           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7661         }
7662       else
7663         {
7664           SUBST (XEXP (x, 0), lhs);
7665           SUBST (XEXP (x, 1), rhs);
7666           goto maybe_swap;
7667         }
7668       x = gen_lowpart (mode, new_rtx);
7669       goto maybe_swap;
7670
7671     case MINUS:
7672       lhs = XEXP (x, 0);
7673       rhs = XEXP (x, 1);
7674       lhs = make_compound_operation (lhs, next_code);
7675       rhs = make_compound_operation (rhs, next_code);
7676       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7677           && SCALAR_INT_MODE_P (mode))
7678         {
7679           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7680                                      XEXP (rhs, 1));
7681           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7682         }
7683       else if (GET_CODE (rhs) == MULT
7684                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7685         {
7686           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7687                                      simplify_gen_unary (NEG, mode,
7688                                                          XEXP (rhs, 1),
7689                                                          mode));
7690           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7691         }
7692       else
7693         {
7694           SUBST (XEXP (x, 0), lhs);
7695           SUBST (XEXP (x, 1), rhs);
7696           return x;
7697         }
7698       return gen_lowpart (mode, new_rtx);
7699
7700     case AND:
7701       /* If the second operand is not a constant, we can't do anything
7702          with it.  */
7703       if (!CONST_INT_P (XEXP (x, 1)))
7704         break;
7705
7706       /* If the constant is a power of two minus one and the first operand
7707          is a logical right shift, make an extraction.  */
7708       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7709           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7710         {
7711           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7712           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7713                                  0, in_code == COMPARE);
7714         }
7715
7716       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7717       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7718                && subreg_lowpart_p (XEXP (x, 0))
7719                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7720                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7721         {
7722           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7723                                          next_code);
7724           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7725                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7726                                  0, in_code == COMPARE);
7727         }
7728       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7729       else if ((GET_CODE (XEXP (x, 0)) == XOR
7730                 || GET_CODE (XEXP (x, 0)) == IOR)
7731                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7732                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7733                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7734         {
7735           /* Apply the distributive law, and then try to make extractions.  */
7736           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7737                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7738                                              XEXP (x, 1)),
7739                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7740                                              XEXP (x, 1)));
7741           new_rtx = make_compound_operation (new_rtx, in_code);
7742         }
7743
7744       /* If we are have (and (rotate X C) M) and C is larger than the number
7745          of bits in M, this is an extraction.  */
7746
7747       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7748                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7749                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7750                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7751         {
7752           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7753           new_rtx = make_extraction (mode, new_rtx,
7754                                  (GET_MODE_PRECISION (mode)
7755                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7756                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7757         }
7758
7759       /* On machines without logical shifts, if the operand of the AND is
7760          a logical shift and our mask turns off all the propagated sign
7761          bits, we can replace the logical shift with an arithmetic shift.  */
7762       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7763                && !have_insn_for (LSHIFTRT, mode)
7764                && have_insn_for (ASHIFTRT, mode)
7765                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7766                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7767                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7768                && mode_width <= HOST_BITS_PER_WIDE_INT)
7769         {
7770           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7771
7772           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7773           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7774             SUBST (XEXP (x, 0),
7775                    gen_rtx_ASHIFTRT (mode,
7776                                      make_compound_operation
7777                                      (XEXP (XEXP (x, 0), 0), next_code),
7778                                      XEXP (XEXP (x, 0), 1)));
7779         }
7780
7781       /* If the constant is one less than a power of two, this might be
7782          representable by an extraction even if no shift is present.
7783          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7784          we are in a COMPARE.  */
7785       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7786         new_rtx = make_extraction (mode,
7787                                make_compound_operation (XEXP (x, 0),
7788                                                         next_code),
7789                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7790
7791       /* If we are in a comparison and this is an AND with a power of two,
7792          convert this into the appropriate bit extract.  */
7793       else if (in_code == COMPARE
7794                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7795         new_rtx = make_extraction (mode,
7796                                make_compound_operation (XEXP (x, 0),
7797                                                         next_code),
7798                                i, NULL_RTX, 1, 1, 0, 1);
7799
7800       break;
7801
7802     case LSHIFTRT:
7803       /* If the sign bit is known to be zero, replace this with an
7804          arithmetic shift.  */
7805       if (have_insn_for (ASHIFTRT, mode)
7806           && ! have_insn_for (LSHIFTRT, mode)
7807           && mode_width <= HOST_BITS_PER_WIDE_INT
7808           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7809         {
7810           new_rtx = gen_rtx_ASHIFTRT (mode,
7811                                   make_compound_operation (XEXP (x, 0),
7812                                                            next_code),
7813                                   XEXP (x, 1));
7814           break;
7815         }
7816
7817       /* ... fall through ...  */
7818
7819     case ASHIFTRT:
7820       lhs = XEXP (x, 0);
7821       rhs = XEXP (x, 1);
7822
7823       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7824          this is a SIGN_EXTRACT.  */
7825       if (CONST_INT_P (rhs)
7826           && GET_CODE (lhs) == ASHIFT
7827           && CONST_INT_P (XEXP (lhs, 1))
7828           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7829           && INTVAL (XEXP (lhs, 1)) >= 0
7830           && INTVAL (rhs) < mode_width)
7831         {
7832           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7833           new_rtx = make_extraction (mode, new_rtx,
7834                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7835                                  NULL_RTX, mode_width - INTVAL (rhs),
7836                                  code == LSHIFTRT, 0, in_code == COMPARE);
7837           break;
7838         }
7839
7840       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7841          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7842          also do this for some cases of SIGN_EXTRACT, but it doesn't
7843          seem worth the effort; the case checked for occurs on Alpha.  */
7844
7845       if (!OBJECT_P (lhs)
7846           && ! (GET_CODE (lhs) == SUBREG
7847                 && (OBJECT_P (SUBREG_REG (lhs))))
7848           && CONST_INT_P (rhs)
7849           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7850           && INTVAL (rhs) < mode_width
7851           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7852         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7853                                0, NULL_RTX, mode_width - INTVAL (rhs),
7854                                code == LSHIFTRT, 0, in_code == COMPARE);
7855
7856       break;
7857
7858     case SUBREG:
7859       /* Call ourselves recursively on the inner expression.  If we are
7860          narrowing the object and it has a different RTL code from
7861          what it originally did, do this SUBREG as a force_to_mode.  */
7862       {
7863         rtx inner = SUBREG_REG (x), simplified;
7864
7865         tem = make_compound_operation (inner, in_code);
7866
7867         simplified
7868           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7869         if (simplified)
7870           tem = simplified;
7871
7872         if (GET_CODE (tem) != GET_CODE (inner)
7873             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7874             && subreg_lowpart_p (x))
7875           {
7876             rtx newer
7877               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7878
7879             /* If we have something other than a SUBREG, we might have
7880                done an expansion, so rerun ourselves.  */
7881             if (GET_CODE (newer) != SUBREG)
7882               newer = make_compound_operation (newer, in_code);
7883
7884             /* force_to_mode can expand compounds.  If it just re-expanded the
7885                compound, use gen_lowpart to convert to the desired mode.  */
7886             if (rtx_equal_p (newer, x)
7887                 /* Likewise if it re-expanded the compound only partially.
7888                    This happens for SUBREG of ZERO_EXTRACT if they extract
7889                    the same number of bits.  */
7890                 || (GET_CODE (newer) == SUBREG
7891                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7892                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7893                     && GET_CODE (inner) == AND
7894                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7895               return gen_lowpart (GET_MODE (x), tem);
7896
7897             return newer;
7898           }
7899
7900         if (simplified)
7901           return tem;
7902       }
7903       break;
7904
7905     default:
7906       break;
7907     }
7908
7909   if (new_rtx)
7910     {
7911       x = gen_lowpart (mode, new_rtx);
7912       code = GET_CODE (x);
7913     }
7914
7915   /* Now recursively process each operand of this operation.  We need to
7916      handle ZERO_EXTEND specially so that we don't lose track of the
7917      inner mode.  */
7918   if (GET_CODE (x) == ZERO_EXTEND)
7919     {
7920       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7921       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7922                                             new_rtx, GET_MODE (XEXP (x, 0)));
7923       if (tem)
7924         return tem;
7925       SUBST (XEXP (x, 0), new_rtx);
7926       return x;
7927     }
7928
7929   fmt = GET_RTX_FORMAT (code);
7930   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7931     if (fmt[i] == 'e')
7932       {
7933         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7934         SUBST (XEXP (x, i), new_rtx);
7935       }
7936     else if (fmt[i] == 'E')
7937       for (j = 0; j < XVECLEN (x, i); j++)
7938         {
7939           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7940           SUBST (XVECEXP (x, i, j), new_rtx);
7941         }
7942
7943  maybe_swap:
7944   /* If this is a commutative operation, the changes to the operands
7945      may have made it noncanonical.  */
7946   if (COMMUTATIVE_ARITH_P (x)
7947       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7948     {
7949       tem = XEXP (x, 0);
7950       SUBST (XEXP (x, 0), XEXP (x, 1));
7951       SUBST (XEXP (x, 1), tem);
7952     }
7953
7954   return x;
7955 }
7956 \f
7957 /* Given M see if it is a value that would select a field of bits
7958    within an item, but not the entire word.  Return -1 if not.
7959    Otherwise, return the starting position of the field, where 0 is the
7960    low-order bit.
7961
7962    *PLEN is set to the length of the field.  */
7963
7964 static int
7965 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7966 {
7967   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7968   int pos = m ? ctz_hwi (m) : -1;
7969   int len = 0;
7970
7971   if (pos >= 0)
7972     /* Now shift off the low-order zero bits and see if we have a
7973        power of two minus 1.  */
7974     len = exact_log2 ((m >> pos) + 1);
7975
7976   if (len <= 0)
7977     pos = -1;
7978
7979   *plen = len;
7980   return pos;
7981 }
7982 \f
7983 /* If X refers to a register that equals REG in value, replace these
7984    references with REG.  */
7985 static rtx
7986 canon_reg_for_combine (rtx x, rtx reg)
7987 {
7988   rtx op0, op1, op2;
7989   const char *fmt;
7990   int i;
7991   bool copied;
7992
7993   enum rtx_code code = GET_CODE (x);
7994   switch (GET_RTX_CLASS (code))
7995     {
7996     case RTX_UNARY:
7997       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7998       if (op0 != XEXP (x, 0))
7999         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8000                                    GET_MODE (reg));
8001       break;
8002
8003     case RTX_BIN_ARITH:
8004     case RTX_COMM_ARITH:
8005       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8006       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8007       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8008         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8009       break;
8010
8011     case RTX_COMPARE:
8012     case RTX_COMM_COMPARE:
8013       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8014       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8015       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8016         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8017                                         GET_MODE (op0), op0, op1);
8018       break;
8019
8020     case RTX_TERNARY:
8021     case RTX_BITFIELD_OPS:
8022       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8023       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8024       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8025       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8026         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8027                                      GET_MODE (op0), op0, op1, op2);
8028
8029     case RTX_OBJ:
8030       if (REG_P (x))
8031         {
8032           if (rtx_equal_p (get_last_value (reg), x)
8033               || rtx_equal_p (reg, get_last_value (x)))
8034             return reg;
8035           else
8036             break;
8037         }
8038
8039       /* fall through */
8040
8041     default:
8042       fmt = GET_RTX_FORMAT (code);
8043       copied = false;
8044       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8045         if (fmt[i] == 'e')
8046           {
8047             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8048             if (op != XEXP (x, i))
8049               {
8050                 if (!copied)
8051                   {
8052                     copied = true;
8053                     x = copy_rtx (x);
8054                   }
8055                 XEXP (x, i) = op;
8056               }
8057           }
8058         else if (fmt[i] == 'E')
8059           {
8060             int j;
8061             for (j = 0; j < XVECLEN (x, i); j++)
8062               {
8063                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8064                 if (op != XVECEXP (x, i, j))
8065                   {
8066                     if (!copied)
8067                       {
8068                         copied = true;
8069                         x = copy_rtx (x);
8070                       }
8071                     XVECEXP (x, i, j) = op;
8072                   }
8073               }
8074           }
8075
8076       break;
8077     }
8078
8079   return x;
8080 }
8081
8082 /* Return X converted to MODE.  If the value is already truncated to
8083    MODE we can just return a subreg even though in the general case we
8084    would need an explicit truncation.  */
8085
8086 static rtx
8087 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8088 {
8089   if (!CONST_INT_P (x)
8090       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8091       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8092       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8093     {
8094       /* Bit-cast X into an integer mode.  */
8095       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8096         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8097       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8098                               x, GET_MODE (x));
8099     }
8100
8101   return gen_lowpart (mode, x);
8102 }
8103
8104 /* See if X can be simplified knowing that we will only refer to it in
8105    MODE and will only refer to those bits that are nonzero in MASK.
8106    If other bits are being computed or if masking operations are done
8107    that select a superset of the bits in MASK, they can sometimes be
8108    ignored.
8109
8110    Return a possibly simplified expression, but always convert X to
8111    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8112
8113    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8114    are all off in X.  This is used when X will be complemented, by either
8115    NOT, NEG, or XOR.  */
8116
8117 static rtx
8118 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8119                int just_select)
8120 {
8121   enum rtx_code code = GET_CODE (x);
8122   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8123   enum machine_mode op_mode;
8124   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8125   rtx op0, op1, temp;
8126
8127   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8128      code below will do the wrong thing since the mode of such an
8129      expression is VOIDmode.
8130
8131      Also do nothing if X is a CLOBBER; this can happen if X was
8132      the return value from a call to gen_lowpart.  */
8133   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8134     return x;
8135
8136   /* We want to perform the operation is its present mode unless we know
8137      that the operation is valid in MODE, in which case we do the operation
8138      in MODE.  */
8139   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8140               && have_insn_for (code, mode))
8141              ? mode : GET_MODE (x));
8142
8143   /* It is not valid to do a right-shift in a narrower mode
8144      than the one it came in with.  */
8145   if ((code == LSHIFTRT || code == ASHIFTRT)
8146       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8147     op_mode = GET_MODE (x);
8148
8149   /* Truncate MASK to fit OP_MODE.  */
8150   if (op_mode)
8151     mask &= GET_MODE_MASK (op_mode);
8152
8153   /* When we have an arithmetic operation, or a shift whose count we
8154      do not know, we need to assume that all bits up to the highest-order
8155      bit in MASK will be needed.  This is how we form such a mask.  */
8156   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8157     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8158   else
8159     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8160                    - 1);
8161
8162   /* Determine what bits of X are guaranteed to be (non)zero.  */
8163   nonzero = nonzero_bits (x, mode);
8164
8165   /* If none of the bits in X are needed, return a zero.  */
8166   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8167     x = const0_rtx;
8168
8169   /* If X is a CONST_INT, return a new one.  Do this here since the
8170      test below will fail.  */
8171   if (CONST_INT_P (x))
8172     {
8173       if (SCALAR_INT_MODE_P (mode))
8174         return gen_int_mode (INTVAL (x) & mask, mode);
8175       else
8176         {
8177           x = GEN_INT (INTVAL (x) & mask);
8178           return gen_lowpart_common (mode, x);
8179         }
8180     }
8181
8182   /* If X is narrower than MODE and we want all the bits in X's mode, just
8183      get X in the proper mode.  */
8184   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8185       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8186     return gen_lowpart (mode, x);
8187
8188   /* We can ignore the effect of a SUBREG if it narrows the mode or
8189      if the constant masks to zero all the bits the mode doesn't have.  */
8190   if (GET_CODE (x) == SUBREG
8191       && subreg_lowpart_p (x)
8192       && ((GET_MODE_SIZE (GET_MODE (x))
8193            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8194           || (0 == (mask
8195                     & GET_MODE_MASK (GET_MODE (x))
8196                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8197     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8198
8199   /* The arithmetic simplifications here only work for scalar integer modes.  */
8200   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8201     return gen_lowpart_or_truncate (mode, x);
8202
8203   switch (code)
8204     {
8205     case CLOBBER:
8206       /* If X is a (clobber (const_int)), return it since we know we are
8207          generating something that won't match.  */
8208       return x;
8209
8210     case SIGN_EXTEND:
8211     case ZERO_EXTEND:
8212     case ZERO_EXTRACT:
8213     case SIGN_EXTRACT:
8214       x = expand_compound_operation (x);
8215       if (GET_CODE (x) != code)
8216         return force_to_mode (x, mode, mask, next_select);
8217       break;
8218
8219     case TRUNCATE:
8220       /* Similarly for a truncate.  */
8221       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8222
8223     case AND:
8224       /* If this is an AND with a constant, convert it into an AND
8225          whose constant is the AND of that constant with MASK.  If it
8226          remains an AND of MASK, delete it since it is redundant.  */
8227
8228       if (CONST_INT_P (XEXP (x, 1)))
8229         {
8230           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8231                                       mask & INTVAL (XEXP (x, 1)));
8232
8233           /* If X is still an AND, see if it is an AND with a mask that
8234              is just some low-order bits.  If so, and it is MASK, we don't
8235              need it.  */
8236
8237           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8238               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8239                   == mask))
8240             x = XEXP (x, 0);
8241
8242           /* If it remains an AND, try making another AND with the bits
8243              in the mode mask that aren't in MASK turned on.  If the
8244              constant in the AND is wide enough, this might make a
8245              cheaper constant.  */
8246
8247           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8248               && GET_MODE_MASK (GET_MODE (x)) != mask
8249               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8250             {
8251               unsigned HOST_WIDE_INT cval
8252                 = UINTVAL (XEXP (x, 1))
8253                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8254               int width = GET_MODE_PRECISION (GET_MODE (x));
8255               rtx y;
8256
8257               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8258                  number, sign extend it.  */
8259               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8260                   && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8261                 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8262
8263               y = simplify_gen_binary (AND, GET_MODE (x),
8264                                        XEXP (x, 0), GEN_INT (cval));
8265               if (set_src_cost (y, optimize_this_for_speed_p)
8266                   < set_src_cost (x, optimize_this_for_speed_p))
8267                 x = y;
8268             }
8269
8270           break;
8271         }
8272
8273       goto binop;
8274
8275     case PLUS:
8276       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8277          low-order bits (as in an alignment operation) and FOO is already
8278          aligned to that boundary, mask C1 to that boundary as well.
8279          This may eliminate that PLUS and, later, the AND.  */
8280
8281       {
8282         unsigned int width = GET_MODE_PRECISION (mode);
8283         unsigned HOST_WIDE_INT smask = mask;
8284
8285         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8286            number, sign extend it.  */
8287
8288         if (width < HOST_BITS_PER_WIDE_INT
8289             && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8290           smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8291
8292         if (CONST_INT_P (XEXP (x, 1))
8293             && exact_log2 (- smask) >= 0
8294             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8295             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8296           return force_to_mode (plus_constant (XEXP (x, 0),
8297                                                (INTVAL (XEXP (x, 1)) & smask)),
8298                                 mode, smask, next_select);
8299       }
8300
8301       /* ... fall through ...  */
8302
8303     case MULT:
8304       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8305          most significant bit in MASK since carries from those bits will
8306          affect the bits we are interested in.  */
8307       mask = fuller_mask;
8308       goto binop;
8309
8310     case MINUS:
8311       /* If X is (minus C Y) where C's least set bit is larger than any bit
8312          in the mask, then we may replace with (neg Y).  */
8313       if (CONST_INT_P (XEXP (x, 0))
8314           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8315                                         & -INTVAL (XEXP (x, 0))))
8316               > mask))
8317         {
8318           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8319                                   GET_MODE (x));
8320           return force_to_mode (x, mode, mask, next_select);
8321         }
8322
8323       /* Similarly, if C contains every bit in the fuller_mask, then we may
8324          replace with (not Y).  */
8325       if (CONST_INT_P (XEXP (x, 0))
8326           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8327         {
8328           x = simplify_gen_unary (NOT, GET_MODE (x),
8329                                   XEXP (x, 1), GET_MODE (x));
8330           return force_to_mode (x, mode, mask, next_select);
8331         }
8332
8333       mask = fuller_mask;
8334       goto binop;
8335
8336     case IOR:
8337     case XOR:
8338       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8339          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8340          operation which may be a bitfield extraction.  Ensure that the
8341          constant we form is not wider than the mode of X.  */
8342
8343       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8344           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8345           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8346           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8347           && CONST_INT_P (XEXP (x, 1))
8348           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8349                + floor_log2 (INTVAL (XEXP (x, 1))))
8350               < GET_MODE_PRECISION (GET_MODE (x)))
8351           && (UINTVAL (XEXP (x, 1))
8352               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8353         {
8354           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8355                           << INTVAL (XEXP (XEXP (x, 0), 1)));
8356           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8357                                       XEXP (XEXP (x, 0), 0), temp);
8358           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8359                                    XEXP (XEXP (x, 0), 1));
8360           return force_to_mode (x, mode, mask, next_select);
8361         }
8362
8363     binop:
8364       /* For most binary operations, just propagate into the operation and
8365          change the mode if we have an operation of that mode.  */
8366
8367       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8368       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8369
8370       /* If we ended up truncating both operands, truncate the result of the
8371          operation instead.  */
8372       if (GET_CODE (op0) == TRUNCATE
8373           && GET_CODE (op1) == TRUNCATE)
8374         {
8375           op0 = XEXP (op0, 0);
8376           op1 = XEXP (op1, 0);
8377         }
8378
8379       op0 = gen_lowpart_or_truncate (op_mode, op0);
8380       op1 = gen_lowpart_or_truncate (op_mode, op1);
8381
8382       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8383         x = simplify_gen_binary (code, op_mode, op0, op1);
8384       break;
8385
8386     case ASHIFT:
8387       /* For left shifts, do the same, but just for the first operand.
8388          However, we cannot do anything with shifts where we cannot
8389          guarantee that the counts are smaller than the size of the mode
8390          because such a count will have a different meaning in a
8391          wider mode.  */
8392
8393       if (! (CONST_INT_P (XEXP (x, 1))
8394              && INTVAL (XEXP (x, 1)) >= 0
8395              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8396           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8397                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8398                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8399         break;
8400
8401       /* If the shift count is a constant and we can do arithmetic in
8402          the mode of the shift, refine which bits we need.  Otherwise, use the
8403          conservative form of the mask.  */
8404       if (CONST_INT_P (XEXP (x, 1))
8405           && INTVAL (XEXP (x, 1)) >= 0
8406           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8407           && HWI_COMPUTABLE_MODE_P (op_mode))
8408         mask >>= INTVAL (XEXP (x, 1));
8409       else
8410         mask = fuller_mask;
8411
8412       op0 = gen_lowpart_or_truncate (op_mode,
8413                                      force_to_mode (XEXP (x, 0), op_mode,
8414                                                     mask, next_select));
8415
8416       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8417         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8418       break;
8419
8420     case LSHIFTRT:
8421       /* Here we can only do something if the shift count is a constant,
8422          this shift constant is valid for the host, and we can do arithmetic
8423          in OP_MODE.  */
8424
8425       if (CONST_INT_P (XEXP (x, 1))
8426           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8427           && HWI_COMPUTABLE_MODE_P (op_mode))
8428         {
8429           rtx inner = XEXP (x, 0);
8430           unsigned HOST_WIDE_INT inner_mask;
8431
8432           /* Select the mask of the bits we need for the shift operand.  */
8433           inner_mask = mask << INTVAL (XEXP (x, 1));
8434
8435           /* We can only change the mode of the shift if we can do arithmetic
8436              in the mode of the shift and INNER_MASK is no wider than the
8437              width of X's mode.  */
8438           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8439             op_mode = GET_MODE (x);
8440
8441           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8442
8443           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8444             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8445         }
8446
8447       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8448          shift and AND produces only copies of the sign bit (C2 is one less
8449          than a power of two), we can do this with just a shift.  */
8450
8451       if (GET_CODE (x) == LSHIFTRT
8452           && CONST_INT_P (XEXP (x, 1))
8453           /* The shift puts one of the sign bit copies in the least significant
8454              bit.  */
8455           && ((INTVAL (XEXP (x, 1))
8456                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8457               >= GET_MODE_PRECISION (GET_MODE (x)))
8458           && exact_log2 (mask + 1) >= 0
8459           /* Number of bits left after the shift must be more than the mask
8460              needs.  */
8461           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8462               <= GET_MODE_PRECISION (GET_MODE (x)))
8463           /* Must be more sign bit copies than the mask needs.  */
8464           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8465               >= exact_log2 (mask + 1)))
8466         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8467                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8468                                           - exact_log2 (mask + 1)));
8469
8470       goto shiftrt;
8471
8472     case ASHIFTRT:
8473       /* If we are just looking for the sign bit, we don't need this shift at
8474          all, even if it has a variable count.  */
8475       if (val_signbit_p (GET_MODE (x), mask))
8476         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8477
8478       /* If this is a shift by a constant, get a mask that contains those bits
8479          that are not copies of the sign bit.  We then have two cases:  If
8480          MASK only includes those bits, this can be a logical shift, which may
8481          allow simplifications.  If MASK is a single-bit field not within
8482          those bits, we are requesting a copy of the sign bit and hence can
8483          shift the sign bit to the appropriate location.  */
8484
8485       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8486           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8487         {
8488           int i;
8489
8490           /* If the considered data is wider than HOST_WIDE_INT, we can't
8491              represent a mask for all its bits in a single scalar.
8492              But we only care about the lower bits, so calculate these.  */
8493
8494           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8495             {
8496               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8497
8498               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8499                  is the number of bits a full-width mask would have set.
8500                  We need only shift if these are fewer than nonzero can
8501                  hold.  If not, we must keep all bits set in nonzero.  */
8502
8503               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8504                   < HOST_BITS_PER_WIDE_INT)
8505                 nonzero >>= INTVAL (XEXP (x, 1))
8506                             + HOST_BITS_PER_WIDE_INT
8507                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8508             }
8509           else
8510             {
8511               nonzero = GET_MODE_MASK (GET_MODE (x));
8512               nonzero >>= INTVAL (XEXP (x, 1));
8513             }
8514
8515           if ((mask & ~nonzero) == 0)
8516             {
8517               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8518                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8519               if (GET_CODE (x) != ASHIFTRT)
8520                 return force_to_mode (x, mode, mask, next_select);
8521             }
8522
8523           else if ((i = exact_log2 (mask)) >= 0)
8524             {
8525               x = simplify_shift_const
8526                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8527                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8528
8529               if (GET_CODE (x) != ASHIFTRT)
8530                 return force_to_mode (x, mode, mask, next_select);
8531             }
8532         }
8533
8534       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8535          even if the shift count isn't a constant.  */
8536       if (mask == 1)
8537         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8538                                  XEXP (x, 0), XEXP (x, 1));
8539
8540     shiftrt:
8541
8542       /* If this is a zero- or sign-extension operation that just affects bits
8543          we don't care about, remove it.  Be sure the call above returned
8544          something that is still a shift.  */
8545
8546       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8547           && CONST_INT_P (XEXP (x, 1))
8548           && INTVAL (XEXP (x, 1)) >= 0
8549           && (INTVAL (XEXP (x, 1))
8550               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8551           && GET_CODE (XEXP (x, 0)) == ASHIFT
8552           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8553         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8554                               next_select);
8555
8556       break;
8557
8558     case ROTATE:
8559     case ROTATERT:
8560       /* If the shift count is constant and we can do computations
8561          in the mode of X, compute where the bits we care about are.
8562          Otherwise, we can't do anything.  Don't change the mode of
8563          the shift or propagate MODE into the shift, though.  */
8564       if (CONST_INT_P (XEXP (x, 1))
8565           && INTVAL (XEXP (x, 1)) >= 0)
8566         {
8567           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8568                                             GET_MODE (x), GEN_INT (mask),
8569                                             XEXP (x, 1));
8570           if (temp && CONST_INT_P (temp))
8571             SUBST (XEXP (x, 0),
8572                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8573                                   INTVAL (temp), next_select));
8574         }
8575       break;
8576
8577     case NEG:
8578       /* If we just want the low-order bit, the NEG isn't needed since it
8579          won't change the low-order bit.  */
8580       if (mask == 1)
8581         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8582
8583       /* We need any bits less significant than the most significant bit in
8584          MASK since carries from those bits will affect the bits we are
8585          interested in.  */
8586       mask = fuller_mask;
8587       goto unop;
8588
8589     case NOT:
8590       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8591          same as the XOR case above.  Ensure that the constant we form is not
8592          wider than the mode of X.  */
8593
8594       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8595           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8596           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8597           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8598               < GET_MODE_PRECISION (GET_MODE (x)))
8599           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8600         {
8601           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8602                                GET_MODE (x));
8603           temp = simplify_gen_binary (XOR, GET_MODE (x),
8604                                       XEXP (XEXP (x, 0), 0), temp);
8605           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8606                                    temp, XEXP (XEXP (x, 0), 1));
8607
8608           return force_to_mode (x, mode, mask, next_select);
8609         }
8610
8611       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8612          use the full mask inside the NOT.  */
8613       mask = fuller_mask;
8614
8615     unop:
8616       op0 = gen_lowpart_or_truncate (op_mode,
8617                                      force_to_mode (XEXP (x, 0), mode, mask,
8618                                                     next_select));
8619       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8620         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8621       break;
8622
8623     case NE:
8624       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8625          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8626          which is equal to STORE_FLAG_VALUE.  */
8627       if ((mask & ~STORE_FLAG_VALUE) == 0
8628           && XEXP (x, 1) == const0_rtx
8629           && GET_MODE (XEXP (x, 0)) == mode
8630           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8631           && (nonzero_bits (XEXP (x, 0), mode)
8632               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8633         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8634
8635       break;
8636
8637     case IF_THEN_ELSE:
8638       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8639          written in a narrower mode.  We play it safe and do not do so.  */
8640
8641       SUBST (XEXP (x, 1),
8642              gen_lowpart_or_truncate (GET_MODE (x),
8643                                       force_to_mode (XEXP (x, 1), mode,
8644                                                      mask, next_select)));
8645       SUBST (XEXP (x, 2),
8646              gen_lowpart_or_truncate (GET_MODE (x),
8647                                       force_to_mode (XEXP (x, 2), mode,
8648                                                      mask, next_select)));
8649       break;
8650
8651     default:
8652       break;
8653     }
8654
8655   /* Ensure we return a value of the proper mode.  */
8656   return gen_lowpart_or_truncate (mode, x);
8657 }
8658 \f
8659 /* Return nonzero if X is an expression that has one of two values depending on
8660    whether some other value is zero or nonzero.  In that case, we return the
8661    value that is being tested, *PTRUE is set to the value if the rtx being
8662    returned has a nonzero value, and *PFALSE is set to the other alternative.
8663
8664    If we return zero, we set *PTRUE and *PFALSE to X.  */
8665
8666 static rtx
8667 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8668 {
8669   enum machine_mode mode = GET_MODE (x);
8670   enum rtx_code code = GET_CODE (x);
8671   rtx cond0, cond1, true0, true1, false0, false1;
8672   unsigned HOST_WIDE_INT nz;
8673
8674   /* If we are comparing a value against zero, we are done.  */
8675   if ((code == NE || code == EQ)
8676       && XEXP (x, 1) == const0_rtx)
8677     {
8678       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8679       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8680       return XEXP (x, 0);
8681     }
8682
8683   /* If this is a unary operation whose operand has one of two values, apply
8684      our opcode to compute those values.  */
8685   else if (UNARY_P (x)
8686            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8687     {
8688       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8689       *pfalse = simplify_gen_unary (code, mode, false0,
8690                                     GET_MODE (XEXP (x, 0)));
8691       return cond0;
8692     }
8693
8694   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8695      make can't possibly match and would suppress other optimizations.  */
8696   else if (code == COMPARE)
8697     ;
8698
8699   /* If this is a binary operation, see if either side has only one of two
8700      values.  If either one does or if both do and they are conditional on
8701      the same value, compute the new true and false values.  */
8702   else if (BINARY_P (x))
8703     {
8704       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8705       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8706
8707       if ((cond0 != 0 || cond1 != 0)
8708           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8709         {
8710           /* If if_then_else_cond returned zero, then true/false are the
8711              same rtl.  We must copy one of them to prevent invalid rtl
8712              sharing.  */
8713           if (cond0 == 0)
8714             true0 = copy_rtx (true0);
8715           else if (cond1 == 0)
8716             true1 = copy_rtx (true1);
8717
8718           if (COMPARISON_P (x))
8719             {
8720               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8721                                                 true0, true1);
8722               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8723                                                  false0, false1);
8724              }
8725           else
8726             {
8727               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8728               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8729             }
8730
8731           return cond0 ? cond0 : cond1;
8732         }
8733
8734       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8735          operands is zero when the other is nonzero, and vice-versa,
8736          and STORE_FLAG_VALUE is 1 or -1.  */
8737
8738       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8739           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8740               || code == UMAX)
8741           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8742         {
8743           rtx op0 = XEXP (XEXP (x, 0), 1);
8744           rtx op1 = XEXP (XEXP (x, 1), 1);
8745
8746           cond0 = XEXP (XEXP (x, 0), 0);
8747           cond1 = XEXP (XEXP (x, 1), 0);
8748
8749           if (COMPARISON_P (cond0)
8750               && COMPARISON_P (cond1)
8751               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8752                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8753                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8754                   || ((swap_condition (GET_CODE (cond0))
8755                        == reversed_comparison_code (cond1, NULL))
8756                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8757                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8758               && ! side_effects_p (x))
8759             {
8760               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8761               *pfalse = simplify_gen_binary (MULT, mode,
8762                                              (code == MINUS
8763                                               ? simplify_gen_unary (NEG, mode,
8764                                                                     op1, mode)
8765                                               : op1),
8766                                               const_true_rtx);
8767               return cond0;
8768             }
8769         }
8770
8771       /* Similarly for MULT, AND and UMIN, except that for these the result
8772          is always zero.  */
8773       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8774           && (code == MULT || code == AND || code == UMIN)
8775           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8776         {
8777           cond0 = XEXP (XEXP (x, 0), 0);
8778           cond1 = XEXP (XEXP (x, 1), 0);
8779
8780           if (COMPARISON_P (cond0)
8781               && COMPARISON_P (cond1)
8782               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8783                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8784                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8785                   || ((swap_condition (GET_CODE (cond0))
8786                        == reversed_comparison_code (cond1, NULL))
8787                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8788                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8789               && ! side_effects_p (x))
8790             {
8791               *ptrue = *pfalse = const0_rtx;
8792               return cond0;
8793             }
8794         }
8795     }
8796
8797   else if (code == IF_THEN_ELSE)
8798     {
8799       /* If we have IF_THEN_ELSE already, extract the condition and
8800          canonicalize it if it is NE or EQ.  */
8801       cond0 = XEXP (x, 0);
8802       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8803       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8804         return XEXP (cond0, 0);
8805       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8806         {
8807           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8808           return XEXP (cond0, 0);
8809         }
8810       else
8811         return cond0;
8812     }
8813
8814   /* If X is a SUBREG, we can narrow both the true and false values
8815      if the inner expression, if there is a condition.  */
8816   else if (code == SUBREG
8817            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8818                                                &true0, &false0)))
8819     {
8820       true0 = simplify_gen_subreg (mode, true0,
8821                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8822       false0 = simplify_gen_subreg (mode, false0,
8823                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8824       if (true0 && false0)
8825         {
8826           *ptrue = true0;
8827           *pfalse = false0;
8828           return cond0;
8829         }
8830     }
8831
8832   /* If X is a constant, this isn't special and will cause confusions
8833      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8834   else if (CONSTANT_P (x)
8835            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8836     ;
8837
8838   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8839      will be least confusing to the rest of the compiler.  */
8840   else if (mode == BImode)
8841     {
8842       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8843       return x;
8844     }
8845
8846   /* If X is known to be either 0 or -1, those are the true and
8847      false values when testing X.  */
8848   else if (x == constm1_rtx || x == const0_rtx
8849            || (mode != VOIDmode
8850                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8851     {
8852       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8853       return x;
8854     }
8855
8856   /* Likewise for 0 or a single bit.  */
8857   else if (HWI_COMPUTABLE_MODE_P (mode)
8858            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8859     {
8860       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8861       return x;
8862     }
8863
8864   /* Otherwise fail; show no condition with true and false values the same.  */
8865   *ptrue = *pfalse = x;
8866   return 0;
8867 }
8868 \f
8869 /* Return the value of expression X given the fact that condition COND
8870    is known to be true when applied to REG as its first operand and VAL
8871    as its second.  X is known to not be shared and so can be modified in
8872    place.
8873
8874    We only handle the simplest cases, and specifically those cases that
8875    arise with IF_THEN_ELSE expressions.  */
8876
8877 static rtx
8878 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8879 {
8880   enum rtx_code code = GET_CODE (x);
8881   rtx temp;
8882   const char *fmt;
8883   int i, j;
8884
8885   if (side_effects_p (x))
8886     return x;
8887
8888   /* If either operand of the condition is a floating point value,
8889      then we have to avoid collapsing an EQ comparison.  */
8890   if (cond == EQ
8891       && rtx_equal_p (x, reg)
8892       && ! FLOAT_MODE_P (GET_MODE (x))
8893       && ! FLOAT_MODE_P (GET_MODE (val)))
8894     return val;
8895
8896   if (cond == UNEQ && rtx_equal_p (x, reg))
8897     return val;
8898
8899   /* If X is (abs REG) and we know something about REG's relationship
8900      with zero, we may be able to simplify this.  */
8901
8902   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8903     switch (cond)
8904       {
8905       case GE:  case GT:  case EQ:
8906         return XEXP (x, 0);
8907       case LT:  case LE:
8908         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8909                                    XEXP (x, 0),
8910                                    GET_MODE (XEXP (x, 0)));
8911       default:
8912         break;
8913       }
8914
8915   /* The only other cases we handle are MIN, MAX, and comparisons if the
8916      operands are the same as REG and VAL.  */
8917
8918   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8919     {
8920       if (rtx_equal_p (XEXP (x, 0), val))
8921         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8922
8923       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8924         {
8925           if (COMPARISON_P (x))
8926             {
8927               if (comparison_dominates_p (cond, code))
8928                 return const_true_rtx;
8929
8930               code = reversed_comparison_code (x, NULL);
8931               if (code != UNKNOWN
8932                   && comparison_dominates_p (cond, code))
8933                 return const0_rtx;
8934               else
8935                 return x;
8936             }
8937           else if (code == SMAX || code == SMIN
8938                    || code == UMIN || code == UMAX)
8939             {
8940               int unsignedp = (code == UMIN || code == UMAX);
8941
8942               /* Do not reverse the condition when it is NE or EQ.
8943                  This is because we cannot conclude anything about
8944                  the value of 'SMAX (x, y)' when x is not equal to y,
8945                  but we can when x equals y.  */
8946               if ((code == SMAX || code == UMAX)
8947                   && ! (cond == EQ || cond == NE))
8948                 cond = reverse_condition (cond);
8949
8950               switch (cond)
8951                 {
8952                 case GE:   case GT:
8953                   return unsignedp ? x : XEXP (x, 1);
8954                 case LE:   case LT:
8955                   return unsignedp ? x : XEXP (x, 0);
8956                 case GEU:  case GTU:
8957                   return unsignedp ? XEXP (x, 1) : x;
8958                 case LEU:  case LTU:
8959                   return unsignedp ? XEXP (x, 0) : x;
8960                 default:
8961                   break;
8962                 }
8963             }
8964         }
8965     }
8966   else if (code == SUBREG)
8967     {
8968       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8969       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8970
8971       if (SUBREG_REG (x) != r)
8972         {
8973           /* We must simplify subreg here, before we lose track of the
8974              original inner_mode.  */
8975           new_rtx = simplify_subreg (GET_MODE (x), r,
8976                                  inner_mode, SUBREG_BYTE (x));
8977           if (new_rtx)
8978             return new_rtx;
8979           else
8980             SUBST (SUBREG_REG (x), r);
8981         }
8982
8983       return x;
8984     }
8985   /* We don't have to handle SIGN_EXTEND here, because even in the
8986      case of replacing something with a modeless CONST_INT, a
8987      CONST_INT is already (supposed to be) a valid sign extension for
8988      its narrower mode, which implies it's already properly
8989      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8990      story is different.  */
8991   else if (code == ZERO_EXTEND)
8992     {
8993       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8994       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8995
8996       if (XEXP (x, 0) != r)
8997         {
8998           /* We must simplify the zero_extend here, before we lose
8999              track of the original inner_mode.  */
9000           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9001                                           r, inner_mode);
9002           if (new_rtx)
9003             return new_rtx;
9004           else
9005             SUBST (XEXP (x, 0), r);
9006         }
9007
9008       return x;
9009     }
9010
9011   fmt = GET_RTX_FORMAT (code);
9012   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9013     {
9014       if (fmt[i] == 'e')
9015         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9016       else if (fmt[i] == 'E')
9017         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9018           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9019                                                 cond, reg, val));
9020     }
9021
9022   return x;
9023 }
9024 \f
9025 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9026    assignment as a field assignment.  */
9027
9028 static int
9029 rtx_equal_for_field_assignment_p (rtx x, rtx y)
9030 {
9031   if (x == y || rtx_equal_p (x, y))
9032     return 1;
9033
9034   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9035     return 0;
9036
9037   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9038      Note that all SUBREGs of MEM are paradoxical; otherwise they
9039      would have been rewritten.  */
9040   if (MEM_P (x) && GET_CODE (y) == SUBREG
9041       && MEM_P (SUBREG_REG (y))
9042       && rtx_equal_p (SUBREG_REG (y),
9043                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9044     return 1;
9045
9046   if (MEM_P (y) && GET_CODE (x) == SUBREG
9047       && MEM_P (SUBREG_REG (x))
9048       && rtx_equal_p (SUBREG_REG (x),
9049                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9050     return 1;
9051
9052   /* We used to see if get_last_value of X and Y were the same but that's
9053      not correct.  In one direction, we'll cause the assignment to have
9054      the wrong destination and in the case, we'll import a register into this
9055      insn that might have already have been dead.   So fail if none of the
9056      above cases are true.  */
9057   return 0;
9058 }
9059 \f
9060 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9061    Return that assignment if so.
9062
9063    We only handle the most common cases.  */
9064
9065 static rtx
9066 make_field_assignment (rtx x)
9067 {
9068   rtx dest = SET_DEST (x);
9069   rtx src = SET_SRC (x);
9070   rtx assign;
9071   rtx rhs, lhs;
9072   HOST_WIDE_INT c1;
9073   HOST_WIDE_INT pos;
9074   unsigned HOST_WIDE_INT len;
9075   rtx other;
9076   enum machine_mode mode;
9077
9078   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9079      a clear of a one-bit field.  We will have changed it to
9080      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
9081      for a SUBREG.  */
9082
9083   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9084       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9085       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9086       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9087     {
9088       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9089                                 1, 1, 1, 0);
9090       if (assign != 0)
9091         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9092       return x;
9093     }
9094
9095   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9096       && subreg_lowpart_p (XEXP (src, 0))
9097       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9098           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9099       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9100       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9101       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9102       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9103     {
9104       assign = make_extraction (VOIDmode, dest, 0,
9105                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9106                                 1, 1, 1, 0);
9107       if (assign != 0)
9108         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9109       return x;
9110     }
9111
9112   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9113      one-bit field.  */
9114   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9115       && XEXP (XEXP (src, 0), 0) == const1_rtx
9116       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9117     {
9118       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9119                                 1, 1, 1, 0);
9120       if (assign != 0)
9121         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9122       return x;
9123     }
9124
9125   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9126      SRC is an AND with all bits of that field set, then we can discard
9127      the AND.  */
9128   if (GET_CODE (dest) == ZERO_EXTRACT
9129       && CONST_INT_P (XEXP (dest, 1))
9130       && GET_CODE (src) == AND
9131       && CONST_INT_P (XEXP (src, 1)))
9132     {
9133       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9134       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9135       unsigned HOST_WIDE_INT ze_mask;
9136
9137       if (width >= HOST_BITS_PER_WIDE_INT)
9138         ze_mask = -1;
9139       else
9140         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9141
9142       /* Complete overlap.  We can remove the source AND.  */
9143       if ((and_mask & ze_mask) == ze_mask)
9144         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9145
9146       /* Partial overlap.  We can reduce the source AND.  */
9147       if ((and_mask & ze_mask) != and_mask)
9148         {
9149           mode = GET_MODE (src);
9150           src = gen_rtx_AND (mode, XEXP (src, 0),
9151                              gen_int_mode (and_mask & ze_mask, mode));
9152           return gen_rtx_SET (VOIDmode, dest, src);
9153         }
9154     }
9155
9156   /* The other case we handle is assignments into a constant-position
9157      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9158      a mask that has all one bits except for a group of zero bits and
9159      OTHER is known to have zeros where C1 has ones, this is such an
9160      assignment.  Compute the position and length from C1.  Shift OTHER
9161      to the appropriate position, force it to the required mode, and
9162      make the extraction.  Check for the AND in both operands.  */
9163
9164   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9165     return x;
9166
9167   rhs = expand_compound_operation (XEXP (src, 0));
9168   lhs = expand_compound_operation (XEXP (src, 1));
9169
9170   if (GET_CODE (rhs) == AND
9171       && CONST_INT_P (XEXP (rhs, 1))
9172       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9173     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9174   else if (GET_CODE (lhs) == AND
9175            && CONST_INT_P (XEXP (lhs, 1))
9176            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9177     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9178   else
9179     return x;
9180
9181   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9182   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9183       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9184       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9185     return x;
9186
9187   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9188   if (assign == 0)
9189     return x;
9190
9191   /* The mode to use for the source is the mode of the assignment, or of
9192      what is inside a possible STRICT_LOW_PART.  */
9193   mode = (GET_CODE (assign) == STRICT_LOW_PART
9194           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9195
9196   /* Shift OTHER right POS places and make it the source, restricting it
9197      to the proper length and mode.  */
9198
9199   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9200                                                      GET_MODE (src),
9201                                                      other, pos),
9202                                dest);
9203   src = force_to_mode (src, mode,
9204                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9205                        ? ~(unsigned HOST_WIDE_INT) 0
9206                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9207                        0);
9208
9209   /* If SRC is masked by an AND that does not make a difference in
9210      the value being stored, strip it.  */
9211   if (GET_CODE (assign) == ZERO_EXTRACT
9212       && CONST_INT_P (XEXP (assign, 1))
9213       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9214       && GET_CODE (src) == AND
9215       && CONST_INT_P (XEXP (src, 1))
9216       && UINTVAL (XEXP (src, 1))
9217          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9218     src = XEXP (src, 0);
9219
9220   return gen_rtx_SET (VOIDmode, assign, src);
9221 }
9222 \f
9223 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9224    if so.  */
9225
9226 static rtx
9227 apply_distributive_law (rtx x)
9228 {
9229   enum rtx_code code = GET_CODE (x);
9230   enum rtx_code inner_code;
9231   rtx lhs, rhs, other;
9232   rtx tem;
9233
9234   /* Distributivity is not true for floating point as it can change the
9235      value.  So we don't do it unless -funsafe-math-optimizations.  */
9236   if (FLOAT_MODE_P (GET_MODE (x))
9237       && ! flag_unsafe_math_optimizations)
9238     return x;
9239
9240   /* The outer operation can only be one of the following:  */
9241   if (code != IOR && code != AND && code != XOR
9242       && code != PLUS && code != MINUS)
9243     return x;
9244
9245   lhs = XEXP (x, 0);
9246   rhs = XEXP (x, 1);
9247
9248   /* If either operand is a primitive we can't do anything, so get out
9249      fast.  */
9250   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9251     return x;
9252
9253   lhs = expand_compound_operation (lhs);
9254   rhs = expand_compound_operation (rhs);
9255   inner_code = GET_CODE (lhs);
9256   if (inner_code != GET_CODE (rhs))
9257     return x;
9258
9259   /* See if the inner and outer operations distribute.  */
9260   switch (inner_code)
9261     {
9262     case LSHIFTRT:
9263     case ASHIFTRT:
9264     case AND:
9265     case IOR:
9266       /* These all distribute except over PLUS.  */
9267       if (code == PLUS || code == MINUS)
9268         return x;
9269       break;
9270
9271     case MULT:
9272       if (code != PLUS && code != MINUS)
9273         return x;
9274       break;
9275
9276     case ASHIFT:
9277       /* This is also a multiply, so it distributes over everything.  */
9278       break;
9279
9280     case SUBREG:
9281       /* Non-paradoxical SUBREGs distributes over all operations,
9282          provided the inner modes and byte offsets are the same, this
9283          is an extraction of a low-order part, we don't convert an fp
9284          operation to int or vice versa, this is not a vector mode,
9285          and we would not be converting a single-word operation into a
9286          multi-word operation.  The latter test is not required, but
9287          it prevents generating unneeded multi-word operations.  Some
9288          of the previous tests are redundant given the latter test,
9289          but are retained because they are required for correctness.
9290
9291          We produce the result slightly differently in this case.  */
9292
9293       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9294           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9295           || ! subreg_lowpart_p (lhs)
9296           || (GET_MODE_CLASS (GET_MODE (lhs))
9297               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9298           || paradoxical_subreg_p (lhs)
9299           || VECTOR_MODE_P (GET_MODE (lhs))
9300           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9301           /* Result might need to be truncated.  Don't change mode if
9302              explicit truncation is needed.  */
9303           || !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x),
9304                                              GET_MODE (SUBREG_REG (lhs))))
9305         return x;
9306
9307       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9308                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
9309       return gen_lowpart (GET_MODE (x), tem);
9310
9311     default:
9312       return x;
9313     }
9314
9315   /* Set LHS and RHS to the inner operands (A and B in the example
9316      above) and set OTHER to the common operand (C in the example).
9317      There is only one way to do this unless the inner operation is
9318      commutative.  */
9319   if (COMMUTATIVE_ARITH_P (lhs)
9320       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9321     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9322   else if (COMMUTATIVE_ARITH_P (lhs)
9323            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9324     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9325   else if (COMMUTATIVE_ARITH_P (lhs)
9326            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9327     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9328   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9329     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9330   else
9331     return x;
9332
9333   /* Form the new inner operation, seeing if it simplifies first.  */
9334   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9335
9336   /* There is one exception to the general way of distributing:
9337      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9338   if (code == XOR && inner_code == IOR)
9339     {
9340       inner_code = AND;
9341       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9342     }
9343
9344   /* We may be able to continuing distributing the result, so call
9345      ourselves recursively on the inner operation before forming the
9346      outer operation, which we return.  */
9347   return simplify_gen_binary (inner_code, GET_MODE (x),
9348                               apply_distributive_law (tem), other);
9349 }
9350
9351 /* See if X is of the form (* (+ A B) C), and if so convert to
9352    (+ (* A C) (* B C)) and try to simplify.
9353
9354    Most of the time, this results in no change.  However, if some of
9355    the operands are the same or inverses of each other, simplifications
9356    will result.
9357
9358    For example, (and (ior A B) (not B)) can occur as the result of
9359    expanding a bit field assignment.  When we apply the distributive
9360    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9361    which then simplifies to (and (A (not B))).
9362
9363    Note that no checks happen on the validity of applying the inverse
9364    distributive law.  This is pointless since we can do it in the
9365    few places where this routine is called.
9366
9367    N is the index of the term that is decomposed (the arithmetic operation,
9368    i.e. (+ A B) in the first example above).  !N is the index of the term that
9369    is distributed, i.e. of C in the first example above.  */
9370 static rtx
9371 distribute_and_simplify_rtx (rtx x, int n)
9372 {
9373   enum machine_mode mode;
9374   enum rtx_code outer_code, inner_code;
9375   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9376
9377   /* Distributivity is not true for floating point as it can change the
9378      value.  So we don't do it unless -funsafe-math-optimizations.  */
9379   if (FLOAT_MODE_P (GET_MODE (x))
9380       && ! flag_unsafe_math_optimizations)
9381     return NULL_RTX;
9382
9383   decomposed = XEXP (x, n);
9384   if (!ARITHMETIC_P (decomposed))
9385     return NULL_RTX;
9386
9387   mode = GET_MODE (x);
9388   outer_code = GET_CODE (x);
9389   distributed = XEXP (x, !n);
9390
9391   inner_code = GET_CODE (decomposed);
9392   inner_op0 = XEXP (decomposed, 0);
9393   inner_op1 = XEXP (decomposed, 1);
9394
9395   /* Special case (and (xor B C) (not A)), which is equivalent to
9396      (xor (ior A B) (ior A C))  */
9397   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9398     {
9399       distributed = XEXP (distributed, 0);
9400       outer_code = IOR;
9401     }
9402
9403   if (n == 0)
9404     {
9405       /* Distribute the second term.  */
9406       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9407       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9408     }
9409   else
9410     {
9411       /* Distribute the first term.  */
9412       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9413       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9414     }
9415
9416   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9417                                                      new_op0, new_op1));
9418   if (GET_CODE (tmp) != outer_code
9419       && (set_src_cost (tmp, optimize_this_for_speed_p)
9420           < set_src_cost (x, optimize_this_for_speed_p)))
9421     return tmp;
9422
9423   return NULL_RTX;
9424 }
9425 \f
9426 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9427    in MODE.  Return an equivalent form, if different from (and VAROP
9428    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9429
9430 static rtx
9431 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9432                           unsigned HOST_WIDE_INT constop)
9433 {
9434   unsigned HOST_WIDE_INT nonzero;
9435   unsigned HOST_WIDE_INT orig_constop;
9436   rtx orig_varop;
9437   int i;
9438
9439   orig_varop = varop;
9440   orig_constop = constop;
9441   if (GET_CODE (varop) == CLOBBER)
9442     return NULL_RTX;
9443
9444   /* Simplify VAROP knowing that we will be only looking at some of the
9445      bits in it.
9446
9447      Note by passing in CONSTOP, we guarantee that the bits not set in
9448      CONSTOP are not significant and will never be examined.  We must
9449      ensure that is the case by explicitly masking out those bits
9450      before returning.  */
9451   varop = force_to_mode (varop, mode, constop, 0);
9452
9453   /* If VAROP is a CLOBBER, we will fail so return it.  */
9454   if (GET_CODE (varop) == CLOBBER)
9455     return varop;
9456
9457   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9458      to VAROP and return the new constant.  */
9459   if (CONST_INT_P (varop))
9460     return gen_int_mode (INTVAL (varop) & constop, mode);
9461
9462   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9463      a call to nonzero_bits, here we don't care about bits outside
9464      MODE.  */
9465
9466   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9467
9468   /* Turn off all bits in the constant that are known to already be zero.
9469      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9470      which is tested below.  */
9471
9472   constop &= nonzero;
9473
9474   /* If we don't have any bits left, return zero.  */
9475   if (constop == 0)
9476     return const0_rtx;
9477
9478   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9479      a power of two, we can replace this with an ASHIFT.  */
9480   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9481       && (i = exact_log2 (constop)) >= 0)
9482     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9483
9484   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9485      or XOR, then try to apply the distributive law.  This may eliminate
9486      operations if either branch can be simplified because of the AND.
9487      It may also make some cases more complex, but those cases probably
9488      won't match a pattern either with or without this.  */
9489
9490   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9491     return
9492       gen_lowpart
9493         (mode,
9494          apply_distributive_law
9495          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9496                                simplify_and_const_int (NULL_RTX,
9497                                                        GET_MODE (varop),
9498                                                        XEXP (varop, 0),
9499                                                        constop),
9500                                simplify_and_const_int (NULL_RTX,
9501                                                        GET_MODE (varop),
9502                                                        XEXP (varop, 1),
9503                                                        constop))));
9504
9505   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9506      the AND and see if one of the operands simplifies to zero.  If so, we
9507      may eliminate it.  */
9508
9509   if (GET_CODE (varop) == PLUS
9510       && exact_log2 (constop + 1) >= 0)
9511     {
9512       rtx o0, o1;
9513
9514       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9515       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9516       if (o0 == const0_rtx)
9517         return o1;
9518       if (o1 == const0_rtx)
9519         return o0;
9520     }
9521
9522   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9523   varop = gen_lowpart (mode, varop);
9524   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9525     return NULL_RTX;
9526
9527   /* If we are only masking insignificant bits, return VAROP.  */
9528   if (constop == nonzero)
9529     return varop;
9530
9531   if (varop == orig_varop && constop == orig_constop)
9532     return NULL_RTX;
9533
9534   /* Otherwise, return an AND.  */
9535   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9536 }
9537
9538
9539 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9540    in MODE.
9541
9542    Return an equivalent form, if different from X.  Otherwise, return X.  If
9543    X is zero, we are to always construct the equivalent form.  */
9544
9545 static rtx
9546 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9547                         unsigned HOST_WIDE_INT constop)
9548 {
9549   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9550   if (tem)
9551     return tem;
9552
9553   if (!x)
9554     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9555                              gen_int_mode (constop, mode));
9556   if (GET_MODE (x) != mode)
9557     x = gen_lowpart (mode, x);
9558   return x;
9559 }
9560 \f
9561 /* Given a REG, X, compute which bits in X can be nonzero.
9562    We don't care about bits outside of those defined in MODE.
9563
9564    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9565    a shift, AND, or zero_extract, we can do better.  */
9566
9567 static rtx
9568 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9569                               const_rtx known_x ATTRIBUTE_UNUSED,
9570                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9571                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9572                               unsigned HOST_WIDE_INT *nonzero)
9573 {
9574   rtx tem;
9575   reg_stat_type *rsp;
9576
9577   /* If X is a register whose nonzero bits value is current, use it.
9578      Otherwise, if X is a register whose value we can find, use that
9579      value.  Otherwise, use the previously-computed global nonzero bits
9580      for this register.  */
9581
9582   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9583   if (rsp->last_set_value != 0
9584       && (rsp->last_set_mode == mode
9585           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9586               && GET_MODE_CLASS (mode) == MODE_INT))
9587       && ((rsp->last_set_label >= label_tick_ebb_start
9588            && rsp->last_set_label < label_tick)
9589           || (rsp->last_set_label == label_tick
9590               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9591           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9592               && REG_N_SETS (REGNO (x)) == 1
9593               && !REGNO_REG_SET_P
9594                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9595     {
9596       *nonzero &= rsp->last_set_nonzero_bits;
9597       return NULL;
9598     }
9599
9600   tem = get_last_value (x);
9601
9602   if (tem)
9603     {
9604 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9605       /* If X is narrower than MODE and TEM is a non-negative
9606          constant that would appear negative in the mode of X,
9607          sign-extend it for use in reg_nonzero_bits because some
9608          machines (maybe most) will actually do the sign-extension
9609          and this is the conservative approach.
9610
9611          ??? For 2.5, try to tighten up the MD files in this regard
9612          instead of this kludge.  */
9613
9614       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9615           && CONST_INT_P (tem)
9616           && INTVAL (tem) > 0
9617           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9618         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9619 #endif
9620       return tem;
9621     }
9622   else if (nonzero_sign_valid && rsp->nonzero_bits)
9623     {
9624       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9625
9626       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9627         /* We don't know anything about the upper bits.  */
9628         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9629       *nonzero &= mask;
9630     }
9631
9632   return NULL;
9633 }
9634
9635 /* Return the number of bits at the high-order end of X that are known to
9636    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9637    VOIDmode, X will be used in its own mode.  The returned value  will always
9638    be between 1 and the number of bits in MODE.  */
9639
9640 static rtx
9641 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9642                                      const_rtx known_x ATTRIBUTE_UNUSED,
9643                                      enum machine_mode known_mode
9644                                      ATTRIBUTE_UNUSED,
9645                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9646                                      unsigned int *result)
9647 {
9648   rtx tem;
9649   reg_stat_type *rsp;
9650
9651   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9652   if (rsp->last_set_value != 0
9653       && rsp->last_set_mode == mode
9654       && ((rsp->last_set_label >= label_tick_ebb_start
9655            && rsp->last_set_label < label_tick)
9656           || (rsp->last_set_label == label_tick
9657               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9658           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9659               && REG_N_SETS (REGNO (x)) == 1
9660               && !REGNO_REG_SET_P
9661                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9662     {
9663       *result = rsp->last_set_sign_bit_copies;
9664       return NULL;
9665     }
9666
9667   tem = get_last_value (x);
9668   if (tem != 0)
9669     return tem;
9670
9671   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9672       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9673     *result = rsp->sign_bit_copies;
9674
9675   return NULL;
9676 }
9677 \f
9678 /* Return the number of "extended" bits there are in X, when interpreted
9679    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9680    unsigned quantities, this is the number of high-order zero bits.
9681    For signed quantities, this is the number of copies of the sign bit
9682    minus 1.  In both case, this function returns the number of "spare"
9683    bits.  For example, if two quantities for which this function returns
9684    at least 1 are added, the addition is known not to overflow.
9685
9686    This function will always return 0 unless called during combine, which
9687    implies that it must be called from a define_split.  */
9688
9689 unsigned int
9690 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9691 {
9692   if (nonzero_sign_valid == 0)
9693     return 0;
9694
9695   return (unsignedp
9696           ? (HWI_COMPUTABLE_MODE_P (mode)
9697              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9698                                - floor_log2 (nonzero_bits (x, mode)))
9699              : 0)
9700           : num_sign_bit_copies (x, mode) - 1);
9701 }
9702 \f
9703 /* This function is called from `simplify_shift_const' to merge two
9704    outer operations.  Specifically, we have already found that we need
9705    to perform operation *POP0 with constant *PCONST0 at the outermost
9706    position.  We would now like to also perform OP1 with constant CONST1
9707    (with *POP0 being done last).
9708
9709    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9710    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9711    complement the innermost operand, otherwise it is unchanged.
9712
9713    MODE is the mode in which the operation will be done.  No bits outside
9714    the width of this mode matter.  It is assumed that the width of this mode
9715    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9716
9717    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9718    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9719    result is simply *PCONST0.
9720
9721    If the resulting operation cannot be expressed as one operation, we
9722    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9723
9724 static int
9725 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9726 {
9727   enum rtx_code op0 = *pop0;
9728   HOST_WIDE_INT const0 = *pconst0;
9729
9730   const0 &= GET_MODE_MASK (mode);
9731   const1 &= GET_MODE_MASK (mode);
9732
9733   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9734   if (op0 == AND)
9735     const1 &= const0;
9736
9737   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9738      if OP0 is SET.  */
9739
9740   if (op1 == UNKNOWN || op0 == SET)
9741     return 1;
9742
9743   else if (op0 == UNKNOWN)
9744     op0 = op1, const0 = const1;
9745
9746   else if (op0 == op1)
9747     {
9748       switch (op0)
9749         {
9750         case AND:
9751           const0 &= const1;
9752           break;
9753         case IOR:
9754           const0 |= const1;
9755           break;
9756         case XOR:
9757           const0 ^= const1;
9758           break;
9759         case PLUS:
9760           const0 += const1;
9761           break;
9762         case NEG:
9763           op0 = UNKNOWN;
9764           break;
9765         default:
9766           break;
9767         }
9768     }
9769
9770   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9771   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9772     return 0;
9773
9774   /* If the two constants aren't the same, we can't do anything.  The
9775      remaining six cases can all be done.  */
9776   else if (const0 != const1)
9777     return 0;
9778
9779   else
9780     switch (op0)
9781       {
9782       case IOR:
9783         if (op1 == AND)
9784           /* (a & b) | b == b */
9785           op0 = SET;
9786         else /* op1 == XOR */
9787           /* (a ^ b) | b == a | b */
9788           {;}
9789         break;
9790
9791       case XOR:
9792         if (op1 == AND)
9793           /* (a & b) ^ b == (~a) & b */
9794           op0 = AND, *pcomp_p = 1;
9795         else /* op1 == IOR */
9796           /* (a | b) ^ b == a & ~b */
9797           op0 = AND, const0 = ~const0;
9798         break;
9799
9800       case AND:
9801         if (op1 == IOR)
9802           /* (a | b) & b == b */
9803         op0 = SET;
9804         else /* op1 == XOR */
9805           /* (a ^ b) & b) == (~a) & b */
9806           *pcomp_p = 1;
9807         break;
9808       default:
9809         break;
9810       }
9811
9812   /* Check for NO-OP cases.  */
9813   const0 &= GET_MODE_MASK (mode);
9814   if (const0 == 0
9815       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9816     op0 = UNKNOWN;
9817   else if (const0 == 0 && op0 == AND)
9818     op0 = SET;
9819   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9820            && op0 == AND)
9821     op0 = UNKNOWN;
9822
9823   *pop0 = op0;
9824
9825   /* ??? Slightly redundant with the above mask, but not entirely.
9826      Moving this above means we'd have to sign-extend the mode mask
9827      for the final test.  */
9828   if (op0 != UNKNOWN && op0 != NEG)
9829     *pconst0 = trunc_int_for_mode (const0, mode);
9830
9831   return 1;
9832 }
9833 \f
9834 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9835    the shift in.  The original shift operation CODE is performed on OP in
9836    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9837    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9838    result of the shift is subject to operation OUTER_CODE with operand
9839    OUTER_CONST.  */
9840
9841 static enum machine_mode
9842 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9843                       enum machine_mode orig_mode, enum machine_mode mode,
9844                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9845 {
9846   if (orig_mode == mode)
9847     return mode;
9848   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9849
9850   /* In general we can't perform in wider mode for right shift and rotate.  */
9851   switch (code)
9852     {
9853     case ASHIFTRT:
9854       /* We can still widen if the bits brought in from the left are identical
9855          to the sign bit of ORIG_MODE.  */
9856       if (num_sign_bit_copies (op, mode)
9857           > (unsigned) (GET_MODE_PRECISION (mode)
9858                         - GET_MODE_PRECISION (orig_mode)))
9859         return mode;
9860       return orig_mode;
9861
9862     case LSHIFTRT:
9863       /* Similarly here but with zero bits.  */
9864       if (HWI_COMPUTABLE_MODE_P (mode)
9865           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9866         return mode;
9867
9868       /* We can also widen if the bits brought in will be masked off.  This
9869          operation is performed in ORIG_MODE.  */
9870       if (outer_code == AND)
9871         {
9872           int care_bits = low_bitmask_len (orig_mode, outer_const);
9873
9874           if (care_bits >= 0
9875               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9876             return mode;
9877         }
9878       /* fall through */
9879
9880     case ROTATE:
9881       return orig_mode;
9882
9883     case ROTATERT:
9884       gcc_unreachable ();
9885
9886     default:
9887       return mode;
9888     }
9889 }
9890
9891 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9892    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9893    if we cannot simplify it.  Otherwise, return a simplified value.
9894
9895    The shift is normally computed in the widest mode we find in VAROP, as
9896    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9897    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9898
9899 static rtx
9900 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9901                         rtx varop, int orig_count)
9902 {
9903   enum rtx_code orig_code = code;
9904   rtx orig_varop = varop;
9905   int count;
9906   enum machine_mode mode = result_mode;
9907   enum machine_mode shift_mode, tmode;
9908   unsigned int mode_words
9909     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9910   /* We form (outer_op (code varop count) (outer_const)).  */
9911   enum rtx_code outer_op = UNKNOWN;
9912   HOST_WIDE_INT outer_const = 0;
9913   int complement_p = 0;
9914   rtx new_rtx, x;
9915
9916   /* Make sure and truncate the "natural" shift on the way in.  We don't
9917      want to do this inside the loop as it makes it more difficult to
9918      combine shifts.  */
9919   if (SHIFT_COUNT_TRUNCATED)
9920     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9921
9922   /* If we were given an invalid count, don't do anything except exactly
9923      what was requested.  */
9924
9925   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9926     return NULL_RTX;
9927
9928   count = orig_count;
9929
9930   /* Unless one of the branches of the `if' in this loop does a `continue',
9931      we will `break' the loop after the `if'.  */
9932
9933   while (count != 0)
9934     {
9935       /* If we have an operand of (clobber (const_int 0)), fail.  */
9936       if (GET_CODE (varop) == CLOBBER)
9937         return NULL_RTX;
9938
9939       /* Convert ROTATERT to ROTATE.  */
9940       if (code == ROTATERT)
9941         {
9942           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9943           code = ROTATE;
9944           if (VECTOR_MODE_P (result_mode))
9945             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9946           else
9947             count = bitsize - count;
9948         }
9949
9950       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9951                                          mode, outer_op, outer_const);
9952
9953       /* Handle cases where the count is greater than the size of the mode
9954          minus 1.  For ASHIFT, use the size minus one as the count (this can
9955          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9956          take the count modulo the size.  For other shifts, the result is
9957          zero.
9958
9959          Since these shifts are being produced by the compiler by combining
9960          multiple operations, each of which are defined, we know what the
9961          result is supposed to be.  */
9962
9963       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9964         {
9965           if (code == ASHIFTRT)
9966             count = GET_MODE_PRECISION (shift_mode) - 1;
9967           else if (code == ROTATE || code == ROTATERT)
9968             count %= GET_MODE_PRECISION (shift_mode);
9969           else
9970             {
9971               /* We can't simply return zero because there may be an
9972                  outer op.  */
9973               varop = const0_rtx;
9974               count = 0;
9975               break;
9976             }
9977         }
9978
9979       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9980          here would cause an infinite loop.  */
9981       if (complement_p)
9982         break;
9983
9984       /* An arithmetic right shift of a quantity known to be -1 or 0
9985          is a no-op.  */
9986       if (code == ASHIFTRT
9987           && (num_sign_bit_copies (varop, shift_mode)
9988               == GET_MODE_PRECISION (shift_mode)))
9989         {
9990           count = 0;
9991           break;
9992         }
9993
9994       /* If we are doing an arithmetic right shift and discarding all but
9995          the sign bit copies, this is equivalent to doing a shift by the
9996          bitsize minus one.  Convert it into that shift because it will often
9997          allow other simplifications.  */
9998
9999       if (code == ASHIFTRT
10000           && (count + num_sign_bit_copies (varop, shift_mode)
10001               >= GET_MODE_PRECISION (shift_mode)))
10002         count = GET_MODE_PRECISION (shift_mode) - 1;
10003
10004       /* We simplify the tests below and elsewhere by converting
10005          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10006          `make_compound_operation' will convert it to an ASHIFTRT for
10007          those machines (such as VAX) that don't have an LSHIFTRT.  */
10008       if (code == ASHIFTRT
10009           && val_signbit_known_clear_p (shift_mode,
10010                                         nonzero_bits (varop, shift_mode)))
10011         code = LSHIFTRT;
10012
10013       if (((code == LSHIFTRT
10014             && HWI_COMPUTABLE_MODE_P (shift_mode)
10015             && !(nonzero_bits (varop, shift_mode) >> count))
10016            || (code == ASHIFT
10017                && HWI_COMPUTABLE_MODE_P (shift_mode)
10018                && !((nonzero_bits (varop, shift_mode) << count)
10019                     & GET_MODE_MASK (shift_mode))))
10020           && !side_effects_p (varop))
10021         varop = const0_rtx;
10022
10023       switch (GET_CODE (varop))
10024         {
10025         case SIGN_EXTEND:
10026         case ZERO_EXTEND:
10027         case SIGN_EXTRACT:
10028         case ZERO_EXTRACT:
10029           new_rtx = expand_compound_operation (varop);
10030           if (new_rtx != varop)
10031             {
10032               varop = new_rtx;
10033               continue;
10034             }
10035           break;
10036
10037         case MEM:
10038           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10039              minus the width of a smaller mode, we can do this with a
10040              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
10041           if ((code == ASHIFTRT || code == LSHIFTRT)
10042               && ! mode_dependent_address_p (XEXP (varop, 0))
10043               && ! MEM_VOLATILE_P (varop)
10044               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10045                                          MODE_INT, 1)) != BLKmode)
10046             {
10047               new_rtx = adjust_address_nv (varop, tmode,
10048                                        BYTES_BIG_ENDIAN ? 0
10049                                        : count / BITS_PER_UNIT);
10050
10051               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10052                                      : ZERO_EXTEND, mode, new_rtx);
10053               count = 0;
10054               continue;
10055             }
10056           break;
10057
10058         case SUBREG:
10059           /* If VAROP is a SUBREG, strip it as long as the inner operand has
10060              the same number of words as what we've seen so far.  Then store
10061              the widest mode in MODE.  */
10062           if (subreg_lowpart_p (varop)
10063               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10064                   > GET_MODE_SIZE (GET_MODE (varop)))
10065               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10066                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10067                  == mode_words
10068               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10069               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10070             {
10071               varop = SUBREG_REG (varop);
10072               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10073                 mode = GET_MODE (varop);
10074               continue;
10075             }
10076           break;
10077
10078         case MULT:
10079           /* Some machines use MULT instead of ASHIFT because MULT
10080              is cheaper.  But it is still better on those machines to
10081              merge two shifts into one.  */
10082           if (CONST_INT_P (XEXP (varop, 1))
10083               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10084             {
10085               varop
10086                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10087                                        XEXP (varop, 0),
10088                                        GEN_INT (exact_log2 (
10089                                                 UINTVAL (XEXP (varop, 1)))));
10090               continue;
10091             }
10092           break;
10093
10094         case UDIV:
10095           /* Similar, for when divides are cheaper.  */
10096           if (CONST_INT_P (XEXP (varop, 1))
10097               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10098             {
10099               varop
10100                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10101                                        XEXP (varop, 0),
10102                                        GEN_INT (exact_log2 (
10103                                                 UINTVAL (XEXP (varop, 1)))));
10104               continue;
10105             }
10106           break;
10107
10108         case ASHIFTRT:
10109           /* If we are extracting just the sign bit of an arithmetic
10110              right shift, that shift is not needed.  However, the sign
10111              bit of a wider mode may be different from what would be
10112              interpreted as the sign bit in a narrower mode, so, if
10113              the result is narrower, don't discard the shift.  */
10114           if (code == LSHIFTRT
10115               && count == (GET_MODE_BITSIZE (result_mode) - 1)
10116               && (GET_MODE_BITSIZE (result_mode)
10117                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
10118             {
10119               varop = XEXP (varop, 0);
10120               continue;
10121             }
10122
10123           /* ... fall through ...  */
10124
10125         case LSHIFTRT:
10126         case ASHIFT:
10127         case ROTATE:
10128           /* Here we have two nested shifts.  The result is usually the
10129              AND of a new shift with a mask.  We compute the result below.  */
10130           if (CONST_INT_P (XEXP (varop, 1))
10131               && INTVAL (XEXP (varop, 1)) >= 0
10132               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10133               && HWI_COMPUTABLE_MODE_P (result_mode)
10134               && HWI_COMPUTABLE_MODE_P (mode)
10135               && !VECTOR_MODE_P (result_mode))
10136             {
10137               enum rtx_code first_code = GET_CODE (varop);
10138               unsigned int first_count = INTVAL (XEXP (varop, 1));
10139               unsigned HOST_WIDE_INT mask;
10140               rtx mask_rtx;
10141
10142               /* We have one common special case.  We can't do any merging if
10143                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10144                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10145                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10146                  we can convert it to
10147                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10148                  This simplifies certain SIGN_EXTEND operations.  */
10149               if (code == ASHIFT && first_code == ASHIFTRT
10150                   && count == (GET_MODE_PRECISION (result_mode)
10151                                - GET_MODE_PRECISION (GET_MODE (varop))))
10152                 {
10153                   /* C3 has the low-order C1 bits zero.  */
10154
10155                   mask = GET_MODE_MASK (mode)
10156                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10157
10158                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10159                                                   XEXP (varop, 0), mask);
10160                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10161                                                 varop, count);
10162                   count = first_count;
10163                   code = ASHIFTRT;
10164                   continue;
10165                 }
10166
10167               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10168                  than C1 high-order bits equal to the sign bit, we can convert
10169                  this to either an ASHIFT or an ASHIFTRT depending on the
10170                  two counts.
10171
10172                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10173
10174               if (code == ASHIFTRT && first_code == ASHIFT
10175                   && GET_MODE (varop) == shift_mode
10176                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10177                       > first_count))
10178                 {
10179                   varop = XEXP (varop, 0);
10180                   count -= first_count;
10181                   if (count < 0)
10182                     {
10183                       count = -count;
10184                       code = ASHIFT;
10185                     }
10186
10187                   continue;
10188                 }
10189
10190               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10191                  we can only do this if FIRST_CODE is also ASHIFTRT.
10192
10193                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10194                  ASHIFTRT.
10195
10196                  If the mode of this shift is not the mode of the outer shift,
10197                  we can't do this if either shift is a right shift or ROTATE.
10198
10199                  Finally, we can't do any of these if the mode is too wide
10200                  unless the codes are the same.
10201
10202                  Handle the case where the shift codes are the same
10203                  first.  */
10204
10205               if (code == first_code)
10206                 {
10207                   if (GET_MODE (varop) != result_mode
10208                       && (code == ASHIFTRT || code == LSHIFTRT
10209                           || code == ROTATE))
10210                     break;
10211
10212                   count += first_count;
10213                   varop = XEXP (varop, 0);
10214                   continue;
10215                 }
10216
10217               if (code == ASHIFTRT
10218                   || (code == ROTATE && first_code == ASHIFTRT)
10219                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10220                   || (GET_MODE (varop) != result_mode
10221                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10222                           || first_code == ROTATE
10223                           || code == ROTATE)))
10224                 break;
10225
10226               /* To compute the mask to apply after the shift, shift the
10227                  nonzero bits of the inner shift the same way the
10228                  outer shift will.  */
10229
10230               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10231
10232               mask_rtx
10233                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10234                                                    GEN_INT (count));
10235
10236               /* Give up if we can't compute an outer operation to use.  */
10237               if (mask_rtx == 0
10238                   || !CONST_INT_P (mask_rtx)
10239                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10240                                         INTVAL (mask_rtx),
10241                                         result_mode, &complement_p))
10242                 break;
10243
10244               /* If the shifts are in the same direction, we add the
10245                  counts.  Otherwise, we subtract them.  */
10246               if ((code == ASHIFTRT || code == LSHIFTRT)
10247                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10248                 count += first_count;
10249               else
10250                 count -= first_count;
10251
10252               /* If COUNT is positive, the new shift is usually CODE,
10253                  except for the two exceptions below, in which case it is
10254                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10255                  always be used  */
10256               if (count > 0
10257                   && ((first_code == ROTATE && code == ASHIFT)
10258                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10259                 code = first_code;
10260               else if (count < 0)
10261                 code = first_code, count = -count;
10262
10263               varop = XEXP (varop, 0);
10264               continue;
10265             }
10266
10267           /* If we have (A << B << C) for any shift, we can convert this to
10268              (A << C << B).  This wins if A is a constant.  Only try this if
10269              B is not a constant.  */
10270
10271           else if (GET_CODE (varop) == code
10272                    && CONST_INT_P (XEXP (varop, 0))
10273                    && !CONST_INT_P (XEXP (varop, 1)))
10274             {
10275               rtx new_rtx = simplify_const_binary_operation (code, mode,
10276                                                          XEXP (varop, 0),
10277                                                          GEN_INT (count));
10278               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10279               count = 0;
10280               continue;
10281             }
10282           break;
10283
10284         case NOT:
10285           if (VECTOR_MODE_P (mode))
10286             break;
10287
10288           /* Make this fit the case below.  */
10289           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10290                                GEN_INT (GET_MODE_MASK (mode)));
10291           continue;
10292
10293         case IOR:
10294         case AND:
10295         case XOR:
10296           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10297              with C the size of VAROP - 1 and the shift is logical if
10298              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10299              we have an (le X 0) operation.   If we have an arithmetic shift
10300              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10301              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10302
10303           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10304               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10305               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10306               && (code == LSHIFTRT || code == ASHIFTRT)
10307               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10308               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10309             {
10310               count = 0;
10311               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10312                                   const0_rtx);
10313
10314               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10315                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10316
10317               continue;
10318             }
10319
10320           /* If we have (shift (logical)), move the logical to the outside
10321              to allow it to possibly combine with another logical and the
10322              shift to combine with another shift.  This also canonicalizes to
10323              what a ZERO_EXTRACT looks like.  Also, some machines have
10324              (and (shift)) insns.  */
10325
10326           if (CONST_INT_P (XEXP (varop, 1))
10327               /* We can't do this if we have (ashiftrt (xor))  and the
10328                  constant has its sign bit set in shift_mode.  */
10329               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10330                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10331                                               shift_mode))
10332               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10333                                                          XEXP (varop, 1),
10334                                                          GEN_INT (count))) != 0
10335               && CONST_INT_P (new_rtx)
10336               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10337                                   INTVAL (new_rtx), result_mode, &complement_p))
10338             {
10339               varop = XEXP (varop, 0);
10340               continue;
10341             }
10342
10343           /* If we can't do that, try to simplify the shift in each arm of the
10344              logical expression, make a new logical expression, and apply
10345              the inverse distributive law.  This also can't be done
10346              for some (ashiftrt (xor)).  */
10347           if (CONST_INT_P (XEXP (varop, 1))
10348              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10349                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10350                                              shift_mode)))
10351             {
10352               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10353                                               XEXP (varop, 0), count);
10354               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10355                                               XEXP (varop, 1), count);
10356
10357               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10358                                            lhs, rhs);
10359               varop = apply_distributive_law (varop);
10360
10361               count = 0;
10362               continue;
10363             }
10364           break;
10365
10366         case EQ:
10367           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10368              says that the sign bit can be tested, FOO has mode MODE, C is
10369              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10370              that may be nonzero.  */
10371           if (code == LSHIFTRT
10372               && XEXP (varop, 1) == const0_rtx
10373               && GET_MODE (XEXP (varop, 0)) == result_mode
10374               && count == (GET_MODE_PRECISION (result_mode) - 1)
10375               && HWI_COMPUTABLE_MODE_P (result_mode)
10376               && STORE_FLAG_VALUE == -1
10377               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10378               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10379                                   &complement_p))
10380             {
10381               varop = XEXP (varop, 0);
10382               count = 0;
10383               continue;
10384             }
10385           break;
10386
10387         case NEG:
10388           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10389              than the number of bits in the mode is equivalent to A.  */
10390           if (code == LSHIFTRT
10391               && count == (GET_MODE_PRECISION (result_mode) - 1)
10392               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10393             {
10394               varop = XEXP (varop, 0);
10395               count = 0;
10396               continue;
10397             }
10398
10399           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10400              NEG outside to allow shifts to combine.  */
10401           if (code == ASHIFT
10402               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10403                                   &complement_p))
10404             {
10405               varop = XEXP (varop, 0);
10406               continue;
10407             }
10408           break;
10409
10410         case PLUS:
10411           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10412              is one less than the number of bits in the mode is
10413              equivalent to (xor A 1).  */
10414           if (code == LSHIFTRT
10415               && count == (GET_MODE_PRECISION (result_mode) - 1)
10416               && XEXP (varop, 1) == constm1_rtx
10417               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10418               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10419                                   &complement_p))
10420             {
10421               count = 0;
10422               varop = XEXP (varop, 0);
10423               continue;
10424             }
10425
10426           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10427              that might be nonzero in BAR are those being shifted out and those
10428              bits are known zero in FOO, we can replace the PLUS with FOO.
10429              Similarly in the other operand order.  This code occurs when
10430              we are computing the size of a variable-size array.  */
10431
10432           if ((code == ASHIFTRT || code == LSHIFTRT)
10433               && count < HOST_BITS_PER_WIDE_INT
10434               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10435               && (nonzero_bits (XEXP (varop, 1), result_mode)
10436                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10437             {
10438               varop = XEXP (varop, 0);
10439               continue;
10440             }
10441           else if ((code == ASHIFTRT || code == LSHIFTRT)
10442                    && count < HOST_BITS_PER_WIDE_INT
10443                    && HWI_COMPUTABLE_MODE_P (result_mode)
10444                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10445                             >> count)
10446                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10447                             & nonzero_bits (XEXP (varop, 1),
10448                                                  result_mode)))
10449             {
10450               varop = XEXP (varop, 1);
10451               continue;
10452             }
10453
10454           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10455           if (code == ASHIFT
10456               && CONST_INT_P (XEXP (varop, 1))
10457               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10458                                                          XEXP (varop, 1),
10459                                                          GEN_INT (count))) != 0
10460               && CONST_INT_P (new_rtx)
10461               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10462                                   INTVAL (new_rtx), result_mode, &complement_p))
10463             {
10464               varop = XEXP (varop, 0);
10465               continue;
10466             }
10467
10468           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10469              signbit', and attempt to change the PLUS to an XOR and move it to
10470              the outer operation as is done above in the AND/IOR/XOR case
10471              leg for shift(logical). See details in logical handling above
10472              for reasoning in doing so.  */
10473           if (code == LSHIFTRT
10474               && CONST_INT_P (XEXP (varop, 1))
10475               && mode_signbit_p (result_mode, XEXP (varop, 1))
10476               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10477                                                          XEXP (varop, 1),
10478                                                          GEN_INT (count))) != 0
10479               && CONST_INT_P (new_rtx)
10480               && merge_outer_ops (&outer_op, &outer_const, XOR,
10481                                   INTVAL (new_rtx), result_mode, &complement_p))
10482             {
10483               varop = XEXP (varop, 0);
10484               continue;
10485             }
10486
10487           break;
10488
10489         case MINUS:
10490           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10491              with C the size of VAROP - 1 and the shift is logical if
10492              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10493              we have a (gt X 0) operation.  If the shift is arithmetic with
10494              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10495              we have a (neg (gt X 0)) operation.  */
10496
10497           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10498               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10499               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10500               && (code == LSHIFTRT || code == ASHIFTRT)
10501               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10502               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10503               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10504             {
10505               count = 0;
10506               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10507                                   const0_rtx);
10508
10509               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10510                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10511
10512               continue;
10513             }
10514           break;
10515
10516         case TRUNCATE:
10517           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10518              if the truncate does not affect the value.  */
10519           if (code == LSHIFTRT
10520               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10521               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10522               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10523                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10524                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10525             {
10526               rtx varop_inner = XEXP (varop, 0);
10527
10528               varop_inner
10529                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10530                                     XEXP (varop_inner, 0),
10531                                     GEN_INT
10532                                     (count + INTVAL (XEXP (varop_inner, 1))));
10533               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10534               count = 0;
10535               continue;
10536             }
10537           break;
10538
10539         default:
10540           break;
10541         }
10542
10543       break;
10544     }
10545
10546   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10547                                      outer_op, outer_const);
10548
10549   /* We have now finished analyzing the shift.  The result should be
10550      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10551      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10552      to the result of the shift.  OUTER_CONST is the relevant constant,
10553      but we must turn off all bits turned off in the shift.  */
10554
10555   if (outer_op == UNKNOWN
10556       && orig_code == code && orig_count == count
10557       && varop == orig_varop
10558       && shift_mode == GET_MODE (varop))
10559     return NULL_RTX;
10560
10561   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10562   varop = gen_lowpart (shift_mode, varop);
10563   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10564     return NULL_RTX;
10565
10566   /* If we have an outer operation and we just made a shift, it is
10567      possible that we could have simplified the shift were it not
10568      for the outer operation.  So try to do the simplification
10569      recursively.  */
10570
10571   if (outer_op != UNKNOWN)
10572     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10573   else
10574     x = NULL_RTX;
10575
10576   if (x == NULL_RTX)
10577     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10578
10579   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10580      turn off all the bits that the shift would have turned off.  */
10581   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10582     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10583                                 GET_MODE_MASK (result_mode) >> orig_count);
10584
10585   /* Do the remainder of the processing in RESULT_MODE.  */
10586   x = gen_lowpart_or_truncate (result_mode, x);
10587
10588   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10589      operation.  */
10590   if (complement_p)
10591     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10592
10593   if (outer_op != UNKNOWN)
10594     {
10595       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10596           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10597         outer_const = trunc_int_for_mode (outer_const, result_mode);
10598
10599       if (outer_op == AND)
10600         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10601       else if (outer_op == SET)
10602         {
10603           /* This means that we have determined that the result is
10604              equivalent to a constant.  This should be rare.  */
10605           if (!side_effects_p (x))
10606             x = GEN_INT (outer_const);
10607         }
10608       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10609         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10610       else
10611         x = simplify_gen_binary (outer_op, result_mode, x,
10612                                  GEN_INT (outer_const));
10613     }
10614
10615   return x;
10616 }
10617
10618 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10619    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10620    return X or, if it is NULL, synthesize the expression with
10621    simplify_gen_binary.  Otherwise, return a simplified value.
10622
10623    The shift is normally computed in the widest mode we find in VAROP, as
10624    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10625    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10626
10627 static rtx
10628 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10629                       rtx varop, int count)
10630 {
10631   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10632   if (tem)
10633     return tem;
10634
10635   if (!x)
10636     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10637   if (GET_MODE (x) != result_mode)
10638     x = gen_lowpart (result_mode, x);
10639   return x;
10640 }
10641
10642 \f
10643 /* Like recog, but we receive the address of a pointer to a new pattern.
10644    We try to match the rtx that the pointer points to.
10645    If that fails, we may try to modify or replace the pattern,
10646    storing the replacement into the same pointer object.
10647
10648    Modifications include deletion or addition of CLOBBERs.
10649
10650    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10651    the CLOBBERs are placed.
10652
10653    The value is the final insn code from the pattern ultimately matched,
10654    or -1.  */
10655
10656 static int
10657 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10658 {
10659   rtx pat = *pnewpat;
10660   int insn_code_number;
10661   int num_clobbers_to_add = 0;
10662   int i;
10663   rtx notes = 0;
10664   rtx old_notes, old_pat;
10665
10666   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10667      we use to indicate that something didn't match.  If we find such a
10668      thing, force rejection.  */
10669   if (GET_CODE (pat) == PARALLEL)
10670     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10671       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10672           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10673         return -1;
10674
10675   old_pat = PATTERN (insn);
10676   old_notes = REG_NOTES (insn);
10677   PATTERN (insn) = pat;
10678   REG_NOTES (insn) = 0;
10679
10680   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10681   if (dump_file && (dump_flags & TDF_DETAILS))
10682     {
10683       if (insn_code_number < 0)
10684         fputs ("Failed to match this instruction:\n", dump_file);
10685       else
10686         fputs ("Successfully matched this instruction:\n", dump_file);
10687       print_rtl_single (dump_file, pat);
10688     }
10689
10690   /* If it isn't, there is the possibility that we previously had an insn
10691      that clobbered some register as a side effect, but the combined
10692      insn doesn't need to do that.  So try once more without the clobbers
10693      unless this represents an ASM insn.  */
10694
10695   if (insn_code_number < 0 && ! check_asm_operands (pat)
10696       && GET_CODE (pat) == PARALLEL)
10697     {
10698       int pos;
10699
10700       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10701         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10702           {
10703             if (i != pos)
10704               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10705             pos++;
10706           }
10707
10708       SUBST_INT (XVECLEN (pat, 0), pos);
10709
10710       if (pos == 1)
10711         pat = XVECEXP (pat, 0, 0);
10712
10713       PATTERN (insn) = pat;
10714       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10715       if (dump_file && (dump_flags & TDF_DETAILS))
10716         {
10717           if (insn_code_number < 0)
10718             fputs ("Failed to match this instruction:\n", dump_file);
10719           else
10720             fputs ("Successfully matched this instruction:\n", dump_file);
10721           print_rtl_single (dump_file, pat);
10722         }
10723     }
10724   PATTERN (insn) = old_pat;
10725   REG_NOTES (insn) = old_notes;
10726
10727   /* Recognize all noop sets, these will be killed by followup pass.  */
10728   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10729     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10730
10731   /* If we had any clobbers to add, make a new pattern than contains
10732      them.  Then check to make sure that all of them are dead.  */
10733   if (num_clobbers_to_add)
10734     {
10735       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10736                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10737                                                   ? (XVECLEN (pat, 0)
10738                                                      + num_clobbers_to_add)
10739                                                   : num_clobbers_to_add + 1));
10740
10741       if (GET_CODE (pat) == PARALLEL)
10742         for (i = 0; i < XVECLEN (pat, 0); i++)
10743           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10744       else
10745         XVECEXP (newpat, 0, 0) = pat;
10746
10747       add_clobbers (newpat, insn_code_number);
10748
10749       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10750            i < XVECLEN (newpat, 0); i++)
10751         {
10752           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10753               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10754             return -1;
10755           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10756             {
10757               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10758               notes = alloc_reg_note (REG_UNUSED,
10759                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10760             }
10761         }
10762       pat = newpat;
10763     }
10764
10765   *pnewpat = pat;
10766   *pnotes = notes;
10767
10768   return insn_code_number;
10769 }
10770 \f
10771 /* Like gen_lowpart_general but for use by combine.  In combine it
10772    is not possible to create any new pseudoregs.  However, it is
10773    safe to create invalid memory addresses, because combine will
10774    try to recognize them and all they will do is make the combine
10775    attempt fail.
10776
10777    If for some reason this cannot do its job, an rtx
10778    (clobber (const_int 0)) is returned.
10779    An insn containing that will not be recognized.  */
10780
10781 static rtx
10782 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10783 {
10784   enum machine_mode imode = GET_MODE (x);
10785   unsigned int osize = GET_MODE_SIZE (omode);
10786   unsigned int isize = GET_MODE_SIZE (imode);
10787   rtx result;
10788
10789   if (omode == imode)
10790     return x;
10791
10792   /* Return identity if this is a CONST or symbolic reference.  */
10793   if (omode == Pmode
10794       && (GET_CODE (x) == CONST
10795           || GET_CODE (x) == SYMBOL_REF
10796           || GET_CODE (x) == LABEL_REF))
10797     return x;
10798
10799   /* We can only support MODE being wider than a word if X is a
10800      constant integer or has a mode the same size.  */
10801   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10802       && ! ((imode == VOIDmode
10803              && (CONST_INT_P (x)
10804                  || GET_CODE (x) == CONST_DOUBLE))
10805             || isize == osize))
10806     goto fail;
10807
10808   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10809      won't know what to do.  So we will strip off the SUBREG here and
10810      process normally.  */
10811   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10812     {
10813       x = SUBREG_REG (x);
10814
10815       /* For use in case we fall down into the address adjustments
10816          further below, we need to adjust the known mode and size of
10817          x; imode and isize, since we just adjusted x.  */
10818       imode = GET_MODE (x);
10819
10820       if (imode == omode)
10821         return x;
10822
10823       isize = GET_MODE_SIZE (imode);
10824     }
10825
10826   result = gen_lowpart_common (omode, x);
10827
10828   if (result)
10829     return result;
10830
10831   if (MEM_P (x))
10832     {
10833       int offset = 0;
10834
10835       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10836          address.  */
10837       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10838         goto fail;
10839
10840       /* If we want to refer to something bigger than the original memref,
10841          generate a paradoxical subreg instead.  That will force a reload
10842          of the original memref X.  */
10843       if (isize < osize)
10844         return gen_rtx_SUBREG (omode, x, 0);
10845
10846       if (WORDS_BIG_ENDIAN)
10847         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10848
10849       /* Adjust the address so that the address-after-the-data is
10850          unchanged.  */
10851       if (BYTES_BIG_ENDIAN)
10852         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10853
10854       return adjust_address_nv (x, omode, offset);
10855     }
10856
10857   /* If X is a comparison operator, rewrite it in a new mode.  This
10858      probably won't match, but may allow further simplifications.  */
10859   else if (COMPARISON_P (x))
10860     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10861
10862   /* If we couldn't simplify X any other way, just enclose it in a
10863      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10864      include an explicit SUBREG or we may simplify it further in combine.  */
10865   else
10866     {
10867       int offset = 0;
10868       rtx res;
10869
10870       offset = subreg_lowpart_offset (omode, imode);
10871       if (imode == VOIDmode)
10872         {
10873           imode = int_mode_for_mode (omode);
10874           x = gen_lowpart_common (imode, x);
10875           if (x == NULL)
10876             goto fail;
10877         }
10878       res = simplify_gen_subreg (omode, x, imode, offset);
10879       if (res)
10880         return res;
10881     }
10882
10883  fail:
10884   return gen_rtx_CLOBBER (omode, const0_rtx);
10885 }
10886 \f
10887 /* Try to simplify a comparison between OP0 and a constant OP1,
10888    where CODE is the comparison code that will be tested, into a
10889    (CODE OP0 const0_rtx) form.
10890
10891    The result is a possibly different comparison code to use.
10892    *POP1 may be updated.  */
10893
10894 static enum rtx_code
10895 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10896 {
10897   enum machine_mode mode = GET_MODE (op0);
10898   unsigned int mode_width = GET_MODE_PRECISION (mode);
10899   HOST_WIDE_INT const_op = INTVAL (*pop1);
10900
10901   /* Get the constant we are comparing against and turn off all bits
10902      not on in our mode.  */
10903   if (mode != VOIDmode)
10904     const_op = trunc_int_for_mode (const_op, mode);
10905
10906   /* If we are comparing against a constant power of two and the value
10907      being compared can only have that single bit nonzero (e.g., it was
10908      `and'ed with that bit), we can replace this with a comparison
10909      with zero.  */
10910   if (const_op
10911       && (code == EQ || code == NE || code == GE || code == GEU
10912           || code == LT || code == LTU)
10913       && mode_width <= HOST_BITS_PER_WIDE_INT
10914       && exact_log2 (const_op) >= 0
10915       && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10916     {
10917       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10918       const_op = 0;
10919     }
10920
10921   /* Similarly, if we are comparing a value known to be either -1 or
10922      0 with -1, change it to the opposite comparison against zero.  */
10923   if (const_op == -1
10924       && (code == EQ || code == NE || code == GT || code == LE
10925           || code == GEU || code == LTU)
10926       && num_sign_bit_copies (op0, mode) == mode_width)
10927     {
10928       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10929       const_op = 0;
10930     }
10931
10932   /* Do some canonicalizations based on the comparison code.  We prefer
10933      comparisons against zero and then prefer equality comparisons.
10934      If we can reduce the size of a constant, we will do that too.  */
10935   switch (code)
10936     {
10937     case LT:
10938       /* < C is equivalent to <= (C - 1) */
10939       if (const_op > 0)
10940         {
10941           const_op -= 1;
10942           code = LE;
10943           /* ... fall through to LE case below.  */
10944         }
10945       else
10946         break;
10947
10948     case LE:
10949       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10950       if (const_op < 0)
10951         {
10952           const_op += 1;
10953           code = LT;
10954         }
10955
10956       /* If we are doing a <= 0 comparison on a value known to have
10957          a zero sign bit, we can replace this with == 0.  */
10958       else if (const_op == 0
10959                && mode_width <= HOST_BITS_PER_WIDE_INT
10960                && (nonzero_bits (op0, mode)
10961                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10962                == 0)
10963         code = EQ;
10964       break;
10965
10966     case GE:
10967       /* >= C is equivalent to > (C - 1).  */
10968       if (const_op > 0)
10969         {
10970           const_op -= 1;
10971           code = GT;
10972           /* ... fall through to GT below.  */
10973         }
10974       else
10975         break;
10976
10977     case GT:
10978       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10979       if (const_op < 0)
10980         {
10981           const_op += 1;
10982           code = GE;
10983         }
10984
10985       /* If we are doing a > 0 comparison on a value known to have
10986          a zero sign bit, we can replace this with != 0.  */
10987       else if (const_op == 0
10988                && mode_width <= HOST_BITS_PER_WIDE_INT
10989                && (nonzero_bits (op0, mode)
10990                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10991                == 0)
10992         code = NE;
10993       break;
10994
10995     case LTU:
10996       /* < C is equivalent to <= (C - 1).  */
10997       if (const_op > 0)
10998         {
10999           const_op -= 1;
11000           code = LEU;
11001           /* ... fall through ...  */
11002         }
11003       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
11004       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11005                && (unsigned HOST_WIDE_INT) const_op
11006                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11007         {
11008           const_op = 0;
11009           code = GE;
11010           break;
11011         }
11012       else
11013         break;
11014
11015     case LEU:
11016       /* unsigned <= 0 is equivalent to == 0 */
11017       if (const_op == 0)
11018         code = EQ;
11019       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
11020       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11021                && (unsigned HOST_WIDE_INT) const_op
11022                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11023         {
11024           const_op = 0;
11025           code = GE;
11026         }
11027       break;
11028
11029     case GEU:
11030       /* >= C is equivalent to > (C - 1).  */
11031       if (const_op > 1)
11032         {
11033           const_op -= 1;
11034           code = GTU;
11035           /* ... fall through ...  */
11036         }
11037
11038       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
11039       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11040                && (unsigned HOST_WIDE_INT) const_op
11041                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11042         {
11043           const_op = 0;
11044           code = LT;
11045           break;
11046         }
11047       else
11048         break;
11049
11050     case GTU:
11051       /* unsigned > 0 is equivalent to != 0 */
11052       if (const_op == 0)
11053         code = NE;
11054       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
11055       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11056                && (unsigned HOST_WIDE_INT) const_op
11057                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11058         {
11059           const_op = 0;
11060           code = LT;
11061         }
11062       break;
11063
11064     default:
11065       break;
11066     }
11067
11068   *pop1 = GEN_INT (const_op);
11069   return code;
11070 }
11071 \f
11072 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11073    comparison code that will be tested.
11074
11075    The result is a possibly different comparison code to use.  *POP0 and
11076    *POP1 may be updated.
11077
11078    It is possible that we might detect that a comparison is either always
11079    true or always false.  However, we do not perform general constant
11080    folding in combine, so this knowledge isn't useful.  Such tautologies
11081    should have been detected earlier.  Hence we ignore all such cases.  */
11082
11083 static enum rtx_code
11084 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11085 {
11086   rtx op0 = *pop0;
11087   rtx op1 = *pop1;
11088   rtx tem, tem1;
11089   int i;
11090   enum machine_mode mode, tmode;
11091
11092   /* Try a few ways of applying the same transformation to both operands.  */
11093   while (1)
11094     {
11095 #ifndef WORD_REGISTER_OPERATIONS
11096       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11097          so check specially.  */
11098       if (code != GTU && code != GEU && code != LTU && code != LEU
11099           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11100           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11101           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11102           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11103           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11104           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11105               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11106           && CONST_INT_P (XEXP (op0, 1))
11107           && XEXP (op0, 1) == XEXP (op1, 1)
11108           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11109           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11110           && (INTVAL (XEXP (op0, 1))
11111               == (GET_MODE_PRECISION (GET_MODE (op0))
11112                   - (GET_MODE_PRECISION
11113                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11114         {
11115           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11116           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11117         }
11118 #endif
11119
11120       /* If both operands are the same constant shift, see if we can ignore the
11121          shift.  We can if the shift is a rotate or if the bits shifted out of
11122          this shift are known to be zero for both inputs and if the type of
11123          comparison is compatible with the shift.  */
11124       if (GET_CODE (op0) == GET_CODE (op1)
11125           && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11126           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11127               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11128                   && (code != GT && code != LT && code != GE && code != LE))
11129               || (GET_CODE (op0) == ASHIFTRT
11130                   && (code != GTU && code != LTU
11131                       && code != GEU && code != LEU)))
11132           && CONST_INT_P (XEXP (op0, 1))
11133           && INTVAL (XEXP (op0, 1)) >= 0
11134           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11135           && XEXP (op0, 1) == XEXP (op1, 1))
11136         {
11137           enum machine_mode mode = GET_MODE (op0);
11138           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11139           int shift_count = INTVAL (XEXP (op0, 1));
11140
11141           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11142             mask &= (mask >> shift_count) << shift_count;
11143           else if (GET_CODE (op0) == ASHIFT)
11144             mask = (mask & (mask << shift_count)) >> shift_count;
11145
11146           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11147               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11148             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11149           else
11150             break;
11151         }
11152
11153       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11154          SUBREGs are of the same mode, and, in both cases, the AND would
11155          be redundant if the comparison was done in the narrower mode,
11156          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11157          and the operand's possibly nonzero bits are 0xffffff01; in that case
11158          if we only care about QImode, we don't need the AND).  This case
11159          occurs if the output mode of an scc insn is not SImode and
11160          STORE_FLAG_VALUE == 1 (e.g., the 386).
11161
11162          Similarly, check for a case where the AND's are ZERO_EXTEND
11163          operations from some narrower mode even though a SUBREG is not
11164          present.  */
11165
11166       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11167                && CONST_INT_P (XEXP (op0, 1))
11168                && CONST_INT_P (XEXP (op1, 1)))
11169         {
11170           rtx inner_op0 = XEXP (op0, 0);
11171           rtx inner_op1 = XEXP (op1, 0);
11172           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11173           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11174           int changed = 0;
11175
11176           if (paradoxical_subreg_p (inner_op0)
11177               && GET_CODE (inner_op1) == SUBREG
11178               && (GET_MODE (SUBREG_REG (inner_op0))
11179                   == GET_MODE (SUBREG_REG (inner_op1)))
11180               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11181                   <= HOST_BITS_PER_WIDE_INT)
11182               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11183                                              GET_MODE (SUBREG_REG (inner_op0)))))
11184               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11185                                              GET_MODE (SUBREG_REG (inner_op1))))))
11186             {
11187               op0 = SUBREG_REG (inner_op0);
11188               op1 = SUBREG_REG (inner_op1);
11189
11190               /* The resulting comparison is always unsigned since we masked
11191                  off the original sign bit.  */
11192               code = unsigned_condition (code);
11193
11194               changed = 1;
11195             }
11196
11197           else if (c0 == c1)
11198             for (tmode = GET_CLASS_NARROWEST_MODE
11199                  (GET_MODE_CLASS (GET_MODE (op0)));
11200                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11201               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11202                 {
11203                   op0 = gen_lowpart (tmode, inner_op0);
11204                   op1 = gen_lowpart (tmode, inner_op1);
11205                   code = unsigned_condition (code);
11206                   changed = 1;
11207                   break;
11208                 }
11209
11210           if (! changed)
11211             break;
11212         }
11213
11214       /* If both operands are NOT, we can strip off the outer operation
11215          and adjust the comparison code for swapped operands; similarly for
11216          NEG, except that this must be an equality comparison.  */
11217       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11218                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11219                    && (code == EQ || code == NE)))
11220         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11221
11222       else
11223         break;
11224     }
11225
11226   /* If the first operand is a constant, swap the operands and adjust the
11227      comparison code appropriately, but don't do this if the second operand
11228      is already a constant integer.  */
11229   if (swap_commutative_operands_p (op0, op1))
11230     {
11231       tem = op0, op0 = op1, op1 = tem;
11232       code = swap_condition (code);
11233     }
11234
11235   /* We now enter a loop during which we will try to simplify the comparison.
11236      For the most part, we only are concerned with comparisons with zero,
11237      but some things may really be comparisons with zero but not start
11238      out looking that way.  */
11239
11240   while (CONST_INT_P (op1))
11241     {
11242       enum machine_mode mode = GET_MODE (op0);
11243       unsigned int mode_width = GET_MODE_PRECISION (mode);
11244       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11245       int equality_comparison_p;
11246       int sign_bit_comparison_p;
11247       int unsigned_comparison_p;
11248       HOST_WIDE_INT const_op;
11249
11250       /* We only want to handle integral modes.  This catches VOIDmode,
11251          CCmode, and the floating-point modes.  An exception is that we
11252          can handle VOIDmode if OP0 is a COMPARE or a comparison
11253          operation.  */
11254
11255       if (GET_MODE_CLASS (mode) != MODE_INT
11256           && ! (mode == VOIDmode
11257                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11258         break;
11259
11260       /* Try to simplify the compare to constant, possibly changing the
11261          comparison op, and/or changing op1 to zero.  */
11262       code = simplify_compare_const (code, op0, &op1);
11263       const_op = INTVAL (op1);
11264
11265       /* Compute some predicates to simplify code below.  */
11266
11267       equality_comparison_p = (code == EQ || code == NE);
11268       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11269       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11270                                || code == GEU);
11271
11272       /* If this is a sign bit comparison and we can do arithmetic in
11273          MODE, say that we will only be needing the sign bit of OP0.  */
11274       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11275         op0 = force_to_mode (op0, mode,
11276                              (unsigned HOST_WIDE_INT) 1
11277                              << (GET_MODE_PRECISION (mode) - 1),
11278                              0);
11279
11280       /* Now try cases based on the opcode of OP0.  If none of the cases
11281          does a "continue", we exit this loop immediately after the
11282          switch.  */
11283
11284       switch (GET_CODE (op0))
11285         {
11286         case ZERO_EXTRACT:
11287           /* If we are extracting a single bit from a variable position in
11288              a constant that has only a single bit set and are comparing it
11289              with zero, we can convert this into an equality comparison
11290              between the position and the location of the single bit.  */
11291           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11292              have already reduced the shift count modulo the word size.  */
11293           if (!SHIFT_COUNT_TRUNCATED
11294               && CONST_INT_P (XEXP (op0, 0))
11295               && XEXP (op0, 1) == const1_rtx
11296               && equality_comparison_p && const_op == 0
11297               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11298             {
11299               if (BITS_BIG_ENDIAN)
11300                 {
11301                   enum machine_mode new_mode
11302                     = mode_for_extraction (EP_extzv, 1);
11303                   if (new_mode == MAX_MACHINE_MODE)
11304                     i = BITS_PER_WORD - 1 - i;
11305                   else
11306                     {
11307                       mode = new_mode;
11308                       i = (GET_MODE_PRECISION (mode) - 1 - i);
11309                     }
11310                 }
11311
11312               op0 = XEXP (op0, 2);
11313               op1 = GEN_INT (i);
11314               const_op = i;
11315
11316               /* Result is nonzero iff shift count is equal to I.  */
11317               code = reverse_condition (code);
11318               continue;
11319             }
11320
11321           /* ... fall through ...  */
11322
11323         case SIGN_EXTRACT:
11324           tem = expand_compound_operation (op0);
11325           if (tem != op0)
11326             {
11327               op0 = tem;
11328               continue;
11329             }
11330           break;
11331
11332         case NOT:
11333           /* If testing for equality, we can take the NOT of the constant.  */
11334           if (equality_comparison_p
11335               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11336             {
11337               op0 = XEXP (op0, 0);
11338               op1 = tem;
11339               continue;
11340             }
11341
11342           /* If just looking at the sign bit, reverse the sense of the
11343              comparison.  */
11344           if (sign_bit_comparison_p)
11345             {
11346               op0 = XEXP (op0, 0);
11347               code = (code == GE ? LT : GE);
11348               continue;
11349             }
11350           break;
11351
11352         case NEG:
11353           /* If testing for equality, we can take the NEG of the constant.  */
11354           if (equality_comparison_p
11355               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11356             {
11357               op0 = XEXP (op0, 0);
11358               op1 = tem;
11359               continue;
11360             }
11361
11362           /* The remaining cases only apply to comparisons with zero.  */
11363           if (const_op != 0)
11364             break;
11365
11366           /* When X is ABS or is known positive,
11367              (neg X) is < 0 if and only if X != 0.  */
11368
11369           if (sign_bit_comparison_p
11370               && (GET_CODE (XEXP (op0, 0)) == ABS
11371                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11372                       && (nonzero_bits (XEXP (op0, 0), mode)
11373                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11374                          == 0)))
11375             {
11376               op0 = XEXP (op0, 0);
11377               code = (code == LT ? NE : EQ);
11378               continue;
11379             }
11380
11381           /* If we have NEG of something whose two high-order bits are the
11382              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11383           if (num_sign_bit_copies (op0, mode) >= 2)
11384             {
11385               op0 = XEXP (op0, 0);
11386               code = swap_condition (code);
11387               continue;
11388             }
11389           break;
11390
11391         case ROTATE:
11392           /* If we are testing equality and our count is a constant, we
11393              can perform the inverse operation on our RHS.  */
11394           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11395               && (tem = simplify_binary_operation (ROTATERT, mode,
11396                                                    op1, XEXP (op0, 1))) != 0)
11397             {
11398               op0 = XEXP (op0, 0);
11399               op1 = tem;
11400               continue;
11401             }
11402
11403           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11404              a particular bit.  Convert it to an AND of a constant of that
11405              bit.  This will be converted into a ZERO_EXTRACT.  */
11406           if (const_op == 0 && sign_bit_comparison_p
11407               && CONST_INT_P (XEXP (op0, 1))
11408               && mode_width <= HOST_BITS_PER_WIDE_INT)
11409             {
11410               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11411                                             ((unsigned HOST_WIDE_INT) 1
11412                                              << (mode_width - 1
11413                                                  - INTVAL (XEXP (op0, 1)))));
11414               code = (code == LT ? NE : EQ);
11415               continue;
11416             }
11417
11418           /* Fall through.  */
11419
11420         case ABS:
11421           /* ABS is ignorable inside an equality comparison with zero.  */
11422           if (const_op == 0 && equality_comparison_p)
11423             {
11424               op0 = XEXP (op0, 0);
11425               continue;
11426             }
11427           break;
11428
11429         case SIGN_EXTEND:
11430           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11431              (compare FOO CONST) if CONST fits in FOO's mode and we
11432              are either testing inequality or have an unsigned
11433              comparison with ZERO_EXTEND or a signed comparison with
11434              SIGN_EXTEND.  But don't do it if we don't have a compare
11435              insn of the given mode, since we'd have to revert it
11436              later on, and then we wouldn't know whether to sign- or
11437              zero-extend.  */
11438           mode = GET_MODE (XEXP (op0, 0));
11439           if (GET_MODE_CLASS (mode) == MODE_INT
11440               && ! unsigned_comparison_p
11441               && HWI_COMPUTABLE_MODE_P (mode)
11442               && trunc_int_for_mode (const_op, mode) == const_op
11443               && have_insn_for (COMPARE, mode))
11444             {
11445               op0 = XEXP (op0, 0);
11446               continue;
11447             }
11448           break;
11449
11450         case SUBREG:
11451           /* Check for the case where we are comparing A - C1 with C2, that is
11452
11453                (subreg:MODE (plus (A) (-C1))) op (C2)
11454
11455              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11456              comparison in the wider mode.  One of the following two conditions
11457              must be true in order for this to be valid:
11458
11459                1. The mode extension results in the same bit pattern being added
11460                   on both sides and the comparison is equality or unsigned.  As
11461                   C2 has been truncated to fit in MODE, the pattern can only be
11462                   all 0s or all 1s.
11463
11464                2. The mode extension results in the sign bit being copied on
11465                   each side.
11466
11467              The difficulty here is that we have predicates for A but not for
11468              (A - C1) so we need to check that C1 is within proper bounds so
11469              as to perturbate A as little as possible.  */
11470
11471           if (mode_width <= HOST_BITS_PER_WIDE_INT
11472               && subreg_lowpart_p (op0)
11473               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11474               && GET_CODE (SUBREG_REG (op0)) == PLUS
11475               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11476             {
11477               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11478               rtx a = XEXP (SUBREG_REG (op0), 0);
11479               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11480
11481               if ((c1 > 0
11482                    && (unsigned HOST_WIDE_INT) c1
11483                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11484                    && (equality_comparison_p || unsigned_comparison_p)
11485                    /* (A - C1) zero-extends if it is positive and sign-extends
11486                       if it is negative, C2 both zero- and sign-extends.  */
11487                    && ((0 == (nonzero_bits (a, inner_mode)
11488                               & ~GET_MODE_MASK (mode))
11489                         && const_op >= 0)
11490                        /* (A - C1) sign-extends if it is positive and 1-extends
11491                           if it is negative, C2 both sign- and 1-extends.  */
11492                        || (num_sign_bit_copies (a, inner_mode)
11493                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11494                                              - mode_width)
11495                            && const_op < 0)))
11496                   || ((unsigned HOST_WIDE_INT) c1
11497                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11498                       /* (A - C1) always sign-extends, like C2.  */
11499                       && num_sign_bit_copies (a, inner_mode)
11500                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11501                                            - (mode_width - 1))))
11502                 {
11503                   op0 = SUBREG_REG (op0);
11504                   continue;
11505                 }
11506             }
11507
11508           /* If the inner mode is narrower and we are extracting the low part,
11509              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11510           if (subreg_lowpart_p (op0)
11511               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11512             /* Fall through */ ;
11513           else
11514             break;
11515
11516           /* ... fall through ...  */
11517
11518         case ZERO_EXTEND:
11519           mode = GET_MODE (XEXP (op0, 0));
11520           if (GET_MODE_CLASS (mode) == MODE_INT
11521               && (unsigned_comparison_p || equality_comparison_p)
11522               && HWI_COMPUTABLE_MODE_P (mode)
11523               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11524               && const_op >= 0
11525               && have_insn_for (COMPARE, mode))
11526             {
11527               op0 = XEXP (op0, 0);
11528               continue;
11529             }
11530           break;
11531
11532         case PLUS:
11533           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11534              this for equality comparisons due to pathological cases involving
11535              overflows.  */
11536           if (equality_comparison_p
11537               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11538                                                         op1, XEXP (op0, 1))))
11539             {
11540               op0 = XEXP (op0, 0);
11541               op1 = tem;
11542               continue;
11543             }
11544
11545           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11546           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11547               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11548             {
11549               op0 = XEXP (XEXP (op0, 0), 0);
11550               code = (code == LT ? EQ : NE);
11551               continue;
11552             }
11553           break;
11554
11555         case MINUS:
11556           /* We used to optimize signed comparisons against zero, but that
11557              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11558              arrive here as equality comparisons, or (GEU, LTU) are
11559              optimized away.  No need to special-case them.  */
11560
11561           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11562              (eq B (minus A C)), whichever simplifies.  We can only do
11563              this for equality comparisons due to pathological cases involving
11564              overflows.  */
11565           if (equality_comparison_p
11566               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11567                                                         XEXP (op0, 1), op1)))
11568             {
11569               op0 = XEXP (op0, 0);
11570               op1 = tem;
11571               continue;
11572             }
11573
11574           if (equality_comparison_p
11575               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11576                                                         XEXP (op0, 0), op1)))
11577             {
11578               op0 = XEXP (op0, 1);
11579               op1 = tem;
11580               continue;
11581             }
11582
11583           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11584              of bits in X minus 1, is one iff X > 0.  */
11585           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11586               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11587               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11588               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11589             {
11590               op0 = XEXP (op0, 1);
11591               code = (code == GE ? LE : GT);
11592               continue;
11593             }
11594           break;
11595
11596         case XOR:
11597           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11598              if C is zero or B is a constant.  */
11599           if (equality_comparison_p
11600               && 0 != (tem = simplify_binary_operation (XOR, mode,
11601                                                         XEXP (op0, 1), op1)))
11602             {
11603               op0 = XEXP (op0, 0);
11604               op1 = tem;
11605               continue;
11606             }
11607           break;
11608
11609         case EQ:  case NE:
11610         case UNEQ:  case LTGT:
11611         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11612         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11613         case UNORDERED: case ORDERED:
11614           /* We can't do anything if OP0 is a condition code value, rather
11615              than an actual data value.  */
11616           if (const_op != 0
11617               || CC0_P (XEXP (op0, 0))
11618               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11619             break;
11620
11621           /* Get the two operands being compared.  */
11622           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11623             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11624           else
11625             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11626
11627           /* Check for the cases where we simply want the result of the
11628              earlier test or the opposite of that result.  */
11629           if (code == NE || code == EQ
11630               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11631                   && (code == LT || code == GE)))
11632             {
11633               enum rtx_code new_code;
11634               if (code == LT || code == NE)
11635                 new_code = GET_CODE (op0);
11636               else
11637                 new_code = reversed_comparison_code (op0, NULL);
11638
11639               if (new_code != UNKNOWN)
11640                 {
11641                   code = new_code;
11642                   op0 = tem;
11643                   op1 = tem1;
11644                   continue;
11645                 }
11646             }
11647           break;
11648
11649         case IOR:
11650           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11651              iff X <= 0.  */
11652           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11653               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11654               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11655             {
11656               op0 = XEXP (op0, 1);
11657               code = (code == GE ? GT : LE);
11658               continue;
11659             }
11660           break;
11661
11662         case AND:
11663           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11664              will be converted to a ZERO_EXTRACT later.  */
11665           if (const_op == 0 && equality_comparison_p
11666               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11667               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11668             {
11669               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11670                                       XEXP (XEXP (op0, 0), 1));
11671               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11672               continue;
11673             }
11674
11675           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11676              zero and X is a comparison and C1 and C2 describe only bits set
11677              in STORE_FLAG_VALUE, we can compare with X.  */
11678           if (const_op == 0 && equality_comparison_p
11679               && mode_width <= HOST_BITS_PER_WIDE_INT
11680               && CONST_INT_P (XEXP (op0, 1))
11681               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11682               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11683               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11684               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11685             {
11686               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11687                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11688               if ((~STORE_FLAG_VALUE & mask) == 0
11689                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11690                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11691                           && COMPARISON_P (tem))))
11692                 {
11693                   op0 = XEXP (XEXP (op0, 0), 0);
11694                   continue;
11695                 }
11696             }
11697
11698           /* If we are doing an equality comparison of an AND of a bit equal
11699              to the sign bit, replace this with a LT or GE comparison of
11700              the underlying value.  */
11701           if (equality_comparison_p
11702               && const_op == 0
11703               && CONST_INT_P (XEXP (op0, 1))
11704               && mode_width <= HOST_BITS_PER_WIDE_INT
11705               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11706                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11707             {
11708               op0 = XEXP (op0, 0);
11709               code = (code == EQ ? GE : LT);
11710               continue;
11711             }
11712
11713           /* If this AND operation is really a ZERO_EXTEND from a narrower
11714              mode, the constant fits within that mode, and this is either an
11715              equality or unsigned comparison, try to do this comparison in
11716              the narrower mode.
11717
11718              Note that in:
11719
11720              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11721              -> (ne:DI (reg:SI 4) (const_int 0))
11722
11723              unless TRULY_NOOP_TRUNCATION allows it or the register is
11724              known to hold a value of the required mode the
11725              transformation is invalid.  */
11726           if ((equality_comparison_p || unsigned_comparison_p)
11727               && CONST_INT_P (XEXP (op0, 1))
11728               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11729                                    & GET_MODE_MASK (mode))
11730                                   + 1)) >= 0
11731               && const_op >> i == 0
11732               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11733               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11734                   || (REG_P (XEXP (op0, 0))
11735                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11736             {
11737               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11738               continue;
11739             }
11740
11741           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11742              fits in both M1 and M2 and the SUBREG is either paradoxical
11743              or represents the low part, permute the SUBREG and the AND
11744              and try again.  */
11745           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11746             {
11747               unsigned HOST_WIDE_INT c1;
11748               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11749               /* Require an integral mode, to avoid creating something like
11750                  (AND:SF ...).  */
11751               if (SCALAR_INT_MODE_P (tmode)
11752                   /* It is unsafe to commute the AND into the SUBREG if the
11753                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11754                      not defined.  As originally written the upper bits
11755                      have a defined value due to the AND operation.
11756                      However, if we commute the AND inside the SUBREG then
11757                      they no longer have defined values and the meaning of
11758                      the code has been changed.  */
11759                   && (0
11760 #ifdef WORD_REGISTER_OPERATIONS
11761                       || (mode_width > GET_MODE_PRECISION (tmode)
11762                           && mode_width <= BITS_PER_WORD)
11763 #endif
11764                       || (mode_width <= GET_MODE_PRECISION (tmode)
11765                           && subreg_lowpart_p (XEXP (op0, 0))))
11766                   && CONST_INT_P (XEXP (op0, 1))
11767                   && mode_width <= HOST_BITS_PER_WIDE_INT
11768                   && HWI_COMPUTABLE_MODE_P (tmode)
11769                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11770                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11771                   && c1 != mask
11772                   && c1 != GET_MODE_MASK (tmode))
11773                 {
11774                   op0 = simplify_gen_binary (AND, tmode,
11775                                              SUBREG_REG (XEXP (op0, 0)),
11776                                              gen_int_mode (c1, tmode));
11777                   op0 = gen_lowpart (mode, op0);
11778                   continue;
11779                 }
11780             }
11781
11782           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11783           if (const_op == 0 && equality_comparison_p
11784               && XEXP (op0, 1) == const1_rtx
11785               && GET_CODE (XEXP (op0, 0)) == NOT)
11786             {
11787               op0 = simplify_and_const_int (NULL_RTX, mode,
11788                                             XEXP (XEXP (op0, 0), 0), 1);
11789               code = (code == NE ? EQ : NE);
11790               continue;
11791             }
11792
11793           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11794              (eq (and (lshiftrt X) 1) 0).
11795              Also handle the case where (not X) is expressed using xor.  */
11796           if (const_op == 0 && equality_comparison_p
11797               && XEXP (op0, 1) == const1_rtx
11798               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11799             {
11800               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11801               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11802
11803               if (GET_CODE (shift_op) == NOT
11804                   || (GET_CODE (shift_op) == XOR
11805                       && CONST_INT_P (XEXP (shift_op, 1))
11806                       && CONST_INT_P (shift_count)
11807                       && HWI_COMPUTABLE_MODE_P (mode)
11808                       && (UINTVAL (XEXP (shift_op, 1))
11809                           == (unsigned HOST_WIDE_INT) 1
11810                                << INTVAL (shift_count))))
11811                 {
11812                   op0
11813                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11814                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11815                   code = (code == NE ? EQ : NE);
11816                   continue;
11817                 }
11818             }
11819           break;
11820
11821         case ASHIFT:
11822           /* If we have (compare (ashift FOO N) (const_int C)) and
11823              the high order N bits of FOO (N+1 if an inequality comparison)
11824              are known to be zero, we can do this by comparing FOO with C
11825              shifted right N bits so long as the low-order N bits of C are
11826              zero.  */
11827           if (CONST_INT_P (XEXP (op0, 1))
11828               && INTVAL (XEXP (op0, 1)) >= 0
11829               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11830                   < HOST_BITS_PER_WIDE_INT)
11831               && (((unsigned HOST_WIDE_INT) const_op
11832                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11833                       - 1)) == 0)
11834               && mode_width <= HOST_BITS_PER_WIDE_INT
11835               && (nonzero_bits (XEXP (op0, 0), mode)
11836                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11837                                + ! equality_comparison_p))) == 0)
11838             {
11839               /* We must perform a logical shift, not an arithmetic one,
11840                  as we want the top N bits of C to be zero.  */
11841               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11842
11843               temp >>= INTVAL (XEXP (op0, 1));
11844               op1 = gen_int_mode (temp, mode);
11845               op0 = XEXP (op0, 0);
11846               continue;
11847             }
11848
11849           /* If we are doing a sign bit comparison, it means we are testing
11850              a particular bit.  Convert it to the appropriate AND.  */
11851           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11852               && mode_width <= HOST_BITS_PER_WIDE_INT)
11853             {
11854               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11855                                             ((unsigned HOST_WIDE_INT) 1
11856                                              << (mode_width - 1
11857                                                  - INTVAL (XEXP (op0, 1)))));
11858               code = (code == LT ? NE : EQ);
11859               continue;
11860             }
11861
11862           /* If this an equality comparison with zero and we are shifting
11863              the low bit to the sign bit, we can convert this to an AND of the
11864              low-order bit.  */
11865           if (const_op == 0 && equality_comparison_p
11866               && CONST_INT_P (XEXP (op0, 1))
11867               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11868             {
11869               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11870               continue;
11871             }
11872           break;
11873
11874         case ASHIFTRT:
11875           /* If this is an equality comparison with zero, we can do this
11876              as a logical shift, which might be much simpler.  */
11877           if (equality_comparison_p && const_op == 0
11878               && CONST_INT_P (XEXP (op0, 1)))
11879             {
11880               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11881                                           XEXP (op0, 0),
11882                                           INTVAL (XEXP (op0, 1)));
11883               continue;
11884             }
11885
11886           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11887              do the comparison in a narrower mode.  */
11888           if (! unsigned_comparison_p
11889               && CONST_INT_P (XEXP (op0, 1))
11890               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11891               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11892               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11893                                          MODE_INT, 1)) != BLKmode
11894               && (((unsigned HOST_WIDE_INT) const_op
11895                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11896                   <= GET_MODE_MASK (tmode)))
11897             {
11898               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11899               continue;
11900             }
11901
11902           /* Likewise if OP0 is a PLUS of a sign extension with a
11903              constant, which is usually represented with the PLUS
11904              between the shifts.  */
11905           if (! unsigned_comparison_p
11906               && CONST_INT_P (XEXP (op0, 1))
11907               && GET_CODE (XEXP (op0, 0)) == PLUS
11908               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11909               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11910               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11911               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11912                                          MODE_INT, 1)) != BLKmode
11913               && (((unsigned HOST_WIDE_INT) const_op
11914                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11915                   <= GET_MODE_MASK (tmode)))
11916             {
11917               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11918               rtx add_const = XEXP (XEXP (op0, 0), 1);
11919               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11920                                                    add_const, XEXP (op0, 1));
11921
11922               op0 = simplify_gen_binary (PLUS, tmode,
11923                                          gen_lowpart (tmode, inner),
11924                                          new_const);
11925               continue;
11926             }
11927
11928           /* ... fall through ...  */
11929         case LSHIFTRT:
11930           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11931              the low order N bits of FOO are known to be zero, we can do this
11932              by comparing FOO with C shifted left N bits so long as no
11933              overflow occurs.  Even if the low order N bits of FOO aren't known
11934              to be zero, if the comparison is >= or < we can use the same
11935              optimization and for > or <= by setting all the low
11936              order N bits in the comparison constant.  */
11937           if (CONST_INT_P (XEXP (op0, 1))
11938               && INTVAL (XEXP (op0, 1)) > 0
11939               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11940               && mode_width <= HOST_BITS_PER_WIDE_INT
11941               && (((unsigned HOST_WIDE_INT) const_op
11942                    + (GET_CODE (op0) != LSHIFTRT
11943                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11944                          + 1)
11945                       : 0))
11946                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11947             {
11948               unsigned HOST_WIDE_INT low_bits
11949                 = (nonzero_bits (XEXP (op0, 0), mode)
11950                    & (((unsigned HOST_WIDE_INT) 1
11951                        << INTVAL (XEXP (op0, 1))) - 1));
11952               if (low_bits == 0 || !equality_comparison_p)
11953                 {
11954                   /* If the shift was logical, then we must make the condition
11955                      unsigned.  */
11956                   if (GET_CODE (op0) == LSHIFTRT)
11957                     code = unsigned_condition (code);
11958
11959                   const_op <<= INTVAL (XEXP (op0, 1));
11960                   if (low_bits != 0
11961                       && (code == GT || code == GTU
11962                           || code == LE || code == LEU))
11963                     const_op
11964                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11965                   op1 = GEN_INT (const_op);
11966                   op0 = XEXP (op0, 0);
11967                   continue;
11968                 }
11969             }
11970
11971           /* If we are using this shift to extract just the sign bit, we
11972              can replace this with an LT or GE comparison.  */
11973           if (const_op == 0
11974               && (equality_comparison_p || sign_bit_comparison_p)
11975               && CONST_INT_P (XEXP (op0, 1))
11976               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11977             {
11978               op0 = XEXP (op0, 0);
11979               code = (code == NE || code == GT ? LT : GE);
11980               continue;
11981             }
11982           break;
11983
11984         default:
11985           break;
11986         }
11987
11988       break;
11989     }
11990
11991   /* Now make any compound operations involved in this comparison.  Then,
11992      check for an outmost SUBREG on OP0 that is not doing anything or is
11993      paradoxical.  The latter transformation must only be performed when
11994      it is known that the "extra" bits will be the same in op0 and op1 or
11995      that they don't matter.  There are three cases to consider:
11996
11997      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11998      care bits and we can assume they have any convenient value.  So
11999      making the transformation is safe.
12000
12001      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12002      In this case the upper bits of op0 are undefined.  We should not make
12003      the simplification in that case as we do not know the contents of
12004      those bits.
12005
12006      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12007      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
12008      also be sure that they are the same as the upper bits of op1.
12009
12010      We can never remove a SUBREG for a non-equality comparison because
12011      the sign bit is in a different place in the underlying object.  */
12012
12013   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
12014   op1 = make_compound_operation (op1, SET);
12015
12016   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12017       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
12018       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
12019       && (code == NE || code == EQ))
12020     {
12021       if (paradoxical_subreg_p (op0))
12022         {
12023           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
12024              implemented.  */
12025           if (REG_P (SUBREG_REG (op0)))
12026             {
12027               op0 = SUBREG_REG (op0);
12028               op1 = gen_lowpart (GET_MODE (op0), op1);
12029             }
12030         }
12031       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12032                 <= HOST_BITS_PER_WIDE_INT)
12033                && (nonzero_bits (SUBREG_REG (op0),
12034                                  GET_MODE (SUBREG_REG (op0)))
12035                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12036         {
12037           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12038
12039           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12040                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12041             op0 = SUBREG_REG (op0), op1 = tem;
12042         }
12043     }
12044
12045   /* We now do the opposite procedure: Some machines don't have compare
12046      insns in all modes.  If OP0's mode is an integer mode smaller than a
12047      word and we can't do a compare in that mode, see if there is a larger
12048      mode for which we can do the compare.  There are a number of cases in
12049      which we can use the wider mode.  */
12050
12051   mode = GET_MODE (op0);
12052   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12053       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12054       && ! have_insn_for (COMPARE, mode))
12055     for (tmode = GET_MODE_WIDER_MODE (mode);
12056          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12057          tmode = GET_MODE_WIDER_MODE (tmode))
12058       if (have_insn_for (COMPARE, tmode))
12059         {
12060           int zero_extended;
12061
12062           /* If this is a test for negative, we can make an explicit
12063              test of the sign bit.  Test this first so we can use
12064              a paradoxical subreg to extend OP0.  */
12065
12066           if (op1 == const0_rtx && (code == LT || code == GE)
12067               && HWI_COMPUTABLE_MODE_P (mode))
12068             {
12069               op0 = simplify_gen_binary (AND, tmode,
12070                                          gen_lowpart (tmode, op0),
12071                                          GEN_INT ((unsigned HOST_WIDE_INT) 1
12072                                                   << (GET_MODE_BITSIZE (mode)
12073                                                       - 1)));
12074               code = (code == LT) ? NE : EQ;
12075               break;
12076             }
12077
12078           /* If the only nonzero bits in OP0 and OP1 are those in the
12079              narrower mode and this is an equality or unsigned comparison,
12080              we can use the wider mode.  Similarly for sign-extended
12081              values, in which case it is true for all comparisons.  */
12082           zero_extended = ((code == EQ || code == NE
12083                             || code == GEU || code == GTU
12084                             || code == LEU || code == LTU)
12085                            && (nonzero_bits (op0, tmode)
12086                                & ~GET_MODE_MASK (mode)) == 0
12087                            && ((CONST_INT_P (op1)
12088                                 || (nonzero_bits (op1, tmode)
12089                                     & ~GET_MODE_MASK (mode)) == 0)));
12090
12091           if (zero_extended
12092               || ((num_sign_bit_copies (op0, tmode)
12093                    > (unsigned int) (GET_MODE_PRECISION (tmode)
12094                                      - GET_MODE_PRECISION (mode)))
12095                   && (num_sign_bit_copies (op1, tmode)
12096                       > (unsigned int) (GET_MODE_PRECISION (tmode)
12097                                         - GET_MODE_PRECISION (mode)))))
12098             {
12099               /* If OP0 is an AND and we don't have an AND in MODE either,
12100                  make a new AND in the proper mode.  */
12101               if (GET_CODE (op0) == AND
12102                   && !have_insn_for (AND, mode))
12103                 op0 = simplify_gen_binary (AND, tmode,
12104                                            gen_lowpart (tmode,
12105                                                         XEXP (op0, 0)),
12106                                            gen_lowpart (tmode,
12107                                                         XEXP (op0, 1)));
12108               else
12109                 {
12110                   if (zero_extended)
12111                     {
12112                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12113                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12114                     }
12115                   else
12116                     {
12117                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12118                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12119                     }
12120                   break;
12121                 }
12122             }
12123         }
12124
12125 #ifdef CANONICALIZE_COMPARISON
12126   /* If this machine only supports a subset of valid comparisons, see if we
12127      can convert an unsupported one into a supported one.  */
12128   CANONICALIZE_COMPARISON (code, op0, op1);
12129 #endif
12130
12131   *pop0 = op0;
12132   *pop1 = op1;
12133
12134   return code;
12135 }
12136 \f
12137 /* Utility function for record_value_for_reg.  Count number of
12138    rtxs in X.  */
12139 static int
12140 count_rtxs (rtx x)
12141 {
12142   enum rtx_code code = GET_CODE (x);
12143   const char *fmt;
12144   int i, j, ret = 1;
12145
12146   if (GET_RTX_CLASS (code) == '2'
12147       || GET_RTX_CLASS (code) == 'c')
12148     {
12149       rtx x0 = XEXP (x, 0);
12150       rtx x1 = XEXP (x, 1);
12151
12152       if (x0 == x1)
12153         return 1 + 2 * count_rtxs (x0);
12154
12155       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12156            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12157           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12158         return 2 + 2 * count_rtxs (x0)
12159                + count_rtxs (x == XEXP (x1, 0)
12160                              ? XEXP (x1, 1) : XEXP (x1, 0));
12161
12162       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12163            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12164           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12165         return 2 + 2 * count_rtxs (x1)
12166                + count_rtxs (x == XEXP (x0, 0)
12167                              ? XEXP (x0, 1) : XEXP (x0, 0));
12168     }
12169
12170   fmt = GET_RTX_FORMAT (code);
12171   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12172     if (fmt[i] == 'e')
12173       ret += count_rtxs (XEXP (x, i));
12174     else if (fmt[i] == 'E')
12175       for (j = 0; j < XVECLEN (x, i); j++)
12176         ret += count_rtxs (XVECEXP (x, i, j));
12177
12178   return ret;
12179 }
12180 \f
12181 /* Utility function for following routine.  Called when X is part of a value
12182    being stored into last_set_value.  Sets last_set_table_tick
12183    for each register mentioned.  Similar to mention_regs in cse.c  */
12184
12185 static void
12186 update_table_tick (rtx x)
12187 {
12188   enum rtx_code code = GET_CODE (x);
12189   const char *fmt = GET_RTX_FORMAT (code);
12190   int i, j;
12191
12192   if (code == REG)
12193     {
12194       unsigned int regno = REGNO (x);
12195       unsigned int endregno = END_REGNO (x);
12196       unsigned int r;
12197
12198       for (r = regno; r < endregno; r++)
12199         {
12200           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12201           rsp->last_set_table_tick = label_tick;
12202         }
12203
12204       return;
12205     }
12206
12207   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12208     if (fmt[i] == 'e')
12209       {
12210         /* Check for identical subexpressions.  If x contains
12211            identical subexpression we only have to traverse one of
12212            them.  */
12213         if (i == 0 && ARITHMETIC_P (x))
12214           {
12215             /* Note that at this point x1 has already been
12216                processed.  */
12217             rtx x0 = XEXP (x, 0);
12218             rtx x1 = XEXP (x, 1);
12219
12220             /* If x0 and x1 are identical then there is no need to
12221                process x0.  */
12222             if (x0 == x1)
12223               break;
12224
12225             /* If x0 is identical to a subexpression of x1 then while
12226                processing x1, x0 has already been processed.  Thus we
12227                are done with x.  */
12228             if (ARITHMETIC_P (x1)
12229                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12230               break;
12231
12232             /* If x1 is identical to a subexpression of x0 then we
12233                still have to process the rest of x0.  */
12234             if (ARITHMETIC_P (x0)
12235                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12236               {
12237                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12238                 break;
12239               }
12240           }
12241
12242         update_table_tick (XEXP (x, i));
12243       }
12244     else if (fmt[i] == 'E')
12245       for (j = 0; j < XVECLEN (x, i); j++)
12246         update_table_tick (XVECEXP (x, i, j));
12247 }
12248
12249 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12250    are saying that the register is clobbered and we no longer know its
12251    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12252    only permitted with VALUE also zero and is used to invalidate the
12253    register.  */
12254
12255 static void
12256 record_value_for_reg (rtx reg, rtx insn, rtx value)
12257 {
12258   unsigned int regno = REGNO (reg);
12259   unsigned int endregno = END_REGNO (reg);
12260   unsigned int i;
12261   reg_stat_type *rsp;
12262
12263   /* If VALUE contains REG and we have a previous value for REG, substitute
12264      the previous value.  */
12265   if (value && insn && reg_overlap_mentioned_p (reg, value))
12266     {
12267       rtx tem;
12268
12269       /* Set things up so get_last_value is allowed to see anything set up to
12270          our insn.  */
12271       subst_low_luid = DF_INSN_LUID (insn);
12272       tem = get_last_value (reg);
12273
12274       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12275          it isn't going to be useful and will take a lot of time to process,
12276          so just use the CLOBBER.  */
12277
12278       if (tem)
12279         {
12280           if (ARITHMETIC_P (tem)
12281               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12282               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12283             tem = XEXP (tem, 0);
12284           else if (count_occurrences (value, reg, 1) >= 2)
12285             {
12286               /* If there are two or more occurrences of REG in VALUE,
12287                  prevent the value from growing too much.  */
12288               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12289                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12290             }
12291
12292           value = replace_rtx (copy_rtx (value), reg, tem);
12293         }
12294     }
12295
12296   /* For each register modified, show we don't know its value, that
12297      we don't know about its bitwise content, that its value has been
12298      updated, and that we don't know the location of the death of the
12299      register.  */
12300   for (i = regno; i < endregno; i++)
12301     {
12302       rsp = VEC_index (reg_stat_type, reg_stat, i);
12303
12304       if (insn)
12305         rsp->last_set = insn;
12306
12307       rsp->last_set_value = 0;
12308       rsp->last_set_mode = VOIDmode;
12309       rsp->last_set_nonzero_bits = 0;
12310       rsp->last_set_sign_bit_copies = 0;
12311       rsp->last_death = 0;
12312       rsp->truncated_to_mode = VOIDmode;
12313     }
12314
12315   /* Mark registers that are being referenced in this value.  */
12316   if (value)
12317     update_table_tick (value);
12318
12319   /* Now update the status of each register being set.
12320      If someone is using this register in this block, set this register
12321      to invalid since we will get confused between the two lives in this
12322      basic block.  This makes using this register always invalid.  In cse, we
12323      scan the table to invalidate all entries using this register, but this
12324      is too much work for us.  */
12325
12326   for (i = regno; i < endregno; i++)
12327     {
12328       rsp = VEC_index (reg_stat_type, reg_stat, i);
12329       rsp->last_set_label = label_tick;
12330       if (!insn
12331           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12332         rsp->last_set_invalid = 1;
12333       else
12334         rsp->last_set_invalid = 0;
12335     }
12336
12337   /* The value being assigned might refer to X (like in "x++;").  In that
12338      case, we must replace it with (clobber (const_int 0)) to prevent
12339      infinite loops.  */
12340   rsp = VEC_index (reg_stat_type, reg_stat, regno);
12341   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12342     {
12343       value = copy_rtx (value);
12344       if (!get_last_value_validate (&value, insn, label_tick, 1))
12345         value = 0;
12346     }
12347
12348   /* For the main register being modified, update the value, the mode, the
12349      nonzero bits, and the number of sign bit copies.  */
12350
12351   rsp->last_set_value = value;
12352
12353   if (value)
12354     {
12355       enum machine_mode mode = GET_MODE (reg);
12356       subst_low_luid = DF_INSN_LUID (insn);
12357       rsp->last_set_mode = mode;
12358       if (GET_MODE_CLASS (mode) == MODE_INT
12359           && HWI_COMPUTABLE_MODE_P (mode))
12360         mode = nonzero_bits_mode;
12361       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12362       rsp->last_set_sign_bit_copies
12363         = num_sign_bit_copies (value, GET_MODE (reg));
12364     }
12365 }
12366
12367 /* Called via note_stores from record_dead_and_set_regs to handle one
12368    SET or CLOBBER in an insn.  DATA is the instruction in which the
12369    set is occurring.  */
12370
12371 static void
12372 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12373 {
12374   rtx record_dead_insn = (rtx) data;
12375
12376   if (GET_CODE (dest) == SUBREG)
12377     dest = SUBREG_REG (dest);
12378
12379   if (!record_dead_insn)
12380     {
12381       if (REG_P (dest))
12382         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12383       return;
12384     }
12385
12386   if (REG_P (dest))
12387     {
12388       /* If we are setting the whole register, we know its value.  Otherwise
12389          show that we don't know the value.  We can handle SUBREG in
12390          some cases.  */
12391       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12392         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12393       else if (GET_CODE (setter) == SET
12394                && GET_CODE (SET_DEST (setter)) == SUBREG
12395                && SUBREG_REG (SET_DEST (setter)) == dest
12396                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12397                && subreg_lowpart_p (SET_DEST (setter)))
12398         record_value_for_reg (dest, record_dead_insn,
12399                               gen_lowpart (GET_MODE (dest),
12400                                                        SET_SRC (setter)));
12401       else
12402         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12403     }
12404   else if (MEM_P (dest)
12405            /* Ignore pushes, they clobber nothing.  */
12406            && ! push_operand (dest, GET_MODE (dest)))
12407     mem_last_set = DF_INSN_LUID (record_dead_insn);
12408 }
12409
12410 /* Update the records of when each REG was most recently set or killed
12411    for the things done by INSN.  This is the last thing done in processing
12412    INSN in the combiner loop.
12413
12414    We update reg_stat[], in particular fields last_set, last_set_value,
12415    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12416    last_death, and also the similar information mem_last_set (which insn
12417    most recently modified memory) and last_call_luid (which insn was the
12418    most recent subroutine call).  */
12419
12420 static void
12421 record_dead_and_set_regs (rtx insn)
12422 {
12423   rtx link;
12424   unsigned int i;
12425
12426   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12427     {
12428       if (REG_NOTE_KIND (link) == REG_DEAD
12429           && REG_P (XEXP (link, 0)))
12430         {
12431           unsigned int regno = REGNO (XEXP (link, 0));
12432           unsigned int endregno = END_REGNO (XEXP (link, 0));
12433
12434           for (i = regno; i < endregno; i++)
12435             {
12436               reg_stat_type *rsp;
12437
12438               rsp = VEC_index (reg_stat_type, reg_stat, i);
12439               rsp->last_death = insn;
12440             }
12441         }
12442       else if (REG_NOTE_KIND (link) == REG_INC)
12443         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12444     }
12445
12446   if (CALL_P (insn))
12447     {
12448       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12449         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12450           {
12451             reg_stat_type *rsp;
12452
12453             rsp = VEC_index (reg_stat_type, reg_stat, i);
12454             rsp->last_set_invalid = 1;
12455             rsp->last_set = insn;
12456             rsp->last_set_value = 0;
12457             rsp->last_set_mode = VOIDmode;
12458             rsp->last_set_nonzero_bits = 0;
12459             rsp->last_set_sign_bit_copies = 0;
12460             rsp->last_death = 0;
12461             rsp->truncated_to_mode = VOIDmode;
12462           }
12463
12464       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12465
12466       /* We can't combine into a call pattern.  Remember, though, that
12467          the return value register is set at this LUID.  We could
12468          still replace a register with the return value from the
12469          wrong subroutine call!  */
12470       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12471     }
12472   else
12473     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12474 }
12475
12476 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12477    register present in the SUBREG, so for each such SUBREG go back and
12478    adjust nonzero and sign bit information of the registers that are
12479    known to have some zero/sign bits set.
12480
12481    This is needed because when combine blows the SUBREGs away, the
12482    information on zero/sign bits is lost and further combines can be
12483    missed because of that.  */
12484
12485 static void
12486 record_promoted_value (rtx insn, rtx subreg)
12487 {
12488   struct insn_link *links;
12489   rtx set;
12490   unsigned int regno = REGNO (SUBREG_REG (subreg));
12491   enum machine_mode mode = GET_MODE (subreg);
12492
12493   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12494     return;
12495
12496   for (links = LOG_LINKS (insn); links;)
12497     {
12498       reg_stat_type *rsp;
12499
12500       insn = links->insn;
12501       set = single_set (insn);
12502
12503       if (! set || !REG_P (SET_DEST (set))
12504           || REGNO (SET_DEST (set)) != regno
12505           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12506         {
12507           links = links->next;
12508           continue;
12509         }
12510
12511       rsp = VEC_index (reg_stat_type, reg_stat, regno);
12512       if (rsp->last_set == insn)
12513         {
12514           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12515             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12516         }
12517
12518       if (REG_P (SET_SRC (set)))
12519         {
12520           regno = REGNO (SET_SRC (set));
12521           links = LOG_LINKS (insn);
12522         }
12523       else
12524         break;
12525     }
12526 }
12527
12528 /* Check if X, a register, is known to contain a value already
12529    truncated to MODE.  In this case we can use a subreg to refer to
12530    the truncated value even though in the generic case we would need
12531    an explicit truncation.  */
12532
12533 static bool
12534 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12535 {
12536   reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12537   enum machine_mode truncated = rsp->truncated_to_mode;
12538
12539   if (truncated == 0
12540       || rsp->truncation_label < label_tick_ebb_start)
12541     return false;
12542   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12543     return true;
12544   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12545     return true;
12546   return false;
12547 }
12548
12549 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12550    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12551    might be able to turn a truncate into a subreg using this information.
12552    Return -1 if traversing *P is complete or 0 otherwise.  */
12553
12554 static int
12555 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12556 {
12557   rtx x = *p;
12558   enum machine_mode truncated_mode;
12559   reg_stat_type *rsp;
12560
12561   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12562     {
12563       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12564       truncated_mode = GET_MODE (x);
12565
12566       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12567         return -1;
12568
12569       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12570         return -1;
12571
12572       x = SUBREG_REG (x);
12573     }
12574   /* ??? For hard-regs we now record everything.  We might be able to
12575      optimize this using last_set_mode.  */
12576   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12577     truncated_mode = GET_MODE (x);
12578   else
12579     return 0;
12580
12581   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12582   if (rsp->truncated_to_mode == 0
12583       || rsp->truncation_label < label_tick_ebb_start
12584       || (GET_MODE_SIZE (truncated_mode)
12585           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12586     {
12587       rsp->truncated_to_mode = truncated_mode;
12588       rsp->truncation_label = label_tick;
12589     }
12590
12591   return -1;
12592 }
12593
12594 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12595    the modes they are used in.  This can help truning TRUNCATEs into
12596    SUBREGs.  */
12597
12598 static void
12599 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12600 {
12601   for_each_rtx (x, record_truncated_value, NULL);
12602 }
12603
12604 /* Scan X for promoted SUBREGs.  For each one found,
12605    note what it implies to the registers used in it.  */
12606
12607 static void
12608 check_promoted_subreg (rtx insn, rtx x)
12609 {
12610   if (GET_CODE (x) == SUBREG
12611       && SUBREG_PROMOTED_VAR_P (x)
12612       && REG_P (SUBREG_REG (x)))
12613     record_promoted_value (insn, x);
12614   else
12615     {
12616       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12617       int i, j;
12618
12619       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12620         switch (format[i])
12621           {
12622           case 'e':
12623             check_promoted_subreg (insn, XEXP (x, i));
12624             break;
12625           case 'V':
12626           case 'E':
12627             if (XVEC (x, i) != 0)
12628               for (j = 0; j < XVECLEN (x, i); j++)
12629                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12630             break;
12631           }
12632     }
12633 }
12634 \f
12635 /* Verify that all the registers and memory references mentioned in *LOC are
12636    still valid.  *LOC was part of a value set in INSN when label_tick was
12637    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12638    the invalid references with (clobber (const_int 0)) and return 1.  This
12639    replacement is useful because we often can get useful information about
12640    the form of a value (e.g., if it was produced by a shift that always
12641    produces -1 or 0) even though we don't know exactly what registers it
12642    was produced from.  */
12643
12644 static int
12645 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12646 {
12647   rtx x = *loc;
12648   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12649   int len = GET_RTX_LENGTH (GET_CODE (x));
12650   int i, j;
12651
12652   if (REG_P (x))
12653     {
12654       unsigned int regno = REGNO (x);
12655       unsigned int endregno = END_REGNO (x);
12656       unsigned int j;
12657
12658       for (j = regno; j < endregno; j++)
12659         {
12660           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12661           if (rsp->last_set_invalid
12662               /* If this is a pseudo-register that was only set once and not
12663                  live at the beginning of the function, it is always valid.  */
12664               || (! (regno >= FIRST_PSEUDO_REGISTER
12665                      && REG_N_SETS (regno) == 1
12666                      && (!REGNO_REG_SET_P
12667                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12668                   && rsp->last_set_label > tick))
12669           {
12670             if (replace)
12671               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12672             return replace;
12673           }
12674         }
12675
12676       return 1;
12677     }
12678   /* If this is a memory reference, make sure that there were no stores after
12679      it that might have clobbered the value.  We don't have alias info, so we
12680      assume any store invalidates it.  Moreover, we only have local UIDs, so
12681      we also assume that there were stores in the intervening basic blocks.  */
12682   else if (MEM_P (x) && !MEM_READONLY_P (x)
12683            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12684     {
12685       if (replace)
12686         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12687       return replace;
12688     }
12689
12690   for (i = 0; i < len; i++)
12691     {
12692       if (fmt[i] == 'e')
12693         {
12694           /* Check for identical subexpressions.  If x contains
12695              identical subexpression we only have to traverse one of
12696              them.  */
12697           if (i == 1 && ARITHMETIC_P (x))
12698             {
12699               /* Note that at this point x0 has already been checked
12700                  and found valid.  */
12701               rtx x0 = XEXP (x, 0);
12702               rtx x1 = XEXP (x, 1);
12703
12704               /* If x0 and x1 are identical then x is also valid.  */
12705               if (x0 == x1)
12706                 return 1;
12707
12708               /* If x1 is identical to a subexpression of x0 then
12709                  while checking x0, x1 has already been checked.  Thus
12710                  it is valid and so as x.  */
12711               if (ARITHMETIC_P (x0)
12712                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12713                 return 1;
12714
12715               /* If x0 is identical to a subexpression of x1 then x is
12716                  valid iff the rest of x1 is valid.  */
12717               if (ARITHMETIC_P (x1)
12718                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12719                 return
12720                   get_last_value_validate (&XEXP (x1,
12721                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12722                                            insn, tick, replace);
12723             }
12724
12725           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12726                                        replace) == 0)
12727             return 0;
12728         }
12729       else if (fmt[i] == 'E')
12730         for (j = 0; j < XVECLEN (x, i); j++)
12731           if (get_last_value_validate (&XVECEXP (x, i, j),
12732                                        insn, tick, replace) == 0)
12733             return 0;
12734     }
12735
12736   /* If we haven't found a reason for it to be invalid, it is valid.  */
12737   return 1;
12738 }
12739
12740 /* Get the last value assigned to X, if known.  Some registers
12741    in the value may be replaced with (clobber (const_int 0)) if their value
12742    is known longer known reliably.  */
12743
12744 static rtx
12745 get_last_value (const_rtx x)
12746 {
12747   unsigned int regno;
12748   rtx value;
12749   reg_stat_type *rsp;
12750
12751   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12752      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12753      we cannot predict what values the "extra" bits might have.  */
12754   if (GET_CODE (x) == SUBREG
12755       && subreg_lowpart_p (x)
12756       && !paradoxical_subreg_p (x)
12757       && (value = get_last_value (SUBREG_REG (x))) != 0)
12758     return gen_lowpart (GET_MODE (x), value);
12759
12760   if (!REG_P (x))
12761     return 0;
12762
12763   regno = REGNO (x);
12764   rsp = VEC_index (reg_stat_type, reg_stat, regno);
12765   value = rsp->last_set_value;
12766
12767   /* If we don't have a value, or if it isn't for this basic block and
12768      it's either a hard register, set more than once, or it's a live
12769      at the beginning of the function, return 0.
12770
12771      Because if it's not live at the beginning of the function then the reg
12772      is always set before being used (is never used without being set).
12773      And, if it's set only once, and it's always set before use, then all
12774      uses must have the same last value, even if it's not from this basic
12775      block.  */
12776
12777   if (value == 0
12778       || (rsp->last_set_label < label_tick_ebb_start
12779           && (regno < FIRST_PSEUDO_REGISTER
12780               || REG_N_SETS (regno) != 1
12781               || REGNO_REG_SET_P
12782                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12783     return 0;
12784
12785   /* If the value was set in a later insn than the ones we are processing,
12786      we can't use it even if the register was only set once.  */
12787   if (rsp->last_set_label == label_tick
12788       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12789     return 0;
12790
12791   /* If the value has all its registers valid, return it.  */
12792   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12793     return value;
12794
12795   /* Otherwise, make a copy and replace any invalid register with
12796      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12797
12798   value = copy_rtx (value);
12799   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12800     return value;
12801
12802   return 0;
12803 }
12804 \f
12805 /* Return nonzero if expression X refers to a REG or to memory
12806    that is set in an instruction more recent than FROM_LUID.  */
12807
12808 static int
12809 use_crosses_set_p (const_rtx x, int from_luid)
12810 {
12811   const char *fmt;
12812   int i;
12813   enum rtx_code code = GET_CODE (x);
12814
12815   if (code == REG)
12816     {
12817       unsigned int regno = REGNO (x);
12818       unsigned endreg = END_REGNO (x);
12819
12820 #ifdef PUSH_ROUNDING
12821       /* Don't allow uses of the stack pointer to be moved,
12822          because we don't know whether the move crosses a push insn.  */
12823       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12824         return 1;
12825 #endif
12826       for (; regno < endreg; regno++)
12827         {
12828           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12829           if (rsp->last_set
12830               && rsp->last_set_label == label_tick
12831               && DF_INSN_LUID (rsp->last_set) > from_luid)
12832             return 1;
12833         }
12834       return 0;
12835     }
12836
12837   if (code == MEM && mem_last_set > from_luid)
12838     return 1;
12839
12840   fmt = GET_RTX_FORMAT (code);
12841
12842   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12843     {
12844       if (fmt[i] == 'E')
12845         {
12846           int j;
12847           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12848             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12849               return 1;
12850         }
12851       else if (fmt[i] == 'e'
12852                && use_crosses_set_p (XEXP (x, i), from_luid))
12853         return 1;
12854     }
12855   return 0;
12856 }
12857 \f
12858 /* Define three variables used for communication between the following
12859    routines.  */
12860
12861 static unsigned int reg_dead_regno, reg_dead_endregno;
12862 static int reg_dead_flag;
12863
12864 /* Function called via note_stores from reg_dead_at_p.
12865
12866    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12867    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12868
12869 static void
12870 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12871 {
12872   unsigned int regno, endregno;
12873
12874   if (!REG_P (dest))
12875     return;
12876
12877   regno = REGNO (dest);
12878   endregno = END_REGNO (dest);
12879   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12880     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12881 }
12882
12883 /* Return nonzero if REG is known to be dead at INSN.
12884
12885    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12886    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12887    live.  Otherwise, see if it is live or dead at the start of the basic
12888    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12889    must be assumed to be always live.  */
12890
12891 static int
12892 reg_dead_at_p (rtx reg, rtx insn)
12893 {
12894   basic_block block;
12895   unsigned int i;
12896
12897   /* Set variables for reg_dead_at_p_1.  */
12898   reg_dead_regno = REGNO (reg);
12899   reg_dead_endregno = END_REGNO (reg);
12900
12901   reg_dead_flag = 0;
12902
12903   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12904      we allow the machine description to decide whether use-and-clobber
12905      patterns are OK.  */
12906   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12907     {
12908       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12909         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12910           return 0;
12911     }
12912
12913   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12914      beginning of basic block.  */
12915   block = BLOCK_FOR_INSN (insn);
12916   for (;;)
12917     {
12918       if (INSN_P (insn))
12919         {
12920           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12921           if (reg_dead_flag)
12922             return reg_dead_flag == 1 ? 1 : 0;
12923
12924           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12925             return 1;
12926         }
12927
12928       if (insn == BB_HEAD (block))
12929         break;
12930
12931       insn = PREV_INSN (insn);
12932     }
12933
12934   /* Look at live-in sets for the basic block that we were in.  */
12935   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12936     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12937       return 0;
12938
12939   return 1;
12940 }
12941 \f
12942 /* Note hard registers in X that are used.  */
12943
12944 static void
12945 mark_used_regs_combine (rtx x)
12946 {
12947   RTX_CODE code = GET_CODE (x);
12948   unsigned int regno;
12949   int i;
12950
12951   switch (code)
12952     {
12953     case LABEL_REF:
12954     case SYMBOL_REF:
12955     case CONST_INT:
12956     case CONST:
12957     case CONST_DOUBLE:
12958     case CONST_VECTOR:
12959     case PC:
12960     case ADDR_VEC:
12961     case ADDR_DIFF_VEC:
12962     case ASM_INPUT:
12963 #ifdef HAVE_cc0
12964     /* CC0 must die in the insn after it is set, so we don't need to take
12965        special note of it here.  */
12966     case CC0:
12967 #endif
12968       return;
12969
12970     case CLOBBER:
12971       /* If we are clobbering a MEM, mark any hard registers inside the
12972          address as used.  */
12973       if (MEM_P (XEXP (x, 0)))
12974         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12975       return;
12976
12977     case REG:
12978       regno = REGNO (x);
12979       /* A hard reg in a wide mode may really be multiple registers.
12980          If so, mark all of them just like the first.  */
12981       if (regno < FIRST_PSEUDO_REGISTER)
12982         {
12983           /* None of this applies to the stack, frame or arg pointers.  */
12984           if (regno == STACK_POINTER_REGNUM
12985 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12986               || regno == HARD_FRAME_POINTER_REGNUM
12987 #endif
12988 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12989               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12990 #endif
12991               || regno == FRAME_POINTER_REGNUM)
12992             return;
12993
12994           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12995         }
12996       return;
12997
12998     case SET:
12999       {
13000         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13001            the address.  */
13002         rtx testreg = SET_DEST (x);
13003
13004         while (GET_CODE (testreg) == SUBREG
13005                || GET_CODE (testreg) == ZERO_EXTRACT
13006                || GET_CODE (testreg) == STRICT_LOW_PART)
13007           testreg = XEXP (testreg, 0);
13008
13009         if (MEM_P (testreg))
13010           mark_used_regs_combine (XEXP (testreg, 0));
13011
13012         mark_used_regs_combine (SET_SRC (x));
13013       }
13014       return;
13015
13016     default:
13017       break;
13018     }
13019
13020   /* Recursively scan the operands of this expression.  */
13021
13022   {
13023     const char *fmt = GET_RTX_FORMAT (code);
13024
13025     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13026       {
13027         if (fmt[i] == 'e')
13028           mark_used_regs_combine (XEXP (x, i));
13029         else if (fmt[i] == 'E')
13030           {
13031             int j;
13032
13033             for (j = 0; j < XVECLEN (x, i); j++)
13034               mark_used_regs_combine (XVECEXP (x, i, j));
13035           }
13036       }
13037   }
13038 }
13039 \f
13040 /* Remove register number REGNO from the dead registers list of INSN.
13041
13042    Return the note used to record the death, if there was one.  */
13043
13044 rtx
13045 remove_death (unsigned int regno, rtx insn)
13046 {
13047   rtx note = find_regno_note (insn, REG_DEAD, regno);
13048
13049   if (note)
13050     remove_note (insn, note);
13051
13052   return note;
13053 }
13054
13055 /* For each register (hardware or pseudo) used within expression X, if its
13056    death is in an instruction with luid between FROM_LUID (inclusive) and
13057    TO_INSN (exclusive), put a REG_DEAD note for that register in the
13058    list headed by PNOTES.
13059
13060    That said, don't move registers killed by maybe_kill_insn.
13061
13062    This is done when X is being merged by combination into TO_INSN.  These
13063    notes will then be distributed as needed.  */
13064
13065 static void
13066 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13067              rtx *pnotes)
13068 {
13069   const char *fmt;
13070   int len, i;
13071   enum rtx_code code = GET_CODE (x);
13072
13073   if (code == REG)
13074     {
13075       unsigned int regno = REGNO (x);
13076       rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13077
13078       /* Don't move the register if it gets killed in between from and to.  */
13079       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13080           && ! reg_referenced_p (x, maybe_kill_insn))
13081         return;
13082
13083       if (where_dead
13084           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13085           && DF_INSN_LUID (where_dead) >= from_luid
13086           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13087         {
13088           rtx note = remove_death (regno, where_dead);
13089
13090           /* It is possible for the call above to return 0.  This can occur
13091              when last_death points to I2 or I1 that we combined with.
13092              In that case make a new note.
13093
13094              We must also check for the case where X is a hard register
13095              and NOTE is a death note for a range of hard registers
13096              including X.  In that case, we must put REG_DEAD notes for
13097              the remaining registers in place of NOTE.  */
13098
13099           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13100               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13101                   > GET_MODE_SIZE (GET_MODE (x))))
13102             {
13103               unsigned int deadregno = REGNO (XEXP (note, 0));
13104               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13105               unsigned int ourend = END_HARD_REGNO (x);
13106               unsigned int i;
13107
13108               for (i = deadregno; i < deadend; i++)
13109                 if (i < regno || i >= ourend)
13110                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13111             }
13112
13113           /* If we didn't find any note, or if we found a REG_DEAD note that
13114              covers only part of the given reg, and we have a multi-reg hard
13115              register, then to be safe we must check for REG_DEAD notes
13116              for each register other than the first.  They could have
13117              their own REG_DEAD notes lying around.  */
13118           else if ((note == 0
13119                     || (note != 0
13120                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13121                             < GET_MODE_SIZE (GET_MODE (x)))))
13122                    && regno < FIRST_PSEUDO_REGISTER
13123                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13124             {
13125               unsigned int ourend = END_HARD_REGNO (x);
13126               unsigned int i, offset;
13127               rtx oldnotes = 0;
13128
13129               if (note)
13130                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13131               else
13132                 offset = 1;
13133
13134               for (i = regno + offset; i < ourend; i++)
13135                 move_deaths (regno_reg_rtx[i],
13136                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13137             }
13138
13139           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13140             {
13141               XEXP (note, 1) = *pnotes;
13142               *pnotes = note;
13143             }
13144           else
13145             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13146         }
13147
13148       return;
13149     }
13150
13151   else if (GET_CODE (x) == SET)
13152     {
13153       rtx dest = SET_DEST (x);
13154
13155       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13156
13157       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13158          that accesses one word of a multi-word item, some
13159          piece of everything register in the expression is used by
13160          this insn, so remove any old death.  */
13161       /* ??? So why do we test for equality of the sizes?  */
13162
13163       if (GET_CODE (dest) == ZERO_EXTRACT
13164           || GET_CODE (dest) == STRICT_LOW_PART
13165           || (GET_CODE (dest) == SUBREG
13166               && (((GET_MODE_SIZE (GET_MODE (dest))
13167                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13168                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13169                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13170         {
13171           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13172           return;
13173         }
13174
13175       /* If this is some other SUBREG, we know it replaces the entire
13176          value, so use that as the destination.  */
13177       if (GET_CODE (dest) == SUBREG)
13178         dest = SUBREG_REG (dest);
13179
13180       /* If this is a MEM, adjust deaths of anything used in the address.
13181          For a REG (the only other possibility), the entire value is
13182          being replaced so the old value is not used in this insn.  */
13183
13184       if (MEM_P (dest))
13185         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13186                      to_insn, pnotes);
13187       return;
13188     }
13189
13190   else if (GET_CODE (x) == CLOBBER)
13191     return;
13192
13193   len = GET_RTX_LENGTH (code);
13194   fmt = GET_RTX_FORMAT (code);
13195
13196   for (i = 0; i < len; i++)
13197     {
13198       if (fmt[i] == 'E')
13199         {
13200           int j;
13201           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13202             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13203                          to_insn, pnotes);
13204         }
13205       else if (fmt[i] == 'e')
13206         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13207     }
13208 }
13209 \f
13210 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13211    pattern of an insn.  X must be a REG.  */
13212
13213 static int
13214 reg_bitfield_target_p (rtx x, rtx body)
13215 {
13216   int i;
13217
13218   if (GET_CODE (body) == SET)
13219     {
13220       rtx dest = SET_DEST (body);
13221       rtx target;
13222       unsigned int regno, tregno, endregno, endtregno;
13223
13224       if (GET_CODE (dest) == ZERO_EXTRACT)
13225         target = XEXP (dest, 0);
13226       else if (GET_CODE (dest) == STRICT_LOW_PART)
13227         target = SUBREG_REG (XEXP (dest, 0));
13228       else
13229         return 0;
13230
13231       if (GET_CODE (target) == SUBREG)
13232         target = SUBREG_REG (target);
13233
13234       if (!REG_P (target))
13235         return 0;
13236
13237       tregno = REGNO (target), regno = REGNO (x);
13238       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13239         return target == x;
13240
13241       endtregno = end_hard_regno (GET_MODE (target), tregno);
13242       endregno = end_hard_regno (GET_MODE (x), regno);
13243
13244       return endregno > tregno && regno < endtregno;
13245     }
13246
13247   else if (GET_CODE (body) == PARALLEL)
13248     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13249       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13250         return 1;
13251
13252   return 0;
13253 }
13254 \f
13255 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13256    as appropriate.  I3 and I2 are the insns resulting from the combination
13257    insns including FROM (I2 may be zero).
13258
13259    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13260    not need REG_DEAD notes because they are being substituted for.  This
13261    saves searching in the most common cases.
13262
13263    Each note in the list is either ignored or placed on some insns, depending
13264    on the type of note.  */
13265
13266 static void
13267 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13268                   rtx elim_i1, rtx elim_i0)
13269 {
13270   rtx note, next_note;
13271   rtx tem;
13272
13273   for (note = notes; note; note = next_note)
13274     {
13275       rtx place = 0, place2 = 0;
13276
13277       next_note = XEXP (note, 1);
13278       switch (REG_NOTE_KIND (note))
13279         {
13280         case REG_BR_PROB:
13281         case REG_BR_PRED:
13282           /* Doesn't matter much where we put this, as long as it's somewhere.
13283              It is preferable to keep these notes on branches, which is most
13284              likely to be i3.  */
13285           place = i3;
13286           break;
13287
13288         case REG_NON_LOCAL_GOTO:
13289           if (JUMP_P (i3))
13290             place = i3;
13291           else
13292             {
13293               gcc_assert (i2 && JUMP_P (i2));
13294               place = i2;
13295             }
13296           break;
13297
13298         case REG_EH_REGION:
13299           /* These notes must remain with the call or trapping instruction.  */
13300           if (CALL_P (i3))
13301             place = i3;
13302           else if (i2 && CALL_P (i2))
13303             place = i2;
13304           else
13305             {
13306               gcc_assert (cfun->can_throw_non_call_exceptions);
13307               if (may_trap_p (i3))
13308                 place = i3;
13309               else if (i2 && may_trap_p (i2))
13310                 place = i2;
13311               /* ??? Otherwise assume we've combined things such that we
13312                  can now prove that the instructions can't trap.  Drop the
13313                  note in this case.  */
13314             }
13315           break;
13316
13317         case REG_ARGS_SIZE:
13318           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13319              entire adjustment.  Assert i3 contains at least some adjust.  */
13320           if (!noop_move_p (i3))
13321             {
13322               int old_size, args_size = INTVAL (XEXP (note, 0));
13323               /* fixup_args_size_notes looks at REG_NORETURN note,
13324                  so ensure the note is placed there first.  */
13325               if (CALL_P (i3))
13326                 {
13327                   rtx *np;
13328                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13329                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13330                       {
13331                         rtx n = *np;
13332                         *np = XEXP (n, 1);
13333                         XEXP (n, 1) = REG_NOTES (i3);
13334                         REG_NOTES (i3) = n;
13335                         break;
13336                       }
13337                 }
13338               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13339               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13340                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13341               gcc_assert (old_size != args_size
13342                           || (CALL_P (i3)
13343                               && !ACCUMULATE_OUTGOING_ARGS
13344                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13345             }
13346           break;
13347
13348         case REG_NORETURN:
13349         case REG_SETJMP:
13350         case REG_TM:
13351           /* These notes must remain with the call.  It should not be
13352              possible for both I2 and I3 to be a call.  */
13353           if (CALL_P (i3))
13354             place = i3;
13355           else
13356             {
13357               gcc_assert (i2 && CALL_P (i2));
13358               place = i2;
13359             }
13360           break;
13361
13362         case REG_UNUSED:
13363           /* Any clobbers for i3 may still exist, and so we must process
13364              REG_UNUSED notes from that insn.
13365
13366              Any clobbers from i2 or i1 can only exist if they were added by
13367              recog_for_combine.  In that case, recog_for_combine created the
13368              necessary REG_UNUSED notes.  Trying to keep any original
13369              REG_UNUSED notes from these insns can cause incorrect output
13370              if it is for the same register as the original i3 dest.
13371              In that case, we will notice that the register is set in i3,
13372              and then add a REG_UNUSED note for the destination of i3, which
13373              is wrong.  However, it is possible to have REG_UNUSED notes from
13374              i2 or i1 for register which were both used and clobbered, so
13375              we keep notes from i2 or i1 if they will turn into REG_DEAD
13376              notes.  */
13377
13378           /* If this register is set or clobbered in I3, put the note there
13379              unless there is one already.  */
13380           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13381             {
13382               if (from_insn != i3)
13383                 break;
13384
13385               if (! (REG_P (XEXP (note, 0))
13386                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13387                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13388                 place = i3;
13389             }
13390           /* Otherwise, if this register is used by I3, then this register
13391              now dies here, so we must put a REG_DEAD note here unless there
13392              is one already.  */
13393           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13394                    && ! (REG_P (XEXP (note, 0))
13395                          ? find_regno_note (i3, REG_DEAD,
13396                                             REGNO (XEXP (note, 0)))
13397                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13398             {
13399               PUT_REG_NOTE_KIND (note, REG_DEAD);
13400               place = i3;
13401             }
13402           break;
13403
13404         case REG_EQUAL:
13405         case REG_EQUIV:
13406         case REG_NOALIAS:
13407           /* These notes say something about results of an insn.  We can
13408              only support them if they used to be on I3 in which case they
13409              remain on I3.  Otherwise they are ignored.
13410
13411              If the note refers to an expression that is not a constant, we
13412              must also ignore the note since we cannot tell whether the
13413              equivalence is still true.  It might be possible to do
13414              slightly better than this (we only have a problem if I2DEST
13415              or I1DEST is present in the expression), but it doesn't
13416              seem worth the trouble.  */
13417
13418           if (from_insn == i3
13419               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13420             place = i3;
13421           break;
13422
13423         case REG_INC:
13424           /* These notes say something about how a register is used.  They must
13425              be present on any use of the register in I2 or I3.  */
13426           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13427             place = i3;
13428
13429           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13430             {
13431               if (place)
13432                 place2 = i2;
13433               else
13434                 place = i2;
13435             }
13436           break;
13437
13438         case REG_LABEL_TARGET:
13439         case REG_LABEL_OPERAND:
13440           /* This can show up in several ways -- either directly in the
13441              pattern, or hidden off in the constant pool with (or without?)
13442              a REG_EQUAL note.  */
13443           /* ??? Ignore the without-reg_equal-note problem for now.  */
13444           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13445               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13446                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13447                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13448             place = i3;
13449
13450           if (i2
13451               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13452                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13453                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13454                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13455             {
13456               if (place)
13457                 place2 = i2;
13458               else
13459                 place = i2;
13460             }
13461
13462           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13463              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13464              there.  */
13465           if (place && JUMP_P (place)
13466               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13467               && (JUMP_LABEL (place) == NULL
13468                   || JUMP_LABEL (place) == XEXP (note, 0)))
13469             {
13470               rtx label = JUMP_LABEL (place);
13471
13472               if (!label)
13473                 JUMP_LABEL (place) = XEXP (note, 0);
13474               else if (LABEL_P (label))
13475                 LABEL_NUSES (label)--;
13476             }
13477
13478           if (place2 && JUMP_P (place2)
13479               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13480               && (JUMP_LABEL (place2) == NULL
13481                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13482             {
13483               rtx label = JUMP_LABEL (place2);
13484
13485               if (!label)
13486                 JUMP_LABEL (place2) = XEXP (note, 0);
13487               else if (LABEL_P (label))
13488                 LABEL_NUSES (label)--;
13489               place2 = 0;
13490             }
13491           break;
13492
13493         case REG_NONNEG:
13494           /* This note says something about the value of a register prior
13495              to the execution of an insn.  It is too much trouble to see
13496              if the note is still correct in all situations.  It is better
13497              to simply delete it.  */
13498           break;
13499
13500         case REG_DEAD:
13501           /* If we replaced the right hand side of FROM_INSN with a
13502              REG_EQUAL note, the original use of the dying register
13503              will not have been combined into I3 and I2.  In such cases,
13504              FROM_INSN is guaranteed to be the first of the combined
13505              instructions, so we simply need to search back before
13506              FROM_INSN for the previous use or set of this register,
13507              then alter the notes there appropriately.
13508
13509              If the register is used as an input in I3, it dies there.
13510              Similarly for I2, if it is nonzero and adjacent to I3.
13511
13512              If the register is not used as an input in either I3 or I2
13513              and it is not one of the registers we were supposed to eliminate,
13514              there are two possibilities.  We might have a non-adjacent I2
13515              or we might have somehow eliminated an additional register
13516              from a computation.  For example, we might have had A & B where
13517              we discover that B will always be zero.  In this case we will
13518              eliminate the reference to A.
13519
13520              In both cases, we must search to see if we can find a previous
13521              use of A and put the death note there.  */
13522
13523           if (from_insn
13524               && from_insn == i2mod
13525               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13526             tem = from_insn;
13527           else
13528             {
13529               if (from_insn
13530                   && CALL_P (from_insn)
13531                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13532                 place = from_insn;
13533               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13534                 place = i3;
13535               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13536                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13537                 place = i2;
13538               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13539                         && !(i2mod
13540                              && reg_overlap_mentioned_p (XEXP (note, 0),
13541                                                          i2mod_old_rhs)))
13542                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13543                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13544                 break;
13545               tem = i3;
13546             }
13547
13548           if (place == 0)
13549             {
13550               basic_block bb = this_basic_block;
13551
13552               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13553                 {
13554                   if (!NONDEBUG_INSN_P (tem))
13555                     {
13556                       if (tem == BB_HEAD (bb))
13557                         break;
13558                       continue;
13559                     }
13560
13561                   /* If the register is being set at TEM, see if that is all
13562                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13563                      into a REG_UNUSED note instead. Don't delete sets to
13564                      global register vars.  */
13565                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13566                        || !global_regs[REGNO (XEXP (note, 0))])
13567                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13568                     {
13569                       rtx set = single_set (tem);
13570                       rtx inner_dest = 0;
13571 #ifdef HAVE_cc0
13572                       rtx cc0_setter = NULL_RTX;
13573 #endif
13574
13575                       if (set != 0)
13576                         for (inner_dest = SET_DEST (set);
13577                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13578                               || GET_CODE (inner_dest) == SUBREG
13579                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13580                              inner_dest = XEXP (inner_dest, 0))
13581                           ;
13582
13583                       /* Verify that it was the set, and not a clobber that
13584                          modified the register.
13585
13586                          CC0 targets must be careful to maintain setter/user
13587                          pairs.  If we cannot delete the setter due to side
13588                          effects, mark the user with an UNUSED note instead
13589                          of deleting it.  */
13590
13591                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13592                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13593 #ifdef HAVE_cc0
13594                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13595                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13596                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13597 #endif
13598                           )
13599                         {
13600                           /* Move the notes and links of TEM elsewhere.
13601                              This might delete other dead insns recursively.
13602                              First set the pattern to something that won't use
13603                              any register.  */
13604                           rtx old_notes = REG_NOTES (tem);
13605
13606                           PATTERN (tem) = pc_rtx;
13607                           REG_NOTES (tem) = NULL;
13608
13609                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13610                                             NULL_RTX, NULL_RTX, NULL_RTX);
13611                           distribute_links (LOG_LINKS (tem));
13612
13613                           SET_INSN_DELETED (tem);
13614                           if (tem == i2)
13615                             i2 = NULL_RTX;
13616
13617 #ifdef HAVE_cc0
13618                           /* Delete the setter too.  */
13619                           if (cc0_setter)
13620                             {
13621                               PATTERN (cc0_setter) = pc_rtx;
13622                               old_notes = REG_NOTES (cc0_setter);
13623                               REG_NOTES (cc0_setter) = NULL;
13624
13625                               distribute_notes (old_notes, cc0_setter,
13626                                                 cc0_setter, NULL_RTX,
13627                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13628                               distribute_links (LOG_LINKS (cc0_setter));
13629
13630                               SET_INSN_DELETED (cc0_setter);
13631                               if (cc0_setter == i2)
13632                                 i2 = NULL_RTX;
13633                             }
13634 #endif
13635                         }
13636                       else
13637                         {
13638                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13639
13640                           /*  If there isn't already a REG_UNUSED note, put one
13641                               here.  Do not place a REG_DEAD note, even if
13642                               the register is also used here; that would not
13643                               match the algorithm used in lifetime analysis
13644                               and can cause the consistency check in the
13645                               scheduler to fail.  */
13646                           if (! find_regno_note (tem, REG_UNUSED,
13647                                                  REGNO (XEXP (note, 0))))
13648                             place = tem;
13649                           break;
13650                         }
13651                     }
13652                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13653                            || (CALL_P (tem)
13654                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13655                     {
13656                       place = tem;
13657
13658                       /* If we are doing a 3->2 combination, and we have a
13659                          register which formerly died in i3 and was not used
13660                          by i2, which now no longer dies in i3 and is used in
13661                          i2 but does not die in i2, and place is between i2
13662                          and i3, then we may need to move a link from place to
13663                          i2.  */
13664                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13665                           && from_insn
13666                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13667                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13668                         {
13669                           struct insn_link *links = LOG_LINKS (place);
13670                           LOG_LINKS (place) = NULL;
13671                           distribute_links (links);
13672                         }
13673                       break;
13674                     }
13675
13676                   if (tem == BB_HEAD (bb))
13677                     break;
13678                 }
13679
13680             }
13681
13682           /* If the register is set or already dead at PLACE, we needn't do
13683              anything with this note if it is still a REG_DEAD note.
13684              We check here if it is set at all, not if is it totally replaced,
13685              which is what `dead_or_set_p' checks, so also check for it being
13686              set partially.  */
13687
13688           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13689             {
13690               unsigned int regno = REGNO (XEXP (note, 0));
13691               reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13692
13693               if (dead_or_set_p (place, XEXP (note, 0))
13694                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13695                 {
13696                   /* Unless the register previously died in PLACE, clear
13697                      last_death.  [I no longer understand why this is
13698                      being done.] */
13699                   if (rsp->last_death != place)
13700                     rsp->last_death = 0;
13701                   place = 0;
13702                 }
13703               else
13704                 rsp->last_death = place;
13705
13706               /* If this is a death note for a hard reg that is occupying
13707                  multiple registers, ensure that we are still using all
13708                  parts of the object.  If we find a piece of the object
13709                  that is unused, we must arrange for an appropriate REG_DEAD
13710                  note to be added for it.  However, we can't just emit a USE
13711                  and tag the note to it, since the register might actually
13712                  be dead; so we recourse, and the recursive call then finds
13713                  the previous insn that used this register.  */
13714
13715               if (place && regno < FIRST_PSEUDO_REGISTER
13716                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13717                 {
13718                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13719                   int all_used = 1;
13720                   unsigned int i;
13721
13722                   for (i = regno; i < endregno; i++)
13723                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13724                          && ! find_regno_fusage (place, USE, i))
13725                         || dead_or_set_regno_p (place, i))
13726                       all_used = 0;
13727
13728                   if (! all_used)
13729                     {
13730                       /* Put only REG_DEAD notes for pieces that are
13731                          not already dead or set.  */
13732
13733                       for (i = regno; i < endregno;
13734                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13735                         {
13736                           rtx piece = regno_reg_rtx[i];
13737                           basic_block bb = this_basic_block;
13738
13739                           if (! dead_or_set_p (place, piece)
13740                               && ! reg_bitfield_target_p (piece,
13741                                                           PATTERN (place)))
13742                             {
13743                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13744                                                              NULL_RTX);
13745
13746                               distribute_notes (new_note, place, place,
13747                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13748                                                 NULL_RTX);
13749                             }
13750                           else if (! refers_to_regno_p (i, i + 1,
13751                                                         PATTERN (place), 0)
13752                                    && ! find_regno_fusage (place, USE, i))
13753                             for (tem = PREV_INSN (place); ;
13754                                  tem = PREV_INSN (tem))
13755                               {
13756                                 if (!NONDEBUG_INSN_P (tem))
13757                                   {
13758                                     if (tem == BB_HEAD (bb))
13759                                       break;
13760                                     continue;
13761                                   }
13762                                 if (dead_or_set_p (tem, piece)
13763                                     || reg_bitfield_target_p (piece,
13764                                                               PATTERN (tem)))
13765                                   {
13766                                     add_reg_note (tem, REG_UNUSED, piece);
13767                                     break;
13768                                   }
13769                               }
13770
13771                         }
13772
13773                       place = 0;
13774                     }
13775                 }
13776             }
13777           break;
13778
13779         default:
13780           /* Any other notes should not be present at this point in the
13781              compilation.  */
13782           gcc_unreachable ();
13783         }
13784
13785       if (place)
13786         {
13787           XEXP (note, 1) = REG_NOTES (place);
13788           REG_NOTES (place) = note;
13789         }
13790
13791       if (place2)
13792         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13793     }
13794 }
13795 \f
13796 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13797    I3, I2, and I1 to new locations.  This is also called to add a link
13798    pointing at I3 when I3's destination is changed.  */
13799
13800 static void
13801 distribute_links (struct insn_link *links)
13802 {
13803   struct insn_link *link, *next_link;
13804
13805   for (link = links; link; link = next_link)
13806     {
13807       rtx place = 0;
13808       rtx insn;
13809       rtx set, reg;
13810
13811       next_link = link->next;
13812
13813       /* If the insn that this link points to is a NOTE or isn't a single
13814          set, ignore it.  In the latter case, it isn't clear what we
13815          can do other than ignore the link, since we can't tell which
13816          register it was for.  Such links wouldn't be used by combine
13817          anyway.
13818
13819          It is not possible for the destination of the target of the link to
13820          have been changed by combine.  The only potential of this is if we
13821          replace I3, I2, and I1 by I3 and I2.  But in that case the
13822          destination of I2 also remains unchanged.  */
13823
13824       if (NOTE_P (link->insn)
13825           || (set = single_set (link->insn)) == 0)
13826         continue;
13827
13828       reg = SET_DEST (set);
13829       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13830              || GET_CODE (reg) == STRICT_LOW_PART)
13831         reg = XEXP (reg, 0);
13832
13833       /* A LOG_LINK is defined as being placed on the first insn that uses
13834          a register and points to the insn that sets the register.  Start
13835          searching at the next insn after the target of the link and stop
13836          when we reach a set of the register or the end of the basic block.
13837
13838          Note that this correctly handles the link that used to point from
13839          I3 to I2.  Also note that not much searching is typically done here
13840          since most links don't point very far away.  */
13841
13842       for (insn = NEXT_INSN (link->insn);
13843            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13844                      || BB_HEAD (this_basic_block->next_bb) != insn));
13845            insn = NEXT_INSN (insn))
13846         if (DEBUG_INSN_P (insn))
13847           continue;
13848         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13849           {
13850             if (reg_referenced_p (reg, PATTERN (insn)))
13851               place = insn;
13852             break;
13853           }
13854         else if (CALL_P (insn)
13855                  && find_reg_fusage (insn, USE, reg))
13856           {
13857             place = insn;
13858             break;
13859           }
13860         else if (INSN_P (insn) && reg_set_p (reg, insn))
13861           break;
13862
13863       /* If we found a place to put the link, place it there unless there
13864          is already a link to the same insn as LINK at that point.  */
13865
13866       if (place)
13867         {
13868           struct insn_link *link2;
13869
13870           FOR_EACH_LOG_LINK (link2, place)
13871             if (link2->insn == link->insn)
13872               break;
13873
13874           if (link2 == NULL)
13875             {
13876               link->next = LOG_LINKS (place);
13877               LOG_LINKS (place) = link;
13878
13879               /* Set added_links_insn to the earliest insn we added a
13880                  link to.  */
13881               if (added_links_insn == 0
13882                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13883                 added_links_insn = place;
13884             }
13885         }
13886     }
13887 }
13888 \f
13889 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13890    Check whether the expression pointer to by LOC is a register or
13891    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13892    Otherwise return zero.  */
13893
13894 static int
13895 unmentioned_reg_p_1 (rtx *loc, void *expr)
13896 {
13897   rtx x = *loc;
13898
13899   if (x != NULL_RTX
13900       && (REG_P (x) || MEM_P (x))
13901       && ! reg_mentioned_p (x, (rtx) expr))
13902     return 1;
13903   return 0;
13904 }
13905
13906 /* Check for any register or memory mentioned in EQUIV that is not
13907    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13908    of EXPR where some registers may have been replaced by constants.  */
13909
13910 static bool
13911 unmentioned_reg_p (rtx equiv, rtx expr)
13912 {
13913   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13914 }
13915 \f
13916 void
13917 dump_combine_stats (FILE *file)
13918 {
13919   fprintf
13920     (file,
13921      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13922      combine_attempts, combine_merges, combine_extras, combine_successes);
13923 }
13924
13925 void
13926 dump_combine_total_stats (FILE *file)
13927 {
13928   fprintf
13929     (file,
13930      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13931      total_attempts, total_merges, total_extras, total_successes);
13932 }
13933 \f
13934 static bool
13935 gate_handle_combine (void)
13936 {
13937   return (optimize > 0);
13938 }
13939
13940 /* Try combining insns through substitution.  */
13941 static unsigned int
13942 rest_of_handle_combine (void)
13943 {
13944   int rebuild_jump_labels_after_combine;
13945
13946   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13947   df_note_add_problem ();
13948   df_analyze ();
13949
13950   regstat_init_n_sets_and_refs ();
13951
13952   rebuild_jump_labels_after_combine
13953     = combine_instructions (get_insns (), max_reg_num ());
13954
13955   /* Combining insns may have turned an indirect jump into a
13956      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13957      instructions.  */
13958   if (rebuild_jump_labels_after_combine)
13959     {
13960       timevar_push (TV_JUMP);
13961       rebuild_jump_labels (get_insns ());
13962       cleanup_cfg (0);
13963       timevar_pop (TV_JUMP);
13964     }
13965
13966   regstat_free_n_sets_and_refs ();
13967   return 0;
13968 }
13969
13970 struct rtl_opt_pass pass_combine =
13971 {
13972  {
13973   RTL_PASS,
13974   "combine",                            /* name */
13975   gate_handle_combine,                  /* gate */
13976   rest_of_handle_combine,               /* execute */
13977   NULL,                                 /* sub */
13978   NULL,                                 /* next */
13979   0,                                    /* static_pass_number */
13980   TV_COMBINE,                           /* tv_id */
13981   PROP_cfglayout,                       /* properties_required */
13982   0,                                    /* properties_provided */
13983   0,                                    /* properties_destroyed */
13984   0,                                    /* todo_flags_start */
13985   TODO_df_finish | TODO_verify_rtl_sharing |
13986   TODO_ggc_collect,                     /* todo_flags_finish */
13987  }
13988 };