1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static rtx
emit_set_insn (rtx
, rtx
);
146 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
149 #ifdef OBJECT_FORMAT_ELF
150 static void arm_elf_asm_constructor (rtx
, int);
153 static void arm_encode_section_info (tree
, rtx
, int);
156 static void arm_file_end (void);
159 static void aof_globalize_label (FILE *, const char *);
160 static void aof_dump_imports (FILE *);
161 static void aof_dump_pic_table (FILE *);
162 static void aof_file_start (void);
163 static void aof_file_end (void);
164 static void aof_asm_init_sections (void);
166 static rtx
arm_struct_value_rtx (tree
, int);
167 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
169 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
170 enum machine_mode
, tree
, bool);
171 static bool arm_promote_prototypes (tree
);
172 static bool arm_default_short_enums (void);
173 static bool arm_align_anon_bitfield (void);
174 static bool arm_return_in_msb (tree
);
175 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
176 #ifdef TARGET_UNWIND_INFO
177 static void arm_unwind_emit (FILE *, rtx
);
178 static bool arm_output_ttype (rtx
);
181 static tree
arm_cxx_guard_type (void);
182 static bool arm_cxx_guard_mask_bit (void);
183 static tree
arm_get_cookie_size (tree
);
184 static bool arm_cookie_has_size (void);
185 static bool arm_cxx_cdtor_returns_this (void);
186 static bool arm_cxx_key_method_may_be_inline (void);
187 static void arm_cxx_determine_class_data_visibility (tree
);
188 static bool arm_cxx_class_data_always_comdat (void);
189 static bool arm_cxx_use_aeabi_atexit (void);
190 static void arm_init_libfuncs (void);
191 static bool arm_handle_option (size_t, const char *, int);
192 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
193 static bool arm_cannot_copy_insn_p (rtx
);
194 static bool arm_tls_symbol_p (rtx x
);
197 /* Initialize the GCC target structure. */
198 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
199 #undef TARGET_MERGE_DECL_ATTRIBUTES
200 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
203 #undef TARGET_ATTRIBUTE_TABLE
204 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
206 #undef TARGET_ASM_FILE_END
207 #define TARGET_ASM_FILE_END arm_file_end
210 #undef TARGET_ASM_BYTE_OP
211 #define TARGET_ASM_BYTE_OP "\tDCB\t"
212 #undef TARGET_ASM_ALIGNED_HI_OP
213 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
216 #undef TARGET_ASM_GLOBALIZE_LABEL
217 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
218 #undef TARGET_ASM_FILE_START
219 #define TARGET_ASM_FILE_START aof_file_start
220 #undef TARGET_ASM_FILE_END
221 #define TARGET_ASM_FILE_END aof_file_end
223 #undef TARGET_ASM_ALIGNED_SI_OP
224 #define TARGET_ASM_ALIGNED_SI_OP NULL
225 #undef TARGET_ASM_INTEGER
226 #define TARGET_ASM_INTEGER arm_assemble_integer
229 #undef TARGET_ASM_FUNCTION_PROLOGUE
230 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
232 #undef TARGET_ASM_FUNCTION_EPILOGUE
233 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
235 #undef TARGET_DEFAULT_TARGET_FLAGS
236 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
237 #undef TARGET_HANDLE_OPTION
238 #define TARGET_HANDLE_OPTION arm_handle_option
240 #undef TARGET_COMP_TYPE_ATTRIBUTES
241 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
243 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
244 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
246 #undef TARGET_SCHED_ADJUST_COST
247 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
249 #undef TARGET_ENCODE_SECTION_INFO
251 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
253 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
256 #undef TARGET_STRIP_NAME_ENCODING
257 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
259 #undef TARGET_ASM_INTERNAL_LABEL
260 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
262 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
263 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
265 #undef TARGET_ASM_OUTPUT_MI_THUNK
266 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
267 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
268 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
270 /* This will be overridden in arm_override_options. */
271 #undef TARGET_RTX_COSTS
272 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
273 #undef TARGET_ADDRESS_COST
274 #define TARGET_ADDRESS_COST arm_address_cost
276 #undef TARGET_SHIFT_TRUNCATION_MASK
277 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
278 #undef TARGET_VECTOR_MODE_SUPPORTED_P
279 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
281 #undef TARGET_MACHINE_DEPENDENT_REORG
282 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
284 #undef TARGET_INIT_BUILTINS
285 #define TARGET_INIT_BUILTINS arm_init_builtins
286 #undef TARGET_EXPAND_BUILTIN
287 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
289 #undef TARGET_INIT_LIBFUNCS
290 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
292 #undef TARGET_PROMOTE_FUNCTION_ARGS
293 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
294 #undef TARGET_PROMOTE_FUNCTION_RETURN
295 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
296 #undef TARGET_PROMOTE_PROTOTYPES
297 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
298 #undef TARGET_PASS_BY_REFERENCE
299 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
300 #undef TARGET_ARG_PARTIAL_BYTES
301 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
303 #undef TARGET_STRUCT_VALUE_RTX
304 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
306 #undef TARGET_SETUP_INCOMING_VARARGS
307 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
309 #undef TARGET_DEFAULT_SHORT_ENUMS
310 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
312 #undef TARGET_ALIGN_ANON_BITFIELD
313 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
315 #undef TARGET_NARROW_VOLATILE_BITFIELD
316 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
318 #undef TARGET_CXX_GUARD_TYPE
319 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
321 #undef TARGET_CXX_GUARD_MASK_BIT
322 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
324 #undef TARGET_CXX_GET_COOKIE_SIZE
325 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
327 #undef TARGET_CXX_COOKIE_HAS_SIZE
328 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
330 #undef TARGET_CXX_CDTOR_RETURNS_THIS
331 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
333 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
334 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
336 #undef TARGET_CXX_USE_AEABI_ATEXIT
337 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
339 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
340 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
341 arm_cxx_determine_class_data_visibility
343 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
344 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
346 #undef TARGET_RETURN_IN_MSB
347 #define TARGET_RETURN_IN_MSB arm_return_in_msb
349 #undef TARGET_MUST_PASS_IN_STACK
350 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
352 #ifdef TARGET_UNWIND_INFO
353 #undef TARGET_UNWIND_EMIT
354 #define TARGET_UNWIND_EMIT arm_unwind_emit
356 /* EABI unwinding tables use a different format for the typeinfo tables. */
357 #undef TARGET_ASM_TTYPE
358 #define TARGET_ASM_TTYPE arm_output_ttype
360 #undef TARGET_ARM_EABI_UNWINDER
361 #define TARGET_ARM_EABI_UNWINDER true
362 #endif /* TARGET_UNWIND_INFO */
364 #undef TARGET_CANNOT_COPY_INSN_P
365 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
368 #undef TARGET_HAVE_TLS
369 #define TARGET_HAVE_TLS true
372 #undef TARGET_CANNOT_FORCE_CONST_MEM
373 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
375 struct gcc_target targetm
= TARGET_INITIALIZER
;
377 /* Obstack for minipool constant handling. */
378 static struct obstack minipool_obstack
;
379 static char * minipool_startobj
;
381 /* The maximum number of insns skipped which
382 will be conditionalised if possible. */
383 static int max_insns_skipped
= 5;
385 extern FILE * asm_out_file
;
387 /* True if we are currently building a constant table. */
388 int making_const_table
;
390 /* Define the information needed to generate branch insns. This is
391 stored from the compare operation. */
392 rtx arm_compare_op0
, arm_compare_op1
;
394 /* The processor for which instructions should be scheduled. */
395 enum processor_type arm_tune
= arm_none
;
397 /* Which floating point model to use. */
398 enum arm_fp_model arm_fp_model
;
400 /* Which floating point hardware is available. */
401 enum fputype arm_fpu_arch
;
403 /* Which floating point hardware to schedule for. */
404 enum fputype arm_fpu_tune
;
406 /* Whether to use floating point hardware. */
407 enum float_abi_type arm_float_abi
;
409 /* Which ABI to use. */
410 enum arm_abi_type arm_abi
;
412 /* Which thread pointer model to use. */
413 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
415 /* Used to parse -mstructure_size_boundary command line option. */
416 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
418 /* Used for Thumb call_via trampolines. */
419 rtx thumb_call_via_label
[14];
420 static int thumb_call_reg_needed
;
422 /* Bit values used to identify processor capabilities. */
423 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
424 #define FL_ARCH3M (1 << 1) /* Extended multiply */
425 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
426 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
427 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
428 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
429 #define FL_THUMB (1 << 6) /* Thumb aware */
430 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
431 #define FL_STRONG (1 << 8) /* StrongARM */
432 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
433 #define FL_XSCALE (1 << 10) /* XScale */
434 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
435 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
436 media instructions. */
437 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
438 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
439 Note: ARM6 & 7 derivatives only. */
440 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
442 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
444 #define FL_FOR_ARCH2 0
445 #define FL_FOR_ARCH3 FL_MODE32
446 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
447 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
448 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
449 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
450 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
451 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
452 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
453 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
454 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
455 #define FL_FOR_ARCH6J FL_FOR_ARCH6
456 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
457 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
458 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
460 /* The bits in this mask specify which
461 instructions we are allowed to generate. */
462 static unsigned long insn_flags
= 0;
464 /* The bits in this mask specify which instruction scheduling options should
466 static unsigned long tune_flags
= 0;
468 /* The following are used in the arm.md file as equivalents to bits
469 in the above two flag variables. */
471 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
474 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
477 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
480 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
483 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
486 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
489 /* Nonzero if this chip supports the ARM 6K extensions. */
492 /* Nonzero if this chip can benefit from load scheduling. */
493 int arm_ld_sched
= 0;
495 /* Nonzero if this chip is a StrongARM. */
496 int arm_tune_strongarm
= 0;
498 /* Nonzero if this chip is a Cirrus variant. */
499 int arm_arch_cirrus
= 0;
501 /* Nonzero if this chip supports Intel Wireless MMX technology. */
502 int arm_arch_iwmmxt
= 0;
504 /* Nonzero if this chip is an XScale. */
505 int arm_arch_xscale
= 0;
507 /* Nonzero if tuning for XScale */
508 int arm_tune_xscale
= 0;
510 /* Nonzero if we want to tune for stores that access the write-buffer.
511 This typically means an ARM6 or ARM7 with MMU or MPU. */
512 int arm_tune_wbuf
= 0;
514 /* Nonzero if generating Thumb instructions. */
517 /* Nonzero if we should define __THUMB_INTERWORK__ in the
519 XXX This is a bit of a hack, it's intended to help work around
520 problems in GLD which doesn't understand that armv5t code is
521 interworking clean. */
522 int arm_cpp_interwork
= 0;
524 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
525 must report the mode of the memory reference from PRINT_OPERAND to
526 PRINT_OPERAND_ADDRESS. */
527 enum machine_mode output_memory_reference_mode
;
529 /* The register number to be used for the PIC offset register. */
530 unsigned arm_pic_register
= INVALID_REGNUM
;
532 /* Set to 1 when a return insn is output, this means that the epilogue
534 int return_used_this_function
;
536 /* Set to 1 after arm_reorg has started. Reset to start at the start of
537 the next function. */
538 static int after_arm_reorg
= 0;
540 /* The maximum number of insns to be used when loading a constant. */
541 static int arm_constant_limit
= 3;
543 /* For an explanation of these variables, see final_prescan_insn below. */
545 enum arm_cond_code arm_current_cc
;
547 int arm_target_label
;
549 /* The condition codes of the ARM, and the inverse function. */
550 static const char * const arm_condition_codes
[] =
552 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
553 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
556 #define streq(string1, string2) (strcmp (string1, string2) == 0)
558 /* Initialization code. */
562 const char *const name
;
563 enum processor_type core
;
565 const unsigned long flags
;
566 bool (* rtx_costs
) (rtx
, int, int, int *);
569 /* Not all of these give usefully different compilation alternatives,
570 but there is no simple way of generalizing them. */
571 static const struct processors all_cores
[] =
574 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
575 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
576 #include "arm-cores.def"
578 {NULL
, arm_none
, NULL
, 0, NULL
}
581 static const struct processors all_architectures
[] =
583 /* ARM Architectures */
584 /* We don't specify rtx_costs here as it will be figured out
587 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
588 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
589 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
590 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
591 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
592 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
593 implementations that support it, so we will leave it out for now. */
594 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
595 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
596 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
597 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
598 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
599 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
600 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
601 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
602 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
603 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
604 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
605 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
606 {NULL
, arm_none
, NULL
, 0 , NULL
}
609 struct arm_cpu_select
613 const struct processors
* processors
;
616 /* This is a magic structure. The 'string' field is magically filled in
617 with a pointer to the value specified by the user on the command line
618 assuming that the user has specified such a value. */
620 static struct arm_cpu_select arm_select
[] =
622 /* string name processors */
623 { NULL
, "-mcpu=", all_cores
},
624 { NULL
, "-march=", all_architectures
},
625 { NULL
, "-mtune=", all_cores
}
628 /* Defines representing the indexes into the above table. */
629 #define ARM_OPT_SET_CPU 0
630 #define ARM_OPT_SET_ARCH 1
631 #define ARM_OPT_SET_TUNE 2
633 /* The name of the proprocessor macro to define for this architecture. */
635 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
644 /* Available values for -mfpu=. */
646 static const struct fpu_desc all_fpus
[] =
648 {"fpa", FPUTYPE_FPA
},
649 {"fpe2", FPUTYPE_FPA_EMU2
},
650 {"fpe3", FPUTYPE_FPA_EMU2
},
651 {"maverick", FPUTYPE_MAVERICK
},
656 /* Floating point models used by the different hardware.
657 See fputype in arm.h. */
659 static const enum fputype fp_model_for_fpu
[] =
661 /* No FP hardware. */
662 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
663 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
664 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
665 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
666 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
667 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
674 enum float_abi_type abi_type
;
678 /* Available values for -mfloat-abi=. */
680 static const struct float_abi all_float_abis
[] =
682 {"soft", ARM_FLOAT_ABI_SOFT
},
683 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
684 {"hard", ARM_FLOAT_ABI_HARD
}
691 enum arm_abi_type abi_type
;
695 /* Available values for -mabi=. */
697 static const struct abi_name arm_all_abis
[] =
699 {"apcs-gnu", ARM_ABI_APCS
},
700 {"atpcs", ARM_ABI_ATPCS
},
701 {"aapcs", ARM_ABI_AAPCS
},
702 {"iwmmxt", ARM_ABI_IWMMXT
},
703 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
706 /* Supported TLS relocations. */
716 /* Emit an insn that's a simple single-set. Both the operands must be known
719 emit_set_insn (rtx x
, rtx y
)
721 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
724 /* Return the number of bits set in VALUE. */
726 bit_count (unsigned long value
)
728 unsigned long count
= 0;
733 value
&= value
- 1; /* Clear the least-significant set bit. */
739 /* Set up library functions unique to ARM. */
742 arm_init_libfuncs (void)
744 /* There are no special library functions unless we are using the
749 /* The functions below are described in Section 4 of the "Run-Time
750 ABI for the ARM architecture", Version 1.0. */
752 /* Double-precision floating-point arithmetic. Table 2. */
753 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
754 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
755 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
756 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
757 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
759 /* Double-precision comparisons. Table 3. */
760 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
761 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
762 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
763 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
764 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
765 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
766 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
768 /* Single-precision floating-point arithmetic. Table 4. */
769 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
770 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
771 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
772 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
773 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
775 /* Single-precision comparisons. Table 5. */
776 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
777 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
778 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
779 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
780 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
781 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
782 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
784 /* Floating-point to integer conversions. Table 6. */
785 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
786 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
787 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
788 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
789 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
790 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
791 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
792 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
794 /* Conversions between floating types. Table 7. */
795 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
796 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
798 /* Integer to floating-point conversions. Table 8. */
799 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
800 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
801 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
802 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
803 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
804 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
805 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
806 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
808 /* Long long. Table 9. */
809 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
810 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
811 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
812 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
813 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
814 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
815 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
816 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
818 /* Integer (32/32->32) division. \S 4.3.1. */
819 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
820 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
822 /* The divmod functions are designed so that they can be used for
823 plain division, even though they return both the quotient and the
824 remainder. The quotient is returned in the usual location (i.e.,
825 r0 for SImode, {r0, r1} for DImode), just as would be expected
826 for an ordinary division routine. Because the AAPCS calling
827 conventions specify that all of { r0, r1, r2, r3 } are
828 callee-saved registers, there is no need to tell the compiler
829 explicitly that those registers are clobbered by these
831 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
832 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
834 /* For SImode division the ABI provides div-without-mod routines,
836 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
837 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
839 /* We don't have mod libcalls. Fortunately gcc knows how to use the
840 divmod libcalls instead. */
841 set_optab_libfunc (smod_optab
, DImode
, NULL
);
842 set_optab_libfunc (umod_optab
, DImode
, NULL
);
843 set_optab_libfunc (smod_optab
, SImode
, NULL
);
844 set_optab_libfunc (umod_optab
, SImode
, NULL
);
847 /* Implement TARGET_HANDLE_OPTION. */
850 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
855 arm_select
[1].string
= arg
;
859 arm_select
[0].string
= arg
;
862 case OPT_mhard_float
:
863 target_float_abi_name
= "hard";
866 case OPT_msoft_float
:
867 target_float_abi_name
= "soft";
871 arm_select
[2].string
= arg
;
879 /* Fix up any incompatible options that the user has specified.
880 This has now turned into a maze. */
882 arm_override_options (void)
885 enum processor_type target_arch_cpu
= arm_none
;
887 /* Set up the flags based on the cpu/architecture selected by the user. */
888 for (i
= ARRAY_SIZE (arm_select
); i
--;)
890 struct arm_cpu_select
* ptr
= arm_select
+ i
;
892 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
894 const struct processors
* sel
;
896 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
897 if (streq (ptr
->string
, sel
->name
))
899 /* Set the architecture define. */
900 if (i
!= ARM_OPT_SET_TUNE
)
901 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
903 /* Determine the processor core for which we should
904 tune code-generation. */
905 if (/* -mcpu= is a sensible default. */
907 /* -mtune= overrides -mcpu= and -march=. */
908 || i
== ARM_OPT_SET_TUNE
)
909 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
911 /* Remember the CPU associated with this architecture.
912 If no other option is used to set the CPU type,
913 we'll use this to guess the most suitable tuning
915 if (i
== ARM_OPT_SET_ARCH
)
916 target_arch_cpu
= sel
->core
;
918 if (i
!= ARM_OPT_SET_TUNE
)
920 /* If we have been given an architecture and a processor
921 make sure that they are compatible. We only generate
922 a warning though, and we prefer the CPU over the
924 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
925 warning (0, "switch -mcpu=%s conflicts with -march= switch",
928 insn_flags
= sel
->flags
;
934 if (sel
->name
== NULL
)
935 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
939 /* Guess the tuning options from the architecture if necessary. */
940 if (arm_tune
== arm_none
)
941 arm_tune
= target_arch_cpu
;
943 /* If the user did not specify a processor, choose one for them. */
946 const struct processors
* sel
;
948 enum processor_type cpu
;
950 cpu
= TARGET_CPU_DEFAULT
;
953 #ifdef SUBTARGET_CPU_DEFAULT
954 /* Use the subtarget default CPU if none was specified by
956 cpu
= SUBTARGET_CPU_DEFAULT
;
958 /* Default to ARM6. */
962 sel
= &all_cores
[cpu
];
964 insn_flags
= sel
->flags
;
966 /* Now check to see if the user has specified some command line
967 switch that require certain abilities from the cpu. */
970 if (TARGET_INTERWORK
|| TARGET_THUMB
)
972 sought
|= (FL_THUMB
| FL_MODE32
);
974 /* There are no ARM processors that support both APCS-26 and
975 interworking. Therefore we force FL_MODE26 to be removed
976 from insn_flags here (if it was set), so that the search
977 below will always be able to find a compatible processor. */
978 insn_flags
&= ~FL_MODE26
;
981 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
983 /* Try to locate a CPU type that supports all of the abilities
984 of the default CPU, plus the extra abilities requested by
986 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
987 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
990 if (sel
->name
== NULL
)
992 unsigned current_bit_count
= 0;
993 const struct processors
* best_fit
= NULL
;
995 /* Ideally we would like to issue an error message here
996 saying that it was not possible to find a CPU compatible
997 with the default CPU, but which also supports the command
998 line options specified by the programmer, and so they
999 ought to use the -mcpu=<name> command line option to
1000 override the default CPU type.
1002 If we cannot find a cpu that has both the
1003 characteristics of the default cpu and the given
1004 command line options we scan the array again looking
1005 for a best match. */
1006 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1007 if ((sel
->flags
& sought
) == sought
)
1011 count
= bit_count (sel
->flags
& insn_flags
);
1013 if (count
>= current_bit_count
)
1016 current_bit_count
= count
;
1020 gcc_assert (best_fit
);
1024 insn_flags
= sel
->flags
;
1026 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1027 if (arm_tune
== arm_none
)
1028 arm_tune
= (enum processor_type
) (sel
- all_cores
);
1031 /* The processor for which we should tune should now have been
1033 gcc_assert (arm_tune
!= arm_none
);
1035 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1037 targetm
.rtx_costs
= arm_size_rtx_costs
;
1039 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1041 /* Make sure that the processor choice does not conflict with any of the
1042 other command line choices. */
1043 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1045 warning (0, "target CPU does not support interworking" );
1046 target_flags
&= ~MASK_INTERWORK
;
1049 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1051 warning (0, "target CPU does not support THUMB instructions");
1052 target_flags
&= ~MASK_THUMB
;
1055 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1057 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1058 target_flags
&= ~MASK_APCS_FRAME
;
1061 /* Callee super interworking implies thumb interworking. Adding
1062 this to the flags here simplifies the logic elsewhere. */
1063 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1064 target_flags
|= MASK_INTERWORK
;
1066 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1067 from here where no function is being compiled currently. */
1068 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1069 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1071 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1072 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1074 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1075 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1077 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1079 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1080 target_flags
|= MASK_APCS_FRAME
;
1083 if (TARGET_POKE_FUNCTION_NAME
)
1084 target_flags
|= MASK_APCS_FRAME
;
1086 if (TARGET_APCS_REENT
&& flag_pic
)
1087 error ("-fpic and -mapcs-reent are incompatible");
1089 if (TARGET_APCS_REENT
)
1090 warning (0, "APCS reentrant code not supported. Ignored");
1092 /* If this target is normally configured to use APCS frames, warn if they
1093 are turned off and debugging is turned on. */
1095 && write_symbols
!= NO_DEBUG
1096 && !TARGET_APCS_FRAME
1097 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1098 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1100 /* If stack checking is disabled, we can use r10 as the PIC register,
1101 which keeps r9 available. */
1102 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1103 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1105 if (TARGET_APCS_FLOAT
)
1106 warning (0, "passing floating point arguments in fp regs not yet supported");
1108 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1109 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1110 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1111 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1112 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1113 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1114 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1115 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1116 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1117 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1119 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1120 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1121 thumb_code
= (TARGET_ARM
== 0);
1122 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1123 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1124 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1126 /* V5 code we generate is completely interworking capable, so we turn off
1127 TARGET_INTERWORK here to avoid many tests later on. */
1129 /* XXX However, we must pass the right pre-processor defines to CPP
1130 or GLD can get confused. This is a hack. */
1131 if (TARGET_INTERWORK
)
1132 arm_cpp_interwork
= 1;
1135 target_flags
&= ~MASK_INTERWORK
;
1137 if (target_abi_name
)
1139 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1141 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1143 arm_abi
= arm_all_abis
[i
].abi_type
;
1147 if (i
== ARRAY_SIZE (arm_all_abis
))
1148 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1151 arm_abi
= ARM_DEFAULT_ABI
;
1153 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1154 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1156 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1157 error ("iwmmxt abi requires an iwmmxt capable cpu");
1159 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1160 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1162 if (streq (target_fpe_name
, "2"))
1163 target_fpu_name
= "fpe2";
1164 else if (streq (target_fpe_name
, "3"))
1165 target_fpu_name
= "fpe3";
1167 error ("invalid floating point emulation option: -mfpe=%s",
1170 if (target_fpu_name
!= NULL
)
1172 /* The user specified a FPU. */
1173 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1175 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1177 arm_fpu_arch
= all_fpus
[i
].fpu
;
1178 arm_fpu_tune
= arm_fpu_arch
;
1179 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1183 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1184 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1188 #ifdef FPUTYPE_DEFAULT
1189 /* Use the default if it is specified for this platform. */
1190 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1191 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1193 /* Pick one based on CPU type. */
1194 /* ??? Some targets assume FPA is the default.
1195 if ((insn_flags & FL_VFP) != 0)
1196 arm_fpu_arch = FPUTYPE_VFP;
1199 if (arm_arch_cirrus
)
1200 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1202 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1204 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1205 arm_fpu_tune
= FPUTYPE_FPA
;
1207 arm_fpu_tune
= arm_fpu_arch
;
1208 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1209 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1212 if (target_float_abi_name
!= NULL
)
1214 /* The user specified a FP ABI. */
1215 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1217 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1219 arm_float_abi
= all_float_abis
[i
].abi_type
;
1223 if (i
== ARRAY_SIZE (all_float_abis
))
1224 error ("invalid floating point abi: -mfloat-abi=%s",
1225 target_float_abi_name
);
1228 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1230 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1231 sorry ("-mfloat-abi=hard and VFP");
1233 /* If soft-float is specified then don't use FPU. */
1234 if (TARGET_SOFT_FLOAT
)
1235 arm_fpu_arch
= FPUTYPE_NONE
;
1237 /* For arm2/3 there is no need to do any scheduling if there is only
1238 a floating point emulator, or we are doing software floating-point. */
1239 if ((TARGET_SOFT_FLOAT
1240 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1241 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1242 && (tune_flags
& FL_MODE32
) == 0)
1243 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1245 if (target_thread_switch
)
1247 if (strcmp (target_thread_switch
, "soft") == 0)
1248 target_thread_pointer
= TP_SOFT
;
1249 else if (strcmp (target_thread_switch
, "auto") == 0)
1250 target_thread_pointer
= TP_AUTO
;
1251 else if (strcmp (target_thread_switch
, "cp15") == 0)
1252 target_thread_pointer
= TP_CP15
;
1254 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1257 /* Use the cp15 method if it is available. */
1258 if (target_thread_pointer
== TP_AUTO
)
1260 if (arm_arch6k
&& !TARGET_THUMB
)
1261 target_thread_pointer
= TP_CP15
;
1263 target_thread_pointer
= TP_SOFT
;
1266 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1267 error ("can not use -mtp=cp15 with -mthumb");
1269 /* Override the default structure alignment for AAPCS ABI. */
1270 if (TARGET_AAPCS_BASED
)
1271 arm_structure_size_boundary
= 8;
1273 if (structure_size_string
!= NULL
)
1275 int size
= strtol (structure_size_string
, NULL
, 0);
1277 if (size
== 8 || size
== 32
1278 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1279 arm_structure_size_boundary
= size
;
1281 warning (0, "structure size boundary can only be set to %s",
1282 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1285 if (arm_pic_register_string
!= NULL
)
1287 int pic_register
= decode_reg_name (arm_pic_register_string
);
1290 warning (0, "-mpic-register= is useless without -fpic");
1292 /* Prevent the user from choosing an obviously stupid PIC register. */
1293 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1294 || pic_register
== HARD_FRAME_POINTER_REGNUM
1295 || pic_register
== STACK_POINTER_REGNUM
1296 || pic_register
>= PC_REGNUM
)
1297 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1299 arm_pic_register
= pic_register
;
1302 if (TARGET_THUMB
&& flag_schedule_insns
)
1304 /* Don't warn since it's on by default in -O2. */
1305 flag_schedule_insns
= 0;
1310 arm_constant_limit
= 1;
1312 /* If optimizing for size, bump the number of instructions that we
1313 are prepared to conditionally execute (even on a StrongARM). */
1314 max_insns_skipped
= 6;
1318 /* For processors with load scheduling, it never costs more than
1319 2 cycles to load a constant, and the load scheduler may well
1320 reduce that to 1. */
1322 arm_constant_limit
= 1;
1324 /* On XScale the longer latency of a load makes it more difficult
1325 to achieve a good schedule, so it's faster to synthesize
1326 constants that can be done in two insns. */
1327 if (arm_tune_xscale
)
1328 arm_constant_limit
= 2;
1330 /* StrongARM has early execution of branches, so a sequence
1331 that is worth skipping is shorter. */
1332 if (arm_tune_strongarm
)
1333 max_insns_skipped
= 3;
1336 /* Register global variables with the garbage collector. */
1337 arm_add_gc_roots ();
1341 arm_add_gc_roots (void)
1343 gcc_obstack_init(&minipool_obstack
);
1344 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1347 /* A table of known ARM exception types.
1348 For use with the interrupt function attribute. */
1352 const char *const arg
;
1353 const unsigned long return_value
;
1357 static const isr_attribute_arg isr_attribute_args
[] =
1359 { "IRQ", ARM_FT_ISR
},
1360 { "irq", ARM_FT_ISR
},
1361 { "FIQ", ARM_FT_FIQ
},
1362 { "fiq", ARM_FT_FIQ
},
1363 { "ABORT", ARM_FT_ISR
},
1364 { "abort", ARM_FT_ISR
},
1365 { "ABORT", ARM_FT_ISR
},
1366 { "abort", ARM_FT_ISR
},
1367 { "UNDEF", ARM_FT_EXCEPTION
},
1368 { "undef", ARM_FT_EXCEPTION
},
1369 { "SWI", ARM_FT_EXCEPTION
},
1370 { "swi", ARM_FT_EXCEPTION
},
1371 { NULL
, ARM_FT_NORMAL
}
1374 /* Returns the (interrupt) function type of the current
1375 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1377 static unsigned long
1378 arm_isr_value (tree argument
)
1380 const isr_attribute_arg
* ptr
;
1383 /* No argument - default to IRQ. */
1384 if (argument
== NULL_TREE
)
1387 /* Get the value of the argument. */
1388 if (TREE_VALUE (argument
) == NULL_TREE
1389 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1390 return ARM_FT_UNKNOWN
;
1392 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1394 /* Check it against the list of known arguments. */
1395 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1396 if (streq (arg
, ptr
->arg
))
1397 return ptr
->return_value
;
1399 /* An unrecognized interrupt type. */
1400 return ARM_FT_UNKNOWN
;
1403 /* Computes the type of the current function. */
1405 static unsigned long
1406 arm_compute_func_type (void)
1408 unsigned long type
= ARM_FT_UNKNOWN
;
1412 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1414 /* Decide if the current function is volatile. Such functions
1415 never return, and many memory cycles can be saved by not storing
1416 register values that will never be needed again. This optimization
1417 was added to speed up context switching in a kernel application. */
1419 && (TREE_NOTHROW (current_function_decl
)
1420 || !(flag_unwind_tables
1421 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
)))
1422 && TREE_THIS_VOLATILE (current_function_decl
))
1423 type
|= ARM_FT_VOLATILE
;
1425 if (cfun
->static_chain_decl
!= NULL
)
1426 type
|= ARM_FT_NESTED
;
1428 attr
= DECL_ATTRIBUTES (current_function_decl
);
1430 a
= lookup_attribute ("naked", attr
);
1432 type
|= ARM_FT_NAKED
;
1434 a
= lookup_attribute ("isr", attr
);
1436 a
= lookup_attribute ("interrupt", attr
);
1439 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1441 type
|= arm_isr_value (TREE_VALUE (a
));
1446 /* Returns the type of the current function. */
1449 arm_current_func_type (void)
1451 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1452 cfun
->machine
->func_type
= arm_compute_func_type ();
1454 return cfun
->machine
->func_type
;
1457 /* Return 1 if it is possible to return using a single instruction.
1458 If SIBLING is non-null, this is a test for a return before a sibling
1459 call. SIBLING is the call insn, so we can examine its register usage. */
1462 use_return_insn (int iscond
, rtx sibling
)
1465 unsigned int func_type
;
1466 unsigned long saved_int_regs
;
1467 unsigned HOST_WIDE_INT stack_adjust
;
1468 arm_stack_offsets
*offsets
;
1470 /* Never use a return instruction before reload has run. */
1471 if (!reload_completed
)
1474 func_type
= arm_current_func_type ();
1476 /* Naked functions and volatile functions need special
1478 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1481 /* So do interrupt functions that use the frame pointer. */
1482 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1485 offsets
= arm_get_frame_offsets ();
1486 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1488 /* As do variadic functions. */
1489 if (current_function_pretend_args_size
1490 || cfun
->machine
->uses_anonymous_args
1491 /* Or if the function calls __builtin_eh_return () */
1492 || current_function_calls_eh_return
1493 /* Or if the function calls alloca */
1494 || current_function_calls_alloca
1495 /* Or if there is a stack adjustment. However, if the stack pointer
1496 is saved on the stack, we can use a pre-incrementing stack load. */
1497 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1500 saved_int_regs
= arm_compute_save_reg_mask ();
1502 /* Unfortunately, the insn
1504 ldmib sp, {..., sp, ...}
1506 triggers a bug on most SA-110 based devices, such that the stack
1507 pointer won't be correctly restored if the instruction takes a
1508 page fault. We work around this problem by popping r3 along with
1509 the other registers, since that is never slower than executing
1510 another instruction.
1512 We test for !arm_arch5 here, because code for any architecture
1513 less than this could potentially be run on one of the buggy
1515 if (stack_adjust
== 4 && !arm_arch5
)
1517 /* Validate that r3 is a call-clobbered register (always true in
1518 the default abi) ... */
1519 if (!call_used_regs
[3])
1522 /* ... that it isn't being used for a return value ... */
1523 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1526 /* ... or for a tail-call argument ... */
1529 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1531 if (find_regno_fusage (sibling
, USE
, 3))
1535 /* ... and that there are no call-saved registers in r0-r2
1536 (always true in the default ABI). */
1537 if (saved_int_regs
& 0x7)
1541 /* Can't be done if interworking with Thumb, and any registers have been
1543 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1546 /* On StrongARM, conditional returns are expensive if they aren't
1547 taken and multiple registers have been stacked. */
1548 if (iscond
&& arm_tune_strongarm
)
1550 /* Conditional return when just the LR is stored is a simple
1551 conditional-load instruction, that's not expensive. */
1552 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1556 && arm_pic_register
!= INVALID_REGNUM
1557 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1561 /* If there are saved registers but the LR isn't saved, then we need
1562 two instructions for the return. */
1563 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1566 /* Can't be done if any of the FPA regs are pushed,
1567 since this also requires an insn. */
1568 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1569 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1570 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1573 /* Likewise VFP regs. */
1574 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1575 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1576 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1579 if (TARGET_REALLY_IWMMXT
)
1580 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1581 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1587 /* Return TRUE if int I is a valid immediate ARM constant. */
1590 const_ok_for_arm (HOST_WIDE_INT i
)
1594 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1595 be all zero, or all one. */
1596 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1597 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1598 != ((~(unsigned HOST_WIDE_INT
) 0)
1599 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1602 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1604 /* Fast return for 0 and small values. We must do this for zero, since
1605 the code below can't handle that one case. */
1606 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1609 /* Get the number of trailing zeros, rounded down to the nearest even
1611 lowbit
= (ffs ((int) i
) - 1) & ~1;
1613 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1615 else if (lowbit
<= 4
1616 && ((i
& ~0xc000003f) == 0
1617 || (i
& ~0xf000000f) == 0
1618 || (i
& ~0xfc000003) == 0))
1624 /* Return true if I is a valid constant for the operation CODE. */
1626 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1628 if (const_ok_for_arm (i
))
1634 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1636 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1642 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1649 /* Emit a sequence of insns to handle a large constant.
1650 CODE is the code of the operation required, it can be any of SET, PLUS,
1651 IOR, AND, XOR, MINUS;
1652 MODE is the mode in which the operation is being performed;
1653 VAL is the integer to operate on;
1654 SOURCE is the other operand (a register, or a null-pointer for SET);
1655 SUBTARGETS means it is safe to create scratch registers if that will
1656 either produce a simpler sequence, or we will want to cse the values.
1657 Return value is the number of insns emitted. */
1660 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1661 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1665 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1666 cond
= COND_EXEC_TEST (PATTERN (insn
));
1670 if (subtargets
|| code
== SET
1671 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1672 && REGNO (target
) != REGNO (source
)))
1674 /* After arm_reorg has been called, we can't fix up expensive
1675 constants by pushing them into memory so we must synthesize
1676 them in-line, regardless of the cost. This is only likely to
1677 be more costly on chips that have load delay slots and we are
1678 compiling without running the scheduler (so no splitting
1679 occurred before the final instruction emission).
1681 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1683 if (!after_arm_reorg
1685 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1687 > arm_constant_limit
+ (code
!= SET
)))
1691 /* Currently SET is the only monadic value for CODE, all
1692 the rest are diadic. */
1693 emit_set_insn (target
, GEN_INT (val
));
1698 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1700 emit_set_insn (temp
, GEN_INT (val
));
1701 /* For MINUS, the value is subtracted from, since we never
1702 have subtraction of a constant. */
1704 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
1706 emit_set_insn (target
,
1707 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
1713 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1718 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1720 HOST_WIDE_INT temp1
;
1728 if (remainder
& (3 << (i
- 2)))
1733 temp1
= remainder
& ((0x0ff << end
)
1734 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1735 remainder
&= ~temp1
;
1740 } while (remainder
);
1744 /* Emit an instruction with the indicated PATTERN. If COND is
1745 non-NULL, conditionalize the execution of the instruction on COND
1749 emit_constant_insn (rtx cond
, rtx pattern
)
1752 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1753 emit_insn (pattern
);
1756 /* As above, but extra parameter GENERATE which, if clear, suppresses
1760 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1761 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1766 int can_negate_initial
= 0;
1769 int num_bits_set
= 0;
1770 int set_sign_bit_copies
= 0;
1771 int clear_sign_bit_copies
= 0;
1772 int clear_zero_bit_copies
= 0;
1773 int set_zero_bit_copies
= 0;
1775 unsigned HOST_WIDE_INT temp1
, temp2
;
1776 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1778 /* Find out which operations are safe for a given CODE. Also do a quick
1779 check for degenerate cases; these can occur when DImode operations
1791 can_negate_initial
= 1;
1795 if (remainder
== 0xffffffff)
1798 emit_constant_insn (cond
,
1799 gen_rtx_SET (VOIDmode
, target
,
1800 GEN_INT (ARM_SIGN_EXTEND (val
))));
1805 if (reload_completed
&& rtx_equal_p (target
, source
))
1808 emit_constant_insn (cond
,
1809 gen_rtx_SET (VOIDmode
, target
, source
));
1818 emit_constant_insn (cond
,
1819 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1822 if (remainder
== 0xffffffff)
1824 if (reload_completed
&& rtx_equal_p (target
, source
))
1827 emit_constant_insn (cond
,
1828 gen_rtx_SET (VOIDmode
, target
, source
));
1837 if (reload_completed
&& rtx_equal_p (target
, source
))
1840 emit_constant_insn (cond
,
1841 gen_rtx_SET (VOIDmode
, target
, source
));
1845 /* We don't know how to handle other cases yet. */
1846 gcc_assert (remainder
== 0xffffffff);
1849 emit_constant_insn (cond
,
1850 gen_rtx_SET (VOIDmode
, target
,
1851 gen_rtx_NOT (mode
, source
)));
1855 /* We treat MINUS as (val - source), since (source - val) is always
1856 passed as (source + (-val)). */
1860 emit_constant_insn (cond
,
1861 gen_rtx_SET (VOIDmode
, target
,
1862 gen_rtx_NEG (mode
, source
)));
1865 if (const_ok_for_arm (val
))
1868 emit_constant_insn (cond
,
1869 gen_rtx_SET (VOIDmode
, target
,
1870 gen_rtx_MINUS (mode
, GEN_INT (val
),
1882 /* If we can do it in one insn get out quickly. */
1883 if (const_ok_for_arm (val
)
1884 || (can_negate_initial
&& const_ok_for_arm (-val
))
1885 || (can_invert
&& const_ok_for_arm (~val
)))
1888 emit_constant_insn (cond
,
1889 gen_rtx_SET (VOIDmode
, target
,
1891 ? gen_rtx_fmt_ee (code
, mode
, source
,
1897 /* Calculate a few attributes that may be useful for specific
1899 for (i
= 31; i
>= 0; i
--)
1901 if ((remainder
& (1 << i
)) == 0)
1902 clear_sign_bit_copies
++;
1907 for (i
= 31; i
>= 0; i
--)
1909 if ((remainder
& (1 << i
)) != 0)
1910 set_sign_bit_copies
++;
1915 for (i
= 0; i
<= 31; i
++)
1917 if ((remainder
& (1 << i
)) == 0)
1918 clear_zero_bit_copies
++;
1923 for (i
= 0; i
<= 31; i
++)
1925 if ((remainder
& (1 << i
)) != 0)
1926 set_zero_bit_copies
++;
1934 /* See if we can do this by sign_extending a constant that is known
1935 to be negative. This is a good, way of doing it, since the shift
1936 may well merge into a subsequent insn. */
1937 if (set_sign_bit_copies
> 1)
1939 if (const_ok_for_arm
1940 (temp1
= ARM_SIGN_EXTEND (remainder
1941 << (set_sign_bit_copies
- 1))))
1945 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1946 emit_constant_insn (cond
,
1947 gen_rtx_SET (VOIDmode
, new_src
,
1949 emit_constant_insn (cond
,
1950 gen_ashrsi3 (target
, new_src
,
1951 GEN_INT (set_sign_bit_copies
- 1)));
1955 /* For an inverted constant, we will need to set the low bits,
1956 these will be shifted out of harm's way. */
1957 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1958 if (const_ok_for_arm (~temp1
))
1962 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1963 emit_constant_insn (cond
,
1964 gen_rtx_SET (VOIDmode
, new_src
,
1966 emit_constant_insn (cond
,
1967 gen_ashrsi3 (target
, new_src
,
1968 GEN_INT (set_sign_bit_copies
- 1)));
1974 /* See if we can calculate the value as the difference between two
1975 valid immediates. */
1976 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1978 int topshift
= clear_sign_bit_copies
& ~1;
1980 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1981 & (0xff000000 >> topshift
));
1983 /* If temp1 is zero, then that means the 9 most significant
1984 bits of remainder were 1 and we've caused it to overflow.
1985 When topshift is 0 we don't need to do anything since we
1986 can borrow from 'bit 32'. */
1987 if (temp1
== 0 && topshift
!= 0)
1988 temp1
= 0x80000000 >> (topshift
- 1);
1990 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1992 if (const_ok_for_arm (temp2
))
1996 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1997 emit_constant_insn (cond
,
1998 gen_rtx_SET (VOIDmode
, new_src
,
2000 emit_constant_insn (cond
,
2001 gen_addsi3 (target
, new_src
,
2009 /* See if we can generate this by setting the bottom (or the top)
2010 16 bits, and then shifting these into the other half of the
2011 word. We only look for the simplest cases, to do more would cost
2012 too much. Be careful, however, not to generate this when the
2013 alternative would take fewer insns. */
2014 if (val
& 0xffff0000)
2016 temp1
= remainder
& 0xffff0000;
2017 temp2
= remainder
& 0x0000ffff;
2019 /* Overlaps outside this range are best done using other methods. */
2020 for (i
= 9; i
< 24; i
++)
2022 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2023 && !const_ok_for_arm (temp2
))
2025 rtx new_src
= (subtargets
2026 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2028 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2029 source
, subtargets
, generate
);
2037 gen_rtx_ASHIFT (mode
, source
,
2044 /* Don't duplicate cases already considered. */
2045 for (i
= 17; i
< 24; i
++)
2047 if (((temp1
| (temp1
>> i
)) == remainder
)
2048 && !const_ok_for_arm (temp1
))
2050 rtx new_src
= (subtargets
2051 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2053 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2054 source
, subtargets
, generate
);
2059 gen_rtx_SET (VOIDmode
, target
,
2062 gen_rtx_LSHIFTRT (mode
, source
,
2073 /* If we have IOR or XOR, and the constant can be loaded in a
2074 single instruction, and we can find a temporary to put it in,
2075 then this can be done in two instructions instead of 3-4. */
2077 /* TARGET can't be NULL if SUBTARGETS is 0 */
2078 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2080 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2084 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2086 emit_constant_insn (cond
,
2087 gen_rtx_SET (VOIDmode
, sub
,
2089 emit_constant_insn (cond
,
2090 gen_rtx_SET (VOIDmode
, target
,
2091 gen_rtx_fmt_ee (code
, mode
,
2101 if (set_sign_bit_copies
> 8
2102 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2106 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2107 rtx shift
= GEN_INT (set_sign_bit_copies
);
2111 gen_rtx_SET (VOIDmode
, sub
,
2113 gen_rtx_ASHIFT (mode
,
2118 gen_rtx_SET (VOIDmode
, target
,
2120 gen_rtx_LSHIFTRT (mode
, sub
,
2126 if (set_zero_bit_copies
> 8
2127 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2131 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2132 rtx shift
= GEN_INT (set_zero_bit_copies
);
2136 gen_rtx_SET (VOIDmode
, sub
,
2138 gen_rtx_LSHIFTRT (mode
,
2143 gen_rtx_SET (VOIDmode
, target
,
2145 gen_rtx_ASHIFT (mode
, sub
,
2151 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2155 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2156 emit_constant_insn (cond
,
2157 gen_rtx_SET (VOIDmode
, sub
,
2158 gen_rtx_NOT (mode
, source
)));
2161 sub
= gen_reg_rtx (mode
);
2162 emit_constant_insn (cond
,
2163 gen_rtx_SET (VOIDmode
, sub
,
2164 gen_rtx_AND (mode
, source
,
2166 emit_constant_insn (cond
,
2167 gen_rtx_SET (VOIDmode
, target
,
2168 gen_rtx_NOT (mode
, sub
)));
2175 /* See if two shifts will do 2 or more insn's worth of work. */
2176 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2178 HOST_WIDE_INT shift_mask
= ((0xffffffff
2179 << (32 - clear_sign_bit_copies
))
2182 if ((remainder
| shift_mask
) != 0xffffffff)
2186 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2187 insns
= arm_gen_constant (AND
, mode
, cond
,
2188 remainder
| shift_mask
,
2189 new_src
, source
, subtargets
, 1);
2194 rtx targ
= subtargets
? NULL_RTX
: target
;
2195 insns
= arm_gen_constant (AND
, mode
, cond
,
2196 remainder
| shift_mask
,
2197 targ
, source
, subtargets
, 0);
2203 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2204 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2206 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2207 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2213 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2215 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2217 if ((remainder
| shift_mask
) != 0xffffffff)
2221 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2223 insns
= arm_gen_constant (AND
, mode
, cond
,
2224 remainder
| shift_mask
,
2225 new_src
, source
, subtargets
, 1);
2230 rtx targ
= subtargets
? NULL_RTX
: target
;
2232 insns
= arm_gen_constant (AND
, mode
, cond
,
2233 remainder
| shift_mask
,
2234 targ
, source
, subtargets
, 0);
2240 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2241 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2243 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2244 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2256 for (i
= 0; i
< 32; i
++)
2257 if (remainder
& (1 << i
))
2260 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2261 remainder
= (~remainder
) & 0xffffffff;
2262 else if (code
== PLUS
&& num_bits_set
> 16)
2263 remainder
= (-remainder
) & 0xffffffff;
2270 /* Now try and find a way of doing the job in either two or three
2272 We start by looking for the largest block of zeros that are aligned on
2273 a 2-bit boundary, we then fill up the temps, wrapping around to the
2274 top of the word when we drop off the bottom.
2275 In the worst case this code should produce no more than four insns. */
2278 int best_consecutive_zeros
= 0;
2280 for (i
= 0; i
< 32; i
+= 2)
2282 int consecutive_zeros
= 0;
2284 if (!(remainder
& (3 << i
)))
2286 while ((i
< 32) && !(remainder
& (3 << i
)))
2288 consecutive_zeros
+= 2;
2291 if (consecutive_zeros
> best_consecutive_zeros
)
2293 best_consecutive_zeros
= consecutive_zeros
;
2294 best_start
= i
- consecutive_zeros
;
2300 /* So long as it won't require any more insns to do so, it's
2301 desirable to emit a small constant (in bits 0...9) in the last
2302 insn. This way there is more chance that it can be combined with
2303 a later addressing insn to form a pre-indexed load or store
2304 operation. Consider:
2306 *((volatile int *)0xe0000100) = 1;
2307 *((volatile int *)0xe0000110) = 2;
2309 We want this to wind up as:
2313 str rB, [rA, #0x100]
2315 str rB, [rA, #0x110]
2317 rather than having to synthesize both large constants from scratch.
2319 Therefore, we calculate how many insns would be required to emit
2320 the constant starting from `best_start', and also starting from
2321 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2322 yield a shorter sequence, we may as well use zero. */
2324 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2325 && (count_insns_for_constant (remainder
, 0) <=
2326 count_insns_for_constant (remainder
, best_start
)))
2329 /* Now start emitting the insns. */
2337 if (remainder
& (3 << (i
- 2)))
2342 temp1
= remainder
& ((0x0ff << end
)
2343 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2344 remainder
&= ~temp1
;
2348 rtx new_src
, temp1_rtx
;
2350 if (code
== SET
|| code
== MINUS
)
2352 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2353 if (can_invert
&& code
!= MINUS
)
2358 if (remainder
&& subtargets
)
2359 new_src
= gen_reg_rtx (mode
);
2364 else if (can_negate
)
2368 temp1
= trunc_int_for_mode (temp1
, mode
);
2369 temp1_rtx
= GEN_INT (temp1
);
2373 else if (code
== MINUS
)
2374 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2376 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2378 emit_constant_insn (cond
,
2379 gen_rtx_SET (VOIDmode
, new_src
,
2389 else if (code
== MINUS
)
2403 /* Canonicalize a comparison so that we are more likely to recognize it.
2404 This can be done for a few constant compares, where we can make the
2405 immediate value easier to load. */
2408 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2411 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2412 unsigned HOST_WIDE_INT maxval
;
2413 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2424 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2426 *op1
= GEN_INT (i
+ 1);
2427 return code
== GT
? GE
: LT
;
2434 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2436 *op1
= GEN_INT (i
- 1);
2437 return code
== GE
? GT
: LE
;
2443 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2444 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2446 *op1
= GEN_INT (i
+ 1);
2447 return code
== GTU
? GEU
: LTU
;
2454 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2456 *op1
= GEN_INT (i
- 1);
2457 return code
== GEU
? GTU
: LEU
;
2469 /* Define how to find the value returned by a function. */
2472 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2474 enum machine_mode mode
;
2475 int unsignedp ATTRIBUTE_UNUSED
;
2476 rtx r ATTRIBUTE_UNUSED
;
2478 mode
= TYPE_MODE (type
);
2479 /* Promote integer types. */
2480 if (INTEGRAL_TYPE_P (type
))
2481 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2483 /* Promotes small structs returned in a register to full-word size
2484 for big-endian AAPCS. */
2485 if (arm_return_in_msb (type
))
2487 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2488 if (size
% UNITS_PER_WORD
!= 0)
2490 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2491 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2495 return LIBCALL_VALUE(mode
);
2498 /* Determine the amount of memory needed to store the possible return
2499 registers of an untyped call. */
2501 arm_apply_result_size (void)
2507 if (TARGET_HARD_FLOAT_ABI
)
2511 if (TARGET_MAVERICK
)
2514 if (TARGET_IWMMXT_ABI
)
2521 /* Decide whether a type should be returned in memory (true)
2522 or in a register (false). This is called by the macro
2523 RETURN_IN_MEMORY. */
2525 arm_return_in_memory (tree type
)
2529 if (!AGGREGATE_TYPE_P (type
) &&
2530 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2531 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2532 /* All simple types are returned in registers.
2533 For AAPCS, complex types are treated the same as aggregates. */
2536 size
= int_size_in_bytes (type
);
2538 if (arm_abi
!= ARM_ABI_APCS
)
2540 /* ATPCS and later return aggregate types in memory only if they are
2541 larger than a word (or are variable size). */
2542 return (size
< 0 || size
> UNITS_PER_WORD
);
2545 /* To maximize backwards compatibility with previous versions of gcc,
2546 return vectors up to 4 words in registers. */
2547 if (TREE_CODE (type
) == VECTOR_TYPE
)
2548 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2550 /* For the arm-wince targets we choose to be compatible with Microsoft's
2551 ARM and Thumb compilers, which always return aggregates in memory. */
2553 /* All structures/unions bigger than one word are returned in memory.
2554 Also catch the case where int_size_in_bytes returns -1. In this case
2555 the aggregate is either huge or of variable size, and in either case
2556 we will want to return it via memory and not in a register. */
2557 if (size
< 0 || size
> UNITS_PER_WORD
)
2560 if (TREE_CODE (type
) == RECORD_TYPE
)
2564 /* For a struct the APCS says that we only return in a register
2565 if the type is 'integer like' and every addressable element
2566 has an offset of zero. For practical purposes this means
2567 that the structure can have at most one non bit-field element
2568 and that this element must be the first one in the structure. */
2570 /* Find the first field, ignoring non FIELD_DECL things which will
2571 have been created by C++. */
2572 for (field
= TYPE_FIELDS (type
);
2573 field
&& TREE_CODE (field
) != FIELD_DECL
;
2574 field
= TREE_CHAIN (field
))
2578 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2580 /* Check that the first field is valid for returning in a register. */
2582 /* ... Floats are not allowed */
2583 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2586 /* ... Aggregates that are not themselves valid for returning in
2587 a register are not allowed. */
2588 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2591 /* Now check the remaining fields, if any. Only bitfields are allowed,
2592 since they are not addressable. */
2593 for (field
= TREE_CHAIN (field
);
2595 field
= TREE_CHAIN (field
))
2597 if (TREE_CODE (field
) != FIELD_DECL
)
2600 if (!DECL_BIT_FIELD_TYPE (field
))
2607 if (TREE_CODE (type
) == UNION_TYPE
)
2611 /* Unions can be returned in registers if every element is
2612 integral, or can be returned in an integer register. */
2613 for (field
= TYPE_FIELDS (type
);
2615 field
= TREE_CHAIN (field
))
2617 if (TREE_CODE (field
) != FIELD_DECL
)
2620 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2623 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2629 #endif /* not ARM_WINCE */
2631 /* Return all other types in memory. */
2635 /* Indicate whether or not words of a double are in big-endian order. */
2638 arm_float_words_big_endian (void)
2640 if (TARGET_MAVERICK
)
2643 /* For FPA, float words are always big-endian. For VFP, floats words
2644 follow the memory system mode. */
2652 return (TARGET_BIG_END
? 1 : 0);
2657 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2658 for a call to a function whose data type is FNTYPE.
2659 For a library call, FNTYPE is NULL. */
2661 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2662 rtx libname ATTRIBUTE_UNUSED
,
2663 tree fndecl ATTRIBUTE_UNUSED
)
2665 /* On the ARM, the offset starts at 0. */
2666 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2667 pcum
->iwmmxt_nregs
= 0;
2668 pcum
->can_split
= true;
2670 pcum
->call_cookie
= CALL_NORMAL
;
2672 if (TARGET_LONG_CALLS
)
2673 pcum
->call_cookie
= CALL_LONG
;
2675 /* Check for long call/short call attributes. The attributes
2676 override any command line option. */
2679 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2680 pcum
->call_cookie
= CALL_SHORT
;
2681 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2682 pcum
->call_cookie
= CALL_LONG
;
2685 /* Varargs vectors are treated the same as long long.
2686 named_count avoids having to change the way arm handles 'named' */
2687 pcum
->named_count
= 0;
2690 if (TARGET_REALLY_IWMMXT
&& fntype
)
2694 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2696 fn_arg
= TREE_CHAIN (fn_arg
))
2697 pcum
->named_count
+= 1;
2699 if (! pcum
->named_count
)
2700 pcum
->named_count
= INT_MAX
;
2705 /* Return true if mode/type need doubleword alignment. */
2707 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2709 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2710 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2714 /* Determine where to put an argument to a function.
2715 Value is zero to push the argument on the stack,
2716 or a hard register in which to store the argument.
2718 MODE is the argument's machine mode.
2719 TYPE is the data type of the argument (as a tree).
2720 This is null for libcalls where that information may
2722 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2723 the preceding args and about the function being called.
2724 NAMED is nonzero if this argument is a named parameter
2725 (otherwise it is an extra parameter matching an ellipsis). */
2728 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2729 tree type
, int named
)
2733 /* Varargs vectors are treated the same as long long.
2734 named_count avoids having to change the way arm handles 'named' */
2735 if (TARGET_IWMMXT_ABI
2736 && arm_vector_mode_supported_p (mode
)
2737 && pcum
->named_count
> pcum
->nargs
+ 1)
2739 if (pcum
->iwmmxt_nregs
<= 9)
2740 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2743 pcum
->can_split
= false;
2748 /* Put doubleword aligned quantities in even register pairs. */
2750 && ARM_DOUBLEWORD_ALIGN
2751 && arm_needs_doubleword_align (mode
, type
))
2754 if (mode
== VOIDmode
)
2755 /* Compute operand 2 of the call insn. */
2756 return GEN_INT (pcum
->call_cookie
);
2758 /* Only allow splitting an arg between regs and memory if all preceding
2759 args were allocated to regs. For args passed by reference we only count
2760 the reference pointer. */
2761 if (pcum
->can_split
)
2764 nregs
= ARM_NUM_REGS2 (mode
, type
);
2766 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2769 return gen_rtx_REG (mode
, pcum
->nregs
);
2773 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2774 tree type
, bool named ATTRIBUTE_UNUSED
)
2776 int nregs
= pcum
->nregs
;
2778 if (arm_vector_mode_supported_p (mode
))
2781 if (NUM_ARG_REGS
> nregs
2782 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2784 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2789 /* Variable sized types are passed by reference. This is a GCC
2790 extension to the ARM ABI. */
2793 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2794 enum machine_mode mode ATTRIBUTE_UNUSED
,
2795 tree type
, bool named ATTRIBUTE_UNUSED
)
2797 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2800 /* Encode the current state of the #pragma [no_]long_calls. */
2803 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2804 LONG
, /* #pragma long_calls is in effect. */
2805 SHORT
/* #pragma no_long_calls is in effect. */
2808 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2811 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2813 arm_pragma_long_calls
= LONG
;
2817 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2819 arm_pragma_long_calls
= SHORT
;
2823 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2825 arm_pragma_long_calls
= OFF
;
2828 /* Table of machine attributes. */
2829 const struct attribute_spec arm_attribute_table
[] =
2831 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2832 /* Function calls made to this symbol must be done indirectly, because
2833 it may lie outside of the 26 bit addressing range of a normal function
2835 { "long_call", 0, 0, false, true, true, NULL
},
2836 /* Whereas these functions are always known to reside within the 26 bit
2837 addressing range. */
2838 { "short_call", 0, 0, false, true, true, NULL
},
2839 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2840 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2841 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2842 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2844 /* ARM/PE has three new attributes:
2846 dllexport - for exporting a function/variable that will live in a dll
2847 dllimport - for importing a function/variable from a dll
2849 Microsoft allows multiple declspecs in one __declspec, separating
2850 them with spaces. We do NOT support this. Instead, use __declspec
2853 { "dllimport", 0, 0, true, false, false, NULL
},
2854 { "dllexport", 0, 0, true, false, false, NULL
},
2855 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2856 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2857 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2858 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2859 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2861 { NULL
, 0, 0, false, false, false, NULL
}
2864 /* Handle an attribute requiring a FUNCTION_DECL;
2865 arguments as in struct attribute_spec.handler. */
2867 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2868 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2870 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2872 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2873 IDENTIFIER_POINTER (name
));
2874 *no_add_attrs
= true;
2880 /* Handle an "interrupt" or "isr" attribute;
2881 arguments as in struct attribute_spec.handler. */
2883 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2888 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2890 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2891 IDENTIFIER_POINTER (name
));
2892 *no_add_attrs
= true;
2894 /* FIXME: the argument if any is checked for type attributes;
2895 should it be checked for decl ones? */
2899 if (TREE_CODE (*node
) == FUNCTION_TYPE
2900 || TREE_CODE (*node
) == METHOD_TYPE
)
2902 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2904 warning (OPT_Wattributes
, "%qs attribute ignored",
2905 IDENTIFIER_POINTER (name
));
2906 *no_add_attrs
= true;
2909 else if (TREE_CODE (*node
) == POINTER_TYPE
2910 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2911 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2912 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2914 *node
= build_variant_type_copy (*node
);
2915 TREE_TYPE (*node
) = build_type_attribute_variant
2917 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2918 *no_add_attrs
= true;
2922 /* Possibly pass this attribute on from the type to a decl. */
2923 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2924 | (int) ATTR_FLAG_FUNCTION_NEXT
2925 | (int) ATTR_FLAG_ARRAY_NEXT
))
2927 *no_add_attrs
= true;
2928 return tree_cons (name
, args
, NULL_TREE
);
2932 warning (OPT_Wattributes
, "%qs attribute ignored",
2933 IDENTIFIER_POINTER (name
));
2941 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2942 /* Handle the "notshared" attribute. This attribute is another way of
2943 requesting hidden visibility. ARM's compiler supports
2944 "__declspec(notshared)"; we support the same thing via an
2948 arm_handle_notshared_attribute (tree
*node
,
2949 tree name ATTRIBUTE_UNUSED
,
2950 tree args ATTRIBUTE_UNUSED
,
2951 int flags ATTRIBUTE_UNUSED
,
2954 tree decl
= TYPE_NAME (*node
);
2958 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2959 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2960 *no_add_attrs
= false;
2966 /* Return 0 if the attributes for two types are incompatible, 1 if they
2967 are compatible, and 2 if they are nearly compatible (which causes a
2968 warning to be generated). */
2970 arm_comp_type_attributes (tree type1
, tree type2
)
2974 /* Check for mismatch of non-default calling convention. */
2975 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2978 /* Check for mismatched call attributes. */
2979 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2980 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2981 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2982 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2984 /* Only bother to check if an attribute is defined. */
2985 if (l1
| l2
| s1
| s2
)
2987 /* If one type has an attribute, the other must have the same attribute. */
2988 if ((l1
!= l2
) || (s1
!= s2
))
2991 /* Disallow mixed attributes. */
2992 if ((l1
& s2
) || (l2
& s1
))
2996 /* Check for mismatched ISR attribute. */
2997 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2999 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
3000 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
3002 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
3009 /* Encode long_call or short_call attribute by prefixing
3010 symbol name in DECL with a special character FLAG. */
3012 arm_encode_call_attribute (tree decl
, int flag
)
3014 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
3015 int len
= strlen (str
);
3018 /* Do not allow weak functions to be treated as short call. */
3019 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3022 newstr
= alloca (len
+ 2);
3024 strcpy (newstr
+ 1, str
);
3026 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3027 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3030 /* Assigns default attributes to newly defined type. This is used to
3031 set short_call/long_call attributes for function types of
3032 functions defined inside corresponding #pragma scopes. */
3034 arm_set_default_type_attributes (tree type
)
3036 /* Add __attribute__ ((long_call)) to all functions, when
3037 inside #pragma long_calls or __attribute__ ((short_call)),
3038 when inside #pragma no_long_calls. */
3039 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3041 tree type_attr_list
, attr_name
;
3042 type_attr_list
= TYPE_ATTRIBUTES (type
);
3044 if (arm_pragma_long_calls
== LONG
)
3045 attr_name
= get_identifier ("long_call");
3046 else if (arm_pragma_long_calls
== SHORT
)
3047 attr_name
= get_identifier ("short_call");
3051 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3052 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3056 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3057 defined within the current compilation unit. If this cannot be
3058 determined, then 0 is returned. */
3060 current_file_function_operand (rtx sym_ref
)
3062 /* This is a bit of a fib. A function will have a short call flag
3063 applied to its name if it has the short call attribute, or it has
3064 already been defined within the current compilation unit. */
3065 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3068 /* The current function is always defined within the current compilation
3069 unit. If it s a weak definition however, then this may not be the real
3070 definition of the function, and so we have to say no. */
3071 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3072 && !DECL_WEAK (current_function_decl
))
3075 /* We cannot make the determination - default to returning 0. */
3079 /* Return nonzero if a 32 bit "long_call" should be generated for
3080 this call. We generate a long_call if the function:
3082 a. has an __attribute__((long call))
3083 or b. is within the scope of a #pragma long_calls
3084 or c. the -mlong-calls command line switch has been specified
3086 1. -ffunction-sections is in effect
3087 or 2. the current function has __attribute__ ((section))
3088 or 3. the target function has __attribute__ ((section))
3090 However we do not generate a long call if the function:
3092 d. has an __attribute__ ((short_call))
3093 or e. is inside the scope of a #pragma no_long_calls
3094 or f. is defined within the current compilation unit.
3096 This function will be called by C fragments contained in the machine
3097 description file. SYM_REF and CALL_COOKIE correspond to the matched
3098 rtl operands. CALL_SYMBOL is used to distinguish between
3099 two different callers of the function. It is set to 1 in the
3100 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3101 and "call_value" patterns. This is because of the difference in the
3102 SYM_REFs passed by these patterns. */
3104 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3108 if (GET_CODE (sym_ref
) != MEM
)
3111 sym_ref
= XEXP (sym_ref
, 0);
3114 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3117 if (call_cookie
& CALL_SHORT
)
3120 if (TARGET_LONG_CALLS
)
3122 if (flag_function_sections
3123 || DECL_SECTION_NAME (current_function_decl
))
3124 /* c.3 is handled by the definition of the
3125 ARM_DECLARE_FUNCTION_SIZE macro. */
3129 if (current_file_function_operand (sym_ref
))
3132 return (call_cookie
& CALL_LONG
)
3133 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3134 || TARGET_LONG_CALLS
;
3137 /* Return nonzero if it is ok to make a tail-call to DECL. */
3139 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3141 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3143 if (cfun
->machine
->sibcall_blocked
)
3146 /* Never tailcall something for which we have no decl, or if we
3147 are in Thumb mode. */
3148 if (decl
== NULL
|| TARGET_THUMB
)
3151 /* Get the calling method. */
3152 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3153 call_type
= CALL_SHORT
;
3154 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3155 call_type
= CALL_LONG
;
3157 /* Cannot tail-call to long calls, since these are out of range of
3158 a branch instruction. However, if not compiling PIC, we know
3159 we can reach the symbol if it is in this compilation unit. */
3160 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3163 /* If we are interworking and the function is not declared static
3164 then we can't tail-call it unless we know that it exists in this
3165 compilation unit (since it might be a Thumb routine). */
3166 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3169 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3170 if (IS_INTERRUPT (arm_current_func_type ()))
3173 /* Everything else is ok. */
3178 /* Addressing mode support functions. */
3180 /* Return nonzero if X is a legitimate immediate operand when compiling
3181 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3183 legitimate_pic_operand_p (rtx x
)
3185 if (GET_CODE (x
) == SYMBOL_REF
3186 || (GET_CODE (x
) == CONST
3187 && GET_CODE (XEXP (x
, 0)) == PLUS
3188 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3195 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3197 if (GET_CODE (orig
) == SYMBOL_REF
3198 || GET_CODE (orig
) == LABEL_REF
)
3200 #ifndef AOF_ASSEMBLER
3201 rtx pic_ref
, address
;
3206 /* If this function doesn't have a pic register, create one now.
3207 A lot of the logic here is made obscure by the fact that this
3208 routine gets called as part of the rtx cost estimation
3209 process. We don't want those calls to affect any assumptions
3210 about the real function; and further, we can't call
3211 entry_of_function() until we start the real expansion
3213 if (!current_function_uses_pic_offset_table
)
3215 gcc_assert (!no_new_pseudos
);
3216 if (arm_pic_register
!= INVALID_REGNUM
)
3218 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
3220 /* Play games to avoid marking the function as needing pic
3221 if we are being called as part of the cost-estimation
3224 current_function_uses_pic_offset_table
= 1;
3230 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
3232 /* Play games to avoid marking the function as needing pic
3233 if we are being called as part of the cost-estimation
3237 current_function_uses_pic_offset_table
= 1;
3240 arm_load_pic_register (0UL);
3244 emit_insn_after (seq
, entry_of_function ());
3251 gcc_assert (!no_new_pseudos
);
3252 reg
= gen_reg_rtx (Pmode
);
3257 #ifdef AOF_ASSEMBLER
3258 /* The AOF assembler can generate relocations for these directly, and
3259 understands that the PIC register has to be added into the offset. */
3260 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3263 address
= gen_reg_rtx (Pmode
);
3268 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3270 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3272 if ((GET_CODE (orig
) == LABEL_REF
3273 || (GET_CODE (orig
) == SYMBOL_REF
&&
3274 SYMBOL_REF_LOCAL_P (orig
)))
3276 pic_ref
= gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
, address
);
3279 pic_ref
= gen_const_mem (Pmode
,
3280 gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
,
3284 insn
= emit_move_insn (reg
, pic_ref
);
3286 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3288 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3292 else if (GET_CODE (orig
) == CONST
)
3296 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3297 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
3300 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3301 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3306 gcc_assert (!no_new_pseudos
);
3307 reg
= gen_reg_rtx (Pmode
);
3310 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3312 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3313 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3314 base
== reg
? 0 : reg
);
3316 if (GET_CODE (offset
) == CONST_INT
)
3318 /* The base register doesn't really matter, we only want to
3319 test the index for the appropriate mode. */
3320 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3322 gcc_assert (!no_new_pseudos
);
3323 offset
= force_reg (Pmode
, offset
);
3326 if (GET_CODE (offset
) == CONST_INT
)
3327 return plus_constant (base
, INTVAL (offset
));
3330 if (GET_MODE_SIZE (mode
) > 4
3331 && (GET_MODE_CLASS (mode
) == MODE_INT
3332 || TARGET_SOFT_FLOAT
))
3334 emit_insn (gen_addsi3 (reg
, base
, offset
));
3338 return gen_rtx_PLUS (Pmode
, base
, offset
);
3345 /* Find a spare low register to use during the prolog of a function. */
3348 thumb_find_work_register (unsigned long pushed_regs_mask
)
3352 /* Check the argument registers first as these are call-used. The
3353 register allocation order means that sometimes r3 might be used
3354 but earlier argument registers might not, so check them all. */
3355 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3356 if (!regs_ever_live
[reg
])
3359 /* Before going on to check the call-saved registers we can try a couple
3360 more ways of deducing that r3 is available. The first is when we are
3361 pushing anonymous arguments onto the stack and we have less than 4
3362 registers worth of fixed arguments(*). In this case r3 will be part of
3363 the variable argument list and so we can be sure that it will be
3364 pushed right at the start of the function. Hence it will be available
3365 for the rest of the prologue.
3366 (*): ie current_function_pretend_args_size is greater than 0. */
3367 if (cfun
->machine
->uses_anonymous_args
3368 && current_function_pretend_args_size
> 0)
3369 return LAST_ARG_REGNUM
;
3371 /* The other case is when we have fixed arguments but less than 4 registers
3372 worth. In this case r3 might be used in the body of the function, but
3373 it is not being used to convey an argument into the function. In theory
3374 we could just check current_function_args_size to see how many bytes are
3375 being passed in argument registers, but it seems that it is unreliable.
3376 Sometimes it will have the value 0 when in fact arguments are being
3377 passed. (See testcase execute/20021111-1.c for an example). So we also
3378 check the args_info.nregs field as well. The problem with this field is
3379 that it makes no allowances for arguments that are passed to the
3380 function but which are not used. Hence we could miss an opportunity
3381 when a function has an unused argument in r3. But it is better to be
3382 safe than to be sorry. */
3383 if (! cfun
->machine
->uses_anonymous_args
3384 && current_function_args_size
>= 0
3385 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3386 && cfun
->args_info
.nregs
< 4)
3387 return LAST_ARG_REGNUM
;
3389 /* Otherwise look for a call-saved register that is going to be pushed. */
3390 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3391 if (pushed_regs_mask
& (1 << reg
))
3394 /* Something went wrong - thumb_compute_save_reg_mask()
3395 should have arranged for a suitable register to be pushed. */
3399 static GTY(()) int pic_labelno
;
3401 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3405 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3407 #ifndef AOF_ASSEMBLER
3408 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3409 rtx global_offset_table
;
3411 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3414 gcc_assert (flag_pic
);
3416 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3417 in the code stream. */
3419 labelno
= GEN_INT (pic_labelno
++);
3420 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3421 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3423 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3424 /* On the ARM the PC register contains 'dot + 8' at the time of the
3425 addition, on the Thumb it is 'dot + 4'. */
3426 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3428 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3429 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3431 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3433 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3437 emit_insn (gen_pic_load_addr_arm (cfun
->machine
->pic_reg
, pic_rtx
));
3438 emit_insn (gen_pic_add_dot_plus_eight (cfun
->machine
->pic_reg
,
3439 cfun
->machine
->pic_reg
, labelno
));
3443 if (arm_pic_register
!= INVALID_REGNUM
3444 && REGNO (cfun
->machine
->pic_reg
) > LAST_LO_REGNUM
)
3446 /* We will have pushed the pic register, so we should always be
3447 able to find a work register. */
3448 pic_tmp
= gen_rtx_REG (SImode
,
3449 thumb_find_work_register (saved_regs
));
3450 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3451 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3454 emit_insn (gen_pic_load_addr_thumb (cfun
->machine
->pic_reg
, pic_rtx
));
3455 emit_insn (gen_pic_add_dot_plus_four (cfun
->machine
->pic_reg
,
3456 cfun
->machine
->pic_reg
, labelno
));
3459 /* Need to emit this whether or not we obey regdecls,
3460 since setjmp/longjmp can cause life info to screw up. */
3461 emit_insn (gen_rtx_USE (VOIDmode
, cfun
->machine
->pic_reg
));
3462 #endif /* AOF_ASSEMBLER */
3466 /* Return nonzero if X is valid as an ARM state addressing register. */
3468 arm_address_register_rtx_p (rtx x
, int strict_p
)
3472 if (GET_CODE (x
) != REG
)
3478 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3480 return (regno
<= LAST_ARM_REGNUM
3481 || regno
>= FIRST_PSEUDO_REGISTER
3482 || regno
== FRAME_POINTER_REGNUM
3483 || regno
== ARG_POINTER_REGNUM
);
3486 /* Return TRUE if this rtx is the difference of a symbol and a label,
3487 and will reduce to a PC-relative relocation in the object file.
3488 Expressions like this can be left alone when generating PIC, rather
3489 than forced through the GOT. */
3491 pcrel_constant_p (rtx x
)
3493 if (GET_CODE (x
) == MINUS
)
3494 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3499 /* Return nonzero if X is a valid ARM state address operand. */
3501 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3505 enum rtx_code code
= GET_CODE (x
);
3507 if (arm_address_register_rtx_p (x
, strict_p
))
3510 use_ldrd
= (TARGET_LDRD
3512 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3514 if (code
== POST_INC
|| code
== PRE_DEC
3515 || ((code
== PRE_INC
|| code
== POST_DEC
)
3516 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3517 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3519 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3520 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3521 && GET_CODE (XEXP (x
, 1)) == PLUS
3522 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3524 rtx addend
= XEXP (XEXP (x
, 1), 1);
3526 /* Don't allow ldrd post increment by register because it's hard
3527 to fixup invalid register choices. */
3529 && GET_CODE (x
) == POST_MODIFY
3530 && GET_CODE (addend
) == REG
)
3533 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3534 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3537 /* After reload constants split into minipools will have addresses
3538 from a LABEL_REF. */
3539 else if (reload_completed
3540 && (code
== LABEL_REF
3542 && GET_CODE (XEXP (x
, 0)) == PLUS
3543 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3544 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3547 else if (mode
== TImode
)
3550 else if (code
== PLUS
)
3552 rtx xop0
= XEXP (x
, 0);
3553 rtx xop1
= XEXP (x
, 1);
3555 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3556 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3557 || (arm_address_register_rtx_p (xop1
, strict_p
)
3558 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3562 /* Reload currently can't handle MINUS, so disable this for now */
3563 else if (GET_CODE (x
) == MINUS
)
3565 rtx xop0
= XEXP (x
, 0);
3566 rtx xop1
= XEXP (x
, 1);
3568 return (arm_address_register_rtx_p (xop0
, strict_p
)
3569 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3573 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3574 && code
== SYMBOL_REF
3575 && CONSTANT_POOL_ADDRESS_P (x
)
3577 && symbol_mentioned_p (get_pool_constant (x
))
3578 && ! pcrel_constant_p (get_pool_constant (x
))))
3584 /* Return nonzero if INDEX is valid for an address index operand in
3587 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3590 HOST_WIDE_INT range
;
3591 enum rtx_code code
= GET_CODE (index
);
3593 /* Standard coprocessor addressing modes. */
3594 if (TARGET_HARD_FLOAT
3595 && (TARGET_FPA
|| TARGET_MAVERICK
)
3596 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3597 || (TARGET_MAVERICK
&& mode
== DImode
)))
3598 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3599 && INTVAL (index
) > -1024
3600 && (INTVAL (index
) & 3) == 0);
3602 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3603 return (code
== CONST_INT
3604 && INTVAL (index
) < 1024
3605 && INTVAL (index
) > -1024
3606 && (INTVAL (index
) & 3) == 0);
3608 if (arm_address_register_rtx_p (index
, strict_p
)
3609 && (GET_MODE_SIZE (mode
) <= 4))
3612 if (mode
== DImode
|| mode
== DFmode
)
3614 if (code
== CONST_INT
)
3616 HOST_WIDE_INT val
= INTVAL (index
);
3619 return val
> -256 && val
< 256;
3621 return val
> -4096 && val
< 4092;
3624 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3627 if (GET_MODE_SIZE (mode
) <= 4
3630 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3634 rtx xiop0
= XEXP (index
, 0);
3635 rtx xiop1
= XEXP (index
, 1);
3637 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3638 && power_of_two_operand (xiop1
, SImode
))
3639 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3640 && power_of_two_operand (xiop0
, SImode
)));
3642 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3643 || code
== ASHIFT
|| code
== ROTATERT
)
3645 rtx op
= XEXP (index
, 1);
3647 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3648 && GET_CODE (op
) == CONST_INT
3650 && INTVAL (op
) <= 31);
3654 /* For ARM v4 we may be doing a sign-extend operation during the
3658 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3664 range
= (mode
== HImode
) ? 4095 : 4096;
3666 return (code
== CONST_INT
3667 && INTVAL (index
) < range
3668 && INTVAL (index
) > -range
);
3671 /* Return nonzero if X is valid as a Thumb state base register. */
3673 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3677 if (GET_CODE (x
) != REG
)
3683 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3685 return (regno
<= LAST_LO_REGNUM
3686 || regno
> LAST_VIRTUAL_REGISTER
3687 || regno
== FRAME_POINTER_REGNUM
3688 || (GET_MODE_SIZE (mode
) >= 4
3689 && (regno
== STACK_POINTER_REGNUM
3690 || regno
>= FIRST_PSEUDO_REGISTER
3691 || x
== hard_frame_pointer_rtx
3692 || x
== arg_pointer_rtx
)));
3695 /* Return nonzero if x is a legitimate index register. This is the case
3696 for any base register that can access a QImode object. */
3698 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3700 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3703 /* Return nonzero if x is a legitimate Thumb-state address.
3705 The AP may be eliminated to either the SP or the FP, so we use the
3706 least common denominator, e.g. SImode, and offsets from 0 to 64.
3708 ??? Verify whether the above is the right approach.
3710 ??? Also, the FP may be eliminated to the SP, so perhaps that
3711 needs special handling also.
3713 ??? Look at how the mips16 port solves this problem. It probably uses
3714 better ways to solve some of these problems.
3716 Although it is not incorrect, we don't accept QImode and HImode
3717 addresses based on the frame pointer or arg pointer until the
3718 reload pass starts. This is so that eliminating such addresses
3719 into stack based ones won't produce impossible code. */
3721 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3723 /* ??? Not clear if this is right. Experiment. */
3724 if (GET_MODE_SIZE (mode
) < 4
3725 && !(reload_in_progress
|| reload_completed
)
3726 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3727 || reg_mentioned_p (arg_pointer_rtx
, x
)
3728 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3729 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3730 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3731 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3734 /* Accept any base register. SP only in SImode or larger. */
3735 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3738 /* This is PC relative data before arm_reorg runs. */
3739 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3740 && GET_CODE (x
) == SYMBOL_REF
3741 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
3744 /* This is PC relative data after arm_reorg runs. */
3745 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3746 && (GET_CODE (x
) == LABEL_REF
3747 || (GET_CODE (x
) == CONST
3748 && GET_CODE (XEXP (x
, 0)) == PLUS
3749 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3750 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3753 /* Post-inc indexing only supported for SImode and larger. */
3754 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3755 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3758 else if (GET_CODE (x
) == PLUS
)
3760 /* REG+REG address can be any two index registers. */
3761 /* We disallow FRAME+REG addressing since we know that FRAME
3762 will be replaced with STACK, and SP relative addressing only
3763 permits SP+OFFSET. */
3764 if (GET_MODE_SIZE (mode
) <= 4
3765 && XEXP (x
, 0) != frame_pointer_rtx
3766 && XEXP (x
, 1) != frame_pointer_rtx
3767 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3768 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3771 /* REG+const has 5-7 bit offset for non-SP registers. */
3772 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3773 || XEXP (x
, 0) == arg_pointer_rtx
)
3774 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3775 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3778 /* REG+const has 10 bit offset for SP, but only SImode and
3779 larger is supported. */
3780 /* ??? Should probably check for DI/DFmode overflow here
3781 just like GO_IF_LEGITIMATE_OFFSET does. */
3782 else if (GET_CODE (XEXP (x
, 0)) == REG
3783 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3784 && GET_MODE_SIZE (mode
) >= 4
3785 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3786 && INTVAL (XEXP (x
, 1)) >= 0
3787 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3788 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3791 else if (GET_CODE (XEXP (x
, 0)) == REG
3792 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3793 && GET_MODE_SIZE (mode
) >= 4
3794 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3795 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3799 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3800 && GET_MODE_SIZE (mode
) == 4
3801 && GET_CODE (x
) == SYMBOL_REF
3802 && CONSTANT_POOL_ADDRESS_P (x
)
3804 && symbol_mentioned_p (get_pool_constant (x
))
3805 && ! pcrel_constant_p (get_pool_constant (x
))))
3811 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3812 instruction of mode MODE. */
3814 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3816 switch (GET_MODE_SIZE (mode
))
3819 return val
>= 0 && val
< 32;
3822 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3826 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3831 /* Build the SYMBOL_REF for __tls_get_addr. */
3833 static GTY(()) rtx tls_get_addr_libfunc
;
3836 get_tls_get_addr (void)
3838 if (!tls_get_addr_libfunc
)
3839 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3840 return tls_get_addr_libfunc
;
3844 arm_load_tp (rtx target
)
3847 target
= gen_reg_rtx (SImode
);
3851 /* Can return in any reg. */
3852 emit_insn (gen_load_tp_hard (target
));
3856 /* Always returned in r0. Immediately copy the result into a pseudo,
3857 otherwise other uses of r0 (e.g. setting up function arguments) may
3858 clobber the value. */
3862 emit_insn (gen_load_tp_soft ());
3864 tmp
= gen_rtx_REG (SImode
, 0);
3865 emit_move_insn (target
, tmp
);
3871 load_tls_operand (rtx x
, rtx reg
)
3875 if (reg
== NULL_RTX
)
3876 reg
= gen_reg_rtx (SImode
);
3878 tmp
= gen_rtx_CONST (SImode
, x
);
3880 emit_move_insn (reg
, tmp
);
3886 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3888 rtx insns
, label
, labelno
, sum
;
3892 labelno
= GEN_INT (pic_labelno
++);
3893 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3894 label
= gen_rtx_CONST (VOIDmode
, label
);
3896 sum
= gen_rtx_UNSPEC (Pmode
,
3897 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
3898 GEN_INT (TARGET_ARM
? 8 : 4)),
3900 reg
= load_tls_operand (sum
, reg
);
3903 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
3905 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3907 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3908 Pmode
, 1, reg
, Pmode
);
3910 insns
= get_insns ();
3917 legitimize_tls_address (rtx x
, rtx reg
)
3919 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
3920 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3924 case TLS_MODEL_GLOBAL_DYNAMIC
:
3925 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3926 dest
= gen_reg_rtx (Pmode
);
3927 emit_libcall_block (insns
, dest
, ret
, x
);
3930 case TLS_MODEL_LOCAL_DYNAMIC
:
3931 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3933 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3934 share the LDM result with other LD model accesses. */
3935 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3937 dest
= gen_reg_rtx (Pmode
);
3938 emit_libcall_block (insns
, dest
, ret
, eqv
);
3940 /* Load the addend. */
3941 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3943 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3944 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3946 case TLS_MODEL_INITIAL_EXEC
:
3947 labelno
= GEN_INT (pic_labelno
++);
3948 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3949 label
= gen_rtx_CONST (VOIDmode
, label
);
3950 sum
= gen_rtx_UNSPEC (Pmode
,
3951 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
3952 GEN_INT (TARGET_ARM
? 8 : 4)),
3954 reg
= load_tls_operand (sum
, reg
);
3957 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
3960 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3961 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3964 tp
= arm_load_tp (NULL_RTX
);
3966 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3968 case TLS_MODEL_LOCAL_EXEC
:
3969 tp
= arm_load_tp (NULL_RTX
);
3971 reg
= gen_rtx_UNSPEC (Pmode
,
3972 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3974 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3976 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3983 /* Try machine-dependent ways of modifying an illegitimate address
3984 to be legitimate. If we find one, return the new, valid address. */
3986 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3988 if (arm_tls_symbol_p (x
))
3989 return legitimize_tls_address (x
, NULL_RTX
);
3991 if (GET_CODE (x
) == PLUS
)
3993 rtx xop0
= XEXP (x
, 0);
3994 rtx xop1
= XEXP (x
, 1);
3996 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3997 xop0
= force_reg (SImode
, xop0
);
3999 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
4000 xop1
= force_reg (SImode
, xop1
);
4002 if (ARM_BASE_REGISTER_RTX_P (xop0
)
4003 && GET_CODE (xop1
) == CONST_INT
)
4005 HOST_WIDE_INT n
, low_n
;
4009 /* VFP addressing modes actually allow greater offsets, but for
4010 now we just stick with the lowest common denominator. */
4012 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
4024 low_n
= ((mode
) == TImode
? 0
4025 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
4029 base_reg
= gen_reg_rtx (SImode
);
4030 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
4031 emit_move_insn (base_reg
, val
);
4032 x
= plus_constant (base_reg
, low_n
);
4034 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4035 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4038 /* XXX We don't allow MINUS any more -- see comment in
4039 arm_legitimate_address_p (). */
4040 else if (GET_CODE (x
) == MINUS
)
4042 rtx xop0
= XEXP (x
, 0);
4043 rtx xop1
= XEXP (x
, 1);
4045 if (CONSTANT_P (xop0
))
4046 xop0
= force_reg (SImode
, xop0
);
4048 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
4049 xop1
= force_reg (SImode
, xop1
);
4051 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4052 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4055 /* Make sure to take full advantage of the pre-indexed addressing mode
4056 with absolute addresses which often allows for the base register to
4057 be factorized for multiple adjacent memory references, and it might
4058 even allows for the mini pool to be avoided entirely. */
4059 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4062 HOST_WIDE_INT mask
, base
, index
;
4065 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4066 use a 8 bit index. So let's use a 12 bit index for SImode only and
4067 hope that arm_gen_constant will enable ldrb to use more bits. */
4068 bits
= (mode
== SImode
) ? 12 : 8;
4069 mask
= (1 << bits
) - 1;
4070 base
= INTVAL (x
) & ~mask
;
4071 index
= INTVAL (x
) & mask
;
4072 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4074 /* It'll most probably be more efficient to generate the base
4075 with more bits set and use a negative index instead. */
4079 base_reg
= force_reg (SImode
, GEN_INT (base
));
4080 x
= plus_constant (base_reg
, index
);
4085 /* We need to find and carefully transform any SYMBOL and LABEL
4086 references; so go back to the original address expression. */
4087 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4089 if (new_x
!= orig_x
)
4097 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4098 to be legitimate. If we find one, return the new, valid address. */
4100 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4102 if (arm_tls_symbol_p (x
))
4103 return legitimize_tls_address (x
, NULL_RTX
);
4105 if (GET_CODE (x
) == PLUS
4106 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4107 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4108 || INTVAL (XEXP (x
, 1)) < 0))
4110 rtx xop0
= XEXP (x
, 0);
4111 rtx xop1
= XEXP (x
, 1);
4112 HOST_WIDE_INT offset
= INTVAL (xop1
);
4114 /* Try and fold the offset into a biasing of the base register and
4115 then offsetting that. Don't do this when optimizing for space
4116 since it can cause too many CSEs. */
4117 if (optimize_size
&& offset
>= 0
4118 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4120 HOST_WIDE_INT delta
;
4123 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4124 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4125 delta
= 31 * GET_MODE_SIZE (mode
);
4127 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4129 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4131 x
= plus_constant (xop0
, delta
);
4133 else if (offset
< 0 && offset
> -256)
4134 /* Small negative offsets are best done with a subtract before the
4135 dereference, forcing these into a register normally takes two
4137 x
= force_operand (x
, NULL_RTX
);
4140 /* For the remaining cases, force the constant into a register. */
4141 xop1
= force_reg (SImode
, xop1
);
4142 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4145 else if (GET_CODE (x
) == PLUS
4146 && s_register_operand (XEXP (x
, 1), SImode
)
4147 && !s_register_operand (XEXP (x
, 0), SImode
))
4149 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4151 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4156 /* We need to find and carefully transform any SYMBOL and LABEL
4157 references; so go back to the original address expression. */
4158 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4160 if (new_x
!= orig_x
)
4168 thumb_legitimize_reload_address (rtx
*x_p
,
4169 enum machine_mode mode
,
4170 int opnum
, int type
,
4171 int ind_levels ATTRIBUTE_UNUSED
)
4175 if (GET_CODE (x
) == PLUS
4176 && GET_MODE_SIZE (mode
) < 4
4177 && REG_P (XEXP (x
, 0))
4178 && XEXP (x
, 0) == stack_pointer_rtx
4179 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4180 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4185 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4186 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4190 /* If both registers are hi-regs, then it's better to reload the
4191 entire expression rather than each register individually. That
4192 only requires one reload register rather than two. */
4193 if (GET_CODE (x
) == PLUS
4194 && REG_P (XEXP (x
, 0))
4195 && REG_P (XEXP (x
, 1))
4196 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4197 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4202 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4203 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4210 /* Test for various thread-local symbols. */
4212 /* Return TRUE if X is a thread-local symbol. */
4215 arm_tls_symbol_p (rtx x
)
4217 if (! TARGET_HAVE_TLS
)
4220 if (GET_CODE (x
) != SYMBOL_REF
)
4223 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4226 /* Helper for arm_tls_referenced_p. */
4229 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4231 if (GET_CODE (*x
) == SYMBOL_REF
)
4232 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4234 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4235 TLS offsets, not real symbol references. */
4236 if (GET_CODE (*x
) == UNSPEC
4237 && XINT (*x
, 1) == UNSPEC_TLS
)
4243 /* Return TRUE if X contains any TLS symbol references. */
4246 arm_tls_referenced_p (rtx x
)
4248 if (! TARGET_HAVE_TLS
)
4251 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4254 #define REG_OR_SUBREG_REG(X) \
4255 (GET_CODE (X) == REG \
4256 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4258 #define REG_OR_SUBREG_RTX(X) \
4259 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4261 #ifndef COSTS_N_INSNS
4262 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4265 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4267 enum machine_mode mode
= GET_MODE (x
);
4280 return COSTS_N_INSNS (1);
4283 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4286 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4293 return COSTS_N_INSNS (2) + cycles
;
4295 return COSTS_N_INSNS (1) + 16;
4298 return (COSTS_N_INSNS (1)
4299 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4300 + GET_CODE (SET_DEST (x
)) == MEM
));
4305 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4307 if (thumb_shiftable_const (INTVAL (x
)))
4308 return COSTS_N_INSNS (2);
4309 return COSTS_N_INSNS (3);
4311 else if ((outer
== PLUS
|| outer
== COMPARE
)
4312 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4314 else if (outer
== AND
4315 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4316 return COSTS_N_INSNS (1);
4317 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4318 || outer
== LSHIFTRT
)
4320 return COSTS_N_INSNS (2);
4326 return COSTS_N_INSNS (3);
4344 /* XXX another guess. */
4345 /* Memory costs quite a lot for the first word, but subsequent words
4346 load at the equivalent of a single insn each. */
4347 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4348 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4353 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4358 /* XXX still guessing. */
4359 switch (GET_MODE (XEXP (x
, 0)))
4362 return (1 + (mode
== DImode
? 4 : 0)
4363 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4366 return (4 + (mode
== DImode
? 4 : 0)
4367 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4370 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4382 /* Worker routine for arm_rtx_costs. */
4384 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4386 enum machine_mode mode
= GET_MODE (x
);
4387 enum rtx_code subcode
;
4393 /* Memory costs quite a lot for the first word, but subsequent words
4394 load at the equivalent of a single insn each. */
4395 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4396 + (GET_CODE (x
) == SYMBOL_REF
4397 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4403 return optimize_size
? COSTS_N_INSNS (2) : 100;
4406 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4413 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4415 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4416 + ((GET_CODE (XEXP (x
, 0)) == REG
4417 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4418 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4420 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4421 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4422 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4424 + ((GET_CODE (XEXP (x
, 1)) == REG
4425 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4426 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4427 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4432 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4433 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4434 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4435 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4438 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4439 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4440 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4441 && arm_const_double_rtx (XEXP (x
, 1))))
4443 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4444 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4445 && arm_const_double_rtx (XEXP (x
, 0))))
4448 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4449 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4450 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4451 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4452 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4453 || subcode
== ROTATE
|| subcode
== ROTATERT
4455 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4456 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4457 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4458 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4459 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4460 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4461 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4466 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4467 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4468 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4469 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4470 && arm_const_double_rtx (XEXP (x
, 1))))
4474 case AND
: case XOR
: case IOR
:
4477 /* Normally the frame registers will be spilt into reg+const during
4478 reload, so it is a bad idea to combine them with other instructions,
4479 since then they might not be moved outside of loops. As a compromise
4480 we allow integration with ops that have a constant as their second
4482 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4483 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4484 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4485 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4486 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4490 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4491 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4492 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4493 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4496 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4497 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4498 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4499 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4500 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4503 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4504 return (1 + extra_cost
4505 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4506 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4507 || subcode
== ROTATE
|| subcode
== ROTATERT
4509 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4510 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4511 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4512 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4513 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4514 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4520 /* This should have been handled by the CPU specific routines. */
4524 if (arm_arch3m
&& mode
== SImode
4525 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4526 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4527 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4528 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4529 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4530 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4535 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4536 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4540 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4542 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4545 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4553 return 4 + (mode
== DImode
? 4 : 0);
4556 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4557 return (4 + (mode
== DImode
? 4 : 0)
4558 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4561 switch (GET_MODE (XEXP (x
, 0)))
4564 return (1 + (mode
== DImode
? 4 : 0)
4565 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4568 return (4 + (mode
== DImode
? 4 : 0)
4569 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4572 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4587 if (const_ok_for_arm (INTVAL (x
)))
4588 return outer
== SET
? 2 : -1;
4589 else if (outer
== AND
4590 && const_ok_for_arm (~INTVAL (x
)))
4592 else if ((outer
== COMPARE
4593 || outer
== PLUS
|| outer
== MINUS
)
4594 && const_ok_for_arm (-INTVAL (x
)))
4605 if (arm_const_double_rtx (x
))
4606 return outer
== SET
? 2 : -1;
4607 else if ((outer
== COMPARE
|| outer
== PLUS
)
4608 && neg_const_double_rtx_ok_for_fpa (x
))
4617 /* RTX costs when optimizing for size. */
4619 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4621 enum machine_mode mode
= GET_MODE (x
);
4625 /* XXX TBD. For now, use the standard costs. */
4626 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4633 /* A memory access costs 1 insn if the mode is small, or the address is
4634 a single register, otherwise it costs one insn per word. */
4635 if (REG_P (XEXP (x
, 0)))
4636 *total
= COSTS_N_INSNS (1);
4638 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4645 /* Needs a libcall, so it costs about this. */
4646 *total
= COSTS_N_INSNS (2);
4650 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4652 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4660 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4662 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4665 else if (mode
== SImode
)
4667 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4668 /* Slightly disparage register shifts, but not by much. */
4669 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4670 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4674 /* Needs a libcall. */
4675 *total
= COSTS_N_INSNS (2);
4679 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4681 *total
= COSTS_N_INSNS (1);
4687 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4688 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4690 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4691 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4692 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4693 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4694 || subcode1
== ASHIFTRT
)
4696 /* It's just the cost of the two operands. */
4701 *total
= COSTS_N_INSNS (1);
4705 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4709 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4711 *total
= COSTS_N_INSNS (1);
4716 case AND
: case XOR
: case IOR
:
4719 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4721 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4722 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4723 || (code
== AND
&& subcode
== NOT
))
4725 /* It's just the cost of the two operands. */
4731 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4735 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4739 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4740 *total
= COSTS_N_INSNS (1);
4743 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4752 if (cc_register (XEXP (x
, 0), VOIDmode
))
4755 *total
= COSTS_N_INSNS (1);
4759 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4760 *total
= COSTS_N_INSNS (1);
4762 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4767 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4769 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4770 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4773 *total
+= COSTS_N_INSNS (1);
4778 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4780 switch (GET_MODE (XEXP (x
, 0)))
4783 *total
+= COSTS_N_INSNS (1);
4787 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4793 *total
+= COSTS_N_INSNS (2);
4798 *total
+= COSTS_N_INSNS (1);
4803 if (const_ok_for_arm (INTVAL (x
)))
4804 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4805 else if (const_ok_for_arm (~INTVAL (x
)))
4806 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4807 else if (const_ok_for_arm (-INTVAL (x
)))
4809 if (outer_code
== COMPARE
|| outer_code
== PLUS
4810 || outer_code
== MINUS
)
4813 *total
= COSTS_N_INSNS (1);
4816 *total
= COSTS_N_INSNS (2);
4822 *total
= COSTS_N_INSNS (2);
4826 *total
= COSTS_N_INSNS (4);
4830 if (mode
!= VOIDmode
)
4831 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4833 *total
= COSTS_N_INSNS (4); /* How knows? */
4838 /* RTX costs for cores with a slow MUL implementation. */
4841 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4843 enum machine_mode mode
= GET_MODE (x
);
4847 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4854 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4861 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4863 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4864 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4865 int cost
, const_ok
= const_ok_for_arm (i
);
4866 int j
, booth_unit_size
;
4868 /* Tune as appropriate. */
4869 cost
= const_ok
? 4 : 8;
4870 booth_unit_size
= 2;
4871 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4873 i
>>= booth_unit_size
;
4881 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4882 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4886 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4892 /* RTX cost for cores with a fast multiply unit (M variants). */
4895 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4897 enum machine_mode mode
= GET_MODE (x
);
4901 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4908 /* There is no point basing this on the tuning, since it is always the
4909 fast variant if it exists at all. */
4911 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4912 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4913 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4920 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4927 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4929 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4930 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4931 int cost
, const_ok
= const_ok_for_arm (i
);
4932 int j
, booth_unit_size
;
4934 /* Tune as appropriate. */
4935 cost
= const_ok
? 4 : 8;
4936 booth_unit_size
= 8;
4937 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4939 i
>>= booth_unit_size
;
4947 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4948 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4952 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4958 /* RTX cost for XScale CPUs. */
4961 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4963 enum machine_mode mode
= GET_MODE (x
);
4967 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4974 /* There is no point basing this on the tuning, since it is always the
4975 fast variant if it exists at all. */
4977 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4978 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4979 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4986 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4993 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4995 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4996 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4997 int cost
, const_ok
= const_ok_for_arm (i
);
4998 unsigned HOST_WIDE_INT masked_const
;
5000 /* The cost will be related to two insns.
5001 First a load of the constant (MOV or LDR), then a multiply. */
5004 cost
+= 1; /* LDR is probably more expensive because
5005 of longer result latency. */
5006 masked_const
= i
& 0xffff8000;
5007 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
5009 masked_const
= i
& 0xf8000000;
5010 if (masked_const
== 0 || masked_const
== 0xf8000000)
5019 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5020 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5024 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5025 will stall until the multiplication is complete. */
5026 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5027 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
5029 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5033 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5039 /* RTX costs for 9e (and later) cores. */
5042 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5044 enum machine_mode mode
= GET_MODE (x
);
5053 *total
= COSTS_N_INSNS (3);
5057 *total
= thumb_rtx_costs (x
, code
, outer_code
);
5065 /* There is no point basing this on the tuning, since it is always the
5066 fast variant if it exists at all. */
5068 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5069 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5070 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5077 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5094 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5095 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5099 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5103 /* All address computations that can be done are free, but rtx cost returns
5104 the same for practically all of them. So we weight the different types
5105 of address here in the order (most pref first):
5106 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5108 arm_arm_address_cost (rtx x
)
5110 enum rtx_code c
= GET_CODE (x
);
5112 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5114 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5117 if (c
== PLUS
|| c
== MINUS
)
5119 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5122 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5132 arm_thumb_address_cost (rtx x
)
5134 enum rtx_code c
= GET_CODE (x
);
5139 && GET_CODE (XEXP (x
, 0)) == REG
5140 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5147 arm_address_cost (rtx x
)
5149 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5153 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5157 /* Some true dependencies can have a higher cost depending
5158 on precisely how certain input operands are used. */
5160 && REG_NOTE_KIND (link
) == 0
5161 && recog_memoized (insn
) >= 0
5162 && recog_memoized (dep
) >= 0)
5164 int shift_opnum
= get_attr_shift (insn
);
5165 enum attr_type attr_type
= get_attr_type (dep
);
5167 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5168 operand for INSN. If we have a shifted input operand and the
5169 instruction we depend on is another ALU instruction, then we may
5170 have to account for an additional stall. */
5171 if (shift_opnum
!= 0
5172 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5174 rtx shifted_operand
;
5177 /* Get the shifted operand. */
5178 extract_insn (insn
);
5179 shifted_operand
= recog_data
.operand
[shift_opnum
];
5181 /* Iterate over all the operands in DEP. If we write an operand
5182 that overlaps with SHIFTED_OPERAND, then we have increase the
5183 cost of this dependency. */
5185 preprocess_constraints ();
5186 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5188 /* We can ignore strict inputs. */
5189 if (recog_data
.operand_type
[opno
] == OP_IN
)
5192 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5199 /* XXX This is not strictly true for the FPA. */
5200 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5201 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5204 /* Call insns don't incur a stall, even if they follow a load. */
5205 if (REG_NOTE_KIND (link
) == 0
5206 && GET_CODE (insn
) == CALL_INSN
)
5209 if ((i_pat
= single_set (insn
)) != NULL
5210 && GET_CODE (SET_SRC (i_pat
)) == MEM
5211 && (d_pat
= single_set (dep
)) != NULL
5212 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5214 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5215 /* This is a load after a store, there is no conflict if the load reads
5216 from a cached area. Assume that loads from the stack, and from the
5217 constant pool are cached, and that others will miss. This is a
5220 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5221 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5222 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5223 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5230 static int fp_consts_inited
= 0;
5232 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5233 static const char * const strings_fp
[8] =
5236 "4", "5", "0.5", "10"
5239 static REAL_VALUE_TYPE values_fp
[8];
5242 init_fp_table (void)
5248 fp_consts_inited
= 1;
5250 fp_consts_inited
= 8;
5252 for (i
= 0; i
< fp_consts_inited
; i
++)
5254 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5259 /* Return TRUE if rtx X is a valid immediate FP constant. */
5261 arm_const_double_rtx (rtx x
)
5266 if (!fp_consts_inited
)
5269 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5270 if (REAL_VALUE_MINUS_ZERO (r
))
5273 for (i
= 0; i
< fp_consts_inited
; i
++)
5274 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5280 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5282 neg_const_double_rtx_ok_for_fpa (rtx x
)
5287 if (!fp_consts_inited
)
5290 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5291 r
= REAL_VALUE_NEGATE (r
);
5292 if (REAL_VALUE_MINUS_ZERO (r
))
5295 for (i
= 0; i
< 8; i
++)
5296 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5302 /* Predicates for `match_operand' and `match_operator'. */
5304 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5306 cirrus_memory_offset (rtx op
)
5308 /* Reject eliminable registers. */
5309 if (! (reload_in_progress
|| reload_completed
)
5310 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5311 || reg_mentioned_p (arg_pointer_rtx
, op
)
5312 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5313 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5314 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5315 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5318 if (GET_CODE (op
) == MEM
)
5324 /* Match: (mem (reg)). */
5325 if (GET_CODE (ind
) == REG
)
5331 if (GET_CODE (ind
) == PLUS
5332 && GET_CODE (XEXP (ind
, 0)) == REG
5333 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5334 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5341 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5342 WB if true if writeback address modes are allowed. */
5345 arm_coproc_mem_operand (rtx op
, bool wb
)
5349 /* Reject eliminable registers. */
5350 if (! (reload_in_progress
|| reload_completed
)
5351 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5352 || reg_mentioned_p (arg_pointer_rtx
, op
)
5353 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5354 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5355 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5356 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5359 /* Constants are converted into offsets from labels. */
5360 if (GET_CODE (op
) != MEM
)
5365 if (reload_completed
5366 && (GET_CODE (ind
) == LABEL_REF
5367 || (GET_CODE (ind
) == CONST
5368 && GET_CODE (XEXP (ind
, 0)) == PLUS
5369 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5370 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5373 /* Match: (mem (reg)). */
5374 if (GET_CODE (ind
) == REG
)
5375 return arm_address_register_rtx_p (ind
, 0);
5377 /* Autoincremment addressing modes. */
5379 && (GET_CODE (ind
) == PRE_INC
5380 || GET_CODE (ind
) == POST_INC
5381 || GET_CODE (ind
) == PRE_DEC
5382 || GET_CODE (ind
) == POST_DEC
))
5383 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5386 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5387 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5388 && GET_CODE (XEXP (ind
, 1)) == PLUS
5389 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5390 ind
= XEXP (ind
, 1);
5395 if (GET_CODE (ind
) == PLUS
5396 && GET_CODE (XEXP (ind
, 0)) == REG
5397 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5398 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5399 && INTVAL (XEXP (ind
, 1)) > -1024
5400 && INTVAL (XEXP (ind
, 1)) < 1024
5401 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5407 /* Return true if X is a register that will be eliminated later on. */
5409 arm_eliminable_register (rtx x
)
5411 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5412 || REGNO (x
) == ARG_POINTER_REGNUM
5413 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5414 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5417 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5418 VFP registers. Otherwise return NO_REGS. */
5421 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5423 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5426 return GENERAL_REGS
;
5429 /* Values which must be returned in the most-significant end of the return
5433 arm_return_in_msb (tree valtype
)
5435 return (TARGET_AAPCS_BASED
5437 && (AGGREGATE_TYPE_P (valtype
)
5438 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5441 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5442 Use by the Cirrus Maverick code which has to workaround
5443 a hardware bug triggered by such instructions. */
5445 arm_memory_load_p (rtx insn
)
5447 rtx body
, lhs
, rhs
;;
5449 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5452 body
= PATTERN (insn
);
5454 if (GET_CODE (body
) != SET
)
5457 lhs
= XEXP (body
, 0);
5458 rhs
= XEXP (body
, 1);
5460 lhs
= REG_OR_SUBREG_RTX (lhs
);
5462 /* If the destination is not a general purpose
5463 register we do not have to worry. */
5464 if (GET_CODE (lhs
) != REG
5465 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5468 /* As well as loads from memory we also have to react
5469 to loads of invalid constants which will be turned
5470 into loads from the minipool. */
5471 return (GET_CODE (rhs
) == MEM
5472 || GET_CODE (rhs
) == SYMBOL_REF
5473 || note_invalid_constants (insn
, -1, false));
5476 /* Return TRUE if INSN is a Cirrus instruction. */
5478 arm_cirrus_insn_p (rtx insn
)
5480 enum attr_cirrus attr
;
5482 /* get_attr cannot accept USE or CLOBBER. */
5484 || GET_CODE (insn
) != INSN
5485 || GET_CODE (PATTERN (insn
)) == USE
5486 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5489 attr
= get_attr_cirrus (insn
);
5491 return attr
!= CIRRUS_NOT
;
5494 /* Cirrus reorg for invalid instruction combinations. */
5496 cirrus_reorg (rtx first
)
5498 enum attr_cirrus attr
;
5499 rtx body
= PATTERN (first
);
5503 /* Any branch must be followed by 2 non Cirrus instructions. */
5504 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5507 t
= next_nonnote_insn (first
);
5509 if (arm_cirrus_insn_p (t
))
5512 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5516 emit_insn_after (gen_nop (), first
);
5521 /* (float (blah)) is in parallel with a clobber. */
5522 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5523 body
= XVECEXP (body
, 0, 0);
5525 if (GET_CODE (body
) == SET
)
5527 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5529 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5530 be followed by a non Cirrus insn. */
5531 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5533 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5534 emit_insn_after (gen_nop (), first
);
5538 else if (arm_memory_load_p (first
))
5540 unsigned int arm_regno
;
5542 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5543 ldr/cfmv64hr combination where the Rd field is the same
5544 in both instructions must be split with a non Cirrus
5551 /* Get Arm register number for ldr insn. */
5552 if (GET_CODE (lhs
) == REG
)
5553 arm_regno
= REGNO (lhs
);
5556 gcc_assert (GET_CODE (rhs
) == REG
);
5557 arm_regno
= REGNO (rhs
);
5561 first
= next_nonnote_insn (first
);
5563 if (! arm_cirrus_insn_p (first
))
5566 body
= PATTERN (first
);
5568 /* (float (blah)) is in parallel with a clobber. */
5569 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5570 body
= XVECEXP (body
, 0, 0);
5572 if (GET_CODE (body
) == FLOAT
)
5573 body
= XEXP (body
, 0);
5575 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5576 && GET_CODE (XEXP (body
, 1)) == REG
5577 && arm_regno
== REGNO (XEXP (body
, 1)))
5578 emit_insn_after (gen_nop (), first
);
5584 /* get_attr cannot accept USE or CLOBBER. */
5586 || GET_CODE (first
) != INSN
5587 || GET_CODE (PATTERN (first
)) == USE
5588 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5591 attr
= get_attr_cirrus (first
);
5593 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5594 must be followed by a non-coprocessor instruction. */
5595 if (attr
== CIRRUS_COMPARE
)
5599 t
= next_nonnote_insn (first
);
5601 if (arm_cirrus_insn_p (t
))
5604 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5608 emit_insn_after (gen_nop (), first
);
5614 /* Return TRUE if X references a SYMBOL_REF. */
5616 symbol_mentioned_p (rtx x
)
5621 if (GET_CODE (x
) == SYMBOL_REF
)
5624 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5625 are constant offsets, not symbols. */
5626 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5629 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5631 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5637 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5638 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5641 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5648 /* Return TRUE if X references a LABEL_REF. */
5650 label_mentioned_p (rtx x
)
5655 if (GET_CODE (x
) == LABEL_REF
)
5658 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5659 instruction, but they are constant offsets, not symbols. */
5660 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5663 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5664 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5670 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5671 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5674 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5682 tls_mentioned_p (rtx x
)
5684 switch (GET_CODE (x
))
5687 return tls_mentioned_p (XEXP (x
, 0));
5690 if (XINT (x
, 1) == UNSPEC_TLS
)
5698 /* Must not copy a SET whose source operand is PC-relative. */
5701 arm_cannot_copy_insn_p (rtx insn
)
5703 rtx pat
= PATTERN (insn
);
5705 if (GET_CODE (pat
) == PARALLEL
5706 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5708 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5710 if (GET_CODE (rhs
) == UNSPEC
5711 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5714 if (GET_CODE (rhs
) == MEM
5715 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5716 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5726 enum rtx_code code
= GET_CODE (x
);
5743 /* Return 1 if memory locations are adjacent. */
5745 adjacent_mem_locations (rtx a
, rtx b
)
5747 /* We don't guarantee to preserve the order of these memory refs. */
5748 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5751 if ((GET_CODE (XEXP (a
, 0)) == REG
5752 || (GET_CODE (XEXP (a
, 0)) == PLUS
5753 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5754 && (GET_CODE (XEXP (b
, 0)) == REG
5755 || (GET_CODE (XEXP (b
, 0)) == PLUS
5756 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5758 HOST_WIDE_INT val0
= 0, val1
= 0;
5762 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5764 reg0
= XEXP (XEXP (a
, 0), 0);
5765 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5770 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5772 reg1
= XEXP (XEXP (b
, 0), 0);
5773 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5778 /* Don't accept any offset that will require multiple
5779 instructions to handle, since this would cause the
5780 arith_adjacentmem pattern to output an overlong sequence. */
5781 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5784 /* Don't allow an eliminable register: register elimination can make
5785 the offset too large. */
5786 if (arm_eliminable_register (reg0
))
5789 val_diff
= val1
- val0
;
5793 /* If the target has load delay slots, then there's no benefit
5794 to using an ldm instruction unless the offset is zero and
5795 we are optimizing for size. */
5796 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5797 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5798 && (val_diff
== 4 || val_diff
== -4));
5801 return ((REGNO (reg0
) == REGNO (reg1
))
5802 && (val_diff
== 4 || val_diff
== -4));
5809 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5810 HOST_WIDE_INT
*load_offset
)
5812 int unsorted_regs
[4];
5813 HOST_WIDE_INT unsorted_offsets
[4];
5818 /* Can only handle 2, 3, or 4 insns at present,
5819 though could be easily extended if required. */
5820 gcc_assert (nops
>= 2 && nops
<= 4);
5822 /* Loop over the operands and check that the memory references are
5823 suitable (i.e. immediate offsets from the same base register). At
5824 the same time, extract the target register, and the memory
5826 for (i
= 0; i
< nops
; i
++)
5831 /* Convert a subreg of a mem into the mem itself. */
5832 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5833 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5835 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5837 /* Don't reorder volatile memory references; it doesn't seem worth
5838 looking for the case where the order is ok anyway. */
5839 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5842 offset
= const0_rtx
;
5844 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5845 || (GET_CODE (reg
) == SUBREG
5846 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5847 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5848 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5850 || (GET_CODE (reg
) == SUBREG
5851 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5852 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5857 base_reg
= REGNO (reg
);
5858 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5859 ? REGNO (operands
[i
])
5860 : REGNO (SUBREG_REG (operands
[i
])));
5865 if (base_reg
!= (int) REGNO (reg
))
5866 /* Not addressed from the same base register. */
5869 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5870 ? REGNO (operands
[i
])
5871 : REGNO (SUBREG_REG (operands
[i
])));
5872 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5876 /* If it isn't an integer register, or if it overwrites the
5877 base register but isn't the last insn in the list, then
5878 we can't do this. */
5879 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5880 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5883 unsorted_offsets
[i
] = INTVAL (offset
);
5886 /* Not a suitable memory address. */
5890 /* All the useful information has now been extracted from the
5891 operands into unsorted_regs and unsorted_offsets; additionally,
5892 order[0] has been set to the lowest numbered register in the
5893 list. Sort the registers into order, and check that the memory
5894 offsets are ascending and adjacent. */
5896 for (i
= 1; i
< nops
; i
++)
5900 order
[i
] = order
[i
- 1];
5901 for (j
= 0; j
< nops
; j
++)
5902 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5903 && (order
[i
] == order
[i
- 1]
5904 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5907 /* Have we found a suitable register? if not, one must be used more
5909 if (order
[i
] == order
[i
- 1])
5912 /* Is the memory address adjacent and ascending? */
5913 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5921 for (i
= 0; i
< nops
; i
++)
5922 regs
[i
] = unsorted_regs
[order
[i
]];
5924 *load_offset
= unsorted_offsets
[order
[0]];
5927 if (unsorted_offsets
[order
[0]] == 0)
5928 return 1; /* ldmia */
5930 if (unsorted_offsets
[order
[0]] == 4)
5931 return 2; /* ldmib */
5933 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5934 return 3; /* ldmda */
5936 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5937 return 4; /* ldmdb */
5939 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5940 if the offset isn't small enough. The reason 2 ldrs are faster
5941 is because these ARMs are able to do more than one cache access
5942 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5943 whilst the ARM8 has a double bandwidth cache. This means that
5944 these cores can do both an instruction fetch and a data fetch in
5945 a single cycle, so the trick of calculating the address into a
5946 scratch register (one of the result regs) and then doing a load
5947 multiple actually becomes slower (and no smaller in code size).
5948 That is the transformation
5950 ldr rd1, [rbase + offset]
5951 ldr rd2, [rbase + offset + 4]
5955 add rd1, rbase, offset
5956 ldmia rd1, {rd1, rd2}
5958 produces worse code -- '3 cycles + any stalls on rd2' instead of
5959 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5960 access per cycle, the first sequence could never complete in less
5961 than 6 cycles, whereas the ldm sequence would only take 5 and
5962 would make better use of sequential accesses if not hitting the
5965 We cheat here and test 'arm_ld_sched' which we currently know to
5966 only be true for the ARM8, ARM9 and StrongARM. If this ever
5967 changes, then the test below needs to be reworked. */
5968 if (nops
== 2 && arm_ld_sched
)
5971 /* Can't do it without setting up the offset, only do this if it takes
5972 no more than one insn. */
5973 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5974 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5978 emit_ldm_seq (rtx
*operands
, int nops
)
5982 HOST_WIDE_INT offset
;
5986 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5989 strcpy (buf
, "ldm%?ia\t");
5993 strcpy (buf
, "ldm%?ib\t");
5997 strcpy (buf
, "ldm%?da\t");
6001 strcpy (buf
, "ldm%?db\t");
6006 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6007 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6010 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6011 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6013 output_asm_insn (buf
, operands
);
6015 strcpy (buf
, "ldm%?ia\t");
6022 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6023 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6025 for (i
= 1; i
< nops
; i
++)
6026 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6027 reg_names
[regs
[i
]]);
6029 strcat (buf
, "}\t%@ phole ldm");
6031 output_asm_insn (buf
, operands
);
6036 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6037 HOST_WIDE_INT
* load_offset
)
6039 int unsorted_regs
[4];
6040 HOST_WIDE_INT unsorted_offsets
[4];
6045 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6046 extended if required. */
6047 gcc_assert (nops
>= 2 && nops
<= 4);
6049 /* Loop over the operands and check that the memory references are
6050 suitable (i.e. immediate offsets from the same base register). At
6051 the same time, extract the target register, and the memory
6053 for (i
= 0; i
< nops
; i
++)
6058 /* Convert a subreg of a mem into the mem itself. */
6059 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6060 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6062 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6064 /* Don't reorder volatile memory references; it doesn't seem worth
6065 looking for the case where the order is ok anyway. */
6066 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6069 offset
= const0_rtx
;
6071 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6072 || (GET_CODE (reg
) == SUBREG
6073 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6074 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6075 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6077 || (GET_CODE (reg
) == SUBREG
6078 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6079 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6084 base_reg
= REGNO (reg
);
6085 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6086 ? REGNO (operands
[i
])
6087 : REGNO (SUBREG_REG (operands
[i
])));
6092 if (base_reg
!= (int) REGNO (reg
))
6093 /* Not addressed from the same base register. */
6096 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6097 ? REGNO (operands
[i
])
6098 : REGNO (SUBREG_REG (operands
[i
])));
6099 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6103 /* If it isn't an integer register, then we can't do this. */
6104 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6107 unsorted_offsets
[i
] = INTVAL (offset
);
6110 /* Not a suitable memory address. */
6114 /* All the useful information has now been extracted from the
6115 operands into unsorted_regs and unsorted_offsets; additionally,
6116 order[0] has been set to the lowest numbered register in the
6117 list. Sort the registers into order, and check that the memory
6118 offsets are ascending and adjacent. */
6120 for (i
= 1; i
< nops
; i
++)
6124 order
[i
] = order
[i
- 1];
6125 for (j
= 0; j
< nops
; j
++)
6126 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6127 && (order
[i
] == order
[i
- 1]
6128 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6131 /* Have we found a suitable register? if not, one must be used more
6133 if (order
[i
] == order
[i
- 1])
6136 /* Is the memory address adjacent and ascending? */
6137 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6145 for (i
= 0; i
< nops
; i
++)
6146 regs
[i
] = unsorted_regs
[order
[i
]];
6148 *load_offset
= unsorted_offsets
[order
[0]];
6151 if (unsorted_offsets
[order
[0]] == 0)
6152 return 1; /* stmia */
6154 if (unsorted_offsets
[order
[0]] == 4)
6155 return 2; /* stmib */
6157 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6158 return 3; /* stmda */
6160 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6161 return 4; /* stmdb */
6167 emit_stm_seq (rtx
*operands
, int nops
)
6171 HOST_WIDE_INT offset
;
6175 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6178 strcpy (buf
, "stm%?ia\t");
6182 strcpy (buf
, "stm%?ib\t");
6186 strcpy (buf
, "stm%?da\t");
6190 strcpy (buf
, "stm%?db\t");
6197 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6198 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6200 for (i
= 1; i
< nops
; i
++)
6201 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6202 reg_names
[regs
[i
]]);
6204 strcat (buf
, "}\t%@ phole stm");
6206 output_asm_insn (buf
, operands
);
6210 /* Routines for use in generating RTL. */
6213 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6214 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6216 HOST_WIDE_INT offset
= *offsetp
;
6219 int sign
= up
? 1 : -1;
6222 /* XScale has load-store double instructions, but they have stricter
6223 alignment requirements than load-store multiple, so we cannot
6226 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6227 the pipeline until completion.
6235 An ldr instruction takes 1-3 cycles, but does not block the
6244 Best case ldr will always win. However, the more ldr instructions
6245 we issue, the less likely we are to be able to schedule them well.
6246 Using ldr instructions also increases code size.
6248 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6249 for counts of 3 or 4 regs. */
6250 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6256 for (i
= 0; i
< count
; i
++)
6258 addr
= plus_constant (from
, i
* 4 * sign
);
6259 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6260 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6266 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6276 result
= gen_rtx_PARALLEL (VOIDmode
,
6277 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6280 XVECEXP (result
, 0, 0)
6281 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
6286 for (j
= 0; i
< count
; i
++, j
++)
6288 addr
= plus_constant (from
, j
* 4 * sign
);
6289 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6290 XVECEXP (result
, 0, i
)
6291 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6302 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6303 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6305 HOST_WIDE_INT offset
= *offsetp
;
6308 int sign
= up
? 1 : -1;
6311 /* See arm_gen_load_multiple for discussion of
6312 the pros/cons of ldm/stm usage for XScale. */
6313 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6319 for (i
= 0; i
< count
; i
++)
6321 addr
= plus_constant (to
, i
* 4 * sign
);
6322 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6323 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6329 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6339 result
= gen_rtx_PARALLEL (VOIDmode
,
6340 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6343 XVECEXP (result
, 0, 0)
6344 = gen_rtx_SET (VOIDmode
, to
,
6345 plus_constant (to
, count
* 4 * sign
));
6350 for (j
= 0; i
< count
; i
++, j
++)
6352 addr
= plus_constant (to
, j
* 4 * sign
);
6353 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6354 XVECEXP (result
, 0, i
)
6355 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6366 arm_gen_movmemqi (rtx
*operands
)
6368 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6369 HOST_WIDE_INT srcoffset
, dstoffset
;
6371 rtx src
, dst
, srcbase
, dstbase
;
6372 rtx part_bytes_reg
= NULL
;
6375 if (GET_CODE (operands
[2]) != CONST_INT
6376 || GET_CODE (operands
[3]) != CONST_INT
6377 || INTVAL (operands
[2]) > 64
6378 || INTVAL (operands
[3]) & 3)
6381 dstbase
= operands
[0];
6382 srcbase
= operands
[1];
6384 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6385 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6387 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6388 out_words_to_go
= INTVAL (operands
[2]) / 4;
6389 last_bytes
= INTVAL (operands
[2]) & 3;
6390 dstoffset
= srcoffset
= 0;
6392 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6393 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6395 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6397 if (in_words_to_go
> 4)
6398 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6399 srcbase
, &srcoffset
));
6401 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6402 FALSE
, srcbase
, &srcoffset
));
6404 if (out_words_to_go
)
6406 if (out_words_to_go
> 4)
6407 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6408 dstbase
, &dstoffset
));
6409 else if (out_words_to_go
!= 1)
6410 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6414 dstbase
, &dstoffset
));
6417 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6418 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6419 if (last_bytes
!= 0)
6421 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6427 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6428 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6431 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6432 if (out_words_to_go
)
6436 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6437 sreg
= copy_to_reg (mem
);
6439 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6440 emit_move_insn (mem
, sreg
);
6443 gcc_assert (!in_words_to_go
); /* Sanity check */
6448 gcc_assert (in_words_to_go
> 0);
6450 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6451 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6454 gcc_assert (!last_bytes
|| part_bytes_reg
);
6456 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6458 rtx tmp
= gen_reg_rtx (SImode
);
6460 /* The bytes we want are in the top end of the word. */
6461 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6462 GEN_INT (8 * (4 - last_bytes
))));
6463 part_bytes_reg
= tmp
;
6467 mem
= adjust_automodify_address (dstbase
, QImode
,
6468 plus_constant (dst
, last_bytes
- 1),
6469 dstoffset
+ last_bytes
- 1);
6470 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6474 tmp
= gen_reg_rtx (SImode
);
6475 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6476 part_bytes_reg
= tmp
;
6485 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6486 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6490 rtx tmp
= gen_reg_rtx (SImode
);
6491 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6492 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6493 part_bytes_reg
= tmp
;
6500 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6501 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6508 /* Select a dominance comparison mode if possible for a test of the general
6509 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6510 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6511 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6512 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6513 In all cases OP will be either EQ or NE, but we don't need to know which
6514 here. If we are unable to support a dominance comparison we return
6515 CC mode. This will then fail to match for the RTL expressions that
6516 generate this call. */
6518 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6520 enum rtx_code cond1
, cond2
;
6523 /* Currently we will probably get the wrong result if the individual
6524 comparisons are not simple. This also ensures that it is safe to
6525 reverse a comparison if necessary. */
6526 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6528 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6532 /* The if_then_else variant of this tests the second condition if the
6533 first passes, but is true if the first fails. Reverse the first
6534 condition to get a true "inclusive-or" expression. */
6535 if (cond_or
== DOM_CC_NX_OR_Y
)
6536 cond1
= reverse_condition (cond1
);
6538 /* If the comparisons are not equal, and one doesn't dominate the other,
6539 then we can't do this. */
6541 && !comparison_dominates_p (cond1
, cond2
)
6542 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6547 enum rtx_code temp
= cond1
;
6555 if (cond_or
== DOM_CC_X_AND_Y
)
6560 case EQ
: return CC_DEQmode
;
6561 case LE
: return CC_DLEmode
;
6562 case LEU
: return CC_DLEUmode
;
6563 case GE
: return CC_DGEmode
;
6564 case GEU
: return CC_DGEUmode
;
6565 default: gcc_unreachable ();
6569 if (cond_or
== DOM_CC_X_AND_Y
)
6585 if (cond_or
== DOM_CC_X_AND_Y
)
6601 if (cond_or
== DOM_CC_X_AND_Y
)
6617 if (cond_or
== DOM_CC_X_AND_Y
)
6632 /* The remaining cases only occur when both comparisons are the
6635 gcc_assert (cond1
== cond2
);
6639 gcc_assert (cond1
== cond2
);
6643 gcc_assert (cond1
== cond2
);
6647 gcc_assert (cond1
== cond2
);
6651 gcc_assert (cond1
== cond2
);
6660 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6662 /* All floating point compares return CCFP if it is an equality
6663 comparison, and CCFPE otherwise. */
6664 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6684 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6693 /* A compare with a shifted operand. Because of canonicalization, the
6694 comparison will have to be swapped when we emit the assembler. */
6695 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6696 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6697 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6698 || GET_CODE (x
) == ROTATERT
))
6701 /* This operation is performed swapped, but since we only rely on the Z
6702 flag we don't need an additional mode. */
6703 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6704 && GET_CODE (x
) == NEG
6705 && (op
== EQ
|| op
== NE
))
6708 /* This is a special case that is used by combine to allow a
6709 comparison of a shifted byte load to be split into a zero-extend
6710 followed by a comparison of the shifted integer (only valid for
6711 equalities and unsigned inequalities). */
6712 if (GET_MODE (x
) == SImode
6713 && GET_CODE (x
) == ASHIFT
6714 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6715 && GET_CODE (XEXP (x
, 0)) == SUBREG
6716 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6717 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6718 && (op
== EQ
|| op
== NE
6719 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6720 && GET_CODE (y
) == CONST_INT
)
6723 /* A construct for a conditional compare, if the false arm contains
6724 0, then both conditions must be true, otherwise either condition
6725 must be true. Not all conditions are possible, so CCmode is
6726 returned if it can't be done. */
6727 if (GET_CODE (x
) == IF_THEN_ELSE
6728 && (XEXP (x
, 2) == const0_rtx
6729 || XEXP (x
, 2) == const1_rtx
)
6730 && COMPARISON_P (XEXP (x
, 0))
6731 && COMPARISON_P (XEXP (x
, 1)))
6732 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6733 INTVAL (XEXP (x
, 2)));
6735 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6736 if (GET_CODE (x
) == AND
6737 && COMPARISON_P (XEXP (x
, 0))
6738 && COMPARISON_P (XEXP (x
, 1)))
6739 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6742 if (GET_CODE (x
) == IOR
6743 && COMPARISON_P (XEXP (x
, 0))
6744 && COMPARISON_P (XEXP (x
, 1)))
6745 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6748 /* An operation (on Thumb) where we want to test for a single bit.
6749 This is done by shifting that bit up into the top bit of a
6750 scratch register; we can then branch on the sign bit. */
6752 && GET_MODE (x
) == SImode
6753 && (op
== EQ
|| op
== NE
)
6754 && GET_CODE (x
) == ZERO_EXTRACT
6755 && XEXP (x
, 1) == const1_rtx
)
6758 /* An operation that sets the condition codes as a side-effect, the
6759 V flag is not set correctly, so we can only use comparisons where
6760 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6762 if (GET_MODE (x
) == SImode
6764 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6765 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6766 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6767 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6768 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6769 || GET_CODE (x
) == LSHIFTRT
6770 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6771 || GET_CODE (x
) == ROTATERT
6772 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6775 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6778 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6779 && GET_CODE (x
) == PLUS
6780 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6786 /* X and Y are two things to compare using CODE. Emit the compare insn and
6787 return the rtx for register 0 in the proper mode. FP means this is a
6788 floating point compare: I don't think that it is needed on the arm. */
6790 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6792 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6793 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6795 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
6800 /* Generate a sequence of insns that will generate the correct return
6801 address mask depending on the physical architecture that the program
6804 arm_gen_return_addr_mask (void)
6806 rtx reg
= gen_reg_rtx (Pmode
);
6808 emit_insn (gen_return_addr_mask (reg
));
6813 arm_reload_in_hi (rtx
*operands
)
6815 rtx ref
= operands
[1];
6817 HOST_WIDE_INT offset
= 0;
6819 if (GET_CODE (ref
) == SUBREG
)
6821 offset
= SUBREG_BYTE (ref
);
6822 ref
= SUBREG_REG (ref
);
6825 if (GET_CODE (ref
) == REG
)
6827 /* We have a pseudo which has been spilt onto the stack; there
6828 are two cases here: the first where there is a simple
6829 stack-slot replacement and a second where the stack-slot is
6830 out of range, or is used as a subreg. */
6831 if (reg_equiv_mem
[REGNO (ref
)])
6833 ref
= reg_equiv_mem
[REGNO (ref
)];
6834 base
= find_replacement (&XEXP (ref
, 0));
6837 /* The slot is out of range, or was dressed up in a SUBREG. */
6838 base
= reg_equiv_address
[REGNO (ref
)];
6841 base
= find_replacement (&XEXP (ref
, 0));
6843 /* Handle the case where the address is too complex to be offset by 1. */
6844 if (GET_CODE (base
) == MINUS
6845 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6847 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6849 emit_set_insn (base_plus
, base
);
6852 else if (GET_CODE (base
) == PLUS
)
6854 /* The addend must be CONST_INT, or we would have dealt with it above. */
6855 HOST_WIDE_INT hi
, lo
;
6857 offset
+= INTVAL (XEXP (base
, 1));
6858 base
= XEXP (base
, 0);
6860 /* Rework the address into a legal sequence of insns. */
6861 /* Valid range for lo is -4095 -> 4095 */
6864 : -((-offset
) & 0xfff));
6866 /* Corner case, if lo is the max offset then we would be out of range
6867 once we have added the additional 1 below, so bump the msb into the
6868 pre-loading insn(s). */
6872 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6873 ^ (HOST_WIDE_INT
) 0x80000000)
6874 - (HOST_WIDE_INT
) 0x80000000);
6876 gcc_assert (hi
+ lo
== offset
);
6880 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6882 /* Get the base address; addsi3 knows how to handle constants
6883 that require more than one insn. */
6884 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6890 /* Operands[2] may overlap operands[0] (though it won't overlap
6891 operands[1]), that's why we asked for a DImode reg -- so we can
6892 use the bit that does not overlap. */
6893 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6894 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6896 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6898 emit_insn (gen_zero_extendqisi2 (scratch
,
6899 gen_rtx_MEM (QImode
,
6900 plus_constant (base
,
6902 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6903 gen_rtx_MEM (QImode
,
6904 plus_constant (base
,
6906 if (!BYTES_BIG_ENDIAN
)
6907 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6908 gen_rtx_IOR (SImode
,
6911 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6915 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6916 gen_rtx_IOR (SImode
,
6917 gen_rtx_ASHIFT (SImode
, scratch
,
6919 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
6922 /* Handle storing a half-word to memory during reload by synthesizing as two
6923 byte stores. Take care not to clobber the input values until after we
6924 have moved them somewhere safe. This code assumes that if the DImode
6925 scratch in operands[2] overlaps either the input value or output address
6926 in some way, then that value must die in this insn (we absolutely need
6927 two scratch registers for some corner cases). */
6929 arm_reload_out_hi (rtx
*operands
)
6931 rtx ref
= operands
[0];
6932 rtx outval
= operands
[1];
6934 HOST_WIDE_INT offset
= 0;
6936 if (GET_CODE (ref
) == SUBREG
)
6938 offset
= SUBREG_BYTE (ref
);
6939 ref
= SUBREG_REG (ref
);
6942 if (GET_CODE (ref
) == REG
)
6944 /* We have a pseudo which has been spilt onto the stack; there
6945 are two cases here: the first where there is a simple
6946 stack-slot replacement and a second where the stack-slot is
6947 out of range, or is used as a subreg. */
6948 if (reg_equiv_mem
[REGNO (ref
)])
6950 ref
= reg_equiv_mem
[REGNO (ref
)];
6951 base
= find_replacement (&XEXP (ref
, 0));
6954 /* The slot is out of range, or was dressed up in a SUBREG. */
6955 base
= reg_equiv_address
[REGNO (ref
)];
6958 base
= find_replacement (&XEXP (ref
, 0));
6960 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6962 /* Handle the case where the address is too complex to be offset by 1. */
6963 if (GET_CODE (base
) == MINUS
6964 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6966 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6968 /* Be careful not to destroy OUTVAL. */
6969 if (reg_overlap_mentioned_p (base_plus
, outval
))
6971 /* Updating base_plus might destroy outval, see if we can
6972 swap the scratch and base_plus. */
6973 if (!reg_overlap_mentioned_p (scratch
, outval
))
6976 scratch
= base_plus
;
6981 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6983 /* Be conservative and copy OUTVAL into the scratch now,
6984 this should only be necessary if outval is a subreg
6985 of something larger than a word. */
6986 /* XXX Might this clobber base? I can't see how it can,
6987 since scratch is known to overlap with OUTVAL, and
6988 must be wider than a word. */
6989 emit_insn (gen_movhi (scratch_hi
, outval
));
6990 outval
= scratch_hi
;
6994 emit_set_insn (base_plus
, base
);
6997 else if (GET_CODE (base
) == PLUS
)
6999 /* The addend must be CONST_INT, or we would have dealt with it above. */
7000 HOST_WIDE_INT hi
, lo
;
7002 offset
+= INTVAL (XEXP (base
, 1));
7003 base
= XEXP (base
, 0);
7005 /* Rework the address into a legal sequence of insns. */
7006 /* Valid range for lo is -4095 -> 4095 */
7009 : -((-offset
) & 0xfff));
7011 /* Corner case, if lo is the max offset then we would be out of range
7012 once we have added the additional 1 below, so bump the msb into the
7013 pre-loading insn(s). */
7017 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7018 ^ (HOST_WIDE_INT
) 0x80000000)
7019 - (HOST_WIDE_INT
) 0x80000000);
7021 gcc_assert (hi
+ lo
== offset
);
7025 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7027 /* Be careful not to destroy OUTVAL. */
7028 if (reg_overlap_mentioned_p (base_plus
, outval
))
7030 /* Updating base_plus might destroy outval, see if we
7031 can swap the scratch and base_plus. */
7032 if (!reg_overlap_mentioned_p (scratch
, outval
))
7035 scratch
= base_plus
;
7040 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7042 /* Be conservative and copy outval into scratch now,
7043 this should only be necessary if outval is a
7044 subreg of something larger than a word. */
7045 /* XXX Might this clobber base? I can't see how it
7046 can, since scratch is known to overlap with
7048 emit_insn (gen_movhi (scratch_hi
, outval
));
7049 outval
= scratch_hi
;
7053 /* Get the base address; addsi3 knows how to handle constants
7054 that require more than one insn. */
7055 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7061 if (BYTES_BIG_ENDIAN
)
7063 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7064 plus_constant (base
, offset
+ 1)),
7065 gen_lowpart (QImode
, outval
)));
7066 emit_insn (gen_lshrsi3 (scratch
,
7067 gen_rtx_SUBREG (SImode
, outval
, 0),
7069 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7070 gen_lowpart (QImode
, scratch
)));
7074 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7075 gen_lowpart (QImode
, outval
)));
7076 emit_insn (gen_lshrsi3 (scratch
,
7077 gen_rtx_SUBREG (SImode
, outval
, 0),
7079 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7080 plus_constant (base
, offset
+ 1)),
7081 gen_lowpart (QImode
, scratch
)));
7085 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7086 (padded to the size of a word) should be passed in a register. */
7089 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7091 if (TARGET_AAPCS_BASED
)
7092 return must_pass_in_stack_var_size (mode
, type
);
7094 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7098 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7099 Return true if an argument passed on the stack should be padded upwards,
7100 i.e. if the least-significant byte has useful data.
7101 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7102 aggregate types are placed in the lowest memory address. */
7105 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7107 if (!TARGET_AAPCS_BASED
)
7108 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7110 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7117 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7118 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7119 byte of the register has useful data, and return the opposite if the
7120 most significant byte does.
7121 For AAPCS, small aggregates and small complex types are always padded
7125 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7126 tree type
, int first ATTRIBUTE_UNUSED
)
7128 if (TARGET_AAPCS_BASED
7130 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7131 && int_size_in_bytes (type
) <= 4)
7134 /* Otherwise, use default padding. */
7135 return !BYTES_BIG_ENDIAN
;
7139 /* Print a symbolic form of X to the debug file, F. */
7141 arm_print_value (FILE *f
, rtx x
)
7143 switch (GET_CODE (x
))
7146 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7150 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7158 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7160 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7161 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7169 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7173 fprintf (f
, "`%s'", XSTR (x
, 0));
7177 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7181 arm_print_value (f
, XEXP (x
, 0));
7185 arm_print_value (f
, XEXP (x
, 0));
7187 arm_print_value (f
, XEXP (x
, 1));
7195 fprintf (f
, "????");
7200 /* Routines for manipulation of the constant pool. */
7202 /* Arm instructions cannot load a large constant directly into a
7203 register; they have to come from a pc relative load. The constant
7204 must therefore be placed in the addressable range of the pc
7205 relative load. Depending on the precise pc relative load
7206 instruction the range is somewhere between 256 bytes and 4k. This
7207 means that we often have to dump a constant inside a function, and
7208 generate code to branch around it.
7210 It is important to minimize this, since the branches will slow
7211 things down and make the code larger.
7213 Normally we can hide the table after an existing unconditional
7214 branch so that there is no interruption of the flow, but in the
7215 worst case the code looks like this:
7233 We fix this by performing a scan after scheduling, which notices
7234 which instructions need to have their operands fetched from the
7235 constant table and builds the table.
7237 The algorithm starts by building a table of all the constants that
7238 need fixing up and all the natural barriers in the function (places
7239 where a constant table can be dropped without breaking the flow).
7240 For each fixup we note how far the pc-relative replacement will be
7241 able to reach and the offset of the instruction into the function.
7243 Having built the table we then group the fixes together to form
7244 tables that are as large as possible (subject to addressing
7245 constraints) and emit each table of constants after the last
7246 barrier that is within range of all the instructions in the group.
7247 If a group does not contain a barrier, then we forcibly create one
7248 by inserting a jump instruction into the flow. Once the table has
7249 been inserted, the insns are then modified to reference the
7250 relevant entry in the pool.
7252 Possible enhancements to the algorithm (not implemented) are:
7254 1) For some processors and object formats, there may be benefit in
7255 aligning the pools to the start of cache lines; this alignment
7256 would need to be taken into account when calculating addressability
7259 /* These typedefs are located at the start of this file, so that
7260 they can be used in the prototypes there. This comment is to
7261 remind readers of that fact so that the following structures
7262 can be understood more easily.
7264 typedef struct minipool_node Mnode;
7265 typedef struct minipool_fixup Mfix; */
7267 struct minipool_node
7269 /* Doubly linked chain of entries. */
7272 /* The maximum offset into the code that this entry can be placed. While
7273 pushing fixes for forward references, all entries are sorted in order
7274 of increasing max_address. */
7275 HOST_WIDE_INT max_address
;
7276 /* Similarly for an entry inserted for a backwards ref. */
7277 HOST_WIDE_INT min_address
;
7278 /* The number of fixes referencing this entry. This can become zero
7279 if we "unpush" an entry. In this case we ignore the entry when we
7280 come to emit the code. */
7282 /* The offset from the start of the minipool. */
7283 HOST_WIDE_INT offset
;
7284 /* The value in table. */
7286 /* The mode of value. */
7287 enum machine_mode mode
;
7288 /* The size of the value. With iWMMXt enabled
7289 sizes > 4 also imply an alignment of 8-bytes. */
7293 struct minipool_fixup
7297 HOST_WIDE_INT address
;
7299 enum machine_mode mode
;
7303 HOST_WIDE_INT forwards
;
7304 HOST_WIDE_INT backwards
;
7307 /* Fixes less than a word need padding out to a word boundary. */
7308 #define MINIPOOL_FIX_SIZE(mode) \
7309 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7311 static Mnode
* minipool_vector_head
;
7312 static Mnode
* minipool_vector_tail
;
7313 static rtx minipool_vector_label
;
7314 static int minipool_pad
;
7316 /* The linked list of all minipool fixes required for this function. */
7317 Mfix
* minipool_fix_head
;
7318 Mfix
* minipool_fix_tail
;
7319 /* The fix entry for the current minipool, once it has been placed. */
7320 Mfix
* minipool_barrier
;
7322 /* Determines if INSN is the start of a jump table. Returns the end
7323 of the TABLE or NULL_RTX. */
7325 is_jump_table (rtx insn
)
7329 if (GET_CODE (insn
) == JUMP_INSN
7330 && JUMP_LABEL (insn
) != NULL
7331 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7332 == next_real_insn (insn
))
7334 && GET_CODE (table
) == JUMP_INSN
7335 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7336 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7342 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7343 #define JUMP_TABLES_IN_TEXT_SECTION 0
7346 static HOST_WIDE_INT
7347 get_jump_table_size (rtx insn
)
7349 /* ADDR_VECs only take room if read-only data does into the text
7351 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
7353 rtx body
= PATTERN (insn
);
7354 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7356 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7362 /* Move a minipool fix MP from its current location to before MAX_MP.
7363 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7364 constraints may need updating. */
7366 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7367 HOST_WIDE_INT max_address
)
7369 /* The code below assumes these are different. */
7370 gcc_assert (mp
!= max_mp
);
7374 if (max_address
< mp
->max_address
)
7375 mp
->max_address
= max_address
;
7379 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7380 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7382 mp
->max_address
= max_address
;
7384 /* Unlink MP from its current position. Since max_mp is non-null,
7385 mp->prev must be non-null. */
7386 mp
->prev
->next
= mp
->next
;
7387 if (mp
->next
!= NULL
)
7388 mp
->next
->prev
= mp
->prev
;
7390 minipool_vector_tail
= mp
->prev
;
7392 /* Re-insert it before MAX_MP. */
7394 mp
->prev
= max_mp
->prev
;
7397 if (mp
->prev
!= NULL
)
7398 mp
->prev
->next
= mp
;
7400 minipool_vector_head
= mp
;
7403 /* Save the new entry. */
7406 /* Scan over the preceding entries and adjust their addresses as
7408 while (mp
->prev
!= NULL
7409 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7411 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7418 /* Add a constant to the minipool for a forward reference. Returns the
7419 node added or NULL if the constant will not fit in this pool. */
7421 add_minipool_forward_ref (Mfix
*fix
)
7423 /* If set, max_mp is the first pool_entry that has a lower
7424 constraint than the one we are trying to add. */
7425 Mnode
* max_mp
= NULL
;
7426 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
7429 /* If this fix's address is greater than the address of the first
7430 entry, then we can't put the fix in this pool. We subtract the
7431 size of the current fix to ensure that if the table is fully
7432 packed we still have enough room to insert this value by shuffling
7433 the other fixes forwards. */
7434 if (minipool_vector_head
&&
7435 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7438 /* Scan the pool to see if a constant with the same value has
7439 already been added. While we are doing this, also note the
7440 location where we must insert the constant if it doesn't already
7442 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7444 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7445 && fix
->mode
== mp
->mode
7446 && (GET_CODE (fix
->value
) != CODE_LABEL
7447 || (CODE_LABEL_NUMBER (fix
->value
)
7448 == CODE_LABEL_NUMBER (mp
->value
)))
7449 && rtx_equal_p (fix
->value
, mp
->value
))
7451 /* More than one fix references this entry. */
7453 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7456 /* Note the insertion point if necessary. */
7458 && mp
->max_address
> max_address
)
7461 /* If we are inserting an 8-bytes aligned quantity and
7462 we have not already found an insertion point, then
7463 make sure that all such 8-byte aligned quantities are
7464 placed at the start of the pool. */
7465 if (ARM_DOUBLEWORD_ALIGN
7467 && fix
->fix_size
== 8
7468 && mp
->fix_size
!= 8)
7471 max_address
= mp
->max_address
;
7475 /* The value is not currently in the minipool, so we need to create
7476 a new entry for it. If MAX_MP is NULL, the entry will be put on
7477 the end of the list since the placement is less constrained than
7478 any existing entry. Otherwise, we insert the new fix before
7479 MAX_MP and, if necessary, adjust the constraints on the other
7482 mp
->fix_size
= fix
->fix_size
;
7483 mp
->mode
= fix
->mode
;
7484 mp
->value
= fix
->value
;
7486 /* Not yet required for a backwards ref. */
7487 mp
->min_address
= -65536;
7491 mp
->max_address
= max_address
;
7493 mp
->prev
= minipool_vector_tail
;
7495 if (mp
->prev
== NULL
)
7497 minipool_vector_head
= mp
;
7498 minipool_vector_label
= gen_label_rtx ();
7501 mp
->prev
->next
= mp
;
7503 minipool_vector_tail
= mp
;
7507 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7508 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7510 mp
->max_address
= max_address
;
7513 mp
->prev
= max_mp
->prev
;
7515 if (mp
->prev
!= NULL
)
7516 mp
->prev
->next
= mp
;
7518 minipool_vector_head
= mp
;
7521 /* Save the new entry. */
7524 /* Scan over the preceding entries and adjust their addresses as
7526 while (mp
->prev
!= NULL
7527 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7529 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7537 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7538 HOST_WIDE_INT min_address
)
7540 HOST_WIDE_INT offset
;
7542 /* The code below assumes these are different. */
7543 gcc_assert (mp
!= min_mp
);
7547 if (min_address
> mp
->min_address
)
7548 mp
->min_address
= min_address
;
7552 /* We will adjust this below if it is too loose. */
7553 mp
->min_address
= min_address
;
7555 /* Unlink MP from its current position. Since min_mp is non-null,
7556 mp->next must be non-null. */
7557 mp
->next
->prev
= mp
->prev
;
7558 if (mp
->prev
!= NULL
)
7559 mp
->prev
->next
= mp
->next
;
7561 minipool_vector_head
= mp
->next
;
7563 /* Reinsert it after MIN_MP. */
7565 mp
->next
= min_mp
->next
;
7567 if (mp
->next
!= NULL
)
7568 mp
->next
->prev
= mp
;
7570 minipool_vector_tail
= mp
;
7576 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7578 mp
->offset
= offset
;
7579 if (mp
->refcount
> 0)
7580 offset
+= mp
->fix_size
;
7582 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7583 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7589 /* Add a constant to the minipool for a backward reference. Returns the
7590 node added or NULL if the constant will not fit in this pool.
7592 Note that the code for insertion for a backwards reference can be
7593 somewhat confusing because the calculated offsets for each fix do
7594 not take into account the size of the pool (which is still under
7597 add_minipool_backward_ref (Mfix
*fix
)
7599 /* If set, min_mp is the last pool_entry that has a lower constraint
7600 than the one we are trying to add. */
7601 Mnode
*min_mp
= NULL
;
7602 /* This can be negative, since it is only a constraint. */
7603 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7606 /* If we can't reach the current pool from this insn, or if we can't
7607 insert this entry at the end of the pool without pushing other
7608 fixes out of range, then we don't try. This ensures that we
7609 can't fail later on. */
7610 if (min_address
>= minipool_barrier
->address
7611 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7612 >= minipool_barrier
->address
))
7615 /* Scan the pool to see if a constant with the same value has
7616 already been added. While we are doing this, also note the
7617 location where we must insert the constant if it doesn't already
7619 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7621 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7622 && fix
->mode
== mp
->mode
7623 && (GET_CODE (fix
->value
) != CODE_LABEL
7624 || (CODE_LABEL_NUMBER (fix
->value
)
7625 == CODE_LABEL_NUMBER (mp
->value
)))
7626 && rtx_equal_p (fix
->value
, mp
->value
)
7627 /* Check that there is enough slack to move this entry to the
7628 end of the table (this is conservative). */
7630 > (minipool_barrier
->address
7631 + minipool_vector_tail
->offset
7632 + minipool_vector_tail
->fix_size
)))
7635 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7639 mp
->min_address
+= fix
->fix_size
;
7642 /* Note the insertion point if necessary. */
7643 if (mp
->min_address
< min_address
)
7645 /* For now, we do not allow the insertion of 8-byte alignment
7646 requiring nodes anywhere but at the start of the pool. */
7647 if (ARM_DOUBLEWORD_ALIGN
7648 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7653 else if (mp
->max_address
7654 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7656 /* Inserting before this entry would push the fix beyond
7657 its maximum address (which can happen if we have
7658 re-located a forwards fix); force the new fix to come
7661 min_address
= mp
->min_address
+ fix
->fix_size
;
7663 /* If we are inserting an 8-bytes aligned quantity and
7664 we have not already found an insertion point, then
7665 make sure that all such 8-byte aligned quantities are
7666 placed at the start of the pool. */
7667 else if (ARM_DOUBLEWORD_ALIGN
7669 && fix
->fix_size
== 8
7670 && mp
->fix_size
< 8)
7673 min_address
= mp
->min_address
+ fix
->fix_size
;
7678 /* We need to create a new entry. */
7680 mp
->fix_size
= fix
->fix_size
;
7681 mp
->mode
= fix
->mode
;
7682 mp
->value
= fix
->value
;
7684 mp
->max_address
= minipool_barrier
->address
+ 65536;
7686 mp
->min_address
= min_address
;
7691 mp
->next
= minipool_vector_head
;
7693 if (mp
->next
== NULL
)
7695 minipool_vector_tail
= mp
;
7696 minipool_vector_label
= gen_label_rtx ();
7699 mp
->next
->prev
= mp
;
7701 minipool_vector_head
= mp
;
7705 mp
->next
= min_mp
->next
;
7709 if (mp
->next
!= NULL
)
7710 mp
->next
->prev
= mp
;
7712 minipool_vector_tail
= mp
;
7715 /* Save the new entry. */
7723 /* Scan over the following entries and adjust their offsets. */
7724 while (mp
->next
!= NULL
)
7726 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7727 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7730 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7732 mp
->next
->offset
= mp
->offset
;
7741 assign_minipool_offsets (Mfix
*barrier
)
7743 HOST_WIDE_INT offset
= 0;
7746 minipool_barrier
= barrier
;
7748 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7750 mp
->offset
= offset
;
7752 if (mp
->refcount
> 0)
7753 offset
+= mp
->fix_size
;
7757 /* Output the literal table */
7759 dump_minipool (rtx scan
)
7765 if (ARM_DOUBLEWORD_ALIGN
)
7766 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7767 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7775 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7776 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7778 scan
= emit_label_after (gen_label_rtx (), scan
);
7779 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7780 scan
= emit_label_after (minipool_vector_label
, scan
);
7782 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7784 if (mp
->refcount
> 0)
7789 ";; Offset %u, min %ld, max %ld ",
7790 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7791 (unsigned long) mp
->max_address
);
7792 arm_print_value (dump_file
, mp
->value
);
7793 fputc ('\n', dump_file
);
7796 switch (mp
->fix_size
)
7798 #ifdef HAVE_consttable_1
7800 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7804 #ifdef HAVE_consttable_2
7806 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7810 #ifdef HAVE_consttable_4
7812 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7816 #ifdef HAVE_consttable_8
7818 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7831 minipool_vector_head
= minipool_vector_tail
= NULL
;
7832 scan
= emit_insn_after (gen_consttable_end (), scan
);
7833 scan
= emit_barrier_after (scan
);
7836 /* Return the cost of forcibly inserting a barrier after INSN. */
7838 arm_barrier_cost (rtx insn
)
7840 /* Basing the location of the pool on the loop depth is preferable,
7841 but at the moment, the basic block information seems to be
7842 corrupt by this stage of the compilation. */
7844 rtx next
= next_nonnote_insn (insn
);
7846 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7849 switch (GET_CODE (insn
))
7852 /* It will always be better to place the table before the label, rather
7861 return base_cost
- 10;
7864 return base_cost
+ 10;
7868 /* Find the best place in the insn stream in the range
7869 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7870 Create the barrier by inserting a jump and add a new fix entry for
7873 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7875 HOST_WIDE_INT count
= 0;
7877 rtx from
= fix
->insn
;
7878 rtx selected
= from
;
7880 HOST_WIDE_INT selected_address
;
7882 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7883 rtx label
= gen_label_rtx ();
7885 selected_cost
= arm_barrier_cost (from
);
7886 selected_address
= fix
->address
;
7888 while (from
&& count
< max_count
)
7893 /* This code shouldn't have been called if there was a natural barrier
7895 gcc_assert (GET_CODE (from
) != BARRIER
);
7897 /* Count the length of this insn. */
7898 count
+= get_attr_length (from
);
7900 /* If there is a jump table, add its length. */
7901 tmp
= is_jump_table (from
);
7904 count
+= get_jump_table_size (tmp
);
7906 /* Jump tables aren't in a basic block, so base the cost on
7907 the dispatch insn. If we select this location, we will
7908 still put the pool after the table. */
7909 new_cost
= arm_barrier_cost (from
);
7911 if (count
< max_count
&& new_cost
<= selected_cost
)
7914 selected_cost
= new_cost
;
7915 selected_address
= fix
->address
+ count
;
7918 /* Continue after the dispatch table. */
7919 from
= NEXT_INSN (tmp
);
7923 new_cost
= arm_barrier_cost (from
);
7925 if (count
< max_count
&& new_cost
<= selected_cost
)
7928 selected_cost
= new_cost
;
7929 selected_address
= fix
->address
+ count
;
7932 from
= NEXT_INSN (from
);
7935 /* Create a new JUMP_INSN that branches around a barrier. */
7936 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7937 JUMP_LABEL (from
) = label
;
7938 barrier
= emit_barrier_after (from
);
7939 emit_label_after (label
, barrier
);
7941 /* Create a minipool barrier entry for the new barrier. */
7942 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7943 new_fix
->insn
= barrier
;
7944 new_fix
->address
= selected_address
;
7945 new_fix
->next
= fix
->next
;
7946 fix
->next
= new_fix
;
7951 /* Record that there is a natural barrier in the insn stream at
7954 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7956 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7959 fix
->address
= address
;
7962 if (minipool_fix_head
!= NULL
)
7963 minipool_fix_tail
->next
= fix
;
7965 minipool_fix_head
= fix
;
7967 minipool_fix_tail
= fix
;
7970 /* Record INSN, which will need fixing up to load a value from the
7971 minipool. ADDRESS is the offset of the insn since the start of the
7972 function; LOC is a pointer to the part of the insn which requires
7973 fixing; VALUE is the constant that must be loaded, which is of type
7976 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7977 enum machine_mode mode
, rtx value
)
7979 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7981 #ifdef AOF_ASSEMBLER
7982 /* PIC symbol references need to be converted into offsets into the
7984 /* XXX This shouldn't be done here. */
7985 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7986 value
= aof_pic_entry (value
);
7987 #endif /* AOF_ASSEMBLER */
7990 fix
->address
= address
;
7993 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7995 fix
->forwards
= get_attr_pool_range (insn
);
7996 fix
->backwards
= get_attr_neg_pool_range (insn
);
7997 fix
->minipool
= NULL
;
7999 /* If an insn doesn't have a range defined for it, then it isn't
8000 expecting to be reworked by this code. Better to stop now than
8001 to generate duff assembly code. */
8002 gcc_assert (fix
->forwards
|| fix
->backwards
);
8004 /* If an entry requires 8-byte alignment then assume all constant pools
8005 require 4 bytes of padding. Trying to do this later on a per-pool
8006 basis is awkward because existing pool entries have to be modified. */
8007 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
8013 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8014 GET_MODE_NAME (mode
),
8015 INSN_UID (insn
), (unsigned long) address
,
8016 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
8017 arm_print_value (dump_file
, fix
->value
);
8018 fprintf (dump_file
, "\n");
8021 /* Add it to the chain of fixes. */
8024 if (minipool_fix_head
!= NULL
)
8025 minipool_fix_tail
->next
= fix
;
8027 minipool_fix_head
= fix
;
8029 minipool_fix_tail
= fix
;
8032 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8033 Returns the number of insns needed, or 99 if we don't know how to
8036 arm_const_double_inline_cost (rtx val
)
8038 rtx lowpart
, highpart
;
8039 enum machine_mode mode
;
8041 mode
= GET_MODE (val
);
8043 if (mode
== VOIDmode
)
8046 gcc_assert (GET_MODE_SIZE (mode
) == 8);
8048 lowpart
= gen_lowpart (SImode
, val
);
8049 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8051 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8052 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8054 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8055 NULL_RTX
, NULL_RTX
, 0, 0)
8056 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8057 NULL_RTX
, NULL_RTX
, 0, 0));
8060 /* Return true if it is worthwhile to split a 64-bit constant into two
8061 32-bit operations. This is the case if optimizing for size, or
8062 if we have load delay slots, or if one 32-bit part can be done with
8063 a single data operation. */
8065 arm_const_double_by_parts (rtx val
)
8067 enum machine_mode mode
= GET_MODE (val
);
8070 if (optimize_size
|| arm_ld_sched
)
8073 if (mode
== VOIDmode
)
8076 part
= gen_highpart_mode (SImode
, mode
, val
);
8078 gcc_assert (GET_CODE (part
) == CONST_INT
);
8080 if (const_ok_for_arm (INTVAL (part
))
8081 || const_ok_for_arm (~INTVAL (part
)))
8084 part
= gen_lowpart (SImode
, val
);
8086 gcc_assert (GET_CODE (part
) == CONST_INT
);
8088 if (const_ok_for_arm (INTVAL (part
))
8089 || const_ok_for_arm (~INTVAL (part
)))
8095 /* Scan INSN and note any of its operands that need fixing.
8096 If DO_PUSHES is false we do not actually push any of the fixups
8097 needed. The function returns TRUE if any fixups were needed/pushed.
8098 This is used by arm_memory_load_p() which needs to know about loads
8099 of constants that will be converted into minipool loads. */
8101 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8103 bool result
= false;
8106 extract_insn (insn
);
8108 if (!constrain_operands (1))
8109 fatal_insn_not_found (insn
);
8111 if (recog_data
.n_alternatives
== 0)
8114 /* Fill in recog_op_alt with information about the constraints of
8116 preprocess_constraints ();
8118 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8120 /* Things we need to fix can only occur in inputs. */
8121 if (recog_data
.operand_type
[opno
] != OP_IN
)
8124 /* If this alternative is a memory reference, then any mention
8125 of constants in this alternative is really to fool reload
8126 into allowing us to accept one there. We need to fix them up
8127 now so that we output the right code. */
8128 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8130 rtx op
= recog_data
.operand
[opno
];
8132 if (CONSTANT_P (op
))
8135 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8136 recog_data
.operand_mode
[opno
], op
);
8139 else if (GET_CODE (op
) == MEM
8140 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8141 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8145 rtx cop
= avoid_constant_pool_reference (op
);
8147 /* Casting the address of something to a mode narrower
8148 than a word can cause avoid_constant_pool_reference()
8149 to return the pool reference itself. That's no good to
8150 us here. Lets just hope that we can use the
8151 constant pool value directly. */
8153 cop
= get_pool_constant (XEXP (op
, 0));
8155 push_minipool_fix (insn
, address
,
8156 recog_data
.operand_loc
[opno
],
8157 recog_data
.operand_mode
[opno
], cop
);
8168 /* Gcc puts the pool in the wrong place for ARM, since we can only
8169 load addresses a limited distance around the pc. We do some
8170 special munging to move the constant pool values to the correct
8171 point in the code. */
8176 HOST_WIDE_INT address
= 0;
8179 minipool_fix_head
= minipool_fix_tail
= NULL
;
8181 /* The first insn must always be a note, or the code below won't
8182 scan it properly. */
8183 insn
= get_insns ();
8184 gcc_assert (GET_CODE (insn
) == NOTE
);
8187 /* Scan all the insns and record the operands that will need fixing. */
8188 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8190 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8191 && (arm_cirrus_insn_p (insn
)
8192 || GET_CODE (insn
) == JUMP_INSN
8193 || arm_memory_load_p (insn
)))
8194 cirrus_reorg (insn
);
8196 if (GET_CODE (insn
) == BARRIER
)
8197 push_minipool_barrier (insn
, address
);
8198 else if (INSN_P (insn
))
8202 note_invalid_constants (insn
, address
, true);
8203 address
+= get_attr_length (insn
);
8205 /* If the insn is a vector jump, add the size of the table
8206 and skip the table. */
8207 if ((table
= is_jump_table (insn
)) != NULL
)
8209 address
+= get_jump_table_size (table
);
8215 fix
= minipool_fix_head
;
8217 /* Now scan the fixups and perform the required changes. */
8222 Mfix
* last_added_fix
;
8223 Mfix
* last_barrier
= NULL
;
8226 /* Skip any further barriers before the next fix. */
8227 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8230 /* No more fixes. */
8234 last_added_fix
= NULL
;
8236 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8238 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8240 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8243 last_barrier
= ftmp
;
8245 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8248 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8251 /* If we found a barrier, drop back to that; any fixes that we
8252 could have reached but come after the barrier will now go in
8253 the next mini-pool. */
8254 if (last_barrier
!= NULL
)
8256 /* Reduce the refcount for those fixes that won't go into this
8258 for (fdel
= last_barrier
->next
;
8259 fdel
&& fdel
!= ftmp
;
8262 fdel
->minipool
->refcount
--;
8263 fdel
->minipool
= NULL
;
8266 ftmp
= last_barrier
;
8270 /* ftmp is first fix that we can't fit into this pool and
8271 there no natural barriers that we could use. Insert a
8272 new barrier in the code somewhere between the previous
8273 fix and this one, and arrange to jump around it. */
8274 HOST_WIDE_INT max_address
;
8276 /* The last item on the list of fixes must be a barrier, so
8277 we can never run off the end of the list of fixes without
8278 last_barrier being set. */
8281 max_address
= minipool_vector_head
->max_address
;
8282 /* Check that there isn't another fix that is in range that
8283 we couldn't fit into this pool because the pool was
8284 already too large: we need to put the pool before such an
8286 if (ftmp
->address
< max_address
)
8287 max_address
= ftmp
->address
;
8289 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8292 assign_minipool_offsets (last_barrier
);
8296 if (GET_CODE (ftmp
->insn
) != BARRIER
8297 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8304 /* Scan over the fixes we have identified for this pool, fixing them
8305 up and adding the constants to the pool itself. */
8306 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8307 this_fix
= this_fix
->next
)
8308 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8311 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8312 minipool_vector_label
),
8313 this_fix
->minipool
->offset
);
8314 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8317 dump_minipool (last_barrier
->insn
);
8321 /* From now on we must synthesize any constants that we can't handle
8322 directly. This can happen if the RTL gets split during final
8323 instruction generation. */
8324 after_arm_reorg
= 1;
8326 /* Free the minipool memory. */
8327 obstack_free (&minipool_obstack
, minipool_startobj
);
8330 /* Routines to output assembly language. */
8332 /* If the rtx is the correct value then return the string of the number.
8333 In this way we can ensure that valid double constants are generated even
8334 when cross compiling. */
8336 fp_immediate_constant (rtx x
)
8341 if (!fp_consts_inited
)
8344 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8345 for (i
= 0; i
< 8; i
++)
8346 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8347 return strings_fp
[i
];
8352 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8354 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8358 if (!fp_consts_inited
)
8361 for (i
= 0; i
< 8; i
++)
8362 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8363 return strings_fp
[i
];
8368 /* Output the operands of a LDM/STM instruction to STREAM.
8369 MASK is the ARM register set mask of which only bits 0-15 are important.
8370 REG is the base register, either the frame pointer or the stack pointer,
8371 INSTR is the possibly suffixed load or store instruction. */
8374 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8378 bool not_first
= FALSE
;
8380 fputc ('\t', stream
);
8381 asm_fprintf (stream
, instr
, reg
);
8382 fputs (", {", stream
);
8384 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8385 if (mask
& (1 << i
))
8388 fprintf (stream
, ", ");
8390 asm_fprintf (stream
, "%r", i
);
8394 fprintf (stream
, "}\n");
8398 /* Output a FLDMX instruction to STREAM.
8399 BASE if the register containing the address.
8400 REG and COUNT specify the register range.
8401 Extra registers may be added to avoid hardware bugs. */
8404 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8408 /* Workaround ARM10 VFPr1 bug. */
8409 if (count
== 2 && !arm_arch6
)
8416 fputc ('\t', stream
);
8417 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8419 for (i
= reg
; i
< reg
+ count
; i
++)
8422 fputs (", ", stream
);
8423 asm_fprintf (stream
, "d%d", i
);
8425 fputs ("}\n", stream
);
8430 /* Output the assembly for a store multiple. */
8433 vfp_output_fstmx (rtx
* operands
)
8440 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8441 p
= strlen (pattern
);
8443 gcc_assert (GET_CODE (operands
[1]) == REG
);
8445 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8446 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8448 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8450 strcpy (&pattern
[p
], "}");
8452 output_asm_insn (pattern
, operands
);
8457 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8458 number of bytes pushed. */
8461 vfp_emit_fstmx (int base_reg
, int count
)
8468 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8469 register pairs are stored by a store multiple insn. We avoid this
8470 by pushing an extra pair. */
8471 if (count
== 2 && !arm_arch6
)
8473 if (base_reg
== LAST_VFP_REGNUM
- 3)
8478 /* ??? The frame layout is implementation defined. We describe
8479 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8480 We really need some way of representing the whole block so that the
8481 unwinder can figure it out at runtime. */
8482 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8483 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8485 reg
= gen_rtx_REG (DFmode
, base_reg
);
8489 = gen_rtx_SET (VOIDmode
,
8490 gen_frame_mem (BLKmode
,
8491 gen_rtx_PRE_DEC (BLKmode
,
8492 stack_pointer_rtx
)),
8493 gen_rtx_UNSPEC (BLKmode
,
8497 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8498 plus_constant (stack_pointer_rtx
, -(count
* 8 + 4)));
8499 RTX_FRAME_RELATED_P (tmp
) = 1;
8500 XVECEXP (dwarf
, 0, 0) = tmp
;
8502 tmp
= gen_rtx_SET (VOIDmode
,
8503 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8505 RTX_FRAME_RELATED_P (tmp
) = 1;
8506 XVECEXP (dwarf
, 0, 1) = tmp
;
8508 for (i
= 1; i
< count
; i
++)
8510 reg
= gen_rtx_REG (DFmode
, base_reg
);
8512 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8514 tmp
= gen_rtx_SET (VOIDmode
,
8515 gen_frame_mem (DFmode
,
8516 plus_constant (stack_pointer_rtx
,
8519 RTX_FRAME_RELATED_P (tmp
) = 1;
8520 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8523 par
= emit_insn (par
);
8524 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8526 RTX_FRAME_RELATED_P (par
) = 1;
8528 return count
* 8 + 4;
8532 /* Output a 'call' insn. */
8534 output_call (rtx
*operands
)
8536 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8538 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8539 if (REGNO (operands
[0]) == LR_REGNUM
)
8541 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8542 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8545 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8547 if (TARGET_INTERWORK
|| arm_arch4t
)
8548 output_asm_insn ("bx%?\t%0", operands
);
8550 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8555 /* Output a 'call' insn that is a reference in memory. */
8557 output_call_mem (rtx
*operands
)
8559 if (TARGET_INTERWORK
&& !arm_arch5
)
8561 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8562 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8563 output_asm_insn ("bx%?\t%|ip", operands
);
8565 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8567 /* LR is used in the memory address. We load the address in the
8568 first instruction. It's safe to use IP as the target of the
8569 load since the call will kill it anyway. */
8570 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8572 output_asm_insn ("blx%?\t%|ip", operands
);
8575 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8577 output_asm_insn ("bx%?\t%|ip", operands
);
8579 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8584 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8585 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8592 /* Output a move from arm registers to an fpa registers.
8593 OPERANDS[0] is an fpa register.
8594 OPERANDS[1] is the first registers of an arm register pair. */
8596 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8598 int arm_reg0
= REGNO (operands
[1]);
8601 gcc_assert (arm_reg0
!= IP_REGNUM
);
8603 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8604 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8605 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8607 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8608 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8613 /* Output a move from an fpa register to arm registers.
8614 OPERANDS[0] is the first registers of an arm register pair.
8615 OPERANDS[1] is an fpa register. */
8617 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8619 int arm_reg0
= REGNO (operands
[0]);
8622 gcc_assert (arm_reg0
!= IP_REGNUM
);
8624 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8625 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8626 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8628 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8629 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8633 /* Output a move from arm registers to arm registers of a long double
8634 OPERANDS[0] is the destination.
8635 OPERANDS[1] is the source. */
8637 output_mov_long_double_arm_from_arm (rtx
*operands
)
8639 /* We have to be careful here because the two might overlap. */
8640 int dest_start
= REGNO (operands
[0]);
8641 int src_start
= REGNO (operands
[1]);
8645 if (dest_start
< src_start
)
8647 for (i
= 0; i
< 3; i
++)
8649 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8650 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8651 output_asm_insn ("mov%?\t%0, %1", ops
);
8656 for (i
= 2; i
>= 0; i
--)
8658 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8659 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8660 output_asm_insn ("mov%?\t%0, %1", ops
);
8668 /* Output a move from arm registers to an fpa registers.
8669 OPERANDS[0] is an fpa register.
8670 OPERANDS[1] is the first registers of an arm register pair. */
8672 output_mov_double_fpa_from_arm (rtx
*operands
)
8674 int arm_reg0
= REGNO (operands
[1]);
8677 gcc_assert (arm_reg0
!= IP_REGNUM
);
8679 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8680 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8681 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8682 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8686 /* Output a move from an fpa register to arm registers.
8687 OPERANDS[0] is the first registers of an arm register pair.
8688 OPERANDS[1] is an fpa register. */
8690 output_mov_double_arm_from_fpa (rtx
*operands
)
8692 int arm_reg0
= REGNO (operands
[0]);
8695 gcc_assert (arm_reg0
!= IP_REGNUM
);
8697 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8698 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8699 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8700 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8704 /* Output a move between double words.
8705 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8706 or MEM<-REG and all MEMs must be offsettable addresses. */
8708 output_move_double (rtx
*operands
)
8710 enum rtx_code code0
= GET_CODE (operands
[0]);
8711 enum rtx_code code1
= GET_CODE (operands
[1]);
8716 int reg0
= REGNO (operands
[0]);
8718 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8720 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8722 switch (GET_CODE (XEXP (operands
[1], 0)))
8725 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8729 gcc_assert (TARGET_LDRD
);
8730 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8734 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8738 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8742 gcc_assert (TARGET_LDRD
);
8743 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8748 otherops
[0] = operands
[0];
8749 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8750 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8752 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8754 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8756 /* Registers overlap so split out the increment. */
8757 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8758 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8761 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8765 /* We only allow constant increments, so this is safe. */
8766 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8772 output_asm_insn ("adr%?\t%0, %1", operands
);
8773 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8777 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8778 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8780 otherops
[0] = operands
[0];
8781 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8782 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8784 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8786 if (GET_CODE (otherops
[2]) == CONST_INT
)
8788 switch ((int) INTVAL (otherops
[2]))
8791 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8794 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8797 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8802 && (GET_CODE (otherops
[2]) == REG
8803 || (GET_CODE (otherops
[2]) == CONST_INT
8804 && INTVAL (otherops
[2]) > -256
8805 && INTVAL (otherops
[2]) < 256)))
8807 if (reg_overlap_mentioned_p (otherops
[0],
8810 /* Swap base and index registers over to
8811 avoid a conflict. */
8812 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8813 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8815 /* If both registers conflict, it will usually
8816 have been fixed by a splitter. */
8817 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8819 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8820 output_asm_insn ("ldr%?d\t%0, [%1]",
8824 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8828 if (GET_CODE (otherops
[2]) == CONST_INT
)
8830 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8831 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8833 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8836 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8839 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8841 return "ldm%?ia\t%0, %M0";
8845 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8846 /* Take care of overlapping base/data reg. */
8847 if (reg_mentioned_p (operands
[0], operands
[1]))
8849 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8850 output_asm_insn ("ldr%?\t%0, %1", operands
);
8854 output_asm_insn ("ldr%?\t%0, %1", operands
);
8855 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8862 /* Constraints should ensure this. */
8863 gcc_assert (code0
== MEM
&& code1
== REG
);
8864 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8866 switch (GET_CODE (XEXP (operands
[0], 0)))
8869 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8873 gcc_assert (TARGET_LDRD
);
8874 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8878 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8882 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8886 gcc_assert (TARGET_LDRD
);
8887 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8892 otherops
[0] = operands
[1];
8893 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8894 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8896 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8897 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8899 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8903 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8904 if (GET_CODE (otherops
[2]) == CONST_INT
)
8906 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8909 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8913 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8917 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8922 && (GET_CODE (otherops
[2]) == REG
8923 || (GET_CODE (otherops
[2]) == CONST_INT
8924 && INTVAL (otherops
[2]) > -256
8925 && INTVAL (otherops
[2]) < 256)))
8927 otherops
[0] = operands
[1];
8928 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8929 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8935 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8936 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8937 output_asm_insn ("str%?\t%1, %0", operands
);
8938 output_asm_insn ("str%?\t%1, %0", otherops
);
8945 /* Output an ADD r, s, #n where n may be too big for one instruction.
8946 If adding zero to one register, output nothing. */
8948 output_add_immediate (rtx
*operands
)
8950 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8952 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8955 output_multi_immediate (operands
,
8956 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8959 output_multi_immediate (operands
,
8960 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8967 /* Output a multiple immediate operation.
8968 OPERANDS is the vector of operands referred to in the output patterns.
8969 INSTR1 is the output pattern to use for the first constant.
8970 INSTR2 is the output pattern to use for subsequent constants.
8971 IMMED_OP is the index of the constant slot in OPERANDS.
8972 N is the constant value. */
8974 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8975 int immed_op
, HOST_WIDE_INT n
)
8977 #if HOST_BITS_PER_WIDE_INT > 32
8983 /* Quick and easy output. */
8984 operands
[immed_op
] = const0_rtx
;
8985 output_asm_insn (instr1
, operands
);
8990 const char * instr
= instr1
;
8992 /* Note that n is never zero here (which would give no output). */
8993 for (i
= 0; i
< 32; i
+= 2)
8997 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8998 output_asm_insn (instr
, operands
);
9008 /* Return the appropriate ARM instruction for the operation code.
9009 The returned result should not be overwritten. OP is the rtx of the
9010 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9013 arithmetic_instr (rtx op
, int shift_first_arg
)
9015 switch (GET_CODE (op
))
9021 return shift_first_arg
? "rsb" : "sub";
9037 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9038 for the operation code. The returned result should not be overwritten.
9039 OP is the rtx code of the shift.
9040 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9043 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
9046 enum rtx_code code
= GET_CODE (op
);
9048 switch (GET_CODE (XEXP (op
, 1)))
9056 *amountp
= INTVAL (XEXP (op
, 1));
9078 gcc_assert (*amountp
!= -1);
9079 *amountp
= 32 - *amountp
;
9088 /* We never have to worry about the amount being other than a
9089 power of 2, since this case can never be reloaded from a reg. */
9090 gcc_assert (*amountp
!= -1);
9091 *amountp
= int_log2 (*amountp
);
9100 /* This is not 100% correct, but follows from the desire to merge
9101 multiplication by a power of 2 with the recognizer for a
9102 shift. >=32 is not a valid shift for "asl", so we must try and
9103 output a shift that produces the correct arithmetical result.
9104 Using lsr #32 is identical except for the fact that the carry bit
9105 is not set correctly if we set the flags; but we never use the
9106 carry bit from such an operation, so we can ignore that. */
9107 if (code
== ROTATERT
)
9108 /* Rotate is just modulo 32. */
9110 else if (*amountp
!= (*amountp
& 31))
9117 /* Shifts of 0 are no-ops. */
9125 /* Obtain the shift from the POWER of two. */
9127 static HOST_WIDE_INT
9128 int_log2 (HOST_WIDE_INT power
)
9130 HOST_WIDE_INT shift
= 0;
9132 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9134 gcc_assert (shift
<= 31);
9141 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9142 because /bin/as is horribly restrictive. The judgement about
9143 whether or not each character is 'printable' (and can be output as
9144 is) or not (and must be printed with an octal escape) must be made
9145 with reference to the *host* character set -- the situation is
9146 similar to that discussed in the comments above pp_c_char in
9147 c-pretty-print.c. */
9149 #define MAX_ASCII_LEN 51
9152 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9157 fputs ("\t.ascii\t\"", stream
);
9159 for (i
= 0; i
< len
; i
++)
9163 if (len_so_far
>= MAX_ASCII_LEN
)
9165 fputs ("\"\n\t.ascii\t\"", stream
);
9171 if (c
== '\\' || c
== '\"')
9173 putc ('\\', stream
);
9181 fprintf (stream
, "\\%03o", c
);
9186 fputs ("\"\n", stream
);
9189 /* Compute the register save mask for registers 0 through 12
9190 inclusive. This code is used by arm_compute_save_reg_mask. */
9192 static unsigned long
9193 arm_compute_save_reg0_reg12_mask (void)
9195 unsigned long func_type
= arm_current_func_type ();
9196 unsigned long save_reg_mask
= 0;
9199 if (IS_INTERRUPT (func_type
))
9201 unsigned int max_reg
;
9202 /* Interrupt functions must not corrupt any registers,
9203 even call clobbered ones. If this is a leaf function
9204 we can just examine the registers used by the RTL, but
9205 otherwise we have to assume that whatever function is
9206 called might clobber anything, and so we have to save
9207 all the call-clobbered registers as well. */
9208 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9209 /* FIQ handlers have registers r8 - r12 banked, so
9210 we only need to check r0 - r7, Normal ISRs only
9211 bank r14 and r15, so we must check up to r12.
9212 r13 is the stack pointer which is always preserved,
9213 so we do not need to consider it here. */
9218 for (reg
= 0; reg
<= max_reg
; reg
++)
9219 if (regs_ever_live
[reg
]
9220 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9221 save_reg_mask
|= (1 << reg
);
9223 /* Also save the pic base register if necessary. */
9225 && !TARGET_SINGLE_PIC_BASE
9226 && arm_pic_register
!= INVALID_REGNUM
9227 && current_function_uses_pic_offset_table
)
9228 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9232 /* In the normal case we only need to save those registers
9233 which are call saved and which are used by this function. */
9234 for (reg
= 0; reg
<= 10; reg
++)
9235 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9236 save_reg_mask
|= (1 << reg
);
9238 /* Handle the frame pointer as a special case. */
9239 if (! TARGET_APCS_FRAME
9240 && ! frame_pointer_needed
9241 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9242 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9243 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9245 /* If we aren't loading the PIC register,
9246 don't stack it even though it may be live. */
9248 && !TARGET_SINGLE_PIC_BASE
9249 && arm_pic_register
!= INVALID_REGNUM
9250 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9251 || current_function_uses_pic_offset_table
))
9252 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9255 /* Save registers so the exception handler can modify them. */
9256 if (current_function_calls_eh_return
)
9262 reg
= EH_RETURN_DATA_REGNO (i
);
9263 if (reg
== INVALID_REGNUM
)
9265 save_reg_mask
|= 1 << reg
;
9269 return save_reg_mask
;
9272 /* Compute a bit mask of which registers need to be
9273 saved on the stack for the current function. */
9275 static unsigned long
9276 arm_compute_save_reg_mask (void)
9278 unsigned int save_reg_mask
= 0;
9279 unsigned long func_type
= arm_current_func_type ();
9281 if (IS_NAKED (func_type
))
9282 /* This should never really happen. */
9285 /* If we are creating a stack frame, then we must save the frame pointer,
9286 IP (which will hold the old stack pointer), LR and the PC. */
9287 if (frame_pointer_needed
)
9289 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9294 /* Volatile functions do not return, so there
9295 is no need to save any other registers. */
9296 if (IS_VOLATILE (func_type
))
9297 return save_reg_mask
;
9299 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9301 /* Decide if we need to save the link register.
9302 Interrupt routines have their own banked link register,
9303 so they never need to save it.
9304 Otherwise if we do not use the link register we do not need to save
9305 it. If we are pushing other registers onto the stack however, we
9306 can save an instruction in the epilogue by pushing the link register
9307 now and then popping it back into the PC. This incurs extra memory
9308 accesses though, so we only do it when optimizing for size, and only
9309 if we know that we will not need a fancy return sequence. */
9310 if (regs_ever_live
[LR_REGNUM
]
9313 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9314 && !current_function_calls_eh_return
))
9315 save_reg_mask
|= 1 << LR_REGNUM
;
9317 if (cfun
->machine
->lr_save_eliminated
)
9318 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9320 if (TARGET_REALLY_IWMMXT
9321 && ((bit_count (save_reg_mask
)
9322 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9326 /* The total number of registers that are going to be pushed
9327 onto the stack is odd. We need to ensure that the stack
9328 is 64-bit aligned before we start to save iWMMXt registers,
9329 and also before we start to create locals. (A local variable
9330 might be a double or long long which we will load/store using
9331 an iWMMXt instruction). Therefore we need to push another
9332 ARM register, so that the stack will be 64-bit aligned. We
9333 try to avoid using the arg registers (r0 -r3) as they might be
9334 used to pass values in a tail call. */
9335 for (reg
= 4; reg
<= 12; reg
++)
9336 if ((save_reg_mask
& (1 << reg
)) == 0)
9340 save_reg_mask
|= (1 << reg
);
9343 cfun
->machine
->sibcall_blocked
= 1;
9344 save_reg_mask
|= (1 << 3);
9348 return save_reg_mask
;
9352 /* Compute a bit mask of which registers need to be
9353 saved on the stack for the current function. */
9354 static unsigned long
9355 thumb_compute_save_reg_mask (void)
9361 for (reg
= 0; reg
< 12; reg
++)
9362 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9366 && !TARGET_SINGLE_PIC_BASE
9367 && arm_pic_register
!= INVALID_REGNUM
9368 && current_function_uses_pic_offset_table
)
9369 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9371 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9372 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9373 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9375 /* LR will also be pushed if any lo regs are pushed. */
9376 if (mask
& 0xff || thumb_force_lr_save ())
9377 mask
|= (1 << LR_REGNUM
);
9379 /* Make sure we have a low work register if we need one.
9380 We will need one if we are going to push a high register,
9381 but we are not currently intending to push a low register. */
9382 if ((mask
& 0xff) == 0
9383 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9385 /* Use thumb_find_work_register to choose which register
9386 we will use. If the register is live then we will
9387 have to push it. Use LAST_LO_REGNUM as our fallback
9388 choice for the register to select. */
9389 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9391 if (! call_used_regs
[reg
])
9399 /* Return the number of bytes required to save VFP registers. */
9401 arm_get_vfp_saved_size (void)
9408 /* Space for saved VFP registers. */
9409 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9412 for (regno
= FIRST_VFP_REGNUM
;
9413 regno
< LAST_VFP_REGNUM
;
9416 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9417 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9421 /* Workaround ARM10 VFPr1 bug. */
9422 if (count
== 2 && !arm_arch6
)
9424 saved
+= count
* 8 + 4;
9433 if (count
== 2 && !arm_arch6
)
9435 saved
+= count
* 8 + 4;
9442 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9443 everything bar the final return instruction. */
9445 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9447 char conditional
[10];
9450 unsigned long live_regs_mask
;
9451 unsigned long func_type
;
9452 arm_stack_offsets
*offsets
;
9454 func_type
= arm_current_func_type ();
9456 if (IS_NAKED (func_type
))
9459 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9461 /* If this function was declared non-returning, and we have
9462 found a tail call, then we have to trust that the called
9463 function won't return. */
9468 /* Otherwise, trap an attempted return by aborting. */
9470 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9472 assemble_external_libcall (ops
[1]);
9473 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9479 gcc_assert (!current_function_calls_alloca
|| really_return
);
9481 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9483 return_used_this_function
= 1;
9485 live_regs_mask
= arm_compute_save_reg_mask ();
9489 const char * return_reg
;
9491 /* If we do not have any special requirements for function exit
9492 (e.g. interworking, or ISR) then we can load the return address
9493 directly into the PC. Otherwise we must load it into LR. */
9495 && ! TARGET_INTERWORK
)
9496 return_reg
= reg_names
[PC_REGNUM
];
9498 return_reg
= reg_names
[LR_REGNUM
];
9500 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9502 /* There are three possible reasons for the IP register
9503 being saved. 1) a stack frame was created, in which case
9504 IP contains the old stack pointer, or 2) an ISR routine
9505 corrupted it, or 3) it was saved to align the stack on
9506 iWMMXt. In case 1, restore IP into SP, otherwise just
9508 if (frame_pointer_needed
)
9510 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9511 live_regs_mask
|= (1 << SP_REGNUM
);
9514 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9517 /* On some ARM architectures it is faster to use LDR rather than
9518 LDM to load a single register. On other architectures, the
9519 cost is the same. In 26 bit mode, or for exception handlers,
9520 we have to use LDM to load the PC so that the CPSR is also
9522 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9523 if (live_regs_mask
== (1U << reg
))
9526 if (reg
<= LAST_ARM_REGNUM
9527 && (reg
!= LR_REGNUM
9529 || ! IS_INTERRUPT (func_type
)))
9531 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9532 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9539 /* Generate the load multiple instruction to restore the
9540 registers. Note we can get here, even if
9541 frame_pointer_needed is true, but only if sp already
9542 points to the base of the saved core registers. */
9543 if (live_regs_mask
& (1 << SP_REGNUM
))
9545 unsigned HOST_WIDE_INT stack_adjust
;
9547 offsets
= arm_get_frame_offsets ();
9548 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9549 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9551 if (stack_adjust
&& arm_arch5
)
9552 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9555 /* If we can't use ldmib (SA110 bug),
9556 then try to pop r3 instead. */
9558 live_regs_mask
|= 1 << 3;
9559 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9563 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9565 p
= instr
+ strlen (instr
);
9567 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9568 if (live_regs_mask
& (1 << reg
))
9570 int l
= strlen (reg_names
[reg
]);
9576 memcpy (p
, ", ", 2);
9580 memcpy (p
, "%|", 2);
9581 memcpy (p
+ 2, reg_names
[reg
], l
);
9585 if (live_regs_mask
& (1 << LR_REGNUM
))
9587 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9588 /* If returning from an interrupt, restore the CPSR. */
9589 if (IS_INTERRUPT (func_type
))
9596 output_asm_insn (instr
, & operand
);
9598 /* See if we need to generate an extra instruction to
9599 perform the actual function return. */
9601 && func_type
!= ARM_FT_INTERWORKED
9602 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9604 /* The return has already been handled
9605 by loading the LR into the PC. */
9612 switch ((int) ARM_FUNC_TYPE (func_type
))
9616 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9619 case ARM_FT_INTERWORKED
:
9620 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9623 case ARM_FT_EXCEPTION
:
9624 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9628 /* Use bx if it's available. */
9629 if (arm_arch5
|| arm_arch4t
)
9630 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9632 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9636 output_asm_insn (instr
, & operand
);
9642 /* Write the function name into the code section, directly preceding
9643 the function prologue.
9645 Code will be output similar to this:
9647 .ascii "arm_poke_function_name", 0
9650 .word 0xff000000 + (t1 - t0)
9651 arm_poke_function_name
9653 stmfd sp!, {fp, ip, lr, pc}
9656 When performing a stack backtrace, code can inspect the value
9657 of 'pc' stored at 'fp' + 0. If the trace function then looks
9658 at location pc - 12 and the top 8 bits are set, then we know
9659 that there is a function name embedded immediately preceding this
9660 location and has length ((pc[-3]) & 0xff000000).
9662 We assume that pc is declared as a pointer to an unsigned long.
9664 It is of no benefit to output the function name if we are assembling
9665 a leaf function. These function types will not contain a stack
9666 backtrace structure, therefore it is not possible to determine the
9669 arm_poke_function_name (FILE *stream
, const char *name
)
9671 unsigned long alignlength
;
9672 unsigned long length
;
9675 length
= strlen (name
) + 1;
9676 alignlength
= ROUND_UP_WORD (length
);
9678 ASM_OUTPUT_ASCII (stream
, name
, length
);
9679 ASM_OUTPUT_ALIGN (stream
, 2);
9680 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9681 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9684 /* Place some comments into the assembler stream
9685 describing the current function. */
9687 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9689 unsigned long func_type
;
9693 thumb_output_function_prologue (f
, frame_size
);
9698 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9700 func_type
= arm_current_func_type ();
9702 switch ((int) ARM_FUNC_TYPE (func_type
))
9707 case ARM_FT_INTERWORKED
:
9708 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9711 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9714 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9716 case ARM_FT_EXCEPTION
:
9717 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9721 if (IS_NAKED (func_type
))
9722 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9724 if (IS_VOLATILE (func_type
))
9725 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9727 if (IS_NESTED (func_type
))
9728 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9730 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9731 current_function_args_size
,
9732 current_function_pretend_args_size
, frame_size
);
9734 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9735 frame_pointer_needed
,
9736 cfun
->machine
->uses_anonymous_args
);
9738 if (cfun
->machine
->lr_save_eliminated
)
9739 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9741 if (current_function_calls_eh_return
)
9742 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9744 #ifdef AOF_ASSEMBLER
9746 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9749 return_used_this_function
= 0;
9753 arm_output_epilogue (rtx sibling
)
9756 unsigned long saved_regs_mask
;
9757 unsigned long func_type
;
9758 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9759 frame that is $fp + 4 for a non-variadic function. */
9760 int floats_offset
= 0;
9762 FILE * f
= asm_out_file
;
9763 unsigned int lrm_count
= 0;
9764 int really_return
= (sibling
== NULL
);
9766 arm_stack_offsets
*offsets
;
9768 /* If we have already generated the return instruction
9769 then it is futile to generate anything else. */
9770 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9773 func_type
= arm_current_func_type ();
9775 if (IS_NAKED (func_type
))
9776 /* Naked functions don't have epilogues. */
9779 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9783 /* A volatile function should never return. Call abort. */
9784 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9785 assemble_external_libcall (op
);
9786 output_asm_insn ("bl\t%a0", &op
);
9791 /* If we are throwing an exception, then we really must be doing a
9792 return, so we can't tail-call. */
9793 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9795 offsets
= arm_get_frame_offsets ();
9796 saved_regs_mask
= arm_compute_save_reg_mask ();
9799 lrm_count
= bit_count (saved_regs_mask
);
9801 floats_offset
= offsets
->saved_args
;
9802 /* Compute how far away the floats will be. */
9803 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9804 if (saved_regs_mask
& (1 << reg
))
9807 if (frame_pointer_needed
)
9809 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9810 int vfp_offset
= offsets
->frame
;
9812 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9814 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9815 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9817 floats_offset
+= 12;
9818 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9819 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9824 start_reg
= LAST_FPA_REGNUM
;
9826 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9828 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9830 floats_offset
+= 12;
9832 /* We can't unstack more than four registers at once. */
9833 if (start_reg
- reg
== 3)
9835 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9836 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9837 start_reg
= reg
- 1;
9842 if (reg
!= start_reg
)
9843 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9844 reg
+ 1, start_reg
- reg
,
9845 FP_REGNUM
, floats_offset
- vfp_offset
);
9846 start_reg
= reg
- 1;
9850 /* Just in case the last register checked also needs unstacking. */
9851 if (reg
!= start_reg
)
9852 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9853 reg
+ 1, start_reg
- reg
,
9854 FP_REGNUM
, floats_offset
- vfp_offset
);
9857 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9861 /* The fldmx insn does not have base+offset addressing modes,
9862 so we use IP to hold the address. */
9863 saved_size
= arm_get_vfp_saved_size ();
9867 floats_offset
+= saved_size
;
9868 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9869 FP_REGNUM
, floats_offset
- vfp_offset
);
9871 start_reg
= FIRST_VFP_REGNUM
;
9872 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9874 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9875 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9877 if (start_reg
!= reg
)
9878 arm_output_fldmx (f
, IP_REGNUM
,
9879 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9880 (reg
- start_reg
) / 2);
9881 start_reg
= reg
+ 2;
9884 if (start_reg
!= reg
)
9885 arm_output_fldmx (f
, IP_REGNUM
,
9886 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9887 (reg
- start_reg
) / 2);
9892 /* The frame pointer is guaranteed to be non-double-word aligned.
9893 This is because it is set to (old_stack_pointer - 4) and the
9894 old_stack_pointer was double word aligned. Thus the offset to
9895 the iWMMXt registers to be loaded must also be non-double-word
9896 sized, so that the resultant address *is* double-word aligned.
9897 We can ignore floats_offset since that was already included in
9898 the live_regs_mask. */
9899 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9901 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9902 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9904 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9905 reg
, FP_REGNUM
, lrm_count
* 4);
9910 /* saved_regs_mask should contain the IP, which at the time of stack
9911 frame generation actually contains the old stack pointer. So a
9912 quick way to unwind the stack is just pop the IP register directly
9913 into the stack pointer. */
9914 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9915 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9916 saved_regs_mask
|= (1 << SP_REGNUM
);
9918 /* There are two registers left in saved_regs_mask - LR and PC. We
9919 only need to restore the LR register (the return address), but to
9920 save time we can load it directly into the PC, unless we need a
9921 special function exit sequence, or we are not really returning. */
9923 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9924 && !current_function_calls_eh_return
)
9925 /* Delete the LR from the register mask, so that the LR on
9926 the stack is loaded into the PC in the register mask. */
9927 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9929 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9931 /* We must use SP as the base register, because SP is one of the
9932 registers being restored. If an interrupt or page fault
9933 happens in the ldm instruction, the SP might or might not
9934 have been restored. That would be bad, as then SP will no
9935 longer indicate the safe area of stack, and we can get stack
9936 corruption. Using SP as the base register means that it will
9937 be reset correctly to the original value, should an interrupt
9938 occur. If the stack pointer already points at the right
9939 place, then omit the subtraction. */
9940 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9941 || current_function_calls_alloca
)
9942 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9943 4 * bit_count (saved_regs_mask
));
9944 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9946 if (IS_INTERRUPT (func_type
))
9947 /* Interrupt handlers will have pushed the
9948 IP onto the stack, so restore it now. */
9949 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9953 /* Restore stack pointer if necessary. */
9954 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9956 operands
[0] = operands
[1] = stack_pointer_rtx
;
9957 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9958 output_add_immediate (operands
);
9961 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9963 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9964 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9965 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9970 start_reg
= FIRST_FPA_REGNUM
;
9972 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9974 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9976 if (reg
- start_reg
== 3)
9978 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9979 start_reg
, SP_REGNUM
);
9980 start_reg
= reg
+ 1;
9985 if (reg
!= start_reg
)
9986 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9987 start_reg
, reg
- start_reg
,
9990 start_reg
= reg
+ 1;
9994 /* Just in case the last register checked also needs unstacking. */
9995 if (reg
!= start_reg
)
9996 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9997 start_reg
, reg
- start_reg
, SP_REGNUM
);
10000 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10002 start_reg
= FIRST_VFP_REGNUM
;
10003 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10005 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10006 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10008 if (start_reg
!= reg
)
10009 arm_output_fldmx (f
, SP_REGNUM
,
10010 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10011 (reg
- start_reg
) / 2);
10012 start_reg
= reg
+ 2;
10015 if (start_reg
!= reg
)
10016 arm_output_fldmx (f
, SP_REGNUM
,
10017 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10018 (reg
- start_reg
) / 2);
10021 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
10022 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10023 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
10025 /* If we can, restore the LR into the PC. */
10026 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
10028 && current_function_pretend_args_size
== 0
10029 && saved_regs_mask
& (1 << LR_REGNUM
)
10030 && !current_function_calls_eh_return
)
10032 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10033 saved_regs_mask
|= (1 << PC_REGNUM
);
10036 /* Load the registers off the stack. If we only have one register
10037 to load use the LDR instruction - it is faster. */
10038 if (saved_regs_mask
== (1 << LR_REGNUM
))
10040 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
10042 else if (saved_regs_mask
)
10044 if (saved_regs_mask
& (1 << SP_REGNUM
))
10045 /* Note - write back to the stack register is not enabled
10046 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10047 in the list of registers and if we add writeback the
10048 instruction becomes UNPREDICTABLE. */
10049 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
10051 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
10054 if (current_function_pretend_args_size
)
10056 /* Unwind the pre-pushed regs. */
10057 operands
[0] = operands
[1] = stack_pointer_rtx
;
10058 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10059 output_add_immediate (operands
);
10063 /* We may have already restored PC directly from the stack. */
10064 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10067 /* Stack adjustment for exception handler. */
10068 if (current_function_calls_eh_return
)
10069 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10070 ARM_EH_STACKADJ_REGNUM
);
10072 /* Generate the return instruction. */
10073 switch ((int) ARM_FUNC_TYPE (func_type
))
10077 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10080 case ARM_FT_EXCEPTION
:
10081 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10084 case ARM_FT_INTERWORKED
:
10085 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10089 if (arm_arch5
|| arm_arch4t
)
10090 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10092 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10100 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10101 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10103 arm_stack_offsets
*offsets
;
10109 /* Emit any call-via-reg trampolines that are needed for v4t support
10110 of call_reg and call_value_reg type insns. */
10111 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10113 rtx label
= cfun
->machine
->call_via
[regno
];
10117 switch_to_section (function_section (current_function_decl
));
10118 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10119 CODE_LABEL_NUMBER (label
));
10120 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10124 /* ??? Probably not safe to set this here, since it assumes that a
10125 function will be emitted as assembly immediately after we generate
10126 RTL for it. This does not happen for inline functions. */
10127 return_used_this_function
= 0;
10131 /* We need to take into account any stack-frame rounding. */
10132 offsets
= arm_get_frame_offsets ();
10134 gcc_assert (!use_return_insn (FALSE
, NULL
)
10135 || !return_used_this_function
10136 || offsets
->saved_regs
== offsets
->outgoing_args
10137 || frame_pointer_needed
);
10139 /* Reset the ARM-specific per-function variables. */
10140 after_arm_reorg
= 0;
10144 /* Generate and emit an insn that we will recognize as a push_multi.
10145 Unfortunately, since this insn does not reflect very well the actual
10146 semantics of the operation, we need to annotate the insn for the benefit
10147 of DWARF2 frame unwind information. */
10149 emit_multi_reg_push (unsigned long mask
)
10152 int num_dwarf_regs
;
10156 int dwarf_par_index
;
10159 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10160 if (mask
& (1 << i
))
10163 gcc_assert (num_regs
&& num_regs
<= 16);
10165 /* We don't record the PC in the dwarf frame information. */
10166 num_dwarf_regs
= num_regs
;
10167 if (mask
& (1 << PC_REGNUM
))
10170 /* For the body of the insn we are going to generate an UNSPEC in
10171 parallel with several USEs. This allows the insn to be recognized
10172 by the push_multi pattern in the arm.md file. The insn looks
10173 something like this:
10176 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10177 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10178 (use (reg:SI 11 fp))
10179 (use (reg:SI 12 ip))
10180 (use (reg:SI 14 lr))
10181 (use (reg:SI 15 pc))
10184 For the frame note however, we try to be more explicit and actually
10185 show each register being stored into the stack frame, plus a (single)
10186 decrement of the stack pointer. We do it this way in order to be
10187 friendly to the stack unwinding code, which only wants to see a single
10188 stack decrement per instruction. The RTL we generate for the note looks
10189 something like this:
10192 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10193 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10194 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10195 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10196 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10199 This sequence is used both by the code to support stack unwinding for
10200 exceptions handlers and the code to generate dwarf2 frame debugging. */
10202 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10203 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10204 dwarf_par_index
= 1;
10206 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10208 if (mask
& (1 << i
))
10210 reg
= gen_rtx_REG (SImode
, i
);
10212 XVECEXP (par
, 0, 0)
10213 = gen_rtx_SET (VOIDmode
,
10214 gen_frame_mem (BLKmode
,
10215 gen_rtx_PRE_DEC (BLKmode
,
10216 stack_pointer_rtx
)),
10217 gen_rtx_UNSPEC (BLKmode
,
10218 gen_rtvec (1, reg
),
10219 UNSPEC_PUSH_MULT
));
10221 if (i
!= PC_REGNUM
)
10223 tmp
= gen_rtx_SET (VOIDmode
,
10224 gen_frame_mem (SImode
, stack_pointer_rtx
),
10226 RTX_FRAME_RELATED_P (tmp
) = 1;
10227 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10235 for (j
= 1, i
++; j
< num_regs
; i
++)
10237 if (mask
& (1 << i
))
10239 reg
= gen_rtx_REG (SImode
, i
);
10241 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10243 if (i
!= PC_REGNUM
)
10246 = gen_rtx_SET (VOIDmode
,
10247 gen_frame_mem (SImode
,
10248 plus_constant (stack_pointer_rtx
,
10251 RTX_FRAME_RELATED_P (tmp
) = 1;
10252 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10259 par
= emit_insn (par
);
10261 tmp
= gen_rtx_SET (VOIDmode
,
10263 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
10264 RTX_FRAME_RELATED_P (tmp
) = 1;
10265 XVECEXP (dwarf
, 0, 0) = tmp
;
10267 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10272 /* Calculate the size of the return value that is passed in registers. */
10274 arm_size_return_regs (void)
10276 enum machine_mode mode
;
10278 if (current_function_return_rtx
!= 0)
10279 mode
= GET_MODE (current_function_return_rtx
);
10281 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10283 return GET_MODE_SIZE (mode
);
10287 emit_sfm (int base_reg
, int count
)
10294 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10295 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10297 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10299 XVECEXP (par
, 0, 0)
10300 = gen_rtx_SET (VOIDmode
,
10301 gen_frame_mem (BLKmode
,
10302 gen_rtx_PRE_DEC (BLKmode
,
10303 stack_pointer_rtx
)),
10304 gen_rtx_UNSPEC (BLKmode
,
10305 gen_rtvec (1, reg
),
10306 UNSPEC_PUSH_MULT
));
10307 tmp
= gen_rtx_SET (VOIDmode
,
10308 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10309 RTX_FRAME_RELATED_P (tmp
) = 1;
10310 XVECEXP (dwarf
, 0, 1) = tmp
;
10312 for (i
= 1; i
< count
; i
++)
10314 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10315 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10317 tmp
= gen_rtx_SET (VOIDmode
,
10318 gen_frame_mem (XFmode
,
10319 plus_constant (stack_pointer_rtx
,
10322 RTX_FRAME_RELATED_P (tmp
) = 1;
10323 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10326 tmp
= gen_rtx_SET (VOIDmode
,
10328 plus_constant (stack_pointer_rtx
, -12 * count
));
10330 RTX_FRAME_RELATED_P (tmp
) = 1;
10331 XVECEXP (dwarf
, 0, 0) = tmp
;
10333 par
= emit_insn (par
);
10334 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10340 /* Return true if the current function needs to save/restore LR. */
10343 thumb_force_lr_save (void)
10345 return !cfun
->machine
->lr_save_eliminated
10346 && (!leaf_function_p ()
10347 || thumb_far_jump_used_p ()
10348 || regs_ever_live
[LR_REGNUM
]);
10352 /* Compute the distance from register FROM to register TO.
10353 These can be the arg pointer (26), the soft frame pointer (25),
10354 the stack pointer (13) or the hard frame pointer (11).
10355 In thumb mode r7 is used as the soft frame pointer, if needed.
10356 Typical stack layout looks like this:
10358 old stack pointer -> | |
10361 | | saved arguments for
10362 | | vararg functions
10365 hard FP & arg pointer -> | | \
10373 soft frame pointer -> | | /
10378 locals base pointer -> | | /
10383 current stack pointer -> | | /
10386 For a given function some or all of these stack components
10387 may not be needed, giving rise to the possibility of
10388 eliminating some of the registers.
10390 The values returned by this function must reflect the behavior
10391 of arm_expand_prologue() and arm_compute_save_reg_mask().
10393 The sign of the number returned reflects the direction of stack
10394 growth, so the values are positive for all eliminations except
10395 from the soft frame pointer to the hard frame pointer.
10397 SFP may point just inside the local variables block to ensure correct
10401 /* Calculate stack offsets. These are used to calculate register elimination
10402 offsets and in prologue/epilogue code. */
10404 static arm_stack_offsets
*
10405 arm_get_frame_offsets (void)
10407 struct arm_stack_offsets
*offsets
;
10408 unsigned long func_type
;
10411 HOST_WIDE_INT frame_size
;
10413 offsets
= &cfun
->machine
->stack_offsets
;
10415 /* We need to know if we are a leaf function. Unfortunately, it
10416 is possible to be called after start_sequence has been called,
10417 which causes get_insns to return the insns for the sequence,
10418 not the function, which will cause leaf_function_p to return
10419 the incorrect result.
10421 to know about leaf functions once reload has completed, and the
10422 frame size cannot be changed after that time, so we can safely
10423 use the cached value. */
10425 if (reload_completed
)
10428 /* Initially this is the size of the local variables. It will translated
10429 into an offset once we have determined the size of preceding data. */
10430 frame_size
= ROUND_UP_WORD (get_frame_size ());
10432 leaf
= leaf_function_p ();
10434 /* Space for variadic functions. */
10435 offsets
->saved_args
= current_function_pretend_args_size
;
10437 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10441 unsigned int regno
;
10443 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10445 /* We know that SP will be doubleword aligned on entry, and we must
10446 preserve that condition at any subroutine call. We also require the
10447 soft frame pointer to be doubleword aligned. */
10449 if (TARGET_REALLY_IWMMXT
)
10451 /* Check for the call-saved iWMMXt registers. */
10452 for (regno
= FIRST_IWMMXT_REGNUM
;
10453 regno
<= LAST_IWMMXT_REGNUM
;
10455 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10459 func_type
= arm_current_func_type ();
10460 if (! IS_VOLATILE (func_type
))
10462 /* Space for saved FPA registers. */
10463 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10464 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10467 /* Space for saved VFP registers. */
10468 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10469 saved
+= arm_get_vfp_saved_size ();
10472 else /* TARGET_THUMB */
10474 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10475 if (TARGET_BACKTRACE
)
10479 /* Saved registers include the stack frame. */
10480 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10481 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10482 /* A leaf function does not need any stack alignment if it has nothing
10484 if (leaf
&& frame_size
== 0)
10486 offsets
->outgoing_args
= offsets
->soft_frame
;
10490 /* Ensure SFP has the correct alignment. */
10491 if (ARM_DOUBLEWORD_ALIGN
10492 && (offsets
->soft_frame
& 7))
10493 offsets
->soft_frame
+= 4;
10495 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10496 offsets
->outgoing_args
= (offsets
->locals_base
10497 + current_function_outgoing_args_size
);
10499 if (ARM_DOUBLEWORD_ALIGN
)
10501 /* Ensure SP remains doubleword aligned. */
10502 if (offsets
->outgoing_args
& 7)
10503 offsets
->outgoing_args
+= 4;
10504 gcc_assert (!(offsets
->outgoing_args
& 7));
10511 /* Calculate the relative offsets for the different stack pointers. Positive
10512 offsets are in the direction of stack growth. */
10515 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10517 arm_stack_offsets
*offsets
;
10519 offsets
= arm_get_frame_offsets ();
10521 /* OK, now we have enough information to compute the distances.
10522 There must be an entry in these switch tables for each pair
10523 of registers in ELIMINABLE_REGS, even if some of the entries
10524 seem to be redundant or useless. */
10527 case ARG_POINTER_REGNUM
:
10530 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10533 case FRAME_POINTER_REGNUM
:
10534 /* This is the reverse of the soft frame pointer
10535 to hard frame pointer elimination below. */
10536 return offsets
->soft_frame
- offsets
->saved_args
;
10538 case ARM_HARD_FRAME_POINTER_REGNUM
:
10539 /* If there is no stack frame then the hard
10540 frame pointer and the arg pointer coincide. */
10541 if (offsets
->frame
== offsets
->saved_regs
)
10543 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10544 return (frame_pointer_needed
10545 && cfun
->static_chain_decl
!= NULL
10546 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10548 case STACK_POINTER_REGNUM
:
10549 /* If nothing has been pushed on the stack at all
10550 then this will return -4. This *is* correct! */
10551 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10554 gcc_unreachable ();
10556 gcc_unreachable ();
10558 case FRAME_POINTER_REGNUM
:
10561 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10564 case ARM_HARD_FRAME_POINTER_REGNUM
:
10565 /* The hard frame pointer points to the top entry in the
10566 stack frame. The soft frame pointer to the bottom entry
10567 in the stack frame. If there is no stack frame at all,
10568 then they are identical. */
10570 return offsets
->frame
- offsets
->soft_frame
;
10572 case STACK_POINTER_REGNUM
:
10573 return offsets
->outgoing_args
- offsets
->soft_frame
;
10576 gcc_unreachable ();
10578 gcc_unreachable ();
10581 /* You cannot eliminate from the stack pointer.
10582 In theory you could eliminate from the hard frame
10583 pointer to the stack pointer, but this will never
10584 happen, since if a stack frame is not needed the
10585 hard frame pointer will never be used. */
10586 gcc_unreachable ();
10591 /* Generate the prologue instructions for entry into an ARM function. */
10593 arm_expand_prologue (void)
10599 unsigned long live_regs_mask
;
10600 unsigned long func_type
;
10602 int saved_pretend_args
= 0;
10603 int saved_regs
= 0;
10604 unsigned HOST_WIDE_INT args_to_push
;
10605 arm_stack_offsets
*offsets
;
10607 func_type
= arm_current_func_type ();
10609 /* Naked functions don't have prologues. */
10610 if (IS_NAKED (func_type
))
10613 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10614 args_to_push
= current_function_pretend_args_size
;
10616 /* Compute which register we will have to save onto the stack. */
10617 live_regs_mask
= arm_compute_save_reg_mask ();
10619 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10621 if (frame_pointer_needed
)
10623 if (IS_INTERRUPT (func_type
))
10625 /* Interrupt functions must not corrupt any registers.
10626 Creating a frame pointer however, corrupts the IP
10627 register, so we must push it first. */
10628 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10630 /* Do not set RTX_FRAME_RELATED_P on this insn.
10631 The dwarf stack unwinding code only wants to see one
10632 stack decrement per function, and this is not it. If
10633 this instruction is labeled as being part of the frame
10634 creation sequence then dwarf2out_frame_debug_expr will
10635 die when it encounters the assignment of IP to FP
10636 later on, since the use of SP here establishes SP as
10637 the CFA register and not IP.
10639 Anyway this instruction is not really part of the stack
10640 frame creation although it is part of the prologue. */
10642 else if (IS_NESTED (func_type
))
10644 /* The Static chain register is the same as the IP register
10645 used as a scratch register during stack frame creation.
10646 To get around this need to find somewhere to store IP
10647 whilst the frame is being created. We try the following
10650 1. The last argument register.
10651 2. A slot on the stack above the frame. (This only
10652 works if the function is not a varargs function).
10653 3. Register r3, after pushing the argument registers
10656 Note - we only need to tell the dwarf2 backend about the SP
10657 adjustment in the second variant; the static chain register
10658 doesn't need to be unwound, as it doesn't contain a value
10659 inherited from the caller. */
10661 if (regs_ever_live
[3] == 0)
10662 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10663 else if (args_to_push
== 0)
10667 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10668 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
10671 /* Just tell the dwarf backend that we adjusted SP. */
10672 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10673 plus_constant (stack_pointer_rtx
,
10675 RTX_FRAME_RELATED_P (insn
) = 1;
10676 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10677 dwarf
, REG_NOTES (insn
));
10681 /* Store the args on the stack. */
10682 if (cfun
->machine
->uses_anonymous_args
)
10683 insn
= emit_multi_reg_push
10684 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10687 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10688 GEN_INT (- args_to_push
)));
10690 RTX_FRAME_RELATED_P (insn
) = 1;
10692 saved_pretend_args
= 1;
10693 fp_offset
= args_to_push
;
10696 /* Now reuse r3 to preserve IP. */
10697 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10701 insn
= emit_set_insn (ip_rtx
,
10702 plus_constant (stack_pointer_rtx
, fp_offset
));
10703 RTX_FRAME_RELATED_P (insn
) = 1;
10708 /* Push the argument registers, or reserve space for them. */
10709 if (cfun
->machine
->uses_anonymous_args
)
10710 insn
= emit_multi_reg_push
10711 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10714 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10715 GEN_INT (- args_to_push
)));
10716 RTX_FRAME_RELATED_P (insn
) = 1;
10719 /* If this is an interrupt service routine, and the link register
10720 is going to be pushed, and we are not creating a stack frame,
10721 (which would involve an extra push of IP and a pop in the epilogue)
10722 subtracting four from LR now will mean that the function return
10723 can be done with a single instruction. */
10724 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10725 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10726 && ! frame_pointer_needed
)
10728 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
10730 emit_set_insn (lr
, plus_constant (lr
, -4));
10733 if (live_regs_mask
)
10735 insn
= emit_multi_reg_push (live_regs_mask
);
10736 saved_regs
+= bit_count (live_regs_mask
) * 4;
10737 RTX_FRAME_RELATED_P (insn
) = 1;
10741 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10742 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10744 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10745 insn
= gen_frame_mem (V2SImode
, insn
);
10746 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
10747 RTX_FRAME_RELATED_P (insn
) = 1;
10751 if (! IS_VOLATILE (func_type
))
10755 /* Save any floating point call-saved registers used by this
10757 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10759 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10760 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10762 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10763 insn
= gen_frame_mem (XFmode
, insn
);
10764 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
10765 RTX_FRAME_RELATED_P (insn
) = 1;
10771 start_reg
= LAST_FPA_REGNUM
;
10773 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10775 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10777 if (start_reg
- reg
== 3)
10779 insn
= emit_sfm (reg
, 4);
10780 RTX_FRAME_RELATED_P (insn
) = 1;
10782 start_reg
= reg
- 1;
10787 if (start_reg
!= reg
)
10789 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10790 RTX_FRAME_RELATED_P (insn
) = 1;
10791 saved_regs
+= (start_reg
- reg
) * 12;
10793 start_reg
= reg
- 1;
10797 if (start_reg
!= reg
)
10799 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10800 saved_regs
+= (start_reg
- reg
) * 12;
10801 RTX_FRAME_RELATED_P (insn
) = 1;
10804 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10806 start_reg
= FIRST_VFP_REGNUM
;
10808 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10810 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10811 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10813 if (start_reg
!= reg
)
10814 saved_regs
+= vfp_emit_fstmx (start_reg
,
10815 (reg
- start_reg
) / 2);
10816 start_reg
= reg
+ 2;
10819 if (start_reg
!= reg
)
10820 saved_regs
+= vfp_emit_fstmx (start_reg
,
10821 (reg
- start_reg
) / 2);
10825 if (frame_pointer_needed
)
10827 /* Create the new frame pointer. */
10828 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10829 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10830 RTX_FRAME_RELATED_P (insn
) = 1;
10832 if (IS_NESTED (func_type
))
10834 /* Recover the static chain register. */
10835 if (regs_ever_live
[3] == 0
10836 || saved_pretend_args
)
10837 insn
= gen_rtx_REG (SImode
, 3);
10838 else /* if (current_function_pretend_args_size == 0) */
10840 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
10841 insn
= gen_frame_mem (SImode
, insn
);
10844 emit_set_insn (ip_rtx
, insn
);
10845 /* Add a USE to stop propagate_one_insn() from barfing. */
10846 emit_insn (gen_prologue_use (ip_rtx
));
10850 offsets
= arm_get_frame_offsets ();
10851 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10853 /* This add can produce multiple insns for a large constant, so we
10854 need to get tricky. */
10855 rtx last
= get_last_insn ();
10857 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10858 - offsets
->outgoing_args
);
10860 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10864 last
= last
? NEXT_INSN (last
) : get_insns ();
10865 RTX_FRAME_RELATED_P (last
) = 1;
10867 while (last
!= insn
);
10869 /* If the frame pointer is needed, emit a special barrier that
10870 will prevent the scheduler from moving stores to the frame
10871 before the stack adjustment. */
10872 if (frame_pointer_needed
)
10873 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10874 hard_frame_pointer_rtx
));
10878 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
10879 arm_load_pic_register (0UL);
10881 /* If we are profiling, make sure no instructions are scheduled before
10882 the call to mcount. Similarly if the user has requested no
10883 scheduling in the prolog. Similarly if we want non-call exceptions
10884 using the EABI unwinder, to prevent faulting instructions from being
10885 swapped with a stack adjustment. */
10886 if (current_function_profile
|| !TARGET_SCHED_PROLOG
10887 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
10888 emit_insn (gen_blockage ());
10890 /* If the link register is being kept alive, with the return address in it,
10891 then make sure that it does not get reused by the ce2 pass. */
10892 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10894 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10895 cfun
->machine
->lr_save_eliminated
= 1;
10899 /* If CODE is 'd', then the X is a condition operand and the instruction
10900 should only be executed if the condition is true.
10901 if CODE is 'D', then the X is a condition operand and the instruction
10902 should only be executed if the condition is false: however, if the mode
10903 of the comparison is CCFPEmode, then always execute the instruction -- we
10904 do this because in these circumstances !GE does not necessarily imply LT;
10905 in these cases the instruction pattern will take care to make sure that
10906 an instruction containing %d will follow, thereby undoing the effects of
10907 doing this instruction unconditionally.
10908 If CODE is 'N' then X is a floating point operand that must be negated
10910 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10911 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10913 arm_print_operand (FILE *stream
, rtx x
, int code
)
10918 fputs (ASM_COMMENT_START
, stream
);
10922 fputs (user_label_prefix
, stream
);
10926 fputs (REGISTER_PREFIX
, stream
);
10930 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10934 output_operand_lossage ("predicated Thumb instruction");
10937 if (current_insn_predicate
!= NULL
)
10939 output_operand_lossage
10940 ("predicated instruction in conditional sequence");
10944 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10946 else if (current_insn_predicate
)
10948 enum arm_cond_code code
;
10952 output_operand_lossage ("predicated Thumb instruction");
10956 code
= get_arm_condition_code (current_insn_predicate
);
10957 fputs (arm_condition_codes
[code
], stream
);
10964 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10965 r
= REAL_VALUE_NEGATE (r
);
10966 fprintf (stream
, "%s", fp_const_from_val (&r
));
10971 if (GET_CODE (x
) == CONST_INT
)
10974 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10975 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10979 putc ('~', stream
);
10980 output_addr_const (stream
, x
);
10985 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10988 /* Truncate Cirrus shift counts. */
10990 if (GET_CODE (x
) == CONST_INT
)
10992 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10995 arm_print_operand (stream
, x
, 0);
10999 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
11005 const char * shift
= shift_op (x
, &val
);
11009 fprintf (stream
, ", %s ", shift_op (x
, &val
));
11011 arm_print_operand (stream
, XEXP (x
, 1), 0);
11013 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
11018 /* An explanation of the 'Q', 'R' and 'H' register operands:
11020 In a pair of registers containing a DI or DF value the 'Q'
11021 operand returns the register number of the register containing
11022 the least significant part of the value. The 'R' operand returns
11023 the register number of the register containing the most
11024 significant part of the value.
11026 The 'H' operand returns the higher of the two register numbers.
11027 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11028 same as the 'Q' operand, since the most significant part of the
11029 value is held in the lower number register. The reverse is true
11030 on systems where WORDS_BIG_ENDIAN is false.
11032 The purpose of these operands is to distinguish between cases
11033 where the endian-ness of the values is important (for example
11034 when they are added together), and cases where the endian-ness
11035 is irrelevant, but the order of register operations is important.
11036 For example when loading a value from memory into a register
11037 pair, the endian-ness does not matter. Provided that the value
11038 from the lower memory address is put into the lower numbered
11039 register, and the value from the higher address is put into the
11040 higher numbered register, the load will work regardless of whether
11041 the value being loaded is big-wordian or little-wordian. The
11042 order of the two register loads can matter however, if the address
11043 of the memory location is actually held in one of the registers
11044 being overwritten by the load. */
11046 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11048 output_operand_lossage ("invalid operand for code '%c'", code
);
11052 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11056 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11058 output_operand_lossage ("invalid operand for code '%c'", code
);
11062 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11066 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11068 output_operand_lossage ("invalid operand for code '%c'", code
);
11072 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11076 asm_fprintf (stream
, "%r",
11077 GET_CODE (XEXP (x
, 0)) == REG
11078 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11082 asm_fprintf (stream
, "{%r-%r}",
11084 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11088 /* CONST_TRUE_RTX means always -- that's the default. */
11089 if (x
== const_true_rtx
)
11092 if (!COMPARISON_P (x
))
11094 output_operand_lossage ("invalid operand for code '%c'", code
);
11098 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11103 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11104 want to do that. */
11105 if (x
== const_true_rtx
)
11107 output_operand_lossage ("instruction never exectued");
11110 if (!COMPARISON_P (x
))
11112 output_operand_lossage ("invalid operand for code '%c'", code
);
11116 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11117 (get_arm_condition_code (x
))],
11121 /* Cirrus registers can be accessed in a variety of ways:
11122 single floating point (f)
11123 double floating point (d)
11125 64bit integer (dx). */
11126 case 'W': /* Cirrus register in F mode. */
11127 case 'X': /* Cirrus register in D mode. */
11128 case 'Y': /* Cirrus register in FX mode. */
11129 case 'Z': /* Cirrus register in DX mode. */
11130 gcc_assert (GET_CODE (x
) == REG
11131 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11133 fprintf (stream
, "mv%s%s",
11135 : code
== 'X' ? "d"
11136 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11140 /* Print cirrus register in the mode specified by the register's mode. */
11143 int mode
= GET_MODE (x
);
11145 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11147 output_operand_lossage ("invalid operand for code '%c'", code
);
11151 fprintf (stream
, "mv%s%s",
11152 mode
== DFmode
? "d"
11153 : mode
== SImode
? "fx"
11154 : mode
== DImode
? "dx"
11155 : "f", reg_names
[REGNO (x
)] + 2);
11161 if (GET_CODE (x
) != REG
11162 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11163 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11164 /* Bad value for wCG register number. */
11166 output_operand_lossage ("invalid operand for code '%c'", code
);
11171 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11174 /* Print an iWMMXt control register name. */
11176 if (GET_CODE (x
) != CONST_INT
11178 || INTVAL (x
) >= 16)
11179 /* Bad value for wC register number. */
11181 output_operand_lossage ("invalid operand for code '%c'", code
);
11187 static const char * wc_reg_names
[16] =
11189 "wCID", "wCon", "wCSSF", "wCASF",
11190 "wC4", "wC5", "wC6", "wC7",
11191 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11192 "wC12", "wC13", "wC14", "wC15"
11195 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11199 /* Print a VFP double precision register name. */
11202 int mode
= GET_MODE (x
);
11205 if (mode
!= DImode
&& mode
!= DFmode
)
11207 output_operand_lossage ("invalid operand for code '%c'", code
);
11211 if (GET_CODE (x
) != REG
11212 || !IS_VFP_REGNUM (REGNO (x
)))
11214 output_operand_lossage ("invalid operand for code '%c'", code
);
11218 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11221 output_operand_lossage ("invalid operand for code '%c'", code
);
11225 fprintf (stream
, "d%d", num
>> 1);
11232 output_operand_lossage ("missing operand");
11236 switch (GET_CODE (x
))
11239 asm_fprintf (stream
, "%r", REGNO (x
));
11243 output_memory_reference_mode
= GET_MODE (x
);
11244 output_address (XEXP (x
, 0));
11248 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11252 gcc_assert (GET_CODE (x
) != NEG
);
11253 fputc ('#', stream
);
11254 output_addr_const (stream
, x
);
11260 #ifndef AOF_ASSEMBLER
11261 /* Target hook for assembling integer objects. The ARM version needs to
11262 handle word-sized values specially. */
11264 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11266 if (size
== UNITS_PER_WORD
&& aligned_p
)
11268 fputs ("\t.word\t", asm_out_file
);
11269 output_addr_const (asm_out_file
, x
);
11271 /* Mark symbols as position independent. We only do this in the
11272 .text segment, not in the .data segment. */
11273 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11274 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11276 if (GET_CODE (x
) == SYMBOL_REF
11277 && (CONSTANT_POOL_ADDRESS_P (x
)
11278 || SYMBOL_REF_LOCAL_P (x
)))
11279 fputs ("(GOTOFF)", asm_out_file
);
11280 else if (GET_CODE (x
) == LABEL_REF
)
11281 fputs ("(GOTOFF)", asm_out_file
);
11283 fputs ("(GOT)", asm_out_file
);
11285 fputc ('\n', asm_out_file
);
11289 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11293 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11295 units
= CONST_VECTOR_NUNITS (x
);
11297 switch (GET_MODE (x
))
11299 case V2SImode
: size
= 4; break;
11300 case V4HImode
: size
= 2; break;
11301 case V8QImode
: size
= 1; break;
11303 gcc_unreachable ();
11306 for (i
= 0; i
< units
; i
++)
11310 elt
= CONST_VECTOR_ELT (x
, i
);
11312 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11318 return default_assemble_integer (x
, size
, aligned_p
);
11322 /* Add a function to the list of static constructors. */
11325 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
11327 if (!TARGET_AAPCS_BASED
)
11329 default_named_section_asm_out_constructor (symbol
, priority
);
11333 /* Put these in the .init_array section, using a special relocation. */
11334 switch_to_section (ctors_section
);
11335 assemble_align (POINTER_SIZE
);
11336 fputs ("\t.word\t", asm_out_file
);
11337 output_addr_const (asm_out_file
, symbol
);
11338 fputs ("(target1)\n", asm_out_file
);
11342 /* A finite state machine takes care of noticing whether or not instructions
11343 can be conditionally executed, and thus decrease execution time and code
11344 size by deleting branch instructions. The fsm is controlled by
11345 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11347 /* The state of the fsm controlling condition codes are:
11348 0: normal, do nothing special
11349 1: make ASM_OUTPUT_OPCODE not output this instruction
11350 2: make ASM_OUTPUT_OPCODE not output this instruction
11351 3: make instructions conditional
11352 4: make instructions conditional
11354 State transitions (state->state by whom under condition):
11355 0 -> 1 final_prescan_insn if the `target' is a label
11356 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11357 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11358 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11359 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11360 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11361 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11362 (the target insn is arm_target_insn).
11364 If the jump clobbers the conditions then we use states 2 and 4.
11366 A similar thing can be done with conditional return insns.
11368 XXX In case the `target' is an unconditional branch, this conditionalising
11369 of the instructions always reduces code size, but not always execution
11370 time. But then, I want to reduce the code size to somewhere near what
11371 /bin/cc produces. */
11373 /* Returns the index of the ARM condition code string in
11374 `arm_condition_codes'. COMPARISON should be an rtx like
11375 `(eq (...) (...))'. */
11376 static enum arm_cond_code
11377 get_arm_condition_code (rtx comparison
)
11379 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11381 enum rtx_code comp_code
= GET_CODE (comparison
);
11383 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11384 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11385 XEXP (comparison
, 1));
11389 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11390 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11391 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11392 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11393 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11394 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11395 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11396 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11397 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11398 case CC_DLTUmode
: code
= ARM_CC
;
11401 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11403 if (comp_code
== EQ
)
11404 return ARM_INVERSE_CONDITION_CODE (code
);
11410 case NE
: return ARM_NE
;
11411 case EQ
: return ARM_EQ
;
11412 case GE
: return ARM_PL
;
11413 case LT
: return ARM_MI
;
11414 default: gcc_unreachable ();
11420 case NE
: return ARM_NE
;
11421 case EQ
: return ARM_EQ
;
11422 default: gcc_unreachable ();
11428 case NE
: return ARM_MI
;
11429 case EQ
: return ARM_PL
;
11430 default: gcc_unreachable ();
11435 /* These encodings assume that AC=1 in the FPA system control
11436 byte. This allows us to handle all cases except UNEQ and
11440 case GE
: return ARM_GE
;
11441 case GT
: return ARM_GT
;
11442 case LE
: return ARM_LS
;
11443 case LT
: return ARM_MI
;
11444 case NE
: return ARM_NE
;
11445 case EQ
: return ARM_EQ
;
11446 case ORDERED
: return ARM_VC
;
11447 case UNORDERED
: return ARM_VS
;
11448 case UNLT
: return ARM_LT
;
11449 case UNLE
: return ARM_LE
;
11450 case UNGT
: return ARM_HI
;
11451 case UNGE
: return ARM_PL
;
11452 /* UNEQ and LTGT do not have a representation. */
11453 case UNEQ
: /* Fall through. */
11454 case LTGT
: /* Fall through. */
11455 default: gcc_unreachable ();
11461 case NE
: return ARM_NE
;
11462 case EQ
: return ARM_EQ
;
11463 case GE
: return ARM_LE
;
11464 case GT
: return ARM_LT
;
11465 case LE
: return ARM_GE
;
11466 case LT
: return ARM_GT
;
11467 case GEU
: return ARM_LS
;
11468 case GTU
: return ARM_CC
;
11469 case LEU
: return ARM_CS
;
11470 case LTU
: return ARM_HI
;
11471 default: gcc_unreachable ();
11477 case LTU
: return ARM_CS
;
11478 case GEU
: return ARM_CC
;
11479 default: gcc_unreachable ();
11485 case NE
: return ARM_NE
;
11486 case EQ
: return ARM_EQ
;
11487 case GE
: return ARM_GE
;
11488 case GT
: return ARM_GT
;
11489 case LE
: return ARM_LE
;
11490 case LT
: return ARM_LT
;
11491 case GEU
: return ARM_CS
;
11492 case GTU
: return ARM_HI
;
11493 case LEU
: return ARM_LS
;
11494 case LTU
: return ARM_CC
;
11495 default: gcc_unreachable ();
11498 default: gcc_unreachable ();
11503 arm_final_prescan_insn (rtx insn
)
11505 /* BODY will hold the body of INSN. */
11506 rtx body
= PATTERN (insn
);
11508 /* This will be 1 if trying to repeat the trick, and things need to be
11509 reversed if it appears to fail. */
11512 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11513 taken are clobbered, even if the rtl suggests otherwise. It also
11514 means that we have to grub around within the jump expression to find
11515 out what the conditions are when the jump isn't taken. */
11516 int jump_clobbers
= 0;
11518 /* If we start with a return insn, we only succeed if we find another one. */
11519 int seeking_return
= 0;
11521 /* START_INSN will hold the insn from where we start looking. This is the
11522 first insn after the following code_label if REVERSE is true. */
11523 rtx start_insn
= insn
;
11525 /* If in state 4, check if the target branch is reached, in order to
11526 change back to state 0. */
11527 if (arm_ccfsm_state
== 4)
11529 if (insn
== arm_target_insn
)
11531 arm_target_insn
= NULL
;
11532 arm_ccfsm_state
= 0;
11537 /* If in state 3, it is possible to repeat the trick, if this insn is an
11538 unconditional branch to a label, and immediately following this branch
11539 is the previous target label which is only used once, and the label this
11540 branch jumps to is not too far off. */
11541 if (arm_ccfsm_state
== 3)
11543 if (simplejump_p (insn
))
11545 start_insn
= next_nonnote_insn (start_insn
);
11546 if (GET_CODE (start_insn
) == BARRIER
)
11548 /* XXX Isn't this always a barrier? */
11549 start_insn
= next_nonnote_insn (start_insn
);
11551 if (GET_CODE (start_insn
) == CODE_LABEL
11552 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11553 && LABEL_NUSES (start_insn
) == 1)
11558 else if (GET_CODE (body
) == RETURN
)
11560 start_insn
= next_nonnote_insn (start_insn
);
11561 if (GET_CODE (start_insn
) == BARRIER
)
11562 start_insn
= next_nonnote_insn (start_insn
);
11563 if (GET_CODE (start_insn
) == CODE_LABEL
11564 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11565 && LABEL_NUSES (start_insn
) == 1)
11568 seeking_return
= 1;
11577 gcc_assert (!arm_ccfsm_state
|| reverse
);
11578 if (GET_CODE (insn
) != JUMP_INSN
)
11581 /* This jump might be paralleled with a clobber of the condition codes
11582 the jump should always come first */
11583 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11584 body
= XVECEXP (body
, 0, 0);
11587 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11588 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11591 int fail
= FALSE
, succeed
= FALSE
;
11592 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11593 int then_not_else
= TRUE
;
11594 rtx this_insn
= start_insn
, label
= 0;
11596 /* If the jump cannot be done with one instruction, we cannot
11597 conditionally execute the instruction in the inverse case. */
11598 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11604 /* Register the insn jumped to. */
11607 if (!seeking_return
)
11608 label
= XEXP (SET_SRC (body
), 0);
11610 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11611 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11612 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11614 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11615 then_not_else
= FALSE
;
11617 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11618 seeking_return
= 1;
11619 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11621 seeking_return
= 1;
11622 then_not_else
= FALSE
;
11625 gcc_unreachable ();
11627 /* See how many insns this branch skips, and what kind of insns. If all
11628 insns are okay, and the label or unconditional branch to the same
11629 label is not too far away, succeed. */
11630 for (insns_skipped
= 0;
11631 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11635 this_insn
= next_nonnote_insn (this_insn
);
11639 switch (GET_CODE (this_insn
))
11642 /* Succeed if it is the target label, otherwise fail since
11643 control falls in from somewhere else. */
11644 if (this_insn
== label
)
11648 arm_ccfsm_state
= 2;
11649 this_insn
= next_nonnote_insn (this_insn
);
11652 arm_ccfsm_state
= 1;
11660 /* Succeed if the following insn is the target label.
11662 If return insns are used then the last insn in a function
11663 will be a barrier. */
11664 this_insn
= next_nonnote_insn (this_insn
);
11665 if (this_insn
&& this_insn
== label
)
11669 arm_ccfsm_state
= 2;
11670 this_insn
= next_nonnote_insn (this_insn
);
11673 arm_ccfsm_state
= 1;
11681 /* The AAPCS says that conditional calls should not be
11682 used since they make interworking inefficient (the
11683 linker can't transform BL<cond> into BLX). That's
11684 only a problem if the machine has BLX. */
11691 /* Succeed if the following insn is the target label, or
11692 if the following two insns are a barrier and the
11694 this_insn
= next_nonnote_insn (this_insn
);
11695 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11696 this_insn
= next_nonnote_insn (this_insn
);
11698 if (this_insn
&& this_insn
== label
11699 && insns_skipped
< max_insns_skipped
)
11703 arm_ccfsm_state
= 2;
11704 this_insn
= next_nonnote_insn (this_insn
);
11707 arm_ccfsm_state
= 1;
11715 /* If this is an unconditional branch to the same label, succeed.
11716 If it is to another label, do nothing. If it is conditional,
11718 /* XXX Probably, the tests for SET and the PC are
11721 scanbody
= PATTERN (this_insn
);
11722 if (GET_CODE (scanbody
) == SET
11723 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11725 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11726 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11728 arm_ccfsm_state
= 2;
11731 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11734 /* Fail if a conditional return is undesirable (e.g. on a
11735 StrongARM), but still allow this if optimizing for size. */
11736 else if (GET_CODE (scanbody
) == RETURN
11737 && !use_return_insn (TRUE
, NULL
)
11740 else if (GET_CODE (scanbody
) == RETURN
11743 arm_ccfsm_state
= 2;
11746 else if (GET_CODE (scanbody
) == PARALLEL
)
11748 switch (get_attr_conds (this_insn
))
11758 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11763 /* Instructions using or affecting the condition codes make it
11765 scanbody
= PATTERN (this_insn
);
11766 if (!(GET_CODE (scanbody
) == SET
11767 || GET_CODE (scanbody
) == PARALLEL
)
11768 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11771 /* A conditional cirrus instruction must be followed by
11772 a non Cirrus instruction. However, since we
11773 conditionalize instructions in this function and by
11774 the time we get here we can't add instructions
11775 (nops), because shorten_branches() has already been
11776 called, we will disable conditionalizing Cirrus
11777 instructions to be safe. */
11778 if (GET_CODE (scanbody
) != USE
11779 && GET_CODE (scanbody
) != CLOBBER
11780 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11790 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11791 arm_target_label
= CODE_LABEL_NUMBER (label
);
11794 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11796 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11798 this_insn
= next_nonnote_insn (this_insn
);
11799 gcc_assert (!this_insn
11800 || (GET_CODE (this_insn
) != BARRIER
11801 && GET_CODE (this_insn
) != CODE_LABEL
));
11805 /* Oh, dear! we ran off the end.. give up. */
11806 recog (PATTERN (insn
), insn
, NULL
);
11807 arm_ccfsm_state
= 0;
11808 arm_target_insn
= NULL
;
11811 arm_target_insn
= this_insn
;
11815 gcc_assert (!reverse
);
11817 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11819 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11820 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11821 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11822 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11826 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11829 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11833 if (reverse
|| then_not_else
)
11834 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11837 /* Restore recog_data (getting the attributes of other insns can
11838 destroy this array, but final.c assumes that it remains intact
11839 across this call; since the insn has been recognized already we
11840 call recog direct). */
11841 recog (PATTERN (insn
), insn
, NULL
);
11845 /* Returns true if REGNO is a valid register
11846 for holding a quantity of type MODE. */
11848 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11850 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11851 return (regno
== CC_REGNUM
11852 || (TARGET_HARD_FLOAT
&& TARGET_VFP
11853 && regno
== VFPCC_REGNUM
));
11856 /* For the Thumb we only allow values bigger than SImode in
11857 registers 0 - 6, so that there is always a second low
11858 register available to hold the upper part of the value.
11859 We probably we ought to ensure that the register is the
11860 start of an even numbered register pair. */
11861 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11863 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
11864 && IS_CIRRUS_REGNUM (regno
))
11865 /* We have outlawed SI values in Cirrus registers because they
11866 reside in the lower 32 bits, but SF values reside in the
11867 upper 32 bits. This causes gcc all sorts of grief. We can't
11868 even split the registers into pairs because Cirrus SI values
11869 get sign extended to 64bits-- aldyh. */
11870 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11872 if (TARGET_HARD_FLOAT
&& TARGET_VFP
11873 && IS_VFP_REGNUM (regno
))
11875 if (mode
== SFmode
|| mode
== SImode
)
11878 /* DFmode values are only valid in even register pairs. */
11879 if (mode
== DFmode
)
11880 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11884 if (TARGET_REALLY_IWMMXT
)
11886 if (IS_IWMMXT_GR_REGNUM (regno
))
11887 return mode
== SImode
;
11889 if (IS_IWMMXT_REGNUM (regno
))
11890 return VALID_IWMMXT_REG_MODE (mode
);
11893 /* We allow any value to be stored in the general registers.
11894 Restrict doubleword quantities to even register pairs so that we can
11896 if (regno
<= LAST_ARM_REGNUM
)
11897 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11899 if (regno
== FRAME_POINTER_REGNUM
11900 || regno
== ARG_POINTER_REGNUM
)
11901 /* We only allow integers in the fake hard registers. */
11902 return GET_MODE_CLASS (mode
) == MODE_INT
;
11904 /* The only registers left are the FPA registers
11905 which we only allow to hold FP values. */
11906 return (TARGET_HARD_FLOAT
&& TARGET_FPA
11907 && GET_MODE_CLASS (mode
) == MODE_FLOAT
11908 && regno
>= FIRST_FPA_REGNUM
11909 && regno
<= LAST_FPA_REGNUM
);
11913 arm_regno_class (int regno
)
11917 if (regno
== STACK_POINTER_REGNUM
)
11919 if (regno
== CC_REGNUM
)
11926 if ( regno
<= LAST_ARM_REGNUM
11927 || regno
== FRAME_POINTER_REGNUM
11928 || regno
== ARG_POINTER_REGNUM
)
11929 return GENERAL_REGS
;
11931 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11934 if (IS_CIRRUS_REGNUM (regno
))
11935 return CIRRUS_REGS
;
11937 if (IS_VFP_REGNUM (regno
))
11940 if (IS_IWMMXT_REGNUM (regno
))
11941 return IWMMXT_REGS
;
11943 if (IS_IWMMXT_GR_REGNUM (regno
))
11944 return IWMMXT_GR_REGS
;
11949 /* Handle a special case when computing the offset
11950 of an argument from the frame pointer. */
11952 arm_debugger_arg_offset (int value
, rtx addr
)
11956 /* We are only interested if dbxout_parms() failed to compute the offset. */
11960 /* We can only cope with the case where the address is held in a register. */
11961 if (GET_CODE (addr
) != REG
)
11964 /* If we are using the frame pointer to point at the argument, then
11965 an offset of 0 is correct. */
11966 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11969 /* If we are using the stack pointer to point at the
11970 argument, then an offset of 0 is correct. */
11971 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11972 && REGNO (addr
) == SP_REGNUM
)
11975 /* Oh dear. The argument is pointed to by a register rather
11976 than being held in a register, or being stored at a known
11977 offset from the frame pointer. Since GDB only understands
11978 those two kinds of argument we must translate the address
11979 held in the register into an offset from the frame pointer.
11980 We do this by searching through the insns for the function
11981 looking to see where this register gets its value. If the
11982 register is initialized from the frame pointer plus an offset
11983 then we are in luck and we can continue, otherwise we give up.
11985 This code is exercised by producing debugging information
11986 for a function with arguments like this:
11988 double func (double a, double b, int c, double d) {return d;}
11990 Without this code the stab for parameter 'd' will be set to
11991 an offset of 0 from the frame pointer, rather than 8. */
11993 /* The if() statement says:
11995 If the insn is a normal instruction
11996 and if the insn is setting the value in a register
11997 and if the register being set is the register holding the address of the argument
11998 and if the address is computing by an addition
11999 that involves adding to a register
12000 which is the frame pointer
12005 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12007 if ( GET_CODE (insn
) == INSN
12008 && GET_CODE (PATTERN (insn
)) == SET
12009 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
12010 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
12011 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
12012 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12013 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
12016 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
12025 warning (0, "unable to compute real location of stacked parameter");
12026 value
= 8; /* XXX magic hack */
12032 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12035 if ((MASK) & insn_flags) \
12036 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
12037 BUILT_IN_MD, NULL, NULL_TREE); \
12041 struct builtin_description
12043 const unsigned int mask
;
12044 const enum insn_code icode
;
12045 const char * const name
;
12046 const enum arm_builtins code
;
12047 const enum rtx_code comparison
;
12048 const unsigned int flag
;
12051 static const struct builtin_description bdesc_2arg
[] =
12053 #define IWMMXT_BUILTIN(code, string, builtin) \
12054 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12055 ARM_BUILTIN_##builtin, 0, 0 },
12057 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12058 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12059 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12060 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12061 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12062 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12063 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12064 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12065 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12066 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12067 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12068 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12069 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12070 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12071 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12072 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12073 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12074 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12075 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12076 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12077 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12078 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12079 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12080 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12081 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12082 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12083 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12084 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12085 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12086 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12087 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12088 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12089 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12090 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12091 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12092 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12093 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12094 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12095 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12096 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12097 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12098 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12099 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12100 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12101 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12102 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12103 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12104 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12105 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12106 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12107 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12108 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12109 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12110 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12111 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12112 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12113 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12114 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12116 #define IWMMXT_BUILTIN2(code, builtin) \
12117 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12119 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12120 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12121 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12122 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12123 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12124 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12125 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12126 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12127 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12128 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12129 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12130 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12131 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12132 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12133 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12134 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12135 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12136 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12137 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12138 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12139 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12140 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12141 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12142 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12143 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12144 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12145 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12146 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12147 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12148 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12149 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12150 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12153 static const struct builtin_description bdesc_1arg
[] =
12155 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12156 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12157 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12158 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12159 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12160 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12161 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12162 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12163 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12164 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12165 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12166 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12167 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12168 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12169 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12170 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12171 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12172 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12175 /* Set up all the iWMMXt builtins. This is
12176 not called if TARGET_IWMMXT is zero. */
12179 arm_init_iwmmxt_builtins (void)
12181 const struct builtin_description
* d
;
12183 tree endlink
= void_list_node
;
12185 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12186 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12187 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12190 = build_function_type (integer_type_node
,
12191 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12192 tree v8qi_ftype_v8qi_v8qi_int
12193 = build_function_type (V8QI_type_node
,
12194 tree_cons (NULL_TREE
, V8QI_type_node
,
12195 tree_cons (NULL_TREE
, V8QI_type_node
,
12196 tree_cons (NULL_TREE
,
12199 tree v4hi_ftype_v4hi_int
12200 = build_function_type (V4HI_type_node
,
12201 tree_cons (NULL_TREE
, V4HI_type_node
,
12202 tree_cons (NULL_TREE
, integer_type_node
,
12204 tree v2si_ftype_v2si_int
12205 = build_function_type (V2SI_type_node
,
12206 tree_cons (NULL_TREE
, V2SI_type_node
,
12207 tree_cons (NULL_TREE
, integer_type_node
,
12209 tree v2si_ftype_di_di
12210 = build_function_type (V2SI_type_node
,
12211 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12212 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12214 tree di_ftype_di_int
12215 = build_function_type (long_long_integer_type_node
,
12216 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12217 tree_cons (NULL_TREE
, integer_type_node
,
12219 tree di_ftype_di_int_int
12220 = build_function_type (long_long_integer_type_node
,
12221 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12222 tree_cons (NULL_TREE
, integer_type_node
,
12223 tree_cons (NULL_TREE
,
12226 tree int_ftype_v8qi
12227 = build_function_type (integer_type_node
,
12228 tree_cons (NULL_TREE
, V8QI_type_node
,
12230 tree int_ftype_v4hi
12231 = build_function_type (integer_type_node
,
12232 tree_cons (NULL_TREE
, V4HI_type_node
,
12234 tree int_ftype_v2si
12235 = build_function_type (integer_type_node
,
12236 tree_cons (NULL_TREE
, V2SI_type_node
,
12238 tree int_ftype_v8qi_int
12239 = build_function_type (integer_type_node
,
12240 tree_cons (NULL_TREE
, V8QI_type_node
,
12241 tree_cons (NULL_TREE
, integer_type_node
,
12243 tree int_ftype_v4hi_int
12244 = build_function_type (integer_type_node
,
12245 tree_cons (NULL_TREE
, V4HI_type_node
,
12246 tree_cons (NULL_TREE
, integer_type_node
,
12248 tree int_ftype_v2si_int
12249 = build_function_type (integer_type_node
,
12250 tree_cons (NULL_TREE
, V2SI_type_node
,
12251 tree_cons (NULL_TREE
, integer_type_node
,
12253 tree v8qi_ftype_v8qi_int_int
12254 = build_function_type (V8QI_type_node
,
12255 tree_cons (NULL_TREE
, V8QI_type_node
,
12256 tree_cons (NULL_TREE
, integer_type_node
,
12257 tree_cons (NULL_TREE
,
12260 tree v4hi_ftype_v4hi_int_int
12261 = build_function_type (V4HI_type_node
,
12262 tree_cons (NULL_TREE
, V4HI_type_node
,
12263 tree_cons (NULL_TREE
, integer_type_node
,
12264 tree_cons (NULL_TREE
,
12267 tree v2si_ftype_v2si_int_int
12268 = build_function_type (V2SI_type_node
,
12269 tree_cons (NULL_TREE
, V2SI_type_node
,
12270 tree_cons (NULL_TREE
, integer_type_node
,
12271 tree_cons (NULL_TREE
,
12274 /* Miscellaneous. */
12275 tree v8qi_ftype_v4hi_v4hi
12276 = build_function_type (V8QI_type_node
,
12277 tree_cons (NULL_TREE
, V4HI_type_node
,
12278 tree_cons (NULL_TREE
, V4HI_type_node
,
12280 tree v4hi_ftype_v2si_v2si
12281 = build_function_type (V4HI_type_node
,
12282 tree_cons (NULL_TREE
, V2SI_type_node
,
12283 tree_cons (NULL_TREE
, V2SI_type_node
,
12285 tree v2si_ftype_v4hi_v4hi
12286 = build_function_type (V2SI_type_node
,
12287 tree_cons (NULL_TREE
, V4HI_type_node
,
12288 tree_cons (NULL_TREE
, V4HI_type_node
,
12290 tree v2si_ftype_v8qi_v8qi
12291 = build_function_type (V2SI_type_node
,
12292 tree_cons (NULL_TREE
, V8QI_type_node
,
12293 tree_cons (NULL_TREE
, V8QI_type_node
,
12295 tree v4hi_ftype_v4hi_di
12296 = build_function_type (V4HI_type_node
,
12297 tree_cons (NULL_TREE
, V4HI_type_node
,
12298 tree_cons (NULL_TREE
,
12299 long_long_integer_type_node
,
12301 tree v2si_ftype_v2si_di
12302 = build_function_type (V2SI_type_node
,
12303 tree_cons (NULL_TREE
, V2SI_type_node
,
12304 tree_cons (NULL_TREE
,
12305 long_long_integer_type_node
,
12307 tree void_ftype_int_int
12308 = build_function_type (void_type_node
,
12309 tree_cons (NULL_TREE
, integer_type_node
,
12310 tree_cons (NULL_TREE
, integer_type_node
,
12313 = build_function_type (long_long_unsigned_type_node
, endlink
);
12315 = build_function_type (long_long_integer_type_node
,
12316 tree_cons (NULL_TREE
, V8QI_type_node
,
12319 = build_function_type (long_long_integer_type_node
,
12320 tree_cons (NULL_TREE
, V4HI_type_node
,
12323 = build_function_type (long_long_integer_type_node
,
12324 tree_cons (NULL_TREE
, V2SI_type_node
,
12326 tree v2si_ftype_v4hi
12327 = build_function_type (V2SI_type_node
,
12328 tree_cons (NULL_TREE
, V4HI_type_node
,
12330 tree v4hi_ftype_v8qi
12331 = build_function_type (V4HI_type_node
,
12332 tree_cons (NULL_TREE
, V8QI_type_node
,
12335 tree di_ftype_di_v4hi_v4hi
12336 = build_function_type (long_long_unsigned_type_node
,
12337 tree_cons (NULL_TREE
,
12338 long_long_unsigned_type_node
,
12339 tree_cons (NULL_TREE
, V4HI_type_node
,
12340 tree_cons (NULL_TREE
,
12344 tree di_ftype_v4hi_v4hi
12345 = build_function_type (long_long_unsigned_type_node
,
12346 tree_cons (NULL_TREE
, V4HI_type_node
,
12347 tree_cons (NULL_TREE
, V4HI_type_node
,
12350 /* Normal vector binops. */
12351 tree v8qi_ftype_v8qi_v8qi
12352 = build_function_type (V8QI_type_node
,
12353 tree_cons (NULL_TREE
, V8QI_type_node
,
12354 tree_cons (NULL_TREE
, V8QI_type_node
,
12356 tree v4hi_ftype_v4hi_v4hi
12357 = build_function_type (V4HI_type_node
,
12358 tree_cons (NULL_TREE
, V4HI_type_node
,
12359 tree_cons (NULL_TREE
, V4HI_type_node
,
12361 tree v2si_ftype_v2si_v2si
12362 = build_function_type (V2SI_type_node
,
12363 tree_cons (NULL_TREE
, V2SI_type_node
,
12364 tree_cons (NULL_TREE
, V2SI_type_node
,
12366 tree di_ftype_di_di
12367 = build_function_type (long_long_unsigned_type_node
,
12368 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12369 tree_cons (NULL_TREE
,
12370 long_long_unsigned_type_node
,
12373 /* Add all builtins that are more or less simple operations on two
12375 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12377 /* Use one of the operands; the target can have a different mode for
12378 mask-generating compares. */
12379 enum machine_mode mode
;
12385 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12390 type
= v8qi_ftype_v8qi_v8qi
;
12393 type
= v4hi_ftype_v4hi_v4hi
;
12396 type
= v2si_ftype_v2si_v2si
;
12399 type
= di_ftype_di_di
;
12403 gcc_unreachable ();
12406 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12409 /* Add the remaining MMX insns with somewhat more complicated types. */
12410 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12411 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12412 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12414 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12415 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12416 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12417 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12418 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12419 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12421 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12422 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12423 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12424 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12425 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12426 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12428 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12429 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12430 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12431 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12432 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12433 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12435 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12436 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12437 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12438 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12439 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12440 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12442 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12444 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12445 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12446 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12447 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12449 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12450 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12451 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12452 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12453 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12454 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12455 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12456 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12457 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12459 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12460 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12461 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12463 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12464 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12465 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12467 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12468 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12469 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12470 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12471 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12472 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12474 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12475 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12476 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12477 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12478 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12479 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12480 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12481 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12482 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12483 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12484 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12485 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12487 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12488 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12489 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12490 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12492 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12493 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12494 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12495 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12496 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12497 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12498 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12502 arm_init_tls_builtins (void)
12505 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12506 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12508 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12509 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
12510 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12511 NULL
, const_nothrow
);
12515 arm_init_builtins (void)
12517 arm_init_tls_builtins ();
12519 if (TARGET_REALLY_IWMMXT
)
12520 arm_init_iwmmxt_builtins ();
12523 /* Errors in the source file can cause expand_expr to return const0_rtx
12524 where we expect a vector. To avoid crashing, use one of the vector
12525 clear instructions. */
12528 safe_vector_operand (rtx x
, enum machine_mode mode
)
12530 if (x
!= const0_rtx
)
12532 x
= gen_reg_rtx (mode
);
12534 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12535 : gen_rtx_SUBREG (DImode
, x
, 0)));
12539 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12542 arm_expand_binop_builtin (enum insn_code icode
,
12543 tree arglist
, rtx target
)
12546 tree arg0
= TREE_VALUE (arglist
);
12547 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12548 rtx op0
= expand_normal (arg0
);
12549 rtx op1
= expand_normal (arg1
);
12550 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12551 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12552 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12554 if (VECTOR_MODE_P (mode0
))
12555 op0
= safe_vector_operand (op0
, mode0
);
12556 if (VECTOR_MODE_P (mode1
))
12557 op1
= safe_vector_operand (op1
, mode1
);
12560 || GET_MODE (target
) != tmode
12561 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12562 target
= gen_reg_rtx (tmode
);
12564 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12566 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12567 op0
= copy_to_mode_reg (mode0
, op0
);
12568 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12569 op1
= copy_to_mode_reg (mode1
, op1
);
12571 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12578 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12581 arm_expand_unop_builtin (enum insn_code icode
,
12582 tree arglist
, rtx target
, int do_load
)
12585 tree arg0
= TREE_VALUE (arglist
);
12586 rtx op0
= expand_normal (arg0
);
12587 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12588 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12591 || GET_MODE (target
) != tmode
12592 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12593 target
= gen_reg_rtx (tmode
);
12595 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12598 if (VECTOR_MODE_P (mode0
))
12599 op0
= safe_vector_operand (op0
, mode0
);
12601 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12602 op0
= copy_to_mode_reg (mode0
, op0
);
12605 pat
= GEN_FCN (icode
) (target
, op0
);
12612 /* Expand an expression EXP that calls a built-in function,
12613 with result going to TARGET if that's convenient
12614 (and in mode MODE if that's convenient).
12615 SUBTARGET may be used as the target for computing one of EXP's operands.
12616 IGNORE is nonzero if the value is to be ignored. */
12619 arm_expand_builtin (tree exp
,
12621 rtx subtarget ATTRIBUTE_UNUSED
,
12622 enum machine_mode mode ATTRIBUTE_UNUSED
,
12623 int ignore ATTRIBUTE_UNUSED
)
12625 const struct builtin_description
* d
;
12626 enum insn_code icode
;
12627 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12628 tree arglist
= TREE_OPERAND (exp
, 1);
12636 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12638 enum machine_mode tmode
;
12639 enum machine_mode mode0
;
12640 enum machine_mode mode1
;
12641 enum machine_mode mode2
;
12645 case ARM_BUILTIN_TEXTRMSB
:
12646 case ARM_BUILTIN_TEXTRMUB
:
12647 case ARM_BUILTIN_TEXTRMSH
:
12648 case ARM_BUILTIN_TEXTRMUH
:
12649 case ARM_BUILTIN_TEXTRMSW
:
12650 case ARM_BUILTIN_TEXTRMUW
:
12651 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12652 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12653 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12654 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12655 : CODE_FOR_iwmmxt_textrmw
);
12657 arg0
= TREE_VALUE (arglist
);
12658 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12659 op0
= expand_normal (arg0
);
12660 op1
= expand_normal (arg1
);
12661 tmode
= insn_data
[icode
].operand
[0].mode
;
12662 mode0
= insn_data
[icode
].operand
[1].mode
;
12663 mode1
= insn_data
[icode
].operand
[2].mode
;
12665 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12666 op0
= copy_to_mode_reg (mode0
, op0
);
12667 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12669 /* @@@ better error message */
12670 error ("selector must be an immediate");
12671 return gen_reg_rtx (tmode
);
12674 || GET_MODE (target
) != tmode
12675 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12676 target
= gen_reg_rtx (tmode
);
12677 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12683 case ARM_BUILTIN_TINSRB
:
12684 case ARM_BUILTIN_TINSRH
:
12685 case ARM_BUILTIN_TINSRW
:
12686 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12687 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12688 : CODE_FOR_iwmmxt_tinsrw
);
12689 arg0
= TREE_VALUE (arglist
);
12690 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12691 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12692 op0
= expand_normal (arg0
);
12693 op1
= expand_normal (arg1
);
12694 op2
= expand_normal (arg2
);
12695 tmode
= insn_data
[icode
].operand
[0].mode
;
12696 mode0
= insn_data
[icode
].operand
[1].mode
;
12697 mode1
= insn_data
[icode
].operand
[2].mode
;
12698 mode2
= insn_data
[icode
].operand
[3].mode
;
12700 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12701 op0
= copy_to_mode_reg (mode0
, op0
);
12702 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12703 op1
= copy_to_mode_reg (mode1
, op1
);
12704 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12706 /* @@@ better error message */
12707 error ("selector must be an immediate");
12711 || GET_MODE (target
) != tmode
12712 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12713 target
= gen_reg_rtx (tmode
);
12714 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12720 case ARM_BUILTIN_SETWCX
:
12721 arg0
= TREE_VALUE (arglist
);
12722 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12723 op0
= force_reg (SImode
, expand_normal (arg0
));
12724 op1
= expand_normal (arg1
);
12725 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12728 case ARM_BUILTIN_GETWCX
:
12729 arg0
= TREE_VALUE (arglist
);
12730 op0
= expand_normal (arg0
);
12731 target
= gen_reg_rtx (SImode
);
12732 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12735 case ARM_BUILTIN_WSHUFH
:
12736 icode
= CODE_FOR_iwmmxt_wshufh
;
12737 arg0
= TREE_VALUE (arglist
);
12738 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12739 op0
= expand_normal (arg0
);
12740 op1
= expand_normal (arg1
);
12741 tmode
= insn_data
[icode
].operand
[0].mode
;
12742 mode1
= insn_data
[icode
].operand
[1].mode
;
12743 mode2
= insn_data
[icode
].operand
[2].mode
;
12745 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12746 op0
= copy_to_mode_reg (mode1
, op0
);
12747 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12749 /* @@@ better error message */
12750 error ("mask must be an immediate");
12754 || GET_MODE (target
) != tmode
12755 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12756 target
= gen_reg_rtx (tmode
);
12757 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12763 case ARM_BUILTIN_WSADB
:
12764 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12765 case ARM_BUILTIN_WSADH
:
12766 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12767 case ARM_BUILTIN_WSADBZ
:
12768 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12769 case ARM_BUILTIN_WSADHZ
:
12770 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12772 /* Several three-argument builtins. */
12773 case ARM_BUILTIN_WMACS
:
12774 case ARM_BUILTIN_WMACU
:
12775 case ARM_BUILTIN_WALIGN
:
12776 case ARM_BUILTIN_TMIA
:
12777 case ARM_BUILTIN_TMIAPH
:
12778 case ARM_BUILTIN_TMIATT
:
12779 case ARM_BUILTIN_TMIATB
:
12780 case ARM_BUILTIN_TMIABT
:
12781 case ARM_BUILTIN_TMIABB
:
12782 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12783 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12784 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12785 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12786 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12787 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12788 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12789 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12790 : CODE_FOR_iwmmxt_walign
);
12791 arg0
= TREE_VALUE (arglist
);
12792 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12793 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12794 op0
= expand_normal (arg0
);
12795 op1
= expand_normal (arg1
);
12796 op2
= expand_normal (arg2
);
12797 tmode
= insn_data
[icode
].operand
[0].mode
;
12798 mode0
= insn_data
[icode
].operand
[1].mode
;
12799 mode1
= insn_data
[icode
].operand
[2].mode
;
12800 mode2
= insn_data
[icode
].operand
[3].mode
;
12802 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12803 op0
= copy_to_mode_reg (mode0
, op0
);
12804 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12805 op1
= copy_to_mode_reg (mode1
, op1
);
12806 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12807 op2
= copy_to_mode_reg (mode2
, op2
);
12809 || GET_MODE (target
) != tmode
12810 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12811 target
= gen_reg_rtx (tmode
);
12812 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12818 case ARM_BUILTIN_WZERO
:
12819 target
= gen_reg_rtx (DImode
);
12820 emit_insn (gen_iwmmxt_clrdi (target
));
12823 case ARM_BUILTIN_THREAD_POINTER
:
12824 return arm_load_tp (target
);
12830 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12831 if (d
->code
== (const enum arm_builtins
) fcode
)
12832 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12834 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12835 if (d
->code
== (const enum arm_builtins
) fcode
)
12836 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12838 /* @@@ Should really do something sensible here. */
12842 /* Return the number (counting from 0) of
12843 the least significant set bit in MASK. */
12846 number_of_first_bit_set (unsigned mask
)
12851 (mask
& (1 << bit
)) == 0;
12858 /* Emit code to push or pop registers to or from the stack. F is the
12859 assembly file. MASK is the registers to push or pop. PUSH is
12860 nonzero if we should push, and zero if we should pop. For debugging
12861 output, if pushing, adjust CFA_OFFSET by the amount of space added
12862 to the stack. REAL_REGS should have the same number of bits set as
12863 MASK, and will be used instead (in the same order) to describe which
12864 registers were saved - this is used to mark the save slots when we
12865 push high registers after moving them to low registers. */
12867 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12868 unsigned long real_regs
)
12871 int lo_mask
= mask
& 0xFF;
12872 int pushed_words
= 0;
12876 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12878 /* Special case. Do not generate a POP PC statement here, do it in
12880 thumb_exit (f
, -1);
12884 if (ARM_EABI_UNWIND_TABLES
&& push
)
12886 fprintf (f
, "\t.save\t{");
12887 for (regno
= 0; regno
< 15; regno
++)
12889 if (real_regs
& (1 << regno
))
12891 if (real_regs
& ((1 << regno
) -1))
12893 asm_fprintf (f
, "%r", regno
);
12896 fprintf (f
, "}\n");
12899 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12901 /* Look at the low registers first. */
12902 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12906 asm_fprintf (f
, "%r", regno
);
12908 if ((lo_mask
& ~1) != 0)
12915 if (push
&& (mask
& (1 << LR_REGNUM
)))
12917 /* Catch pushing the LR. */
12921 asm_fprintf (f
, "%r", LR_REGNUM
);
12925 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12927 /* Catch popping the PC. */
12928 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12929 || current_function_calls_eh_return
)
12931 /* The PC is never poped directly, instead
12932 it is popped into r3 and then BX is used. */
12933 fprintf (f
, "}\n");
12935 thumb_exit (f
, -1);
12944 asm_fprintf (f
, "%r", PC_REGNUM
);
12948 fprintf (f
, "}\n");
12950 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12952 char *l
= dwarf2out_cfi_label ();
12953 int pushed_mask
= real_regs
;
12955 *cfa_offset
+= pushed_words
* 4;
12956 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12959 pushed_mask
= real_regs
;
12960 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12962 if (pushed_mask
& 1)
12963 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12968 /* Generate code to return from a thumb function.
12969 If 'reg_containing_return_addr' is -1, then the return address is
12970 actually on the stack, at the stack pointer. */
12972 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12974 unsigned regs_available_for_popping
;
12975 unsigned regs_to_pop
;
12977 unsigned available
;
12981 int restore_a4
= FALSE
;
12983 /* Compute the registers we need to pop. */
12987 if (reg_containing_return_addr
== -1)
12989 regs_to_pop
|= 1 << LR_REGNUM
;
12993 if (TARGET_BACKTRACE
)
12995 /* Restore the (ARM) frame pointer and stack pointer. */
12996 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
13000 /* If there is nothing to pop then just emit the BX instruction and
13002 if (pops_needed
== 0)
13004 if (current_function_calls_eh_return
)
13005 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13007 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13010 /* Otherwise if we are not supporting interworking and we have not created
13011 a backtrace structure and the function was not entered in ARM mode then
13012 just pop the return address straight into the PC. */
13013 else if (!TARGET_INTERWORK
13014 && !TARGET_BACKTRACE
13015 && !is_called_in_ARM_mode (current_function_decl
)
13016 && !current_function_calls_eh_return
)
13018 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
13022 /* Find out how many of the (return) argument registers we can corrupt. */
13023 regs_available_for_popping
= 0;
13025 /* If returning via __builtin_eh_return, the bottom three registers
13026 all contain information needed for the return. */
13027 if (current_function_calls_eh_return
)
13031 /* If we can deduce the registers used from the function's
13032 return value. This is more reliable that examining
13033 regs_ever_live[] because that will be set if the register is
13034 ever used in the function, not just if the register is used
13035 to hold a return value. */
13037 if (current_function_return_rtx
!= 0)
13038 mode
= GET_MODE (current_function_return_rtx
);
13040 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13042 size
= GET_MODE_SIZE (mode
);
13046 /* In a void function we can use any argument register.
13047 In a function that returns a structure on the stack
13048 we can use the second and third argument registers. */
13049 if (mode
== VOIDmode
)
13050 regs_available_for_popping
=
13051 (1 << ARG_REGISTER (1))
13052 | (1 << ARG_REGISTER (2))
13053 | (1 << ARG_REGISTER (3));
13055 regs_available_for_popping
=
13056 (1 << ARG_REGISTER (2))
13057 | (1 << ARG_REGISTER (3));
13059 else if (size
<= 4)
13060 regs_available_for_popping
=
13061 (1 << ARG_REGISTER (2))
13062 | (1 << ARG_REGISTER (3));
13063 else if (size
<= 8)
13064 regs_available_for_popping
=
13065 (1 << ARG_REGISTER (3));
13068 /* Match registers to be popped with registers into which we pop them. */
13069 for (available
= regs_available_for_popping
,
13070 required
= regs_to_pop
;
13071 required
!= 0 && available
!= 0;
13072 available
&= ~(available
& - available
),
13073 required
&= ~(required
& - required
))
13076 /* If we have any popping registers left over, remove them. */
13078 regs_available_for_popping
&= ~available
;
13080 /* Otherwise if we need another popping register we can use
13081 the fourth argument register. */
13082 else if (pops_needed
)
13084 /* If we have not found any free argument registers and
13085 reg a4 contains the return address, we must move it. */
13086 if (regs_available_for_popping
== 0
13087 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13089 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13090 reg_containing_return_addr
= LR_REGNUM
;
13092 else if (size
> 12)
13094 /* Register a4 is being used to hold part of the return value,
13095 but we have dire need of a free, low register. */
13098 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13101 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13103 /* The fourth argument register is available. */
13104 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13110 /* Pop as many registers as we can. */
13111 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13112 regs_available_for_popping
);
13114 /* Process the registers we popped. */
13115 if (reg_containing_return_addr
== -1)
13117 /* The return address was popped into the lowest numbered register. */
13118 regs_to_pop
&= ~(1 << LR_REGNUM
);
13120 reg_containing_return_addr
=
13121 number_of_first_bit_set (regs_available_for_popping
);
13123 /* Remove this register for the mask of available registers, so that
13124 the return address will not be corrupted by further pops. */
13125 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13128 /* If we popped other registers then handle them here. */
13129 if (regs_available_for_popping
)
13133 /* Work out which register currently contains the frame pointer. */
13134 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13136 /* Move it into the correct place. */
13137 asm_fprintf (f
, "\tmov\t%r, %r\n",
13138 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13140 /* (Temporarily) remove it from the mask of popped registers. */
13141 regs_available_for_popping
&= ~(1 << frame_pointer
);
13142 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13144 if (regs_available_for_popping
)
13148 /* We popped the stack pointer as well,
13149 find the register that contains it. */
13150 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13152 /* Move it into the stack register. */
13153 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13155 /* At this point we have popped all necessary registers, so
13156 do not worry about restoring regs_available_for_popping
13157 to its correct value:
13159 assert (pops_needed == 0)
13160 assert (regs_available_for_popping == (1 << frame_pointer))
13161 assert (regs_to_pop == (1 << STACK_POINTER)) */
13165 /* Since we have just move the popped value into the frame
13166 pointer, the popping register is available for reuse, and
13167 we know that we still have the stack pointer left to pop. */
13168 regs_available_for_popping
|= (1 << frame_pointer
);
13172 /* If we still have registers left on the stack, but we no longer have
13173 any registers into which we can pop them, then we must move the return
13174 address into the link register and make available the register that
13176 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13178 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13180 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13181 reg_containing_return_addr
);
13183 reg_containing_return_addr
= LR_REGNUM
;
13186 /* If we have registers left on the stack then pop some more.
13187 We know that at most we will want to pop FP and SP. */
13188 if (pops_needed
> 0)
13193 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13194 regs_available_for_popping
);
13196 /* We have popped either FP or SP.
13197 Move whichever one it is into the correct register. */
13198 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13199 move_to
= number_of_first_bit_set (regs_to_pop
);
13201 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13203 regs_to_pop
&= ~(1 << move_to
);
13208 /* If we still have not popped everything then we must have only
13209 had one register available to us and we are now popping the SP. */
13210 if (pops_needed
> 0)
13214 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13215 regs_available_for_popping
);
13217 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13219 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13221 assert (regs_to_pop == (1 << STACK_POINTER))
13222 assert (pops_needed == 1)
13226 /* If necessary restore the a4 register. */
13229 if (reg_containing_return_addr
!= LR_REGNUM
)
13231 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13232 reg_containing_return_addr
= LR_REGNUM
;
13235 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13238 if (current_function_calls_eh_return
)
13239 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13241 /* Return to caller. */
13242 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13247 thumb_final_prescan_insn (rtx insn
)
13249 if (flag_print_asm_name
)
13250 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13251 INSN_ADDRESSES (INSN_UID (insn
)));
13255 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13257 unsigned HOST_WIDE_INT mask
= 0xff;
13260 if (val
== 0) /* XXX */
13263 for (i
= 0; i
< 25; i
++)
13264 if ((val
& (mask
<< i
)) == val
)
13270 /* Returns nonzero if the current function contains,
13271 or might contain a far jump. */
13273 thumb_far_jump_used_p (void)
13277 /* This test is only important for leaf functions. */
13278 /* assert (!leaf_function_p ()); */
13280 /* If we have already decided that far jumps may be used,
13281 do not bother checking again, and always return true even if
13282 it turns out that they are not being used. Once we have made
13283 the decision that far jumps are present (and that hence the link
13284 register will be pushed onto the stack) we cannot go back on it. */
13285 if (cfun
->machine
->far_jump_used
)
13288 /* If this function is not being called from the prologue/epilogue
13289 generation code then it must be being called from the
13290 INITIAL_ELIMINATION_OFFSET macro. */
13291 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13293 /* In this case we know that we are being asked about the elimination
13294 of the arg pointer register. If that register is not being used,
13295 then there are no arguments on the stack, and we do not have to
13296 worry that a far jump might force the prologue to push the link
13297 register, changing the stack offsets. In this case we can just
13298 return false, since the presence of far jumps in the function will
13299 not affect stack offsets.
13301 If the arg pointer is live (or if it was live, but has now been
13302 eliminated and so set to dead) then we do have to test to see if
13303 the function might contain a far jump. This test can lead to some
13304 false negatives, since before reload is completed, then length of
13305 branch instructions is not known, so gcc defaults to returning their
13306 longest length, which in turn sets the far jump attribute to true.
13308 A false negative will not result in bad code being generated, but it
13309 will result in a needless push and pop of the link register. We
13310 hope that this does not occur too often.
13312 If we need doubleword stack alignment this could affect the other
13313 elimination offsets so we can't risk getting it wrong. */
13314 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13315 cfun
->machine
->arg_pointer_live
= 1;
13316 else if (!cfun
->machine
->arg_pointer_live
)
13320 /* Check to see if the function contains a branch
13321 insn with the far jump attribute set. */
13322 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13324 if (GET_CODE (insn
) == JUMP_INSN
13325 /* Ignore tablejump patterns. */
13326 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13327 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13328 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13331 /* Record the fact that we have decided that
13332 the function does use far jumps. */
13333 cfun
->machine
->far_jump_used
= 1;
13341 /* Return nonzero if FUNC must be entered in ARM mode. */
13343 is_called_in_ARM_mode (tree func
)
13345 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13347 /* Ignore the problem about functions whose address is taken. */
13348 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13352 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13358 /* The bits which aren't usefully expanded as rtl. */
13360 thumb_unexpanded_epilogue (void)
13363 unsigned long live_regs_mask
= 0;
13364 int high_regs_pushed
= 0;
13365 int had_to_push_lr
;
13368 if (return_used_this_function
)
13371 if (IS_NAKED (arm_current_func_type ()))
13374 live_regs_mask
= thumb_compute_save_reg_mask ();
13375 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13377 /* If we can deduce the registers used from the function's return value.
13378 This is more reliable that examining regs_ever_live[] because that
13379 will be set if the register is ever used in the function, not just if
13380 the register is used to hold a return value. */
13381 size
= arm_size_return_regs ();
13383 /* The prolog may have pushed some high registers to use as
13384 work registers. e.g. the testsuite file:
13385 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13386 compiles to produce:
13387 push {r4, r5, r6, r7, lr}
13391 as part of the prolog. We have to undo that pushing here. */
13393 if (high_regs_pushed
)
13395 unsigned long mask
= live_regs_mask
& 0xff;
13398 /* The available low registers depend on the size of the value we are
13406 /* Oh dear! We have no low registers into which we can pop
13409 ("no low registers available for popping high registers");
13411 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13412 if (live_regs_mask
& (1 << next_hi_reg
))
13415 while (high_regs_pushed
)
13417 /* Find lo register(s) into which the high register(s) can
13419 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13421 if (mask
& (1 << regno
))
13422 high_regs_pushed
--;
13423 if (high_regs_pushed
== 0)
13427 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13429 /* Pop the values into the low register(s). */
13430 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13432 /* Move the value(s) into the high registers. */
13433 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13435 if (mask
& (1 << regno
))
13437 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13440 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13441 if (live_regs_mask
& (1 << next_hi_reg
))
13446 live_regs_mask
&= ~0x0f00;
13449 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13450 live_regs_mask
&= 0xff;
13452 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13454 /* Pop the return address into the PC. */
13455 if (had_to_push_lr
)
13456 live_regs_mask
|= 1 << PC_REGNUM
;
13458 /* Either no argument registers were pushed or a backtrace
13459 structure was created which includes an adjusted stack
13460 pointer, so just pop everything. */
13461 if (live_regs_mask
)
13462 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13465 /* We have either just popped the return address into the
13466 PC or it is was kept in LR for the entire function. */
13467 if (!had_to_push_lr
)
13468 thumb_exit (asm_out_file
, LR_REGNUM
);
13472 /* Pop everything but the return address. */
13473 if (live_regs_mask
)
13474 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13477 if (had_to_push_lr
)
13481 /* We have no free low regs, so save one. */
13482 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13486 /* Get the return address into a temporary register. */
13487 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13488 1 << LAST_ARG_REGNUM
);
13492 /* Move the return address to lr. */
13493 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13495 /* Restore the low register. */
13496 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13501 regno
= LAST_ARG_REGNUM
;
13506 /* Remove the argument registers that were pushed onto the stack. */
13507 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13508 SP_REGNUM
, SP_REGNUM
,
13509 current_function_pretend_args_size
);
13511 thumb_exit (asm_out_file
, regno
);
13517 /* Functions to save and restore machine-specific function data. */
13518 static struct machine_function
*
13519 arm_init_machine_status (void)
13521 struct machine_function
*machine
;
13522 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13524 #if ARM_FT_UNKNOWN != 0
13525 machine
->func_type
= ARM_FT_UNKNOWN
;
13530 /* Return an RTX indicating where the return address to the
13531 calling function can be found. */
13533 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13538 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13541 /* Do anything needed before RTL is emitted for each function. */
13543 arm_init_expanders (void)
13545 /* Arrange to initialize and mark the machine per-function status. */
13546 init_machine_status
= arm_init_machine_status
;
13548 /* This is to stop the combine pass optimizing away the alignment
13549 adjustment of va_arg. */
13550 /* ??? It is claimed that this should not be necessary. */
13552 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13556 /* Like arm_compute_initial_elimination offset. Simpler because there
13557 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13558 to point at the base of the local variables after static stack
13559 space for a function has been allocated. */
13562 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13564 arm_stack_offsets
*offsets
;
13566 offsets
= arm_get_frame_offsets ();
13570 case ARG_POINTER_REGNUM
:
13573 case STACK_POINTER_REGNUM
:
13574 return offsets
->outgoing_args
- offsets
->saved_args
;
13576 case FRAME_POINTER_REGNUM
:
13577 return offsets
->soft_frame
- offsets
->saved_args
;
13579 case ARM_HARD_FRAME_POINTER_REGNUM
:
13580 return offsets
->saved_regs
- offsets
->saved_args
;
13582 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13583 return offsets
->locals_base
- offsets
->saved_args
;
13586 gcc_unreachable ();
13590 case FRAME_POINTER_REGNUM
:
13593 case STACK_POINTER_REGNUM
:
13594 return offsets
->outgoing_args
- offsets
->soft_frame
;
13596 case ARM_HARD_FRAME_POINTER_REGNUM
:
13597 return offsets
->saved_regs
- offsets
->soft_frame
;
13599 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13600 return offsets
->locals_base
- offsets
->soft_frame
;
13603 gcc_unreachable ();
13608 gcc_unreachable ();
13613 /* Generate the rest of a function's prologue. */
13615 thumb_expand_prologue (void)
13619 HOST_WIDE_INT amount
;
13620 arm_stack_offsets
*offsets
;
13621 unsigned long func_type
;
13623 unsigned long live_regs_mask
;
13625 func_type
= arm_current_func_type ();
13627 /* Naked functions don't have prologues. */
13628 if (IS_NAKED (func_type
))
13631 if (IS_INTERRUPT (func_type
))
13633 error ("interrupt Service Routines cannot be coded in Thumb mode");
13637 live_regs_mask
= thumb_compute_save_reg_mask ();
13638 /* Load the pic register before setting the frame pointer,
13639 so we can use r7 as a temporary work register. */
13640 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
13641 arm_load_pic_register (live_regs_mask
);
13643 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13644 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13645 stack_pointer_rtx
);
13647 offsets
= arm_get_frame_offsets ();
13648 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13653 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13654 GEN_INT (- amount
)));
13655 RTX_FRAME_RELATED_P (insn
) = 1;
13661 /* The stack decrement is too big for an immediate value in a single
13662 insn. In theory we could issue multiple subtracts, but after
13663 three of them it becomes more space efficient to place the full
13664 value in the constant pool and load into a register. (Also the
13665 ARM debugger really likes to see only one stack decrement per
13666 function). So instead we look for a scratch register into which
13667 we can load the decrement, and then we subtract this from the
13668 stack pointer. Unfortunately on the thumb the only available
13669 scratch registers are the argument registers, and we cannot use
13670 these as they may hold arguments to the function. Instead we
13671 attempt to locate a call preserved register which is used by this
13672 function. If we can find one, then we know that it will have
13673 been pushed at the start of the prologue and so we can corrupt
13675 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13676 if (live_regs_mask
& (1 << regno
)
13677 && !(frame_pointer_needed
13678 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13681 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13683 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13685 /* Choose an arbitrary, non-argument low register. */
13686 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13688 /* Save it by copying it into a high, scratch register. */
13689 emit_insn (gen_movsi (spare
, reg
));
13690 /* Add a USE to stop propagate_one_insn() from barfing. */
13691 emit_insn (gen_prologue_use (spare
));
13693 /* Decrement the stack. */
13694 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13695 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13696 stack_pointer_rtx
, reg
));
13697 RTX_FRAME_RELATED_P (insn
) = 1;
13698 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13699 plus_constant (stack_pointer_rtx
,
13701 RTX_FRAME_RELATED_P (dwarf
) = 1;
13703 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13706 /* Restore the low register's original value. */
13707 emit_insn (gen_movsi (reg
, spare
));
13709 /* Emit a USE of the restored scratch register, so that flow
13710 analysis will not consider the restore redundant. The
13711 register won't be used again in this function and isn't
13712 restored by the epilogue. */
13713 emit_insn (gen_prologue_use (reg
));
13717 reg
= gen_rtx_REG (SImode
, regno
);
13719 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13721 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13722 stack_pointer_rtx
, reg
));
13723 RTX_FRAME_RELATED_P (insn
) = 1;
13724 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13725 plus_constant (stack_pointer_rtx
,
13727 RTX_FRAME_RELATED_P (dwarf
) = 1;
13729 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13735 if (frame_pointer_needed
)
13737 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13740 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13741 stack_pointer_rtx
, GEN_INT (amount
)));
13744 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13745 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13746 hard_frame_pointer_rtx
,
13747 stack_pointer_rtx
));
13748 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
13749 plus_constant (stack_pointer_rtx
, amount
));
13750 RTX_FRAME_RELATED_P (dwarf
) = 1;
13751 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13755 RTX_FRAME_RELATED_P (insn
) = 1;
13758 /* If we are profiling, make sure no instructions are scheduled before
13759 the call to mcount. Similarly if the user has requested no
13760 scheduling in the prolog. Similarly if we want non-call exceptions
13761 using the EABI unwinder, to prevent faulting instructions from being
13762 swapped with a stack adjustment. */
13763 if (current_function_profile
|| !TARGET_SCHED_PROLOG
13764 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
13765 emit_insn (gen_blockage ());
13767 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13768 if (live_regs_mask
& 0xff)
13769 cfun
->machine
->lr_save_eliminated
= 0;
13771 /* If the link register is being kept alive, with the return address in it,
13772 then make sure that it does not get reused by the ce2 pass. */
13773 if (cfun
->machine
->lr_save_eliminated
)
13774 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13779 thumb_expand_epilogue (void)
13781 HOST_WIDE_INT amount
;
13782 arm_stack_offsets
*offsets
;
13785 /* Naked functions don't have prologues. */
13786 if (IS_NAKED (arm_current_func_type ()))
13789 offsets
= arm_get_frame_offsets ();
13790 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13792 if (frame_pointer_needed
)
13794 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13795 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13801 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13802 GEN_INT (amount
)));
13805 /* r3 is always free in the epilogue. */
13806 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13808 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13809 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13813 /* Emit a USE (stack_pointer_rtx), so that
13814 the stack adjustment will not be deleted. */
13815 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13817 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13818 emit_insn (gen_blockage ());
13820 /* Emit a clobber for each insn that will be restored in the epilogue,
13821 so that flow2 will get register lifetimes correct. */
13822 for (regno
= 0; regno
< 13; regno
++)
13823 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13824 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13826 if (! regs_ever_live
[LR_REGNUM
])
13827 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13831 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13833 unsigned long live_regs_mask
= 0;
13834 unsigned long l_mask
;
13835 unsigned high_regs_pushed
= 0;
13836 int cfa_offset
= 0;
13839 if (IS_NAKED (arm_current_func_type ()))
13842 if (is_called_in_ARM_mode (current_function_decl
))
13846 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13847 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13849 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13851 /* Generate code sequence to switch us into Thumb mode. */
13852 /* The .code 32 directive has already been emitted by
13853 ASM_DECLARE_FUNCTION_NAME. */
13854 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13855 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13857 /* Generate a label, so that the debugger will notice the
13858 change in instruction sets. This label is also used by
13859 the assembler to bypass the ARM code when this function
13860 is called from a Thumb encoded function elsewhere in the
13861 same file. Hence the definition of STUB_NAME here must
13862 agree with the definition in gas/config/tc-arm.c. */
13864 #define STUB_NAME ".real_start_of"
13866 fprintf (f
, "\t.code\t16\n");
13868 if (arm_dllexport_name_p (name
))
13869 name
= arm_strip_name_encoding (name
);
13871 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13872 fprintf (f
, "\t.thumb_func\n");
13873 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13876 if (current_function_pretend_args_size
)
13878 /* Output unwind directive for the stack adjustment. */
13879 if (ARM_EABI_UNWIND_TABLES
)
13880 fprintf (f
, "\t.pad #%d\n",
13881 current_function_pretend_args_size
);
13883 if (cfun
->machine
->uses_anonymous_args
)
13887 fprintf (f
, "\tpush\t{");
13889 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13891 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13892 regno
<= LAST_ARG_REGNUM
;
13894 asm_fprintf (f
, "%r%s", regno
,
13895 regno
== LAST_ARG_REGNUM
? "" : ", ");
13897 fprintf (f
, "}\n");
13900 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13901 SP_REGNUM
, SP_REGNUM
,
13902 current_function_pretend_args_size
);
13904 /* We don't need to record the stores for unwinding (would it
13905 help the debugger any if we did?), but record the change in
13906 the stack pointer. */
13907 if (dwarf2out_do_frame ())
13909 char *l
= dwarf2out_cfi_label ();
13911 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13912 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13916 /* Get the registers we are going to push. */
13917 live_regs_mask
= thumb_compute_save_reg_mask ();
13918 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13919 l_mask
= live_regs_mask
& 0x40ff;
13920 /* Then count how many other high registers will need to be pushed. */
13921 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13923 if (TARGET_BACKTRACE
)
13926 unsigned work_register
;
13928 /* We have been asked to create a stack backtrace structure.
13929 The code looks like this:
13933 0 sub SP, #16 Reserve space for 4 registers.
13934 2 push {R7} Push low registers.
13935 4 add R7, SP, #20 Get the stack pointer before the push.
13936 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13937 8 mov R7, PC Get hold of the start of this code plus 12.
13938 10 str R7, [SP, #16] Store it.
13939 12 mov R7, FP Get hold of the current frame pointer.
13940 14 str R7, [SP, #4] Store it.
13941 16 mov R7, LR Get hold of the current return address.
13942 18 str R7, [SP, #12] Store it.
13943 20 add R7, SP, #16 Point at the start of the backtrace structure.
13944 22 mov FP, R7 Put this value into the frame pointer. */
13946 work_register
= thumb_find_work_register (live_regs_mask
);
13948 if (ARM_EABI_UNWIND_TABLES
)
13949 asm_fprintf (f
, "\t.pad #16\n");
13952 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13953 SP_REGNUM
, SP_REGNUM
);
13955 if (dwarf2out_do_frame ())
13957 char *l
= dwarf2out_cfi_label ();
13959 cfa_offset
= cfa_offset
+ 16;
13960 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13965 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13966 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13971 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13972 offset
+ 16 + current_function_pretend_args_size
);
13974 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13977 /* Make sure that the instruction fetching the PC is in the right place
13978 to calculate "start of backtrace creation code + 12". */
13981 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13982 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13984 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13985 ARM_HARD_FRAME_POINTER_REGNUM
);
13986 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13991 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13992 ARM_HARD_FRAME_POINTER_REGNUM
);
13993 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13995 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13996 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14000 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
14001 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14003 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14005 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14006 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
14008 /* Optimization: If we are not pushing any low registers but we are going
14009 to push some high registers then delay our first push. This will just
14010 be a push of LR and we can combine it with the push of the first high
14012 else if ((l_mask
& 0xff) != 0
14013 || (high_regs_pushed
== 0 && l_mask
))
14014 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14016 if (high_regs_pushed
)
14018 unsigned pushable_regs
;
14019 unsigned next_hi_reg
;
14021 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
14022 if (live_regs_mask
& (1 << next_hi_reg
))
14025 pushable_regs
= l_mask
& 0xff;
14027 if (pushable_regs
== 0)
14028 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
14030 while (high_regs_pushed
> 0)
14032 unsigned long real_regs_mask
= 0;
14034 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
14036 if (pushable_regs
& (1 << regno
))
14038 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
14040 high_regs_pushed
--;
14041 real_regs_mask
|= (1 << next_hi_reg
);
14043 if (high_regs_pushed
)
14045 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
14047 if (live_regs_mask
& (1 << next_hi_reg
))
14052 pushable_regs
&= ~((1 << regno
) - 1);
14058 /* If we had to find a work register and we have not yet
14059 saved the LR then add it to the list of regs to push. */
14060 if (l_mask
== (1 << LR_REGNUM
))
14062 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14064 real_regs_mask
| (1 << LR_REGNUM
));
14068 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14073 /* Handle the case of a double word load into a low register from
14074 a computed memory address. The computed address may involve a
14075 register which is overwritten by the load. */
14077 thumb_load_double_from_address (rtx
*operands
)
14085 gcc_assert (GET_CODE (operands
[0]) == REG
);
14086 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14088 /* Get the memory address. */
14089 addr
= XEXP (operands
[1], 0);
14091 /* Work out how the memory address is computed. */
14092 switch (GET_CODE (addr
))
14095 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14097 if (REGNO (operands
[0]) == REGNO (addr
))
14099 output_asm_insn ("ldr\t%H0, %2", operands
);
14100 output_asm_insn ("ldr\t%0, %1", operands
);
14104 output_asm_insn ("ldr\t%0, %1", operands
);
14105 output_asm_insn ("ldr\t%H0, %2", operands
);
14110 /* Compute <address> + 4 for the high order load. */
14111 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14113 output_asm_insn ("ldr\t%0, %1", operands
);
14114 output_asm_insn ("ldr\t%H0, %2", operands
);
14118 arg1
= XEXP (addr
, 0);
14119 arg2
= XEXP (addr
, 1);
14121 if (CONSTANT_P (arg1
))
14122 base
= arg2
, offset
= arg1
;
14124 base
= arg1
, offset
= arg2
;
14126 gcc_assert (GET_CODE (base
) == REG
);
14128 /* Catch the case of <address> = <reg> + <reg> */
14129 if (GET_CODE (offset
) == REG
)
14131 int reg_offset
= REGNO (offset
);
14132 int reg_base
= REGNO (base
);
14133 int reg_dest
= REGNO (operands
[0]);
14135 /* Add the base and offset registers together into the
14136 higher destination register. */
14137 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14138 reg_dest
+ 1, reg_base
, reg_offset
);
14140 /* Load the lower destination register from the address in
14141 the higher destination register. */
14142 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14143 reg_dest
, reg_dest
+ 1);
14145 /* Load the higher destination register from its own address
14147 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14148 reg_dest
+ 1, reg_dest
+ 1);
14152 /* Compute <address> + 4 for the high order load. */
14153 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14155 /* If the computed address is held in the low order register
14156 then load the high order register first, otherwise always
14157 load the low order register first. */
14158 if (REGNO (operands
[0]) == REGNO (base
))
14160 output_asm_insn ("ldr\t%H0, %2", operands
);
14161 output_asm_insn ("ldr\t%0, %1", operands
);
14165 output_asm_insn ("ldr\t%0, %1", operands
);
14166 output_asm_insn ("ldr\t%H0, %2", operands
);
14172 /* With no registers to worry about we can just load the value
14174 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14176 output_asm_insn ("ldr\t%H0, %2", operands
);
14177 output_asm_insn ("ldr\t%0, %1", operands
);
14181 gcc_unreachable ();
14188 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14195 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14198 operands
[4] = operands
[5];
14201 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14202 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14206 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14209 operands
[4] = operands
[5];
14212 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14215 operands
[5] = operands
[6];
14218 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14221 operands
[4] = operands
[5];
14225 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14226 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14230 gcc_unreachable ();
14236 /* Output a call-via instruction for thumb state. */
14238 thumb_call_via_reg (rtx reg
)
14240 int regno
= REGNO (reg
);
14243 gcc_assert (regno
< LR_REGNUM
);
14245 /* If we are in the normal text section we can use a single instance
14246 per compilation unit. If we are doing function sections, then we need
14247 an entry per section, since we can't rely on reachability. */
14248 if (in_section
== text_section
)
14250 thumb_call_reg_needed
= 1;
14252 if (thumb_call_via_label
[regno
] == NULL
)
14253 thumb_call_via_label
[regno
] = gen_label_rtx ();
14254 labelp
= thumb_call_via_label
+ regno
;
14258 if (cfun
->machine
->call_via
[regno
] == NULL
)
14259 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14260 labelp
= cfun
->machine
->call_via
+ regno
;
14263 output_asm_insn ("bl\t%a0", labelp
);
14267 /* Routines for generating rtl. */
14269 thumb_expand_movmemqi (rtx
*operands
)
14271 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14272 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14273 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14274 HOST_WIDE_INT offset
= 0;
14278 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14284 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14290 rtx reg
= gen_reg_rtx (SImode
);
14291 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14292 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14299 rtx reg
= gen_reg_rtx (HImode
);
14300 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14301 plus_constant (in
, offset
))));
14302 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14310 rtx reg
= gen_reg_rtx (QImode
);
14311 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14312 plus_constant (in
, offset
))));
14313 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14319 thumb_reload_out_hi (rtx
*operands
)
14321 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14324 /* Handle reading a half-word from memory during reload. */
14326 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14328 gcc_unreachable ();
14331 /* Return the length of a function name prefix
14332 that starts with the character 'c'. */
14334 arm_get_strip_length (int c
)
14338 ARM_NAME_ENCODING_LENGTHS
14343 /* Return a pointer to a function's name with any
14344 and all prefix encodings stripped from it. */
14346 arm_strip_name_encoding (const char *name
)
14350 while ((skip
= arm_get_strip_length (* name
)))
14356 /* If there is a '*' anywhere in the name's prefix, then
14357 emit the stripped name verbatim, otherwise prepend an
14358 underscore if leading underscores are being used. */
14360 arm_asm_output_labelref (FILE *stream
, const char *name
)
14365 while ((skip
= arm_get_strip_length (* name
)))
14367 verbatim
|= (*name
== '*');
14372 fputs (name
, stream
);
14374 asm_fprintf (stream
, "%U%s", name
);
14378 arm_file_end (void)
14382 if (! thumb_call_reg_needed
)
14385 switch_to_section (text_section
);
14386 asm_fprintf (asm_out_file
, "\t.code 16\n");
14387 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14389 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14391 rtx label
= thumb_call_via_label
[regno
];
14395 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14396 CODE_LABEL_NUMBER (label
));
14397 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14404 #ifdef AOF_ASSEMBLER
14405 /* Special functions only needed when producing AOF syntax assembler. */
14409 struct pic_chain
* next
;
14410 const char * symname
;
14413 static struct pic_chain
* aof_pic_chain
= NULL
;
14416 aof_pic_entry (rtx x
)
14418 struct pic_chain
** chainp
;
14421 if (aof_pic_label
== NULL_RTX
)
14423 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14426 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14427 offset
+= 4, chainp
= &(*chainp
)->next
)
14428 if ((*chainp
)->symname
== XSTR (x
, 0))
14429 return plus_constant (aof_pic_label
, offset
);
14431 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14432 (*chainp
)->next
= NULL
;
14433 (*chainp
)->symname
= XSTR (x
, 0);
14434 return plus_constant (aof_pic_label
, offset
);
14438 aof_dump_pic_table (FILE *f
)
14440 struct pic_chain
* chain
;
14442 if (aof_pic_chain
== NULL
)
14445 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14446 PIC_OFFSET_TABLE_REGNUM
,
14447 PIC_OFFSET_TABLE_REGNUM
);
14448 fputs ("|x$adcons|\n", f
);
14450 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14452 fputs ("\tDCD\t", f
);
14453 assemble_name (f
, chain
->symname
);
14458 int arm_text_section_count
= 1;
14460 /* A get_unnamed_section callback for switching to the text section. */
14463 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
14465 fprintf (asm_out_file
, "\tAREA |C$$code%d|, CODE, READONLY",
14466 arm_text_section_count
++);
14468 fprintf (asm_out_file
, ", PIC, REENTRANT");
14469 fprintf (asm_out_file
, "\n");
14472 static int arm_data_section_count
= 1;
14474 /* A get_unnamed_section callback for switching to the data section. */
14477 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
14479 fprintf (asm_out_file
, "\tAREA |C$$data%d|, DATA\n",
14480 arm_data_section_count
++);
14483 /* Implement TARGET_ASM_INIT_SECTIONS.
14485 AOF Assembler syntax is a nightmare when it comes to areas, since once
14486 we change from one area to another, we can't go back again. Instead,
14487 we must create a new area with the same attributes and add the new output
14488 to that. Unfortunately, there is nothing we can do here to guarantee that
14489 two areas with the same attributes will be linked adjacently in the
14490 resulting executable, so we have to be careful not to do pc-relative
14491 addressing across such boundaries. */
14494 aof_asm_init_sections (void)
14496 text_section
= get_unnamed_section (SECTION_CODE
,
14497 aof_output_text_section_asm_op
, NULL
);
14498 data_section
= get_unnamed_section (SECTION_WRITE
,
14499 aof_output_data_section_asm_op
, NULL
);
14500 readonly_data_section
= text_section
;
14504 zero_init_section (void)
14506 static int zero_init_count
= 1;
14508 fprintf (asm_out_file
, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count
++);
14512 /* The AOF assembler is religiously strict about declarations of
14513 imported and exported symbols, so that it is impossible to declare
14514 a function as imported near the beginning of the file, and then to
14515 export it later on. It is, however, possible to delay the decision
14516 until all the functions in the file have been compiled. To get
14517 around this, we maintain a list of the imports and exports, and
14518 delete from it any that are subsequently defined. At the end of
14519 compilation we spit the remainder of the list out before the END
14524 struct import
* next
;
14528 static struct import
* imports_list
= NULL
;
14531 aof_add_import (const char *name
)
14533 struct import
* new;
14535 for (new = imports_list
; new; new = new->next
)
14536 if (new->name
== name
)
14539 new = (struct import
*) xmalloc (sizeof (struct import
));
14540 new->next
= imports_list
;
14541 imports_list
= new;
14546 aof_delete_import (const char *name
)
14548 struct import
** old
;
14550 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14552 if ((*old
)->name
== name
)
14554 *old
= (*old
)->next
;
14560 int arm_main_function
= 0;
14563 aof_dump_imports (FILE *f
)
14565 /* The AOF assembler needs this to cause the startup code to be extracted
14566 from the library. Brining in __main causes the whole thing to work
14568 if (arm_main_function
)
14570 switch_to_section (text_section
);
14571 fputs ("\tIMPORT __main\n", f
);
14572 fputs ("\tDCD __main\n", f
);
14575 /* Now dump the remaining imports. */
14576 while (imports_list
)
14578 fprintf (f
, "\tIMPORT\t");
14579 assemble_name (f
, imports_list
->name
);
14581 imports_list
= imports_list
->next
;
14586 aof_globalize_label (FILE *stream
, const char *name
)
14588 default_globalize_label (stream
, name
);
14589 if (! strcmp (name
, "main"))
14590 arm_main_function
= 1;
14594 aof_file_start (void)
14596 fputs ("__r0\tRN\t0\n", asm_out_file
);
14597 fputs ("__a1\tRN\t0\n", asm_out_file
);
14598 fputs ("__a2\tRN\t1\n", asm_out_file
);
14599 fputs ("__a3\tRN\t2\n", asm_out_file
);
14600 fputs ("__a4\tRN\t3\n", asm_out_file
);
14601 fputs ("__v1\tRN\t4\n", asm_out_file
);
14602 fputs ("__v2\tRN\t5\n", asm_out_file
);
14603 fputs ("__v3\tRN\t6\n", asm_out_file
);
14604 fputs ("__v4\tRN\t7\n", asm_out_file
);
14605 fputs ("__v5\tRN\t8\n", asm_out_file
);
14606 fputs ("__v6\tRN\t9\n", asm_out_file
);
14607 fputs ("__sl\tRN\t10\n", asm_out_file
);
14608 fputs ("__fp\tRN\t11\n", asm_out_file
);
14609 fputs ("__ip\tRN\t12\n", asm_out_file
);
14610 fputs ("__sp\tRN\t13\n", asm_out_file
);
14611 fputs ("__lr\tRN\t14\n", asm_out_file
);
14612 fputs ("__pc\tRN\t15\n", asm_out_file
);
14613 fputs ("__f0\tFN\t0\n", asm_out_file
);
14614 fputs ("__f1\tFN\t1\n", asm_out_file
);
14615 fputs ("__f2\tFN\t2\n", asm_out_file
);
14616 fputs ("__f3\tFN\t3\n", asm_out_file
);
14617 fputs ("__f4\tFN\t4\n", asm_out_file
);
14618 fputs ("__f5\tFN\t5\n", asm_out_file
);
14619 fputs ("__f6\tFN\t6\n", asm_out_file
);
14620 fputs ("__f7\tFN\t7\n", asm_out_file
);
14621 switch_to_section (text_section
);
14625 aof_file_end (void)
14628 aof_dump_pic_table (asm_out_file
);
14630 aof_dump_imports (asm_out_file
);
14631 fputs ("\tEND\n", asm_out_file
);
14633 #endif /* AOF_ASSEMBLER */
14636 /* Symbols in the text segment can be accessed without indirecting via the
14637 constant pool; it may take an extra binary operation, but this is still
14638 faster than indirecting via memory. Don't do this when not optimizing,
14639 since we won't be calculating al of the offsets necessary to do this
14643 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14645 /* This doesn't work with AOF syntax, since the string table may be in
14646 a different AREA. */
14647 #ifndef AOF_ASSEMBLER
14648 if (optimize
> 0 && TREE_CONSTANT (decl
))
14649 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14652 /* If we are referencing a function that is weak then encode a long call
14653 flag in the function name, otherwise if the function is static or
14654 or known to be defined in this file then encode a short call flag. */
14655 if (first
&& DECL_P (decl
))
14657 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14658 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14659 else if (! TREE_PUBLIC (decl
))
14660 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14663 default_encode_section_info (decl
, rtl
, first
);
14665 #endif /* !ARM_PE */
14668 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14670 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14671 && !strcmp (prefix
, "L"))
14673 arm_ccfsm_state
= 0;
14674 arm_target_insn
= NULL
;
14676 default_internal_label (stream
, prefix
, labelno
);
14679 /* Output code to add DELTA to the first argument, and then jump
14680 to FUNCTION. Used for C++ multiple inheritance. */
14682 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14683 HOST_WIDE_INT delta
,
14684 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14687 static int thunk_label
= 0;
14689 int mi_delta
= delta
;
14690 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14692 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14695 mi_delta
= - mi_delta
;
14698 int labelno
= thunk_label
++;
14699 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14700 fputs ("\tldr\tr12, ", file
);
14701 assemble_name (file
, label
);
14702 fputc ('\n', file
);
14704 while (mi_delta
!= 0)
14706 if ((mi_delta
& (3 << shift
)) == 0)
14710 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14711 mi_op
, this_regno
, this_regno
,
14712 mi_delta
& (0xff << shift
));
14713 mi_delta
&= ~(0xff << shift
);
14719 fprintf (file
, "\tbx\tr12\n");
14720 ASM_OUTPUT_ALIGN (file
, 2);
14721 assemble_name (file
, label
);
14722 fputs (":\n", file
);
14723 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14727 fputs ("\tb\t", file
);
14728 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14729 if (NEED_PLT_RELOC
)
14730 fputs ("(PLT)", file
);
14731 fputc ('\n', file
);
14736 arm_emit_vector_const (FILE *file
, rtx x
)
14739 const char * pattern
;
14741 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14743 switch (GET_MODE (x
))
14745 case V2SImode
: pattern
= "%08x"; break;
14746 case V4HImode
: pattern
= "%04x"; break;
14747 case V8QImode
: pattern
= "%02x"; break;
14748 default: gcc_unreachable ();
14751 fprintf (file
, "0x");
14752 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14756 element
= CONST_VECTOR_ELT (x
, i
);
14757 fprintf (file
, pattern
, INTVAL (element
));
14764 arm_output_load_gr (rtx
*operands
)
14771 if (GET_CODE (operands
[1]) != MEM
14772 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14773 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14774 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14775 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14776 return "wldrw%?\t%0, %1";
14778 /* Fix up an out-of-range load of a GR register. */
14779 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14780 wcgr
= operands
[0];
14782 output_asm_insn ("ldr%?\t%0, %1", operands
);
14784 operands
[0] = wcgr
;
14786 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14787 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14793 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14794 int incoming ATTRIBUTE_UNUSED
)
14797 /* FIXME: The ARM backend has special code to handle structure
14798 returns, and will reserve its own hidden first argument. So
14799 if this macro is enabled a *second* hidden argument will be
14800 reserved, which will break binary compatibility with old
14801 toolchains and also thunk handling. One day this should be
14805 /* Register in which address to store a structure value
14806 is passed to a function. */
14807 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14811 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14813 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14814 named arg and all anonymous args onto the stack.
14815 XXX I know the prologue shouldn't be pushing registers, but it is faster
14819 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14820 enum machine_mode mode ATTRIBUTE_UNUSED
,
14821 tree type ATTRIBUTE_UNUSED
,
14823 int second_time ATTRIBUTE_UNUSED
)
14825 cfun
->machine
->uses_anonymous_args
= 1;
14826 if (cum
->nregs
< NUM_ARG_REGS
)
14827 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14830 /* Return nonzero if the CONSUMER instruction (a store) does not need
14831 PRODUCER's value to calculate the address. */
14834 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14836 rtx value
= PATTERN (producer
);
14837 rtx addr
= PATTERN (consumer
);
14839 if (GET_CODE (value
) == COND_EXEC
)
14840 value
= COND_EXEC_CODE (value
);
14841 if (GET_CODE (value
) == PARALLEL
)
14842 value
= XVECEXP (value
, 0, 0);
14843 value
= XEXP (value
, 0);
14844 if (GET_CODE (addr
) == COND_EXEC
)
14845 addr
= COND_EXEC_CODE (addr
);
14846 if (GET_CODE (addr
) == PARALLEL
)
14847 addr
= XVECEXP (addr
, 0, 0);
14848 addr
= XEXP (addr
, 0);
14850 return !reg_overlap_mentioned_p (value
, addr
);
14853 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14854 have an early register shift value or amount dependency on the
14855 result of PRODUCER. */
14858 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14860 rtx value
= PATTERN (producer
);
14861 rtx op
= PATTERN (consumer
);
14864 if (GET_CODE (value
) == COND_EXEC
)
14865 value
= COND_EXEC_CODE (value
);
14866 if (GET_CODE (value
) == PARALLEL
)
14867 value
= XVECEXP (value
, 0, 0);
14868 value
= XEXP (value
, 0);
14869 if (GET_CODE (op
) == COND_EXEC
)
14870 op
= COND_EXEC_CODE (op
);
14871 if (GET_CODE (op
) == PARALLEL
)
14872 op
= XVECEXP (op
, 0, 0);
14875 early_op
= XEXP (op
, 0);
14876 /* This is either an actual independent shift, or a shift applied to
14877 the first operand of another operation. We want the whole shift
14879 if (GET_CODE (early_op
) == REG
)
14882 return !reg_overlap_mentioned_p (value
, early_op
);
14885 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14886 have an early register shift value dependency on the result of
14890 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14892 rtx value
= PATTERN (producer
);
14893 rtx op
= PATTERN (consumer
);
14896 if (GET_CODE (value
) == COND_EXEC
)
14897 value
= COND_EXEC_CODE (value
);
14898 if (GET_CODE (value
) == PARALLEL
)
14899 value
= XVECEXP (value
, 0, 0);
14900 value
= XEXP (value
, 0);
14901 if (GET_CODE (op
) == COND_EXEC
)
14902 op
= COND_EXEC_CODE (op
);
14903 if (GET_CODE (op
) == PARALLEL
)
14904 op
= XVECEXP (op
, 0, 0);
14907 early_op
= XEXP (op
, 0);
14909 /* This is either an actual independent shift, or a shift applied to
14910 the first operand of another operation. We want the value being
14911 shifted, in either case. */
14912 if (GET_CODE (early_op
) != REG
)
14913 early_op
= XEXP (early_op
, 0);
14915 return !reg_overlap_mentioned_p (value
, early_op
);
14918 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14919 have an early register mult dependency on the result of
14923 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14925 rtx value
= PATTERN (producer
);
14926 rtx op
= PATTERN (consumer
);
14928 if (GET_CODE (value
) == COND_EXEC
)
14929 value
= COND_EXEC_CODE (value
);
14930 if (GET_CODE (value
) == PARALLEL
)
14931 value
= XVECEXP (value
, 0, 0);
14932 value
= XEXP (value
, 0);
14933 if (GET_CODE (op
) == COND_EXEC
)
14934 op
= COND_EXEC_CODE (op
);
14935 if (GET_CODE (op
) == PARALLEL
)
14936 op
= XVECEXP (op
, 0, 0);
14939 return (GET_CODE (op
) == PLUS
14940 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14944 /* We can't rely on the caller doing the proper promotion when
14945 using APCS or ATPCS. */
14948 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14950 return !TARGET_AAPCS_BASED
;
14954 /* AAPCS based ABIs use short enums by default. */
14957 arm_default_short_enums (void)
14959 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
14963 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14966 arm_align_anon_bitfield (void)
14968 return TARGET_AAPCS_BASED
;
14972 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14975 arm_cxx_guard_type (void)
14977 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14981 /* The EABI says test the least significant bit of a guard variable. */
14984 arm_cxx_guard_mask_bit (void)
14986 return TARGET_AAPCS_BASED
;
14990 /* The EABI specifies that all array cookies are 8 bytes long. */
14993 arm_get_cookie_size (tree type
)
14997 if (!TARGET_AAPCS_BASED
)
14998 return default_cxx_get_cookie_size (type
);
15000 size
= build_int_cst (sizetype
, 8);
15005 /* The EABI says that array cookies should also contain the element size. */
15008 arm_cookie_has_size (void)
15010 return TARGET_AAPCS_BASED
;
15014 /* The EABI says constructors and destructors should return a pointer to
15015 the object constructed/destroyed. */
15018 arm_cxx_cdtor_returns_this (void)
15020 return TARGET_AAPCS_BASED
;
15023 /* The EABI says that an inline function may never be the key
15027 arm_cxx_key_method_may_be_inline (void)
15029 return !TARGET_AAPCS_BASED
;
15033 arm_cxx_determine_class_data_visibility (tree decl
)
15035 if (!TARGET_AAPCS_BASED
)
15038 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15039 is exported. However, on systems without dynamic vague linkage,
15040 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15041 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
15042 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
15044 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
15045 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
15049 arm_cxx_class_data_always_comdat (void)
15051 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15052 vague linkage if the class has no key function. */
15053 return !TARGET_AAPCS_BASED
;
15057 /* The EABI says __aeabi_atexit should be used to register static
15061 arm_cxx_use_aeabi_atexit (void)
15063 return TARGET_AAPCS_BASED
;
15068 arm_set_return_address (rtx source
, rtx scratch
)
15070 arm_stack_offsets
*offsets
;
15071 HOST_WIDE_INT delta
;
15073 unsigned long saved_regs
;
15075 saved_regs
= arm_compute_save_reg_mask ();
15077 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
15078 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15081 if (frame_pointer_needed
)
15082 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
15085 /* LR will be the first saved register. */
15086 offsets
= arm_get_frame_offsets ();
15087 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15092 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15093 GEN_INT (delta
& ~4095)));
15098 addr
= stack_pointer_rtx
;
15100 addr
= plus_constant (addr
, delta
);
15102 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15108 thumb_set_return_address (rtx source
, rtx scratch
)
15110 arm_stack_offsets
*offsets
;
15111 HOST_WIDE_INT delta
;
15114 unsigned long mask
;
15116 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15118 mask
= thumb_compute_save_reg_mask ();
15119 if (mask
& (1 << LR_REGNUM
))
15121 offsets
= arm_get_frame_offsets ();
15123 /* Find the saved regs. */
15124 if (frame_pointer_needed
)
15126 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15127 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15131 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15134 /* Allow for the stack frame. */
15135 if (TARGET_BACKTRACE
)
15137 /* The link register is always the first saved register. */
15140 /* Construct the address. */
15141 addr
= gen_rtx_REG (SImode
, reg
);
15142 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15145 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15146 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15150 addr
= plus_constant (addr
, delta
);
15152 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15155 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15158 /* Implements target hook vector_mode_supported_p. */
15160 arm_vector_mode_supported_p (enum machine_mode mode
)
15162 if ((mode
== V2SImode
)
15163 || (mode
== V4HImode
)
15164 || (mode
== V8QImode
))
15170 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15171 ARM insns and therefore guarantee that the shift count is modulo 256.
15172 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15173 guarantee no particular behavior for out-of-range counts. */
15175 static unsigned HOST_WIDE_INT
15176 arm_shift_truncation_mask (enum machine_mode mode
)
15178 return mode
== SImode
? 255 : 0;
15182 /* Map internal gcc register numbers to DWARF2 register numbers. */
15185 arm_dbx_register_number (unsigned int regno
)
15190 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15191 compatibility. The EABI defines them as registers 96-103. */
15192 if (IS_FPA_REGNUM (regno
))
15193 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15195 if (IS_VFP_REGNUM (regno
))
15196 return 64 + regno
- FIRST_VFP_REGNUM
;
15198 if (IS_IWMMXT_GR_REGNUM (regno
))
15199 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15201 if (IS_IWMMXT_REGNUM (regno
))
15202 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15204 gcc_unreachable ();
15208 #ifdef TARGET_UNWIND_INFO
15209 /* Emit unwind directives for a store-multiple instruction. This should
15210 only ever be generated by the function prologue code, so we expect it
15211 to have a particular form. */
15214 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15217 HOST_WIDE_INT offset
;
15218 HOST_WIDE_INT nregs
;
15224 /* First insn will adjust the stack pointer. */
15225 e
= XVECEXP (p
, 0, 0);
15226 if (GET_CODE (e
) != SET
15227 || GET_CODE (XEXP (e
, 0)) != REG
15228 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15229 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15232 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15233 nregs
= XVECLEN (p
, 0) - 1;
15235 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15238 /* The function prologue may also push pc, but not annotate it as it is
15239 never restored. We turn this into a stack pointer adjustment. */
15240 if (nregs
* 4 == offset
- 4)
15242 fprintf (asm_out_file
, "\t.pad #4\n");
15247 else if (IS_VFP_REGNUM (reg
))
15249 /* FPA register saves use an additional word. */
15253 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15255 /* FPA registers are done differently. */
15256 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15260 /* Unknown register type. */
15263 /* If the stack increment doesn't match the size of the saved registers,
15264 something has gone horribly wrong. */
15265 if (offset
!= nregs
* reg_size
)
15268 fprintf (asm_out_file
, "\t.save {");
15272 /* The remaining insns will describe the stores. */
15273 for (i
= 1; i
<= nregs
; i
++)
15275 /* Expect (set (mem <addr>) (reg)).
15276 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15277 e
= XVECEXP (p
, 0, i
);
15278 if (GET_CODE (e
) != SET
15279 || GET_CODE (XEXP (e
, 0)) != MEM
15280 || GET_CODE (XEXP (e
, 1)) != REG
)
15283 reg
= REGNO (XEXP (e
, 1));
15288 fprintf (asm_out_file
, ", ");
15289 /* We can't use %r for vfp because we need to use the
15290 double precision register names. */
15291 if (IS_VFP_REGNUM (reg
))
15292 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15294 asm_fprintf (asm_out_file
, "%r", reg
);
15296 #ifdef ENABLE_CHECKING
15297 /* Check that the addresses are consecutive. */
15298 e
= XEXP (XEXP (e
, 0), 0);
15299 if (GET_CODE (e
) == PLUS
)
15301 offset
+= reg_size
;
15302 if (GET_CODE (XEXP (e
, 0)) != REG
15303 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15304 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15305 || offset
!= INTVAL (XEXP (e
, 1)))
15309 || GET_CODE (e
) != REG
15310 || REGNO (e
) != SP_REGNUM
)
15314 fprintf (asm_out_file
, "}\n");
15317 /* Emit unwind directives for a SET. */
15320 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15327 switch (GET_CODE (e0
))
15330 /* Pushing a single register. */
15331 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15332 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15333 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15336 asm_fprintf (asm_out_file
, "\t.save ");
15337 if (IS_VFP_REGNUM (REGNO (e1
)))
15338 asm_fprintf(asm_out_file
, "{d%d}\n",
15339 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15341 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15345 if (REGNO (e0
) == SP_REGNUM
)
15347 /* A stack increment. */
15348 if (GET_CODE (e1
) != PLUS
15349 || GET_CODE (XEXP (e1
, 0)) != REG
15350 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15351 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15354 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15355 -INTVAL (XEXP (e1
, 1)));
15357 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15359 HOST_WIDE_INT offset
;
15362 if (GET_CODE (e1
) == PLUS
)
15364 if (GET_CODE (XEXP (e1
, 0)) != REG
15365 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15367 reg
= REGNO (XEXP (e1
, 0));
15368 offset
= INTVAL (XEXP (e1
, 1));
15369 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15370 HARD_FRAME_POINTER_REGNUM
, reg
,
15371 INTVAL (XEXP (e1
, 1)));
15373 else if (GET_CODE (e1
) == REG
)
15376 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15377 HARD_FRAME_POINTER_REGNUM
, reg
);
15382 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15384 /* Move from sp to reg. */
15385 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15397 /* Emit unwind directives for the given insn. */
15400 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15404 if (!ARM_EABI_UNWIND_TABLES
)
15407 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15410 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15412 pat
= XEXP (pat
, 0);
15414 pat
= PATTERN (insn
);
15416 switch (GET_CODE (pat
))
15419 arm_unwind_emit_set (asm_out_file
, pat
);
15423 /* Store multiple. */
15424 arm_unwind_emit_stm (asm_out_file
, pat
);
15433 /* Output a reference from a function exception table to the type_info
15434 object X. The EABI specifies that the symbol should be relocated by
15435 an R_ARM_TARGET2 relocation. */
15438 arm_output_ttype (rtx x
)
15440 fputs ("\t.word\t", asm_out_file
);
15441 output_addr_const (asm_out_file
, x
);
15442 /* Use special relocations for symbol references. */
15443 if (GET_CODE (x
) != CONST_INT
)
15444 fputs ("(TARGET2)", asm_out_file
);
15445 fputc ('\n', asm_out_file
);
15449 #endif /* TARGET_UNWIND_INFO */
15452 /* Output unwind directives for the start/end of a function. */
15455 arm_output_fn_unwind (FILE * f
, bool prologue
)
15457 if (!ARM_EABI_UNWIND_TABLES
)
15461 fputs ("\t.fnstart\n", f
);
15463 fputs ("\t.fnend\n", f
);
15467 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15469 enum tls_reloc reloc
;
15472 val
= XVECEXP (x
, 0, 0);
15473 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15475 output_addr_const (fp
, val
);
15480 fputs ("(tlsgd)", fp
);
15483 fputs ("(tlsldm)", fp
);
15486 fputs ("(tlsldo)", fp
);
15489 fputs ("(gottpoff)", fp
);
15492 fputs ("(tpoff)", fp
);
15495 gcc_unreachable ();
15503 fputs (" + (. - ", fp
);
15504 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15506 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15517 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15519 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15520 return arm_emit_tls_decoration (fp
, x
);
15521 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
15524 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
15526 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
15527 assemble_name_raw (fp
, label
);
15531 else if (GET_CODE (x
) == CONST_VECTOR
)
15532 return arm_emit_vector_const (fp
, x
);
15537 #include "gt-arm.h"