1 ;;- Instruction patterns for the System z vector facility builtins.
2 ;; Copyright (C) 2015-2017 Free Software Foundation, Inc.
3 ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ; The patterns in this file are enabled with -mzvector
23 (define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF (V4SF "TARGET_VXE")])
24 (define_mode_iterator VI_HW_SD [V4SI V2DI])
25 (define_mode_iterator V_HW_HSD [V8HI V4SI V2DI V2DF])
26 (define_mode_iterator V_HW_4 [V4SI V4SF])
27 ; Full size vector modes with more than one element which are directly supported in vector registers by the hardware.
28 (define_mode_iterator VEC_HW [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")])
29 (define_mode_iterator VECF_HW [(V4SF "TARGET_VXE") V2DF])
31 ; The element type of the vector with floating point modes translated
32 ; to int modes of the same size.
33 (define_mode_attr non_vec_int[(V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI")
34 (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI")
35 (V1SI "SI") (V2SI "SI") (V4SI "SI")
36 (V1DI "DI") (V2DI "DI")
37 (V1SF "SI") (V2SF "SI") (V4SF "SI")
38 (V1DF "DI") (V2DF "DI")])
40 ; Condition code modes generated by int comparisons
41 (define_mode_iterator VICMP [CCVEQ CCVIH CCVIHU])
43 ; Comparisons supported by the vec_cmp* builtins
44 (define_code_iterator intcmp [eq gt gtu ge geu lt ltu le leu])
45 (define_code_iterator fpcmp [eq gt ge lt le])
47 ; Comparisons supported by the vec_all/any* builtins
48 (define_code_iterator intcmpcc [eq ne gt ge lt le gtu geu ltu leu])
49 (define_code_iterator fpcmpcc [eq ne gt ge unle unlt lt le])
51 ; Flags for vector string instructions (vfae all 4, vfee only ZS and CS, vstrc all 4)
53 [(VSTRING_FLAG_IN 8) ; invert result
54 (VSTRING_FLAG_RT 4) ; result type
55 (VSTRING_FLAG_ZS 2) ; zero search
56 (VSTRING_FLAG_CS 1)]) ; condition code set
58 ; Rounding modes as being used for e.g. VFI
61 (VEC_RND_NEAREST_AWAY_FROM_ZERO 1)
62 (VEC_RND_SHORT_PREC 3)
63 (VEC_RND_NEAREST_TO_EVEN 4)
68 ; Inexact suppression facility flag as being used for e.g. VFI
74 ; Vector gather element
77 (define_insn "vec_gather_element<mode>"
78 [(set (match_operand:V_HW_32_64 0 "register_operand" "=v")
79 (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0")
80 (match_operand:<tointvec> 2 "register_operand" "v")
81 (match_operand:BLK 3 "memory_operand" "R")
82 (match_operand:QI 4 "const_mask_operand" "C")]
84 "TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
85 "vge<bhfgq>\t%0,%O3(%v2,%R3),%b4"
86 [(set_attr "op_type" "VRV")])
88 (define_expand "vec_genmask<mode>"
89 [(match_operand:VI_HW 0 "register_operand" "=v")
90 (match_operand:QI 1 "const_int_operand" "C")
91 (match_operand:QI 2 "const_int_operand" "C")]
94 int bitlen = GET_MODE_UNIT_BITSIZE (<VI_HW:MODE>mode);
95 /* To bit little endian style. */
96 int end = bitlen - 1 - INTVAL (operands[1]);
97 int start = bitlen - 1 - INTVAL (operands[2]);
99 unsigned HOST_WIDE_INT mask;
100 bool swapped_p = false;
104 i = start - 1; start = end + 1; end = i;
108 mask = HOST_WIDE_INT_M1U;
110 mask = (HOST_WIDE_INT_1U << (end + 1)) - 1;
112 mask &= ~((HOST_WIDE_INT_1U << start) - 1);
117 rtx mask_rtx = gen_int_mode (mask, GET_MODE_INNER (<VI_HW:MODE>mode));
119 emit_insn (gen_rtx_SET (operands[0],
120 gen_const_vec_duplicate (<VI_HW:MODE>mode,
125 (define_expand "vec_genbytemaskv16qi"
126 [(match_operand:V16QI 0 "register_operand" "")
127 (match_operand:HI 1 "const_int_operand" "")]
131 unsigned mask = 0x8000;
133 unsigned HOST_WIDE_INT byte_mask = UINTVAL (operands[1]);
135 for (i = 0; i < 16; i++)
137 if (mask & byte_mask)
138 const_vec[i] = constm1_rtx;
140 const_vec[i] = const0_rtx;
143 emit_insn (gen_rtx_SET (operands[0],
144 gen_rtx_CONST_VECTOR (V16QImode,
145 gen_rtvec_v (16, const_vec))));
149 (define_expand "vec_splats<mode>"
150 [(set (match_operand:VEC_HW 0 "register_operand" "")
151 (vec_duplicate:VEC_HW (match_operand:<non_vec> 1 "general_operand" "")))]
154 (define_expand "vec_insert<mode>"
155 [(set (match_operand:VEC_HW 0 "register_operand" "")
156 (unspec:VEC_HW [(match_operand:<non_vec> 2 "register_operand" "")
157 (match_operand:SI 3 "nonmemory_operand" "")
158 (match_operand:VEC_HW 1 "register_operand" "")]
163 ; This is vec_set + modulo arithmetic on the element selector (op 2)
164 (define_expand "vec_promote<mode>"
165 [(set (match_operand:VEC_HW 0 "register_operand" "")
166 (unspec:VEC_HW [(match_operand:<non_vec> 1 "register_operand" "")
167 (match_operand:SI 2 "nonmemory_operand" "")
173 ; vec_extract is also an RTL standard name -> vector.md
175 ; vllezb, vllezh, vllezf, vllezg
176 (define_insn "vec_insert_and_zero<mode>"
177 [(set (match_operand:VEC_HW 0 "register_operand" "=v")
178 (unspec:VEC_HW [(match_operand:<non_vec> 1 "memory_operand" "R")]
179 UNSPEC_VEC_INSERT_AND_ZERO))]
181 "vllez<bhfgq>\t%v0,%1"
182 [(set_attr "op_type" "VRX")])
185 [(set (match_operand:V16QI 0 "register_operand" "=v")
186 (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "R")
187 (match_operand:QI 2 "const_mask_operand" "C")]
188 UNSPEC_VEC_LOAD_BNDRY))]
189 "TARGET_VX && UINTVAL (operands[2]) < 7"
191 [(set_attr "op_type" "VRX")])
193 (define_insn "vlrlrv16qi"
194 [(set (match_operand:V16QI 0 "register_operand" "=v,v")
195 (unspec:V16QI [(match_operand:BLK 2 "memory_operand" "Q,Q")
196 (match_operand:SI 1 "nonmemory_operand" "d,C")]
197 UNSPEC_VEC_LOAD_LEN_R))]
202 [(set_attr "op_type" "VRS,VSI")])
205 ; FIXME: The following two patterns might using vec_merge. But what is
206 ; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge
207 ; (vec_select op0) (vec_select op1)
208 ; vmrhb, vmrhh, vmrhf, vmrhg
209 (define_insn "vec_mergeh<mode>"
210 [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "=v")
211 (unspec:V_128_NOSINGLE [(match_operand:V_128_NOSINGLE 1 "register_operand" "v")
212 (match_operand:V_128_NOSINGLE 2 "register_operand" "v")]
215 "vmrh<bhfgq>\t%v0,%1,%2"
216 [(set_attr "op_type" "VRR")])
218 ; vmrlb, vmrlh, vmrlf, vmrlg
219 (define_insn "vec_mergel<mode>"
220 [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "=v")
221 (unspec:V_128_NOSINGLE [(match_operand:V_128_NOSINGLE 1 "register_operand" "v")
222 (match_operand:V_128_NOSINGLE 2 "register_operand" "v")]
225 "vmrl<bhfgq>\t%v0,%1,%2"
226 [(set_attr "op_type" "VRR")])
232 (define_insn "vec_pack<mode>"
233 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
234 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
235 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
238 "vpk<bhfgq>\t%v0,%v1,%v2"
239 [(set_attr "op_type" "VRR")])
242 ; Vector pack saturate
244 ; vpksh, vpksf, vpksg
245 (define_insn "vec_packs<mode>"
246 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
247 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
248 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
249 UNSPEC_VEC_PACK_SATURATE))]
251 "vpks<bhfgq>\t%v0,%v1,%v2"
252 [(set_attr "op_type" "VRR")])
255 ; This is vec_packs_cc + loading cc into a caller specified memory location.
256 (define_expand "vec_packs_cc<mode>"
258 [(set (reg:CCRAW CC_REGNUM)
259 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "")
260 (match_operand:VI_HW_HSD 2 "register_operand" "")]
261 UNSPEC_VEC_PACK_SATURATE_GENCC))
262 (set (match_operand:<vec_half> 0 "register_operand" "")
263 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
264 UNSPEC_VEC_PACK_SATURATE_CC))])
266 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
267 (set (match_operand:SI 3 "memory_operand" "")
271 operands[4] = gen_reg_rtx (SImode);
274 ; vpksh, vpksf, vpksg
275 (define_insn "*vec_packs_cc<mode>"
276 [(set (reg:CCRAW CC_REGNUM)
277 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
278 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
279 UNSPEC_VEC_PACK_SATURATE_GENCC))
280 (set (match_operand:<vec_half> 0 "register_operand" "=v")
281 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
282 UNSPEC_VEC_PACK_SATURATE_CC))]
284 "vpks<bhfgq>s\t%v0,%v1,%v2"
285 [(set_attr "op_type" "VRR")])
288 ; Vector pack logical saturate
290 ; vpklsh, vpklsf, vpklsg
291 (define_insn "vec_packsu<mode>"
292 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
293 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
294 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
295 UNSPEC_VEC_PACK_UNSIGNED_SATURATE))]
297 "vpkls<bhfgq>\t%v0,%v1,%v2"
298 [(set_attr "op_type" "VRR")])
300 ; Emulate saturate unsigned pack on signed operands.
301 ; Zero out negative elements and continue with the unsigned saturating pack.
302 (define_expand "vec_packsu_u<mode>"
303 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
304 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
305 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
306 UNSPEC_VEC_PACK_UNSIGNED_SATURATE))]
309 rtx null_vec = CONST0_RTX(<MODE>mode);
310 machine_mode half_mode;
313 case E_V8HImode: half_mode = V16QImode; break;
314 case E_V4SImode: half_mode = V8HImode; break;
315 case E_V2DImode: half_mode = V4SImode; break;
316 default: gcc_unreachable ();
318 s390_expand_vcond (operands[1], operands[1], null_vec,
319 GE, operands[1], null_vec);
320 s390_expand_vcond (operands[2], operands[2], null_vec,
321 GE, operands[2], null_vec);
322 emit_insn (gen_rtx_SET (operands[0],
323 gen_rtx_UNSPEC (half_mode,
324 gen_rtvec (2, operands[1], operands[2]),
325 UNSPEC_VEC_PACK_UNSIGNED_SATURATE)));
329 ; This is vec_packsu_cc + loading cc into a caller specified memory location.
330 ; FIXME: The reg to target mem copy should be issued by reload?!
331 (define_expand "vec_packsu_cc<mode>"
333 [(set (reg:CCRAW CC_REGNUM)
334 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "")
335 (match_operand:VI_HW_HSD 2 "register_operand" "")]
336 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC))
337 (set (match_operand:<vec_half> 0 "register_operand" "")
338 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
339 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))])
341 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
342 (set (match_operand:SI 3 "memory_operand" "")
346 operands[4] = gen_reg_rtx (SImode);
349 ; vpklsh, vpklsf, vpklsg
350 (define_insn "*vec_packsu_cc<mode>"
351 [(set (reg:CCRAW CC_REGNUM)
352 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
353 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
354 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC))
355 (set (match_operand:<vec_half> 0 "register_operand" "=v")
356 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
357 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))]
359 "vpkls<bhfgq>s\t%v0,%v1,%v2"
360 [(set_attr "op_type" "VRR")])
365 ; vec_perm is also RTL standard name, but we can only use it for V16QI
367 (define_insn "vec_zperm<mode>"
368 [(set (match_operand:V_HW_HSD 0 "register_operand" "=v")
369 (unspec:V_HW_HSD [(match_operand:V_HW_HSD 1 "register_operand" "v")
370 (match_operand:V_HW_HSD 2 "register_operand" "v")
371 (match_operand:V16QI 3 "register_operand" "v")]
374 "vperm\t%v0,%v1,%v2,%v3"
375 [(set_attr "op_type" "VRR")])
377 (define_expand "vec_permi<mode>"
378 [(set (match_operand:V_HW_64 0 "register_operand" "")
379 (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "")
380 (match_operand:V_HW_64 2 "register_operand" "")
381 (match_operand:QI 3 "const_mask_operand" "")]
385 HOST_WIDE_INT val = INTVAL (operands[3]);
386 operands[3] = GEN_INT ((val & 1) | (val & 2) << 1);
389 (define_insn "*vec_permi<mode>"
390 [(set (match_operand:V_HW_64 0 "register_operand" "=v")
391 (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "v")
392 (match_operand:V_HW_64 2 "register_operand" "v")
393 (match_operand:QI 3 "const_mask_operand" "C")]
395 "TARGET_VX && (UINTVAL (operands[3]) & 10) == 0"
396 "vpdi\t%v0,%v1,%v2,%b3"
397 [(set_attr "op_type" "VRR")])
403 ; Replicate from vector element
404 (define_expand "vec_splat<mode>"
405 [(set (match_operand:V_HW 0 "register_operand" "")
406 (vec_duplicate:V_HW (vec_select:<non_vec>
407 (match_operand:V_HW 1 "register_operand" "")
409 [(match_operand:QI 2 "const_mask_operand" "")]))))]
412 ; Vector scatter element
416 ; A 64 bit target address generated from 32 bit elements
417 (define_insn "vec_scatter_element<V_HW_4:mode>_DI"
419 (plus:DI (zero_extend:DI
420 (unspec:SI [(match_operand:V4SI 1 "register_operand" "v")
421 (match_operand:QI 3 "const_mask_operand" "C")]
423 (match_operand:SI 2 "address_operand" "ZQ")))
424 (unspec:<non_vec> [(match_operand:V_HW_4 0 "register_operand" "v")
425 (match_dup 3)] UNSPEC_VEC_EXTRACT))]
426 "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
427 "vscef\t%v0,%O2(%v1,%R2),%3"
428 [(set_attr "op_type" "VRV")])
430 ; A 31 bit target address is generated from 64 bit elements
432 (define_insn "vec_scatter_element<V_HW_64:mode>_SI"
435 (unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand" "v")
436 (match_operand:QI 3 "const_mask_operand" "C")]
437 UNSPEC_VEC_EXTRACT) 4)
438 (match_operand:SI 2 "address_operand" "ZQ")))
439 (unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v")
440 (match_dup 3)] UNSPEC_VEC_EXTRACT))]
441 "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_64:MODE>mode)"
442 "vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
443 [(set_attr "op_type" "VRV")])
445 ; Element size and target address size is the same
447 (define_insn "vec_scatter_element<mode>_<non_vec_int>"
449 (plus:<non_vec_int> (unspec:<non_vec_int>
450 [(match_operand:<tointvec> 1 "register_operand" "v")
451 (match_operand:QI 3 "const_mask_operand" "C")]
453 (match_operand:DI 2 "address_operand" "ZQ")))
454 (unspec:<non_vec> [(match_operand:V_HW_32_64 0 "register_operand" "v")
455 (match_dup 3)] UNSPEC_VEC_EXTRACT))]
456 "TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
457 "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3"
458 [(set_attr "op_type" "VRV")])
460 ; Depending on the address size we have to expand a different pattern.
461 ; This however cannot be represented in s390-builtins.def so we do the
462 ; multiplexing here in the expander.
463 (define_expand "vec_scatter_element<V_HW_32_64:mode>"
464 [(match_operand:V_HW_32_64 0 "register_operand" "")
465 (match_operand:<tointvec> 1 "register_operand" "")
466 (match_operand 2 "address_operand" "")
467 (match_operand:QI 3 "const_mask_operand" "")]
472 PUT_MODE (operands[2], DImode);
474 gen_vec_scatter_element<V_HW_32_64:mode>_DI (operands[0], operands[1],
475 operands[2], operands[3]));
479 PUT_MODE (operands[2], SImode);
481 gen_vec_scatter_element<V_HW_32_64:mode>_SI (operands[0], operands[1],
482 operands[2], operands[3]));
490 ; Operand 3 selects bits from either OP1 (0) or OP2 (1)
492 ; Comparison operator should not matter as long as we always use the same ?!
494 ; Operands 1 and 2 are swapped in order to match the altivec builtin.
495 ; If operand 3 is a const_int bitmask this would be vec_merge
496 (define_expand "vec_sel<mode>"
497 [(set (match_operand:V_HW 0 "register_operand" "")
499 (eq (match_operand:<tointvec> 3 "register_operand" "")
501 (match_operand:V_HW 2 "register_operand" "")
502 (match_operand:V_HW 1 "register_operand" "")))]
505 operands[4] = CONST0_RTX (<tointvec>mode);
509 ; Vector sign extend to doubleword
511 ; Sign extend of right most vector element to respective double-word
512 ; vsegb, vsegh, vsegf
513 (define_insn "vec_extend<mode>"
514 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
515 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
518 "vseg<bhfgq>\t%v0,%1"
519 [(set_attr "op_type" "VRR")])
522 ; Vector store with length
524 ; Store bytes in OP1 from OP0 with the highest indexed byte to be
525 ; stored from OP0 given by OP2
526 (define_insn "vstl<mode>"
527 [(set (match_operand:BLK 2 "memory_operand" "=Q")
528 (unspec:BLK [(match_operand:V 0 "register_operand" "v")
529 (match_operand:SI 1 "register_operand" "d")]
530 UNSPEC_VEC_STORE_LEN))]
533 [(set_attr "op_type" "VRS")])
535 ; Vector store rightmost with length
537 (define_insn "vstrlrv16qi"
538 [(set (match_operand:BLK 2 "memory_operand" "=Q,Q")
539 (unspec:BLK [(match_operand:V16QI 0 "register_operand" "v,v")
540 (match_operand:SI 1 "nonmemory_operand" "d,C")]
541 UNSPEC_VEC_STORE_LEN_R))]
546 [(set_attr "op_type" "VRS,VSI")])
552 (define_insn "vbpermv16qi"
553 [(set (match_operand:V2DI 0 "register_operand" "=v")
554 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v")
555 (match_operand:V16QI 2 "register_operand" "v")]
558 "vbperm\t%v0,%v1,%v2"
559 [(set_attr "op_type" "VRR")])
563 ; vuphb, vuphh, vuphf
564 (define_insn "vec_unpackh<mode>"
565 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
566 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
567 UNSPEC_VEC_UNPACKH))]
569 "vuph<bhfgq>\t%v0,%v1"
570 [(set_attr "op_type" "VRR")])
572 ; vuplhb, vuplhh, vuplhf
573 (define_insn "vec_unpackh_l<mode>"
574 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
575 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
576 UNSPEC_VEC_UNPACKH_L))]
578 "vuplh<bhfgq>\t%v0,%v1"
579 [(set_attr "op_type" "VRR")])
584 ; vuplb, vuplhw, vuplf
585 (define_insn "vec_unpackl<mode>"
586 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
587 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
588 UNSPEC_VEC_UNPACKL))]
590 "vupl<bhfgq><w>\t%v0,%v1"
591 [(set_attr "op_type" "VRR")])
593 ; vupllb, vupllh, vupllf
594 (define_insn "vec_unpackl_l<mode>"
595 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
596 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
597 UNSPEC_VEC_UNPACKL_L))]
599 "vupll<bhfgq>\t%v0,%v1"
600 [(set_attr "op_type" "VRR")])
605 ; Vector add compute carry
607 ; vaccb, vacch, vaccf, vaccg, vaccq
608 (define_insn "vacc<bhfgq>_<mode>"
609 [(set (match_operand:VIT_HW 0 "register_operand" "=v")
610 (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v")
611 (match_operand:VIT_HW 2 "register_operand" "v")]
614 "vacc<bhfgq>\t%v0,%v1,%v2"
615 [(set_attr "op_type" "VRR")])
617 ; Vector add with carry
620 [(set (match_operand:TI 0 "register_operand" "=v")
621 (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
622 (match_operand:TI 2 "register_operand" "v")
623 (match_operand:TI 3 "register_operand" "v")]
624 UNSPEC_VEC_ADDE_U128))]
626 "vacq\t%v0,%v1,%v2,%v3"
627 [(set_attr "op_type" "VRR")])
630 ; Vector add with carry compute carry
632 (define_insn "vacccq"
633 [(set (match_operand:TI 0 "register_operand" "=v")
634 (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
635 (match_operand:TI 2 "register_operand" "v")
636 (match_operand:TI 3 "register_operand" "v")]
637 UNSPEC_VEC_ADDEC_U128))]
639 "vacccq\t%v0,%v1,%v2,%v3"
640 [(set_attr "op_type" "VRR")])
645 ; Vector and with complement
648 (define_insn "vec_andc<mode>3"
649 [(set (match_operand:VT_HW 0 "register_operand" "=v")
650 (and:VT_HW (not:VT_HW (match_operand:VT_HW 2 "register_operand" "v"))
651 (match_operand:VT_HW 1 "register_operand" "v")))]
654 [(set_attr "op_type" "VRR")])
659 ; vavgb, vavgh, vavgf, vavgg
660 (define_insn "vec_avg<mode>"
661 [(set (match_operand:VI_HW 0 "register_operand" "=v")
662 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
663 (match_operand:VI_HW 2 "register_operand" "v")]
666 "vavg<bhfgq>\t%v0,%v1,%v2"
667 [(set_attr "op_type" "VRR")])
669 ; Vector average logical
671 ; vavglb, vavglh, vavglf, vavglg
672 (define_insn "vec_avgu<mode>"
673 [(set (match_operand:VI_HW 0 "register_operand" "=v")
674 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
675 (match_operand:VI_HW 2 "register_operand" "v")]
678 "vavgl<bhfgq>\t%v0,%v1,%v2"
679 [(set_attr "op_type" "VRR")])
684 (define_insn "vec_checksum"
685 [(set (match_operand:V4SI 0 "register_operand" "=v")
686 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
687 (match_operand:V4SI 2 "register_operand" "v")]
688 UNSPEC_VEC_CHECKSUM))]
691 [(set_attr "op_type" "VRR")])
697 ; vec_all/any int compares
699 (define_expand "vec_all_<intcmpcc:code><VI_HW:mode>"
700 [(match_operand:SI 0 "register_operand" "")
701 (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
702 (match_operand:VI_HW 2 "register_operand" ""))]
705 s390_expand_vec_compare_cc (operands[0],
713 (define_expand "vec_any_<intcmpcc:code><VI_HW:mode>"
714 [(match_operand:SI 0 "register_operand" "")
715 (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
716 (match_operand:VI_HW 2 "register_operand" ""))]
719 s390_expand_vec_compare_cc (operands[0],
727 ; vec_all/any fp compares
729 (define_expand "vec_all_<fpcmpcc:code><mode>"
730 [(match_operand:SI 0 "register_operand" "")
731 (fpcmpcc (match_operand:VECF_HW 1 "register_operand" "")
732 (match_operand:VECF_HW 2 "register_operand" ""))]
735 s390_expand_vec_compare_cc (operands[0],
743 (define_expand "vec_any_<fpcmpcc:code><mode>"
744 [(match_operand:SI 0 "register_operand" "")
745 (fpcmpcc (match_operand:VECF_HW 1 "register_operand" "")
746 (match_operand:VECF_HW 2 "register_operand" ""))]
749 s390_expand_vec_compare_cc (operands[0],
758 ; Compare without generating CC
760 (define_expand "vec_cmp<intcmp:code><VI_HW:mode>"
761 [(set (match_operand:VI_HW 0 "register_operand" "=v")
762 (intcmp:VI_HW (match_operand:VI_HW 1 "register_operand" "v")
763 (match_operand:VI_HW 2 "register_operand" "v")))]
766 s390_expand_vec_compare (operands[0], <intcmp:CODE>, operands[1], operands[2]);
770 (define_expand "vec_cmp<fpcmp:code><mode>"
771 [(set (match_operand:<tointvec> 0 "register_operand" "=v")
772 (fpcmp:<tointvec> (match_operand:VF_HW 1 "register_operand" "v")
773 (match_operand:VF_HW 2 "register_operand" "v")))]
776 s390_expand_vec_compare (operands[0], <fpcmp:CODE>, operands[1], operands[2]);
781 ; Vector count leading zeros
790 ; Vector Galois field multiply sum
792 ; vgfmb, vgfmh, vgfmf
793 (define_insn "vec_gfmsum<mode>"
794 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
795 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
796 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
799 "vgfm<bhfgq>\t%v0,%v1,%v2"
800 [(set_attr "op_type" "VRR")])
802 (define_insn "vec_gfmsum_128"
803 [(set (match_operand:V16QI 0 "register_operand" "=v")
804 (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
805 (match_operand:V2DI 2 "register_operand" "v")]
806 UNSPEC_VEC_GFMSUM_128))]
809 [(set_attr "op_type" "VRR")])
811 ; vgfmab, vgfmah, vgfmaf
812 (define_insn "vec_gfmsum_accum<mode>"
813 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
814 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
815 (match_operand:VI_HW_QHS 2 "register_operand" "v")
816 (match_operand:<vec_double> 3 "register_operand" "v")]
817 UNSPEC_VEC_GFMSUM_ACCUM))]
819 "vgfma<bhfgq>\t%v0,%v1,%v2,%v3"
820 [(set_attr "op_type" "VRR")])
822 (define_insn "vec_gfmsum_accum_128"
823 [(set (match_operand:V16QI 0 "register_operand" "=v")
824 (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
825 (match_operand:V2DI 2 "register_operand" "v")
826 (match_operand:V16QI 3 "register_operand" "v")]
827 UNSPEC_VEC_GFMSUM_ACCUM_128))]
829 "vgfmag\t%v0,%v1,%v2,%v3"
830 [(set_attr "op_type" "VRR")])
835 ; Vector load positive: vec_abs -> abs
836 ; Vector maximum vec_max -> smax, logical vec_max -> umax
837 ; Vector maximum vec_min -> smin, logical vec_min -> umin
840 ; Vector multiply and add high
842 ; vec_mladd -> vec_vmal
843 ; vmalb, vmalh, vmalf, vmalg
844 (define_insn "vec_vmal<mode>"
845 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
846 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
847 (match_operand:VI_HW_QHS 2 "register_operand" "v")
848 (match_operand:VI_HW_QHS 3 "register_operand" "v")]
851 "vmal<bhfgq><w>\t%v0,%v1,%v2,%v3"
852 [(set_attr "op_type" "VRR")])
854 ; vec_mhadd -> vec_vmah/vec_vmalh
856 ; vmahb; vmahh, vmahf, vmahg
857 (define_insn "vec_vmah<mode>"
858 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
859 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
860 (match_operand:VI_HW_QHS 2 "register_operand" "v")
861 (match_operand:VI_HW_QHS 3 "register_operand" "v")]
864 "vmah<bhfgq>\t%v0,%v1,%v2,%v3"
865 [(set_attr "op_type" "VRR")])
867 ; vmalhb; vmalhh, vmalhf, vmalhg
868 (define_insn "vec_vmalh<mode>"
869 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
870 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
871 (match_operand:VI_HW_QHS 2 "register_operand" "v")
872 (match_operand:VI_HW_QHS 3 "register_operand" "v")]
875 "vmalh<bhfgq>\t%v0,%v1,%v2,%v3"
876 [(set_attr "op_type" "VRR")])
878 ; vec_meadd -> vec_vmae/vec_vmale
880 ; vmaeb; vmaeh, vmaef, vmaeg
881 (define_insn "vec_vmae<mode>"
882 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
883 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
884 (match_operand:VI_HW_QHS 2 "register_operand" "v")
885 (match_operand:<vec_double> 3 "register_operand" "v")]
888 "vmae<bhfgq>\t%v0,%v1,%v2,%v3"
889 [(set_attr "op_type" "VRR")])
891 ; vmaleb; vmaleh, vmalef, vmaleg
892 (define_insn "vec_vmale<mode>"
893 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
894 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
895 (match_operand:VI_HW_QHS 2 "register_operand" "v")
896 (match_operand:<vec_double> 3 "register_operand" "v")]
899 "vmale<bhfgq>\t%v0,%v1,%v2,%v3"
900 [(set_attr "op_type" "VRR")])
902 ; vec_moadd -> vec_vmao/vec_vmalo
904 ; vmaob; vmaoh, vmaof, vmaog
905 (define_insn "vec_vmao<mode>"
906 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
907 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
908 (match_operand:VI_HW_QHS 2 "register_operand" "v")
909 (match_operand:<vec_double> 3 "register_operand" "v")]
912 "vmao<bhfgq>\t%v0,%v1,%v2,%v3"
913 [(set_attr "op_type" "VRR")])
915 ; vmalob; vmaloh, vmalof, vmalog
916 (define_insn "vec_vmalo<mode>"
917 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
918 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
919 (match_operand:VI_HW_QHS 2 "register_operand" "v")
920 (match_operand:<vec_double> 3 "register_operand" "v")]
923 "vmalo<bhfgq>\t%v0,%v1,%v2,%v3"
924 [(set_attr "op_type" "VRR")])
927 ; Vector multiply high
929 ; vec_mulh -> vec_smulh/vec_umulh
932 (define_insn "vec_smulh<mode>"
933 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
934 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
935 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
936 UNSPEC_VEC_SMULT_HI))]
938 "vmh<bhfgq>\t%v0,%v1,%v2"
939 [(set_attr "op_type" "VRR")])
941 ; vmlhb, vmlhh, vmlhf
942 (define_insn "vec_umulh<mode>"
943 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
944 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
945 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
946 UNSPEC_VEC_UMULT_HI))]
948 "vmlh<bhfgq>\t%v0,%v1,%v2"
949 [(set_attr "op_type" "VRR")])
952 ; Vector multiply low
954 ; vec_mule -> vec_widen_umult_even/vec_widen_smult_even
955 ; vec_mulo -> vec_widen_umult_odd/vec_widen_smult_odd
960 (define_insn "vec_nor<mode>3"
961 [(set (match_operand:VT_HW 0 "register_operand" "=v")
963 (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
964 (match_operand:VT_HW 2 "register_operand" "v"))))]
967 [(set_attr "op_type" "VRR")])
972 ; Vector population count vec_popcnt -> popcount
973 ; Vector element rotate left logical vec_rl -> vrotl, vec_rli -> rot
975 ; Vector element rotate and insert under mask
977 ; verimb, verimh, verimf, verimg
978 (define_insn "verim<mode>"
979 [(set (match_operand:VI_HW 0 "register_operand" "=v")
980 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "0")
981 (match_operand:VI_HW 2 "register_operand" "v")
982 (match_operand:VI_HW 3 "register_operand" "v")
983 (match_operand:QI 4 "const_int_operand" "C")]
984 UNSPEC_VEC_RL_MASK))]
986 "verim<bhfgq>\t%v0,%v2,%v3,%b4"
987 [(set_attr "op_type" "VRI")])
992 (define_insn "vec_sll<VI_HW:mode><VI_HW_QHS:mode>"
993 [(set (match_operand:VI_HW 0 "register_operand" "=v")
994 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
995 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
999 [(set_attr "op_type" "VRR")])
1002 ; Vector shift left by byte
1004 ; Pattern definition in vector.md, see vec_vslb
1005 (define_expand "vec_slb<mode>"
1006 [(set (match_operand:V_HW 0 "register_operand" "")
1007 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
1008 (match_operand:<tointvec> 2 "register_operand" "")]
1012 PUT_MODE (operands[2], V16QImode);
1015 ; Vector shift left double by byte
1017 (define_insn "vec_sld<mode>"
1018 [(set (match_operand:V_HW 0 "register_operand" "=v")
1019 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
1020 (match_operand:V_HW 2 "register_operand" "v")
1021 (match_operand:QI 3 "const_int_operand" "C")]
1024 "vsldb\t%v0,%v1,%v2,%b3"
1025 [(set_attr "op_type" "VRI")])
1027 (define_expand "vec_sldw<mode>"
1028 [(set (match_operand:V_HW 0 "register_operand" "")
1029 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
1030 (match_operand:V_HW 2 "register_operand" "")
1031 (match_operand:QI 3 "const_int_operand" "")]
1035 operands[3] = GEN_INT (INTVAL (operands[3]) << 2);
1038 ; Vector shift right arithmetic
1040 (define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>"
1041 [(set (match_operand:VI_HW 0 "register_operand" "=v")
1042 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
1043 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
1047 [(set_attr "op_type" "VRR")])
1050 ; Vector shift right arithmetic by byte
1052 (define_insn "vec_srab<mode>"
1053 [(set (match_operand:V_HW 0 "register_operand" "=v")
1054 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
1055 (match_operand:<tointvec> 2 "register_operand" "v")]
1058 "vsrab\t%v0,%v1,%v2"
1059 [(set_attr "op_type" "VRR")])
1062 ; Vector shift right logical
1064 (define_insn "vec_srl<VI_HW:mode><VI_HW_QHS:mode>"
1065 [(set (match_operand:VI_HW 0 "register_operand" "=v")
1066 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
1067 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
1071 [(set_attr "op_type" "VRR")])
1074 ; Vector shift right logical by byte
1076 ; Pattern definition in vector.md, see vec_vsrb
1077 (define_expand "vec_srb<mode>"
1078 [(set (match_operand:V_HW 0 "register_operand" "")
1079 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
1080 (match_operand:<tointvec> 2 "register_operand" "")]
1084 PUT_MODE (operands[2], V16QImode);
1089 ; Vector subtract compute borrow indication
1091 ; vscbib, vscbih, vscbif, vscbig, vscbiq
1092 (define_insn "vscbi<bhfgq>_<mode>"
1093 [(set (match_operand:VIT_HW 0 "register_operand" "=v")
1094 (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v")
1095 (match_operand:VIT_HW 2 "register_operand" "v")]
1098 "vscbi<bhfgq>\t%v0,%v1,%v2"
1099 [(set_attr "op_type" "VRR")])
1101 ; Vector subtract with borrow indication
1103 (define_insn "vsbiq"
1104 [(set (match_operand:TI 0 "register_operand" "=v")
1105 (unspec:TI [(match_operand:TI 1 "register_operand" "v")
1106 (match_operand:TI 2 "register_operand" "v")
1107 (match_operand:TI 3 "register_operand" "v")]
1108 UNSPEC_VEC_SUBE_U128))]
1110 "vsbiq\t%v0,%v1,%v2,%v3"
1111 [(set_attr "op_type" "VRR")])
1114 ; Vector subtract with borrow compute and borrow indication
1116 (define_insn "vsbcbiq"
1117 [(set (match_operand:TI 0 "register_operand" "=v")
1118 (unspec:TI [(match_operand:TI 1 "register_operand" "v")
1119 (match_operand:TI 2 "register_operand" "v")
1120 (match_operand:TI 3 "register_operand" "v")]
1121 UNSPEC_VEC_SUBEC_U128))]
1123 "vsbcbiq\t%v0,%v1,%v2,%v3"
1124 [(set_attr "op_type" "VRR")])
1129 ; Sum across DImode parts of the 1st operand and add the rightmost
1130 ; element of 2nd operand
1132 (define_expand "vec_sum2<mode>"
1133 [(set (match_operand:V2DI 0 "register_operand" "")
1134 (unspec:V2DI [(match_operand:VI_HW_HS 1 "register_operand" "")
1135 (match_operand:VI_HW_HS 2 "register_operand" "")]
1140 (define_insn "vec_sum_u128<mode>"
1141 [(set (match_operand:V2DI 0 "register_operand" "=v")
1142 (unspec:V2DI [(match_operand:VI_HW_SD 1 "register_operand" "v")
1143 (match_operand:VI_HW_SD 2 "register_operand" "v")]
1146 "vsumq<bhfgq>\t%v0,%v1,%v2"
1147 [(set_attr "op_type" "VRR")])
1150 (define_expand "vec_sum4<mode>"
1151 [(set (match_operand:V4SI 0 "register_operand" "")
1152 (unspec:V4SI [(match_operand:VI_HW_QH 1 "register_operand" "")
1153 (match_operand:VI_HW_QH 2 "register_operand" "")]
1158 ; Vector test under mask
1160 (define_expand "vec_test_mask_int<mode>"
1161 [(set (reg:CCRAW CC_REGNUM)
1162 (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "")
1163 (match_operand:<tointvec> 2 "register_operand" "")]
1164 UNSPEC_VEC_TEST_MASK))
1165 (set (match_operand:SI 0 "register_operand" "")
1166 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1169 (define_insn "*vec_test_mask<mode>"
1170 [(set (reg:CCRAW CC_REGNUM)
1171 (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v")
1172 (match_operand:<tointvec> 1 "register_operand" "v")]
1173 UNSPEC_VEC_TEST_MASK))]
1176 [(set_attr "op_type" "VRR")])
1179 ; Vector multiply sum logical
1181 (define_insn "vec_msumv2di"
1182 [(set (match_operand:V16QI 0 "register_operand" "=v")
1183 (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
1184 (match_operand:V2DI 2 "register_operand" "v")
1185 (match_operand:V16QI 3 "register_operand" "v")
1186 (match_operand:QI 4 "const_mask_operand" "C")]
1189 "vmslg\t%v0,%v1,%v2,%v3,%4"
1190 [(set_attr "op_type" "VRR")])
1192 (define_insn "vmslg"
1193 [(set (match_operand:TI 0 "register_operand" "=v")
1194 (unspec:TI [(match_operand:V2DI 1 "register_operand" "v")
1195 (match_operand:V2DI 2 "register_operand" "v")
1196 (match_operand:TI 3 "register_operand" "v")
1197 (match_operand:QI 4 "const_mask_operand" "C")]
1200 "vmslg\t%v0,%v1,%v2,%v3,%4"
1201 [(set_attr "op_type" "VRR")])
1204 ; Vector find any element equal
1206 ; vfaeb, vfaeh, vfaef
1207 ; vfaezb, vfaezh, vfaezf
1208 (define_insn "vfae<mode>"
1209 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1210 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1211 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1212 (match_operand:QI 3 "const_mask_operand" "C")]
1216 unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
1218 if (flags & VSTRING_FLAG_ZS)
1220 flags &= ~VSTRING_FLAG_ZS;
1221 operands[3] = GEN_INT (flags);
1222 return "vfaez<bhfgq>\t%v0,%v1,%v2,%b3";
1224 return "vfae<bhfgq>\t%v0,%v1,%v2,%b3";
1226 [(set_attr "op_type" "VRR")])
1228 ; vfaebs, vfaehs, vfaefs
1229 ; vfaezbs, vfaezhs, vfaezfs
1230 (define_insn "*vfaes<mode>"
1231 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1232 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1233 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1234 (match_operand:QI 3 "const_mask_operand" "C")]
1236 (set (reg:CCRAW CC_REGNUM)
1237 (unspec:CCRAW [(match_dup 1)
1240 UNSPEC_VEC_VFAECC))]
1243 unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
1245 if (flags & VSTRING_FLAG_ZS)
1247 flags &= ~VSTRING_FLAG_ZS;
1248 operands[3] = GEN_INT (flags);
1249 return "vfaez<bhfgq>s\t%v0,%v1,%v2,%b3";
1251 return "vfae<bhfgq>s\t%v0,%v1,%v2,%b3";
1253 [(set_attr "op_type" "VRR")])
1255 (define_expand "vfaez<mode>"
1256 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1257 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1258 (match_operand:VI_HW_QHS 2 "register_operand" "")
1259 (match_operand:QI 3 "const_mask_operand" "")]
1263 operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_ZS);
1266 (define_expand "vfaes<mode>"
1268 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1269 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1270 (match_operand:VI_HW_QHS 2 "register_operand" "")
1271 (match_operand:QI 3 "const_mask_operand" "")]
1273 (set (reg:CCRAW CC_REGNUM)
1274 (unspec:CCRAW [(match_dup 1)
1277 UNSPEC_VEC_VFAECC))])
1278 (set (match_operand:SI 4 "memory_operand" "")
1279 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1282 operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS);
1285 (define_expand "vfaezs<mode>"
1287 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1288 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1289 (match_operand:VI_HW_QHS 2 "register_operand" "")
1290 (match_operand:SI 3 "const_mask_operand" "")]
1292 (set (reg:CCRAW CC_REGNUM)
1293 (unspec:CCRAW [(match_dup 1)
1296 UNSPEC_VEC_VFAECC))])
1297 (set (match_operand:SI 4 "memory_operand" "")
1298 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1301 operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
1305 ; Vector find element equal
1307 ; vfeebs, vfeehs, vfeefs
1308 ; vfeezbs, vfeezhs, vfeezfs
1309 (define_insn "*vfees<mode>"
1310 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1311 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1312 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1313 (match_operand:QI 3 "const_mask_operand" "C")]
1315 (set (reg:CCRAW CC_REGNUM)
1316 (unspec:CCRAW [(match_dup 1)
1319 UNSPEC_VEC_VFEECC))]
1322 unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
1324 gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS)));
1325 flags &= ~VSTRING_FLAG_CS;
1327 if (flags == VSTRING_FLAG_ZS)
1328 return "vfeez<bhfgq>s\t%v0,%v1,%v2";
1329 return "vfee<bhfgq>s\t%v0,%v1,%v2,%b3";
1331 [(set_attr "op_type" "VRR")])
1333 ; vfeeb, vfeeh, vfeef
1334 (define_insn "vfee<mode>"
1335 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1336 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1337 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1341 "vfee<bhfgq>\t%v0,%v1,%v2,0"
1342 [(set_attr "op_type" "VRR")])
1344 ; vfeezb, vfeezh, vfeezf
1345 (define_insn "vfeez<mode>"
1346 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1347 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1348 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1349 (const_int VSTRING_FLAG_ZS)]
1352 "vfeez<bhfgq>s\t%v0,%v1,%v2,2"
1353 [(set_attr "op_type" "VRR")])
1355 (define_expand "vfees<mode>"
1357 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1358 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1359 (match_operand:VI_HW_QHS 2 "register_operand" "")
1360 (const_int VSTRING_FLAG_CS)]
1362 (set (reg:CCRAW CC_REGNUM)
1363 (unspec:CCRAW [(match_dup 1)
1365 (const_int VSTRING_FLAG_CS)]
1366 UNSPEC_VEC_VFEECC))])
1367 (set (match_operand:SI 3 "memory_operand" "")
1368 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1371 (define_expand "vfeezs<mode>"
1373 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1374 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1375 (match_operand:VI_HW_QHS 2 "register_operand" "")
1378 (set (reg:CCRAW CC_REGNUM)
1379 (unspec:CCRAW [(match_dup 1)
1382 UNSPEC_VEC_VFEECC))])
1383 (set (match_operand:SI 3 "memory_operand" "")
1384 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1387 operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS);
1390 ; Vector find element not equal
1392 ; vfeneb, vfeneh, vfenef
1393 (define_insn "vfene<mode>"
1394 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1395 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1396 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1400 "vfene<bhfgq>\t%v0,%v1,%v2,0"
1401 [(set_attr "op_type" "VRR")])
1403 ; vec_vfenes can be found in vector.md since it is used for strlen
1405 ; vfenezb, vfenezh, vfenezf
1406 (define_insn "vfenez<mode>"
1407 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1408 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1409 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1410 (const_int VSTRING_FLAG_ZS)]
1413 "vfenez<bhfgq>\t%v0,%v1,%v2"
1414 [(set_attr "op_type" "VRR")])
1416 (define_expand "vfenes<mode>"
1418 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1419 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1420 (match_operand:VI_HW_QHS 2 "register_operand" "")
1421 (const_int VSTRING_FLAG_CS)]
1423 (set (reg:CCRAW CC_REGNUM)
1424 (unspec:CCRAW [(match_dup 1)
1426 (const_int VSTRING_FLAG_CS)]
1427 UNSPEC_VEC_VFENECC))])
1428 (set (match_operand:SI 3 "memory_operand" "")
1429 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1432 (define_expand "vfenezs<mode>"
1434 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1435 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1436 (match_operand:VI_HW_QHS 2 "register_operand" "")
1439 (set (reg:CCRAW CC_REGNUM)
1440 (unspec:CCRAW [(match_dup 1)
1443 UNSPEC_VEC_VFENECC))])
1444 (set (match_operand:SI 3 "memory_operand" "")
1445 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1448 operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS);
1451 ; Vector isolate string
1453 ; vistrb, vistrh, vistrf
1454 (define_insn "vistr<mode>"
1455 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1456 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
1459 "vistr<bhfgq>\t%v0,%v1"
1460 [(set_attr "op_type" "VRR")])
1462 ; vistrbs, vistrhs, vistrfs
1463 (define_insn "*vistrs<mode>"
1464 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1465 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
1467 (set (reg:CCRAW CC_REGNUM)
1468 (unspec:CCRAW [(match_dup 1)] UNSPEC_VEC_VISTRCC))]
1470 "vistr<bhfgq>s\t%v0,%v1"
1471 [(set_attr "op_type" "VRR")])
1473 (define_expand "vistrs<mode>"
1475 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1476 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")]
1478 (set (reg:CCRAW CC_REGNUM)
1479 (unspec:CCRAW [(match_dup 1)]
1480 UNSPEC_VEC_VISTRCC))])
1481 (set (match_operand:SI 2 "memory_operand" "")
1482 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1486 ; Vector compare range
1488 ; vstrcb, vstrch, vstrcf
1489 ; vstrczb, vstrczh, vstrczf
1490 (define_insn "vstrc<mode>"
1491 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1492 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1493 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1494 (match_operand:VI_HW_QHS 3 "register_operand" "v")
1495 (match_operand:QI 4 "const_mask_operand" "C")]
1499 unsigned HOST_WIDE_INT flags = UINTVAL (operands[4]);
1501 if (flags & VSTRING_FLAG_ZS)
1503 flags &= ~VSTRING_FLAG_ZS;
1504 operands[4] = GEN_INT (flags);
1505 return "vstrcz<bhfgq>\t%v0,%v1,%v2,%v3,%b4";
1507 return "vstrc<bhfgq>\t%v0,%v1,%v2,%v3,%b4";
1509 [(set_attr "op_type" "VRR")])
1511 ; vstrcbs, vstrchs, vstrcfs
1512 ; vstrczbs, vstrczhs, vstrczfs
1513 (define_insn "*vstrcs<mode>"
1514 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1515 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1516 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1517 (match_operand:VI_HW_QHS 3 "register_operand" "v")
1518 (match_operand:QI 4 "const_mask_operand" "C")]
1520 (set (reg:CCRAW CC_REGNUM)
1521 (unspec:CCRAW [(match_dup 1)
1525 UNSPEC_VEC_VSTRCCC))]
1528 unsigned HOST_WIDE_INT flags = UINTVAL (operands[4]);
1530 if (flags & VSTRING_FLAG_ZS)
1532 flags &= ~VSTRING_FLAG_ZS;
1533 operands[4] = GEN_INT (flags);
1534 return "vstrcz<bhfgq>s\t%v0,%v1,%v2,%v3,%b4";
1536 return "vstrc<bhfgq>s\t%v0,%v1,%v2,%v3,%b4";
1538 [(set_attr "op_type" "VRR")])
1540 (define_expand "vstrcz<mode>"
1541 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1542 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1543 (match_operand:VI_HW_QHS 2 "register_operand" "")
1544 (match_operand:VI_HW_QHS 3 "register_operand" "")
1545 (match_operand:QI 4 "const_mask_operand" "")]
1549 operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_ZS);
1552 (define_expand "vstrcs<mode>"
1554 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1555 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1556 (match_operand:VI_HW_QHS 2 "register_operand" "")
1557 (match_operand:VI_HW_QHS 3 "register_operand" "")
1558 (match_operand:QI 4 "const_mask_operand" "")]
1560 (set (reg:CCRAW CC_REGNUM)
1561 (unspec:CCRAW [(match_dup 1)
1565 UNSPEC_VEC_VSTRCCC))])
1566 (set (match_operand:SI 5 "memory_operand" "")
1567 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1570 operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS);
1573 (define_expand "vstrczs<mode>"
1575 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1576 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1577 (match_operand:VI_HW_QHS 2 "register_operand" "")
1578 (match_operand:VI_HW_QHS 3 "register_operand" "")
1579 (match_operand:QI 4 "const_mask_operand" "")]
1581 (set (reg:CCRAW CC_REGNUM)
1582 (unspec:CCRAW [(match_dup 1)
1586 UNSPEC_VEC_VSTRCCC))])
1587 (set (match_operand:SI 5 "memory_operand" "")
1588 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1591 operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
1594 (define_insn "vcdgb"
1595 [(set (match_operand:V2DF 0 "register_operand" "=v")
1596 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
1597 (match_operand:QI 2 "const_mask_operand" "C") ; inexact suppression
1598 (match_operand:QI 3 "const_mask_operand" "C")] ; rounding mode
1600 "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1601 "vcdgb\t%v0,%v1,%b2,%b3"
1602 [(set_attr "op_type" "VRR")])
1605 ; The result needs to be multiplied with 2**-op2
1606 (define_expand "vec_ctd_s64"
1607 [(set (match_operand:V2DF 0 "register_operand" "")
1608 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
1609 (const_int 4) ; inexact suppressed
1610 (const_int VEC_RND_CURRENT)]
1612 (use (match_operand:QI 2 "const_int_operand" ""))
1613 (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
1619 real_2expN (&f, -INTVAL (operands[2]), DFmode);
1620 c = const_double_from_real_value (f, DFmode);
1622 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1623 operands[3] = force_reg (V2DFmode, operands[3]);
1626 (define_insn "vcdlgb"
1627 [(set (match_operand:V2DF 0 "register_operand" "=v")
1628 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
1629 (match_operand:QI 2 "const_mask_operand" "C") ; inexact suppression
1630 (match_operand:QI 3 "const_mask_operand" "C")] ; rounding mode
1631 UNSPEC_VEC_VCDLGB))]
1632 "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1633 "vcdlgb\t%v0,%v1,%b2,%b3"
1634 [(set_attr "op_type" "VRR")])
1636 ; The result needs to be multiplied with 2**-op2
1637 (define_expand "vec_ctd_u64"
1638 [(set (match_operand:V2DF 0 "register_operand" "")
1639 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
1640 (const_int 4) ; inexact suppressed
1641 (const_int VEC_RND_CURRENT)]
1643 (use (match_operand:QI 2 "const_int_operand" ""))
1644 (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
1650 real_2expN (&f, -INTVAL (operands[2]), DFmode);
1651 c = const_double_from_real_value (f, DFmode);
1653 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1654 operands[3] = force_reg (V2DFmode, operands[3]);
1657 (define_insn "vcgdb"
1658 [(set (match_operand:V2DI 0 "register_operand" "=v")
1659 (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
1660 (match_operand:QI 2 "const_mask_operand" "C")
1661 (match_operand:QI 3 "const_mask_operand" "C")]
1663 "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1664 "vcgdb\t%v0,%v1,%b2,%b3"
1665 [(set_attr "op_type" "VRR")])
1667 ; The input needs to be multiplied with 2**op2
1668 (define_expand "vec_ctsl"
1669 [(use (match_operand:QI 2 "const_int_operand" ""))
1670 (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
1672 (set (match_operand:V2DI 0 "register_operand" "")
1673 (unspec:V2DI [(match_dup 4)
1674 (const_int 4) ; inexact suppressed
1675 (const_int VEC_RND_CURRENT)]
1682 real_2expN (&f, INTVAL (operands[2]), DFmode);
1683 c = const_double_from_real_value (f, DFmode);
1685 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1686 operands[3] = force_reg (V2DFmode, operands[3]);
1687 operands[4] = gen_reg_rtx (V2DFmode);
1690 (define_insn "vclgdb"
1691 [(set (match_operand:V2DI 0 "register_operand" "=v")
1692 (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
1693 (match_operand:QI 2 "const_mask_operand" "C")
1694 (match_operand:QI 3 "const_mask_operand" "C")]
1695 UNSPEC_VEC_VCLGDB))]
1696 "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1697 "vclgdb\t%v0,%v1,%b2,%b3"
1698 [(set_attr "op_type" "VRR")])
1700 ; The input needs to be multiplied with 2**op2
1701 (define_expand "vec_ctul"
1702 [(use (match_operand:QI 2 "const_int_operand" ""))
1703 (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
1705 (set (match_operand:V2DI 0 "register_operand" "")
1706 (unspec:V2DI [(match_dup 4)
1707 (const_int 4) ; inexact suppressed
1708 (const_int VEC_RND_CURRENT)]
1709 UNSPEC_VEC_VCLGDB))]
1715 real_2expN (&f, INTVAL (operands[2]), DFmode);
1716 c = const_double_from_real_value (f, DFmode);
1718 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1719 operands[3] = force_reg (V2DFmode, operands[3]);
1720 operands[4] = gen_reg_rtx (V2DFmode);
1723 ; Vector load fp integer - IEEE inexact exception is suppressed
1724 ; vfisb, vfidb, wfisb, wfidb, wfixb
1725 (define_insn "vec_fpint<mode>"
1726 [(set (match_operand:VFT 0 "register_operand" "=v")
1727 (unspec:VFT [(match_operand:VFT 1 "register_operand" "v")
1728 (match_operand:QI 2 "const_mask_operand" "C") ; inexact suppression control
1729 (match_operand:QI 3 "const_mask_operand" "C")] ; rounding mode
1732 "<vw>fi<sdx>b\t%v0,%v1,%b2,%b3"
1733 [(set_attr "op_type" "VRR")])
1736 ; Vector load lengthened - V4SF -> V2DF
1738 (define_insn "vflls"
1739 [(set (match_operand:V2DF 0 "register_operand" "=v")
1740 (unspec:V2DF [(match_operand:V4SF 1 "register_operand" "v")]
1744 [(set_attr "op_type" "VRR")])
1746 (define_expand "vec_ld2f"
1747 [; Initialize a vector to all zeroes. FIXME: This should not be
1748 ; necessary since all elements of the vector will be set anyway.
1749 ; This is just to make it explicit to the data flow framework.
1750 (set (match_dup 2) (match_dup 3))
1751 (set (match_dup 2) (unspec:V4SF [(match_operand:SF 1 "memory_operand" "")
1755 (set (match_dup 2) (unspec:V4SF [(match_dup 4)
1759 (set (match_operand:V2DF 0 "register_operand" "")
1760 (unspec:V2DF [(match_dup 2)] UNSPEC_VEC_VFLL))]
1763 operands[2] = gen_reg_rtx (V4SFmode);
1764 operands[3] = CONST0_RTX (V4SFmode);
1765 operands[4] = adjust_address (operands[1], SFmode, 4);
1769 ; Vector load rounded - V2DF -> V4SF
1771 (define_insn "vflrd"
1772 [(set (match_operand:V4SF 0 "register_operand" "=v")
1773 (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "v")
1774 (match_operand:QI 2 "const_mask_operand" "C")
1775 (match_operand:QI 3 "const_mask_operand" "C")]
1778 "vledb\t%v0,%v1,%b2,%b3"
1779 [(set_attr "op_type" "VRR")])
1781 (define_expand "vec_st2f"
1783 (unspec:V4SF [(match_operand:V2DF 0 "register_operand" "")
1784 (const_int VEC_INEXACT)
1785 (const_int VEC_RND_CURRENT)]
1787 (set (match_operand:SF 1 "memory_operand" "")
1788 (unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT))
1790 (unspec:SF [(match_dup 2) (const_int 2)] UNSPEC_VEC_EXTRACT))]
1793 operands[2] = gen_reg_rtx (V4SFmode);
1794 operands[3] = adjust_address (operands[1], SFmode, 4);
1798 ; Vector square root fp vec_sqrt -> sqrt rtx standard name
1800 ;; Vector FP test data class immediate
1802 ; vec_all_nan, vec_all_numeric, vec_any_nan, vec_any_numeric
1803 ; These ignore the vector result and only want CC stored to an int
1807 (define_insn "*vftci<mode>_cconly"
1808 [(set (reg:CCRAW CC_REGNUM)
1809 (unspec:CCRAW [(match_operand:VECF_HW 1 "register_operand")
1810 (match_operand:HI 2 "const_int_operand")]
1811 UNSPEC_VEC_VFTCICC))
1812 (clobber (match_scratch:<tointvec> 0))]
1813 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
1814 "vftci<sdx>b\t%v0,%v1,%x2"
1815 [(set_attr "op_type" "VRR")])
1817 (define_expand "vftci<mode>_intcconly"
1819 [(set (reg:CCRAW CC_REGNUM)
1820 (unspec:CCRAW [(match_operand:VECF_HW 0 "register_operand")
1821 (match_operand:HI 1 "const_int_operand")]
1822 UNSPEC_VEC_VFTCICC))
1823 (clobber (scratch:<tointvec>))])
1824 (set (match_operand:SI 2 "register_operand" "")
1825 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1826 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")")
1828 ; vec_fp_test_data_class wants the result vector and the CC stored to
1832 (define_insn "*vftci<mode>"
1833 [(set (match_operand:VECF_HW 0 "register_operand" "=v")
1834 (unspec:VECF_HW [(match_operand:VECF_HW 1 "register_operand" "v")
1835 (match_operand:HI 2 "const_int_operand" "J")]
1837 (set (reg:CCRAW CC_REGNUM)
1838 (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCICC))]
1839 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
1840 "vftci<sdx>b\t%v0,%v1,%x2"
1841 [(set_attr "op_type" "VRR")])
1843 (define_expand "vftci<mode>_intcc"
1845 [(set (match_operand:VECF_HW 0 "register_operand")
1846 (unspec:VECF_HW [(match_operand:VECF_HW 1 "register_operand")
1847 (match_operand:HI 2 "const_int_operand")]
1849 (set (reg:CCRAW CC_REGNUM)
1850 (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCICC))])
1851 (set (match_operand:SI 3 "memory_operand" "")
1852 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1853 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")")
1859 ; All comparisons which produce a CC need fully populated (VI_HW)
1860 ; vector arguments. Otherwise the any/all CCs would be just bogus.
1862 (define_insn "*vec_cmp<VICMP:insn_cmp><VI_HW:mode>_cconly"
1863 [(set (reg:VICMP CC_REGNUM)
1864 (compare:VICMP (match_operand:VI_HW 0 "register_operand" "v")
1865 (match_operand:VI_HW 1 "register_operand" "v")))
1866 (clobber (match_scratch:VI_HW 2 "=v"))]
1868 "vc<VICMP:insn_cmp><VI_HW:bhfgq>s\t%v2,%v0,%v1"
1869 [(set_attr "op_type" "VRR")])
1871 ; FIXME: The following 2x3 definitions should be merged into 2 with
1872 ; VICMP like above but I could not find a way to set the comparison
1873 ; operator (eq) depending on the mode CCVEQ (mode_iterator). Or the
1874 ; other way around - setting the mode depending on the code
1876 (define_expand "vec_cmpeq<VI_HW:mode>_cc"
1878 [(set (reg:CCVEQ CC_REGNUM)
1879 (compare:CCVEQ (match_operand:VI_HW 1 "register_operand" "v")
1880 (match_operand:VI_HW 2 "register_operand" "v")))
1881 (set (match_operand:VI_HW 0 "register_operand" "=v")
1882 (eq:VI_HW (match_dup 1) (match_dup 2)))])
1883 (set (match_operand:SI 3 "memory_operand" "")
1884 (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
1887 (define_expand "vec_cmph<VI_HW:mode>_cc"
1889 [(set (reg:CCVIH CC_REGNUM)
1890 (compare:CCVIH (match_operand:VI_HW 1 "register_operand" "v")
1891 (match_operand:VI_HW 2 "register_operand" "v")))
1892 (set (match_operand:VI_HW 0 "register_operand" "=v")
1893 (gt:VI_HW (match_dup 1) (match_dup 2)))])
1894 (set (match_operand:SI 3 "memory_operand" "")
1895 (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
1898 (define_expand "vec_cmphl<VI_HW:mode>_cc"
1900 [(set (reg:CCVIHU CC_REGNUM)
1901 (compare:CCVIHU (match_operand:VI_HW 1 "register_operand" "v")
1902 (match_operand:VI_HW 2 "register_operand" "v")))
1903 (set (match_operand:VI_HW 0 "register_operand" "=v")
1904 (gtu:VI_HW (match_dup 1) (match_dup 2)))])
1905 (set (match_operand:SI 3 "memory_operand" "")
1906 (unspec:SI [(reg:CCVIHU CC_REGNUM)] UNSPEC_CC_TO_INT))]
1910 (define_insn "*vec_cmpeq<VI_HW:mode>_cc"
1911 [(set (reg:CCVEQ CC_REGNUM)
1912 (compare:CCVEQ (match_operand:VI_HW 0 "register_operand" "v")
1913 (match_operand:VI_HW 1 "register_operand" "v")))
1914 (set (match_operand:VI_HW 2 "register_operand" "=v")
1915 (eq:VI_HW (match_dup 0) (match_dup 1)))]
1917 "vceq<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1918 [(set_attr "op_type" "VRR")])
1920 (define_insn "*vec_cmph<VI_HW:mode>_cc"
1921 [(set (reg:CCVIH CC_REGNUM)
1922 (compare:CCVIH (match_operand:VI_HW 0 "register_operand" "v")
1923 (match_operand:VI_HW 1 "register_operand" "v")))
1924 (set (match_operand:VI_HW 2 "register_operand" "=v")
1925 (gt:VI_HW (match_dup 0) (match_dup 1)))]
1927 "vch<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1928 [(set_attr "op_type" "VRR")])
1930 (define_insn "*vec_cmphl<VI_HW:mode>_cc"
1931 [(set (reg:CCVIHU CC_REGNUM)
1932 (compare:CCVIHU (match_operand:VI_HW 0 "register_operand" "v")
1933 (match_operand:VI_HW 1 "register_operand" "v")))
1934 (set (match_operand:VI_HW 2 "register_operand" "=v")
1935 (gtu:VI_HW (match_dup 0) (match_dup 1)))]
1937 "vchl<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1938 [(set_attr "op_type" "VRR")])
1941 ;; Floating point compares
1944 ; vfcesbs, vfcedbs, wfcexbs, vfchsbs, vfchdbs, wfchxbs, vfchesbs, vfchedbs, wfchexbs
1945 (define_insn "*vec_cmp<insn_cmp><mode>_cconly"
1946 [(set (reg:VFCMP CC_REGNUM)
1947 (compare:VFCMP (match_operand:VF_HW 0 "register_operand" "v")
1948 (match_operand:VF_HW 1 "register_operand" "v")))
1949 (clobber (match_scratch:<tointvec> 2 "=v"))]
1951 "<vw>fc<asm_fcmp><sdx>bs\t%v2,%v0,%v1"
1952 [(set_attr "op_type" "VRR")])
1954 ; FIXME: Merge the following 2x3 patterns with VFCMP
1955 (define_expand "vec_cmpeq<mode>_cc"
1957 [(set (reg:CCVEQ CC_REGNUM)
1958 (compare:CCVEQ (match_operand:VF_HW 1 "register_operand" "v")
1959 (match_operand:VF_HW 2 "register_operand" "v")))
1960 (set (match_operand:<tointvec> 0 "register_operand" "=v")
1961 (eq:<tointvec> (match_dup 1) (match_dup 2)))])
1962 (set (match_operand:SI 3 "memory_operand" "")
1963 (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
1966 (define_expand "vec_cmph<mode>_cc"
1968 [(set (reg:CCVFH CC_REGNUM)
1969 (compare:CCVFH (match_operand:VF_HW 1 "register_operand" "v")
1970 (match_operand:VF_HW 2 "register_operand" "v")))
1971 (set (match_operand:<tointvec> 0 "register_operand" "=v")
1972 (gt:<tointvec> (match_dup 1) (match_dup 2)))])
1973 (set (match_operand:SI 3 "memory_operand" "")
1974 (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
1977 (define_expand "vec_cmphe<mode>_cc"
1979 [(set (reg:CCVFHE CC_REGNUM)
1980 (compare:CCVFHE (match_operand:VF_HW 1 "register_operand" "v")
1981 (match_operand:VF_HW 2 "register_operand" "v")))
1982 (set (match_operand:<tointvec> 0 "register_operand" "=v")
1983 (ge:<tointvec> (match_dup 1) (match_dup 2)))])
1984 (set (match_operand:SI 3 "memory_operand" "")
1985 (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))]
1988 ; These 3 cannot be merged as the insn defintion above since it also
1989 ; requires to rewrite the RTL equality operator that the same time as
1992 ; vfcesbs, vfcedbs, wfcexbs
1993 (define_insn "*vec_cmpeq<mode>_cc"
1994 [(set (reg:CCVEQ CC_REGNUM)
1995 (compare:CCVEQ (match_operand:VF_HW 0 "register_operand" "v")
1996 (match_operand:VF_HW 1 "register_operand" "v")))
1997 (set (match_operand:<tointvec> 2 "register_operand" "=v")
1998 (eq:<tointvec> (match_dup 0) (match_dup 1)))]
2000 "<vw>fce<sdx>bs\t%v2,%v0,%v1"
2001 [(set_attr "op_type" "VRR")])
2003 ; vfchsbs, vfchdbs, wfchxbs
2004 (define_insn "*vec_cmph<mode>_cc"
2005 [(set (reg:CCVFH CC_REGNUM)
2006 (compare:CCVFH (match_operand:VF_HW 0 "register_operand" "v")
2007 (match_operand:VF_HW 1 "register_operand" "v")))
2008 (set (match_operand:<tointvec> 2 "register_operand" "=v")
2009 (gt:<tointvec> (match_dup 0) (match_dup 1)))]
2011 "<vw>fch<sdx>bs\t%v2,%v0,%v1"
2012 [(set_attr "op_type" "VRR")])
2014 ; vfchesbs, vfchedbs, wfchexbs
2015 (define_insn "*vec_cmphe<mode>_cc"
2016 [(set (reg:CCVFHE CC_REGNUM)
2017 (compare:CCVFHE (match_operand:VF_HW 0 "register_operand" "v")
2018 (match_operand:VF_HW 1 "register_operand" "v")))
2019 (set (match_operand:<tointvec> 2 "register_operand" "=v")
2020 (ge:<tointvec> (match_dup 0) (match_dup 1)))]
2022 "<vw>fche<sdx>bs\t%v2,%v0,%v1"
2023 [(set_attr "op_type" "VRR")])
2025 (define_expand "vec_double_s64"
2026 [(set (match_operand:V2DF 0 "register_operand")
2027 (unspec:V2DF [(match_operand:V2DI 1 "register_operand")
2028 (const_int 0) ; inexact suppression disabled
2029 (const_int VEC_RND_CURRENT)]
2033 (define_expand "vec_double_u64"
2034 [(set (match_operand:V2DF 0 "register_operand")
2035 (unspec:V2DF [(match_operand:V2DI 1 "register_operand")
2036 (const_int 0) ; inexact suppression disabled
2037 (const_int VEC_RND_CURRENT)]
2038 UNSPEC_VEC_VCDLGB))]
2042 (define_insn "vfmin<mode>"
2043 [(set (match_operand:VF_HW 0 "register_operand" "=v")
2044 (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
2045 (match_operand:VF_HW 2 "register_operand" "v")
2046 (match_operand:QI 3 "const_mask_operand" "C")]
2049 "<vw>fmin<sdx>b\t%v0,%v1,%v2,%b3"
2050 [(set_attr "op_type" "VRR")])
2052 (define_insn "vfmax<mode>"
2053 [(set (match_operand:VF_HW 0 "register_operand" "=v")
2054 (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
2055 (match_operand:VF_HW 2 "register_operand" "v")
2056 (match_operand:QI 3 "const_mask_operand" "C")]
2059 "<vw>fmax<sdx>b\t%v0,%v1,%v2,%b3"
2060 [(set_attr "op_type" "VRR")])