| blob | d116a6353843713bd21320d856650b0378079002 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; `unspec' values used in rs6000.md:
26 ;; Number Use
27 ;; 0 frsp for POWER machines
28 ;; 0/v blockage
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
32 ;; 8 movsi_got
33 ;; 9/v eh_reg_restore
34 ;; 10 fctiwz
35 ;; 19 movesi_from_cr
36 ;; 20 movesi_to_cr
37 \f
38 ;; Define an insn type attribute. This is used in function unit delay
39 ;; computations.
40 (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
41 (const_string "integer"))
43 ;; Length (in bytes).
44 ; '(pc)' in the following doesn't include the instruction itself; it is
45 ; calculated as if the instruction had zero size.
46 (define_attr "length" ""
47 (if_then_else (eq_attr "type" "branch")
48 (if_then_else (and (ge (minus (match_dup 0) (pc))
49 (const_int -32768))
50 (lt (minus (match_dup 0) (pc))
51 (const_int 32764)))
52 (const_int 4)
53 (const_int 8))
54 (const_int 4)))
56 ;; Processor type -- this attribute must exactly match the processor_type
57 ;; enumeration in rs6000.h.
59 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"
60 (const (symbol_ref "rs6000_cpu_attr")))
62 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
63 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
65 ; Load/Store Unit -- pure PowerPC only
66 ; (POWER and 601 use Integer Unit)
67 (define_function_unit "lsu" 1 0
68 (and (eq_attr "type" "load")
69 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
70 2 1)
72 (define_function_unit "lsu" 1 0
73 (and (eq_attr "type" "store,fpstore")
74 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
75 1 1)
77 (define_function_unit "lsu" 1 0
78 (and (eq_attr "type" "fpload")
79 (eq_attr "cpu" "mpccore,ppc603,ppc750"))
80 2 1)
82 (define_function_unit "lsu" 1 0
83 (and (eq_attr "type" "fpload")
84 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
85 3 1)
87 (define_function_unit "iu" 1 0
88 (and (eq_attr "type" "load")
89 (eq_attr "cpu" "rios1,ppc403,ppc601"))
90 2 1)
92 (define_function_unit "iu" 1 0
93 (and (eq_attr "type" "store,fpstore")
94 (eq_attr "cpu" "rios1,ppc403,ppc601"))
95 1 1)
97 (define_function_unit "fpu" 1 0
98 (and (eq_attr "type" "fpstore")
99 (eq_attr "cpu" "rios1,ppc601"))
100 0 1)
102 (define_function_unit "iu" 1 0
103 (and (eq_attr "type" "fpload")
104 (eq_attr "cpu" "rios1"))
105 2 1)
107 (define_function_unit "iu" 1 0
108 (and (eq_attr "type" "fpload")
109 (eq_attr "cpu" "ppc601"))
110 3 1)
112 (define_function_unit "iu2" 2 0
113 (and (eq_attr "type" "load,fpload")
114 (eq_attr "cpu" "rios2"))
115 2 1)
117 (define_function_unit "iu2" 2 0
118 (and (eq_attr "type" "store,fpstore")
119 (eq_attr "cpu" "rios2"))
120 1 1)
122 ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
123 (define_function_unit "iu" 1 0
124 (and (eq_attr "type" "integer")
125 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
126 1 1)
128 (define_function_unit "iu" 1 0
129 (and (eq_attr "type" "cr_logical")
130 (eq_attr "cpu" "mpccore,ppc403,ppc601"))
131 1 1)
133 (define_function_unit "iu" 1 0
134 (and (eq_attr "type" "imul")
135 (eq_attr "cpu" "ppc403"))
136 4 4)
138 (define_function_unit "iu" 1 0
139 (and (eq_attr "type" "imul")
140 (eq_attr "cpu" "rios1,ppc601,ppc603"))
141 5 5)
143 (define_function_unit "iu" 1 0
144 (and (eq_attr "type" "imul")
145 (eq_attr "cpu" "rs64a"))
146 20 14)
148 (define_function_unit "iu" 1 0
149 (and (eq_attr "type" "lmul")
150 (eq_attr "cpu" "rs64a"))
151 34 34)
153 (define_function_unit "iu" 1 0
154 (and (eq_attr "type" "idiv")
155 (eq_attr "cpu" "rios1"))
156 19 19)
158 (define_function_unit "iu" 1 0
159 (and (eq_attr "type" "idiv")
160 (eq_attr "cpu" "rs64a"))
161 66 66)
163 (define_function_unit "iu" 1 0
164 (and (eq_attr "type" "ldiv")
165 (eq_attr "cpu" "rs64a"))
166 66 66)
168 (define_function_unit "iu" 1 0
169 (and (eq_attr "type" "idiv")
170 (eq_attr "cpu" "ppc403"))
171 33 33)
173 (define_function_unit "iu" 1 0
174 (and (eq_attr "type" "idiv")
175 (eq_attr "cpu" "ppc601"))
176 36 36)
178 (define_function_unit "iu" 1 0
179 (and (eq_attr "type" "idiv")
180 (eq_attr "cpu" "ppc603"))
181 37 36)
183 ; RIOS2 has two integer units: a primary one which can perform all
184 ; operations and a secondary one which is fed in lock step with the first
185 ; and can perform "simple" integer operations.
186 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
187 ; for the complex insns.
188 (define_function_unit "iu2" 2 0
189 (and (eq_attr "type" "integer")
190 (eq_attr "cpu" "rios2"))
191 1 1)
193 (define_function_unit "iu2" 2 0
194 (and (eq_attr "type" "imul")
195 (eq_attr "cpu" "rios2"))
196 2 2)
198 (define_function_unit "iu2" 2 0
199 (and (eq_attr "type" "idiv")
200 (eq_attr "cpu" "rios2"))
201 13 13)
203 (define_function_unit "imuldiv" 1 0
204 (and (eq_attr "type" "imul")
205 (eq_attr "cpu" "rios2"))
206 2 2)
208 (define_function_unit "imuldiv" 1 0
209 (and (eq_attr "type" "idiv")
210 (eq_attr "cpu" "rios2"))
211 13 13)
213 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
214 ; Divide latency varies greatly from 2-11, use 6 as average
215 (define_function_unit "imuldiv" 1 0
216 (and (eq_attr "type" "imul")
217 (eq_attr "cpu" "mpccore"))
218 2 1)
220 (define_function_unit "imuldiv" 1 0
221 (and (eq_attr "type" "idiv")
222 (eq_attr "cpu" "mpccore"))
223 6 6)
225 ; PPC604{,e} has two units that perform integer operations
226 ; and one unit for divide/multiply operations (and move
227 ; from/to spr).
228 (define_function_unit "iu2" 2 0
229 (and (eq_attr "type" "integer")
230 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
231 1 1)
233 (define_function_unit "imuldiv" 1 0
234 (and (eq_attr "type" "imul")
235 (eq_attr "cpu" "ppc604"))
236 4 2)
238 (define_function_unit "imuldiv" 1 0
239 (and (eq_attr "type" "imul")
240 (eq_attr "cpu" "ppc620,ppc630"))
241 5 3)
243 (define_function_unit "imuldiv" 1 0
244 (and (eq_attr "type" "lmul")
245 (eq_attr "cpu" "ppc620,ppc630"))
246 5 3)
248 (define_function_unit "imuldiv" 1 0
249 (and (eq_attr "type" "imul")
250 (eq_attr "cpu" "ppc604e"))
251 2 1)
253 (define_function_unit "imuldiv" 1 0
254 (and (eq_attr "type" "idiv")
255 (eq_attr "cpu" "ppc604,ppc604e"))
256 20 19)
258 (define_function_unit "imuldiv" 1 0
259 (and (eq_attr "type" "idiv")
260 (eq_attr "cpu" "ppc620"))
261 37 36)
263 (define_function_unit "imuldiv" 1 0
264 (and (eq_attr "type" "idiv")
265 (eq_attr "cpu" "ppc630"))
266 21 20)
268 (define_function_unit "imuldiv" 1 0
269 (and (eq_attr "type" "ldiv")
270 (eq_attr "cpu" "ppc620,ppc630"))
271 37 36)
273 ; PPC750 has two integer units: a primary one which can perform all
274 ; operations and a secondary one which is fed in lock step with the first
275 ; and can perform "simple" integer operations.
276 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
277 ; for the complex insns.
278 (define_function_unit "iu2" 2 0
279 (and (eq_attr "type" "integer")
280 (eq_attr "cpu" "ppc750"))
281 1 1)
283 (define_function_unit "iu2" 2 0
284 (and (eq_attr "type" "imul")
285 (eq_attr "cpu" "ppc750"))
286 4 2)
288 (define_function_unit "imuldiv" 1 0
289 (and (eq_attr "type" "imul")
290 (eq_attr "cpu" "ppc750"))
291 4 2)
293 (define_function_unit "imuldiv" 1 0
294 (and (eq_attr "type" "idiv")
295 (eq_attr "cpu" "ppc750"))
296 19 19)
298 ; CR-logical operations are execute-serialized, that is they don't
299 ; start (and block the function unit) until all preceding operations
300 ; have finished. They don't block dispatch of other insns, though.
301 ; I've imitated this by giving them longer latency.
302 (define_function_unit "sru" 1 0
303 (and (eq_attr "type" "cr_logical")
304 (eq_attr "cpu" "ppc603,ppc750"))
305 3 2)
307 ; compare is done on integer unit, but feeds insns which
308 ; execute on the branch unit.
309 (define_function_unit "iu" 1 0
310 (and (eq_attr "type" "compare")
311 (eq_attr "cpu" "rios1"))
312 4 1)
314 (define_function_unit "iu" 1 0
315 (and (eq_attr "type" "delayed_compare")
316 (eq_attr "cpu" "rios1"))
317 5 1)
319 (define_function_unit "iu" 1 0
320 (and (eq_attr "type" "compare,delayed_compare")
321 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
322 3 1)
324 (define_function_unit "iu2" 2 0
325 (and (eq_attr "type" "compare,delayed_compare")
326 (eq_attr "cpu" "rios2"))
327 3 1)
329 (define_function_unit "iu2" 2 0
330 (and (eq_attr "type" "compare,delayed_compare")
331 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750"))
332 1 1)
334 ; fp compare uses fp unit
335 (define_function_unit "fpu" 1 0
336 (and (eq_attr "type" "fpcompare")
337 (eq_attr "cpu" "rios1"))
338 9 1)
340 ; rios1 and rios2 have different fpcompare delays
341 (define_function_unit "fpu2" 2 0
342 (and (eq_attr "type" "fpcompare")
343 (eq_attr "cpu" "rios2,ppc630"))
344 5 1)
346 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
347 ; the integer unit
348 ; here we do not define delays, just occupy the unit. The dependencies
349 ; will be assigned by the fpcompare definition in the fpu.
350 (define_function_unit "iu" 1 0
351 (and (eq_attr "type" "fpcompare")
352 (eq_attr "cpu" "ppc601,ppc603"))
353 0 2)
355 ; fp compare uses fp unit
356 (define_function_unit "fpu" 1 0
357 (and (eq_attr "type" "fpcompare")
358 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
359 5 1)
361 (define_function_unit "fpu" 1 0
362 (and (eq_attr "type" "fpcompare")
363 (eq_attr "cpu" "mpccore"))
364 1 1)
366 (define_function_unit "bpu" 1 0
367 (and (eq_attr "type" "mtjmpr")
368 (eq_attr "cpu" "rios1,rios2,rs64a"))
369 5 1)
371 (define_function_unit "bpu" 1 0
372 (and (eq_attr "type" "mtjmpr")
373 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
374 4 1)
376 (define_function_unit "bpu" 1 0
377 (and (eq_attr "type" "cr_logical")
378 (eq_attr "cpu" "rios1,rios2,ppc604"))
379 4 1)
381 (define_function_unit "cru" 1 0
382 (and (eq_attr "type" "cr_logical")
383 (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
384 1 1)
386 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
387 (define_function_unit "bpu" 1 0
388 (eq_attr "type" "jmpreg")
389 1 1)
391 (define_function_unit "bpu" 1 0
392 (eq_attr "type" "branch")
393 1 1)
395 ; Floating Point Unit
396 (define_function_unit "fpu" 1 0
397 (and (eq_attr "type" "fp,dmul")
398 (eq_attr "cpu" "rios1"))
399 2 1)
401 (define_function_unit "fpu" 1 0
402 (and (eq_attr "type" "fp")
403 (eq_attr "cpu" "rs64a,mpccore"))
404 4 2)
406 (define_function_unit "fpu" 1 0
407 (and (eq_attr "type" "fp")
408 (eq_attr "cpu" "ppc601"))
409 4 1)
411 (define_function_unit "fpu" 1 0
412 (and (eq_attr "type" "fp")
413 (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620"))
414 3 1)
416 (define_function_unit "fpu" 1 0
417 (and (eq_attr "type" "dmul")
418 (eq_attr "cpu" "rs64a"))
419 7 2)
421 (define_function_unit "fpu" 1 0
422 (and (eq_attr "type" "dmul")
423 (eq_attr "cpu" "mpccore"))
424 5 5)
426 (define_function_unit "fpu" 1 0
427 (and (eq_attr "type" "dmul")
428 (eq_attr "cpu" "ppc601"))
429 5 2)
431 ; is this true?
432 (define_function_unit "fpu" 1 0
433 (and (eq_attr "type" "dmul")
434 (eq_attr "cpu" "ppc603,ppc750"))
435 4 2)
437 (define_function_unit "fpu" 1 0
438 (and (eq_attr "type" "dmul")
439 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
440 3 1)
442 (define_function_unit "fpu" 1 0
443 (and (eq_attr "type" "sdiv,ddiv")
444 (eq_attr "cpu" "rios1"))
445 19 19)
447 (define_function_unit "fpu" 1 0
448 (and (eq_attr "type" "sdiv")
449 (eq_attr "cpu" "rs64a"))
450 31 31)
452 (define_function_unit "fpu" 1 0
453 (and (eq_attr "type" "sdiv")
454 (eq_attr "cpu" "ppc601"))
455 17 17)
457 (define_function_unit "fpu" 1 0
458 (and (eq_attr "type" "sdiv")
459 (eq_attr "cpu" "mpccore"))
460 10 10)
462 (define_function_unit "fpu" 1 0
463 (and (eq_attr "type" "sdiv")
464 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
465 18 18)
467 (define_function_unit "fpu" 1 0
468 (and (eq_attr "type" "ddiv")
469 (eq_attr "cpu" "mpccore"))
470 17 17)
472 (define_function_unit "fpu" 1 0
473 (and (eq_attr "type" "ddiv")
474 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620"))
475 31 31)
477 (define_function_unit "fpu" 1 0
478 (and (eq_attr "type" "ddiv")
479 (eq_attr "cpu" "ppc603"))
480 33 33)
482 (define_function_unit "fpu" 1 0
483 (and (eq_attr "type" "ssqrt")
484 (eq_attr "cpu" "ppc620"))
485 31 31)
487 (define_function_unit "fpu" 1 0
488 (and (eq_attr "type" "dsqrt")
489 (eq_attr "cpu" "ppc620"))
490 31 31)
492 ; RIOS2 has two symmetric FPUs.
493 (define_function_unit "fpu2" 2 0
494 (and (eq_attr "type" "fp")
495 (eq_attr "cpu" "rios2"))
496 2 1)
498 (define_function_unit "fpu2" 2 0
499 (and (eq_attr "type" "fp")
500 (eq_attr "cpu" "ppc630"))
501 3 1)
503 (define_function_unit "fpu2" 2 0
504 (and (eq_attr "type" "dmul")
505 (eq_attr "cpu" "rios2"))
506 2 1)
508 (define_function_unit "fpu2" 2 0
509 (and (eq_attr "type" "dmul")
510 (eq_attr "cpu" "ppc630"))
511 3 1)
513 (define_function_unit "fpu2" 2 0
514 (and (eq_attr "type" "sdiv,ddiv")
515 (eq_attr "cpu" "rios2"))
516 17 17)
518 (define_function_unit "fpu2" 2 0
519 (and (eq_attr "type" "sdiv")
520 (eq_attr "cpu" "ppc630"))
521 17 17)
523 (define_function_unit "fpu2" 2 0
524 (and (eq_attr "type" "ddiv")
525 (eq_attr "cpu" "ppc630"))
526 21 21)
528 (define_function_unit "fpu2" 2 0
529 (and (eq_attr "type" "ssqrt,dsqrt")
530 (eq_attr "cpu" "rios2"))
531 26 26)
533 (define_function_unit "fpu2" 2 0
534 (and (eq_attr "type" "ssqrt")
535 (eq_attr "cpu" "ppc630"))
536 18 18)
538 (define_function_unit "fpu2" 2 0
539 (and (eq_attr "type" "dsqrt")
540 (eq_attr "cpu" "ppc630"))
541 26 26)
543 \f
544 ;; Start with fixed-point load and store insns. Here we put only the more
545 ;; complex forms. Basic data transfer is done later.
547 (define_expand "zero_extendqidi2"
548 [(set (match_operand:DI 0 "gpc_reg_operand" "")
549 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
550 "TARGET_POWERPC64"
551 "")
553 (define_insn ""
554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
555 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
556 "TARGET_POWERPC64"
557 "@
558 lbz%U1%X1 %0,%1
559 rldicl %0,%1,0,56"
560 [(set_attr "type" "load,*")])
562 (define_insn ""
563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
564 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (clobber (match_scratch:DI 2 "=r,r"))]
567 "TARGET_POWERPC64"
568 "@
569 rldicl. %2,%1,0,56
570 #"
571 [(set_attr "type" "compare")
572 (set_attr "length" "4,8")])
574 (define_split
575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
576 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
577 (const_int 0)))
578 (clobber (match_scratch:DI 2 ""))]
579 "TARGET_POWERPC64 && reload_completed"
580 [(set (match_dup 2)
581 (zero_extend:DI (match_dup 1)))
582 (set (match_dup 0)
583 (compare:CC (match_dup 2)
584 (const_int 0)))]
585 "")
587 (define_insn ""
588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
589 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
590 (const_int 0)))
591 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
592 (zero_extend:DI (match_dup 1)))]
593 "TARGET_POWERPC64"
594 "@
595 rldicl. %0,%1,0,56
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
600 (define_split
601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
602 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (set (match_operand:DI 0 "gpc_reg_operand" "")
605 (zero_extend:DI (match_dup 1)))]
606 "TARGET_POWERPC64 && reload_completed"
607 [(set (match_dup 0)
608 (zero_extend:DI (match_dup 1)))
609 (set (match_dup 2)
610 (compare:CC (match_dup 0)
611 (const_int 0)))]
612 "")
614 (define_insn "extendqidi2"
615 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
616 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
617 "TARGET_POWERPC64"
618 "extsb %0,%1")
620 (define_insn ""
621 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
622 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
623 (const_int 0)))
624 (clobber (match_scratch:DI 2 "=r,r"))]
625 "TARGET_POWERPC64"
626 "@
627 extsb. %2,%1
628 #"
629 [(set_attr "type" "compare")
630 (set_attr "length" "4,8")])
632 (define_split
633 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
634 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
635 (const_int 0)))
636 (clobber (match_scratch:DI 2 ""))]
637 "TARGET_POWERPC64 && reload_completed"
638 [(set (match_dup 2)
639 (sign_extend:DI (match_dup 1)))
640 (set (match_dup 0)
641 (compare:CC (match_dup 2)
642 (const_int 0)))]
643 "")
645 (define_insn ""
646 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
647 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
648 (const_int 0)))
649 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
650 (sign_extend:DI (match_dup 1)))]
651 "TARGET_POWERPC64"
652 "@
653 extsb. %0,%1
654 #"
655 [(set_attr "type" "compare")
656 (set_attr "length" "4,8")])
658 (define_split
659 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
660 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
661 (const_int 0)))
662 (set (match_operand:DI 0 "gpc_reg_operand" "")
663 (sign_extend:DI (match_dup 1)))]
664 "TARGET_POWERPC64 && reload_completed"
665 [(set (match_dup 0)
666 (sign_extend:DI (match_dup 1)))
667 (set (match_dup 2)
668 (compare:CC (match_dup 0)
669 (const_int 0)))]
670 "")
672 (define_expand "zero_extendhidi2"
673 [(set (match_operand:DI 0 "gpc_reg_operand" "")
674 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
675 "TARGET_POWERPC64"
676 "")
678 (define_insn ""
679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
680 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
681 "TARGET_POWERPC64"
682 "@
683 lhz%U1%X1 %0,%1
684 rldicl %0,%1,0,48"
685 [(set_attr "type" "load,*")])
687 (define_insn ""
688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
689 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
690 (const_int 0)))
691 (clobber (match_scratch:DI 2 "=r,r"))]
692 "TARGET_POWERPC64"
693 "@
694 rldicl. %2,%1,0,48
695 #"
696 [(set_attr "type" "compare")
697 (set_attr "length" "4,8")])
699 (define_split
700 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
701 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
702 (const_int 0)))
703 (clobber (match_scratch:DI 2 ""))]
704 "TARGET_POWERPC64 && reload_completed"
705 [(set (match_dup 2)
706 (zero_extend:DI (match_dup 1)))
707 (set (match_dup 0)
708 (compare:CC (match_dup 2)
709 (const_int 0)))]
710 "")
712 (define_insn ""
713 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
714 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
715 (const_int 0)))
716 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
717 (zero_extend:DI (match_dup 1)))]
718 "TARGET_POWERPC64"
719 "@
720 rldicl. %0,%1,0,48
721 #"
722 [(set_attr "type" "compare")
723 (set_attr "length" "4,8")])
725 (define_split
726 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
727 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
728 (const_int 0)))
729 (set (match_operand:DI 0 "gpc_reg_operand" "")
730 (zero_extend:DI (match_dup 1)))]
731 "TARGET_POWERPC64 && reload_completed"
732 [(set (match_dup 0)
733 (zero_extend:DI (match_dup 1)))
734 (set (match_dup 2)
735 (compare:CC (match_dup 0)
736 (const_int 0)))]
737 "")
739 (define_expand "extendhidi2"
740 [(set (match_operand:DI 0 "gpc_reg_operand" "")
741 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
742 "TARGET_POWERPC64"
743 "")
745 (define_insn ""
746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
747 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
748 "TARGET_POWERPC64"
749 "@
750 lha%U1%X1 %0,%1
751 extsh %0,%1"
752 [(set_attr "type" "load,*")])
754 (define_insn ""
755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
756 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
757 (const_int 0)))
758 (clobber (match_scratch:DI 2 "=r,r"))]
759 "TARGET_POWERPC64"
760 "@
761 extsh. %2,%1
762 #"
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
766 (define_split
767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
769 (const_int 0)))
770 (clobber (match_scratch:DI 2 ""))]
771 "TARGET_POWERPC64 && reload_completed"
772 [(set (match_dup 2)
773 (sign_extend:DI (match_dup 1)))
774 (set (match_dup 0)
775 (compare:CC (match_dup 2)
776 (const_int 0)))]
777 "")
779 (define_insn ""
780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
781 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
782 (const_int 0)))
783 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
784 (sign_extend:DI (match_dup 1)))]
785 "TARGET_POWERPC64"
786 "@
787 extsh. %0,%1
788 #"
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
792 (define_split
793 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
794 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
795 (const_int 0)))
796 (set (match_operand:DI 0 "gpc_reg_operand" "")
797 (sign_extend:DI (match_dup 1)))]
798 "TARGET_POWERPC64 && reload_completed"
799 [(set (match_dup 0)
800 (sign_extend:DI (match_dup 1)))
801 (set (match_dup 2)
802 (compare:CC (match_dup 0)
803 (const_int 0)))]
804 "")
806 (define_expand "zero_extendsidi2"
807 [(set (match_operand:DI 0 "gpc_reg_operand" "")
808 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
809 "TARGET_POWERPC64"
810 "")
812 (define_insn ""
813 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
814 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
815 "TARGET_POWERPC64"
816 "@
817 lwz%U1%X1 %0,%1
818 rldicl %0,%1,0,32"
819 [(set_attr "type" "load,*")])
821 (define_insn ""
822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
823 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
824 (const_int 0)))
825 (clobber (match_scratch:DI 2 "=r,r"))]
826 "TARGET_POWERPC64"
827 "@
828 rldicl. %2,%1,0,32
829 #"
830 [(set_attr "type" "compare")
831 (set_attr "length" "4,8")])
833 (define_split
834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
835 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
836 (const_int 0)))
837 (clobber (match_scratch:DI 2 ""))]
838 "TARGET_POWERPC64 && reload_completed"
839 [(set (match_dup 2)
840 (zero_extend:DI (match_dup 1)))
841 (set (match_dup 0)
842 (compare:CC (match_dup 2)
843 (const_int 0)))]
844 "")
846 (define_insn ""
847 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
848 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
849 (const_int 0)))
850 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
851 (zero_extend:DI (match_dup 1)))]
852 "TARGET_POWERPC64"
853 "@
854 rldicl. %0,%1,0,32
855 #"
856 [(set_attr "type" "compare")
857 (set_attr "length" "4,8")])
859 (define_split
860 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
861 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
862 (const_int 0)))
863 (set (match_operand:DI 0 "gpc_reg_operand" "")
864 (zero_extend:DI (match_dup 1)))]
865 "TARGET_POWERPC64 && reload_completed"
866 [(set (match_dup 0)
867 (zero_extend:DI (match_dup 1)))
868 (set (match_dup 2)
869 (compare:CC (match_dup 0)
870 (const_int 0)))]
871 "")
873 (define_expand "extendsidi2"
874 [(set (match_operand:DI 0 "gpc_reg_operand" "")
875 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
876 "TARGET_POWERPC64"
877 "")
879 (define_insn ""
880 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
881 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
882 "TARGET_POWERPC64"
883 "@
884 lwa%U1%X1 %0,%1
885 extsw %0,%1"
886 [(set_attr "type" "load,*")])
888 (define_insn ""
889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
890 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
891 (const_int 0)))
892 (clobber (match_scratch:DI 2 "=r,r"))]
893 "TARGET_POWERPC64"
894 "@
895 extsw. %2,%1
896 #"
897 [(set_attr "type" "compare")
898 (set_attr "length" "4,8")])
900 (define_split
901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
902 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
903 (const_int 0)))
904 (clobber (match_scratch:DI 2 ""))]
905 "TARGET_POWERPC64 && reload_completed"
906 [(set (match_dup 2)
907 (sign_extend:DI (match_dup 1)))
908 (set (match_dup 0)
909 (compare:CC (match_dup 2)
910 (const_int 0)))]
911 "")
913 (define_insn ""
914 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
915 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
916 (const_int 0)))
917 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
918 (sign_extend:DI (match_dup 1)))]
919 "TARGET_POWERPC64"
920 "@
921 extsw. %0,%1
922 #"
923 [(set_attr "type" "compare")
924 (set_attr "length" "4,8")])
926 (define_split
927 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
928 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
929 (const_int 0)))
930 (set (match_operand:DI 0 "gpc_reg_operand" "")
931 (sign_extend:DI (match_dup 1)))]
932 "TARGET_POWERPC64 && reload_completed"
933 [(set (match_dup 0)
934 (sign_extend:DI (match_dup 1)))
935 (set (match_dup 2)
936 (compare:CC (match_dup 0)
937 (const_int 0)))]
938 "")
940 (define_expand "zero_extendqisi2"
941 [(set (match_operand:SI 0 "gpc_reg_operand" "")
942 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
943 ""
944 "")
946 (define_insn ""
947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
949 ""
950 "@
951 lbz%U1%X1 %0,%1
952 {rlinm|rlwinm} %0,%1,0,0xff"
953 [(set_attr "type" "load,*")])
955 (define_insn ""
956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
957 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
958 (const_int 0)))
959 (clobber (match_scratch:SI 2 "=r,r"))]
960 ""
961 "@
962 {andil.|andi.} %2,%1,0xff
963 #"
964 [(set_attr "type" "compare")
965 (set_attr "length" "4,8")])
967 (define_split
968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
969 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
970 (const_int 0)))
971 (clobber (match_scratch:SI 2 ""))]
972 "reload_completed"
973 [(set (match_dup 2)
974 (zero_extend:SI (match_dup 1)))
975 (set (match_dup 0)
976 (compare:CC (match_dup 2)
977 (const_int 0)))]
978 "")
980 (define_insn ""
981 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
982 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
983 (const_int 0)))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
985 (zero_extend:SI (match_dup 1)))]
986 ""
987 "@
988 {andil.|andi.} %0,%1,0xff
989 #"
990 [(set_attr "type" "compare")
991 (set_attr "length" "4,8")])
993 (define_split
994 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
995 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
996 (const_int 0)))
997 (set (match_operand:SI 0 "gpc_reg_operand" "")
998 (zero_extend:SI (match_dup 1)))]
999 "reload_completed"
1000 [(set (match_dup 0)
1001 (zero_extend:SI (match_dup 1)))
1002 (set (match_dup 2)
1003 (compare:CC (match_dup 0)
1004 (const_int 0)))]
1005 "")
1007 (define_expand "extendqisi2"
1008 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1009 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1010 ""
1011 "
1012 {
1013 if (TARGET_POWERPC)
1014 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
1015 else if (TARGET_POWER)
1016 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
1017 else
1018 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
1019 DONE;
1020 }")
1022 (define_insn "extendqisi2_ppc"
1023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1024 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1025 "TARGET_POWERPC"
1026 "extsb %0,%1")
1028 (define_insn ""
1029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1030 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1031 (const_int 0)))
1032 (clobber (match_scratch:SI 2 "=r,r"))]
1033 "TARGET_POWERPC"
1034 "@
1035 extsb. %2,%1
1036 #"
1037 [(set_attr "type" "compare")
1038 (set_attr "length" "4,8")])
1040 (define_split
1041 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1042 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1043 (const_int 0)))
1044 (clobber (match_scratch:SI 2 ""))]
1045 "TARGET_POWERPC && reload_completed"
1046 [(set (match_dup 2)
1047 (sign_extend:SI (match_dup 1)))
1048 (set (match_dup 0)
1049 (compare:CC (match_dup 2)
1050 (const_int 0)))]
1051 "")
1053 (define_insn ""
1054 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1055 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1056 (const_int 0)))
1057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1058 (sign_extend:SI (match_dup 1)))]
1059 "TARGET_POWERPC"
1060 "@
1061 extsb. %0,%1
1062 #"
1063 [(set_attr "type" "compare")
1064 (set_attr "length" "4,8")])
1066 (define_split
1067 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1068 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "")
1071 (sign_extend:SI (match_dup 1)))]
1072 "TARGET_POWERPC && reload_completed"
1073 [(set (match_dup 0)
1074 (sign_extend:SI (match_dup 1)))
1075 (set (match_dup 2)
1076 (compare:CC (match_dup 0)
1077 (const_int 0)))]
1078 "")
1080 (define_expand "extendqisi2_power"
1081 [(parallel [(set (match_dup 2)
1082 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1083 (const_int 24)))
1084 (clobber (scratch:SI))])
1085 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1086 (ashiftrt:SI (match_dup 2)
1087 (const_int 24)))
1088 (clobber (scratch:SI))])]
1089 "TARGET_POWER"
1090 "
1091 { operands[1] = gen_lowpart (SImode, operands[1]);
1092 operands[2] = gen_reg_rtx (SImode); }")
1094 (define_expand "extendqisi2_no_power"
1095 [(set (match_dup 2)
1096 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1097 (const_int 24)))
1098 (set (match_operand:SI 0 "gpc_reg_operand" "")
1099 (ashiftrt:SI (match_dup 2)
1100 (const_int 24)))]
1101 "! TARGET_POWER && ! TARGET_POWERPC"
1102 "
1103 { operands[1] = gen_lowpart (SImode, operands[1]);
1104 operands[2] = gen_reg_rtx (SImode); }")
1106 (define_expand "zero_extendqihi2"
1107 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1108 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1109 ""
1110 "")
1112 (define_insn ""
1113 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1114 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1115 ""
1116 "@
1117 lbz%U1%X1 %0,%1
1118 {rlinm|rlwinm} %0,%1,0,0xff"
1119 [(set_attr "type" "load,*")])
1121 (define_insn ""
1122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1123 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1124 (const_int 0)))
1125 (clobber (match_scratch:HI 2 "=r,r"))]
1126 ""
1127 "@
1128 {andil.|andi.} %2,%1,0xff
1129 #"
1130 [(set_attr "type" "compare")
1131 (set_attr "length" "4,8")])
1133 (define_split
1134 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1135 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1136 (const_int 0)))
1137 (clobber (match_scratch:HI 2 ""))]
1138 "reload_completed"
1139 [(set (match_dup 2)
1140 (zero_extend:HI (match_dup 1)))
1141 (set (match_dup 0)
1142 (compare:CC (match_dup 2)
1143 (const_int 0)))]
1144 "")
1146 (define_insn ""
1147 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1148 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1149 (const_int 0)))
1150 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1151 (zero_extend:HI (match_dup 1)))]
1152 ""
1153 "@
1154 {andil.|andi.} %0,%1,0xff
1155 #"
1156 [(set_attr "type" "compare")
1157 (set_attr "length" "4,8")])
1159 (define_split
1160 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1161 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1162 (const_int 0)))
1163 (set (match_operand:HI 0 "gpc_reg_operand" "")
1164 (zero_extend:HI (match_dup 1)))]
1165 "reload_completed"
1166 [(set (match_dup 0)
1167 (zero_extend:HI (match_dup 1)))
1168 (set (match_dup 2)
1169 (compare:CC (match_dup 0)
1170 (const_int 0)))]
1171 "")
1173 (define_expand "extendqihi2"
1174 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
1175 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1176 ""
1177 "
1178 {
1179 if (TARGET_POWERPC)
1180 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
1181 else if (TARGET_POWER)
1182 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
1183 else
1184 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
1185 DONE;
1186 }")
1188 (define_insn "extendqihi2_ppc"
1189 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1190 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1191 "TARGET_POWERPC"
1192 "extsb %0,%1")
1194 (define_insn ""
1195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1196 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1197 (const_int 0)))
1198 (clobber (match_scratch:HI 2 "=r,r"))]
1199 "TARGET_POWERPC"
1200 "@
1201 extsb. %2,%1
1202 #"
1203 [(set_attr "type" "compare")
1204 (set_attr "length" "4,8")])
1206 (define_split
1207 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1208 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1209 (const_int 0)))
1210 (clobber (match_scratch:HI 2 ""))]
1211 "TARGET_POWERPC && reload_completed"
1212 [(set (match_dup 2)
1213 (sign_extend:HI (match_dup 1)))
1214 (set (match_dup 0)
1215 (compare:CC (match_dup 2)
1216 (const_int 0)))]
1217 "")
1219 (define_insn ""
1220 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1221 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1222 (const_int 0)))
1223 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1224 (sign_extend:HI (match_dup 1)))]
1225 "TARGET_POWERPC"
1226 "@
1227 extsb. %0,%1
1228 #"
1229 [(set_attr "type" "compare")
1230 (set_attr "length" "4,8")])
1232 (define_split
1233 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1234 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1235 (const_int 0)))
1236 (set (match_operand:HI 0 "gpc_reg_operand" "")
1237 (sign_extend:HI (match_dup 1)))]
1238 "TARGET_POWERPC && reload_completed"
1239 [(set (match_dup 0)
1240 (sign_extend:HI (match_dup 1)))
1241 (set (match_dup 2)
1242 (compare:CC (match_dup 0)
1243 (const_int 0)))]
1244 "")
1246 (define_expand "extendqihi2_power"
1247 [(parallel [(set (match_dup 2)
1248 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1249 (const_int 24)))
1250 (clobber (scratch:SI))])
1251 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1252 (ashiftrt:SI (match_dup 2)
1253 (const_int 24)))
1254 (clobber (scratch:SI))])]
1255 "TARGET_POWER"
1256 "
1257 { operands[0] = gen_lowpart (SImode, operands[0]);
1258 operands[1] = gen_lowpart (SImode, operands[1]);
1259 operands[2] = gen_reg_rtx (SImode); }")
1261 (define_expand "extendqihi2_no_power"
1262 [(set (match_dup 2)
1263 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1264 (const_int 24)))
1265 (set (match_operand:HI 0 "gpc_reg_operand" "")
1266 (ashiftrt:SI (match_dup 2)
1267 (const_int 24)))]
1268 "! TARGET_POWER && ! TARGET_POWERPC"
1269 "
1270 { operands[0] = gen_lowpart (SImode, operands[0]);
1271 operands[1] = gen_lowpart (SImode, operands[1]);
1272 operands[2] = gen_reg_rtx (SImode); }")
1274 (define_expand "zero_extendhisi2"
1275 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1276 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1277 ""
1278 "")
1280 (define_insn ""
1281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1282 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1283 ""
1284 "@
1285 lhz%U1%X1 %0,%1
1286 {rlinm|rlwinm} %0,%1,0,0xffff"
1287 [(set_attr "type" "load,*")])
1289 (define_insn ""
1290 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1291 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1292 (const_int 0)))
1293 (clobber (match_scratch:SI 2 "=r,r"))]
1294 ""
1295 "@
1296 {andil.|andi.} %2,%1,0xffff
1297 #"
1298 [(set_attr "type" "compare")
1299 (set_attr "length" "4,8")])
1301 (define_split
1302 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1303 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1304 (const_int 0)))
1305 (clobber (match_scratch:SI 2 ""))]
1306 "reload_completed"
1307 [(set (match_dup 2)
1308 (zero_extend:SI (match_dup 1)))
1309 (set (match_dup 0)
1310 (compare:CC (match_dup 2)
1311 (const_int 0)))]
1312 "")
1314 (define_insn ""
1315 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1316 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1317 (const_int 0)))
1318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1319 (zero_extend:SI (match_dup 1)))]
1320 ""
1321 "@
1322 {andil.|andi.} %0,%1,0xffff
1323 #"
1324 [(set_attr "type" "compare")
1325 (set_attr "length" "4,8")])
1327 (define_split
1328 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1329 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1330 (const_int 0)))
1331 (set (match_operand:SI 0 "gpc_reg_operand" "")
1332 (zero_extend:SI (match_dup 1)))]
1333 "reload_completed"
1334 [(set (match_dup 0)
1335 (zero_extend:SI (match_dup 1)))
1336 (set (match_dup 2)
1337 (compare:CC (match_dup 0)
1338 (const_int 0)))]
1339 "")
1341 (define_expand "extendhisi2"
1342 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1343 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1344 ""
1345 "")
1347 (define_insn ""
1348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1349 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1350 ""
1351 "@
1352 lha%U1%X1 %0,%1
1353 {exts|extsh} %0,%1"
1354 [(set_attr "type" "load,*")])
1356 (define_insn ""
1357 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1358 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1359 (const_int 0)))
1360 (clobber (match_scratch:SI 2 "=r,r"))]
1361 ""
1362 "@
1363 {exts.|extsh.} %2,%1
1364 #"
1365 [(set_attr "type" "compare")
1366 (set_attr "length" "4,8")])
1368 (define_split
1369 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1370 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1371 (const_int 0)))
1372 (clobber (match_scratch:SI 2 ""))]
1373 "reload_completed"
1374 [(set (match_dup 2)
1375 (sign_extend:SI (match_dup 1)))
1376 (set (match_dup 0)
1377 (compare:CC (match_dup 2)
1378 (const_int 0)))]
1379 "")
1381 (define_insn ""
1382 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1383 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1384 (const_int 0)))
1385 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1386 (sign_extend:SI (match_dup 1)))]
1387 ""
1388 "@
1389 {exts.|extsh.} %0,%1
1390 #"
1391 [(set_attr "type" "compare")
1392 (set_attr "length" "4,8")])
1393 \f
1394 (define_split
1395 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1396 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1397 (const_int 0)))
1398 (set (match_operand:SI 0 "gpc_reg_operand" "")
1399 (sign_extend:SI (match_dup 1)))]
1400 "reload_completed"
1401 [(set (match_dup 0)
1402 (sign_extend:SI (match_dup 1)))
1403 (set (match_dup 2)
1404 (compare:CC (match_dup 0)
1405 (const_int 0)))]
1406 "")
1408 ;; Fixed-point arithmetic insns.
1410 ;; Discourage ai/addic because of carry but provide it in an alternative
1411 ;; allowing register zero as source.
1412 (define_expand "addsi3"
1413 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1414 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1415 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1416 ""
1417 "
1418 {
1419 if (GET_CODE (operands[2]) == CONST_INT
1420 && ! add_operand (operands[2], SImode))
1421 {
1422 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1423 ? operands[0] : gen_reg_rtx (SImode));
1425 HOST_WIDE_INT val = INTVAL (operands[2]);
1426 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
1427 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1429 /* The ordering here is important for the prolog expander.
1430 When space is allocated from the stack, adding 'low' first may
1431 produce a temporary deallocation (which would be bad). */
1432 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1433 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1434 DONE;
1435 }
1436 }")
1438 (define_insn "*addsi3_internal1"
1439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1440 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1441 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1442 ""
1443 "@
1444 {cax|add} %0,%1,%2
1445 {cal %0,%2(%1)|addi %0,%1,%2}
1446 {ai|addic} %0,%1,%2
1447 {cau|addis} %0,%1,%v2"
1448 [(set_attr "length" "4,4,4,4")])
1450 (define_insn "addsi3_high"
1451 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1452 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1453 (high:SI (match_operand 2 "" ""))))]
1454 "TARGET_MACHO && !TARGET_64BIT"
1455 "{cau|addis} %0,%1,ha16(%2)"
1456 [(set_attr "length" "4")])
1458 (define_insn "*addsi3_internal2"
1459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1460 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1461 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1462 (const_int 0)))
1463 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1464 "! TARGET_POWERPC64"
1465 "@
1466 {cax.|add.} %3,%1,%2
1467 {ai.|addic.} %3,%1,%2
1468 #
1469 #"
1470 [(set_attr "type" "compare")
1471 (set_attr "length" "4,4,8,8")])
1473 (define_split
1474 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1475 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1476 (match_operand:SI 2 "reg_or_short_operand" ""))
1477 (const_int 0)))
1478 (clobber (match_scratch:SI 3 ""))]
1479 "! TARGET_POWERPC64 && reload_completed"
1480 [(set (match_dup 3)
1481 (plus:SI (match_dup 1)
1482 (match_dup 2)))
1483 (set (match_dup 0)
1484 (compare:CC (match_dup 3)
1485 (const_int 0)))]
1486 "")
1488 (define_insn "*addsi3_internal3"
1489 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1490 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1491 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1492 (const_int 0)))
1493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1494 (plus:SI (match_dup 1)
1495 (match_dup 2)))]
1496 "! TARGET_POWERPC64"
1497 "@
1498 {cax.|add.} %0,%1,%2
1499 {ai.|addic.} %0,%1,%2
1500 #
1501 #"
1502 [(set_attr "type" "compare")
1503 (set_attr "length" "4,4,8,8")])
1505 (define_split
1506 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1507 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1508 (match_operand:SI 2 "reg_or_short_operand" ""))
1509 (const_int 0)))
1510 (set (match_operand:SI 0 "gpc_reg_operand" "")
1511 (plus:SI (match_dup 1) (match_dup 2)))]
1512 "! TARGET_POWERPC64 && reload_completed"
1513 [(set (match_dup 0)
1514 (plus:SI (match_dup 1)
1515 (match_dup 2)))
1516 (set (match_dup 3)
1517 (compare:CC (match_dup 0)
1518 (const_int 0)))]
1519 "")
1521 ;; Split an add that we can't do in one insn into two insns, each of which
1522 ;; does one 16-bit part. This is used by combine. Note that the low-order
1523 ;; add should be last in case the result gets used in an address.
1525 (define_split
1526 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1527 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1528 (match_operand:SI 2 "non_add_cint_operand" "")))]
1529 ""
1530 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1531 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1532 "
1533 {
1534 HOST_WIDE_INT val = INTVAL (operands[2]);
1535 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
1536 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1538 operands[3] = GEN_INT (rest);
1539 operands[4] = GEN_INT (low);
1540 }")
1542 (define_insn "one_cmplsi2"
1543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1544 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1545 ""
1546 "nor %0,%1,%1")
1548 (define_insn ""
1549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1550 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1551 (const_int 0)))
1552 (clobber (match_scratch:SI 2 "=r,r"))]
1553 "! TARGET_POWERPC64"
1554 "@
1555 nor. %2,%1,%1
1556 #"
1557 [(set_attr "type" "compare")
1558 (set_attr "length" "4,8")])
1560 (define_split
1561 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1562 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1563 (const_int 0)))
1564 (clobber (match_scratch:SI 2 ""))]
1565 "! TARGET_POWERPC64 && reload_completed"
1566 [(set (match_dup 2)
1567 (not:SI (match_dup 1)))
1568 (set (match_dup 0)
1569 (compare:CC (match_dup 2)
1570 (const_int 0)))]
1571 "")
1573 (define_insn ""
1574 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1575 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1576 (const_int 0)))
1577 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1578 (not:SI (match_dup 1)))]
1579 "! TARGET_POWERPC64"
1580 "@
1581 nor. %0,%1,%1
1582 #"
1583 [(set_attr "type" "compare")
1584 (set_attr "length" "4,8")])
1586 (define_split
1587 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1588 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1589 (const_int 0)))
1590 (set (match_operand:SI 0 "gpc_reg_operand" "")
1591 (not:SI (match_dup 1)))]
1592 "! TARGET_POWERPC64 && reload_completed"
1593 [(set (match_dup 0)
1594 (not:SI (match_dup 1)))
1595 (set (match_dup 2)
1596 (compare:CC (match_dup 0)
1597 (const_int 0)))]
1598 "")
1600 (define_insn ""
1601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1602 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1603 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1604 "! TARGET_POWERPC"
1605 "{sf%I1|subf%I1c} %0,%2,%1")
1607 (define_insn ""
1608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1609 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1610 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1611 "TARGET_POWERPC"
1612 "@
1613 subf %0,%2,%1
1614 subfic %0,%2,%1")
1616 (define_insn ""
1617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1618 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1619 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1620 (const_int 0)))
1621 (clobber (match_scratch:SI 3 "=r,r"))]
1622 "! TARGET_POWERPC"
1623 "@
1624 {sf.|subfc.} %3,%2,%1
1625 #"
1626 [(set_attr "type" "compare")
1627 (set_attr "length" "4,8")])
1629 (define_insn ""
1630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1631 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1632 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1633 (const_int 0)))
1634 (clobber (match_scratch:SI 3 "=r,r"))]
1635 "TARGET_POWERPC && ! TARGET_POWERPC64"
1636 "@
1637 subf. %3,%2,%1
1638 #"
1639 [(set_attr "type" "compare")
1640 (set_attr "length" "4,8")])
1642 (define_split
1643 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1644 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1645 (match_operand:SI 2 "gpc_reg_operand" ""))
1646 (const_int 0)))
1647 (clobber (match_scratch:SI 3 ""))]
1648 "! TARGET_POWERPC64 && reload_completed"
1649 [(set (match_dup 3)
1650 (minus:SI (match_dup 1)
1651 (match_dup 2)))
1652 (set (match_dup 0)
1653 (compare:CC (match_dup 3)
1654 (const_int 0)))]
1655 "")
1657 (define_insn ""
1658 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1659 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1660 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1661 (const_int 0)))
1662 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1663 (minus:SI (match_dup 1) (match_dup 2)))]
1664 "! TARGET_POWERPC"
1665 "@
1666 {sf.|subfc.} %0,%2,%1
1667 #"
1668 [(set_attr "type" "compare")
1669 (set_attr "length" "4,8")])
1671 (define_insn ""
1672 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1673 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1674 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1675 (const_int 0)))
1676 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1677 (minus:SI (match_dup 1)
1678 (match_dup 2)))]
1679 "TARGET_POWERPC && ! TARGET_POWERPC64"
1680 "@
1681 subf. %0,%2,%1
1682 #"
1683 [(set_attr "type" "compare")
1684 (set_attr "length" "4,8")])
1686 (define_split
1687 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1688 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1689 (match_operand:SI 2 "gpc_reg_operand" ""))
1690 (const_int 0)))
1691 (set (match_operand:SI 0 "gpc_reg_operand" "")
1692 (minus:SI (match_dup 1)
1693 (match_dup 2)))]
1694 "! TARGET_POWERPC64 && reload_completed"
1695 [(set (match_dup 0)
1696 (minus:SI (match_dup 1)
1697 (match_dup 2)))
1698 (set (match_dup 3)
1699 (compare:CC (match_dup 0)
1700 (const_int 0)))]
1701 "")
1703 (define_expand "subsi3"
1704 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1705 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1706 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1707 ""
1708 "
1709 {
1710 if (GET_CODE (operands[2]) == CONST_INT)
1711 {
1712 emit_insn (gen_addsi3 (operands[0], operands[1],
1713 negate_rtx (SImode, operands[2])));
1714 DONE;
1715 }
1716 }")
1718 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1719 ;; instruction and some auxiliary computations. Then we just have a single
1720 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1721 ;; combine.
1723 (define_expand "sminsi3"
1724 [(set (match_dup 3)
1725 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1726 (match_operand:SI 2 "reg_or_short_operand" ""))
1727 (const_int 0)
1728 (minus:SI (match_dup 2) (match_dup 1))))
1729 (set (match_operand:SI 0 "gpc_reg_operand" "")
1730 (minus:SI (match_dup 2) (match_dup 3)))]
1731 "TARGET_POWER"
1732 "
1733 { operands[3] = gen_reg_rtx (SImode); }")
1735 (define_split
1736 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1737 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1738 (match_operand:SI 2 "reg_or_short_operand" "")))
1739 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1740 "TARGET_POWER"
1741 [(set (match_dup 3)
1742 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1743 (const_int 0)
1744 (minus:SI (match_dup 2) (match_dup 1))))
1745 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1746 "")
1748 (define_expand "smaxsi3"
1749 [(set (match_dup 3)
1750 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1751 (match_operand:SI 2 "reg_or_short_operand" ""))
1752 (const_int 0)
1753 (minus:SI (match_dup 2) (match_dup 1))))
1754 (set (match_operand:SI 0 "gpc_reg_operand" "")
1755 (plus:SI (match_dup 3) (match_dup 1)))]
1756 "TARGET_POWER"
1757 "
1758 { operands[3] = gen_reg_rtx (SImode); }")
1760 (define_split
1761 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1762 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1763 (match_operand:SI 2 "reg_or_short_operand" "")))
1764 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1765 "TARGET_POWER"
1766 [(set (match_dup 3)
1767 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1768 (const_int 0)
1769 (minus:SI (match_dup 2) (match_dup 1))))
1770 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1771 "")
1773 (define_expand "uminsi3"
1774 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1775 (match_dup 5)))
1776 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1777 (match_dup 5)))
1778 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1779 (const_int 0)
1780 (minus:SI (match_dup 4) (match_dup 3))))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (minus:SI (match_dup 2) (match_dup 3)))]
1783 "TARGET_POWER"
1784 "
1785 {
1786 operands[3] = gen_reg_rtx (SImode);
1787 operands[4] = gen_reg_rtx (SImode);
1788 operands[5] = GEN_INT (-2147483647 - 1);
1789 }")
1791 (define_expand "umaxsi3"
1792 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1793 (match_dup 5)))
1794 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1795 (match_dup 5)))
1796 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1797 (const_int 0)
1798 (minus:SI (match_dup 4) (match_dup 3))))
1799 (set (match_operand:SI 0 "gpc_reg_operand" "")
1800 (plus:SI (match_dup 3) (match_dup 1)))]
1801 "TARGET_POWER"
1802 "
1803 {
1804 operands[3] = gen_reg_rtx (SImode);
1805 operands[4] = gen_reg_rtx (SImode);
1806 operands[5] = GEN_INT (-2147483647 - 1);
1807 }")
1809 (define_insn ""
1810 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1811 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1812 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1813 (const_int 0)
1814 (minus:SI (match_dup 2) (match_dup 1))))]
1815 "TARGET_POWER"
1816 "doz%I2 %0,%1,%2")
1818 (define_insn ""
1819 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1820 (compare:CC
1821 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1822 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1823 (const_int 0)
1824 (minus:SI (match_dup 2) (match_dup 1)))
1825 (const_int 0)))
1826 (clobber (match_scratch:SI 3 "=r,r"))]
1827 "TARGET_POWER"
1828 "@
1829 doz%I2. %3,%1,%2
1830 #"
1831 [(set_attr "type" "delayed_compare")
1832 (set_attr "length" "4,8")])
1834 (define_split
1835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1836 (compare:CC
1837 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1838 (match_operand:SI 2 "reg_or_short_operand" ""))
1839 (const_int 0)
1840 (minus:SI (match_dup 2) (match_dup 1)))
1841 (const_int 0)))
1842 (clobber (match_scratch:SI 3 ""))]
1843 "TARGET_POWER && reload_completed"
1844 [(set (match_dup 3)
1845 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1846 (const_int 0)
1847 (minus:SI (match_dup 2) (match_dup 1))))
1848 (set (match_dup 0)
1849 (compare:CC (match_dup 3)
1850 (const_int 0)))]
1851 "")
1853 (define_insn ""
1854 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1855 (compare:CC
1856 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1857 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1858 (const_int 0)
1859 (minus:SI (match_dup 2) (match_dup 1)))
1860 (const_int 0)))
1861 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1862 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1863 (const_int 0)
1864 (minus:SI (match_dup 2) (match_dup 1))))]
1865 "TARGET_POWER"
1866 "@
1867 doz%I2. %0,%1,%2
1868 #"
1869 [(set_attr "type" "delayed_compare")
1870 (set_attr "length" "4,8")])
1872 (define_split
1873 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1874 (compare:CC
1875 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "reg_or_short_operand" ""))
1877 (const_int 0)
1878 (minus:SI (match_dup 2) (match_dup 1)))
1879 (const_int 0)))
1880 (set (match_operand:SI 0 "gpc_reg_operand" "")
1881 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1882 (const_int 0)
1883 (minus:SI (match_dup 2) (match_dup 1))))]
1884 "TARGET_POWER && reload_completed"
1885 [(set (match_dup 0)
1886 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1887 (const_int 0)
1888 (minus:SI (match_dup 2) (match_dup 1))))
1889 (set (match_dup 3)
1890 (compare:CC (match_dup 0)
1891 (const_int 0)))]
1892 "")
1894 ;; We don't need abs with condition code because such comparisons should
1895 ;; never be done.
1896 (define_expand "abssi2"
1897 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1898 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1899 ""
1900 "
1901 {
1902 if (! TARGET_POWER)
1903 {
1904 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1905 DONE;
1906 }
1907 }")
1909 (define_insn "abssi2_power"
1910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1911 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1912 "TARGET_POWER"
1913 "abs %0,%1")
1915 (define_insn "abssi2_nopower"
1916 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1917 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1918 (clobber (match_scratch:SI 2 "=&r,&r"))]
1919 "! TARGET_POWER"
1920 "*
1921 {
1922 return (TARGET_POWERPC)
1923 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1924 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1925 }"
1926 [(set_attr "length" "12")])
1928 (define_split
1929 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1930 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
1931 (clobber (match_scratch:SI 2 ""))]
1932 "! TARGET_POWER && reload_completed"
1933 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1934 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1935 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1936 "")
1938 (define_insn "*nabs_power"
1939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1940 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1941 "TARGET_POWER"
1942 "nabs %0,%1")
1944 (define_insn "*nabs_no_power"
1945 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1946 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1947 (clobber (match_scratch:SI 2 "=&r,&r"))]
1948 "! TARGET_POWER"
1949 "*
1950 {
1951 return (TARGET_POWERPC)
1952 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1953 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1954 }"
1955 [(set_attr "length" "12")])
1957 (define_split
1958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1959 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))))
1960 (clobber (match_scratch:SI 2 ""))]
1961 "! TARGET_POWER && reload_completed"
1962 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1963 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1964 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1965 "")
1967 (define_insn "negsi2"
1968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1969 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1970 ""
1971 "neg %0,%1")
1973 (define_insn ""
1974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1975 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1976 (const_int 0)))
1977 (clobber (match_scratch:SI 2 "=r,r"))]
1978 "! TARGET_POWERPC64"
1979 "@
1980 neg. %2,%1
1981 #"
1982 [(set_attr "type" "compare")
1983 (set_attr "length" "4,8")])
1985 (define_split
1986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1987 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1988 (const_int 0)))
1989 (clobber (match_scratch:SI 2 ""))]
1990 "! TARGET_POWERPC64 && reload_completed"
1991 [(set (match_dup 2)
1992 (neg:SI (match_dup 1)))
1993 (set (match_dup 0)
1994 (compare:CC (match_dup 2)
1995 (const_int 0)))]
1996 "")
1998 (define_insn ""
1999 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2000 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2001 (const_int 0)))
2002 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2003 (neg:SI (match_dup 1)))]
2004 "! TARGET_POWERPC64"
2005 "@
2006 neg. %0,%1
2007 #"
2008 [(set_attr "type" "compare")
2009 (set_attr "length" "4,8")])
2011 (define_split
2012 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2013 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2014 (const_int 0)))
2015 (set (match_operand:SI 0 "gpc_reg_operand" "")
2016 (neg:SI (match_dup 1)))]
2017 "! TARGET_POWERPC64 && reload_completed"
2018 [(set (match_dup 0)
2019 (neg:SI (match_dup 1)))
2020 (set (match_dup 2)
2021 (compare:CC (match_dup 0)
2022 (const_int 0)))]
2023 "")
2025 (define_insn "ffssi2"
2026 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
2027 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2028 ""
2029 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
2030 [(set_attr "length" "16")])
2032 (define_expand "mulsi3"
2033 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2034 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2035 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2036 ""
2037 "
2038 {
2039 if (TARGET_POWER)
2040 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2041 else
2042 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2043 DONE;
2044 }")
2046 (define_insn "mulsi3_mq"
2047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2048 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2049 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2050 (clobber (match_scratch:SI 3 "=q,q"))]
2051 "TARGET_POWER"
2052 "@
2053 {muls|mullw} %0,%1,%2
2054 {muli|mulli} %0,%1,%2"
2055 [(set_attr "type" "imul")])
2057 (define_insn "mulsi3_no_mq"
2058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2059 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2060 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2061 "! TARGET_POWER"
2062 "@
2063 {muls|mullw} %0,%1,%2
2064 {muli|mulli} %0,%1,%2"
2065 [(set_attr "type" "imul")])
2067 (define_insn ""
2068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2069 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2070 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2071 (const_int 0)))
2072 (clobber (match_scratch:SI 3 "=r,r"))
2073 (clobber (match_scratch:SI 4 "=q,q"))]
2074 "TARGET_POWER"
2075 "@
2076 {muls.|mullw.} %3,%1,%2
2077 #"
2078 [(set_attr "type" "delayed_compare")
2079 (set_attr "length" "4,8")])
2081 (define_split
2082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2083 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2084 (match_operand:SI 2 "gpc_reg_operand" ""))
2085 (const_int 0)))
2086 (clobber (match_scratch:SI 3 ""))
2087 (clobber (match_scratch:SI 4 ""))]
2088 "TARGET_POWER && reload_completed"
2089 [(parallel [(set (match_dup 3)
2090 (mult:SI (match_dup 1) (match_dup 2)))
2091 (clobber (match_dup 4))])
2092 (set (match_dup 0)
2093 (compare:CC (match_dup 3)
2094 (const_int 0)))]
2095 "")
2097 (define_insn ""
2098 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2099 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2100 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2101 (const_int 0)))
2102 (clobber (match_scratch:SI 3 "=r,r"))]
2103 "! TARGET_POWER"
2104 "@
2105 {muls.|mullw.} %3,%1,%2
2106 #"
2107 [(set_attr "type" "delayed_compare")
2108 (set_attr "length" "4,8")])
2110 (define_split
2111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2112 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2113 (match_operand:SI 2 "gpc_reg_operand" ""))
2114 (const_int 0)))
2115 (clobber (match_scratch:SI 3 ""))]
2116 "! TARGET_POWER && reload_completed"
2117 [(set (match_dup 3)
2118 (mult:SI (match_dup 1) (match_dup 2)))
2119 (set (match_dup 0)
2120 (compare:CC (match_dup 3)
2121 (const_int 0)))]
2122 "")
2124 (define_insn ""
2125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2126 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2127 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2128 (const_int 0)))
2129 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2130 (mult:SI (match_dup 1) (match_dup 2)))
2131 (clobber (match_scratch:SI 4 "=q,q"))]
2132 "TARGET_POWER"
2133 "@
2134 {muls.|mullw.} %0,%1,%2
2135 #"
2136 [(set_attr "type" "delayed_compare")
2137 (set_attr "length" "4,8")])
2139 (define_split
2140 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2141 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2142 (match_operand:SI 2 "gpc_reg_operand" ""))
2143 (const_int 0)))
2144 (set (match_operand:SI 0 "gpc_reg_operand" "")
2145 (mult:SI (match_dup 1) (match_dup 2)))
2146 (clobber (match_scratch:SI 4 ""))]
2147 "TARGET_POWER && reload_completed"
2148 [(parallel [(set (match_dup 0)
2149 (mult:SI (match_dup 1) (match_dup 2)))
2150 (clobber (match_dup 4))])
2151 (set (match_dup 3)
2152 (compare:CC (match_dup 0)
2153 (const_int 0)))]
2154 "")
2156 (define_insn ""
2157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2158 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2159 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2160 (const_int 0)))
2161 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2162 (mult:SI (match_dup 1) (match_dup 2)))]
2163 "! TARGET_POWER"
2164 "@
2165 {muls.|mullw.} %0,%1,%2
2166 #"
2167 [(set_attr "type" "delayed_compare")
2168 (set_attr "length" "4,8")])
2170 (define_split
2171 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2172 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2173 (match_operand:SI 2 "gpc_reg_operand" ""))
2174 (const_int 0)))
2175 (set (match_operand:SI 0 "gpc_reg_operand" "")
2176 (mult:SI (match_dup 1) (match_dup 2)))]
2177 "! TARGET_POWER && reload_completed"
2178 [(set (match_dup 0)
2179 (mult:SI (match_dup 1) (match_dup 2)))
2180 (set (match_dup 3)
2181 (compare:CC (match_dup 0)
2182 (const_int 0)))]
2183 "")
2185 ;; Operand 1 is divided by operand 2; quotient goes to operand
2186 ;; 0 and remainder to operand 3.
2187 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2189 (define_expand "divmodsi4"
2190 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2191 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2192 (match_operand:SI 2 "gpc_reg_operand" "")))
2193 (set (match_operand:SI 3 "gpc_reg_operand" "")
2194 (mod:SI (match_dup 1) (match_dup 2)))])]
2195 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2196 "
2197 {
2198 if (! TARGET_POWER && ! TARGET_POWERPC)
2199 {
2200 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2201 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2202 emit_insn (gen_divss_call ());
2203 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2204 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2205 DONE;
2206 }
2207 }")
2209 (define_insn ""
2210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2211 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2212 (match_operand:SI 2 "gpc_reg_operand" "r")))
2213 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
2214 (mod:SI (match_dup 1) (match_dup 2)))]
2215 "TARGET_POWER"
2216 "divs %0,%1,%2"
2217 [(set_attr "type" "idiv")])
2219 (define_expand "udivsi3"
2220 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2221 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2222 (match_operand:SI 2 "gpc_reg_operand" "")))]
2223 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2224 "
2225 {
2226 if (! TARGET_POWER && ! TARGET_POWERPC)
2227 {
2228 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2229 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2230 emit_insn (gen_quous_call ());
2231 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2232 DONE;
2233 }
2234 else if (TARGET_POWER)
2235 {
2236 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2237 DONE;
2238 }
2239 }")
2241 (define_insn "udivsi3_mq"
2242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2243 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2244 (match_operand:SI 2 "gpc_reg_operand" "r")))
2245 (clobber (match_scratch:SI 3 "=q"))]
2246 "TARGET_POWERPC && TARGET_POWER"
2247 "divwu %0,%1,%2"
2248 [(set_attr "type" "idiv")])
2250 (define_insn "*udivsi3_no_mq"
2251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2252 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2253 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2254 "TARGET_POWERPC && ! TARGET_POWER"
2255 "divwu %0,%1,%2"
2256 [(set_attr "type" "idiv")])
2258 ;; For powers of two we can do srai/aze for divide and then adjust for
2259 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2260 ;; used; for PowerPC, force operands into register and do a normal divide;
2261 ;; for AIX common-mode, use quoss call on register operands.
2262 (define_expand "divsi3"
2263 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2264 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2266 ""
2267 "
2268 {
2269 if (GET_CODE (operands[2]) == CONST_INT
2270 && INTVAL (operands[2]) > 0
2271 && exact_log2 (INTVAL (operands[2])) >= 0)
2272 ;
2273 else if (TARGET_POWERPC)
2274 {
2275 operands[2] = force_reg (SImode, operands[2]);
2276 if (TARGET_POWER)
2277 {
2278 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2279 DONE;
2280 }
2281 }
2282 else if (TARGET_POWER)
2283 FAIL;
2284 else
2285 {
2286 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2287 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2288 emit_insn (gen_quoss_call ());
2289 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2290 DONE;
2291 }
2292 }")
2294 (define_insn "divsi3_mq"
2295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2296 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2297 (match_operand:SI 2 "gpc_reg_operand" "r")))
2298 (clobber (match_scratch:SI 3 "=q"))]
2299 "TARGET_POWERPC && TARGET_POWER"
2300 "divw %0,%1,%2"
2301 [(set_attr "type" "idiv")])
2303 (define_insn "*divsi3_no_mq"
2304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2305 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2306 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2307 "TARGET_POWERPC && ! TARGET_POWER"
2308 "divw %0,%1,%2"
2309 [(set_attr "type" "idiv")])
2311 (define_expand "modsi3"
2312 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2313 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2314 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2315 ""
2316 "
2317 {
2318 int i;
2319 rtx temp1;
2320 rtx temp2;
2322 if (GET_CODE (operands[2]) != CONST_INT
2323 || INTVAL (operands[2]) < 0
2324 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2325 FAIL;
2327 temp1 = gen_reg_rtx (SImode);
2328 temp2 = gen_reg_rtx (SImode);
2330 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2331 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2332 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2333 DONE;
2334 }")
2336 (define_insn ""
2337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2338 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2339 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2340 ""
2341 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2342 [(set_attr "length" "8")])
2344 (define_insn ""
2345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2346 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2347 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2348 (const_int 0)))
2349 (clobber (match_scratch:SI 3 "=r,r"))]
2350 ""
2351 "@
2352 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2353 #"
2354 [(set_attr "type" "compare")
2355 (set_attr "length" "8,12")])
2357 (define_split
2358 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2359 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2360 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2361 (const_int 0)))
2362 (clobber (match_scratch:SI 3 ""))]
2363 "reload_completed"
2364 [(set (match_dup 3)
2365 (div:SI (match_dup 1) (match_dup 2)))
2366 (set (match_dup 0)
2367 (compare:CC (match_dup 3)
2368 (const_int 0)))]
2369 "")
2371 (define_insn ""
2372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2373 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2374 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2375 (const_int 0)))
2376 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2377 (div:SI (match_dup 1) (match_dup 2)))]
2378 ""
2379 "@
2380 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2381 #"
2382 [(set_attr "type" "compare")
2383 (set_attr "length" "8,12")])
2385 (define_split
2386 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2387 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2388 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2389 (const_int 0)))
2390 (set (match_operand:SI 0 "gpc_reg_operand" "")
2391 (div:SI (match_dup 1) (match_dup 2)))]
2392 "reload_completed"
2393 [(set (match_dup 0)
2394 (div:SI (match_dup 1) (match_dup 2)))
2395 (set (match_dup 3)
2396 (compare:CC (match_dup 0)
2397 (const_int 0)))]
2398 "")
2400 (define_insn ""
2401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2402 (udiv:SI
2403 (plus:DI (ashift:DI
2404 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2405 (const_int 32))
2406 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2407 (match_operand:SI 3 "gpc_reg_operand" "r")))
2408 (set (match_operand:SI 2 "register_operand" "=*q")
2409 (umod:SI
2410 (plus:DI (ashift:DI
2411 (zero_extend:DI (match_dup 1)) (const_int 32))
2412 (zero_extend:DI (match_dup 4)))
2413 (match_dup 3)))]
2414 "TARGET_POWER"
2415 "div %0,%1,%3"
2416 [(set_attr "type" "idiv")])
2418 ;; To do unsigned divide we handle the cases of the divisor looking like a
2419 ;; negative number. If it is a constant that is less than 2**31, we don't
2420 ;; have to worry about the branches. So make a few subroutines here.
2421 ;;
2422 ;; First comes the normal case.
2423 (define_expand "udivmodsi4_normal"
2424 [(set (match_dup 4) (const_int 0))
2425 (parallel [(set (match_operand:SI 0 "" "")
2426 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2427 (const_int 32))
2428 (zero_extend:DI (match_operand:SI 1 "" "")))
2429 (match_operand:SI 2 "" "")))
2430 (set (match_operand:SI 3 "" "")
2431 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2432 (const_int 32))
2433 (zero_extend:DI (match_dup 1)))
2434 (match_dup 2)))])]
2435 "TARGET_POWER"
2436 "
2437 { operands[4] = gen_reg_rtx (SImode); }")
2439 ;; This handles the branches.
2440 (define_expand "udivmodsi4_tests"
2441 [(set (match_operand:SI 0 "" "") (const_int 0))
2442 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2443 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2444 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2445 (label_ref (match_operand:SI 4 "" "")) (pc)))
2446 (set (match_dup 0) (const_int 1))
2447 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2448 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2449 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2450 (label_ref (match_dup 4)) (pc)))]
2451 "TARGET_POWER"
2452 "
2453 { operands[5] = gen_reg_rtx (CCUNSmode);
2454 operands[6] = gen_reg_rtx (CCmode);
2455 }")
2457 (define_expand "udivmodsi4"
2458 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2459 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2460 (match_operand:SI 2 "reg_or_cint_operand" "")))
2461 (set (match_operand:SI 3 "gpc_reg_operand" "")
2462 (umod:SI (match_dup 1) (match_dup 2)))])]
2463 ""
2464 "
2465 {
2466 rtx label = 0;
2468 if (! TARGET_POWER)
2469 {
2470 if (! TARGET_POWERPC)
2471 {
2472 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2473 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2474 emit_insn (gen_divus_call ());
2475 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2476 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2477 DONE;
2478 }
2479 else
2480 FAIL;
2481 }
2483 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2484 {
2485 operands[2] = force_reg (SImode, operands[2]);
2486 label = gen_label_rtx ();
2487 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2488 operands[3], label));
2489 }
2490 else
2491 operands[2] = force_reg (SImode, operands[2]);
2493 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2494 operands[3]));
2495 if (label)
2496 emit_label (label);
2498 DONE;
2499 }")
2501 ;; AIX architecture-independent common-mode multiply (DImode),
2502 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2503 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2504 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2505 ;; assumed unused if generating common-mode, so ignore.
2506 (define_insn "mulh_call"
2507 [(set (reg:SI 3)
2508 (truncate:SI
2509 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2510 (sign_extend:DI (reg:SI 4)))
2511 (const_int 32))))
2512 (clobber (match_scratch:SI 0 "=l"))]
2513 "! TARGET_POWER && ! TARGET_POWERPC"
2514 "bla __mulh"
2515 [(set_attr "type" "imul")])
2517 (define_insn "mull_call"
2518 [(set (reg:DI 3)
2519 (mult:DI (sign_extend:DI (reg:SI 3))
2520 (sign_extend:DI (reg:SI 4))))
2521 (clobber (match_scratch:SI 0 "=l"))
2522 (clobber (reg:SI 0))]
2523 "! TARGET_POWER && ! TARGET_POWERPC"
2524 "bla __mull"
2525 [(set_attr "type" "imul")])
2527 (define_insn "divss_call"
2528 [(set (reg:SI 3)
2529 (div:SI (reg:SI 3) (reg:SI 4)))
2530 (set (reg:SI 4)
2531 (mod:SI (reg:SI 3) (reg:SI 4)))
2532 (clobber (match_scratch:SI 0 "=l"))
2533 (clobber (reg:SI 0))]
2534 "! TARGET_POWER && ! TARGET_POWERPC"
2535 "bla __divss"
2536 [(set_attr "type" "idiv")])
2538 (define_insn "divus_call"
2539 [(set (reg:SI 3)
2540 (udiv:SI (reg:SI 3) (reg:SI 4)))
2541 (set (reg:SI 4)
2542 (umod:SI (reg:SI 3) (reg:SI 4)))
2543 (clobber (match_scratch:SI 0 "=l"))
2544 (clobber (reg:SI 0))
2545 (clobber (match_scratch:CC 1 "=x"))
2546 (clobber (reg:CC 69))]
2547 "! TARGET_POWER && ! TARGET_POWERPC"
2548 "bla __divus"
2549 [(set_attr "type" "idiv")])
2551 (define_insn "quoss_call"
2552 [(set (reg:SI 3)
2553 (div:SI (reg:SI 3) (reg:SI 4)))
2554 (clobber (match_scratch:SI 0 "=l"))]
2555 "! TARGET_POWER && ! TARGET_POWERPC"
2556 "bla __quoss"
2557 [(set_attr "type" "idiv")])
2559 (define_insn "quous_call"
2560 [(set (reg:SI 3)
2561 (udiv:SI (reg:SI 3) (reg:SI 4)))
2562 (clobber (match_scratch:SI 0 "=l"))
2563 (clobber (reg:SI 0))
2564 (clobber (match_scratch:CC 1 "=x"))
2565 (clobber (reg:CC 69))]
2566 "! TARGET_POWER && ! TARGET_POWERPC"
2567 "bla __quous"
2568 [(set_attr "type" "idiv")])
2569 \f
2570 ;; Logical instructions
2571 ;; The logical instructions are mostly combined by using match_operator,
2572 ;; but the plain AND insns are somewhat different because there is no
2573 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2574 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2576 (define_insn "andsi3"
2577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2578 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2579 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2580 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2581 ""
2582 "@
2583 and %0,%1,%2
2584 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2585 {andil.|andi.} %0,%1,%b2
2586 {andiu.|andis.} %0,%1,%u2")
2588 ;; Note to set cr's other than cr0 we do the and immediate and then
2589 ;; the test again -- this avoids a mcrf which on the higher end
2590 ;; machines causes an execution serialization
2592 (define_insn "*andsi3_internal2"
2593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2594 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2595 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2596 (const_int 0)))
2597 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2598 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2599 "! TARGET_POWERPC64"
2600 "@
2601 and. %3,%1,%2
2602 {andil.|andi.} %3,%1,%b2
2603 {andiu.|andis.} %3,%1,%u2
2604 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2605 #
2606 #
2607 #
2608 #"
2609 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2610 (set_attr "length" "4,4,4,4,8,8,8,8")])
2612 (define_split
2613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2614 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2615 (match_operand:SI 2 "and_operand" ""))
2616 (const_int 0)))
2617 (clobber (match_scratch:SI 3 ""))
2618 (clobber (match_scratch:CC 4 ""))]
2619 "! TARGET_POWERPC64 && reload_completed"
2620 [(parallel [(set (match_dup 3)
2621 (and:SI (match_dup 1)
2622 (match_dup 2)))
2623 (clobber (match_dup 4))])
2624 (set (match_dup 0)
2625 (compare:CC (match_dup 3)
2626 (const_int 0)))]
2627 "")
2629 (define_insn "*andsi3_internal3"
2630 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2631 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2632 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2633 (const_int 0)))
2634 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2635 (and:SI (match_dup 1)
2636 (match_dup 2)))
2637 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2638 "! TARGET_POWERPC64"
2639 "@
2640 and. %0,%1,%2
2641 {andil.|andi.} %0,%1,%b2
2642 {andiu.|andis.} %0,%1,%u2
2643 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2644 #
2645 #
2646 #
2647 #"
2648 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2649 (set_attr "length" "4,4,4,4,8,8,8,8")])
2651 (define_split
2652 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2653 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2654 (match_operand:SI 2 "and_operand" ""))
2655 (const_int 0)))
2656 (set (match_operand:SI 0 "gpc_reg_operand" "")
2657 (and:SI (match_dup 1)
2658 (match_dup 2)))
2659 (clobber (match_scratch:CC 4 ""))]
2660 "! TARGET_POWERPC64 && reload_completed"
2661 [(parallel [(set (match_dup 0)
2662 (and:SI (match_dup 1)
2663 (match_dup 2)))
2664 (clobber (match_dup 4))])
2665 (set (match_dup 3)
2666 (compare:CC (match_dup 0)
2667 (const_int 0)))]
2668 "")
2670 (define_expand "iorsi3"
2671 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2672 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2673 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2674 ""
2675 "
2676 {
2677 if (GET_CODE (operands[2]) == CONST_INT
2678 && ! logical_operand (operands[2], SImode))
2679 {
2680 HOST_WIDE_INT value = INTVAL (operands[2]);
2681 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2682 ? operands[0] : gen_reg_rtx (SImode));
2684 emit_insn (gen_iorsi3 (tmp, operands[1],
2685 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2686 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2687 DONE;
2688 }
2689 }")
2691 (define_expand "xorsi3"
2692 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2693 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2694 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2695 ""
2696 "
2697 {
2698 if (GET_CODE (operands[2]) == CONST_INT
2699 && ! logical_operand (operands[2], SImode))
2700 {
2701 HOST_WIDE_INT value = INTVAL (operands[2]);
2702 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2703 ? operands[0] : gen_reg_rtx (SImode));
2705 emit_insn (gen_xorsi3 (tmp, operands[1],
2706 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2707 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2708 DONE;
2709 }
2710 }")
2712 (define_insn "*boolsi3_internal1"
2713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2714 (match_operator:SI 3 "boolean_or_operator"
2715 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2716 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2717 ""
2718 "@
2719 %q3 %0,%1,%2
2720 {%q3il|%q3i} %0,%1,%b2
2721 {%q3iu|%q3is} %0,%1,%u2")
2723 (define_insn "*boolsi3_internal2"
2724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2725 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2726 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2727 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2728 (const_int 0)))
2729 (clobber (match_scratch:SI 3 "=r,r"))]
2730 "! TARGET_POWERPC64"
2731 "@
2732 %q4. %3,%1,%2
2733 #"
2734 [(set_attr "type" "compare")
2735 (set_attr "length" "4,8")])
2737 (define_split
2738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2739 (compare:CC (match_operator:SI 4 "boolean_operator"
2740 [(match_operand:SI 1 "gpc_reg_operand" "")
2741 (match_operand:SI 2 "gpc_reg_operand" "")])
2742 (const_int 0)))
2743 (clobber (match_scratch:SI 3 ""))]
2744 "! TARGET_POWERPC64 && reload_completed"
2745 [(set (match_dup 3) (match_dup 4))
2746 (set (match_dup 0)
2747 (compare:CC (match_dup 3)
2748 (const_int 0)))]
2749 "")
2751 (define_insn "*boolsi3_internal3"
2752 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2753 (compare:CC (match_operator:SI 4 "boolean_operator"
2754 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2755 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2756 (const_int 0)))
2757 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2758 (match_dup 4))]
2759 "! TARGET_POWERPC64"
2760 "@
2761 %q4. %0,%1,%2
2762 #"
2763 [(set_attr "type" "compare")
2764 (set_attr "length" "4,8")])
2766 (define_split
2767 [(set (match_operand:CC 3 "cc_reg_operand" "")
2768 (compare:CC (match_operator:SI 4 "boolean_operator"
2769 [(match_operand:SI 1 "gpc_reg_operand" "")
2770 (match_operand:SI 2 "gpc_reg_operand" "")])
2771 (const_int 0)))
2772 (set (match_operand:SI 0 "gpc_reg_operand" "")
2773 (match_dup 4))]
2774 "! TARGET_POWERPC64 && reload_completed"
2775 [(set (match_dup 0) (match_dup 4))
2776 (set (match_dup 3)
2777 (compare:CC (match_dup 0)
2778 (const_int 0)))]
2779 "")
2781 ;; Split an logical operation that we can't do in one insn into two insns,
2782 ;; each of which does one 16-bit part. This is used by combine.
2784 (define_split
2785 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2786 (match_operator:SI 3 "boolean_or_operator"
2787 [(match_operand:SI 1 "gpc_reg_operand" "")
2788 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2789 ""
2790 [(set (match_dup 0) (match_dup 4))
2791 (set (match_dup 0) (match_dup 5))]
2792 "
2793 {
2794 rtx i;
2795 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2796 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2797 operands[1], i);
2798 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2799 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2800 operands[0], i);
2801 }")
2803 (define_insn "*boolcsi3_internal1"
2804 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2805 (match_operator:SI 3 "boolean_operator"
2806 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2807 (match_operand:SI 2 "logical_operand" "r")]))]
2808 ""
2809 "%q3 %0,%2,%1")
2811 (define_insn "*boolcsi3_internal2"
2812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2813 (compare:CC (match_operator:SI 4 "boolean_operator"
2814 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2815 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2816 (const_int 0)))
2817 (clobber (match_scratch:SI 3 "=r,r"))]
2818 "! TARGET_POWERPC64"
2819 "@
2820 %q4. %3,%2,%1
2821 #"
2822 [(set_attr "type" "compare")
2823 (set_attr "length" "4,8")])
2825 (define_split
2826 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2827 (compare:CC (match_operator:SI 4 "boolean_operator"
2828 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2829 (match_operand:SI 2 "gpc_reg_operand" "")])
2830 (const_int 0)))
2831 (clobber (match_scratch:SI 3 ""))]
2832 "! TARGET_POWERPC64 && reload_completed"
2833 [(set (match_dup 3) (match_dup 4))
2834 (set (match_dup 0)
2835 (compare:CC (match_dup 3)
2836 (const_int 0)))]
2837 "")
2839 (define_insn "*boolcsi3_internal3"
2840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2841 (compare:CC (match_operator:SI 4 "boolean_operator"
2842 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2843 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2844 (const_int 0)))
2845 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2846 (match_dup 4))]
2847 "! TARGET_POWERPC64"
2848 "@
2849 %q4. %0,%2,%1
2850 #"
2851 [(set_attr "type" "compare")
2852 (set_attr "length" "4,8")])
2854 (define_split
2855 [(set (match_operand:CC 3 "cc_reg_operand" "")
2856 (compare:CC (match_operator:SI 4 "boolean_operator"
2857 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2858 (match_operand:SI 2 "gpc_reg_operand" "")])
2859 (const_int 0)))
2860 (set (match_operand:SI 0 "gpc_reg_operand" "")
2861 (match_dup 4))]
2862 "! TARGET_POWERPC64 && reload_completed"
2863 [(set (match_dup 0) (match_dup 4))
2864 (set (match_dup 3)
2865 (compare:CC (match_dup 0)
2866 (const_int 0)))]
2867 "")
2869 (define_insn "*boolccsi3_internal1"
2870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2871 (match_operator:SI 3 "boolean_operator"
2872 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2873 (not:SI (match_operand:SI 2 "logical_operand" "r"))]))]
2874 ""
2875 "%q3 %0,%1,%2")
2877 (define_insn "*boolccsi3_internal2"
2878 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2879 (compare:CC (match_operator:SI 4 "boolean_operator"
2880 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2881 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2882 (const_int 0)))
2883 (clobber (match_scratch:SI 3 "=r,r"))]
2884 "! TARGET_POWERPC64"
2885 "@
2886 %q4. %3,%1,%2
2887 #"
2888 [(set_attr "type" "compare")
2889 (set_attr "length" "4,8")])
2891 (define_split
2892 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2893 (compare:CC (match_operator:SI 4 "boolean_operator"
2894 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2895 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2896 (const_int 0)))
2897 (clobber (match_scratch:SI 3 ""))]
2898 "! TARGET_POWERPC64 && reload_completed"
2899 [(set (match_dup 3) (match_dup 4))
2900 (set (match_dup 0)
2901 (compare:CC (match_dup 3)
2902 (const_int 0)))]
2903 "")
2905 (define_insn "*boolccsi3_internal3"
2906 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2907 (compare:CC (match_operator:SI 4 "boolean_operator"
2908 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2909 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2910 (const_int 0)))
2911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2912 (match_dup 4))]
2913 "! TARGET_POWERPC64"
2914 "@
2915 %q4. %0,%1,%2
2916 #"
2917 [(set_attr "type" "compare")
2918 (set_attr "length" "4,8")])
2920 (define_split
2921 [(set (match_operand:CC 3 "cc_reg_operand" "")
2922 (compare:CC (match_operator:SI 4 "boolean_operator"
2923 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2924 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2925 (const_int 0)))
2926 (set (match_operand:SI 0 "gpc_reg_operand" "")
2927 (match_dup 4))]
2928 "! TARGET_POWERPC64 && reload_completed"
2929 [(set (match_dup 0) (match_dup 4))
2930 (set (match_dup 3)
2931 (compare:CC (match_dup 0)
2932 (const_int 0)))]
2933 "")
2935 ;; maskir insn. We need four forms because things might be in arbitrary
2936 ;; orders. Don't define forms that only set CR fields because these
2937 ;; would modify an input register.
2939 (define_insn "*maskir_internal1"
2940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2941 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2942 (match_operand:SI 1 "gpc_reg_operand" "0"))
2943 (and:SI (match_dup 2)
2944 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2945 "TARGET_POWER"
2946 "maskir %0,%3,%2")
2948 (define_insn "*maskir_internal2"
2949 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2950 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2951 (match_operand:SI 1 "gpc_reg_operand" "0"))
2952 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2953 (match_dup 2))))]
2954 "TARGET_POWER"
2955 "maskir %0,%3,%2")
2957 (define_insn "*maskir_internal3"
2958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2959 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2960 (match_operand:SI 3 "gpc_reg_operand" "r"))
2961 (and:SI (not:SI (match_dup 2))
2962 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2963 "TARGET_POWER"
2964 "maskir %0,%3,%2")
2966 (define_insn "*maskir_internal4"
2967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2968 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2969 (match_operand:SI 2 "gpc_reg_operand" "r"))
2970 (and:SI (not:SI (match_dup 2))
2971 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2972 "TARGET_POWER"
2973 "maskir %0,%3,%2")
2975 (define_insn "*maskir_internal5"
2976 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2977 (compare:CC
2978 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2979 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2980 (and:SI (match_dup 2)
2981 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2982 (const_int 0)))
2983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2984 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2985 (and:SI (match_dup 2) (match_dup 3))))]
2986 "TARGET_POWER"
2987 "@
2988 maskir. %0,%3,%2
2989 #"
2990 [(set_attr "type" "compare")
2991 (set_attr "length" "4,8")])
2993 (define_split
2994 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2995 (compare:CC
2996 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2997 (match_operand:SI 1 "gpc_reg_operand" ""))
2998 (and:SI (match_dup 2)
2999 (match_operand:SI 3 "gpc_reg_operand" "")))
3000 (const_int 0)))
3001 (set (match_operand:SI 0 "gpc_reg_operand" "")
3002 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3003 (and:SI (match_dup 2) (match_dup 3))))]
3004 "TARGET_POWER && reload_completed"
3005 [(set (match_dup 0)
3006 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3007 (and:SI (match_dup 2) (match_dup 3))))
3008 (set (match_dup 4)
3009 (compare:CC (match_dup 0)
3010 (const_int 0)))]
3011 "")
3013 (define_insn "*maskir_internal6"
3014 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3015 (compare:CC
3016 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3017 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3018 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3019 (match_dup 2)))
3020 (const_int 0)))
3021 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3022 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3023 (and:SI (match_dup 3) (match_dup 2))))]
3024 "TARGET_POWER"
3025 "@
3026 maskir. %0,%3,%2
3027 #"
3028 [(set_attr "type" "compare")
3029 (set_attr "length" "4,8")])
3031 (define_split
3032 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3033 (compare:CC
3034 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3035 (match_operand:SI 1 "gpc_reg_operand" ""))
3036 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3037 (match_dup 2)))
3038 (const_int 0)))
3039 (set (match_operand:SI 0 "gpc_reg_operand" "")
3040 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3041 (and:SI (match_dup 3) (match_dup 2))))]
3042 "TARGET_POWER && reload_completed"
3043 [(set (match_dup 0)
3044 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3045 (and:SI (match_dup 3) (match_dup 2))))
3046 (set (match_dup 4)
3047 (compare:CC (match_dup 0)
3048 (const_int 0)))]
3049 "")
3051 (define_insn "*maskir_internal7"
3052 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3053 (compare:CC
3054 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3055 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3056 (and:SI (not:SI (match_dup 2))
3057 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3058 (const_int 0)))
3059 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3060 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3061 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3062 "TARGET_POWER"
3063 "@
3064 maskir. %0,%3,%2
3065 #"
3066 [(set_attr "type" "compare")
3067 (set_attr "length" "4,8")])
3069 (define_split
3070 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3071 (compare:CC
3072 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3073 (match_operand:SI 3 "gpc_reg_operand" ""))
3074 (and:SI (not:SI (match_dup 2))
3075 (match_operand:SI 1 "gpc_reg_operand" "")))
3076 (const_int 0)))
3077 (set (match_operand:SI 0 "gpc_reg_operand" "")
3078 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3079 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3080 "TARGET_POWER && reload_completed"
3081 [(set (match_dup 0)
3082 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3083 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3084 (set (match_dup 4)
3085 (compare:CC (match_dup 0)
3086 (const_int 0)))]
3087 "")
3089 (define_insn "*maskir_internal8"
3090 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3091 (compare:CC
3092 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3093 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3094 (and:SI (not:SI (match_dup 2))
3095 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3096 (const_int 0)))
3097 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3098 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3099 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3100 "TARGET_POWER"
3101 "@
3102 maskir. %0,%3,%2
3103 #"
3104 [(set_attr "type" "compare")
3105 (set_attr "length" "4,8")])
3106 \f
3107 (define_split
3108 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3109 (compare:CC
3110 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3111 (match_operand:SI 2 "gpc_reg_operand" ""))
3112 (and:SI (not:SI (match_dup 2))
3113 (match_operand:SI 1 "gpc_reg_operand" "")))
3114 (const_int 0)))
3115 (set (match_operand:SI 0 "gpc_reg_operand" "")
3116 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3117 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3118 "TARGET_POWER && reload_completed"
3119 [(set (match_dup 0)
3120 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3121 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3122 (set (match_dup 4)
3123 (compare:CC (match_dup 0)
3124 (const_int 0)))]
3125 "")
3127 ;; Rotate and shift insns, in all their variants. These support shifts,
3128 ;; field inserts and extracts, and various combinations thereof.
3129 (define_expand "insv"
3130 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3131 (match_operand:SI 1 "const_int_operand" "")
3132 (match_operand:SI 2 "const_int_operand" ""))
3133 (match_operand 3 "gpc_reg_operand" ""))]
3134 ""
3135 "
3136 {
3137 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3138 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3139 compiler if the address of the structure is taken later. */
3140 if (GET_CODE (operands[0]) == SUBREG
3141 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3142 FAIL;
3144 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3145 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3146 else
3147 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3148 DONE;
3149 }")
3151 (define_insn "insvsi"
3152 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3153 (match_operand:SI 1 "const_int_operand" "i")
3154 (match_operand:SI 2 "const_int_operand" "i"))
3155 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3156 ""
3157 "*
3158 {
3159 int start = INTVAL (operands[2]) & 31;
3160 int size = INTVAL (operands[1]) & 31;
3162 operands[4] = GEN_INT (32 - start - size);
3163 operands[1] = GEN_INT (start + size - 1);
3164 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3165 }")
3167 (define_insn "*insvsi_internal1"
3168 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3169 (match_operand:SI 1 "const_int_operand" "i")
3170 (match_operand:SI 2 "const_int_operand" "i"))
3171 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3172 (match_operand:SI 4 "const_int_operand" "i")))]
3173 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3174 "*
3175 {
3176 int shift = INTVAL (operands[4]) & 31;
3177 int start = INTVAL (operands[2]) & 31;
3178 int size = INTVAL (operands[1]) & 31;
3180 operands[4] = GEN_INT (shift - start - size);
3181 operands[1] = GEN_INT (start + size - 1);
3182 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3183 }")
3185 (define_insn "*insvsi_internal2"
3186 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3187 (match_operand:SI 1 "const_int_operand" "i")
3188 (match_operand:SI 2 "const_int_operand" "i"))
3189 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3190 (match_operand:SI 4 "const_int_operand" "i")))]
3191 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3192 "*
3193 {
3194 int shift = INTVAL (operands[4]) & 31;
3195 int start = INTVAL (operands[2]) & 31;
3196 int size = INTVAL (operands[1]) & 31;
3198 operands[4] = GEN_INT (32 - shift - start - size);
3199 operands[1] = GEN_INT (start + size - 1);
3200 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3201 }")
3203 (define_insn "*insvsi_internal3"
3204 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3205 (match_operand:SI 1 "const_int_operand" "i")
3206 (match_operand:SI 2 "const_int_operand" "i"))
3207 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3208 (match_operand:SI 4 "const_int_operand" "i")))]
3209 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3210 "*
3211 {
3212 int shift = INTVAL (operands[4]) & 31;
3213 int start = INTVAL (operands[2]) & 31;
3214 int size = INTVAL (operands[1]) & 31;
3216 operands[4] = GEN_INT (32 - shift - start - size);
3217 operands[1] = GEN_INT (start + size - 1);
3218 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3219 }")
3221 (define_insn "*insvsi_internal4"
3222 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3223 (match_operand:SI 1 "const_int_operand" "i")
3224 (match_operand:SI 2 "const_int_operand" "i"))
3225 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3226 (match_operand:SI 4 "const_int_operand" "i")
3227 (match_operand:SI 5 "const_int_operand" "i")))]
3228 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3229 "*
3230 {
3231 int extract_start = INTVAL (operands[5]) & 31;
3232 int extract_size = INTVAL (operands[4]) & 31;
3233 int insert_start = INTVAL (operands[2]) & 31;
3234 int insert_size = INTVAL (operands[1]) & 31;
3236 /* Align extract field with insert field */
3237 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3238 operands[1] = GEN_INT (insert_start + insert_size - 1);
3239 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3240 }")
3242 (define_insn "insvdi"
3243 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3244 (match_operand:SI 1 "const_int_operand" "i")
3245 (match_operand:SI 2 "const_int_operand" "i"))
3246 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3247 "TARGET_POWERPC64"
3248 "*
3249 {
3250 int start = INTVAL (operands[2]) & 63;
3251 int size = INTVAL (operands[1]) & 63;
3253 operands[1] = GEN_INT (64 - start - size);
3254 return \"rldimi %0,%3,%H1,%H2\";
3255 }")
3257 (define_expand "extzv"
3258 [(set (match_operand 0 "gpc_reg_operand" "")
3259 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3260 (match_operand:SI 2 "const_int_operand" "")
3261 (match_operand:SI 3 "const_int_operand" "")))]
3262 ""
3263 "
3264 {
3265 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3266 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3267 compiler if the address of the structure is taken later. */
3268 if (GET_CODE (operands[0]) == SUBREG
3269 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3270 FAIL;
3272 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3273 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3274 else
3275 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3276 DONE;
3277 }")
3279 (define_insn "extzvsi"
3280 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3281 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3282 (match_operand:SI 2 "const_int_operand" "i")
3283 (match_operand:SI 3 "const_int_operand" "i")))]
3284 ""
3285 "*
3286 {
3287 int start = INTVAL (operands[3]) & 31;
3288 int size = INTVAL (operands[2]) & 31;
3290 if (start + size >= 32)
3291 operands[3] = const0_rtx;
3292 else
3293 operands[3] = GEN_INT (start + size);
3294 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3295 }")
3297 (define_insn "*extzvsi_internal1"
3298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3299 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3300 (match_operand:SI 2 "const_int_operand" "i,i")
3301 (match_operand:SI 3 "const_int_operand" "i,i"))
3302 (const_int 0)))
3303 (clobber (match_scratch:SI 4 "=r,r"))]
3304 "! TARGET_POWERPC64"
3305 "*
3306 {
3307 int start = INTVAL (operands[3]) & 31;
3308 int size = INTVAL (operands[2]) & 31;
3310 /* Force split for non-cc0 compare. */
3311 if (which_alternative == 1)
3312 return \"#\";
3314 /* If the bitfield being tested fits in the upper or lower half of a
3315 word, it is possible to use andiu. or andil. to test it. This is
3316 useful because the condition register set-use delay is smaller for
3317 andi[ul]. than for rlinm. This doesn't work when the starting bit
3318 position is 0 because the LT and GT bits may be set wrong. */
3320 if ((start > 0 && start + size <= 16) || start >= 16)
3321 {
3322 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3323 - (1 << (16 - (start & 15) - size))));
3324 if (start < 16)
3325 return \"{andiu.|andis.} %4,%1,%3\";
3326 else
3327 return \"{andil.|andi.} %4,%1,%3\";
3328 }
3330 if (start + size >= 32)
3331 operands[3] = const0_rtx;
3332 else
3333 operands[3] = GEN_INT (start + size);
3334 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3335 }"
3336 [(set_attr "type" "compare")
3337 (set_attr "length" "4,8")])
3339 (define_split
3340 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3341 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3342 (match_operand:SI 2 "const_int_operand" "")
3343 (match_operand:SI 3 "const_int_operand" ""))
3344 (const_int 0)))
3345 (clobber (match_scratch:SI 4 ""))]
3346 "! TARGET_POWERPC64 && reload_completed"
3347 [(set (match_dup 4)
3348 (zero_extract:SI (match_dup 1) (match_dup 2)
3349 (match_dup 3)))
3350 (set (match_dup 0)
3351 (compare:CC (match_dup 4)
3352 (const_int 0)))]
3353 "")
3355 (define_insn "*extzvsi_internal2"
3356 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3357 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3358 (match_operand:SI 2 "const_int_operand" "i,i")
3359 (match_operand:SI 3 "const_int_operand" "i,i"))
3360 (const_int 0)))
3361 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3362 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3363 "! TARGET_POWERPC64"
3364 "*
3365 {
3366 int start = INTVAL (operands[3]) & 31;
3367 int size = INTVAL (operands[2]) & 31;
3369 /* Force split for non-cc0 compare. */
3370 if (which_alternative == 1)
3371 return \"#\";
3373 if (start >= 16 && start + size == 32)
3374 {
3375 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
3376 return \"{andil.|andi.} %0,%1,%3\";
3377 }
3379 if (start + size >= 32)
3380 operands[3] = const0_rtx;
3381 else
3382 operands[3] = GEN_INT (start + size);
3383 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3384 }"
3385 [(set_attr "type" "delayed_compare")
3386 (set_attr "length" "4,8")])
3388 (define_split
3389 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3390 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3391 (match_operand:SI 2 "const_int_operand" "")
3392 (match_operand:SI 3 "const_int_operand" ""))
3393 (const_int 0)))
3394 (set (match_operand:SI 0 "gpc_reg_operand" "")
3395 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3396 "! TARGET_POWERPC64 && reload_completed"
3397 [(set (match_dup 0)
3398 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3399 (set (match_dup 4)
3400 (compare:CC (match_dup 0)
3401 (const_int 0)))]
3402 "")
3404 (define_insn "extzvdi"
3405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3406 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3407 (match_operand:SI 2 "const_int_operand" "i")
3408 (match_operand:SI 3 "const_int_operand" "i")))]
3409 "TARGET_POWERPC64"
3410 "*
3411 {
3412 int start = INTVAL (operands[3]) & 63;
3413 int size = INTVAL (operands[2]) & 63;
3415 if (start + size >= 64)
3416 operands[3] = const0_rtx;
3417 else
3418 operands[3] = GEN_INT (start + size);
3419 operands[2] = GEN_INT (64 - size);
3420 return \"rldicl %0,%1,%3,%2\";
3421 }")
3423 (define_insn "*extzvdi_internal1"
3424 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3425 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3426 (match_operand:SI 2 "const_int_operand" "i")
3427 (match_operand:SI 3 "const_int_operand" "i"))
3428 (const_int 0)))
3429 (clobber (match_scratch:DI 4 "=r"))]
3430 "TARGET_POWERPC64"
3431 "*
3432 {
3433 int start = INTVAL (operands[3]) & 63;
3434 int size = INTVAL (operands[2]) & 63;
3436 if (start + size >= 64)
3437 operands[3] = const0_rtx;
3438 else
3439 operands[3] = GEN_INT (start + size);
3440 operands[2] = GEN_INT (64 - size);
3441 return \"rldicl. %4,%1,%3,%2\";
3442 }")
3444 (define_insn "*extzvdi_internal2"
3445 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3446 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3447 (match_operand:SI 2 "const_int_operand" "i")
3448 (match_operand:SI 3 "const_int_operand" "i"))
3449 (const_int 0)))
3450 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3451 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3452 "TARGET_POWERPC64"
3453 "*
3454 {
3455 int start = INTVAL (operands[3]) & 63;
3456 int size = INTVAL (operands[2]) & 63;
3458 if (start + size >= 64)
3459 operands[3] = const0_rtx;
3460 else
3461 operands[3] = GEN_INT (start + size);
3462 operands[2] = GEN_INT (64 - size);
3463 return \"rldicl. %0,%1,%3,%2\";
3464 }")
3466 (define_insn "rotlsi3"
3467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3469 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3470 ""
3471 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3473 (define_insn "*rotlsi3_internal2"
3474 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3475 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3476 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3477 (const_int 0)))
3478 (clobber (match_scratch:SI 3 "=r,r"))]
3479 "! TARGET_POWERPC64"
3480 "@
3481 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3482 #"
3483 [(set_attr "type" "delayed_compare")
3484 (set_attr "length" "4,8")])
3486 (define_split
3487 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3488 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3489 (match_operand:SI 2 "reg_or_cint_operand" ""))
3490 (const_int 0)))
3491 (clobber (match_scratch:SI 3 ""))]
3492 "! TARGET_POWERPC64 && reload_completed"
3493 [(set (match_dup 3)
3494 (rotate:SI (match_dup 1) (match_dup 2)))
3495 (set (match_dup 0)
3496 (compare:CC (match_dup 3)
3497 (const_int 0)))]
3498 "")
3500 (define_insn "*rotlsi3_internal3"
3501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3502 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3503 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3504 (const_int 0)))
3505 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3506 (rotate:SI (match_dup 1) (match_dup 2)))]
3507 "! TARGET_POWERPC64"
3508 "@
3509 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3510 #"
3511 [(set_attr "type" "delayed_compare")
3512 (set_attr "length" "4,8")])
3514 (define_split
3515 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3516 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3517 (match_operand:SI 2 "reg_or_cint_operand" ""))
3518 (const_int 0)))
3519 (set (match_operand:SI 0 "gpc_reg_operand" "")
3520 (rotate:SI (match_dup 1) (match_dup 2)))]
3521 "! TARGET_POWERPC64 && reload_completed"
3522 [(set (match_dup 0)
3523 (rotate:SI (match_dup 1) (match_dup 2)))
3524 (set (match_dup 3)
3525 (compare:CC (match_dup 0)
3526 (const_int 0)))]
3527 "")
3529 (define_insn "*rotlsi3_internal4"
3530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3531 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3532 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3533 (match_operand:SI 3 "mask_operand" "T")))]
3534 ""
3535 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3537 (define_insn "*rotlsi3_internal5"
3538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3539 (compare:CC (and:SI
3540 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3541 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3542 (match_operand:SI 3 "mask_operand" "T,T"))
3543 (const_int 0)))
3544 (clobber (match_scratch:SI 4 "=r,r"))]
3545 "! TARGET_POWERPC64"
3546 "@
3547 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3548 #"
3549 [(set_attr "type" "delayed_compare")
3550 (set_attr "length" "4,8")])
3552 (define_split
3553 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3554 (compare:CC (and:SI
3555 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3556 (match_operand:SI 2 "reg_or_cint_operand" ""))
3557 (match_operand:SI 3 "mask_operand" ""))
3558 (const_int 0)))
3559 (clobber (match_scratch:SI 4 ""))]
3560 "! TARGET_POWERPC64 && reload_completed"
3561 [(set (match_dup 4)
3562 (and:SI (rotate:SI (match_dup 1)
3563 (match_dup 2))
3564 (match_dup 3)))
3565 (set (match_dup 0)
3566 (compare:CC (match_dup 4)
3567 (const_int 0)))]
3568 "")
3570 (define_insn "*rotlsi3_internal6"
3571 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3572 (compare:CC (and:SI
3573 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3574 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3575 (match_operand:SI 3 "mask_operand" "T,T"))
3576 (const_int 0)))
3577 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3578 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3579 "! TARGET_POWERPC64"
3580 "@
3581 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3582 #"
3583 [(set_attr "type" "delayed_compare")
3584 (set_attr "length" "4,8")])
3586 (define_split
3587 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3588 (compare:CC (and:SI
3589 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3590 (match_operand:SI 2 "reg_or_cint_operand" ""))
3591 (match_operand:SI 3 "mask_operand" ""))
3592 (const_int 0)))
3593 (set (match_operand:SI 0 "gpc_reg_operand" "")
3594 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3595 "! TARGET_POWERPC64 && reload_completed"
3596 [(set (match_dup 0)
3597 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3598 (set (match_dup 4)
3599 (compare:CC (match_dup 0)
3600 (const_int 0)))]
3601 "")
3603 (define_insn "*rotlsi3_internal7"
3604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3605 (zero_extend:SI
3606 (subreg:QI
3607 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3608 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3609 ""
3610 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3612 (define_insn "*rotlsi3_internal8"
3613 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3614 (compare:CC (zero_extend:SI
3615 (subreg:QI
3616 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3617 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3618 (const_int 0)))
3619 (clobber (match_scratch:SI 3 "=r,r"))]
3620 ""
3621 "@
3622 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3623 #"
3624 [(set_attr "type" "delayed_compare")
3625 (set_attr "length" "4,8")])
3627 (define_split
3628 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3629 (compare:CC (zero_extend:SI
3630 (subreg:QI
3631 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3633 (const_int 0)))
3634 (clobber (match_scratch:SI 3 ""))]
3635 "reload_completed"
3636 [(set (match_dup 3)
3637 (zero_extend:SI (subreg:QI
3638 (rotate:SI (match_dup 1)
3639 (match_dup 2)) 0)))
3640 (set (match_dup 0)
3641 (compare:CC (match_dup 3)
3642 (const_int 0)))]
3643 "")
3645 (define_insn "*rotlsi3_internal9"
3646 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3647 (compare:CC (zero_extend:SI
3648 (subreg:QI
3649 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3650 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3651 (const_int 0)))
3652 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3653 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3654 ""
3655 "@
3656 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3657 #"
3658 [(set_attr "type" "delayed_compare")
3659 (set_attr "length" "4,8")])
3661 (define_split
3662 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3663 (compare:CC (zero_extend:SI
3664 (subreg:QI
3665 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3666 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3667 (const_int 0)))
3668 (set (match_operand:SI 0 "gpc_reg_operand" "")
3669 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3670 "reload_completed"
3671 [(set (match_dup 0)
3672 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3673 (set (match_dup 3)
3674 (compare:CC (match_dup 0)
3675 (const_int 0)))]
3676 "")
3678 (define_insn "*rotlsi3_internal10"
3679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3680 (zero_extend:SI
3681 (subreg:HI
3682 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3683 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3684 ""
3685 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3687 (define_insn "*rotlsi3_internal11"
3688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3689 (compare:CC (zero_extend:SI
3690 (subreg:HI
3691 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3692 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3693 (const_int 0)))
3694 (clobber (match_scratch:SI 3 "=r,r"))]
3695 ""
3696 "@
3697 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3698 #"
3699 [(set_attr "type" "delayed_compare")
3700 (set_attr "length" "4,8")])
3702 (define_split
3703 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3704 (compare:CC (zero_extend:SI
3705 (subreg:HI
3706 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3707 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3708 (const_int 0)))
3709 (clobber (match_scratch:SI 3 ""))]
3710 "reload_completed"
3711 [(set (match_dup 3)
3712 (zero_extend:SI (subreg:HI
3713 (rotate:SI (match_dup 1)
3714 (match_dup 2)) 0)))
3715 (set (match_dup 0)
3716 (compare:CC (match_dup 3)
3717 (const_int 0)))]
3718 "")
3720 (define_insn "*rotlsi3_internal12"
3721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3722 (compare:CC (zero_extend:SI
3723 (subreg:HI
3724 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3725 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3726 (const_int 0)))
3727 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3728 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3729 ""
3730 "@
3731 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3732 #"
3733 [(set_attr "type" "delayed_compare")
3734 (set_attr "length" "4,8")])
3736 (define_split
3737 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3738 (compare:CC (zero_extend:SI
3739 (subreg:HI
3740 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3741 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3742 (const_int 0)))
3743 (set (match_operand:SI 0 "gpc_reg_operand" "")
3744 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3745 "reload_completed"
3746 [(set (match_dup 0)
3747 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3748 (set (match_dup 3)
3749 (compare:CC (match_dup 0)
3750 (const_int 0)))]
3751 "")
3753 ;; Note that we use "sle." instead of "sl." so that we can set
3754 ;; SHIFT_COUNT_TRUNCATED.
3756 (define_expand "ashlsi3"
3757 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3758 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3759 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3760 ""
3761 "
3762 {
3763 if (TARGET_POWER)
3764 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3765 else
3766 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3767 DONE;
3768 }")
3770 (define_insn "ashlsi3_power"
3771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3772 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3773 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3774 (clobber (match_scratch:SI 3 "=q,X"))]
3775 "TARGET_POWER"
3776 "@
3777 sle %0,%1,%2
3778 {sli|slwi} %0,%1,%h2")
3780 (define_insn "ashlsi3_no_power"
3781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3782 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3783 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3784 "! TARGET_POWER"
3785 "{sl|slw}%I2 %0,%1,%h2")
3787 (define_insn ""
3788 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3789 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3790 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3791 (const_int 0)))
3792 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3793 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3794 "TARGET_POWER"
3795 "@
3796 sle. %3,%1,%2
3797 {sli.|slwi.} %3,%1,%h2
3798 #
3799 #"
3800 [(set_attr "type" "delayed_compare")
3801 (set_attr "length" "4,4,8,8")])
3803 (define_split
3804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3805 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3806 (match_operand:SI 2 "reg_or_cint_operand" ""))
3807 (const_int 0)))
3808 (clobber (match_scratch:SI 3 ""))
3809 (clobber (match_scratch:SI 4 ""))]
3810 "TARGET_POWER && reload_completed"
3811 [(parallel [(set (match_dup 3)
3812 (ashift:SI (match_dup 1) (match_dup 2)))
3813 (clobber (match_dup 4))])
3814 (set (match_dup 0)
3815 (compare:CC (match_dup 3)
3816 (const_int 0)))]
3817 "")
3819 (define_insn ""
3820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3821 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3822 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3823 (const_int 0)))
3824 (clobber (match_scratch:SI 3 "=r,r"))]
3825 "! TARGET_POWER && ! TARGET_POWERPC64"
3826 "@
3827 {sl|slw}%I2. %3,%1,%h2
3828 #"
3829 [(set_attr "type" "delayed_compare")
3830 (set_attr "length" "4,8")])
3832 (define_split
3833 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3834 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3835 (match_operand:SI 2 "reg_or_cint_operand" ""))
3836 (const_int 0)))
3837 (clobber (match_scratch:SI 3 ""))]
3838 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3839 [(set (match_dup 3)
3840 (ashift:SI (match_dup 1) (match_dup 2)))
3841 (set (match_dup 0)
3842 (compare:CC (match_dup 3)
3843 (const_int 0)))]
3844 "")
3846 (define_insn ""
3847 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3848 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3849 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3850 (const_int 0)))
3851 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3852 (ashift:SI (match_dup 1) (match_dup 2)))
3853 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3854 "TARGET_POWER"
3855 "@
3856 sle. %0,%1,%2
3857 {sli.|slwi.} %0,%1,%h2
3858 #
3859 #"
3860 [(set_attr "type" "delayed_compare")
3861 (set_attr "length" "4,4,8,8")])
3863 (define_split
3864 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3865 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3866 (match_operand:SI 2 "reg_or_cint_operand" ""))
3867 (const_int 0)))
3868 (set (match_operand:SI 0 "gpc_reg_operand" "")
3869 (ashift:SI (match_dup 1) (match_dup 2)))
3870 (clobber (match_scratch:SI 4 ""))]
3871 "TARGET_POWER && reload_completed"
3872 [(parallel [(set (match_dup 0)
3873 (ashift:SI (match_dup 1) (match_dup 2)))
3874 (clobber (match_dup 4))])
3875 (set (match_dup 3)
3876 (compare:CC (match_dup 0)
3877 (const_int 0)))]
3878 "")
3880 (define_insn ""
3881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3882 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3883 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3884 (const_int 0)))
3885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3886 (ashift:SI (match_dup 1) (match_dup 2)))]
3887 "! TARGET_POWER && ! TARGET_POWERPC64"
3888 "@
3889 {sl|slw}%I2. %0,%1,%h2
3890 #"
3891 [(set_attr "type" "delayed_compare")
3892 (set_attr "length" "4,8")])
3894 (define_split
3895 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3896 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3897 (match_operand:SI 2 "reg_or_cint_operand" ""))
3898 (const_int 0)))
3899 (set (match_operand:SI 0 "gpc_reg_operand" "")
3900 (ashift:SI (match_dup 1) (match_dup 2)))]
3901 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3902 [(set (match_dup 0)
3903 (ashift:SI (match_dup 1) (match_dup 2)))
3904 (set (match_dup 3)
3905 (compare:CC (match_dup 0)
3906 (const_int 0)))]
3907 "")
3909 (define_insn ""
3910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3911 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3912 (match_operand:SI 2 "const_int_operand" "i"))
3913 (match_operand:SI 3 "mask_operand" "T")))]
3914 "includes_lshift_p (operands[2], operands[3])"
3915 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3917 (define_insn ""
3918 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3919 (compare:CC
3920 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3921 (match_operand:SI 2 "const_int_operand" "i,i"))
3922 (match_operand:SI 3 "mask_operand" "T,T"))
3923 (const_int 0)))
3924 (clobber (match_scratch:SI 4 "=r,r"))]
3925 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
3926 "@
3927 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3928 #"
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,8")])
3932 (define_split
3933 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3934 (compare:CC
3935 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3936 (match_operand:SI 2 "const_int_operand" ""))
3937 (match_operand:SI 3 "mask_operand" ""))
3938 (const_int 0)))
3939 (clobber (match_scratch:SI 4 ""))]
3940 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
3941 [(set (match_dup 4)
3942 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3943 (match_dup 3)))
3944 (set (match_dup 0)
3945 (compare:CC (match_dup 4)
3946 (const_int 0)))]
3947 "")
3949 (define_insn ""
3950 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3951 (compare:CC
3952 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3953 (match_operand:SI 2 "const_int_operand" "i,i"))
3954 (match_operand:SI 3 "mask_operand" "T,T"))
3955 (const_int 0)))
3956 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3957 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3958 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
3959 "@
3960 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3961 #"
3962 [(set_attr "type" "delayed_compare")
3963 (set_attr "length" "4,8")])
3965 (define_split
3966 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3967 (compare:CC
3968 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3969 (match_operand:SI 2 "const_int_operand" ""))
3970 (match_operand:SI 3 "mask_operand" ""))
3971 (const_int 0)))
3972 (set (match_operand:SI 0 "gpc_reg_operand" "")
3973 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3974 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
3975 [(set (match_dup 0)
3976 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3977 (set (match_dup 4)
3978 (compare:CC (match_dup 0)
3979 (const_int 0)))]
3980 "")
3982 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3983 ;; "sli x,x,0".
3984 (define_expand "lshrsi3"
3985 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3986 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3987 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3988 ""
3989 "
3990 {
3991 if (TARGET_POWER)
3992 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3993 else
3994 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3995 DONE;
3996 }")
3998 (define_insn "lshrsi3_power"
3999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4000 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4001 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4002 (clobber (match_scratch:SI 3 "=q,X,X"))]
4003 "TARGET_POWER"
4004 "@
4005 sre %0,%1,%2
4006 mr %0,%1
4007 {s%A2i|s%A2wi} %0,%1,%h2")
4009 (define_insn "lshrsi3_no_power"
4010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4011 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4012 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4013 "! TARGET_POWER"
4014 "@
4015 mr %0,%1
4016 {sr|srw}%I2 %0,%1,%h2")
4018 (define_insn ""
4019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4020 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4021 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4022 (const_int 0)))
4023 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4024 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4025 "TARGET_POWER"
4026 "@
4027 sre. %3,%1,%2
4028 mr. %1,%1
4029 {s%A2i.|s%A2wi.} %3,%1,%h2
4030 #
4031 #
4032 #"
4033 [(set_attr "type" "delayed_compare")
4034 (set_attr "length" "4,4,4,8,8,8")])
4036 (define_split
4037 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4038 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4039 (match_operand:SI 2 "reg_or_cint_operand" ""))
4040 (const_int 0)))
4041 (clobber (match_scratch:SI 3 ""))
4042 (clobber (match_scratch:SI 4 ""))]
4043 "TARGET_POWER && reload_completed"
4044 [(parallel [(set (match_dup 3)
4045 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4046 (clobber (match_dup 4))])
4047 (set (match_dup 0)
4048 (compare:CC (match_dup 3)
4049 (const_int 0)))]
4050 "")
4052 (define_insn ""
4053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4054 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4055 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4056 (const_int 0)))
4057 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4058 "! TARGET_POWER && ! TARGET_POWERPC64"
4059 "@
4060 mr. %1,%1
4061 {sr|srw}%I2. %3,%1,%h2
4062 #
4063 #"
4064 [(set_attr "type" "delayed_compare")
4065 (set_attr "length" "4,4,8,8")])
4067 (define_split
4068 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4069 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4070 (match_operand:SI 2 "reg_or_cint_operand" ""))
4071 (const_int 0)))
4072 (clobber (match_scratch:SI 3 ""))]
4073 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4074 [(set (match_dup 3)
4075 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4076 (set (match_dup 0)
4077 (compare:CC (match_dup 3)
4078 (const_int 0)))]
4079 "")
4081 (define_insn ""
4082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4083 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4084 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4085 (const_int 0)))
4086 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4087 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4088 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4089 "TARGET_POWER"
4090 "@
4091 sre. %0,%1,%2
4092 mr. %0,%1
4093 {s%A2i.|s%A2wi.} %0,%1,%h2
4094 #
4095 #
4096 #"
4097 [(set_attr "type" "delayed_compare")
4098 (set_attr "length" "4,4,4,8,8,8")])
4100 (define_split
4101 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4102 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4103 (match_operand:SI 2 "reg_or_cint_operand" ""))
4104 (const_int 0)))
4105 (set (match_operand:SI 0 "gpc_reg_operand" "")
4106 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4107 (clobber (match_scratch:SI 4 ""))]
4108 "TARGET_POWER && reload_completed"
4109 [(parallel [(set (match_dup 0)
4110 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4111 (clobber (match_dup 4))])
4112 (set (match_dup 3)
4113 (compare:CC (match_dup 0)
4114 (const_int 0)))]
4115 "")
4117 (define_insn ""
4118 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4119 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4120 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4121 (const_int 0)))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4123 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4124 "! TARGET_POWER && ! TARGET_POWERPC64"
4125 "@
4126 mr. %0,%1
4127 {sr|srw}%I2. %0,%1,%h2
4128 #
4129 #"
4130 [(set_attr "type" "delayed_compare")
4131 (set_attr "length" "4,4,8,8")])
4133 (define_split
4134 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4135 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4136 (match_operand:SI 2 "reg_or_cint_operand" ""))
4137 (const_int 0)))
4138 (set (match_operand:SI 0 "gpc_reg_operand" "")
4139 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4140 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4141 [(set (match_dup 0)
4142 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4143 (set (match_dup 3)
4144 (compare:CC (match_dup 0)
4145 (const_int 0)))]
4146 "")
4148 (define_insn ""
4149 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4150 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4151 (match_operand:SI 2 "const_int_operand" "i"))
4152 (match_operand:SI 3 "mask_operand" "T")))]
4153 "includes_rshift_p (operands[2], operands[3])"
4154 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4156 (define_insn ""
4157 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4158 (compare:CC
4159 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4160 (match_operand:SI 2 "const_int_operand" "i,i"))
4161 (match_operand:SI 3 "mask_operand" "T,T"))
4162 (const_int 0)))
4163 (clobber (match_scratch:SI 4 "=r,r"))]
4164 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4165 "@
4166 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4167 #"
4168 [(set_attr "type" "delayed_compare")
4169 (set_attr "length" "4,8")])
4171 (define_split
4172 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4173 (compare:CC
4174 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4175 (match_operand:SI 2 "const_int_operand" ""))
4176 (match_operand:SI 3 "mask_operand" ""))
4177 (const_int 0)))
4178 (clobber (match_scratch:SI 4 ""))]
4179 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4180 [(set (match_dup 4)
4181 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4182 (match_dup 3)))
4183 (set (match_dup 0)
4184 (compare:CC (match_dup 4)
4185 (const_int 0)))]
4186 "")
4188 (define_insn ""
4189 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4190 (compare:CC
4191 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4192 (match_operand:SI 2 "const_int_operand" "i,i"))
4193 (match_operand:SI 3 "mask_operand" "T,T"))
4194 (const_int 0)))
4195 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4196 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4197 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4198 "@
4199 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4200 #"
4201 [(set_attr "type" "delayed_compare")
4202 (set_attr "length" "4,8")])
4204 (define_split
4205 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4206 (compare:CC
4207 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4208 (match_operand:SI 2 "const_int_operand" ""))
4209 (match_operand:SI 3 "mask_operand" ""))
4210 (const_int 0)))
4211 (set (match_operand:SI 0 "gpc_reg_operand" "")
4212 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4213 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4214 [(set (match_dup 0)
4215 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4216 (set (match_dup 4)
4217 (compare:CC (match_dup 0)
4218 (const_int 0)))]
4219 "")
4221 (define_insn ""
4222 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4223 (zero_extend:SI
4224 (subreg:QI
4225 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4226 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4227 "includes_rshift_p (operands[2], GEN_INT (255))"
4228 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4230 (define_insn ""
4231 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4232 (compare:CC
4233 (zero_extend:SI
4234 (subreg:QI
4235 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4236 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4237 (const_int 0)))
4238 (clobber (match_scratch:SI 3 "=r,r"))]
4239 "includes_rshift_p (operands[2], GEN_INT (255))"
4240 "@
4241 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4242 #"
4243 [(set_attr "type" "delayed_compare")
4244 (set_attr "length" "4,8")])
4246 (define_split
4247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4248 (compare:CC
4249 (zero_extend:SI
4250 (subreg:QI
4251 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4252 (match_operand:SI 2 "const_int_operand" "")) 0))
4253 (const_int 0)))
4254 (clobber (match_scratch:SI 3 ""))]
4255 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4256 [(set (match_dup 3)
4257 (zero_extend:SI (subreg:QI
4258 (lshiftrt:SI (match_dup 1)
4259 (match_dup 2)) 0)))
4260 (set (match_dup 0)
4261 (compare:CC (match_dup 3)
4262 (const_int 0)))]
4263 "")
4265 (define_insn ""
4266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4267 (compare:CC
4268 (zero_extend:SI
4269 (subreg:QI
4270 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4271 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4272 (const_int 0)))
4273 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4274 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4275 "includes_rshift_p (operands[2], GEN_INT (255))"
4276 "@
4277 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4278 #"
4279 [(set_attr "type" "delayed_compare")
4280 (set_attr "length" "4,8")])
4282 (define_split
4283 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4284 (compare:CC
4285 (zero_extend:SI
4286 (subreg:QI
4287 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4288 (match_operand:SI 2 "const_int_operand" "")) 0))
4289 (const_int 0)))
4290 (set (match_operand:SI 0 "gpc_reg_operand" "")
4291 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4292 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4293 [(set (match_dup 0)
4294 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4295 (set (match_dup 3)
4296 (compare:CC (match_dup 0)
4297 (const_int 0)))]
4298 "")
4300 (define_insn ""
4301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4302 (zero_extend:SI
4303 (subreg:HI
4304 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4305 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4306 "includes_rshift_p (operands[2], GEN_INT (65535))"
4307 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4309 (define_insn ""
4310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4311 (compare:CC
4312 (zero_extend:SI
4313 (subreg:HI
4314 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4315 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4316 (const_int 0)))
4317 (clobber (match_scratch:SI 3 "=r,r"))]
4318 "includes_rshift_p (operands[2], GEN_INT (65535))"
4319 "@
4320 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4321 #"
4322 [(set_attr "type" "delayed_compare")
4323 (set_attr "length" "4,8")])
4325 (define_split
4326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4327 (compare:CC
4328 (zero_extend:SI
4329 (subreg:HI
4330 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4331 (match_operand:SI 2 "const_int_operand" "")) 0))
4332 (const_int 0)))
4333 (clobber (match_scratch:SI 3 ""))]
4334 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4335 [(set (match_dup 3)
4336 (zero_extend:SI (subreg:HI
4337 (lshiftrt:SI (match_dup 1)
4338 (match_dup 2)) 0)))
4339 (set (match_dup 0)
4340 (compare:CC (match_dup 3)
4341 (const_int 0)))]
4342 "")
4344 (define_insn ""
4345 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4346 (compare:CC
4347 (zero_extend:SI
4348 (subreg:HI
4349 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4350 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4351 (const_int 0)))
4352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4353 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4354 "includes_rshift_p (operands[2], GEN_INT (65535))"
4355 "@
4356 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4357 #"
4358 [(set_attr "type" "delayed_compare")
4359 (set_attr "length" "4,8")])
4361 (define_split
4362 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4363 (compare:CC
4364 (zero_extend:SI
4365 (subreg:HI
4366 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4367 (match_operand:SI 2 "const_int_operand" "")) 0))
4368 (const_int 0)))
4369 (set (match_operand:SI 0 "gpc_reg_operand" "")
4370 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4371 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4372 [(set (match_dup 0)
4373 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4374 (set (match_dup 3)
4375 (compare:CC (match_dup 0)
4376 (const_int 0)))]
4377 "")
4379 (define_insn ""
4380 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4381 (const_int 1)
4382 (match_operand:SI 1 "gpc_reg_operand" "r"))
4383 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4384 (const_int 31)))]
4385 "TARGET_POWER"
4386 "rrib %0,%1,%2")
4388 (define_insn ""
4389 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4390 (const_int 1)
4391 (match_operand:SI 1 "gpc_reg_operand" "r"))
4392 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4393 (const_int 31)))]
4394 "TARGET_POWER"
4395 "rrib %0,%1,%2")
4397 (define_insn ""
4398 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4399 (const_int 1)
4400 (match_operand:SI 1 "gpc_reg_operand" "r"))
4401 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4402 (const_int 1)
4403 (const_int 0)))]
4404 "TARGET_POWER"
4405 "rrib %0,%1,%2")
4407 (define_expand "ashrsi3"
4408 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4409 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4410 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4411 ""
4412 "
4413 {
4414 if (TARGET_POWER)
4415 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4416 else
4417 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4418 DONE;
4419 }")
4421 (define_insn "ashrsi3_power"
4422 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4423 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4424 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4425 (clobber (match_scratch:SI 3 "=q,X"))]
4426 "TARGET_POWER"
4427 "@
4428 srea %0,%1,%2
4429 {srai|srawi} %0,%1,%h2")
4431 (define_insn "ashrsi3_no_power"
4432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4433 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4434 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4435 "! TARGET_POWER"
4436 "{sra|sraw}%I2 %0,%1,%h2")
4438 (define_insn ""
4439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4440 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4441 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4442 (const_int 0)))
4443 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4444 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4445 "TARGET_POWER"
4446 "@
4447 srea. %3,%1,%2
4448 {srai.|srawi.} %3,%1,%h2
4449 #
4450 #"
4451 [(set_attr "type" "delayed_compare")
4452 (set_attr "length" "4,4,8,8")])
4454 (define_split
4455 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4456 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4457 (match_operand:SI 2 "reg_or_cint_operand" ""))
4458 (const_int 0)))
4459 (clobber (match_scratch:SI 3 ""))
4460 (clobber (match_scratch:SI 4 ""))]
4461 "TARGET_POWER && reload_completed"
4462 [(parallel [(set (match_dup 3)
4463 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4464 (clobber (match_dup 4))])
4465 (set (match_dup 0)
4466 (compare:CC (match_dup 3)
4467 (const_int 0)))]
4468 "")
4470 (define_insn ""
4471 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4472 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4473 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4474 (const_int 0)))
4475 (clobber (match_scratch:SI 3 "=r,r"))]
4476 "! TARGET_POWER"
4477 "@
4478 {sra|sraw}%I2. %3,%1,%h2
4479 #"
4480 [(set_attr "type" "delayed_compare")
4481 (set_attr "length" "4,8")])
4483 (define_split
4484 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4485 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4486 (match_operand:SI 2 "reg_or_cint_operand" ""))
4487 (const_int 0)))
4488 (clobber (match_scratch:SI 3 ""))]
4489 "! TARGET_POWER && reload_completed"
4490 [(set (match_dup 3)
4491 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4492 (set (match_dup 0)
4493 (compare:CC (match_dup 3)
4494 (const_int 0)))]
4495 "")
4497 (define_insn ""
4498 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4499 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4500 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4501 (const_int 0)))
4502 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4503 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4504 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4505 "TARGET_POWER"
4506 "@
4507 srea. %0,%1,%2
4508 {srai.|srawi.} %0,%1,%h2
4509 #
4510 #"
4511 [(set_attr "type" "delayed_compare")
4512 (set_attr "length" "4,4,8,8")])
4514 (define_split
4515 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4516 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4517 (match_operand:SI 2 "reg_or_cint_operand" ""))
4518 (const_int 0)))
4519 (set (match_operand:SI 0 "gpc_reg_operand" "")
4520 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4521 (clobber (match_scratch:SI 4 ""))]
4522 "TARGET_POWER && reload_completed"
4523 [(parallel [(set (match_dup 0)
4524 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4525 (clobber (match_dup 4))])
4526 (set (match_dup 3)
4527 (compare:CC (match_dup 0)
4528 (const_int 0)))]
4529 "")
4531 (define_insn ""
4532 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4533 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4534 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4535 (const_int 0)))
4536 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4537 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4538 "! TARGET_POWER"
4539 "@
4540 {sra|sraw}%I2. %0,%1,%h2
4541 #"
4542 [(set_attr "type" "delayed_compare")
4543 (set_attr "length" "4,8")])
4544 \f
4545 (define_split
4546 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4547 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4548 (match_operand:SI 2 "reg_or_cint_operand" ""))
4549 (const_int 0)))
4550 (set (match_operand:SI 0 "gpc_reg_operand" "")
4551 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4552 "! TARGET_POWER && reload_completed"
4553 [(set (match_dup 0)
4554 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4555 (set (match_dup 3)
4556 (compare:CC (match_dup 0)
4557 (const_int 0)))]
4558 "")
4560 ;; Floating-point insns, excluding normal data motion.
4561 ;;
4562 ;; PowerPC has a full set of single-precision floating point instructions.
4563 ;;
4564 ;; For the POWER architecture, we pretend that we have both SFmode and
4565 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4566 ;; The only conversions we will do will be when storing to memory. In that
4567 ;; case, we will use the "frsp" instruction before storing.
4568 ;;
4569 ;; Note that when we store into a single-precision memory location, we need to
4570 ;; use the frsp insn first. If the register being stored isn't dead, we
4571 ;; need a scratch register for the frsp. But this is difficult when the store
4572 ;; is done by reload. It is not incorrect to do the frsp on the register in
4573 ;; this case, we just lose precision that we would have otherwise gotten but
4574 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4576 (define_insn "extendsfdf2"
4577 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4578 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4579 "TARGET_HARD_FLOAT"
4580 "*
4581 {
4582 if (REGNO (operands[0]) == REGNO (operands[1]))
4583 return \"\";
4584 else
4585 return \"fmr %0,%1\";
4586 }"
4587 [(set_attr "type" "fp")])
4589 (define_insn "truncdfsf2"
4590 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4591 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4592 "TARGET_HARD_FLOAT"
4593 "frsp %0,%1"
4594 [(set_attr "type" "fp")])
4596 (define_insn "aux_truncdfsf2"
4597 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4598 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4599 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4600 "frsp %0,%1"
4601 [(set_attr "type" "fp")])
4603 (define_insn "negsf2"
4604 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4605 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4606 "TARGET_HARD_FLOAT"
4607 "fneg %0,%1"
4608 [(set_attr "type" "fp")])
4610 (define_insn "abssf2"
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4613 "TARGET_HARD_FLOAT"
4614 "fabs %0,%1"
4615 [(set_attr "type" "fp")])
4617 (define_insn ""
4618 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4619 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4620 "TARGET_HARD_FLOAT"
4621 "fnabs %0,%1"
4622 [(set_attr "type" "fp")])
4624 (define_expand "addsf3"
4625 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4626 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4627 (match_operand:SF 2 "gpc_reg_operand" "")))]
4628 "TARGET_HARD_FLOAT"
4629 "")
4631 (define_insn ""
4632 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4633 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4634 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4635 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4636 "fadds %0,%1,%2"
4637 [(set_attr "type" "fp")])
4639 (define_insn ""
4640 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4641 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4642 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4643 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4644 "{fa|fadd} %0,%1,%2"
4645 [(set_attr "type" "fp")])
4647 (define_expand "subsf3"
4648 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4649 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4650 (match_operand:SF 2 "gpc_reg_operand" "")))]
4651 "TARGET_HARD_FLOAT"
4652 "")
4654 (define_insn ""
4655 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4656 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4657 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4658 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4659 "fsubs %0,%1,%2"
4660 [(set_attr "type" "fp")])
4662 (define_insn ""
4663 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4664 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4665 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4666 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4667 "{fs|fsub} %0,%1,%2"
4668 [(set_attr "type" "fp")])
4670 (define_expand "mulsf3"
4671 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4672 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4673 (match_operand:SF 2 "gpc_reg_operand" "")))]
4674 "TARGET_HARD_FLOAT"
4675 "")
4677 (define_insn ""
4678 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4679 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4680 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4681 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4682 "fmuls %0,%1,%2"
4683 [(set_attr "type" "fp")])
4685 (define_insn ""
4686 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4687 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4688 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4689 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4690 "{fm|fmul} %0,%1,%2"
4691 [(set_attr "type" "dmul")])
4693 (define_expand "divsf3"
4694 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4695 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4696 (match_operand:SF 2 "gpc_reg_operand" "")))]
4697 "TARGET_HARD_FLOAT"
4698 "")
4700 (define_insn ""
4701 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4702 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4703 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4704 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4705 "fdivs %0,%1,%2"
4706 [(set_attr "type" "sdiv")])
4708 (define_insn ""
4709 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4710 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4711 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4712 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4713 "{fd|fdiv} %0,%1,%2"
4714 [(set_attr "type" "ddiv")])
4716 (define_insn ""
4717 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4718 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4719 (match_operand:SF 2 "gpc_reg_operand" "f"))
4720 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4721 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4722 "fmadds %0,%1,%2,%3"
4723 [(set_attr "type" "fp")])
4725 (define_insn ""
4726 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4727 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4728 (match_operand:SF 2 "gpc_reg_operand" "f"))
4729 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4730 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4731 "{fma|fmadd} %0,%1,%2,%3"
4732 [(set_attr "type" "dmul")])
4734 (define_insn ""
4735 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4736 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4737 (match_operand:SF 2 "gpc_reg_operand" "f"))
4738 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4739 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4740 "fmsubs %0,%1,%2,%3"
4741 [(set_attr "type" "fp")])
4743 (define_insn ""
4744 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4745 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4746 (match_operand:SF 2 "gpc_reg_operand" "f"))
4747 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4748 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4749 "{fms|fmsub} %0,%1,%2,%3"
4750 [(set_attr "type" "dmul")])
4752 (define_insn ""
4753 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4754 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4755 (match_operand:SF 2 "gpc_reg_operand" "f"))
4756 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4757 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4758 "fnmadds %0,%1,%2,%3"
4759 [(set_attr "type" "fp")])
4761 (define_insn ""
4762 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4763 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4764 (match_operand:SF 2 "gpc_reg_operand" "f"))
4765 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4766 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4767 "{fnma|fnmadd} %0,%1,%2,%3"
4768 [(set_attr "type" "dmul")])
4770 (define_insn ""
4771 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4772 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4773 (match_operand:SF 2 "gpc_reg_operand" "f"))
4774 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4775 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4776 "fnmsubs %0,%1,%2,%3"
4777 [(set_attr "type" "fp")])
4779 (define_insn ""
4780 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4781 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4782 (match_operand:SF 2 "gpc_reg_operand" "f"))
4783 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4784 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4785 "{fnms|fnmsub} %0,%1,%2,%3"
4786 [(set_attr "type" "dmul")])
4788 (define_expand "sqrtsf2"
4789 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4790 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4791 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
4792 "")
4794 (define_insn ""
4795 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4796 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4797 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
4798 "fsqrts %0,%1"
4799 [(set_attr "type" "ssqrt")])
4801 (define_insn ""
4802 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4803 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4804 "TARGET_POWER2 && TARGET_HARD_FLOAT"
4805 "fsqrt %0,%1"
4806 [(set_attr "type" "dsqrt")])
4808 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4809 ;; fsel instruction and some auxiliary computations. Then we just have a
4810 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4811 ;; combine.
4812 (define_expand "maxsf3"
4813 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4814 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4815 (match_operand:SF 2 "gpc_reg_operand" ""))
4816 (match_dup 1)
4817 (match_dup 2)))]
4818 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4819 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4821 (define_expand "minsf3"
4822 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4823 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4824 (match_operand:SF 2 "gpc_reg_operand" ""))
4825 (match_dup 2)
4826 (match_dup 1)))]
4827 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4828 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4830 (define_split
4831 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4832 (match_operator:SF 3 "min_max_operator"
4833 [(match_operand:SF 1 "gpc_reg_operand" "")
4834 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4835 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4836 [(const_int 0)]
4837 "
4838 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4839 operands[1], operands[2]);
4840 DONE;
4841 }")
4843 (define_expand "movsfcc"
4844 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4845 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4846 (match_operand:SF 2 "gpc_reg_operand" "")
4847 (match_operand:SF 3 "gpc_reg_operand" "")))]
4848 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4849 "
4850 {
4851 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4852 DONE;
4853 else
4854 FAIL;
4855 }")
4857 (define_insn "*fselsfsf4"
4858 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4859 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4860 (match_operand:SF 4 "zero_fp_constant" "F"))
4861 (match_operand:SF 2 "gpc_reg_operand" "f")
4862 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4863 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4864 "fsel %0,%1,%2,%3"
4865 [(set_attr "type" "fp")])
4867 (define_insn "*fseldfsf4"
4868 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4869 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4870 (match_operand:DF 4 "zero_fp_constant" "F"))
4871 (match_operand:SF 2 "gpc_reg_operand" "f")
4872 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4874 "fsel %0,%1,%2,%3"
4875 [(set_attr "type" "fp")])
4877 (define_insn "negdf2"
4878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4879 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4880 "TARGET_HARD_FLOAT"
4881 "fneg %0,%1"
4882 [(set_attr "type" "fp")])
4884 (define_insn "absdf2"
4885 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4886 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4887 "TARGET_HARD_FLOAT"
4888 "fabs %0,%1"
4889 [(set_attr "type" "fp")])
4891 (define_insn ""
4892 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4893 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4894 "TARGET_HARD_FLOAT"
4895 "fnabs %0,%1"
4896 [(set_attr "type" "fp")])
4898 (define_insn "adddf3"
4899 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4900 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4901 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4902 "TARGET_HARD_FLOAT"
4903 "{fa|fadd} %0,%1,%2"
4904 [(set_attr "type" "fp")])
4906 (define_insn "subdf3"
4907 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4908 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4909 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4910 "TARGET_HARD_FLOAT"
4911 "{fs|fsub} %0,%1,%2"
4912 [(set_attr "type" "fp")])
4914 (define_insn "muldf3"
4915 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4916 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4917 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4918 "TARGET_HARD_FLOAT"
4919 "{fm|fmul} %0,%1,%2"
4920 [(set_attr "type" "dmul")])
4922 (define_insn "divdf3"
4923 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4924 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4925 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4926 "TARGET_HARD_FLOAT"
4927 "{fd|fdiv} %0,%1,%2"
4928 [(set_attr "type" "ddiv")])
4930 (define_insn ""
4931 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4932 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4933 (match_operand:DF 2 "gpc_reg_operand" "f"))
4934 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4935 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4936 "{fma|fmadd} %0,%1,%2,%3"
4937 [(set_attr "type" "dmul")])
4939 (define_insn ""
4940 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4941 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4942 (match_operand:DF 2 "gpc_reg_operand" "f"))
4943 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4944 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4945 "{fms|fmsub} %0,%1,%2,%3"
4946 [(set_attr "type" "dmul")])
4948 (define_insn ""
4949 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4950 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4951 (match_operand:DF 2 "gpc_reg_operand" "f"))
4952 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4953 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4954 "{fnma|fnmadd} %0,%1,%2,%3"
4955 [(set_attr "type" "dmul")])
4957 (define_insn ""
4958 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4959 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4960 (match_operand:DF 2 "gpc_reg_operand" "f"))
4961 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4962 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4963 "{fnms|fnmsub} %0,%1,%2,%3"
4964 [(set_attr "type" "dmul")])
4966 (define_insn "sqrtdf2"
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4968 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4969 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
4970 "fsqrt %0,%1"
4971 [(set_attr "type" "dsqrt")])
4973 ;; The conditional move instructions allow us to perform max and min
4974 ;; operations even when
4976 (define_expand "maxdf3"
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4978 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4979 (match_operand:DF 2 "gpc_reg_operand" ""))
4980 (match_dup 1)
4981 (match_dup 2)))]
4982 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4983 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4985 (define_expand "mindf3"
4986 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4987 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4988 (match_operand:DF 2 "gpc_reg_operand" ""))
4989 (match_dup 2)
4990 (match_dup 1)))]
4991 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4992 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4994 (define_split
4995 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4996 (match_operator:DF 3 "min_max_operator"
4997 [(match_operand:DF 1 "gpc_reg_operand" "")
4998 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4999 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5000 [(const_int 0)]
5001 "
5002 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5003 operands[1], operands[2]);
5004 DONE;
5005 }")
5007 (define_expand "movdfcc"
5008 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5009 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5010 (match_operand:DF 2 "gpc_reg_operand" "")
5011 (match_operand:DF 3 "gpc_reg_operand" "")))]
5012 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5013 "
5014 {
5015 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5016 DONE;
5017 else
5018 FAIL;
5019 }")
5021 (define_insn "*fseldfdf4"
5022 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5023 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5024 (match_operand:DF 4 "zero_fp_constant" "F"))
5025 (match_operand:DF 2 "gpc_reg_operand" "f")
5026 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5027 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5028 "fsel %0,%1,%2,%3"
5029 [(set_attr "type" "fp")])
5031 (define_insn "*fselsfdf4"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5033 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5034 (match_operand:SF 4 "zero_fp_constant" "F"))
5035 (match_operand:DF 2 "gpc_reg_operand" "f")
5036 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5037 "TARGET_PPC_GFXOPT"
5038 "fsel %0,%1,%2,%3"
5039 [(set_attr "type" "fp")])
5040 \f
5041 ;; Conversions to and from floating-point.
5043 ; For each of these conversions, there is a define_expand, a define_insn
5044 ; with a '#' template, and a define_split (with C code). The idea is
5045 ; to allow constant folding with the template of the define_insn,
5046 ; then to have the insns split later (between sched1 and final).
5048 (define_expand "floatsidf2"
5049 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5050 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5051 (use (match_dup 2))
5052 (use (match_dup 3))
5053 (clobber (match_dup 4))
5054 (clobber (match_dup 5))
5055 (clobber (match_dup 6))])]
5056 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5057 "
5058 {
5059 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5060 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
5061 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5062 operands[5] = gen_reg_rtx (DFmode);
5063 operands[6] = gen_reg_rtx (SImode);
5064 }")
5066 (define_insn "*floatsidf2_internal"
5067 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5068 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5069 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5070 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5071 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5072 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))
5073 (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))]
5074 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5075 "#"
5076 [(set_attr "length" "24")])
5078 (define_split
5079 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5080 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5081 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5082 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5083 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5084 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5085 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5086 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5087 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5088 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5089 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5090 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5091 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5092 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5093 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5094 "
5095 {
5096 rtx lowword, highword;
5097 if (GET_CODE (operands[4]) != MEM)
5098 abort();
5099 highword = XEXP (operands[4], 0);
5100 lowword = plus_constant (highword, 4);
5101 if (! WORDS_BIG_ENDIAN)
5102 {
5103 rtx tmp;
5104 tmp = highword; highword = lowword; lowword = tmp;
5105 }
5107 emit_insn (gen_xorsi3 (operands[6], operands[1],
5108 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5109 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5110 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5111 emit_move_insn (operands[5], operands[4]);
5112 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5113 DONE;
5114 }")
5116 (define_expand "floatunssidf2"
5117 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5118 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5119 (use (match_dup 2))
5120 (use (match_dup 3))
5121 (clobber (match_dup 4))
5122 (clobber (match_dup 5))])]
5123 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5124 "
5125 {
5126 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5127 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
5128 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5129 operands[5] = gen_reg_rtx (DFmode);
5130 }")
5132 (define_insn "*floatunssidf2_internal"
5133 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5134 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5135 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5136 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5137 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5138 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))]
5139 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5140 "#"
5141 [(set_attr "length" "20")])
5143 (define_split
5144 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5145 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5146 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5147 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5148 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5149 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5150 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5151 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5152 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5153 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5154 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5155 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5156 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5157 "
5158 {
5159 rtx lowword, highword;
5160 if (GET_CODE (operands[4]) != MEM)
5161 abort();
5162 highword = XEXP (operands[4], 0);
5163 lowword = plus_constant (highword, 4);
5164 if (! WORDS_BIG_ENDIAN)
5165 {
5166 rtx tmp;
5167 tmp = highword; highword = lowword; lowword = tmp;
5168 }
5170 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5171 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5172 emit_move_insn (operands[5], operands[4]);
5173 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5174 DONE;
5175 }")
5177 (define_expand "fix_truncdfsi2"
5178 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5179 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5180 (clobber (match_dup 2))
5181 (clobber (match_dup 3))])]
5182 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5183 "
5184 {
5185 operands[2] = gen_reg_rtx (DImode);
5186 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5187 }")
5189 (define_insn "*fix_truncdfsi2_internal"
5190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5191 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5192 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5193 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5194 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5195 "#"
5196 [(set_attr "length" "16")])
5198 (define_split
5199 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5200 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5201 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5202 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5203 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5204 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5205 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5206 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5207 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5208 "
5209 {
5210 rtx lowword;
5211 if (GET_CODE (operands[3]) != MEM)
5212 abort();
5213 lowword = XEXP (operands[3], 0);
5214 if (WORDS_BIG_ENDIAN)
5215 lowword = plus_constant (lowword, 4);
5217 emit_insn (gen_fctiwz (operands[2], operands[1]));
5218 emit_move_insn (operands[3], operands[2]);
5219 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5220 DONE;
5221 }")
5223 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5224 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5225 ; because the first makes it clear that operand 0 is not live
5226 ; before the instruction.
5227 (define_insn "fctiwz"
5228 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5229 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5230 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5231 "{fcirz|fctiwz} %0,%1"
5232 [(set_attr "type" "fp")])
5234 (define_insn "floatdidf2"
5235 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5236 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
5237 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5238 "fcfid %0,%1"
5239 [(set_attr "type" "fp")])
5241 (define_insn "fix_truncdfdi2"
5242 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5243 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5244 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5245 "fctidz %0,%1"
5246 [(set_attr "type" "fp")])
5247 \f
5248 ;; Define the DImode operations that can be done in a small number
5249 ;; of instructions. The & constraints are to prevent the register
5250 ;; allocator from allocating registers that overlap with the inputs
5251 ;; (for example, having an input in 7,8 and an output in 6,7). We
5252 ;; also allow for the output being the same as one of the inputs.
5254 (define_insn "*adddi3_noppc64"
5255 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5256 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5257 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5258 "! TARGET_POWERPC64"
5259 "*
5260 {
5261 if (WORDS_BIG_ENDIAN)
5262 return (GET_CODE (operands[2])) != CONST_INT
5263 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5264 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5265 else
5266 return (GET_CODE (operands[2])) != CONST_INT
5267 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5268 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5269 }"
5270 [(set_attr "length" "8")])
5272 (define_insn "*subdi3_noppc64"
5273 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5274 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5275 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5276 "! TARGET_POWERPC64"
5277 "*
5278 {
5279 if (WORDS_BIG_ENDIAN)
5280 return (GET_CODE (operands[1]) != CONST_INT)
5281 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5282 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5283 else
5284 return (GET_CODE (operands[1]) != CONST_INT)
5285 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5286 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5287 }"
5288 [(set_attr "length" "8")])
5290 (define_insn "*negdi2_noppc64"
5291 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5292 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5293 "! TARGET_POWERPC64"
5294 "*
5295 {
5296 return (WORDS_BIG_ENDIAN)
5297 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5298 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5299 }"
5300 [(set_attr "length" "8")])
5302 (define_expand "mulsidi3"
5303 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5304 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5305 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5306 "! TARGET_POWERPC64"
5307 "
5308 {
5309 if (! TARGET_POWER && ! TARGET_POWERPC)
5310 {
5311 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5312 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5313 emit_insn (gen_mull_call ());
5314 if (WORDS_BIG_ENDIAN)
5315 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5316 else
5317 {
5318 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5319 gen_rtx_REG (SImode, 3));
5320 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5321 gen_rtx_REG (SImode, 4));
5322 }
5323 DONE;
5324 }
5325 else if (TARGET_POWER)
5326 {
5327 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5328 DONE;
5329 }
5330 }")
5332 (define_insn "mulsidi3_mq"
5333 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5334 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5335 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5336 (clobber (match_scratch:SI 3 "=q"))]
5337 "TARGET_POWER"
5338 "mul %0,%1,%2\;mfmq %L0"
5339 [(set_attr "type" "imul")
5340 (set_attr "length" "8")])
5342 (define_insn "*mulsidi3_no_mq"
5343 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5344 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5345 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5346 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5347 "*
5348 {
5349 return (WORDS_BIG_ENDIAN)
5350 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5351 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5352 }"
5353 [(set_attr "type" "imul")
5354 (set_attr "length" "8")])
5356 (define_split
5357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5358 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5359 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5360 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5361 [(set (match_dup 3)
5362 (truncate:SI
5363 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5364 (sign_extend:DI (match_dup 2)))
5365 (const_int 32))))
5366 (set (match_dup 4)
5367 (mult:SI (match_dup 1)
5368 (match_dup 2)))]
5369 "
5370 {
5371 int endian = (WORDS_BIG_ENDIAN == 0);
5372 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5373 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5374 }")
5376 (define_expand "umulsidi3"
5377 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5378 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5379 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5380 "TARGET_POWERPC && ! TARGET_POWERPC64"
5381 "
5382 {
5383 if (TARGET_POWER)
5384 {
5385 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5386 DONE;
5387 }
5388 }")
5390 (define_insn "umulsidi3_mq"
5391 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5392 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5393 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5394 (clobber (match_scratch:SI 3 "=q"))]
5395 "TARGET_POWERPC && TARGET_POWER"
5396 "*
5397 {
5398 return (WORDS_BIG_ENDIAN)
5399 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5400 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5401 }"
5402 [(set_attr "type" "imul")
5403 (set_attr "length" "8")])
5405 (define_insn "*umulsidi3_no_mq"
5406 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5407 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5408 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5409 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5410 "*
5411 {
5412 return (WORDS_BIG_ENDIAN)
5413 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5414 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5415 }"
5416 [(set_attr "type" "imul")
5417 (set_attr "length" "8")])
5419 (define_split
5420 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5421 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5422 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5423 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5424 [(set (match_dup 3)
5425 (truncate:SI
5426 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5427 (zero_extend:DI (match_dup 2)))
5428 (const_int 32))))
5429 (set (match_dup 4)
5430 (mult:SI (match_dup 1)
5431 (match_dup 2)))]
5432 "
5433 {
5434 int endian = (WORDS_BIG_ENDIAN == 0);
5435 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5436 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5437 }")
5439 (define_expand "smulsi3_highpart"
5440 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5441 (truncate:SI
5442 (lshiftrt:DI (mult:DI (sign_extend:DI
5443 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5444 (sign_extend:DI
5445 (match_operand:SI 2 "gpc_reg_operand" "r")))
5446 (const_int 32))))]
5447 ""
5448 "
5449 {
5450 if (! TARGET_POWER && ! TARGET_POWERPC)
5451 {
5452 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5453 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5454 emit_insn (gen_mulh_call ());
5455 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5456 DONE;
5457 }
5458 else if (TARGET_POWER)
5459 {
5460 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5461 DONE;
5462 }
5463 }")
5465 (define_insn "smulsi3_highpart_mq"
5466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5467 (truncate:SI
5468 (lshiftrt:DI (mult:DI (sign_extend:DI
5469 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5470 (sign_extend:DI
5471 (match_operand:SI 2 "gpc_reg_operand" "r")))
5472 (const_int 32))))
5473 (clobber (match_scratch:SI 3 "=q"))]
5474 "TARGET_POWER"
5475 "mul %0,%1,%2"
5476 [(set_attr "type" "imul")])
5478 (define_insn "*smulsi3_highpart_no_mq"
5479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5480 (truncate:SI
5481 (lshiftrt:DI (mult:DI (sign_extend:DI
5482 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5483 (sign_extend:DI
5484 (match_operand:SI 2 "gpc_reg_operand" "r")))
5485 (const_int 32))))]
5486 "TARGET_POWERPC && ! TARGET_POWER"
5487 "mulhw %0,%1,%2"
5488 [(set_attr "type" "imul")])
5490 (define_expand "umulsi3_highpart"
5491 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5492 (truncate:SI
5493 (lshiftrt:DI (mult:DI (zero_extend:DI
5494 (match_operand:SI 1 "gpc_reg_operand" ""))
5495 (zero_extend:DI
5496 (match_operand:SI 2 "gpc_reg_operand" "")))
5497 (const_int 32))))]
5498 "TARGET_POWERPC"
5499 "
5500 {
5501 if (TARGET_POWER)
5502 {
5503 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5504 DONE;
5505 }
5506 }")
5508 (define_insn "umulsi3_highpart_mq"
5509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5510 (truncate:SI
5511 (lshiftrt:DI (mult:DI (zero_extend:DI
5512 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5513 (zero_extend:DI
5514 (match_operand:SI 2 "gpc_reg_operand" "r")))
5515 (const_int 32))))
5516 (clobber (match_scratch:SI 3 "=q"))]
5517 "TARGET_POWERPC && TARGET_POWER"
5518 "mulhwu %0,%1,%2"
5519 [(set_attr "type" "imul")])
5521 (define_insn "*umulsi3_highpart_no_mq"
5522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5523 (truncate:SI
5524 (lshiftrt:DI (mult:DI (zero_extend:DI
5525 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5526 (zero_extend:DI
5527 (match_operand:SI 2 "gpc_reg_operand" "r")))
5528 (const_int 32))))]
5529 "TARGET_POWERPC && ! TARGET_POWER"
5530 "mulhwu %0,%1,%2"
5531 [(set_attr "type" "imul")])
5533 ;; If operands 0 and 2 are in the same register, we have a problem. But
5534 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5535 ;; why we have the strange constraints below.
5536 (define_insn "ashldi3_power"
5537 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5538 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5539 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5540 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5541 "TARGET_POWER"
5542 "@
5543 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5544 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5545 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5546 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5547 [(set_attr "length" "8")])
5549 (define_insn "lshrdi3_power"
5550 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5551 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5552 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5553 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5554 "TARGET_POWER"
5555 "@
5556 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5557 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5558 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5559 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5560 [(set_attr "length" "8")])
5562 ;; Shift by a variable amount is too complex to be worth open-coding. We
5563 ;; just handle shifts by constants.
5564 (define_insn "ashrdi3_power"
5565 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5566 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5567 (match_operand:SI 2 "const_int_operand" "M,i")))
5568 (clobber (match_scratch:SI 3 "=X,q"))]
5569 "TARGET_POWER"
5570 "@
5571 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5572 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5573 [(set_attr "length" "8")])
5574 \f
5575 ;; PowerPC64 DImode operations.
5577 (define_expand "adddi3"
5578 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5579 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5580 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5581 ""
5582 "
5583 {
5584 if (! TARGET_POWERPC64)
5585 {
5586 if (non_short_cint_operand (operands[2], DImode))
5587 FAIL;
5588 }
5589 else
5590 if (GET_CODE (operands[2]) == CONST_INT
5591 && ! add_operand (operands[2], DImode))
5592 {
5593 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5594 ? operands[0] : gen_reg_rtx (DImode));
5596 HOST_WIDE_INT val = INTVAL (operands[2]);
5597 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
5598 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5600 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5601 FAIL;
5603 /* The ordering here is important for the prolog expander.
5604 When space is allocated from the stack, adding 'low' first may
5605 produce a temporary deallocation (which would be bad). */
5606 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5607 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5608 DONE;
5609 }
5610 }")
5612 ;; Discourage ai/addic because of carry but provide it in an alternative
5613 ;; allowing register zero as source.
5615 (define_insn "*adddi3_internal1"
5616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5617 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5618 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5619 "TARGET_POWERPC64"
5620 "@
5621 add %0,%1,%2
5622 addi %0,%1,%2
5623 addic %0,%1,%2
5624 addis %0,%1,%v2")
5626 (define_insn "*adddi3_internal2"
5627 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5628 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5629 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5630 (const_int 0)))
5631 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5632 "TARGET_POWERPC64"
5633 "@
5634 add. %3,%1,%2
5635 addic. %3,%1,%2
5636 #
5637 #"
5638 [(set_attr "type" "compare")
5639 (set_attr "length" "4,4,8,8")])
5641 (define_split
5642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5643 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5644 (match_operand:DI 2 "reg_or_short_operand" ""))
5645 (const_int 0)))
5646 (clobber (match_scratch:DI 3 ""))]
5647 "TARGET_POWERPC64 && reload_completed"
5648 [(set (match_dup 3)
5649 (plus:DI (match_dup 1) (match_dup 2)))
5650 (set (match_dup 0)
5651 (compare:CC (match_dup 3)
5652 (const_int 0)))]
5653 "")
5655 (define_insn "*adddi3_internal3"
5656 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5657 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5658 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5659 (const_int 0)))
5660 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5661 (plus:DI (match_dup 1) (match_dup 2)))]
5662 "TARGET_POWERPC64"
5663 "@
5664 add. %0,%1,%2
5665 addic. %0,%1,%2
5666 #
5667 #"
5668 [(set_attr "type" "compare")
5669 (set_attr "length" "4,4,8,8")])
5671 (define_split
5672 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5673 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5674 (match_operand:DI 2 "reg_or_short_operand" ""))
5675 (const_int 0)))
5676 (set (match_operand:DI 0 "gpc_reg_operand" "")
5677 (plus:DI (match_dup 1) (match_dup 2)))]
5678 "TARGET_POWERPC64 && reload_completed"
5679 [(set (match_dup 0)
5680 (plus:DI (match_dup 1) (match_dup 2)))
5681 (set (match_dup 3)
5682 (compare:CC (match_dup 0)
5683 (const_int 0)))]
5684 "")
5686 ;; Split an add that we can't do in one insn into two insns, each of which
5687 ;; does one 16-bit part. This is used by combine. Note that the low-order
5688 ;; add should be last in case the result gets used in an address.
5690 (define_split
5691 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5692 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5693 (match_operand:DI 2 "non_add_cint_operand" "")))]
5694 "TARGET_POWERPC64"
5695 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5696 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5697 "
5698 {
5699 HOST_WIDE_INT val = INTVAL (operands[2]);
5700 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
5701 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5703 operands[4] = GEN_INT (low);
5704 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5705 operands[3] = GEN_INT (rest);
5706 else if (! no_new_pseudos)
5707 {
5708 operands[3] = gen_reg_rtx (DImode);
5709 emit_move_insn (operands[3], operands[2]);
5710 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5711 DONE;
5712 }
5713 else
5714 FAIL;
5715 }")
5717 (define_insn "one_cmpldi2"
5718 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5719 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5720 "TARGET_POWERPC64"
5721 "nor %0,%1,%1")
5723 (define_insn ""
5724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5725 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5726 (const_int 0)))
5727 (clobber (match_scratch:DI 2 "=r,r"))]
5728 "TARGET_POWERPC64"
5729 "@
5730 nor. %2,%1,%1
5731 #"
5732 [(set_attr "type" "compare")
5733 (set_attr "length" "4,8")])
5735 (define_split
5736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5737 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5738 (const_int 0)))
5739 (clobber (match_scratch:DI 2 ""))]
5740 "TARGET_POWERPC64 && reload_completed"
5741 [(set (match_dup 2)
5742 (not:DI (match_dup 1)))
5743 (set (match_dup 0)
5744 (compare:CC (match_dup 2)
5745 (const_int 0)))]
5746 "")
5748 (define_insn ""
5749 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5750 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5751 (const_int 0)))
5752 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5753 (not:DI (match_dup 1)))]
5754 "TARGET_POWERPC64"
5755 "@
5756 nor. %0,%1,%1
5757 #"
5758 [(set_attr "type" "compare")
5759 (set_attr "length" "4,8")])
5761 (define_split
5762 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5763 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5764 (const_int 0)))
5765 (set (match_operand:DI 0 "gpc_reg_operand" "")
5766 (not:DI (match_dup 1)))]
5767 "TARGET_POWERPC64 && reload_completed"
5768 [(set (match_dup 0)
5769 (not:DI (match_dup 1)))
5770 (set (match_dup 2)
5771 (compare:CC (match_dup 0)
5772 (const_int 0)))]
5773 "")
5775 (define_insn ""
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5777 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5778 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5779 "TARGET_POWERPC64"
5780 "@
5781 subf %0,%2,%1
5782 subfic %0,%2,%1")
5784 (define_insn ""
5785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5786 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5787 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5788 (const_int 0)))
5789 (clobber (match_scratch:DI 3 "=r,r"))]
5790 "TARGET_POWERPC64"
5791 "@
5792 subf. %3,%2,%1
5793 #"
5794 [(set_attr "type" "compare")
5795 (set_attr "length" "4,8")])
5797 (define_split
5798 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5799 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5800 (match_operand:DI 2 "gpc_reg_operand" ""))
5801 (const_int 0)))
5802 (clobber (match_scratch:DI 3 ""))]
5803 "TARGET_POWERPC64 && reload_completed"
5804 [(set (match_dup 3)
5805 (minus:DI (match_dup 1) (match_dup 2)))
5806 (set (match_dup 0)
5807 (compare:CC (match_dup 3)
5808 (const_int 0)))]
5809 "")
5811 (define_insn ""
5812 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5813 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5814 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5815 (const_int 0)))
5816 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5817 (minus:DI (match_dup 1) (match_dup 2)))]
5818 "TARGET_POWERPC64"
5819 "@
5820 subf. %0,%2,%1
5821 #"
5822 [(set_attr "type" "compare")
5823 (set_attr "length" "4,8")])
5825 (define_split
5826 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5827 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5828 (match_operand:DI 2 "gpc_reg_operand" ""))
5829 (const_int 0)))
5830 (set (match_operand:DI 0 "gpc_reg_operand" "")
5831 (minus:DI (match_dup 1) (match_dup 2)))]
5832 "TARGET_POWERPC64 && reload_completed"
5833 [(set (match_dup 0)
5834 (minus:DI (match_dup 1) (match_dup 2)))
5835 (set (match_dup 3)
5836 (compare:CC (match_dup 0)
5837 (const_int 0)))]
5838 "")
5840 (define_expand "subdi3"
5841 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5842 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5843 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5844 ""
5845 "
5846 {
5847 if (GET_CODE (operands[2]) == CONST_INT)
5848 {
5849 emit_insn (gen_adddi3 (operands[0], operands[1],
5850 negate_rtx (DImode, operands[2])));
5851 DONE;
5852 }
5853 }")
5855 (define_insn "absdi2"
5856 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5857 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5858 (clobber (match_scratch:DI 2 "=&r,&r"))]
5859 "TARGET_POWERPC64"
5860 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
5861 [(set_attr "length" "12")])
5863 (define_split
5864 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5865 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
5866 (clobber (match_scratch:DI 2 ""))]
5867 "TARGET_POWERPC64 && reload_completed"
5868 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5869 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5870 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5871 "")
5873 (define_insn "*nabsdi2"
5874 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5875 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5876 (clobber (match_scratch:DI 2 "=&r,&r"))]
5877 "TARGET_POWERPC64"
5878 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
5879 [(set_attr "length" "12")])
5881 (define_split
5882 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5883 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))))
5884 (clobber (match_scratch:DI 2 ""))]
5885 "TARGET_POWERPC64 && reload_completed"
5886 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5887 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5888 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5889 "")
5891 (define_expand "negdi2"
5892 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5893 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5894 ""
5895 "")
5897 (define_insn ""
5898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5899 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5900 "TARGET_POWERPC64"
5901 "neg %0,%1")
5903 (define_insn ""
5904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5905 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5906 (const_int 0)))
5907 (clobber (match_scratch:DI 2 "=r,r"))]
5908 "TARGET_POWERPC64"
5909 "@
5910 neg. %2,%1
5911 #"
5912 [(set_attr "type" "compare")
5913 (set_attr "length" "4,8")])
5915 (define_split
5916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5917 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5918 (const_int 0)))
5919 (clobber (match_scratch:DI 2 ""))]
5920 "TARGET_POWERPC64 && reload_completed"
5921 [(set (match_dup 2)
5922 (neg:DI (match_dup 1)))
5923 (set (match_dup 0)
5924 (compare:CC (match_dup 2)
5925 (const_int 0)))]
5926 "")
5928 (define_insn ""
5929 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5930 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5931 (const_int 0)))
5932 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5933 (neg:DI (match_dup 1)))]
5934 "TARGET_POWERPC64"
5935 "@
5936 neg. %0,%1
5937 #"
5938 [(set_attr "type" "compare")
5939 (set_attr "length" "4,8")])
5941 (define_split
5942 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5943 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5944 (const_int 0)))
5945 (set (match_operand:DI 0 "gpc_reg_operand" "")
5946 (neg:DI (match_dup 1)))]
5947 "TARGET_POWERPC64 && reload_completed"
5948 [(set (match_dup 0)
5949 (neg:DI (match_dup 1)))
5950 (set (match_dup 2)
5951 (compare:CC (match_dup 0)
5952 (const_int 0)))]
5953 "")
5955 (define_insn "ffsdi2"
5956 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5957 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5958 "TARGET_POWERPC64"
5959 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
5960 [(set_attr "length" "16")])
5962 (define_insn "muldi3"
5963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5964 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5965 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5966 "TARGET_POWERPC64"
5967 "mulld %0,%1,%2"
5968 [(set_attr "type" "lmul")])
5970 (define_insn "smuldi3_highpart"
5971 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5972 (truncate:DI
5973 (lshiftrt:TI (mult:TI (sign_extend:TI
5974 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5975 (sign_extend:TI
5976 (match_operand:DI 2 "gpc_reg_operand" "r")))
5977 (const_int 64))))]
5978 "TARGET_POWERPC64"
5979 "mulhd %0,%1,%2"
5980 [(set_attr "type" "lmul")])
5982 (define_insn "umuldi3_highpart"
5983 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5984 (truncate:DI
5985 (lshiftrt:TI (mult:TI (zero_extend:TI
5986 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5987 (zero_extend:TI
5988 (match_operand:DI 2 "gpc_reg_operand" "r")))
5989 (const_int 64))))]
5990 "TARGET_POWERPC64"
5991 "mulhdu %0,%1,%2"
5992 [(set_attr "type" "lmul")])
5994 (define_expand "divdi3"
5995 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5996 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
5997 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5998 "TARGET_POWERPC64"
5999 "
6000 {
6001 if (GET_CODE (operands[2]) == CONST_INT
6002 && INTVAL (operands[2]) > 0
6003 && exact_log2 (INTVAL (operands[2])) >= 0)
6004 ;
6005 else
6006 operands[2] = force_reg (DImode, operands[2]);
6007 }")
6009 (define_expand "moddi3"
6010 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6011 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6012 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6013 "TARGET_POWERPC64"
6014 "
6015 {
6016 int i;
6017 rtx temp1;
6018 rtx temp2;
6020 if (GET_CODE (operands[2]) != CONST_INT
6021 || INTVAL (operands[2]) <= 0
6022 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6023 FAIL;
6025 temp1 = gen_reg_rtx (DImode);
6026 temp2 = gen_reg_rtx (DImode);
6028 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6029 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6030 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6031 DONE;
6032 }")
6034 (define_insn ""
6035 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6036 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6037 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6038 "TARGET_POWERPC64"
6039 "sradi %0,%1,%p2\;addze %0,%0"
6040 [(set_attr "length" "8")])
6042 (define_insn ""
6043 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6044 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6045 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6046 (const_int 0)))
6047 (clobber (match_scratch:DI 3 "=r,r"))]
6048 "TARGET_POWERPC64"
6049 "@
6050 sradi %3,%1,%p2\;addze. %3,%3
6051 #"
6052 [(set_attr "type" "compare")
6053 (set_attr "length" "8,12")])
6055 (define_split
6056 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6057 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6058 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6059 (const_int 0)))
6060 (clobber (match_scratch:DI 3 ""))]
6061 "TARGET_POWERPC64 && reload_completed"
6062 [(set (match_dup 3)
6063 (div:DI (match_dup 1) (match_dup 2)))
6064 (set (match_dup 0)
6065 (compare:CC (match_dup 3)
6066 (const_int 0)))]
6067 "")
6069 (define_insn ""
6070 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6071 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6072 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6073 (const_int 0)))
6074 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6075 (div:DI (match_dup 1) (match_dup 2)))]
6076 "TARGET_POWERPC64"
6077 "@
6078 sradi %0,%1,%p2\;addze. %0,%0
6079 #"
6080 [(set_attr "type" "compare")
6081 (set_attr "length" "8,12")])
6083 (define_split
6084 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6085 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6086 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6087 (const_int 0)))
6088 (set (match_operand:DI 0 "gpc_reg_operand" "")
6089 (div:DI (match_dup 1) (match_dup 2)))]
6090 "TARGET_POWERPC64 && reload_completed"
6091 [(set (match_dup 0)
6092 (div:DI (match_dup 1) (match_dup 2)))
6093 (set (match_dup 3)
6094 (compare:CC (match_dup 0)
6095 (const_int 0)))]
6096 "")
6098 (define_insn ""
6099 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6100 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6101 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6102 "TARGET_POWERPC64"
6103 "divd %0,%1,%2"
6104 [(set_attr "type" "ldiv")])
6106 (define_insn "udivdi3"
6107 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6108 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6109 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6110 "TARGET_POWERPC64"
6111 "divdu %0,%1,%2"
6112 [(set_attr "type" "ldiv")])
6114 (define_insn "rotldi3"
6115 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6116 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6117 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6118 "TARGET_POWERPC64"
6119 "rld%I2cl %0,%1,%H2,0")
6121 (define_insn "*rotldi3_internal2"
6122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6123 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6124 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6125 (const_int 0)))
6126 (clobber (match_scratch:DI 3 "=r,r"))]
6127 "TARGET_POWERPC64"
6128 "@
6129 rld%I2cl. %3,%1,%H2,0
6130 #"
6131 [(set_attr "type" "delayed_compare")
6132 (set_attr "length" "4,8")])
6134 (define_split
6135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6136 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6137 (match_operand:DI 2 "reg_or_cint_operand" ""))
6138 (const_int 0)))
6139 (clobber (match_scratch:DI 3 ""))]
6140 "TARGET_POWERPC64 && reload_completed"
6141 [(set (match_dup 3)
6142 (rotate:DI (match_dup 1) (match_dup 2)))
6143 (set (match_dup 0)
6144 (compare:CC (match_dup 3)
6145 (const_int 0)))]
6146 "")
6148 (define_insn "*rotldi3_internal3"
6149 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6150 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6151 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6152 (const_int 0)))
6153 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6154 (rotate:DI (match_dup 1) (match_dup 2)))]
6155 "TARGET_POWERPC64"
6156 "@
6157 rld%I2cl. %0,%1,%H2,0
6158 #"
6159 [(set_attr "type" "delayed_compare")
6160 (set_attr "length" "4,8")])
6162 (define_split
6163 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6164 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6165 (match_operand:DI 2 "reg_or_cint_operand" ""))
6166 (const_int 0)))
6167 (set (match_operand:DI 0 "gpc_reg_operand" "")
6168 (rotate:DI (match_dup 1) (match_dup 2)))]
6169 "TARGET_POWERPC64 && reload_completed"
6170 [(set (match_dup 0)
6171 (rotate:DI (match_dup 1) (match_dup 2)))
6172 (set (match_dup 3)
6173 (compare:CC (match_dup 0)
6174 (const_int 0)))]
6175 "")
6177 (define_insn "*rotldi3_internal4"
6178 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6179 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6180 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6181 (match_operand:DI 3 "mask64_operand" "S")))]
6182 "TARGET_POWERPC64"
6183 "rld%I2c%B3 %0,%1,%H2,%S3")
6185 (define_insn "*rotldi3_internal5"
6186 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6187 (compare:CC (and:DI
6188 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6189 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6190 (match_operand:DI 3 "mask64_operand" "S,S"))
6191 (const_int 0)))
6192 (clobber (match_scratch:DI 4 "=r,r"))]
6193 "TARGET_POWERPC64"
6194 "@
6195 rld%I2c%B3. %4,%1,%H2,%S3
6196 #"
6197 [(set_attr "type" "delayed_compare")
6198 (set_attr "length" "4,8")])
6200 (define_split
6201 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6202 (compare:CC (and:DI
6203 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6204 (match_operand:DI 2 "reg_or_cint_operand" ""))
6205 (match_operand:DI 3 "mask64_operand" ""))
6206 (const_int 0)))
6207 (clobber (match_scratch:DI 4 ""))]
6208 "TARGET_POWERPC64 && reload_completed"
6209 [(set (match_dup 4)
6210 (and:DI (rotate:DI (match_dup 1)
6211 (match_dup 2))
6212 (match_dup 3)))
6213 (set (match_dup 0)
6214 (compare:CC (match_dup 4)
6215 (const_int 0)))]
6216 "")
6218 (define_insn "*rotldi3_internal6"
6219 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6220 (compare:CC (and:DI
6221 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6222 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6223 (match_operand:DI 3 "mask64_operand" "S,S"))
6224 (const_int 0)))
6225 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6226 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6227 "TARGET_POWERPC64"
6228 "@
6229 rld%I2c%B3. %0,%1,%H2,%S3
6230 #"
6231 [(set_attr "type" "delayed_compare")
6232 (set_attr "length" "4,8")])
6234 (define_split
6235 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6236 (compare:CC (and:DI
6237 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6238 (match_operand:DI 2 "reg_or_cint_operand" ""))
6239 (match_operand:DI 3 "mask64_operand" ""))
6240 (const_int 0)))
6241 (set (match_operand:DI 0 "gpc_reg_operand" "")
6242 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6243 "TARGET_POWERPC64 && reload_completed"
6244 [(set (match_dup 0)
6245 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6246 (set (match_dup 4)
6247 (compare:CC (match_dup 0)
6248 (const_int 0)))]
6249 "")
6251 (define_insn "*rotldi3_internal7"
6252 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6253 (zero_extend:DI
6254 (subreg:QI
6255 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6256 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6257 "TARGET_POWERPC64"
6258 "rld%I2cl %0,%1,%H2,56")
6260 (define_insn "*rotldi3_internal8"
6261 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6262 (compare:CC (zero_extend:DI
6263 (subreg:QI
6264 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6265 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6266 (const_int 0)))
6267 (clobber (match_scratch:DI 3 "=r,r"))]
6268 "TARGET_POWERPC64"
6269 "@
6270 rld%I2cl. %3,%1,%H2,56
6271 #"
6272 [(set_attr "type" "delayed_compare")
6273 (set_attr "length" "4,8")])
6275 (define_split
6276 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6277 (compare:CC (zero_extend:DI
6278 (subreg:QI
6279 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6280 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6281 (const_int 0)))
6282 (clobber (match_scratch:DI 3 ""))]
6283 "TARGET_POWERPC64 && reload_completed"
6284 [(set (match_dup 3)
6285 (zero_extend:DI (subreg:QI
6286 (rotate:DI (match_dup 1)
6287 (match_dup 2)) 0)))
6288 (set (match_dup 0)
6289 (compare:CC (match_dup 3)
6290 (const_int 0)))]
6291 "")
6293 (define_insn "*rotldi3_internal9"
6294 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6295 (compare:CC (zero_extend:DI
6296 (subreg:QI
6297 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6298 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6299 (const_int 0)))
6300 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6301 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6302 "TARGET_POWERPC64"
6303 "@
6304 rld%I2cl. %0,%1,%H2,56
6305 #"
6306 [(set_attr "type" "delayed_compare")
6307 (set_attr "length" "4,8")])
6309 (define_split
6310 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6311 (compare:CC (zero_extend:DI
6312 (subreg:QI
6313 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6314 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6315 (const_int 0)))
6316 (set (match_operand:DI 0 "gpc_reg_operand" "")
6317 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6318 "TARGET_POWERPC64 && reload_completed"
6319 [(set (match_dup 0)
6320 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6321 (set (match_dup 3)
6322 (compare:CC (match_dup 0)
6323 (const_int 0)))]
6324 "")
6326 (define_insn "*rotldi3_internal10"
6327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6328 (zero_extend:DI
6329 (subreg:HI
6330 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6331 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6332 "TARGET_POWERPC64"
6333 "rld%I2cl %0,%1,%H2,48")
6335 (define_insn "*rotldi3_internal11"
6336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6337 (compare:CC (zero_extend:DI
6338 (subreg:HI
6339 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6340 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6341 (const_int 0)))
6342 (clobber (match_scratch:DI 3 "=r,r"))]
6343 "TARGET_POWERPC64"
6344 "@
6345 rld%I2cl. %3,%1,%H2,48
6346 #"
6347 [(set_attr "type" "delayed_compare")
6348 (set_attr "length" "4,8")])
6350 (define_split
6351 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6352 (compare:CC (zero_extend:DI
6353 (subreg:HI
6354 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6355 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6356 (const_int 0)))
6357 (clobber (match_scratch:DI 3 ""))]
6358 "TARGET_POWERPC64 && reload_completed"
6359 [(set (match_dup 3)
6360 (zero_extend:DI (subreg:HI
6361 (rotate:DI (match_dup 1)
6362 (match_dup 2)) 0)))
6363 (set (match_dup 0)
6364 (compare:CC (match_dup 3)
6365 (const_int 0)))]
6366 "")
6368 (define_insn "*rotldi3_internal12"
6369 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6370 (compare:CC (zero_extend:DI
6371 (subreg:HI
6372 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6373 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6374 (const_int 0)))
6375 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6376 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6377 "TARGET_POWERPC64"
6378 "@
6379 rld%I2cl. %0,%1,%H2,48
6380 #"
6381 [(set_attr "type" "delayed_compare")
6382 (set_attr "length" "4,8")])
6384 (define_split
6385 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6386 (compare:CC (zero_extend:DI
6387 (subreg:HI
6388 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6389 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6390 (const_int 0)))
6391 (set (match_operand:DI 0 "gpc_reg_operand" "")
6392 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6393 "TARGET_POWERPC64 && reload_completed"
6394 [(set (match_dup 0)
6395 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6396 (set (match_dup 3)
6397 (compare:CC (match_dup 0)
6398 (const_int 0)))]
6399 "")
6401 (define_insn "*rotldi3_internal13"
6402 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6403 (zero_extend:DI
6404 (subreg:SI
6405 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6406 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6407 "TARGET_POWERPC64"
6408 "rld%I2cl %0,%1,%H2,32")
6410 (define_insn "*rotldi3_internal14"
6411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6412 (compare:CC (zero_extend:DI
6413 (subreg:SI
6414 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6415 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6416 (const_int 0)))
6417 (clobber (match_scratch:DI 3 "=r,r"))]
6418 "TARGET_POWERPC64"
6419 "@
6420 rld%I2cl. %3,%1,%H2,32
6421 #"
6422 [(set_attr "type" "delayed_compare")
6423 (set_attr "length" "4,8")])
6425 (define_split
6426 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6427 (compare:CC (zero_extend:DI
6428 (subreg:SI
6429 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6430 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6431 (const_int 0)))
6432 (clobber (match_scratch:DI 3 ""))]
6433 "TARGET_POWERPC64 && reload_completed"
6434 [(set (match_dup 3)
6435 (zero_extend:DI (subreg:SI
6436 (rotate:DI (match_dup 1)
6437 (match_dup 2)) 0)))
6438 (set (match_dup 0)
6439 (compare:CC (match_dup 3)
6440 (const_int 0)))]
6441 "")
6443 (define_insn "*rotldi3_internal15"
6444 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6445 (compare:CC (zero_extend:DI
6446 (subreg:SI
6447 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6448 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6449 (const_int 0)))
6450 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6451 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6452 "TARGET_POWERPC64"
6453 "@
6454 rld%I2cl. %0,%1,%H2,32
6455 #"
6456 [(set_attr "type" "delayed_compare")
6457 (set_attr "length" "4,8")])
6459 (define_split
6460 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6461 (compare:CC (zero_extend:DI
6462 (subreg:SI
6463 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6464 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6465 (const_int 0)))
6466 (set (match_operand:DI 0 "gpc_reg_operand" "")
6467 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6468 "TARGET_POWERPC64 && reload_completed"
6469 [(set (match_dup 0)
6470 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6471 (set (match_dup 3)
6472 (compare:CC (match_dup 0)
6473 (const_int 0)))]
6474 "")
6476 (define_expand "ashldi3"
6477 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6478 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6479 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6480 "TARGET_POWERPC64 || TARGET_POWER"
6481 "
6482 {
6483 if (TARGET_POWERPC64)
6484 ;
6485 else if (TARGET_POWER)
6486 {
6487 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6488 DONE;
6489 }
6490 else
6491 FAIL;
6492 }")
6494 (define_insn "*ashldi3_internal1"
6495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6496 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6497 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6498 "TARGET_POWERPC64"
6499 "sld%I2 %0,%1,%H2"
6500 [(set_attr "length" "8")])
6502 (define_insn "*ashldi3_internal2"
6503 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6504 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6505 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6506 (const_int 0)))
6507 (clobber (match_scratch:DI 3 "=r,r"))]
6508 "TARGET_POWERPC64"
6509 "@
6510 sld%I2. %3,%1,%H2
6511 #"
6512 [(set_attr "type" "delayed_compare")
6513 (set_attr "length" "4,8")])
6515 (define_split
6516 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6517 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6518 (match_operand:SI 2 "reg_or_cint_operand" ""))
6519 (const_int 0)))
6520 (clobber (match_scratch:DI 3 ""))]
6521 "TARGET_POWERPC64 && reload_completed"
6522 [(set (match_dup 3)
6523 (ashift:DI (match_dup 1) (match_dup 2)))
6524 (set (match_dup 0)
6525 (compare:CC (match_dup 3)
6526 (const_int 0)))]
6527 "")
6529 (define_insn "*ashldi3_internal3"
6530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6531 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6532 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6533 (const_int 0)))
6534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6535 (ashift:DI (match_dup 1) (match_dup 2)))]
6536 "TARGET_POWERPC64"
6537 "@
6538 sld%I2. %0,%1,%H2
6539 #"
6540 [(set_attr "type" "delayed_compare")
6541 (set_attr "length" "4,8")])
6543 (define_split
6544 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6545 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6546 (match_operand:SI 2 "reg_or_cint_operand" ""))
6547 (const_int 0)))
6548 (set (match_operand:DI 0 "gpc_reg_operand" "")
6549 (ashift:DI (match_dup 1) (match_dup 2)))]
6550 "TARGET_POWERPC64 && reload_completed"
6551 [(set (match_dup 0)
6552 (ashift:DI (match_dup 1) (match_dup 2)))
6553 (set (match_dup 3)
6554 (compare:CC (match_dup 0)
6555 (const_int 0)))]
6556 "")
6558 (define_insn "*ashldi3_internal4"
6559 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6560 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6561 (match_operand:SI 2 "const_int_operand" "i"))
6562 (match_operand:DI 3 "const_int_operand" "n")))]
6563 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6564 "rldic %0,%1,%H2,%W3")
6566 (define_insn "ashldi3_internal5"
6567 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6568 (compare:CC
6569 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6570 (match_operand:SI 2 "const_int_operand" "i,i"))
6571 (match_operand:DI 3 "const_int_operand" "n,n"))
6572 (const_int 0)))
6573 (clobber (match_scratch:DI 4 "=r,r"))]
6574 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6575 "@
6576 rldic. %4,%1,%H2,%W3
6577 #"
6578 [(set_attr "type" "delayed_compare")
6579 (set_attr "length" "4,8")])
6581 (define_split
6582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6583 (compare:CC
6584 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6585 (match_operand:SI 2 "const_int_operand" ""))
6586 (match_operand:DI 3 "const_int_operand" ""))
6587 (const_int 0)))
6588 (clobber (match_scratch:DI 4 ""))]
6589 "TARGET_POWERPC64 && reload_completed
6590 && includes_rldic_lshift_p (operands[2], operands[3])"
6591 [(set (match_dup 4)
6592 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6593 (match_dup 3)))
6594 (set (match_dup 0)
6595 (compare:CC (match_dup 4)
6596 (const_int 0)))]
6597 "")
6599 (define_insn "*ashldi3_internal6"
6600 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6601 (compare:CC
6602 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6603 (match_operand:SI 2 "const_int_operand" "i,i"))
6604 (match_operand:DI 3 "const_int_operand" "n,n"))
6605 (const_int 0)))
6606 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6607 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6608 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6609 "@
6610 rldic. %0,%1,%H2,%W3
6611 #"
6612 [(set_attr "type" "delayed_compare")
6613 (set_attr "length" "4,8")])
6615 (define_split
6616 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6617 (compare:CC
6618 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6619 (match_operand:SI 2 "const_int_operand" ""))
6620 (match_operand:DI 3 "const_int_operand" ""))
6621 (const_int 0)))
6622 (set (match_operand:DI 0 "gpc_reg_operand" "")
6623 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6624 "TARGET_POWERPC64 && reload_completed
6625 && includes_rldic_lshift_p (operands[2], operands[3])"
6626 [(set (match_dup 0)
6627 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6628 (match_dup 3)))
6629 (set (match_dup 4)
6630 (compare:CC (match_dup 0)
6631 (const_int 0)))]
6632 "")
6634 (define_insn "*ashldi3_internal7"
6635 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6636 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6637 (match_operand:SI 2 "const_int_operand" "i"))
6638 (match_operand:DI 3 "mask64_operand" "S")))]
6639 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6640 "rldicr %0,%1,%H2,%S3")
6642 (define_insn "ashldi3_internal8"
6643 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6644 (compare:CC
6645 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6646 (match_operand:SI 2 "const_int_operand" "i,i"))
6647 (match_operand:DI 3 "mask64_operand" "S,S"))
6648 (const_int 0)))
6649 (clobber (match_scratch:DI 4 "=r,r"))]
6650 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6651 "@
6652 rldicr. %4,%1,%H2,%S3
6653 #"
6654 [(set_attr "type" "delayed_compare")
6655 (set_attr "length" "4,8")])
6657 (define_split
6658 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6659 (compare:CC
6660 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6661 (match_operand:SI 2 "const_int_operand" ""))
6662 (match_operand:DI 3 "mask64_operand" ""))
6663 (const_int 0)))
6664 (clobber (match_scratch:DI 4 ""))]
6665 "TARGET_POWERPC64 && reload_completed
6666 && includes_rldicr_lshift_p (operands[2], operands[3])"
6667 [(set (match_dup 4)
6668 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6669 (match_dup 3)))
6670 (set (match_dup 0)
6671 (compare:CC (match_dup 4)
6672 (const_int 0)))]
6673 "")
6675 (define_insn "*ashldi3_internal9"
6676 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6677 (compare:CC
6678 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6679 (match_operand:SI 2 "const_int_operand" "i,i"))
6680 (match_operand:DI 3 "mask64_operand" "S,S"))
6681 (const_int 0)))
6682 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6683 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6684 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6685 "@
6686 rldicr. %0,%1,%H2,%S3
6687 #"
6688 [(set_attr "type" "delayed_compare")
6689 (set_attr "length" "4,8")])
6691 (define_split
6692 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6693 (compare:CC
6694 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6695 (match_operand:SI 2 "const_int_operand" ""))
6696 (match_operand:DI 3 "mask64_operand" ""))
6697 (const_int 0)))
6698 (set (match_operand:DI 0 "gpc_reg_operand" "")
6699 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6700 "TARGET_POWERPC64 && reload_completed
6701 && includes_rldicr_lshift_p (operands[2], operands[3])"
6702 [(set (match_dup 0)
6703 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6704 (match_dup 3)))
6705 (set (match_dup 4)
6706 (compare:CC (match_dup 0)
6707 (const_int 0)))]
6708 "")
6710 (define_expand "lshrdi3"
6711 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6712 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6713 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6714 "TARGET_POWERPC64 || TARGET_POWER"
6715 "
6716 {
6717 if (TARGET_POWERPC64)
6718 ;
6719 else if (TARGET_POWER)
6720 {
6721 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6722 DONE;
6723 }
6724 else
6725 FAIL;
6726 }")
6728 (define_insn "*lshrdi3_internal1"
6729 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6730 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6731 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6732 "TARGET_POWERPC64"
6733 "srd%I2 %0,%1,%H2")
6735 (define_insn "*lshrdi3_internal2"
6736 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6737 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6738 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6739 (const_int 0)))
6740 (clobber (match_scratch:DI 3 "=r,r"))]
6741 "TARGET_POWERPC64"
6742 "@
6743 srd%I2. %3,%1,%H2
6744 #"
6745 [(set_attr "type" "delayed_compare")
6746 (set_attr "length" "4,8")])
6748 (define_split
6749 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6750 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6751 (match_operand:SI 2 "reg_or_cint_operand" ""))
6752 (const_int 0)))
6753 (clobber (match_scratch:DI 3 ""))]
6754 "TARGET_POWERPC64 && reload_completed"
6755 [(set (match_dup 3)
6756 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6757 (set (match_dup 0)
6758 (compare:CC (match_dup 3)
6759 (const_int 0)))]
6760 "")
6762 (define_insn "*lshrdi3_internal3"
6763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6764 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6765 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6766 (const_int 0)))
6767 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6768 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6769 "TARGET_POWERPC64"
6770 "@
6771 srd%I2. %0,%1,%H2
6772 #"
6773 [(set_attr "type" "delayed_compare")
6774 (set_attr "length" "4,8")])
6776 (define_split
6777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6778 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6779 (match_operand:SI 2 "reg_or_cint_operand" ""))
6780 (const_int 0)))
6781 (set (match_operand:DI 0 "gpc_reg_operand" "")
6782 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6783 "TARGET_POWERPC64 && reload_completed"
6784 [(set (match_dup 0)
6785 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6786 (set (match_dup 3)
6787 (compare:CC (match_dup 0)
6788 (const_int 0)))]
6789 "")
6791 (define_expand "ashrdi3"
6792 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6793 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6794 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6795 "TARGET_POWERPC64 || TARGET_POWER"
6796 "
6797 {
6798 if (TARGET_POWERPC64)
6799 ;
6800 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6801 {
6802 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6803 DONE;
6804 }
6805 else
6806 FAIL;
6807 }")
6809 (define_insn "*ashrdi3_internal1"
6810 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6811 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6812 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6813 "TARGET_POWERPC64"
6814 "srad%I2 %0,%1,%H2")
6816 (define_insn "*ashrdi3_internal2"
6817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6818 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6819 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6820 (const_int 0)))
6821 (clobber (match_scratch:DI 3 "=r,r"))]
6822 "TARGET_POWERPC64"
6823 "@
6824 srad%I2. %3,%1,%H2
6825 #"
6826 [(set_attr "type" "delayed_compare")
6827 (set_attr "length" "4,8")])
6829 (define_split
6830 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6831 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6832 (match_operand:SI 2 "reg_or_cint_operand" ""))
6833 (const_int 0)))
6834 (clobber (match_scratch:DI 3 ""))]
6835 "TARGET_POWERPC64 && reload_completed"
6836 [(set (match_dup 3)
6837 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6838 (set (match_dup 0)
6839 (compare:CC (match_dup 3)
6840 (const_int 0)))]
6841 "")
6843 (define_insn "*ashrdi3_internal3"
6844 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6845 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6846 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6847 (const_int 0)))
6848 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6849 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6850 "TARGET_POWERPC64"
6851 "@
6852 srad%I2. %0,%1,%H2
6853 #"
6854 [(set_attr "type" "delayed_compare")
6855 (set_attr "length" "4,8")])
6857 (define_split
6858 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6859 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6860 (match_operand:SI 2 "reg_or_cint_operand" ""))
6861 (const_int 0)))
6862 (set (match_operand:DI 0 "gpc_reg_operand" "")
6863 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6864 "TARGET_POWERPC64 && reload_completed"
6865 [(set (match_dup 0)
6866 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6867 (set (match_dup 3)
6868 (compare:CC (match_dup 0)
6869 (const_int 0)))]
6870 "")
6872 (define_insn "anddi3"
6873 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6874 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6875 (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
6876 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
6877 "TARGET_POWERPC64"
6878 "@
6879 and %0,%1,%2
6880 rldic%B2 %0,%1,0,%S2
6881 andi. %0,%1,%b2
6882 andis. %0,%1,%u2")
6884 (define_insn "*anddi3_internal2"
6885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
6886 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,")
6887 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r"))
6890 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
6891 "TARGET_POWERPC64"
6892 "@
6893 and. %3,%1,%2
6894 rldic%B2. %3,%1,0,%S2
6895 andi. %3,%1,%b2
6896 andis. %3,%1,%u2
6897 #
6898 #
6899 #
6900 #"
6901 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
6902 (set_attr "length" "4,4,4,4,8,8,8,8")])
6904 (define_split
6905 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6906 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6907 (match_operand:DI 2 "and64_operand" ""))
6908 (const_int 0)))
6909 (clobber (match_scratch:DI 3 ""))
6910 (clobber (match_scratch:CC 4 ""))]
6911 "TARGET_POWERPC64 && reload_completed"
6912 [(parallel [(set (match_dup 3)
6913 (and:DI (match_dup 1)
6914 (match_dup 2)))
6915 (clobber (match_dup 4))])
6916 (set (match_dup 0)
6917 (compare:CC (match_dup 3)
6918 (const_int 0)))]
6919 "")
6921 (define_insn "*anddi3_internal3"
6922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
6923 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
6924 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
6925 (const_int 0)))
6926 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
6927 (and:DI (match_dup 1) (match_dup 2)))
6928 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
6929 "TARGET_POWERPC64"
6930 "@
6931 and. %0,%1,%2
6932 rldic%B2. %0,%1,0,%S2
6933 andi. %0,%1,%b2
6934 andis. %0,%1,%u2
6935 #
6936 #
6937 #
6938 #"
6939 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
6940 (set_attr "length" "4,4,4,4,8,8,8,8")])
6942 (define_split
6943 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6944 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6945 (match_operand:DI 2 "and64_operand" ""))
6946 (const_int 0)))
6947 (set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (and:DI (match_dup 1) (match_dup 2)))
6949 (clobber (match_scratch:CC 4 ""))]
6950 "TARGET_POWERPC64 && reload_completed"
6951 [(parallel [(set (match_dup 0)
6952 (and:DI (match_dup 1) (match_dup 2)))
6953 (clobber (match_dup 4))])
6954 (set (match_dup 3)
6955 (compare:CC (match_dup 0)
6956 (const_int 0)))]
6957 "")
6959 (define_expand "iordi3"
6960 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6961 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6962 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6963 "TARGET_POWERPC64"
6964 "
6965 {
6966 if (non_logical_cint_operand (operands[2], DImode))
6967 {
6968 HOST_WIDE_INT value;
6969 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6970 ? operands[0] : gen_reg_rtx (DImode));
6972 if (GET_CODE (operands[2]) == CONST_INT)
6973 {
6974 value = INTVAL (operands[2]);
6975 emit_insn (gen_iordi3 (tmp, operands[1],
6976 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6977 }
6978 else
6979 {
6980 value = CONST_DOUBLE_LOW (operands[2]);
6981 emit_insn (gen_iordi3 (tmp, operands[1],
6982 immed_double_const (value
6983 & (~ (HOST_WIDE_INT) 0xffff),
6984 0, DImode)));
6985 }
6987 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6988 DONE;
6989 }
6990 }")
6992 (define_expand "xordi3"
6993 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6994 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6995 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6996 "TARGET_POWERPC64"
6997 "
6998 {
6999 if (non_logical_cint_operand (operands[2], DImode))
7000 {
7001 HOST_WIDE_INT value;
7002 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7003 ? operands[0] : gen_reg_rtx (DImode));
7005 if (GET_CODE (operands[2]) == CONST_INT)
7006 {
7007 value = INTVAL (operands[2]);
7008 emit_insn (gen_xordi3 (tmp, operands[1],
7009 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7010 }
7011 else
7012 {
7013 value = CONST_DOUBLE_LOW (operands[2]);
7014 emit_insn (gen_xordi3 (tmp, operands[1],
7015 immed_double_const (value
7016 & (~ (HOST_WIDE_INT) 0xffff),
7017 0, DImode)));
7018 }
7020 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7021 DONE;
7022 }
7023 }")
7025 (define_insn "*booldi3_internal1"
7026 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7027 (match_operator:DI 3 "boolean_or_operator"
7028 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7029 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7030 "TARGET_POWERPC64"
7031 "@
7032 %q3 %0,%1,%2
7033 %q3i %0,%1,%b2
7034 %q3is %0,%1,%u2")
7036 (define_insn "*booldi3_internal2"
7037 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7038 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7039 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7040 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7041 (const_int 0)))
7042 (clobber (match_scratch:DI 3 "=r,r"))]
7043 "TARGET_POWERPC64"
7044 "@
7045 %q4. %3,%1,%2
7046 #"
7047 [(set_attr "type" "compare")
7048 (set_attr "length" "4,8")])
7050 (define_split
7051 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7052 (compare:CC (match_operator:DI 4 "boolean_operator"
7053 [(match_operand:DI 1 "gpc_reg_operand" "")
7054 (match_operand:DI 2 "gpc_reg_operand" "")])
7055 (const_int 0)))
7056 (clobber (match_scratch:DI 3 ""))]
7057 "TARGET_POWERPC64 && reload_completed"
7058 [(set (match_dup 3) (match_dup 4))
7059 (set (match_dup 0)
7060 (compare:CC (match_dup 3)
7061 (const_int 0)))]
7062 "")
7064 (define_insn "*booldi3_internal3"
7065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7066 (compare:CC (match_operator:DI 4 "boolean_operator"
7067 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7068 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7069 (const_int 0)))
7070 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7071 (match_dup 4))]
7072 "TARGET_POWERPC64"
7073 "@
7074 %q4. %0,%1,%2
7075 #"
7076 [(set_attr "type" "compare")
7077 (set_attr "length" "4,8")])
7079 (define_split
7080 [(set (match_operand:CC 3 "cc_reg_operand" "")
7081 (compare:CC (match_operator:DI 4 "boolean_operator"
7082 [(match_operand:DI 1 "gpc_reg_operand" "")
7083 (match_operand:DI 2 "gpc_reg_operand" "")])
7084 (const_int 0)))
7085 (set (match_operand:DI 0 "gpc_reg_operand" "")
7086 (match_dup 4))]
7087 "TARGET_POWERPC64 && reload_completed"
7088 [(set (match_dup 0) (match_dup 4))
7089 (set (match_dup 3)
7090 (compare:CC (match_dup 0)
7091 (const_int 0)))]
7092 "")
7094 ;; Split an logical operation that we can't do in one insn into two insns,
7095 ;; each of which does one 16-bit part. This is used by combine.
7097 (define_split
7098 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7099 (match_operator:DI 3 "boolean_or_operator"
7100 [(match_operand:DI 1 "gpc_reg_operand" "")
7101 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7102 "TARGET_POWERPC64"
7103 [(set (match_dup 0) (match_dup 4))
7104 (set (match_dup 0) (match_dup 5))]
7105 "
7106 {
7107 rtx i3,i4;
7109 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7110 {
7111 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7112 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7113 0, DImode);
7114 i4 = GEN_INT (value & 0xffff);
7115 }
7116 else
7117 {
7118 i3 = GEN_INT (INTVAL (operands[2])
7119 & (~ (HOST_WIDE_INT) 0xffff));
7120 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7121 }
7122 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7123 operands[1], i3);
7124 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7125 operands[0], i4);
7126 }")
7128 (define_insn "*boolcdi3_internal1"
7129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7130 (match_operator:DI 3 "boolean_operator"
7131 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7132 (match_operand:DI 2 "logical_operand" "r")]))]
7133 "TARGET_POWERPC64"
7134 "%q3 %0,%2,%1")
7136 (define_insn "*boolcdi3_internal2"
7137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7138 (compare:CC (match_operator:DI 4 "boolean_operator"
7139 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7140 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7141 (const_int 0)))
7142 (clobber (match_scratch:DI 3 "=r,r"))]
7143 "TARGET_POWERPC64"
7144 "@
7145 %q4. %3,%2,%1
7146 #"
7147 [(set_attr "type" "compare")
7148 (set_attr "length" "4,8")])
7150 (define_split
7151 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7152 (compare:CC (match_operator:DI 4 "boolean_operator"
7153 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7154 (match_operand:DI 2 "gpc_reg_operand" "")])
7155 (const_int 0)))
7156 (clobber (match_scratch:DI 3 ""))]
7157 "TARGET_POWERPC64 && reload_completed"
7158 [(set (match_dup 3) (match_dup 4))
7159 (set (match_dup 0)
7160 (compare:CC (match_dup 3)
7161 (const_int 0)))]
7162 "")
7164 (define_insn "*boolcdi3_internal3"
7165 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7166 (compare:CC (match_operator:DI 4 "boolean_operator"
7167 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7168 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7169 (const_int 0)))
7170 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7171 (match_dup 4))]
7172 "TARGET_POWERPC64"
7173 "@
7174 %q4. %0,%2,%1
7175 #"
7176 [(set_attr "type" "compare")
7177 (set_attr "length" "4,8")])
7179 (define_split
7180 [(set (match_operand:CC 3 "cc_reg_operand" "")
7181 (compare:CC (match_operator:DI 4 "boolean_operator"
7182 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7183 (match_operand:DI 2 "gpc_reg_operand" "")])
7184 (const_int 0)))
7185 (set (match_operand:DI 0 "gpc_reg_operand" "")
7186 (match_dup 4))]
7187 "TARGET_POWERPC64 && reload_completed"
7188 [(set (match_dup 0) (match_dup 4))
7189 (set (match_dup 3)
7190 (compare:CC (match_dup 0)
7191 (const_int 0)))]
7192 "")
7194 (define_insn "*boolccdi3_internal1"
7195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7196 (match_operator:DI 3 "boolean_operator"
7197 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7198 (not:DI (match_operand:DI 2 "logical_operand" "r"))]))]
7199 "TARGET_POWERPC64"
7200 "%q3 %0,%1,%2")
7202 (define_insn "*boolccdi3_internal2"
7203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7204 (compare:CC (match_operator:DI 4 "boolean_operator"
7205 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7206 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7207 (const_int 0)))
7208 (clobber (match_scratch:DI 3 "=r,r"))]
7209 "TARGET_POWERPC64"
7210 "@
7211 %q4. %3,%1,%2
7212 #"
7213 [(set_attr "type" "compare")
7214 (set_attr "length" "4,8")])
7216 (define_split
7217 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7218 (compare:CC (match_operator:DI 4 "boolean_operator"
7219 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7220 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7221 (const_int 0)))
7222 (clobber (match_scratch:DI 3 ""))]
7223 "TARGET_POWERPC64 && reload_completed"
7224 [(set (match_dup 3) (match_dup 4))
7225 (set (match_dup 0)
7226 (compare:CC (match_dup 3)
7227 (const_int 0)))]
7228 "")
7230 (define_insn "*boolccdi3_internal3"
7231 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7232 (compare:CC (match_operator:DI 4 "boolean_operator"
7233 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7234 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7235 (const_int 0)))
7236 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7237 (match_dup 4))]
7238 "TARGET_POWERPC64"
7239 "@
7240 %q4. %0,%1,%2
7241 #"
7242 [(set_attr "type" "compare")
7243 (set_attr "length" "4,8")])
7245 (define_split
7246 [(set (match_operand:CC 3 "cc_reg_operand" "")
7247 (compare:CC (match_operator:DI 4 "boolean_operator"
7248 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7249 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7250 (const_int 0)))
7251 (set (match_operand:DI 0 "gpc_reg_operand" "")
7252 (match_dup 4))]
7253 "TARGET_POWERPC64 && reload_completed"
7254 [(set (match_dup 0) (match_dup 4))
7255 (set (match_dup 3)
7256 (compare:CC (match_dup 0)
7257 (const_int 0)))]
7258 "")
7259 \f
7260 ;; Now define ways of moving data around.
7262 ;; Elf specific ways of loading addresses for non-PIC code.
7263 ;; The output of this could be r0, but we make a very strong
7264 ;; preference for a base register because it will usually
7265 ;; be needed there.
7266 (define_insn "elf_high"
7267 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7268 (high:SI (match_operand 1 "" "")))]
7269 "TARGET_ELF && ! TARGET_64BIT"
7270 "{liu|lis} %0,%1@ha")
7272 (define_insn "elf_low"
7273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7274 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7275 (match_operand 2 "" "")))]
7276 "TARGET_ELF && ! TARGET_64BIT"
7277 "@
7278 {cal|la} %0,%2@l(%1)
7279 {ai|addic} %0,%1,%K2")
7281 ;; Mach-O PIC trickery.
7282 (define_insn "macho_high"
7283 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7284 (high:SI (match_operand 1 "" "")))]
7285 "TARGET_MACHO && ! TARGET_64BIT"
7286 "{liu|lis} %0,ha16(%1)")
7288 (define_insn "macho_low"
7289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7290 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7291 (match_operand 2 "" "")))]
7292 "TARGET_MACHO && ! TARGET_64BIT"
7293 "@
7294 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7295 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7297 ;; Set up a register with a value from the GOT table
7299 (define_expand "movsi_got"
7300 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7301 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7302 (match_dup 2)] 8))]
7303 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
7304 "
7305 {
7306 if (GET_CODE (operands[1]) == CONST)
7307 {
7308 rtx offset = const0_rtx;
7309 HOST_WIDE_INT value;
7311 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7312 value = INTVAL (offset);
7313 if (value != 0)
7314 {
7315 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7316 emit_insn (gen_movsi_got (tmp, operands[1]));
7317 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7318 DONE;
7319 }
7320 }
7322 operands[2] = rs6000_got_register (operands[1]);
7323 }")
7325 (define_insn "*movsi_got_internal"
7326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7327 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7328 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
7329 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
7330 "{l|lwz} %0,%a1@got(%2)"
7331 [(set_attr "type" "load")])
7333 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7334 ;; didn't get allocated to a hard register.
7335 (define_split
7336 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7337 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7338 (match_operand:SI 2 "memory_operand" "")] 8))]
7339 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7340 && flag_pic == 1
7341 && (reload_in_progress || reload_completed)"
7342 [(set (match_dup 0) (match_dup 2))
7343 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
7344 "")
7346 ;; For SI, we special-case integers that can't be loaded in one insn. We
7347 ;; do the load 16-bits at a time. We could do this by loading from memory,
7348 ;; and this is even supposed to be faster, but it is simpler not to get
7349 ;; integers in the TOC.
7350 (define_expand "movsi"
7351 [(set (match_operand:SI 0 "general_operand" "")
7352 (match_operand:SI 1 "any_operand" ""))]
7353 ""
7354 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7356 (define_insn "movsi_low"
7357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7358 (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
7359 (match_operand 2 "" ""))))]
7360 "TARGET_MACHO && ! TARGET_64BIT"
7361 "{l|lwz} %0,lo16(%2)(%1)"
7362 [(set_attr "type" "load")
7363 (set_attr "length" "4")])
7365 (define_insn "*movsi_internal1"
7366 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
7367 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
7368 "gpc_reg_operand (operands[0], SImode)
7369 || gpc_reg_operand (operands[1], SImode)"
7370 "@
7371 mr %0,%1
7372 {cal|la} %0,%a1
7373 {l%U1%X1|lwz%U1%X1} %0,%1
7374 {st%U0%X0|stw%U0%X0} %1,%0
7375 {lil|li} %0,%1
7376 {liu|lis} %0,%v1
7377 #
7378 {cal|la} %0,%a1
7379 mf%1 %0
7380 mt%0 %1
7381 mt%0 %1
7382 cror 0,0,0"
7383 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
7384 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
7386 ;; Split a load of a large constant into the appropriate two-insn
7387 ;; sequence.
7389 (define_split
7390 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7391 (match_operand:SI 1 "const_int_operand" ""))]
7392 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7393 && (INTVAL (operands[1]) & 0xffff) != 0"
7394 [(set (match_dup 0)
7395 (match_dup 2))
7396 (set (match_dup 0)
7397 (ior:SI (match_dup 0)
7398 (match_dup 3)))]
7399 "
7400 {
7401 operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
7402 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
7403 }")
7405 (define_insn "*movsi_internal2"
7406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7407 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
7408 (const_int 0)))
7409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
7410 "! TARGET_POWERPC64"
7411 "@
7412 mr. %0,%1
7413 #"
7414 [(set_attr "type" "compare")
7415 (set_attr "length" "4,8")])
7416 \f
7417 (define_split
7418 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7419 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7420 (const_int 0)))
7421 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7422 "! TARGET_POWERPC64 && reload_completed"
7423 [(set (match_dup 0) (match_dup 1))
7424 (set (match_dup 2)
7425 (compare:CC (match_dup 0)
7426 (const_int 0)))]
7427 "")
7429 (define_expand "movhi"
7430 [(set (match_operand:HI 0 "general_operand" "")
7431 (match_operand:HI 1 "any_operand" ""))]
7432 ""
7433 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7435 (define_insn ""
7436 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7437 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7438 "gpc_reg_operand (operands[0], HImode)
7439 || gpc_reg_operand (operands[1], HImode)"
7440 "@
7441 mr %0,%1
7442 lhz%U1%X1 %0,%1
7443 sth%U0%X0 %1,%0
7444 {lil|li} %0,%w1
7445 mf%1 %0
7446 mt%0 %1
7447 mt%0 %1
7448 cror 0,0,0"
7449 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7451 (define_expand "movqi"
7452 [(set (match_operand:QI 0 "general_operand" "")
7453 (match_operand:QI 1 "any_operand" ""))]
7454 ""
7455 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7457 (define_insn ""
7458 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7459 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7460 "gpc_reg_operand (operands[0], QImode)
7461 || gpc_reg_operand (operands[1], QImode)"
7462 "@
7463 mr %0,%1
7464 lbz%U1%X1 %0,%1
7465 stb%U0%X0 %1,%0
7466 {lil|li} %0,%1
7467 mf%1 %0
7468 mt%0 %1
7469 mt%0 %1
7470 cror 0,0,0"
7471 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7472 \f
7473 ;; Here is how to move condition codes around. When we store CC data in
7474 ;; an integer register or memory, we store just the high-order 4 bits.
7475 ;; This lets us not shift in the most common case of CR0.
7476 (define_expand "movcc"
7477 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7478 (match_operand:CC 1 "nonimmediate_operand" ""))]
7479 ""
7480 "")
7482 (define_insn ""
7483 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
7484 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
7485 "register_operand (operands[0], CCmode)
7486 || register_operand (operands[1], CCmode)"
7487 "@
7488 mcrf %0,%1
7489 mtcrf 128,%1
7490 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7491 mfcr %0
7492 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7493 mr %0,%1
7494 {l%U1%X1|lwz%U1%X1} %0,%1
7495 {st%U0%U1|stw%U0%U1} %1,%0"
7496 [(set_attr "type" "*,*,*,compare,*,*,load,store")
7497 (set_attr "length" "*,*,12,*,8,*,*,*")])
7498 \f
7499 ;; For floating-point, we normally deal with the floating-point registers
7500 ;; unless -msoft-float is used. The sole exception is that parameter passing
7501 ;; can produce floating-point values in fixed-point registers. Unless the
7502 ;; value is a simple constant or already in memory, we deal with this by
7503 ;; allocating memory and copying the value explicitly via that memory location.
7504 (define_expand "movsf"
7505 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7506 (match_operand:SF 1 "any_operand" ""))]
7507 ""
7508 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7510 (define_split
7511 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7512 (match_operand:SF 1 "const_double_operand" ""))]
7513 "reload_completed
7514 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7515 || (GET_CODE (operands[0]) == SUBREG
7516 && GET_CODE (SUBREG_REG (operands[0])) == REG
7517 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7518 [(set (match_dup 2) (match_dup 3))]
7519 "
7520 {
7521 long l;
7522 REAL_VALUE_TYPE rv;
7524 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7525 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7527 if (! TARGET_POWERPC64)
7528 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7529 else
7530 operands[2] = gen_lowpart (SImode, operands[0]);
7532 operands[3] = GEN_INT (trunc_int_for_mode (l, SImode));
7533 }")
7535 (define_insn "*movsf_hardfloat"
7536 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
7537 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
7538 "(gpc_reg_operand (operands[0], SFmode)
7539 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
7540 "@
7541 mr %0,%1
7542 {l%U1%X1|lwz%U1%X1} %0,%1
7543 {st%U0%X0|stw%U0%X0} %1,%0
7544 fmr %0,%1
7545 lfs%U1%X1 %0,%1
7546 stfs%U0%X0 %1,%0
7547 #
7548 #"
7549 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
7550 (set_attr "length" "4,4,4,4,4,4,4,8")])
7552 (define_insn "*movsf_softfloat"
7553 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
7554 (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
7555 "(gpc_reg_operand (operands[0], SFmode)
7556 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
7557 "@
7558 mr %0,%1
7559 {l%U1%X1|lwz%U1%X1} %0,%1
7560 {st%U0%X0|stw%U0%X0} %1,%0
7561 {lil|li} %0,%1
7562 {liu|lis} %0,%v1
7563 {cal|la} %0,%a1
7564 #
7565 #"
7566 [(set_attr "type" "*,load,store,*,*,*,*,*")
7567 (set_attr "length" "4,4,4,4,4,4,4,8")])
7569 \f
7570 (define_expand "movdf"
7571 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7572 (match_operand:DF 1 "any_operand" ""))]
7573 ""
7574 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7576 (define_split
7577 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7578 (match_operand:DF 1 "const_int_operand" ""))]
7579 "! TARGET_POWERPC64 && reload_completed
7580 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7581 || (GET_CODE (operands[0]) == SUBREG
7582 && GET_CODE (SUBREG_REG (operands[0])) == REG
7583 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7584 [(set (match_dup 2) (match_dup 4))
7585 (set (match_dup 3) (match_dup 1))]
7586 "
7587 {
7588 int endian = (WORDS_BIG_ENDIAN == 0);
7589 HOST_WIDE_INT value = INTVAL (operands[1]);
7591 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7592 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7593 #if HOST_BITS_PER_WIDE_INT == 32
7594 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7595 #else
7596 operands[4] = GEN_INT (value >> 32);
7597 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7598 #endif
7599 }")
7601 (define_split
7602 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7603 (match_operand:DF 1 "const_double_operand" ""))]
7604 "! TARGET_POWERPC64 && reload_completed
7605 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7606 || (GET_CODE (operands[0]) == SUBREG
7607 && GET_CODE (SUBREG_REG (operands[0])) == REG
7608 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7609 [(set (match_dup 2) (match_dup 4))
7610 (set (match_dup 3) (match_dup 5))]
7611 "
7612 {
7613 int endian = (WORDS_BIG_ENDIAN == 0);
7614 long l[2];
7615 REAL_VALUE_TYPE rv;
7617 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7618 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7620 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7621 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7622 operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode));
7623 operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode));
7624 }")
7626 (define_split
7627 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7628 (match_operand:DF 1 "easy_fp_constant" ""))]
7629 "TARGET_POWERPC64 && reload_completed
7630 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7631 || (GET_CODE (operands[0]) == SUBREG
7632 && GET_CODE (SUBREG_REG (operands[0])) == REG
7633 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7634 [(set (match_dup 2) (match_dup 3))]
7635 "
7636 {
7637 int endian = (WORDS_BIG_ENDIAN == 0);
7638 long l[2];
7639 REAL_VALUE_TYPE rv;
7641 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7642 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7644 operands[2] = gen_lowpart (DImode, operands[0]);
7645 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7646 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7647 }")
7649 ;; Don't have reload use general registers to load a constant. First,
7650 ;; it might not work if the output operand is the equivalent of
7651 ;; a non-offsettable memref, but also it is less efficient than loading
7652 ;; the constant into an FP register, since it will probably be used there.
7653 ;; The "??" is a kludge until we can figure out a more reasonable way
7654 ;; of handling these non-offsettable values.
7655 (define_insn "*movdf_hardfloat32"
7656 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7657 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7658 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
7659 && (gpc_reg_operand (operands[0], DFmode)
7660 || gpc_reg_operand (operands[1], DFmode))"
7661 "*
7662 {
7663 switch (which_alternative)
7664 {
7665 default:
7666 abort ();
7667 case 0:
7668 /* We normally copy the low-numbered register first. However, if
7669 the first register operand 0 is the same as the second register
7670 of operand 1, we must copy in the opposite order. */
7671 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7672 return \"mr %L0,%L1\;mr %0,%1\";
7673 else
7674 return \"mr %0,%1\;mr %L0,%L1\";
7675 case 1:
7676 if (offsettable_memref_p (operands[1])
7677 || (GET_CODE (operands[1]) == MEM
7678 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7679 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7680 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
7681 {
7682 /* If the low-address word is used in the address, we must load
7683 it last. Otherwise, load it first. Note that we cannot have
7684 auto-increment in that case since the address register is
7685 known to be dead. */
7686 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7687 operands[1], 0))
7688 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7689 else
7690 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7691 }
7692 else
7693 {
7694 rtx addreg;
7696 addreg = find_addr_reg (XEXP (operands[1], 0));
7697 if (refers_to_regno_p (REGNO (operands[0]),
7698 REGNO (operands[0]) + 1,
7699 operands[1], 0))
7700 {
7701 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7702 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7703 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7704 return \"{lx|lwzx} %0,%1\";
7705 }
7706 else
7707 {
7708 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7709 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7710 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7711 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7712 return \"\";
7713 }
7714 }
7715 case 2:
7716 if (offsettable_memref_p (operands[0])
7717 || (GET_CODE (operands[0]) == MEM
7718 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7719 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7720 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
7721 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7722 else
7723 {
7724 rtx addreg;
7726 addreg = find_addr_reg (XEXP (operands[0], 0));
7727 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7728 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7729 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7730 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7731 return \"\";
7732 }
7733 case 3:
7734 case 4:
7735 case 5:
7736 return \"#\";
7737 case 6:
7738 return \"fmr %0,%1\";
7739 case 7:
7740 return \"lfd%U1%X1 %0,%1\";
7741 case 8:
7742 return \"stfd%U0%X0 %1,%0\";
7743 }
7744 }"
7745 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
7746 (set_attr "length" "8,16,16,8,12,16,*,*,*")])
7748 (define_insn "*movdf_softfloat32"
7749 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7750 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7751 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
7752 && (gpc_reg_operand (operands[0], DFmode)
7753 || gpc_reg_operand (operands[1], DFmode))"
7754 "*
7755 {
7756 switch (which_alternative)
7757 {
7758 default:
7759 abort ();
7760 case 0:
7761 /* We normally copy the low-numbered register first. However, if
7762 the first register operand 0 is the same as the second register of
7763 operand 1, we must copy in the opposite order. */
7764 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7765 return \"mr %L0,%L1\;mr %0,%1\";
7766 else
7767 return \"mr %0,%1\;mr %L0,%L1\";
7768 case 1:
7769 /* If the low-address word is used in the address, we must load
7770 it last. Otherwise, load it first. Note that we cannot have
7771 auto-increment in that case since the address register is
7772 known to be dead. */
7773 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7774 operands[1], 0))
7775 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7776 else
7777 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7778 case 2:
7779 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7780 case 3:
7781 case 4:
7782 case 5:
7783 return \"#\";
7784 }
7785 }"
7786 [(set_attr "type" "*,load,store,*,*,*")
7787 (set_attr "length" "8,8,8,8,12,16")])
7789 (define_insn "*movdf_hardfloat64"
7790 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7791 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7792 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
7793 && (gpc_reg_operand (operands[0], DFmode)
7794 || gpc_reg_operand (operands[1], DFmode))"
7795 "@
7796 mr %0,%1
7797 ld%U1%X1 %0,%1
7798 std%U0%X0 %1,%0
7799 #
7800 #
7801 #
7802 fmr %0,%1
7803 lfd%U1%X1 %0,%1
7804 stfd%U0%X0 %1,%0"
7805 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
7806 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
7808 (define_insn "*movdf_softfloat64"
7809 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7810 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7811 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
7812 && (gpc_reg_operand (operands[0], DFmode)
7813 || gpc_reg_operand (operands[1], DFmode))"
7814 "@
7815 mr %0,%1
7816 ld%U1%X1 %0,%1
7817 std%U0%X0 %1,%0
7818 #
7819 #
7820 #"
7821 [(set_attr "type" "*,load,store,*,*,*")
7822 (set_attr "length" "*,*,*,8,12,16")])
7823 \f
7824 ;; Next come the multi-word integer load and store and the load and store
7825 ;; multiple insns.
7826 (define_expand "movdi"
7827 [(set (match_operand:DI 0 "general_operand" "")
7828 (match_operand:DI 1 "any_operand" ""))]
7829 ""
7830 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
7832 (define_insn "*movdi_internal32"
7833 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
7834 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
7835 "! TARGET_POWERPC64
7836 && (gpc_reg_operand (operands[0], DImode)
7837 || gpc_reg_operand (operands[1], DImode))"
7838 "*
7839 {
7840 switch (which_alternative)
7841 {
7842 default:
7843 abort ();
7844 case 0:
7845 /* We normally copy the low-numbered register first. However, if
7846 the first register operand 0 is the same as the second register of
7847 operand 1, we must copy in the opposite order. */
7848 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7849 return \"mr %L0,%L1\;mr %0,%1\";
7850 else
7851 return \"mr %0,%1\;mr %L0,%L1\";
7852 case 1:
7853 /* If the low-address word is used in the address, we must load it
7854 last. Otherwise, load it first. Note that we cannot have
7855 auto-increment in that case since the address register is known to be
7856 dead. */
7857 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7858 operands[1], 0))
7859 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7860 else
7861 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7862 case 2:
7863 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7864 case 3:
7865 return \"fmr %0,%1\";
7866 case 4:
7867 return \"lfd%U1%X1 %0,%1\";
7868 case 5:
7869 return \"stfd%U0%X0 %1,%0\";
7870 case 6:
7871 case 7:
7872 case 8:
7873 case 9:
7874 case 10:
7875 return \"#\";
7876 }
7877 }"
7878 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
7879 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
7881 (define_split
7882 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7883 (match_operand:DI 1 "const_int_operand" ""))]
7884 "! TARGET_POWERPC64 && reload_completed"
7885 [(set (match_dup 2) (match_dup 4))
7886 (set (match_dup 3) (match_dup 1))]
7887 "
7888 {
7889 HOST_WIDE_INT value = INTVAL (operands[1]);
7890 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7891 DImode);
7892 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7893 DImode);
7894 #if HOST_BITS_PER_WIDE_INT == 32
7895 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7896 #else
7897 operands[4] = GEN_INT (value >> 32);
7898 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7899 #endif
7900 }")
7902 (define_split
7903 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7904 (match_operand:DI 1 "const_double_operand" ""))]
7905 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
7906 [(set (match_dup 2) (match_dup 4))
7907 (set (match_dup 3) (match_dup 5))]
7908 "
7909 {
7910 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7911 DImode);
7912 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7913 DImode);
7914 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7915 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7916 }")
7918 (define_insn "*movdi_internal64"
7919 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
7920 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
7921 "TARGET_POWERPC64
7922 && (gpc_reg_operand (operands[0], DImode)
7923 || gpc_reg_operand (operands[1], DImode))"
7924 "@
7925 mr %0,%1
7926 ld%U1%X1 %0,%1
7927 std%U0%X0 %1,%0
7928 li %0,%1
7929 lis %0,%v1
7930 #
7931 {cal|la} %0,%a1
7932 fmr %0,%1
7933 lfd%U1%X1 %0,%1
7934 stfd%U0%X0 %1,%0
7935 mf%1 %0
7936 mt%0 %1
7937 cror 0,0,0"
7938 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
7939 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
7941 ;; immediate value valid for a single instruction hiding in a const_double
7942 (define_insn ""
7943 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7944 (match_operand:DI 1 "const_double_operand" "F"))]
7945 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
7946 && GET_CODE (operands[1]) == CONST_DOUBLE
7947 && num_insns_constant (operands[1], DImode) == 1"
7948 "*
7949 {
7950 return ((unsigned HOST_WIDE_INT)
7951 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
7952 ? \"li %0,%1\" : \"lis %0,%v1\";
7953 }")
7955 ;; Generate all one-bits and clear left or right.
7956 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
7957 (define_split
7958 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7959 (match_operand:DI 1 "mask64_operand" ""))]
7960 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
7961 [(set (match_dup 0) (const_int -1))
7962 (set (match_dup 0)
7963 (and:DI (rotate:DI (match_dup 0)
7964 (const_int 0))
7965 (match_dup 1)))]
7966 "")
7968 ;; Split a load of a large constant into the appropriate five-instruction
7969 ;; sequence. Handle anything in a constant number of insns.
7970 ;; When non-easy constants can go in the TOC, this should use
7971 ;; easy_fp_constant predicate.
7972 (define_split
7973 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7974 (match_operand:DI 1 "const_int_operand" ""))]
7975 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
7976 [(set (match_dup 0) (match_dup 2))
7977 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
7978 "
7979 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
7981 if (tem == operands[0])
7982 DONE;
7983 else
7984 FAIL;
7985 }")
7987 (define_split
7988 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7989 (match_operand:DI 1 "const_double_operand" ""))]
7990 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
7991 [(set (match_dup 0) (match_dup 2))
7992 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
7993 "
7994 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
7996 if (tem == operands[0])
7997 DONE;
7998 else
7999 FAIL;
8000 }")
8002 ;; Split a load of a large constant into the appropriate five-instruction
8003 (define_insn "*movdi_internal2"
8004 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8005 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
8006 (const_int 0)))
8007 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8008 "TARGET_POWERPC64"
8009 "@
8010 mr. %0,%1
8011 #"
8012 [(set_attr "type" "compare")
8013 (set_attr "length" "4,8")])
8015 (define_split
8016 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8017 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8018 (const_int 0)))
8019 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8020 "TARGET_POWERPC64 && reload_completed"
8021 [(set (match_dup 0) (match_dup 1))
8022 (set (match_dup 2)
8023 (compare:CC (match_dup 0)
8024 (const_int 0)))]
8025 "")
8026 \f
8027 ;; TImode is similar, except that we usually want to compute the address into
8028 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8029 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8030 (define_expand "movti"
8031 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8032 (match_operand:TI 1 "general_operand" ""))
8033 (clobber (scratch:SI))])]
8034 "TARGET_STRING || TARGET_POWERPC64"
8035 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8037 ;; We say that MQ is clobbered in the last alternative because the first
8038 ;; alternative would never get used otherwise since it would need a reload
8039 ;; while the 2nd alternative would not. We put memory cases first so they
8040 ;; are preferred. Otherwise, we'd try to reload the output instead of
8041 ;; giving the SCRATCH mq.
8042 (define_insn "*movti_power"
8043 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8044 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8045 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8046 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8047 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8048 "*
8049 {
8050 switch (which_alternative)
8051 {
8052 default:
8053 abort ();
8055 case 0:
8056 return \"{stsi|stswi} %1,%P0,16\";
8058 case 1:
8059 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8061 case 2:
8062 /* Normally copy registers with lowest numbered register copied first.
8063 But copy in the other order if the first register of the output
8064 is the second, third, or fourth register in the input. */
8065 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8066 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8067 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8068 else
8069 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8070 case 3:
8071 /* If the address is not used in the output, we can use lsi. Otherwise,
8072 fall through to generating four loads. */
8073 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8074 return \"{lsi|lswi} %0,%P1,16\";
8075 /* ... fall through ... */
8076 case 4:
8077 /* If the address register is the same as the register for the lowest-
8078 addressed word, load it last. Similarly for the next two words.
8079 Otherwise load lowest address to highest. */
8080 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8081 operands[1], 0))
8082 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8083 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8084 REGNO (operands[0]) + 2, operands[1], 0))
8085 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8086 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8087 REGNO (operands[0]) + 3, operands[1], 0))
8088 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8089 else
8090 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8091 }
8092 }"
8093 [(set_attr "type" "store,store,*,load,load")
8094 (set_attr "length" "*,16,16,*,16")])
8096 (define_insn "*movti_string"
8097 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
8098 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
8099 (clobber (match_scratch:SI 2 "=X,X,X"))]
8100 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8101 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8102 "*
8103 {
8104 switch (which_alternative)
8105 {
8106 default:
8107 abort ();
8109 case 0:
8110 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8112 case 1:
8113 /* Normally copy registers with lowest numbered register copied first.
8114 But copy in the other order if the first register of the output
8115 is the second, third, or fourth register in the input. */
8116 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8117 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8118 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8119 else
8120 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8121 case 2:
8122 /* If the address register is the same as the register for the lowest-
8123 addressed word, load it last. Similarly for the next two words.
8124 Otherwise load lowest address to highest. */
8125 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8126 operands[1], 0))
8127 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8128 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8129 REGNO (operands[0]) + 2, operands[1], 0))
8130 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8131 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8132 REGNO (operands[0]) + 3, operands[1], 0))
8133 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8134 else
8135 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8136 }
8137 }"
8138 [(set_attr "type" "store,*,load")
8139 (set_attr "length" "16,16,16")])
8141 (define_insn "*movti_ppc64"
8142 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8143 (match_operand:TI 1 "input_operand" "r,m,r"))]
8144 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8145 || gpc_reg_operand (operands[1], TImode))"
8146 "*
8147 {
8148 switch (which_alternative)
8149 {
8150 default:
8151 abort ();
8152 case 0:
8153 /* We normally copy the low-numbered register first. However, if
8154 the first register operand 0 is the same as the second register of
8155 operand 1, we must copy in the opposite order. */
8156 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8157 return \"mr %L0,%L1\;mr %0,%1\";
8158 else
8159 return \"mr %0,%1\;mr %L0,%L1\";
8160 case 1:
8161 /* If the low-address word is used in the address, we must load it
8162 last. Otherwise, load it first. Note that we cannot have
8163 auto-increment in that case since the address register is known to be
8164 dead. */
8165 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8166 operands[1], 0))
8167 return \"ld %L0,%L1\;ld %0,%1\";
8168 else
8169 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8170 case 2:
8171 return \"std%U0 %1,%0\;std %L1,%L0\";
8172 }
8173 }"
8174 [(set_attr "type" "*,load,store")
8175 (set_attr "length" "8,8,8")])
8176 \f
8177 (define_expand "load_multiple"
8178 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8179 (match_operand:SI 1 "" ""))
8180 (use (match_operand:SI 2 "" ""))])]
8181 "TARGET_STRING"
8182 "
8183 {
8184 int regno;
8185 int count;
8186 rtx op1;
8187 int i;
8189 /* Support only loading a constant number of fixed-point registers from
8190 memory and only bother with this if more than two; the machine
8191 doesn't support more than eight. */
8192 if (GET_CODE (operands[2]) != CONST_INT
8193 || INTVAL (operands[2]) <= 2
8194 || INTVAL (operands[2]) > 8
8195 || GET_CODE (operands[1]) != MEM
8196 || GET_CODE (operands[0]) != REG
8197 || REGNO (operands[0]) >= 32)
8198 FAIL;
8200 count = INTVAL (operands[2]);
8201 regno = REGNO (operands[0]);
8203 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8204 op1 = replace_equiv_address (operands[1],
8205 force_reg (SImode, XEXP (operands[1], 0)));
8207 for (i = 0; i < count; i++)
8208 XVECEXP (operands[3], 0, i)
8209 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8210 adjust_address (op1, SImode, i * 4));
8211 }")
8213 (define_insn ""
8214 [(match_parallel 0 "load_multiple_operation"
8215 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8216 (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])]
8217 "TARGET_STRING"
8218 "*
8219 {
8220 /* We have to handle the case where the pseudo used to contain the address
8221 is assigned to one of the output registers. */
8222 int i, j;
8223 int words = XVECLEN (operands[0], 0);
8224 rtx xop[10];
8226 if (XVECLEN (operands[0], 0) == 1)
8227 return \"{l|lwz} %1,0(%2)\";
8229 for (i = 0; i < words; i++)
8230 if (refers_to_regno_p (REGNO (operands[1]) + i,
8231 REGNO (operands[1]) + i + 1, operands[2], 0))
8232 {
8233 if (i == words-1)
8234 {
8235 xop[0] = operands[1];
8236 xop[1] = operands[2];
8237 xop[2] = GEN_INT (4 * (words-1));
8238 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
8239 return \"\";
8240 }
8241 else if (i == 0)
8242 {
8243 xop[0] = operands[1];
8244 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8245 xop[2] = GEN_INT (4 * (words-1));
8246 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
8247 return \"\";
8248 }
8249 else
8250 {
8251 for (j = 0; j < words; j++)
8252 if (j != i)
8253 {
8254 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
8255 xop[1] = operands[2];
8256 xop[2] = GEN_INT (j * 4);
8257 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
8258 }
8259 xop[0] = operands[2];
8260 xop[1] = GEN_INT (i * 4);
8261 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
8262 return \"\";
8263 }
8264 }
8266 return \"{lsi|lswi} %1,%2,%N0\";
8267 }"
8268 [(set_attr "type" "load")
8269 (set_attr "length" "32")])
8271 \f
8272 (define_expand "store_multiple"
8273 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8274 (match_operand:SI 1 "" ""))
8275 (clobber (scratch:SI))
8276 (use (match_operand:SI 2 "" ""))])]
8277 "TARGET_STRING"
8278 "
8279 {
8280 int regno;
8281 int count;
8282 rtx to;
8283 rtx op0;
8284 int i;
8286 /* Support only storing a constant number of fixed-point registers to
8287 memory and only bother with this if more than two; the machine
8288 doesn't support more than eight. */
8289 if (GET_CODE (operands[2]) != CONST_INT
8290 || INTVAL (operands[2]) <= 2
8291 || INTVAL (operands[2]) > 8
8292 || GET_CODE (operands[0]) != MEM
8293 || GET_CODE (operands[1]) != REG
8294 || REGNO (operands[1]) >= 32)
8295 FAIL;
8297 count = INTVAL (operands[2]);
8298 regno = REGNO (operands[1]);
8300 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8301 to = force_reg (SImode, XEXP (operands[0], 0));
8302 op0 = replace_equiv_address (operands[0], to);
8304 XVECEXP (operands[3], 0, 0)
8305 = gen_rtx_SET (VOIDmode, op0, operands[1]);
8306 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8307 gen_rtx_SCRATCH (SImode));
8309 for (i = 1; i < count; i++)
8310 XVECEXP (operands[3], 0, i + 1)
8311 = gen_rtx_SET (VOIDmode,
8312 adjust_address (op0, SImode, i * 4),
8313 gen_rtx_REG (SImode, regno + i));
8314 }")
8316 (define_insn ""
8317 [(match_parallel 0 "store_multiple_operation"
8318 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8319 (match_operand:SI 2 "gpc_reg_operand" "r"))
8320 (clobber (match_scratch:SI 3 "=q"))])]
8321 "TARGET_STRING && TARGET_POWER"
8322 "{stsi|stswi} %2,%P1,%O0"
8323 [(set_attr "type" "store")])
8325 (define_insn ""
8326 [(match_parallel 0 "store_multiple_operation"
8327 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8328 (match_operand:SI 2 "gpc_reg_operand" "r"))
8329 (clobber (match_scratch:SI 3 "X"))])]
8330 "TARGET_STRING && ! TARGET_POWER"
8331 "{stsi|stswi} %2,%1,%O0"
8332 [(set_attr "type" "store")])
8334 \f
8335 ;; String/block move insn.
8336 ;; Argument 0 is the destination
8337 ;; Argument 1 is the source
8338 ;; Argument 2 is the length
8339 ;; Argument 3 is the alignment
8341 (define_expand "movstrsi"
8342 [(parallel [(set (match_operand:BLK 0 "" "")
8343 (match_operand:BLK 1 "" ""))
8344 (use (match_operand:SI 2 "" ""))
8345 (use (match_operand:SI 3 "" ""))])]
8346 ""
8347 "
8348 {
8349 if (expand_block_move (operands))
8350 DONE;
8351 else
8352 FAIL;
8353 }")
8355 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8356 ;; register allocator doesn't have a clue about allocating 8 word registers.
8357 ;; rD/rS = r5 is preferred, efficient form.
8358 (define_expand "movstrsi_8reg"
8359 [(parallel [(set (match_operand 0 "" "")
8360 (match_operand 1 "" ""))
8361 (use (match_operand 2 "" ""))
8362 (use (match_operand 3 "" ""))
8363 (clobber (reg:SI 5))
8364 (clobber (reg:SI 6))
8365 (clobber (reg:SI 7))
8366 (clobber (reg:SI 8))
8367 (clobber (reg:SI 9))
8368 (clobber (reg:SI 10))
8369 (clobber (reg:SI 11))
8370 (clobber (reg:SI 12))
8371 (clobber (match_scratch:SI 4 ""))])]
8372 "TARGET_STRING"
8373 "")
8375 (define_insn ""
8376 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8377 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8378 (use (match_operand:SI 2 "immediate_operand" "i"))
8379 (use (match_operand:SI 3 "immediate_operand" "i"))
8380 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8381 (clobber (reg:SI 6))
8382 (clobber (reg:SI 7))
8383 (clobber (reg:SI 8))
8384 (clobber (reg:SI 9))
8385 (clobber (reg:SI 10))
8386 (clobber (reg:SI 11))
8387 (clobber (reg:SI 12))
8388 (clobber (match_scratch:SI 5 "=q"))]
8389 "TARGET_STRING && TARGET_POWER
8390 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8391 || INTVAL (operands[2]) == 0)
8392 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8393 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8394 && REGNO (operands[4]) == 5"
8395 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8396 [(set_attr "type" "load")
8397 (set_attr "length" "8")])
8399 (define_insn ""
8400 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8401 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8402 (use (match_operand:SI 2 "immediate_operand" "i"))
8403 (use (match_operand:SI 3 "immediate_operand" "i"))
8404 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8405 (clobber (reg:SI 6))
8406 (clobber (reg:SI 7))
8407 (clobber (reg:SI 8))
8408 (clobber (reg:SI 9))
8409 (clobber (reg:SI 10))
8410 (clobber (reg:SI 11))
8411 (clobber (reg:SI 12))
8412 (clobber (match_scratch:SI 5 "X"))]
8413 "TARGET_STRING && ! TARGET_POWER
8414 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8415 || INTVAL (operands[2]) == 0)
8416 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8417 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8418 && REGNO (operands[4]) == 5"
8419 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8420 [(set_attr "type" "load")
8421 (set_attr "length" "8")])
8423 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8424 ;; register allocator doesn't have a clue about allocating 6 word registers.
8425 ;; rD/rS = r5 is preferred, efficient form.
8426 (define_expand "movstrsi_6reg"
8427 [(parallel [(set (match_operand 0 "" "")
8428 (match_operand 1 "" ""))
8429 (use (match_operand 2 "" ""))
8430 (use (match_operand 3 "" ""))
8431 (clobber (reg:SI 5))
8432 (clobber (reg:SI 6))
8433 (clobber (reg:SI 7))
8434 (clobber (reg:SI 8))
8435 (clobber (reg:SI 9))
8436 (clobber (reg:SI 10))
8437 (clobber (match_scratch:SI 4 ""))])]
8438 "TARGET_STRING"
8439 "")
8441 (define_insn ""
8442 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8443 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8444 (use (match_operand:SI 2 "immediate_operand" "i"))
8445 (use (match_operand:SI 3 "immediate_operand" "i"))
8446 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8447 (clobber (reg:SI 6))
8448 (clobber (reg:SI 7))
8449 (clobber (reg:SI 8))
8450 (clobber (reg:SI 9))
8451 (clobber (reg:SI 10))
8452 (clobber (match_scratch:SI 5 "=q"))]
8453 "TARGET_STRING && TARGET_POWER
8454 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8455 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8456 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8457 && REGNO (operands[4]) == 5"
8458 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8459 [(set_attr "type" "load")
8460 (set_attr "length" "8")])
8462 (define_insn ""
8463 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8464 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8465 (use (match_operand:SI 2 "immediate_operand" "i"))
8466 (use (match_operand:SI 3 "immediate_operand" "i"))
8467 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8468 (clobber (reg:SI 6))
8469 (clobber (reg:SI 7))
8470 (clobber (reg:SI 8))
8471 (clobber (reg:SI 9))
8472 (clobber (reg:SI 10))
8473 (clobber (match_scratch:SI 5 "X"))]
8474 "TARGET_STRING && ! TARGET_POWER
8475 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8476 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8477 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8478 && REGNO (operands[4]) == 5"
8479 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8480 [(set_attr "type" "load")
8481 (set_attr "length" "8")])
8483 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8484 ;; problems with TImode.
8485 ;; rD/rS = r5 is preferred, efficient form.
8486 (define_expand "movstrsi_4reg"
8487 [(parallel [(set (match_operand 0 "" "")
8488 (match_operand 1 "" ""))
8489 (use (match_operand 2 "" ""))
8490 (use (match_operand 3 "" ""))
8491 (clobber (reg:SI 5))
8492 (clobber (reg:SI 6))
8493 (clobber (reg:SI 7))
8494 (clobber (reg:SI 8))
8495 (clobber (match_scratch:SI 4 ""))])]
8496 "TARGET_STRING"
8497 "")
8499 (define_insn ""
8500 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8501 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8502 (use (match_operand:SI 2 "immediate_operand" "i"))
8503 (use (match_operand:SI 3 "immediate_operand" "i"))
8504 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8505 (clobber (reg:SI 6))
8506 (clobber (reg:SI 7))
8507 (clobber (reg:SI 8))
8508 (clobber (match_scratch:SI 5 "=q"))]
8509 "TARGET_STRING && TARGET_POWER
8510 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8511 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8512 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8513 && REGNO (operands[4]) == 5"
8514 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8515 [(set_attr "type" "load")
8516 (set_attr "length" "8")])
8518 (define_insn ""
8519 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8520 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8521 (use (match_operand:SI 2 "immediate_operand" "i"))
8522 (use (match_operand:SI 3 "immediate_operand" "i"))
8523 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8524 (clobber (reg:SI 6))
8525 (clobber (reg:SI 7))
8526 (clobber (reg:SI 8))
8527 (clobber (match_scratch:SI 5 "X"))]
8528 "TARGET_STRING && ! TARGET_POWER
8529 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8530 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8531 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8532 && REGNO (operands[4]) == 5"
8533 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8534 [(set_attr "type" "load")
8535 (set_attr "length" "8")])
8537 ;; Move up to 8 bytes at a time.
8538 (define_expand "movstrsi_2reg"
8539 [(parallel [(set (match_operand 0 "" "")
8540 (match_operand 1 "" ""))
8541 (use (match_operand 2 "" ""))
8542 (use (match_operand 3 "" ""))
8543 (clobber (match_scratch:DI 4 ""))
8544 (clobber (match_scratch:SI 5 ""))])]
8545 "TARGET_STRING && ! TARGET_POWERPC64"
8546 "")
8548 (define_insn ""
8549 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8550 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8551 (use (match_operand:SI 2 "immediate_operand" "i"))
8552 (use (match_operand:SI 3 "immediate_operand" "i"))
8553 (clobber (match_scratch:DI 4 "=&r"))
8554 (clobber (match_scratch:SI 5 "=q"))]
8555 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8556 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8557 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8558 [(set_attr "type" "load")
8559 (set_attr "length" "8")])
8561 (define_insn ""
8562 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8563 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8564 (use (match_operand:SI 2 "immediate_operand" "i"))
8565 (use (match_operand:SI 3 "immediate_operand" "i"))
8566 (clobber (match_scratch:DI 4 "=&r"))
8567 (clobber (match_scratch:SI 5 "X"))]
8568 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8569 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8570 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8571 [(set_attr "type" "load")
8572 (set_attr "length" "8")])
8574 ;; Move up to 4 bytes at a time.
8575 (define_expand "movstrsi_1reg"
8576 [(parallel [(set (match_operand 0 "" "")
8577 (match_operand 1 "" ""))
8578 (use (match_operand 2 "" ""))
8579 (use (match_operand 3 "" ""))
8580 (clobber (match_scratch:SI 4 ""))
8581 (clobber (match_scratch:SI 5 ""))])]
8582 "TARGET_STRING"
8583 "")
8585 (define_insn ""
8586 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8587 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8588 (use (match_operand:SI 2 "immediate_operand" "i"))
8589 (use (match_operand:SI 3 "immediate_operand" "i"))
8590 (clobber (match_scratch:SI 4 "=&r"))
8591 (clobber (match_scratch:SI 5 "=q"))]
8592 "TARGET_STRING && TARGET_POWER
8593 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8594 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8595 [(set_attr "type" "load")
8596 (set_attr "length" "8")])
8598 (define_insn ""
8599 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8600 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8601 (use (match_operand:SI 2 "immediate_operand" "i"))
8602 (use (match_operand:SI 3 "immediate_operand" "i"))
8603 (clobber (match_scratch:SI 4 "=&r"))
8604 (clobber (match_scratch:SI 5 "X"))]
8605 "TARGET_STRING && ! TARGET_POWER
8606 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8607 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8608 [(set_attr "type" "load")
8609 (set_attr "length" "8")])
8611 \f
8612 ;; Define insns that do load or store with update. Some of these we can
8613 ;; get by using pre-decrement or pre-increment, but the hardware can also
8614 ;; do cases where the increment is not the size of the object.
8615 ;;
8616 ;; In all these cases, we use operands 0 and 1 for the register being
8617 ;; incremented because those are the operands that local-alloc will
8618 ;; tie and these are the pair most likely to be tieable (and the ones
8619 ;; that will benefit the most).
8621 (define_insn "*movdi_update1"
8622 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8623 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8624 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
8625 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8626 (plus:DI (match_dup 1) (match_dup 2)))]
8627 "TARGET_POWERPC64 && TARGET_UPDATE"
8628 "@
8629 ldux %3,%0,%2
8630 ldu %3,%2(%0)"
8631 [(set_attr "type" "load")])
8633 (define_insn "*movdi_update2"
8634 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8635 (sign_extend:DI
8636 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8637 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8638 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8639 (plus:DI (match_dup 1) (match_dup 2)))]
8640 "TARGET_POWERPC64"
8641 "lwaux %3,%0,%2"
8642 [(set_attr "type" "load")])
8644 (define_insn "movdi_update"
8645 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8646 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
8647 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8648 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8649 (plus:DI (match_dup 1) (match_dup 2)))]
8650 "TARGET_POWERPC64 && TARGET_UPDATE"
8651 "@
8652 stdux %3,%0,%2
8653 stdu %3,%2(%0)"
8654 [(set_attr "type" "store")])
8656 (define_insn "*movsi_update1"
8657 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8658 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8659 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8660 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8661 (plus:SI (match_dup 1) (match_dup 2)))]
8662 ""
8663 "@
8664 {lux|lwzux} %3,%0,%2
8665 {lu|lwzu} %3,%2(%0)"
8666 [(set_attr "type" "load")])
8668 (define_insn "movsi_update"
8669 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8670 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8671 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8672 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8673 (plus:SI (match_dup 1) (match_dup 2)))]
8674 "TARGET_UPDATE"
8675 "@
8676 {stux|stwux} %3,%0,%2
8677 {stu|stwu} %3,%2(%0)"
8678 [(set_attr "type" "store")])
8680 (define_insn "*movhi_update"
8681 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8682 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8683 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8684 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8685 (plus:SI (match_dup 1) (match_dup 2)))]
8686 "TARGET_UPDATE"
8687 "@
8688 lhzux %3,%0,%2
8689 lhzu %3,%2(%0)"
8690 [(set_attr "type" "load")])
8692 (define_insn "*movhi_update2"
8693 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8694 (zero_extend:SI
8695 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8696 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8697 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8698 (plus:SI (match_dup 1) (match_dup 2)))]
8699 "TARGET_UPDATE"
8700 "@
8701 lhzux %3,%0,%2
8702 lhzu %3,%2(%0)"
8703 [(set_attr "type" "load")])
8705 (define_insn "*movhi_update3"
8706 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8707 (sign_extend:SI
8708 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8709 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8710 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8711 (plus:SI (match_dup 1) (match_dup 2)))]
8712 "TARGET_UPDATE"
8713 "@
8714 lhaux %3,%0,%2
8715 lhau %3,%2(%0)"
8716 [(set_attr "type" "load")])
8718 (define_insn "*movhi_update4"
8719 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8720 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8721 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8722 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8723 (plus:SI (match_dup 1) (match_dup 2)))]
8724 "TARGET_UPDATE"
8725 "@
8726 sthux %3,%0,%2
8727 sthu %3,%2(%0)"
8728 [(set_attr "type" "store")])
8730 (define_insn "*movqi_update1"
8731 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8732 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8733 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8734 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8735 (plus:SI (match_dup 1) (match_dup 2)))]
8736 "TARGET_UPDATE"
8737 "@
8738 lbzux %3,%0,%2
8739 lbzu %3,%2(%0)"
8740 [(set_attr "type" "load")])
8742 (define_insn "*movqi_update2"
8743 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8744 (zero_extend:SI
8745 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8746 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8747 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8748 (plus:SI (match_dup 1) (match_dup 2)))]
8749 "TARGET_UPDATE"
8750 "@
8751 lbzux %3,%0,%2
8752 lbzu %3,%2(%0)"
8753 [(set_attr "type" "load")])
8755 (define_insn "*movqi_update3"
8756 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8757 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8758 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8759 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8760 (plus:SI (match_dup 1) (match_dup 2)))]
8761 "TARGET_UPDATE"
8762 "@
8763 stbux %3,%0,%2
8764 stbu %3,%2(%0)"
8765 [(set_attr "type" "store")])
8767 (define_insn "*movsf_update1"
8768 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
8769 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8770 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8771 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8772 (plus:SI (match_dup 1) (match_dup 2)))]
8773 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8774 "@
8775 lfsux %3,%0,%2
8776 lfsu %3,%2(%0)"
8777 [(set_attr "type" "fpload")])
8779 (define_insn "*movsf_update2"
8780 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8781 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8782 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8783 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8784 (plus:SI (match_dup 1) (match_dup 2)))]
8785 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8786 "@
8787 stfsux %3,%0,%2
8788 stfsu %3,%2(%0)"
8789 [(set_attr "type" "fpstore")])
8791 (define_insn "*movsf_update3"
8792 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8793 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8794 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8795 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8796 (plus:SI (match_dup 1) (match_dup 2)))]
8797 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
8798 "@
8799 {lux|lwzux} %3,%0,%2
8800 {lu|lwzu} %3,%2(%0)"
8801 [(set_attr "type" "load")])
8803 (define_insn "*movsf_update4"
8804 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8805 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8806 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
8807 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8808 (plus:SI (match_dup 1) (match_dup 2)))]
8809 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
8810 "@
8811 {stux|stwux} %3,%0,%2
8812 {stu|stwu} %3,%2(%0)"
8813 [(set_attr "type" "store")])
8815 (define_insn "*movdf_update1"
8816 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
8817 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8818 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8819 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8820 (plus:SI (match_dup 1) (match_dup 2)))]
8821 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8822 "@
8823 lfdux %3,%0,%2
8824 lfdu %3,%2(%0)"
8825 [(set_attr "type" "fpload")])
8827 (define_insn "*movdf_update2"
8828 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8829 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8830 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
8831 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8832 (plus:SI (match_dup 1) (match_dup 2)))]
8833 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8834 "@
8835 stfdux %3,%0,%2
8836 stfdu %3,%2(%0)"
8837 [(set_attr "type" "fpstore")])
8839 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
8841 (define_peephole
8842 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8843 (match_operand:DF 1 "memory_operand" ""))
8844 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
8845 (match_operand:DF 3 "memory_operand" ""))]
8846 "TARGET_POWER2
8847 && TARGET_HARD_FLOAT
8848 && registers_ok_for_quad_peep (operands[0], operands[2])
8849 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
8850 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
8851 "lfq%U1%X1 %0,%1")
8853 (define_peephole
8854 [(set (match_operand:DF 0 "memory_operand" "")
8855 (match_operand:DF 1 "gpc_reg_operand" "f"))
8856 (set (match_operand:DF 2 "memory_operand" "")
8857 (match_operand:DF 3 "gpc_reg_operand" "f"))]
8858 "TARGET_POWER2
8859 && TARGET_HARD_FLOAT
8860 && registers_ok_for_quad_peep (operands[1], operands[3])
8861 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
8862 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
8863 "stfq%U0%X0 %1,%0")
8864 \f
8865 ;; Next come insns related to the calling sequence.
8866 ;;
8867 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
8868 ;; We move the back-chain and decrement the stack pointer.
8870 (define_expand "allocate_stack"
8871 [(set (match_operand 0 "gpc_reg_operand" "=r")
8872 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
8873 (set (reg 1)
8874 (minus (reg 1) (match_dup 1)))]
8875 ""
8876 "
8877 { rtx chain = gen_reg_rtx (Pmode);
8878 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8879 rtx neg_op0;
8881 emit_move_insn (chain, stack_bot);
8883 /* Check stack bounds if necessary. */
8884 if (current_function_limit_stack)
8885 {
8886 rtx available;
8887 available = expand_binop (Pmode, sub_optab,
8888 stack_pointer_rtx, stack_limit_rtx,
8889 NULL_RTX, 1, OPTAB_WIDEN);
8890 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
8891 }
8893 if (GET_CODE (operands[1]) != CONST_INT
8894 || INTVAL (operands[1]) < -32767
8895 || INTVAL (operands[1]) > 32768)
8896 {
8897 neg_op0 = gen_reg_rtx (Pmode);
8898 if (TARGET_32BIT)
8899 emit_insn (gen_negsi2 (neg_op0, operands[1]));
8900 else
8901 emit_insn (gen_negdi2 (neg_op0, operands[1]));
8902 }
8903 else
8904 neg_op0 = GEN_INT (- INTVAL (operands[1]));
8906 if (TARGET_UPDATE)
8907 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
8908 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
8910 else
8911 {
8912 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
8913 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
8914 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
8915 }
8917 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8918 DONE;
8919 }")
8921 ;; These patterns say how to save and restore the stack pointer. We need not
8922 ;; save the stack pointer at function level since we are careful to
8923 ;; preserve the backchain. At block level, we have to restore the backchain
8924 ;; when we restore the stack pointer.
8925 ;;
8926 ;; For nonlocal gotos, we must save both the stack pointer and its
8927 ;; backchain and restore both. Note that in the nonlocal case, the
8928 ;; save area is a memory location.
8930 (define_expand "save_stack_function"
8931 [(match_operand 0 "any_operand" "")
8932 (match_operand 1 "any_operand" "")]
8933 ""
8934 "DONE;")
8936 (define_expand "restore_stack_function"
8937 [(match_operand 0 "any_operand" "")
8938 (match_operand 1 "any_operand" "")]
8939 ""
8940 "DONE;")
8942 (define_expand "restore_stack_block"
8943 [(use (match_operand 0 "register_operand" ""))
8944 (set (match_dup 2) (match_dup 3))
8945 (set (match_dup 0) (match_operand 1 "register_operand" ""))
8946 (set (match_dup 3) (match_dup 2))]
8947 ""
8948 "
8949 {
8950 operands[2] = gen_reg_rtx (Pmode);
8951 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
8952 }")
8954 (define_expand "save_stack_nonlocal"
8955 [(match_operand 0 "memory_operand" "")
8956 (match_operand 1 "register_operand" "")]
8957 ""
8958 "
8959 {
8960 rtx temp = gen_reg_rtx (Pmode);
8962 /* Copy the backchain to the first word, sp to the second. */
8963 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
8964 emit_move_insn (operand_subword (operands[0], 0, 0,
8965 (TARGET_32BIT ? DImode : TImode)),
8966 temp);
8967 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
8968 operands[1]);
8969 DONE;
8970 }")
8972 (define_expand "restore_stack_nonlocal"
8973 [(match_operand 0 "register_operand" "")
8974 (match_operand 1 "memory_operand" "")]
8975 ""
8976 "
8977 {
8978 rtx temp = gen_reg_rtx (Pmode);
8980 /* Restore the backchain from the first word, sp from the second. */
8981 emit_move_insn (temp,
8982 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
8983 emit_move_insn (operands[0],
8984 operand_subword (operands[1], 1, 0,
8985 (TARGET_32BIT ? DImode : TImode)));
8986 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
8987 DONE;
8988 }")
8989 \f
8990 ;; TOC register handling.
8992 ;; Code to initialize the TOC register...
8994 (define_insn "load_toc_aix_si"
8995 [(set (match_operand:SI 0 "register_operand" "=r")
8996 (unspec:SI [(const_int 0)] 7))]
8997 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
8998 "*
8999 {
9000 char buf[30];
9001 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9002 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9003 operands[2] = gen_rtx_REG (Pmode, 2);
9004 return \"{l|lwz} %0,%1(%2)\";
9005 }"
9006 [(set_attr "type" "load")])
9008 (define_insn "load_toc_aix_di"
9009 [(set (match_operand:DI 0 "register_operand" "=r")
9010 (unspec:DI [(const_int 0)] 7))]
9011 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9012 "*
9013 {
9014 char buf[30];
9015 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9016 if (TARGET_ELF)
9017 strcat (buf, \"@toc\");
9018 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9019 operands[2] = gen_rtx_REG (Pmode, 2);
9020 return \"ld %0,%1(%2)\";
9021 }"
9022 [(set_attr "type" "load")])
9024 (define_insn "load_toc_v4_pic_si"
9025 [(set (match_operand:SI 0 "register_operand" "=l")
9026 (unspec:SI [(const_int 0)] 7))]
9027 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1
9028 && TARGET_32BIT"
9029 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9030 [(set_attr "type" "branch")
9031 (set_attr "length" "4")])
9033 (define_insn "load_toc_v4_PIC_1"
9034 [(set (match_operand:SI 0 "register_operand" "=l")
9035 (match_operand:SI 1 "immediate_operand" "s"))
9036 (unspec [(match_dup 1)] 7)]
9037 "TARGET_ELF && flag_pic == 2"
9038 "bl %1\\n%1:"
9039 [(set_attr "type" "branch")
9040 (set_attr "length" "4")])
9042 (define_insn "load_toc_v4_PIC_1b"
9043 [(set (match_operand:SI 0 "register_operand" "=l")
9044 (match_operand:SI 1 "immediate_operand" "s"))
9045 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
9046 "TARGET_ELF && flag_pic == 2"
9047 "bl %1\\n\\t.long %2-%1+4\\n%1:"
9048 [(set_attr "type" "branch")
9049 (set_attr "length" "8")])
9051 (define_insn "load_toc_v4_PIC_2"
9052 [(set (match_operand:SI 0 "register_operand" "=r")
9053 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
9054 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9055 (match_operand:SI 3 "immediate_operand" "s")))))]
9056 "TARGET_ELF && flag_pic == 2"
9057 "{l|lwz} %0,%2-%3(%1)"
9058 [(set_attr "type" "load")])
9060 (define_insn "load_macho_picbase"
9061 [(set (match_operand:SI 0 "register_operand" "=l")
9062 (unspec:SI [(const_int 0)] 15))]
9063 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
9064 "*
9065 {
9066 #if TARGET_MACHO
9067 char *picbase = machopic_function_base_name ();
9068 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
9069 #endif
9070 return \"bcl 20,31,%1\\n%1:\";
9071 }"
9072 [(set_attr "type" "branch")
9073 (set_attr "length" "4")])
9075 ;; If the TOC is shared over a translation unit, as happens with all
9076 ;; the kinds of PIC that we support, we need to restore the TOC
9077 ;; pointer only when jumping over units of translation.
9079 (define_expand "builtin_setjmp_receiver"
9080 [(use (label_ref (match_operand 0 "" "")))]
9081 "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1)
9082 || (TARGET_TOC && TARGET_MINIMAL_TOC)"
9083 "
9084 {
9085 rs6000_emit_load_toc_table (FALSE);
9086 DONE;
9087 }")
9088 \f
9089 ;; A function pointer under AIX is a pointer to a data area whose first word
9090 ;; contains the actual address of the function, whose second word contains a
9091 ;; pointer to its TOC, and whose third word contains a value to place in the
9092 ;; static chain register (r11). Note that if we load the static chain, our
9093 ;; "trampoline" need not have any executable code.
9095 (define_expand "call_indirect_aix32"
9096 [(set (match_dup 2)
9097 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9098 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9099 (reg:SI 2))
9100 (set (reg:SI 2)
9101 (mem:SI (plus:SI (match_dup 0)
9102 (const_int 4))))
9103 (set (reg:SI 11)
9104 (mem:SI (plus:SI (match_dup 0)
9105 (const_int 8))))
9106 (parallel [(call (mem:SI (match_dup 2))
9107 (match_operand 1 "" ""))
9108 (use (reg:SI 2))
9109 (use (reg:SI 11))
9110 (set (reg:SI 2)
9111 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9112 (clobber (scratch:SI))])]
9113 "TARGET_32BIT"
9114 "
9115 { operands[2] = gen_reg_rtx (SImode); }")
9117 (define_expand "call_indirect_aix64"
9118 [(set (match_dup 2)
9119 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9120 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9121 (reg:DI 2))
9122 (set (reg:DI 2)
9123 (mem:DI (plus:DI (match_dup 0)
9124 (const_int 8))))
9125 (set (reg:DI 11)
9126 (mem:DI (plus:DI (match_dup 0)
9127 (const_int 16))))
9128 (parallel [(call (mem:SI (match_dup 2))
9129 (match_operand 1 "" ""))
9130 (use (reg:DI 2))
9131 (use (reg:DI 11))
9132 (set (reg:DI 2)
9133 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9134 (clobber (scratch:SI))])]
9135 "TARGET_64BIT"
9136 "
9137 { operands[2] = gen_reg_rtx (DImode); }")
9139 (define_expand "call_value_indirect_aix32"
9140 [(set (match_dup 3)
9141 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9142 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9143 (reg:SI 2))
9144 (set (reg:SI 2)
9145 (mem:SI (plus:SI (match_dup 1)
9146 (const_int 4))))
9147 (set (reg:SI 11)
9148 (mem:SI (plus:SI (match_dup 1)
9149 (const_int 8))))
9150 (parallel [(set (match_operand 0 "" "")
9151 (call (mem:SI (match_dup 3))
9152 (match_operand 2 "" "")))
9153 (use (reg:SI 2))
9154 (use (reg:SI 11))
9155 (set (reg:SI 2)
9156 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9157 (clobber (scratch:SI))])]
9158 "TARGET_32BIT"
9159 "
9160 { operands[3] = gen_reg_rtx (SImode); }")
9162 (define_expand "call_value_indirect_aix64"
9163 [(set (match_dup 3)
9164 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9165 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9166 (reg:DI 2))
9167 (set (reg:DI 2)
9168 (mem:DI (plus:DI (match_dup 1)
9169 (const_int 8))))
9170 (set (reg:DI 11)
9171 (mem:DI (plus:DI (match_dup 1)
9172 (const_int 16))))
9173 (parallel [(set (match_operand 0 "" "")
9174 (call (mem:SI (match_dup 3))
9175 (match_operand 2 "" "")))
9176 (use (reg:DI 2))
9177 (use (reg:DI 11))
9178 (set (reg:DI 2)
9179 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9180 (clobber (scratch:SI))])]
9181 "TARGET_64BIT"
9182 "
9183 { operands[3] = gen_reg_rtx (DImode); }")
9185 ;; Now the definitions for the call and call_value insns
9186 (define_expand "call"
9187 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9188 (match_operand 1 "" ""))
9189 (use (match_operand 2 "" ""))
9190 (clobber (scratch:SI))])]
9191 ""
9192 "
9193 {
9194 #if TARGET_MACHO
9195 if (flag_pic)
9196 operands[0] = machopic_indirect_call_target (operands[0]);
9197 #endif
9199 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
9200 abort ();
9202 operands[0] = XEXP (operands[0], 0);
9204 if (GET_CODE (operands[0]) != SYMBOL_REF
9205 || (INTVAL (operands[2]) & CALL_LONG) != 0)
9206 {
9207 if (INTVAL (operands[2]) & CALL_LONG)
9208 operands[0] = rs6000_longcall_ref (operands[0]);
9210 if (DEFAULT_ABI == ABI_V4
9211 || DEFAULT_ABI == ABI_AIX_NODESC
9212 || DEFAULT_ABI == ABI_DARWIN
9213 || DEFAULT_ABI == ABI_SOLARIS)
9214 operands[0] = force_reg (Pmode, operands[0]);
9216 else if (DEFAULT_ABI == ABI_AIX)
9217 {
9218 /* AIX function pointers are really pointers to a three word
9219 area. */
9220 emit_call_insn (TARGET_32BIT
9221 ? gen_call_indirect_aix32 (force_reg (SImode,
9222 operands[0]),
9223 operands[1])
9224 : gen_call_indirect_aix64 (force_reg (DImode,
9225 operands[0]),
9226 operands[1]));
9227 DONE;
9228 }
9229 else
9230 abort ();
9231 }
9232 }")
9234 (define_expand "call_value"
9235 [(parallel [(set (match_operand 0 "" "")
9236 (call (mem:SI (match_operand 1 "address_operand" ""))
9237 (match_operand 2 "" "")))
9238 (use (match_operand 3 "" ""))
9239 (clobber (scratch:SI))])]
9240 ""
9241 "
9242 {
9243 #if TARGET_MACHO
9244 if (flag_pic)
9245 operands[1] = machopic_indirect_call_target (operands[1]);
9246 #endif
9248 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
9249 abort ();
9251 operands[1] = XEXP (operands[1], 0);
9253 if (GET_CODE (operands[1]) != SYMBOL_REF
9254 || (INTVAL (operands[3]) & CALL_LONG) != 0)
9255 {
9256 if (INTVAL (operands[3]) & CALL_LONG)
9257 operands[1] = rs6000_longcall_ref (operands[1]);
9259 if (DEFAULT_ABI == ABI_V4
9260 || DEFAULT_ABI == ABI_AIX_NODESC
9261 || DEFAULT_ABI == ABI_DARWIN
9262 || DEFAULT_ABI == ABI_SOLARIS)
9263 operands[0] = force_reg (Pmode, operands[0]);
9265 else if (DEFAULT_ABI == ABI_AIX)
9266 {
9267 /* AIX function pointers are really pointers to a three word
9268 area. */
9269 emit_call_insn (TARGET_32BIT
9270 ? gen_call_value_indirect_aix32 (operands[0],
9271 force_reg (SImode,
9272 operands[1]),
9273 operands[2])
9274 : gen_call_value_indirect_aix64 (operands[0],
9275 force_reg (DImode,
9276 operands[1]),
9277 operands[2]));
9278 DONE;
9279 }
9280 else
9281 abort ();
9282 }
9283 }")
9285 ;; Call to function in current module. No TOC pointer reload needed.
9286 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9287 ;; either the function was not prototyped, or it was prototyped as a
9288 ;; variable argument function. It is > 0 if FP registers were passed
9289 ;; and < 0 if they were not.
9291 (define_insn "*call_local32"
9292 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9293 (match_operand 1 "" "g,g"))
9294 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9295 (clobber (match_scratch:SI 3 "=l,l"))]
9296 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9297 "*
9298 {
9299 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9300 output_asm_insn (\"crxor 6,6,6\", operands);
9302 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9303 output_asm_insn (\"creqv 6,6,6\", operands);
9305 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9306 }"
9307 [(set_attr "type" "branch")
9308 (set_attr "length" "4,8")])
9310 (define_insn "*call_local64"
9311 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9312 (match_operand 1 "" "g,g"))
9313 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9314 (clobber (match_scratch:SI 3 "=l,l"))]
9315 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9316 "*
9317 {
9318 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9319 output_asm_insn (\"crxor 6,6,6\", operands);
9321 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9322 output_asm_insn (\"creqv 6,6,6\", operands);
9324 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9325 }"
9326 [(set_attr "type" "branch")
9327 (set_attr "length" "4,8")])
9329 (define_insn "*call_value_local32"
9330 [(set (match_operand 0 "" "=fg,fg")
9331 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9332 (match_operand 2 "" "g,g")))
9333 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9334 (clobber (match_scratch:SI 4 "=l,l"))]
9335 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9336 "*
9337 {
9338 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9339 output_asm_insn (\"crxor 6,6,6\", operands);
9341 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9342 output_asm_insn (\"creqv 6,6,6\", operands);
9344 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9345 }"
9346 [(set_attr "type" "branch")
9347 (set_attr "length" "4,8")])
9350 (define_insn "*call_value_local64"
9351 [(set (match_operand 0 "" "=fg,fg")
9352 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9353 (match_operand 2 "" "g,g")))
9354 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9355 (clobber (match_scratch:SI 4 "=l,l"))]
9356 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9357 "*
9358 {
9359 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9360 output_asm_insn (\"crxor 6,6,6\", operands);
9362 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9363 output_asm_insn (\"creqv 6,6,6\", operands);
9365 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9366 }"
9367 [(set_attr "type" "branch")
9368 (set_attr "length" "4,8")])
9370 ;; Call to function which may be in another module. Restore the TOC
9371 ;; pointer (r2) after the call unless this is System V.
9372 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9373 ;; either the function was not prototyped, or it was prototyped as a
9374 ;; variable argument function. It is > 0 if FP registers were passed
9375 ;; and < 0 if they were not.
9377 (define_insn "*call_indirect_nonlocal_aix32"
9378 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
9379 (match_operand 1 "" "g"))
9380 (use (reg:SI 2))
9381 (use (reg:SI 11))
9382 (set (reg:SI 2)
9383 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9384 (clobber (match_scratch:SI 2 "=l"))]
9385 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9386 "b%T0l\;{l|lwz} 2,20(1)"
9387 [(set_attr "type" "jmpreg")
9388 (set_attr "length" "8")])
9390 (define_insn "*call_nonlocal_aix32"
9391 [(call (mem:SI (match_operand:SI 0 "call_operand" "s"))
9392 (match_operand 1 "" "g"))
9393 (use (match_operand:SI 2 "immediate_operand" "O"))
9394 (clobber (match_scratch:SI 3 "=l"))]
9395 "TARGET_32BIT
9396 && DEFAULT_ABI == ABI_AIX
9397 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9398 "bl %z0\;%."
9399 [(set_attr "type" "branch")
9400 (set_attr "length" "8")])
9402 (define_insn "*call_indirect_nonlocal_aix64"
9403 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
9404 (match_operand 1 "" "g"))
9405 (use (reg:DI 2))
9406 (use (reg:DI 11))
9407 (set (reg:DI 2)
9408 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9409 (clobber (match_scratch:SI 2 "=l"))]
9410 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9411 "b%T0l\;ld 2,40(1)"
9412 [(set_attr "type" "jmpreg")
9413 (set_attr "length" "8")])
9415 (define_insn "*call_nonlocal_aix64"
9416 [(call (mem:SI (match_operand:DI 0 "call_operand" "s"))
9417 (match_operand 1 "" "g"))
9418 (use (match_operand:SI 2 "immediate_operand" "O"))
9419 (clobber (match_scratch:SI 3 "=l"))]
9420 "TARGET_64BIT
9421 && DEFAULT_ABI == ABI_AIX
9422 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9423 "bl %z0\;%."
9424 [(set_attr "type" "branch")
9425 (set_attr "length" "8")])
9427 (define_insn "*call_value_indirect_nonlocal_aix32"
9428 [(set (match_operand 0 "" "=fg")
9429 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
9430 (match_operand 2 "" "g")))
9431 (use (reg:SI 2))
9432 (use (reg:SI 11))
9433 (set (reg:SI 2)
9434 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9435 (clobber (match_scratch:SI 3 "=l"))]
9436 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9437 "b%T1l\;{l|lwz} 2,20(1)"
9438 [(set_attr "type" "jmpreg")
9439 (set_attr "length" "8")])
9441 (define_insn "*call_value_nonlocal_aix32"
9442 [(set (match_operand 0 "" "=fg")
9443 (call (mem:SI (match_operand:SI 1 "call_operand" "s"))
9444 (match_operand 2 "" "g")))
9445 (use (match_operand:SI 3 "immediate_operand" "O"))
9446 (clobber (match_scratch:SI 4 "=l"))]
9447 "TARGET_32BIT
9448 && DEFAULT_ABI == ABI_AIX
9449 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9450 "bl %z1\;%."
9451 [(set_attr "type" "branch")
9452 (set_attr "length" "8")])
9454 (define_insn "*call_value_indirect_nonlocal_aix64"
9455 [(set (match_operand 0 "" "=fg")
9456 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
9457 (match_operand 2 "" "g")))
9458 (use (reg:DI 2))
9459 (use (reg:DI 11))
9460 (set (reg:DI 2)
9461 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9462 (clobber (match_scratch:SI 3 "=l"))]
9463 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9464 "b%T1l\;ld 2,40(1)"
9465 [(set_attr "type" "jmpreg")
9466 (set_attr "length" "8")])
9468 (define_insn "*call_value_nonlocal_aix64"
9469 [(set (match_operand 0 "" "=fg")
9470 (call (mem:SI (match_operand:DI 1 "call_operand" "s"))
9471 (match_operand 2 "" "g")))
9472 (use (match_operand:SI 3 "immediate_operand" "O"))
9473 (clobber (match_scratch:SI 4 "=l"))]
9474 "TARGET_64BIT
9475 && DEFAULT_ABI == ABI_AIX
9476 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9477 "bl %z1\;%."
9478 [(set_attr "type" "branch")
9479 (set_attr "length" "8")])
9481 ;; A function pointer under System V is just a normal pointer
9482 ;; operands[0] is the function pointer
9483 ;; operands[1] is the stack size to clean up
9484 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9485 ;; which indicates how to set cr1
9487 (define_insn "*call_nonlocal_sysv"
9488 [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s"))
9489 (match_operand 1 "" "g,g,g,g"))
9490 (use (match_operand:SI 2 "immediate_operand" "O,n,O,n"))
9491 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
9492 "DEFAULT_ABI == ABI_AIX_NODESC
9493 || DEFAULT_ABI == ABI_V4
9494 || DEFAULT_ABI == ABI_DARWIN
9495 || DEFAULT_ABI == ABI_SOLARIS"
9496 "*
9497 {
9498 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9499 output_asm_insn (\"crxor 6,6,6\", operands);
9501 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9502 output_asm_insn (\"creqv 6,6,6\", operands);
9504 switch (which_alternative)
9505 {
9506 default:
9507 abort ();
9508 case 0:
9509 case 1:
9510 return \"b%T0l\";
9511 case 2:
9512 case 3:
9513 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
9514 }
9515 }"
9516 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
9517 (set_attr "length" "4,8,4,8")])
9519 (define_insn "*call_value_nonlocal_sysv"
9520 [(set (match_operand 0 "" "=fg,fg,fg,fg")
9521 (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s"))
9522 (match_operand 2 "" "g,g,g,g")))
9523 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
9524 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
9525 "DEFAULT_ABI == ABI_AIX_NODESC
9526 || DEFAULT_ABI == ABI_V4
9527 || DEFAULT_ABI == ABI_DARWIN
9528 || DEFAULT_ABI == ABI_SOLARIS"
9529 "*
9530 {
9531 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9532 output_asm_insn (\"crxor 6,6,6\", operands);
9534 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9535 output_asm_insn (\"creqv 6,6,6\", operands);
9537 switch (which_alternative)
9538 {
9539 default:
9540 abort ();
9541 case 0:
9542 case 1:
9543 return \"b%T1l\";
9544 case 2:
9545 case 3:
9546 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
9547 }
9548 }"
9549 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
9550 (set_attr "length" "4,8,4,8")])
9552 ;; Call subroutine returning any type.
9553 (define_expand "untyped_call"
9554 [(parallel [(call (match_operand 0 "" "")
9555 (const_int 0))
9556 (match_operand 1 "" "")
9557 (match_operand 2 "" "")])]
9558 ""
9559 "
9560 {
9561 int i;
9563 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
9565 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9566 {
9567 rtx set = XVECEXP (operands[2], 0, i);
9568 emit_move_insn (SET_DEST (set), SET_SRC (set));
9569 }
9571 /* The optimizer does not know that the call sets the function value
9572 registers we stored in the result block. We avoid problems by
9573 claiming that all hard registers are used and clobbered at this
9574 point. */
9575 emit_insn (gen_blockage ());
9577 DONE;
9578 }")
9580 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9581 ;; all of memory. This blocks insns from being moved across this point.
9583 (define_insn "blockage"
9584 [(unspec_volatile [(const_int 0)] 0)]
9585 ""
9586 "")
9587 \f
9588 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
9589 ;; signed & unsigned, and one type of branch.
9590 ;;
9591 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
9592 ;; insns, and branches. We store the operands of compares until we see
9593 ;; how it is used.
9594 (define_expand "cmpsi"
9595 [(set (cc0)
9596 (compare (match_operand:SI 0 "gpc_reg_operand" "")
9597 (match_operand:SI 1 "reg_or_short_operand" "")))]
9598 ""
9599 "
9600 {
9601 /* Take care of the possibility that operands[1] might be negative but
9602 this might be a logical operation. That insn doesn't exist. */
9603 if (GET_CODE (operands[1]) == CONST_INT
9604 && INTVAL (operands[1]) < 0)
9605 operands[1] = force_reg (SImode, operands[1]);
9607 rs6000_compare_op0 = operands[0];
9608 rs6000_compare_op1 = operands[1];
9609 rs6000_compare_fp_p = 0;
9610 DONE;
9611 }")
9613 (define_expand "cmpdi"
9614 [(set (cc0)
9615 (compare (match_operand:DI 0 "gpc_reg_operand" "")
9616 (match_operand:DI 1 "reg_or_short_operand" "")))]
9617 "TARGET_POWERPC64"
9618 "
9619 {
9620 /* Take care of the possibility that operands[1] might be negative but
9621 this might be a logical operation. That insn doesn't exist. */
9622 if (GET_CODE (operands[1]) == CONST_INT
9623 && INTVAL (operands[1]) < 0)
9624 operands[1] = force_reg (DImode, operands[1]);
9626 rs6000_compare_op0 = operands[0];
9627 rs6000_compare_op1 = operands[1];
9628 rs6000_compare_fp_p = 0;
9629 DONE;
9630 }")
9632 (define_expand "cmpsf"
9633 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
9634 (match_operand:SF 1 "gpc_reg_operand" "")))]
9635 "TARGET_HARD_FLOAT"
9636 "
9637 {
9638 rs6000_compare_op0 = operands[0];
9639 rs6000_compare_op1 = operands[1];
9640 rs6000_compare_fp_p = 1;
9641 DONE;
9642 }")
9644 (define_expand "cmpdf"
9645 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
9646 (match_operand:DF 1 "gpc_reg_operand" "")))]
9647 "TARGET_HARD_FLOAT"
9648 "
9649 {
9650 rs6000_compare_op0 = operands[0];
9651 rs6000_compare_op1 = operands[1];
9652 rs6000_compare_fp_p = 1;
9653 DONE;
9654 }")
9656 (define_expand "beq"
9657 [(use (match_operand 0 "" ""))]
9658 ""
9659 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
9661 (define_expand "bne"
9662 [(use (match_operand 0 "" ""))]
9663 ""
9664 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
9666 (define_expand "bge"
9667 [(use (match_operand 0 "" ""))]
9668 ""
9669 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
9671 (define_expand "bgt"
9672 [(use (match_operand 0 "" ""))]
9673 ""
9674 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
9676 (define_expand "ble"
9677 [(use (match_operand 0 "" ""))]
9678 ""
9679 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
9681 (define_expand "blt"
9682 [(use (match_operand 0 "" ""))]
9683 ""
9684 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
9686 (define_expand "bgeu"
9687 [(use (match_operand 0 "" ""))]
9688 ""
9689 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
9691 (define_expand "bgtu"
9692 [(use (match_operand 0 "" ""))]
9693 ""
9694 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
9696 (define_expand "bleu"
9697 [(use (match_operand 0 "" ""))]
9698 ""
9699 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
9701 (define_expand "bltu"
9702 [(use (match_operand 0 "" ""))]
9703 ""
9704 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
9706 (define_expand "bunordered"
9707 [(use (match_operand 0 "" ""))]
9708 ""
9709 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
9711 (define_expand "bordered"
9712 [(use (match_operand 0 "" ""))]
9713 ""
9714 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
9716 (define_expand "buneq"
9717 [(use (match_operand 0 "" ""))]
9718 ""
9719 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
9721 (define_expand "bunge"
9722 [(use (match_operand 0 "" ""))]
9723 ""
9724 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
9726 (define_expand "bungt"
9727 [(use (match_operand 0 "" ""))]
9728 ""
9729 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
9731 (define_expand "bunle"
9732 [(use (match_operand 0 "" ""))]
9733 ""
9734 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
9736 (define_expand "bunlt"
9737 [(use (match_operand 0 "" ""))]
9738 ""
9739 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
9741 (define_expand "bltgt"
9742 [(use (match_operand 0 "" ""))]
9743 ""
9744 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
9746 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
9747 ;; For SEQ, likewise, except that comparisons with zero should be done
9748 ;; with an scc insns. However, due to the order that combine see the
9749 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
9750 ;; the cases we don't want to handle.
9751 (define_expand "seq"
9752 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9753 ""
9754 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
9756 (define_expand "sne"
9757 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9758 ""
9759 "
9760 {
9761 if (! rs6000_compare_fp_p)
9762 FAIL;
9764 rs6000_emit_sCOND (NE, operands[0]);
9765 DONE;
9766 }")
9768 ;; A > 0 is best done using the portable sequence, so fail in that case.
9769 (define_expand "sgt"
9770 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9771 ""
9772 "
9773 {
9774 if (! rs6000_compare_fp_p
9775 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9776 FAIL;
9778 rs6000_emit_sCOND (GT, operands[0]);
9779 DONE;
9780 }")
9782 ;; A < 0 is best done in the portable way for A an integer.
9783 (define_expand "slt"
9784 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9785 ""
9786 "
9787 {
9788 if (! rs6000_compare_fp_p
9789 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9790 FAIL;
9792 rs6000_emit_sCOND (LT, operands[0]);
9793 DONE;
9794 }")
9796 ;; A >= 0 is best done the portable way for A an integer.
9797 (define_expand "sge"
9798 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9799 ""
9800 "
9801 {
9802 if (! rs6000_compare_fp_p
9803 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9804 FAIL;
9806 rs6000_emit_sCOND (GE, operands[0]);
9807 DONE;
9808 }")
9810 ;; A <= 0 is best done the portable way for A an integer.
9811 (define_expand "sle"
9812 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9813 ""
9814 "
9815 {
9816 if (! rs6000_compare_fp_p
9817 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9818 FAIL;
9820 rs6000_emit_sCOND (LE, operands[0]);
9821 DONE;
9822 }")
9824 (define_expand "sgtu"
9825 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9826 ""
9827 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
9829 (define_expand "sltu"
9830 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9831 ""
9832 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
9834 (define_expand "sgeu"
9835 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9836 ""
9837 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
9839 (define_expand "sleu"
9840 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9841 ""
9842 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
9843 \f
9844 ;; Here are the actual compare insns.
9845 (define_insn "*cmpsi_internal1"
9846 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
9847 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
9848 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9849 ""
9850 "{cmp%I2|cmpw%I2} %0,%1,%2"
9851 [(set_attr "type" "compare")])
9853 (define_insn "*cmpdi_internal1"
9854 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
9855 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
9856 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
9857 "TARGET_POWERPC64"
9858 "cmpd%I2 %0,%1,%2"
9859 [(set_attr "type" "compare")])
9861 ;; If we are comparing a register for equality with a large constant,
9862 ;; we can do this with an XOR followed by a compare. But we need a scratch
9863 ;; register for the result of the XOR.
9865 (define_split
9866 [(set (match_operand:CC 0 "cc_reg_operand" "")
9867 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
9868 (match_operand:SI 2 "non_short_cint_operand" "")))
9869 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
9870 "find_single_use (operands[0], insn, 0)
9871 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
9872 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
9873 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
9874 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
9875 "
9876 {
9877 /* Get the constant we are comparing against, C, and see what it looks like
9878 sign-extended to 16 bits. Then see what constant could be XOR'ed
9879 with C to get the sign-extended value. */
9881 HOST_WIDE_INT c = INTVAL (operands[2]);
9882 HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000);
9883 HOST_WIDE_INT xorv = c ^ sextc;
9885 operands[4] = GEN_INT (xorv);
9886 operands[5] = GEN_INT (sextc);
9887 }")
9889 (define_insn "*cmpsi_internal2"
9890 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
9891 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9892 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
9893 ""
9894 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
9895 [(set_attr "type" "compare")])
9897 (define_insn "*cmpdi_internal2"
9898 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
9899 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9900 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
9901 ""
9902 "cmpld%I2 %0,%1,%b2"
9903 [(set_attr "type" "compare")])
9905 ;; The following two insns don't exist as single insns, but if we provide
9906 ;; them, we can swap an add and compare, which will enable us to overlap more
9907 ;; of the required delay between a compare and branch. We generate code for
9908 ;; them by splitting.
9910 (define_insn ""
9911 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
9912 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
9913 (match_operand:SI 2 "short_cint_operand" "i")))
9914 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9915 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
9916 ""
9917 "#"
9918 [(set_attr "length" "8")])
9920 (define_insn ""
9921 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
9922 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9923 (match_operand:SI 2 "u_short_cint_operand" "i")))
9924 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9925 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
9926 ""
9927 "#"
9928 [(set_attr "length" "8")])
9930 (define_split
9931 [(set (match_operand:CC 3 "cc_reg_operand" "")
9932 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
9933 (match_operand:SI 2 "short_cint_operand" "")))
9934 (set (match_operand:SI 0 "gpc_reg_operand" "")
9935 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
9936 ""
9937 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
9938 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
9940 (define_split
9941 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
9942 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
9943 (match_operand:SI 2 "u_short_cint_operand" "")))
9944 (set (match_operand:SI 0 "gpc_reg_operand" "")
9945 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
9946 ""
9947 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
9948 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
9950 (define_insn "*cmpsf_internal1"
9951 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
9952 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
9953 (match_operand:SF 2 "gpc_reg_operand" "f")))]
9954 "TARGET_HARD_FLOAT"
9955 "fcmpu %0,%1,%2"
9956 [(set_attr "type" "fpcompare")])
9958 (define_insn "*cmpdf_internal1"
9959 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
9960 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
9961 (match_operand:DF 2 "gpc_reg_operand" "f")))]
9962 "TARGET_HARD_FLOAT"
9963 "fcmpu %0,%1,%2"
9964 [(set_attr "type" "fpcompare")])
9965 \f
9966 ;; Now we have the scc insns. We can do some combinations because of the
9967 ;; way the machine works.
9968 ;;
9969 ;; Note that this is probably faster if we can put an insn between the
9970 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
9971 ;; cases the insns below which don't use an intermediate CR field will
9972 ;; be used instead.
9973 (define_insn ""
9974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9975 (match_operator:SI 1 "scc_comparison_operator"
9976 [(match_operand 2 "cc_reg_operand" "y")
9977 (const_int 0)]))]
9978 ""
9979 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
9980 [(set_attr "length" "12")])
9982 (define_insn ""
9983 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9984 (match_operator:DI 1 "scc_comparison_operator"
9985 [(match_operand 2 "cc_reg_operand" "y")
9986 (const_int 0)]))]
9987 "TARGET_POWERPC64"
9988 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
9989 [(set_attr "length" "12")])
9991 (define_insn ""
9992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9993 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9994 [(match_operand 2 "cc_reg_operand" "y,y")
9995 (const_int 0)])
9996 (const_int 0)))
9997 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9998 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
9999 "! TARGET_POWERPC64"
10000 "@
10001 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
10002 #"
10003 [(set_attr "type" "delayed_compare")
10004 (set_attr "length" "12,16")])
10006 (define_split
10007 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10008 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10009 [(match_operand 2 "cc_reg_operand" "")
10010 (const_int 0)])
10011 (const_int 0)))
10012 (set (match_operand:SI 3 "gpc_reg_operand" "")
10013 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10014 "! TARGET_POWERPC64 && reload_completed"
10015 [(set (match_dup 3)
10016 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
10017 (set (match_dup 0)
10018 (compare:CC (match_dup 3)
10019 (const_int 0)))]
10020 "")
10022 (define_insn ""
10023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10024 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10025 [(match_operand 2 "cc_reg_operand" "y")
10026 (const_int 0)])
10027 (match_operand:SI 3 "const_int_operand" "n")))]
10028 ""
10029 "*
10030 {
10031 int is_bit = ccr_bit (operands[1], 1);
10032 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10033 int count;
10035 if (is_bit >= put_bit)
10036 count = is_bit - put_bit;
10037 else
10038 count = 32 - (put_bit - is_bit);
10040 operands[4] = GEN_INT (count);
10041 operands[5] = GEN_INT (put_bit);
10043 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
10044 }"
10045 [(set_attr "length" "12")])
10047 (define_insn ""
10048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10049 (compare:CC
10050 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10051 [(match_operand 2 "cc_reg_operand" "y,y")
10052 (const_int 0)])
10053 (match_operand:SI 3 "const_int_operand" "n,n"))
10054 (const_int 0)))
10055 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
10056 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10057 (match_dup 3)))]
10058 "! TARGET_POWERPC64"
10059 "*
10060 {
10061 int is_bit = ccr_bit (operands[1], 1);
10062 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10063 int count;
10065 /* Force split for non-cc0 compare. */
10066 if (which_alternative == 1)
10067 return \"#\";
10069 if (is_bit >= put_bit)
10070 count = is_bit - put_bit;
10071 else
10072 count = 32 - (put_bit - is_bit);
10074 operands[5] = GEN_INT (count);
10075 operands[6] = GEN_INT (put_bit);
10077 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
10078 }"
10079 [(set_attr "type" "delayed_compare")
10080 (set_attr "length" "12,16")])
10082 (define_split
10083 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10084 (compare:CC
10085 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10086 [(match_operand 2 "cc_reg_operand" "")
10087 (const_int 0)])
10088 (match_operand:SI 3 "const_int_operand" ""))
10089 (const_int 0)))
10090 (set (match_operand:SI 4 "gpc_reg_operand" "")
10091 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10092 (match_dup 3)))]
10093 "! TARGET_POWERPC64 && reload_completed"
10094 [(set (match_dup 4)
10095 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10096 (match_dup 3)))
10097 (set (match_dup 0)
10098 (compare:CC (match_dup 4)
10099 (const_int 0)))]
10100 "")
10102 ;; There is a 3 cycle delay between consecutive mfcr instructions
10103 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
10105 (define_peephole
10106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10107 (match_operator:SI 1 "scc_comparison_operator"
10108 [(match_operand 2 "cc_reg_operand" "y")
10109 (const_int 0)]))
10110 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
10111 (match_operator:SI 4 "scc_comparison_operator"
10112 [(match_operand 5 "cc_reg_operand" "y")
10113 (const_int 0)]))]
10114 "REGNO (operands[2]) != REGNO (operands[5])"
10115 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10116 [(set_attr "length" "20")])
10118 (define_peephole
10119 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10120 (match_operator:DI 1 "scc_comparison_operator"
10121 [(match_operand 2 "cc_reg_operand" "y")
10122 (const_int 0)]))
10123 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
10124 (match_operator:DI 4 "scc_comparison_operator"
10125 [(match_operand 5 "cc_reg_operand" "y")
10126 (const_int 0)]))]
10127 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
10128 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10129 [(set_attr "length" "20")])
10131 ;; There are some scc insns that can be done directly, without a compare.
10132 ;; These are faster because they don't involve the communications between
10133 ;; the FXU and branch units. In fact, we will be replacing all of the
10134 ;; integer scc insns here or in the portable methods in emit_store_flag.
10135 ;;
10136 ;; Also support (neg (scc ..)) since that construct is used to replace
10137 ;; branches, (plus (scc ..) ..) since that construct is common and
10138 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
10139 ;; cases where it is no more expensive than (neg (scc ..)).
10141 ;; Have reload force a constant into a register for the simple insns that
10142 ;; otherwise won't accept constants. We do this because it is faster than
10143 ;; the cmp/mfcr sequence we would otherwise generate.
10145 (define_insn ""
10146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10147 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10148 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
10149 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
10150 "! TARGET_POWERPC64"
10151 "@
10152 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10153 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
10154 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10155 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10156 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
10157 [(set_attr "length" "12,8,12,12,12")])
10159 (define_insn ""
10160 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
10161 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
10162 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
10163 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
10164 "TARGET_POWERPC64"
10165 "@
10166 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
10167 subfic %3,%1,0\;adde %0,%3,%1
10168 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
10169 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
10170 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
10171 [(set_attr "length" "12,8,12,12,12")])
10173 (define_insn ""
10174 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10175 (compare:CC
10176 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10177 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10178 (const_int 0)))
10179 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10180 (eq:SI (match_dup 1) (match_dup 2)))
10181 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10182 "! TARGET_POWERPC64"
10183 "@
10184 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10185 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
10186 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10187 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10188 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10189 #
10190 #
10191 #
10192 #
10193 #"
10194 [(set_attr "type" "compare")
10195 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10197 (define_split
10198 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10199 (compare:CC
10200 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10201 (match_operand:SI 2 "reg_or_cint_operand" ""))
10202 (const_int 0)))
10203 (set (match_operand:SI 0 "gpc_reg_operand" "")
10204 (eq:SI (match_dup 1) (match_dup 2)))
10205 (clobber (match_scratch:SI 3 ""))]
10206 "! TARGET_POWERPC64 && reload_completed"
10207 [(parallel [(set (match_dup 0)
10208 (eq:SI (match_dup 1) (match_dup 2)))
10209 (clobber (match_dup 3))])
10210 (set (match_dup 4)
10211 (compare:CC (match_dup 0)
10212 (const_int 0)))]
10213 "")
10215 (define_insn ""
10216 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10217 (compare:CC
10218 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10219 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
10220 (const_int 0)))
10221 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10222 (eq:DI (match_dup 1) (match_dup 2)))
10223 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10224 "TARGET_POWERPC64"
10225 "@
10226 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10227 subfic %3,%1,0\;adde. %0,%3,%1
10228 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
10229 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
10230 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10231 #
10232 #
10233 #
10234 #
10235 #"
10236 [(set_attr "type" "compare")
10237 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10239 (define_split
10240 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10241 (compare:CC
10242 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
10243 (match_operand:DI 2 "reg_or_cint_operand" ""))
10244 (const_int 0)))
10245 (set (match_operand:DI 0 "gpc_reg_operand" "")
10246 (eq:DI (match_dup 1) (match_dup 2)))
10247 (clobber (match_scratch:DI 3 ""))]
10248 "TARGET_POWERPC64 && reload_completed"
10249 [(parallel [(set (match_dup 0)
10250 (eq:DI (match_dup 1) (match_dup 2)))
10251 (clobber (match_dup 3))])
10252 (set (match_dup 4)
10253 (compare:CC (match_dup 0)
10254 (const_int 0)))]
10255 "")
10257 ;; We have insns of the form shown by the first define_insn below. If
10258 ;; there is something inside the comparison operation, we must split it.
10259 (define_split
10260 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10261 (plus:SI (match_operator 1 "comparison_operator"
10262 [(match_operand:SI 2 "" "")
10263 (match_operand:SI 3
10264 "reg_or_cint_operand" "")])
10265 (match_operand:SI 4 "gpc_reg_operand" "")))
10266 (clobber (match_operand:SI 5 "register_operand" ""))]
10267 "! gpc_reg_operand (operands[2], SImode)"
10268 [(set (match_dup 5) (match_dup 2))
10269 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
10270 (match_dup 4)))])
10272 (define_insn ""
10273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10274 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10275 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
10276 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
10277 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
10278 "! TARGET_POWERPC64"
10279 "@
10280 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10281 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
10282 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10283 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10284 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
10285 [(set_attr "length" "12,8,12,12,12")])
10287 (define_insn ""
10288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10289 (compare:CC
10290 (plus:SI
10291 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10292 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10293 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10294 (const_int 0)))
10295 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10296 "! TARGET_POWERPC64"
10297 "@
10298 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10299 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
10300 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10301 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10302 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10303 #
10304 #
10305 #
10306 #
10307 #"
10308 [(set_attr "type" "compare")
10309 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10311 (define_split
10312 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10313 (compare:CC
10314 (plus:SI
10315 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10316 (match_operand:SI 2 "reg_or_cint_operand" ""))
10317 (match_operand:SI 3 "gpc_reg_operand" ""))
10318 (const_int 0)))
10319 (clobber (match_scratch:SI 4 ""))]
10320 "! TARGET_POWERPC64 && reload_completed"
10321 [(set (match_dup 4)
10322 (plus:SI (eq:SI (match_dup 1)
10323 (match_dup 2))
10324 (match_dup 3)))
10325 (set (match_dup 0)
10326 (compare:CC (match_dup 4)
10327 (const_int 0)))]
10328 "")
10330 (define_insn ""
10331 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10332 (compare:CC
10333 (plus:SI
10334 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10335 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10336 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10337 (const_int 0)))
10338 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10339 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10340 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10341 "! TARGET_POWERPC64"
10342 "@
10343 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10344 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
10345 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10346 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10347 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10348 #
10349 #
10350 #
10351 #
10352 #"
10353 [(set_attr "type" "compare")
10354 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10356 (define_split
10357 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10358 (compare:CC
10359 (plus:SI
10360 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10361 (match_operand:SI 2 "reg_or_cint_operand" ""))
10362 (match_operand:SI 3 "gpc_reg_operand" ""))
10363 (const_int 0)))
10364 (set (match_operand:SI 0 "gpc_reg_operand" "")
10365 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10366 (clobber (match_scratch:SI 4 ""))]
10367 "! TARGET_POWERPC64 && reload_completed"
10368 [(parallel [(set (match_dup 0)
10369 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10370 (clobber (match_dup 4))])
10371 (set (match_dup 5)
10372 (compare:CC (match_dup 0)
10373 (const_int 0)))]
10374 "")
10376 (define_insn ""
10377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10378 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10379 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
10380 "! TARGET_POWERPC64"
10381 "@
10382 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10383 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
10384 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10385 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10386 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
10387 [(set_attr "length" "12,8,12,12,12")])
10389 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
10390 ;; since it nabs/sr is just as fast.
10391 (define_insn "*ne0"
10392 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
10393 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10394 (const_int 31)))
10395 (clobber (match_scratch:SI 2 "=&r"))]
10396 "! TARGET_POWER && ! TARGET_POWERPC64"
10397 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
10398 [(set_attr "length" "8")])
10400 (define_insn ""
10401 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10402 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10403 (const_int 63)))
10404 (clobber (match_scratch:DI 2 "=&r"))]
10405 "TARGET_POWERPC64"
10406 "addic %2,%1,-1\;subfe %0,%2,%1"
10407 [(set_attr "length" "8")])
10409 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
10410 (define_insn ""
10411 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10412 (plus:SI (lshiftrt:SI
10413 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10414 (const_int 31))
10415 (match_operand:SI 2 "gpc_reg_operand" "r")))
10416 (clobber (match_scratch:SI 3 "=&r"))]
10417 "! TARGET_POWERPC64"
10418 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
10419 [(set_attr "length" "8")])
10421 (define_insn ""
10422 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10423 (plus:DI (lshiftrt:DI
10424 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10425 (const_int 63))
10426 (match_operand:DI 2 "gpc_reg_operand" "r")))
10427 (clobber (match_scratch:DI 3 "=&r"))]
10428 "TARGET_POWERPC64"
10429 "addic %3,%1,-1\;addze %0,%2"
10430 [(set_attr "length" "8")])
10432 (define_insn ""
10433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10434 (compare:CC
10435 (plus:SI (lshiftrt:SI
10436 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
10437 (const_int 31))
10438 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
10439 (const_int 0)))
10440 (clobber (match_scratch:SI 3 "=&r,&r"))]
10441 "! TARGET_POWERPC64"
10442 "@
10443 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
10444 #"
10445 [(set_attr "type" "compare")
10446 (set_attr "length" "8,12")])
10448 (define_split
10449 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10450 (compare:CC
10451 (plus:SI (lshiftrt:SI
10452 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10453 (const_int 31))
10454 (match_operand:SI 2 "gpc_reg_operand" ""))
10455 (const_int 0)))
10456 (clobber (match_scratch:SI 3 ""))]
10457 "! TARGET_POWERPC64 && reload_completed"
10458 [(set (match_dup 3)
10459 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
10460 (const_int 31))
10461 (match_dup 2)))
10462 (set (match_dup 0)
10463 (compare:CC (match_dup 3)
10464 (const_int 0)))]
10465 "")
10467 (define_insn ""
10468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10469 (compare:CC
10470 (plus:DI (lshiftrt:DI
10471 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
10472 (const_int 63))
10473 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
10474 (const_int 0)))
10475 (clobber (match_scratch:DI 3 "=&r,&r"))]
10476 "TARGET_POWERPC64"
10477 "@
10478 addic %3,%1,-1\;addze. %3,%2
10479 #"
10480 [(set_attr "type" "compare")
10481 (set_attr "length" "8,12")])
10483 (define_split
10484 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10485 (compare:CC
10486 (plus:DI (lshiftrt:DI
10487 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10488 (const_int 63))
10489 (match_operand:DI 2 "gpc_reg_operand" ""))
10490 (const_int 0)))
10491 (clobber (match_scratch:DI 3 ""))]
10492 "TARGET_POWERPC64 && reload_completed"
10493 [(set (match_dup 3)
10494 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
10495 (const_int 63))
10496 (match_dup 2)))
10497 (set (match_dup 0)
10498 (compare:CC (match_dup 3)
10499 (const_int 0)))]
10500 "")
10502 (define_insn ""
10503 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
10504 (compare:CC
10505 (plus:SI (lshiftrt:SI
10506 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
10507 (const_int 31))
10508 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
10509 (const_int 0)))
10510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10511 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10512 (match_dup 2)))
10513 (clobber (match_scratch:SI 3 "=&r,&r"))]
10514 "! TARGET_POWERPC64"
10515 "@
10516 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
10517 #"
10518 [(set_attr "type" "compare")
10519 (set_attr "length" "8,12")])
10521 (define_split
10522 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10523 (compare:CC
10524 (plus:SI (lshiftrt:SI
10525 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10526 (const_int 31))
10527 (match_operand:SI 2 "gpc_reg_operand" ""))
10528 (const_int 0)))
10529 (set (match_operand:SI 0 "gpc_reg_operand" "")
10530 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10531 (match_dup 2)))
10532 (clobber (match_scratch:SI 3 ""))]
10533 "! TARGET_POWERPC64 && reload_completed"
10534 [(parallel [(set (match_dup 0)
10535 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10536 (match_dup 2)))
10537 (clobber (match_dup 3))])
10538 (set (match_dup 4)
10539 (compare:CC (match_dup 0)
10540 (const_int 0)))]
10541 "")
10543 (define_insn ""
10544 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
10545 (compare:CC
10546 (plus:DI (lshiftrt:DI
10547 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
10548 (const_int 63))
10549 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
10550 (const_int 0)))
10551 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10552 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10553 (match_dup 2)))
10554 (clobber (match_scratch:DI 3 "=&r,&r"))]
10555 "TARGET_POWERPC64"
10556 "@
10557 addic %3,%1,-1\;addze. %0,%2
10558 #"
10559 [(set_attr "type" "compare")
10560 (set_attr "length" "8,12")])
10562 (define_split
10563 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10564 (compare:CC
10565 (plus:DI (lshiftrt:DI
10566 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10567 (const_int 63))
10568 (match_operand:DI 2 "gpc_reg_operand" ""))
10569 (const_int 0)))
10570 (set (match_operand:DI 0 "gpc_reg_operand" "")
10571 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10572 (match_dup 2)))
10573 (clobber (match_scratch:DI 3 ""))]
10574 "TARGET_POWERPC64 && reload_completed"
10575 [(parallel [(set (match_dup 0)
10576 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10577 (match_dup 2)))
10578 (clobber (match_dup 3))])
10579 (set (match_dup 4)
10580 (compare:CC (match_dup 0)
10581 (const_int 0)))]
10582 "")
10584 (define_insn ""
10585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10586 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10587 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
10588 (clobber (match_scratch:SI 3 "=r,X"))]
10589 "TARGET_POWER"
10590 "@
10591 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
10592 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
10593 [(set_attr "length" "12")])
10595 (define_insn ""
10596 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
10597 (compare:CC
10598 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10599 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10600 (const_int 0)))
10601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
10602 (le:SI (match_dup 1) (match_dup 2)))
10603 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
10604 "TARGET_POWER"
10605 "@
10606 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
10607 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
10608 #
10609 #"
10610 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
10611 (set_attr "length" "12,12,16,16")])
10613 (define_split
10614 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10615 (compare:CC
10616 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10617 (match_operand:SI 2 "reg_or_short_operand" ""))
10618 (const_int 0)))
10619 (set (match_operand:SI 0 "gpc_reg_operand" "")
10620 (le:SI (match_dup 1) (match_dup 2)))
10621 (clobber (match_scratch:SI 3 ""))]
10622 "TARGET_POWER && reload_completed"
10623 [(parallel [(set (match_dup 0)
10624 (le:SI (match_dup 1) (match_dup 2)))
10625 (clobber (match_dup 3))])
10626 (set (match_dup 4)
10627 (compare:CC (match_dup 0)
10628 (const_int 0)))]
10629 "")
10631 (define_insn ""
10632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10633 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10634 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
10635 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
10636 (clobber (match_scratch:SI 4 "=&r,&r"))]
10637 "TARGET_POWER"
10638 "@
10639 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10640 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
10641 [(set_attr "length" "12")])
10643 (define_insn ""
10644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
10645 (compare:CC
10646 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10647 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10648 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
10649 (const_int 0)))
10650 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
10651 "TARGET_POWER"
10652 "@
10653 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10654 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
10655 #
10656 #"
10657 [(set_attr "type" "compare")
10658 (set_attr "length" "12,12,16,16")])
10660 (define_split
10661 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10662 (compare:CC
10663 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10664 (match_operand:SI 2 "reg_or_short_operand" ""))
10665 (match_operand:SI 3 "gpc_reg_operand" ""))
10666 (const_int 0)))
10667 (clobber (match_scratch:SI 4 ""))]
10668 "TARGET_POWER && reload_completed"
10669 [(set (match_dup 4)
10670 (plus:SI (le:SI (match_dup 1) (match_dup 2))
10671 (match_dup 3)))
10672 (set (match_dup 0)
10673 (compare:CC (match_dup 4)
10674 (const_int 0)))]
10675 "")
10677 (define_insn ""
10678 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
10679 (compare:CC
10680 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10681 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10682 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
10683 (const_int 0)))
10684 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
10685 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10686 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
10687 "TARGET_POWER"
10688 "@
10689 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10690 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
10691 #
10692 #"
10693 [(set_attr "type" "compare")
10694 (set_attr "length" "12,12,16,16")])
10696 (define_split
10697 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10698 (compare:CC
10699 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10700 (match_operand:SI 2 "reg_or_short_operand" ""))
10701 (match_operand:SI 3 "gpc_reg_operand" ""))
10702 (const_int 0)))
10703 (set (match_operand:SI 0 "gpc_reg_operand" "")
10704 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10705 (clobber (match_scratch:SI 4 ""))]
10706 "TARGET_POWER && reload_completed"
10707 [(parallel [(set (match_dup 0)
10708 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10709 (clobber (match_dup 4))])
10710 (set (match_dup 5)
10711 (compare:CC (match_dup 0)
10712 (const_int 0)))]
10713 "")
10715 (define_insn ""
10716 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10717 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10718 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
10719 "TARGET_POWER"
10720 "@
10721 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10722 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
10723 [(set_attr "length" "12")])
10725 (define_insn ""
10726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10727 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10728 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10729 "! TARGET_POWERPC64"
10730 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
10731 [(set_attr "length" "12")])
10733 (define_insn ""
10734 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10735 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10736 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10737 "TARGET_POWERPC64"
10738 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
10739 [(set_attr "length" "12")])
10741 (define_insn ""
10742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10743 (compare:CC
10744 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10745 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
10746 (const_int 0)))
10747 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10748 (leu:DI (match_dup 1) (match_dup 2)))]
10749 "TARGET_POWERPC64"
10750 "@
10751 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
10752 #"
10753 [(set_attr "type" "compare")
10754 (set_attr "length" "12,16")])
10756 (define_split
10757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
10758 (compare:CC
10759 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
10760 (match_operand:DI 2 "reg_or_short_operand" ""))
10761 (const_int 0)))
10762 (set (match_operand:DI 0 "gpc_reg_operand" "")
10763 (leu:DI (match_dup 1) (match_dup 2)))]
10764 "TARGET_POWERPC64 && reload_completed"
10765 [(set (match_dup 0)
10766 (leu:DI (match_dup 1) (match_dup 2)))
10767 (set (match_dup 3)
10768 (compare:CC (match_dup 0)
10769 (const_int 0)))]
10770 "")
10772 (define_insn ""
10773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10774 (compare:CC
10775 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10776 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10777 (const_int 0)))
10778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10779 (leu:SI (match_dup 1) (match_dup 2)))]
10780 "! TARGET_POWERPC64"
10781 "@
10782 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
10783 #"
10784 [(set_attr "type" "compare")
10785 (set_attr "length" "12,16")])
10787 (define_split
10788 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
10789 (compare:CC
10790 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10791 (match_operand:SI 2 "reg_or_short_operand" ""))
10792 (const_int 0)))
10793 (set (match_operand:SI 0 "gpc_reg_operand" "")
10794 (leu:SI (match_dup 1) (match_dup 2)))]
10795 "! TARGET_POWERPC64 && reload_completed"
10796 [(set (match_dup 0)
10797 (leu:SI (match_dup 1) (match_dup 2)))
10798 (set (match_dup 3)
10799 (compare:CC (match_dup 0)
10800 (const_int 0)))]
10801 "")
10803 (define_insn ""
10804 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10805 (compare:CC
10806 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10807 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
10808 (const_int 0)))
10809 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10810 (leu:DI (match_dup 1) (match_dup 2)))]
10811 "TARGET_POWERPC64"
10812 "@
10813 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
10814 #"
10815 [(set_attr "type" "compare")
10816 (set_attr "length" "12,16")])
10818 (define_insn ""
10819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10820 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10821 (match_operand:SI 2 "reg_or_short_operand" "rI"))
10822 (match_operand:SI 3 "gpc_reg_operand" "r")))
10823 (clobber (match_scratch:SI 4 "=&r"))]
10824 "! TARGET_POWERPC64"
10825 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
10826 [(set_attr "length" "8")])
10828 (define_insn ""
10829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10830 (compare:CC
10831 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10832 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10833 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10834 (const_int 0)))
10835 (clobber (match_scratch:SI 4 "=&r,&r"))]
10836 "! TARGET_POWERPC64"
10837 "@
10838 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
10839 #"
10840 [(set_attr "type" "compare")
10841 (set_attr "length" "8,12")])
10843 (define_split
10844 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10845 (compare:CC
10846 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10847 (match_operand:SI 2 "reg_or_short_operand" ""))
10848 (match_operand:SI 3 "gpc_reg_operand" ""))
10849 (const_int 0)))
10850 (clobber (match_scratch:SI 4 ""))]
10851 "! TARGET_POWERPC64 && reload_completed"
10852 [(set (match_dup 4)
10853 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
10854 (match_dup 3)))
10855 (set (match_dup 0)
10856 (compare:CC (match_dup 4)
10857 (const_int 0)))]
10858 "")
10860 (define_insn ""
10861 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
10862 (compare:CC
10863 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10864 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10865 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10866 (const_int 0)))
10867 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10868 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10869 (clobber (match_scratch:SI 4 "=&r,&r"))]
10870 "! TARGET_POWERPC64"
10871 "@
10872 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
10873 #"
10874 [(set_attr "type" "compare")
10875 (set_attr "length" "8,12")])
10877 (define_split
10878 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10879 (compare:CC
10880 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10881 (match_operand:SI 2 "reg_or_short_operand" ""))
10882 (match_operand:SI 3 "gpc_reg_operand" ""))
10883 (const_int 0)))
10884 (set (match_operand:SI 0 "gpc_reg_operand" "")
10885 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10886 (clobber (match_scratch:SI 4 ""))]
10887 "! TARGET_POWERPC64 && reload_completed"
10888 [(parallel [(set (match_dup 0)
10889 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10890 (clobber (match_dup 4))])
10891 (set (match_dup 5)
10892 (compare:CC (match_dup 0)
10893 (const_int 0)))]
10894 "")
10896 (define_insn ""
10897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10898 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10899 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
10900 "! TARGET_POWERPC64"
10901 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
10902 [(set_attr "length" "12")])
10904 (define_insn ""
10905 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10906 (and:SI (neg:SI
10907 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10908 (match_operand:SI 2 "reg_or_short_operand" "rI")))
10909 (match_operand:SI 3 "gpc_reg_operand" "r")))
10910 (clobber (match_scratch:SI 4 "=&r"))]
10911 "! TARGET_POWERPC64"
10912 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
10913 [(set_attr "length" "12")])
10915 (define_insn ""
10916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10917 (compare:CC
10918 (and:SI (neg:SI
10919 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10920 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
10921 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10922 (const_int 0)))
10923 (clobber (match_scratch:SI 4 "=&r,&r"))]
10924 "! TARGET_POWERPC64"
10925 "@
10926 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
10927 #"
10928 [(set_attr "type" "compare")
10929 (set_attr "length" "12,16")])
10931 (define_split
10932 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10933 (compare:CC
10934 (and:SI (neg:SI
10935 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10936 (match_operand:SI 2 "reg_or_short_operand" "")))
10937 (match_operand:SI 3 "gpc_reg_operand" ""))
10938 (const_int 0)))
10939 (clobber (match_scratch:SI 4 ""))]
10940 "! TARGET_POWERPC64 && reload_completed"
10941 [(set (match_dup 4)
10942 (and:SI (neg:SI (leu:SI (match_dup 1)
10943 (match_dup 2)))
10944 (match_dup 3)))
10945 (set (match_dup 0)
10946 (compare:CC (match_dup 4)
10947 (const_int 0)))]
10948 "")
10950 (define_insn ""
10951 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
10952 (compare:CC
10953 (and:SI (neg:SI
10954 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10955 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
10956 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10957 (const_int 0)))
10958 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10959 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
10960 (clobber (match_scratch:SI 4 "=&r,&r"))]
10961 "! TARGET_POWERPC64"
10962 "@
10963 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
10964 #"
10965 [(set_attr "type" "compare")
10966 (set_attr "length" "12,16")])
10968 (define_split
10969 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10970 (compare:CC
10971 (and:SI (neg:SI
10972 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10973 (match_operand:SI 2 "reg_or_short_operand" "")))
10974 (match_operand:SI 3 "gpc_reg_operand" ""))
10975 (const_int 0)))
10976 (set (match_operand:SI 0 "gpc_reg_operand" "")
10977 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
10978 (clobber (match_scratch:SI 4 ""))]
10979 "! TARGET_POWERPC64 && reload_completed"
10980 [(parallel [(set (match_dup 0)
10981 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
10982 (clobber (match_dup 4))])
10983 (set (match_dup 5)
10984 (compare:CC (match_dup 0)
10985 (const_int 0)))]
10986 "")
10988 (define_insn ""
10989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10990 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10991 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10992 "TARGET_POWER"
10993 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
10994 [(set_attr "length" "12")])
10996 (define_insn ""
10997 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10998 (compare:CC
10999 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11000 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11001 (const_int 0)))
11002 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11003 (lt:SI (match_dup 1) (match_dup 2)))]
11004 "TARGET_POWER"
11005 "@
11006 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11007 #"
11008 [(set_attr "type" "delayed_compare")
11009 (set_attr "length" "12,16")])
11011 (define_split
11012 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11013 (compare:CC
11014 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11015 (match_operand:SI 2 "reg_or_short_operand" ""))
11016 (const_int 0)))
11017 (set (match_operand:SI 0 "gpc_reg_operand" "")
11018 (lt:SI (match_dup 1) (match_dup 2)))]
11019 "TARGET_POWER && reload_completed"
11020 [(set (match_dup 0)
11021 (lt:SI (match_dup 1) (match_dup 2)))
11022 (set (match_dup 3)
11023 (compare:CC (match_dup 0)
11024 (const_int 0)))]
11025 "")
11027 (define_insn ""
11028 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11029 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11030 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11031 (match_operand:SI 3 "gpc_reg_operand" "r")))
11032 (clobber (match_scratch:SI 4 "=&r"))]
11033 "TARGET_POWER"
11034 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
11035 [(set_attr "length" "12")])
11037 (define_insn ""
11038 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11039 (compare:CC
11040 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11041 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11042 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11043 (const_int 0)))
11044 (clobber (match_scratch:SI 4 "=&r,&r"))]
11045 "TARGET_POWER"
11046 "@
11047 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11048 #"
11049 [(set_attr "type" "compare")
11050 (set_attr "length" "12,16")])
11052 (define_split
11053 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11054 (compare:CC
11055 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11056 (match_operand:SI 2 "reg_or_short_operand" ""))
11057 (match_operand:SI 3 "gpc_reg_operand" ""))
11058 (const_int 0)))
11059 (clobber (match_scratch:SI 4 ""))]
11060 "TARGET_POWER && reload_completed"
11061 [(set (match_dup 4)
11062 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
11063 (match_dup 3)))
11064 (set (match_dup 0)
11065 (compare:CC (match_dup 4)
11066 (const_int 0)))]
11067 "")
11069 (define_insn ""
11070 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11071 (compare:CC
11072 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11073 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11074 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11075 (const_int 0)))
11076 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11077 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11078 (clobber (match_scratch:SI 4 "=&r,&r"))]
11079 "TARGET_POWER"
11080 "@
11081 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
11082 #"
11083 [(set_attr "type" "compare")
11084 (set_attr "length" "12,16")])
11086 (define_split
11087 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11088 (compare:CC
11089 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11090 (match_operand:SI 2 "reg_or_short_operand" ""))
11091 (match_operand:SI 3 "gpc_reg_operand" ""))
11092 (const_int 0)))
11093 (set (match_operand:SI 0 "gpc_reg_operand" "")
11094 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11095 (clobber (match_scratch:SI 4 ""))]
11096 "TARGET_POWER && reload_completed"
11097 [(parallel [(set (match_dup 0)
11098 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11099 (clobber (match_dup 4))])
11100 (set (match_dup 5)
11101 (compare:CC (match_dup 0)
11102 (const_int 0)))]
11103 "")
11105 (define_insn ""
11106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11107 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11108 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11109 "TARGET_POWER"
11110 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
11111 [(set_attr "length" "12")])
11113 (define_insn ""
11114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11115 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11116 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11117 "! TARGET_POWERPC64"
11118 "@
11119 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
11120 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
11121 [(set_attr "length" "12")])
11123 (define_insn ""
11124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11125 (compare:CC
11126 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11127 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11128 (const_int 0)))
11129 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11130 (ltu:SI (match_dup 1) (match_dup 2)))]
11131 "! TARGET_POWERPC64"
11132 "@
11133 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11134 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11135 #
11136 #"
11137 [(set_attr "type" "compare")
11138 (set_attr "length" "12,12,16,16")])
11140 (define_split
11141 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11142 (compare:CC
11143 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11144 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11145 (const_int 0)))
11146 (set (match_operand:SI 0 "gpc_reg_operand" "")
11147 (ltu:SI (match_dup 1) (match_dup 2)))]
11148 "! TARGET_POWERPC64 && reload_completed"
11149 [(set (match_dup 0)
11150 (ltu:SI (match_dup 1) (match_dup 2)))
11151 (set (match_dup 3)
11152 (compare:CC (match_dup 0)
11153 (const_int 0)))]
11154 "")
11156 (define_insn ""
11157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11158 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11159 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11160 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
11161 (clobber (match_scratch:SI 4 "=&r,&r"))]
11162 "! TARGET_POWERPC64"
11163 "@
11164 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
11165 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
11166 [(set_attr "length" "12")])
11168 (define_insn ""
11169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11170 (compare:CC
11171 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11172 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11173 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11174 (const_int 0)))
11175 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11176 "! TARGET_POWERPC64"
11177 "@
11178 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11179 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11180 #
11181 #"
11182 [(set_attr "type" "compare")
11183 (set_attr "length" "12,12,16,16")])
11185 (define_split
11186 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11187 (compare:CC
11188 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11189 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11190 (match_operand:SI 3 "gpc_reg_operand" ""))
11191 (const_int 0)))
11192 (clobber (match_scratch:SI 4 ""))]
11193 "! TARGET_POWERPC64 && reload_completed"
11194 [(set (match_dup 4)
11195 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
11196 (match_dup 3)))
11197 (set (match_dup 0)
11198 (compare:CC (match_dup 4)
11199 (const_int 0)))]
11200 "")
11202 (define_insn ""
11203 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11204 (compare:CC
11205 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11206 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11207 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11208 (const_int 0)))
11209 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11210 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11211 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11212 "! TARGET_POWERPC64"
11213 "@
11214 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11215 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11216 #
11217 #"
11218 [(set_attr "type" "compare")
11219 (set_attr "length" "12,12,16,16")])
11221 (define_split
11222 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11223 (compare:CC
11224 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11225 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11226 (match_operand:SI 3 "gpc_reg_operand" ""))
11227 (const_int 0)))
11228 (set (match_operand:SI 0 "gpc_reg_operand" "")
11229 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11230 (clobber (match_scratch:SI 4 ""))]
11231 "! TARGET_POWERPC64 && reload_completed"
11232 [(parallel [(set (match_dup 0)
11233 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11234 (clobber (match_dup 4))])
11235 (set (match_dup 5)
11236 (compare:CC (match_dup 0)
11237 (const_int 0)))]
11238 "")
11240 (define_insn ""
11241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11242 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11243 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
11244 "! TARGET_POWERPC64"
11245 "@
11246 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
11247 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
11248 [(set_attr "length" "8")])
11250 (define_insn ""
11251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11252 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11253 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11254 (clobber (match_scratch:SI 3 "=r"))]
11255 "TARGET_POWER"
11256 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
11257 [(set_attr "length" "12")])
11259 (define_insn ""
11260 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11261 (compare:CC
11262 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11263 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11264 (const_int 0)))
11265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11266 (ge:SI (match_dup 1) (match_dup 2)))
11267 (clobber (match_scratch:SI 3 "=r,r"))]
11268 "TARGET_POWER"
11269 "@
11270 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11271 #"
11272 [(set_attr "type" "compare")
11273 (set_attr "length" "12,16")])
11275 (define_split
11276 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11277 (compare:CC
11278 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11279 (match_operand:SI 2 "reg_or_short_operand" ""))
11280 (const_int 0)))
11281 (set (match_operand:SI 0 "gpc_reg_operand" "")
11282 (ge:SI (match_dup 1) (match_dup 2)))
11283 (clobber (match_scratch:SI 3 ""))]
11284 "TARGET_POWER && reload_completed"
11285 [(parallel [(set (match_dup 0)
11286 (ge:SI (match_dup 1) (match_dup 2)))
11287 (clobber (match_dup 3))])
11288 (set (match_dup 4)
11289 (compare:CC (match_dup 0)
11290 (const_int 0)))]
11291 "")
11293 (define_insn ""
11294 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11295 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11296 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11297 (match_operand:SI 3 "gpc_reg_operand" "r")))
11298 (clobber (match_scratch:SI 4 "=&r"))]
11299 "TARGET_POWER"
11300 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
11301 [(set_attr "length" "12")])
11303 (define_insn ""
11304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11305 (compare:CC
11306 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11307 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11308 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11309 (const_int 0)))
11310 (clobber (match_scratch:SI 4 "=&r,&r"))]
11311 "TARGET_POWER"
11312 "@
11313 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11314 #"
11315 [(set_attr "type" "compare")
11316 (set_attr "length" "12,16")])
11318 (define_split
11319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11320 (compare:CC
11321 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11322 (match_operand:SI 2 "reg_or_short_operand" ""))
11323 (match_operand:SI 3 "gpc_reg_operand" ""))
11324 (const_int 0)))
11325 (clobber (match_scratch:SI 4 ""))]
11326 "TARGET_POWER && reload_completed"
11327 [(set (match_dup 4)
11328 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
11329 (match_dup 3)))
11330 (set (match_dup 0)
11331 (compare:CC (match_dup 4)
11332 (const_int 0)))]
11333 "")
11335 (define_insn ""
11336 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11337 (compare:CC
11338 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11339 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11340 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11341 (const_int 0)))
11342 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11343 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11344 (clobber (match_scratch:SI 4 "=&r,&r"))]
11345 "TARGET_POWER"
11346 "@
11347 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11348 #"
11349 [(set_attr "type" "compare")
11350 (set_attr "length" "12,16")])
11352 (define_split
11353 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11354 (compare:CC
11355 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11356 (match_operand:SI 2 "reg_or_short_operand" ""))
11357 (match_operand:SI 3 "gpc_reg_operand" ""))
11358 (const_int 0)))
11359 (set (match_operand:SI 0 "gpc_reg_operand" "")
11360 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11361 (clobber (match_scratch:SI 4 ""))]
11362 "TARGET_POWER && reload_completed"
11363 [(parallel [(set (match_dup 0)
11364 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11365 (clobber (match_dup 4))])
11366 (set (match_dup 5)
11367 (compare:CC (match_dup 0)
11368 (const_int 0)))]
11369 "")
11371 (define_insn ""
11372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11373 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11374 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11375 "TARGET_POWER"
11376 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11377 [(set_attr "length" "12")])
11379 (define_insn ""
11380 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11381 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11382 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11383 "! TARGET_POWERPC64"
11384 "@
11385 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
11386 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11387 [(set_attr "length" "12")])
11389 (define_insn ""
11390 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11391 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11392 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
11393 "TARGET_POWERPC64"
11394 "@
11395 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
11396 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
11397 [(set_attr "length" "12")])
11399 (define_insn ""
11400 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11401 (compare:CC
11402 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11403 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11404 (const_int 0)))
11405 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11406 (geu:SI (match_dup 1) (match_dup 2)))]
11407 "! TARGET_POWERPC64"
11408 "@
11409 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11410 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11411 #
11412 #"
11413 [(set_attr "type" "compare")
11414 (set_attr "length" "12,12,16,16")])
11416 (define_split
11417 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11418 (compare:CC
11419 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11420 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11421 (const_int 0)))
11422 (set (match_operand:SI 0 "gpc_reg_operand" "")
11423 (geu:SI (match_dup 1) (match_dup 2)))]
11424 "! TARGET_POWERPC64 && reload_completed"
11425 [(set (match_dup 0)
11426 (geu:SI (match_dup 1) (match_dup 2)))
11427 (set (match_dup 3)
11428 (compare:CC (match_dup 0)
11429 (const_int 0)))]
11430 "")
11432 (define_insn ""
11433 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11434 (compare:CC
11435 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
11436 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11437 (const_int 0)))
11438 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
11439 (geu:DI (match_dup 1) (match_dup 2)))]
11440 "TARGET_POWERPC64"
11441 "@
11442 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
11443 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
11444 #
11445 #"
11446 [(set_attr "type" "compare")
11447 (set_attr "length" "12,12,16,16")])
11449 (define_split
11450 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11451 (compare:CC
11452 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11453 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
11454 (const_int 0)))
11455 (set (match_operand:DI 0 "gpc_reg_operand" "")
11456 (geu:DI (match_dup 1) (match_dup 2)))]
11457 "TARGET_POWERPC64 && reload_completed"
11458 [(set (match_dup 0)
11459 (geu:DI (match_dup 1) (match_dup 2)))
11460 (set (match_dup 3)
11461 (compare:CC (match_dup 0)
11462 (const_int 0)))]
11463 "")
11465 (define_insn ""
11466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11467 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11468 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11469 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11470 (clobber (match_scratch:SI 4 "=&r,&r"))]
11471 "! TARGET_POWERPC64"
11472 "@
11473 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
11474 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
11475 [(set_attr "length" "8")])
11477 (define_insn ""
11478 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11479 (compare:CC
11480 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11481 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11482 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11483 (const_int 0)))
11484 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11485 "! TARGET_POWERPC64"
11486 "@
11487 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
11488 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
11489 #
11490 #"
11491 [(set_attr "type" "compare")
11492 (set_attr "length" "8,8,12,12")])
11494 (define_split
11495 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11496 (compare:CC
11497 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11498 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11499 (match_operand:SI 3 "gpc_reg_operand" ""))
11500 (const_int 0)))
11501 (clobber (match_scratch:SI 4 ""))]
11502 "! TARGET_POWERPC64 && reload_completed"
11503 [(set (match_dup 4)
11504 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
11505 (match_dup 3)))
11506 (set (match_dup 0)
11507 (compare:CC (match_dup 4)
11508 (const_int 0)))]
11509 "")
11511 (define_insn ""
11512 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11513 (compare:CC
11514 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11515 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11516 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11517 (const_int 0)))
11518 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11519 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11520 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11521 "! TARGET_POWERPC64"
11522 "@
11523 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
11524 {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3
11525 #
11526 #"
11527 [(set_attr "type" "compare")
11528 (set_attr "length" "8,8,12,12")])
11530 (define_split
11531 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11532 (compare:CC
11533 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11534 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11535 (match_operand:SI 3 "gpc_reg_operand" ""))
11536 (const_int 0)))
11537 (set (match_operand:SI 0 "gpc_reg_operand" "")
11538 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11539 (clobber (match_scratch:SI 4 ""))]
11540 "! TARGET_POWERPC64 && reload_completed"
11541 [(parallel [(set (match_dup 0)
11542 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11543 (clobber (match_dup 4))])
11544 (set (match_dup 5)
11545 (compare:CC (match_dup 0)
11546 (const_int 0)))]
11547 "")
11549 (define_insn ""
11550 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11551 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11552 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
11553 "! TARGET_POWERPC64"
11554 "@
11555 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
11556 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
11557 [(set_attr "length" "12")])
11559 (define_insn ""
11560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11561 (and:SI (neg:SI
11562 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11563 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
11564 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11565 (clobber (match_scratch:SI 4 "=&r,&r"))]
11566 "! TARGET_POWERPC64"
11567 "@
11568 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
11569 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11570 [(set_attr "length" "12")])
11572 (define_insn ""
11573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11574 (compare:CC
11575 (and:SI (neg:SI
11576 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11577 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
11578 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11579 (const_int 0)))
11580 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11581 "! TARGET_POWERPC64"
11582 "@
11583 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11584 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11585 #
11586 #"
11587 [(set_attr "type" "compare")
11588 (set_attr "length" "12,12,16,16")])
11590 (define_split
11591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11592 (compare:CC
11593 (and:SI (neg:SI
11594 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11595 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
11596 (match_operand:SI 3 "gpc_reg_operand" ""))
11597 (const_int 0)))
11598 (clobber (match_scratch:SI 4 ""))]
11599 "! TARGET_POWERPC64 && reload_completed"
11600 [(set (match_dup 4)
11601 (and:SI (neg:SI (geu:SI (match_dup 1)
11602 (match_dup 2)))
11603 (match_dup 3)))
11604 (set (match_dup 0)
11605 (compare:CC (match_dup 4)
11606 (const_int 0)))]
11607 "")
11609 (define_insn ""
11610 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11611 (compare:CC
11612 (and:SI (neg:SI
11613 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11614 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
11615 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11616 (const_int 0)))
11617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11618 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11619 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11620 "! TARGET_POWERPC64"
11621 "@
11622 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11623 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11624 #
11625 #"
11626 [(set_attr "type" "compare")
11627 (set_attr "length" "12,12,16,16")])
11629 (define_split
11630 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11631 (compare:CC
11632 (and:SI (neg:SI
11633 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11634 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
11635 (match_operand:SI 3 "gpc_reg_operand" ""))
11636 (const_int 0)))
11637 (set (match_operand:SI 0 "gpc_reg_operand" "")
11638 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11639 (clobber (match_scratch:SI 4 ""))]
11640 "! TARGET_POWERPC64 && reload_completed"
11641 [(parallel [(set (match_dup 0)
11642 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11643 (clobber (match_dup 4))])
11644 (set (match_dup 5)
11645 (compare:CC (match_dup 0)
11646 (const_int 0)))]
11647 "")
11649 (define_insn ""
11650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11651 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11652 (const_int 0)))]
11653 "! TARGET_POWERPC64"
11654 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
11655 [(set_attr "length" "12")])
11657 (define_insn ""
11658 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11659 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11660 (const_int 0)))]
11661 "TARGET_POWERPC64"
11662 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
11663 [(set_attr "length" "12")])
11665 (define_insn ""
11666 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
11667 (compare:CC
11668 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11669 (const_int 0))
11670 (const_int 0)))
11671 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11672 (gt:SI (match_dup 1) (const_int 0)))]
11673 "! TARGET_POWERPC64"
11674 "@
11675 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
11676 #"
11677 [(set_attr "type" "delayed_compare")
11678 (set_attr "length" "12,16")])
11680 (define_split
11681 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
11682 (compare:CC
11683 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11684 (const_int 0))
11685 (const_int 0)))
11686 (set (match_operand:SI 0 "gpc_reg_operand" "")
11687 (gt:SI (match_dup 1) (const_int 0)))]
11688 "! TARGET_POWERPC64 && reload_completed"
11689 [(set (match_dup 0)
11690 (gt:SI (match_dup 1) (const_int 0)))
11691 (set (match_dup 2)
11692 (compare:CC (match_dup 0)
11693 (const_int 0)))]
11694 "")
11696 (define_insn ""
11697 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
11698 (compare:CC
11699 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11700 (const_int 0))
11701 (const_int 0)))
11702 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11703 (gt:DI (match_dup 1) (const_int 0)))]
11704 "TARGET_POWERPC64"
11705 "@
11706 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
11707 #"
11708 [(set_attr "type" "delayed_compare")
11709 (set_attr "length" "12,16")])
11711 (define_split
11712 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
11713 (compare:CC
11714 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11715 (const_int 0))
11716 (const_int 0)))
11717 (set (match_operand:DI 0 "gpc_reg_operand" "")
11718 (gt:DI (match_dup 1) (const_int 0)))]
11719 "TARGET_POWERPC64 && reload_completed"
11720 [(set (match_dup 0)
11721 (gt:DI (match_dup 1) (const_int 0)))
11722 (set (match_dup 2)
11723 (compare:CC (match_dup 0)
11724 (const_int 0)))]
11725 "")
11727 (define_insn ""
11728 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11729 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11730 (match_operand:SI 2 "reg_or_short_operand" "r")))]
11731 "TARGET_POWER"
11732 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11733 [(set_attr "length" "12")])
11735 (define_insn ""
11736 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11737 (compare:CC
11738 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11739 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
11740 (const_int 0)))
11741 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11742 (gt:SI (match_dup 1) (match_dup 2)))]
11743 "TARGET_POWER"
11744 "@
11745 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11746 #"
11747 [(set_attr "type" "delayed_compare")
11748 (set_attr "length" "12,16")])
11750 (define_split
11751 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11752 (compare:CC
11753 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11754 (match_operand:SI 2 "reg_or_short_operand" ""))
11755 (const_int 0)))
11756 (set (match_operand:SI 0 "gpc_reg_operand" "")
11757 (gt:SI (match_dup 1) (match_dup 2)))]
11758 "TARGET_POWER && reload_completed"
11759 [(set (match_dup 0)
11760 (gt:SI (match_dup 1) (match_dup 2)))
11761 (set (match_dup 3)
11762 (compare:CC (match_dup 0)
11763 (const_int 0)))]
11764 "")
11766 (define_insn ""
11767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11768 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11769 (const_int 0))
11770 (match_operand:SI 2 "gpc_reg_operand" "r")))
11771 (clobber (match_scratch:SI 3 "=&r"))]
11772 "! TARGET_POWERPC64"
11773 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
11774 [(set_attr "length" "12")])
11776 (define_insn ""
11777 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11778 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11779 (const_int 0))
11780 (match_operand:DI 2 "gpc_reg_operand" "r")))
11781 (clobber (match_scratch:DI 3 "=&r"))]
11782 "TARGET_POWERPC64"
11783 "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
11784 [(set_attr "length" "12")])
11786 (define_insn ""
11787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11788 (compare:CC
11789 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11790 (const_int 0))
11791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11792 (const_int 0)))
11793 (clobber (match_scratch:SI 3 "=&r,&r"))]
11794 "! TARGET_POWERPC64"
11795 "@
11796 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
11797 #"
11798 [(set_attr "type" "compare")
11799 (set_attr "length" "12,16")])
11801 (define_split
11802 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11803 (compare:CC
11804 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11805 (const_int 0))
11806 (match_operand:SI 2 "gpc_reg_operand" ""))
11807 (const_int 0)))
11808 (clobber (match_scratch:SI 3 ""))]
11809 "! TARGET_POWERPC64 && reload_completed"
11810 [(set (match_dup 3)
11811 (plus:SI (gt:SI (match_dup 1) (const_int 0))
11812 (match_dup 2)))
11813 (set (match_dup 0)
11814 (compare:CC (match_dup 3)
11815 (const_int 0)))]
11816 "")
11818 (define_insn ""
11819 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11820 (compare:CC
11821 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11822 (const_int 0))
11823 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11824 (const_int 0)))
11825 (clobber (match_scratch:DI 3 "=&r,&r"))]
11826 "TARGET_POWERPC64"
11827 "@
11828 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
11829 #"
11830 [(set_attr "type" "compare")
11831 (set_attr "length" "12,16")])
11833 (define_split
11834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11835 (compare:CC
11836 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11837 (const_int 0))
11838 (match_operand:DI 2 "gpc_reg_operand" ""))
11839 (const_int 0)))
11840 (clobber (match_scratch:DI 3 ""))]
11841 "TARGET_POWERPC64 && reload_completed"
11842 [(set (match_dup 3)
11843 (plus:DI (gt:DI (match_dup 1) (const_int 0))
11844 (match_dup 2)))
11845 (set (match_dup 0)
11846 (compare:CC (match_dup 3)
11847 (const_int 0)))]
11848 "")
11850 (define_insn ""
11851 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11852 (compare:CC
11853 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11854 (const_int 0))
11855 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11856 (const_int 0)))
11857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11858 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
11859 (clobber (match_scratch:SI 3 "=&r,&r"))]
11860 "! TARGET_POWERPC64"
11861 "@
11862 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2
11863 #"
11864 [(set_attr "type" "compare")
11865 (set_attr "length" "12,16")])
11867 (define_split
11868 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11869 (compare:CC
11870 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11871 (const_int 0))
11872 (match_operand:SI 2 "gpc_reg_operand" ""))
11873 (const_int 0)))
11874 (set (match_operand:SI 0 "gpc_reg_operand" "")
11875 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
11876 (clobber (match_scratch:SI 3 ""))]
11877 "! TARGET_POWERPC64 && reload_completed"
11878 [(parallel [(set (match_dup 0)
11879 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
11880 (clobber (match_dup 3))])
11881 (set (match_dup 4)
11882 (compare:CC (match_dup 0)
11883 (const_int 0)))]
11884 "")
11886 (define_insn ""
11887 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11888 (compare:CC
11889 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11890 (const_int 0))
11891 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11892 (const_int 0)))
11893 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11894 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
11895 (clobber (match_scratch:DI 3 "=&r,&r"))]
11896 "TARGET_POWERPC64"
11897 "@
11898 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2
11899 #"
11900 [(set_attr "type" "compare")
11901 (set_attr "length" "12,16")])
11903 (define_split
11904 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11905 (compare:CC
11906 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11907 (const_int 0))
11908 (match_operand:DI 2 "gpc_reg_operand" ""))
11909 (const_int 0)))
11910 (set (match_operand:DI 0 "gpc_reg_operand" "")
11911 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
11912 (clobber (match_scratch:DI 3 ""))]
11913 "TARGET_POWERPC64 && reload_completed"
11914 [(parallel [(set (match_dup 0)
11915 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
11916 (clobber (match_dup 3))])
11917 (set (match_dup 4)
11918 (compare:CC (match_dup 0)
11919 (const_int 0)))]
11920 "")
11922 (define_insn ""
11923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11924 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11925 (match_operand:SI 2 "reg_or_short_operand" "r"))
11926 (match_operand:SI 3 "gpc_reg_operand" "r")))
11927 (clobber (match_scratch:SI 4 "=&r"))]
11928 "TARGET_POWER"
11929 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
11930 [(set_attr "length" "12")])
11932 (define_insn ""
11933 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11934 (compare:CC
11935 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11936 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
11937 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11938 (const_int 0)))
11939 (clobber (match_scratch:SI 4 "=&r,&r"))]
11940 "TARGET_POWER"
11941 "@
11942 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11943 #"
11944 [(set_attr "type" "compare")
11945 (set_attr "length" "12,16")])
11947 (define_split
11948 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11949 (compare:CC
11950 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11951 (match_operand:SI 2 "reg_or_short_operand" ""))
11952 (match_operand:SI 3 "gpc_reg_operand" ""))
11953 (const_int 0)))
11954 (clobber (match_scratch:SI 4 ""))]
11955 "TARGET_POWER && reload_completed"
11956 [(set (match_dup 4)
11957 (plus:SI (gt:SI (match_dup 1) (match_dup 2))
11958 (match_dup 3)))
11959 (set (match_dup 0)
11960 (compare:CC (match_dup 4)
11961 (const_int 0)))]
11962 "")
11964 (define_insn ""
11965 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11966 (compare:CC
11967 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11968 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
11969 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11970 (const_int 0)))
11971 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11972 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11973 (clobber (match_scratch:SI 4 "=&r,&r"))]
11974 "TARGET_POWER"
11975 "@
11976 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
11977 #"
11978 [(set_attr "type" "compare")
11979 (set_attr "length" "12,16")])
11981 (define_split
11982 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11983 (compare:CC
11984 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11985 (match_operand:SI 2 "reg_or_short_operand" ""))
11986 (match_operand:SI 3 "gpc_reg_operand" ""))
11987 (const_int 0)))
11988 (set (match_operand:SI 0 "gpc_reg_operand" "")
11989 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11990 (clobber (match_scratch:SI 4 ""))]
11991 "TARGET_POWER && reload_completed"
11992 [(parallel [(set (match_dup 0)
11993 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11994 (clobber (match_dup 4))])
11995 (set (match_dup 5)
11996 (compare:CC (match_dup 0)
11997 (const_int 0)))]
11998 "")
12000 (define_insn ""
12001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12002 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12003 (const_int 0))))]
12004 "! TARGET_POWERPC64"
12005 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
12006 [(set_attr "length" "12")])
12008 (define_insn ""
12009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12010 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12011 (const_int 0))))]
12012 "TARGET_POWERPC64"
12013 "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63"
12014 [(set_attr "length" "12")])
12016 (define_insn ""
12017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12018 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12019 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12020 "TARGET_POWER"
12021 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12022 [(set_attr "length" "12")])
12024 (define_insn ""
12025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12026 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12027 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12028 "! TARGET_POWERPC64"
12029 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12030 [(set_attr "length" "12")])
12032 (define_insn ""
12033 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12034 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12035 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12036 "TARGET_POWERPC64"
12037 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
12038 [(set_attr "length" "12")])
12040 (define_insn ""
12041 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12042 (compare:CC
12043 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12044 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12045 (const_int 0)))
12046 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12047 (gtu:SI (match_dup 1) (match_dup 2)))]
12048 "! TARGET_POWERPC64"
12049 "@
12050 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12051 #"
12052 [(set_attr "type" "compare")
12053 (set_attr "length" "12,16")])
12055 (define_split
12056 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12057 (compare:CC
12058 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12059 (match_operand:SI 2 "reg_or_short_operand" ""))
12060 (const_int 0)))
12061 (set (match_operand:SI 0 "gpc_reg_operand" "")
12062 (gtu:SI (match_dup 1) (match_dup 2)))]
12063 "! TARGET_POWERPC64 && reload_completed"
12064 [(set (match_dup 0)
12065 (gtu:SI (match_dup 1) (match_dup 2)))
12066 (set (match_dup 3)
12067 (compare:CC (match_dup 0)
12068 (const_int 0)))]
12069 "")
12071 (define_insn ""
12072 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12073 (compare:CC
12074 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12075 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12076 (const_int 0)))
12077 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12078 (gtu:DI (match_dup 1) (match_dup 2)))]
12079 "TARGET_POWERPC64"
12080 "@
12081 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
12082 #"
12083 [(set_attr "type" "compare")
12084 (set_attr "length" "12,16")])
12086 (define_split
12087 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12088 (compare:CC
12089 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12090 (match_operand:DI 2 "reg_or_short_operand" ""))
12091 (const_int 0)))
12092 (set (match_operand:DI 0 "gpc_reg_operand" "")
12093 (gtu:DI (match_dup 1) (match_dup 2)))]
12094 "TARGET_POWERPC64 && reload_completed"
12095 [(set (match_dup 0)
12096 (gtu:DI (match_dup 1) (match_dup 2)))
12097 (set (match_dup 3)
12098 (compare:CC (match_dup 0)
12099 (const_int 0)))]
12100 "")
12102 (define_insn ""
12103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12104 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12105 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
12106 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
12107 (clobber (match_scratch:SI 4 "=&r,&r"))]
12108 "! TARGET_POWERPC64"
12109 "@
12110 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
12111 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
12112 [(set_attr "length" "8,12")])
12114 (define_insn ""
12115 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12116 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12117 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
12118 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
12119 (clobber (match_scratch:DI 4 "=&r,&r"))]
12120 "TARGET_POWERPC64"
12121 "@
12122 addic %4,%1,%k2\;addze %0,%3
12123 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
12124 [(set_attr "length" "8,12")])
12126 (define_insn ""
12127 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12128 (compare:CC
12129 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12130 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12131 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12132 (const_int 0)))
12133 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12134 "! TARGET_POWERPC64"
12135 "@
12136 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
12137 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12138 #
12139 #"
12140 [(set_attr "type" "compare")
12141 (set_attr "length" "8,12,12,16")])
12143 (define_split
12144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12145 (compare:CC
12146 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12147 (match_operand:SI 2 "reg_or_short_operand" ""))
12148 (match_operand:SI 3 "gpc_reg_operand" ""))
12149 (const_int 0)))
12150 (clobber (match_scratch:SI 4 ""))]
12151 "! TARGET_POWERPC64 && reload_completed"
12152 [(set (match_dup 4)
12153 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
12154 (match_dup 3)))
12155 (set (match_dup 0)
12156 (compare:CC (match_dup 4)
12157 (const_int 0)))]
12158 "")
12160 (define_insn ""
12161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12162 (compare:CC
12163 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12164 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12165 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12166 (const_int 0)))
12167 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12168 "TARGET_POWERPC64"
12169 "@
12170 addic %4,%1,%k2\;addze. %4,%3
12171 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
12172 #
12173 #"
12174 [(set_attr "type" "compare")
12175 (set_attr "length" "8,12,12,16")])
12177 (define_split
12178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12179 (compare:CC
12180 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12181 (match_operand:DI 2 "reg_or_short_operand" ""))
12182 (match_operand:DI 3 "gpc_reg_operand" ""))
12183 (const_int 0)))
12184 (clobber (match_scratch:DI 4 ""))]
12185 "TARGET_POWERPC64 && reload_completed"
12186 [(set (match_dup 4)
12187 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
12188 (match_dup 3)))
12189 (set (match_dup 0)
12190 (compare:CC (match_dup 4)
12191 (const_int 0)))]
12192 "")
12194 (define_insn ""
12195 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12196 (compare:CC
12197 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12198 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12199 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12200 (const_int 0)))
12201 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12202 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12203 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12204 "! TARGET_POWERPC64"
12205 "@
12206 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
12207 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12208 #
12209 #"
12210 [(set_attr "type" "compare")
12211 (set_attr "length" "8,12,12,16")])
12213 (define_split
12214 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12215 (compare:CC
12216 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12217 (match_operand:SI 2 "reg_or_short_operand" ""))
12218 (match_operand:SI 3 "gpc_reg_operand" ""))
12219 (const_int 0)))
12220 (set (match_operand:SI 0 "gpc_reg_operand" "")
12221 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12222 (clobber (match_scratch:SI 4 ""))]
12223 "! TARGET_POWERPC64 && reload_completed"
12224 [(parallel [(set (match_dup 0)
12225 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12226 (clobber (match_dup 4))])
12227 (set (match_dup 5)
12228 (compare:CC (match_dup 0)
12229 (const_int 0)))]
12230 "")
12232 (define_insn ""
12233 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12234 (compare:CC
12235 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12236 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12237 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12238 (const_int 0)))
12239 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12240 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12241 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12242 "TARGET_POWERPC64"
12243 "@
12244 addic %4,%1,%k2\;addze. %0,%3
12245 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3
12246 #
12247 #"
12248 [(set_attr "type" "compare")
12249 (set_attr "length" "8,12,12,16")])
12251 (define_split
12252 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12253 (compare:CC
12254 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12255 (match_operand:DI 2 "reg_or_short_operand" ""))
12256 (match_operand:DI 3 "gpc_reg_operand" ""))
12257 (const_int 0)))
12258 (set (match_operand:DI 0 "gpc_reg_operand" "")
12259 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12260 (clobber (match_scratch:DI 4 ""))]
12261 "TARGET_POWERPC64 && reload_completed"
12262 [(parallel [(set (match_dup 0)
12263 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12264 (clobber (match_dup 4))])
12265 (set (match_dup 5)
12266 (compare:CC (match_dup 0)
12267 (const_int 0)))]
12268 "")
12270 (define_insn ""
12271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12272 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12273 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12274 "! TARGET_POWERPC64"
12275 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12276 [(set_attr "length" "8")])
12278 (define_insn ""
12279 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12280 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12281 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
12282 "TARGET_POWERPC64"
12283 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12284 [(set_attr "length" "8")])
12285 \f
12286 ;; Define both directions of branch and return. If we need a reload
12287 ;; register, we'd rather use CR0 since it is much easier to copy a
12288 ;; register CC value to there.
12290 (define_insn ""
12291 [(set (pc)
12292 (if_then_else (match_operator 1 "branch_comparison_operator"
12293 [(match_operand 2
12294 "cc_reg_operand" "x,?y")
12295 (const_int 0)])
12296 (label_ref (match_operand 0 "" ""))
12297 (pc)))]
12298 ""
12299 "*
12300 {
12301 return output_cbranch (operands[1], \"%l0\", 0, insn);
12302 }"
12303 [(set_attr "type" "branch")])
12305 (define_insn ""
12306 [(set (pc)
12307 (if_then_else (match_operator 0 "branch_comparison_operator"
12308 [(match_operand 1
12309 "cc_reg_operand" "x,?y")
12310 (const_int 0)])
12311 (return)
12312 (pc)))]
12313 "direct_return ()"
12314 "*
12315 {
12316 return output_cbranch (operands[0], NULL, 0, insn);
12317 }"
12318 [(set_attr "type" "branch")
12319 (set_attr "length" "4")])
12321 (define_insn ""
12322 [(set (pc)
12323 (if_then_else (match_operator 1 "branch_comparison_operator"
12324 [(match_operand 2
12325 "cc_reg_operand" "x,?y")
12326 (const_int 0)])
12327 (pc)
12328 (label_ref (match_operand 0 "" ""))))]
12329 ""
12330 "*
12331 {
12332 return output_cbranch (operands[1], \"%l0\", 1, insn);
12333 }"
12334 [(set_attr "type" "branch")])
12336 (define_insn ""
12337 [(set (pc)
12338 (if_then_else (match_operator 0 "branch_comparison_operator"
12339 [(match_operand 1
12340 "cc_reg_operand" "x,?y")
12341 (const_int 0)])
12342 (pc)
12343 (return)))]
12344 "direct_return ()"
12345 "*
12346 {
12347 return output_cbranch (operands[0], NULL, 1, insn);
12348 }"
12349 [(set_attr "type" "branch")
12350 (set_attr "length" "4")])
12352 ;; Logic on condition register values.
12354 ; This pattern matches things like
12355 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12356 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12357 ; (const_int 1)))
12358 ; which are generated by the branch logic.
12360 (define_insn ""
12361 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12362 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12363 [(match_operator:SI 2
12364 "branch_positive_comparison_operator"
12365 [(match_operand 3
12366 "cc_reg_operand" "y")
12367 (const_int 0)])
12368 (match_operator:SI 4
12369 "branch_positive_comparison_operator"
12370 [(match_operand 5
12371 "cc_reg_operand" "y")
12372 (const_int 0)])])
12373 (const_int 1)))]
12374 ""
12375 "cr%q1 %E0,%j2,%j4"
12376 [(set_attr "type" "cr_logical")])
12378 ; Why is the constant -1 here, but 1 in the previous pattern?
12379 ; Because ~1 has all but the low bit set.
12380 (define_insn ""
12381 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12382 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12383 [(not:SI (match_operator:SI 2
12384 "branch_positive_comparison_operator"
12385 [(match_operand 3
12386 "cc_reg_operand" "y")
12387 (const_int 0)]))
12388 (match_operator:SI 4
12389 "branch_positive_comparison_operator"
12390 [(match_operand 5
12391 "cc_reg_operand" "y")
12392 (const_int 0)])])
12393 (const_int -1)))]
12394 ""
12395 "cr%q1 %E0,%j2,%j4"
12396 [(set_attr "type" "cr_logical")])
12398 (define_insn ""
12399 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12400 (compare:CCEQ (match_operator:SI 1
12401 "branch_positive_comparison_operator"
12402 [(match_operand 2
12403 "cc_reg_operand" "y")
12404 (const_int 0)])
12405 (const_int 0)))]
12406 ""
12407 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12408 [(set_attr "type" "cr_logical")])
12410 ;; If we are comparing the result of two comparisons, this can be done
12411 ;; using creqv or crxor.
12413 (define_insn_and_split ""
12414 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12415 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12416 [(match_operand 2 "cc_reg_operand" "y")
12417 (const_int 0)])
12418 (match_operator 3 "branch_comparison_operator"
12419 [(match_operand 4 "cc_reg_operand" "y")
12420 (const_int 0)])))]
12421 ""
12422 "#"
12423 ""
12424 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12425 (match_dup 5)))]
12426 "
12427 {
12428 int positive_1, positive_2;
12430 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
12431 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
12433 if (! positive_1)
12434 operands[1] = gen_rtx (SImode,
12435 rs6000_reverse_condition (GET_MODE (operands[2]),
12436 GET_CODE (operands[1])),
12437 operands[2]);
12438 else if (GET_MODE (operands[1]) != SImode)
12439 operands[1] = gen_rtx (SImode,
12440 GET_CODE (operands[1]),
12441 operands[2]);
12443 if (! positive_2)
12444 operands[3] = gen_rtx (SImode,
12445 rs6000_reverse_condition (GET_MODE (operands[4]),
12446 GET_CODE (operands[3])),
12447 operands[4]);
12448 else if (GET_MODE (operands[3]) != SImode)
12449 operands[3] = gen_rtx (SImode,
12450 GET_CODE (operands[3]),
12451 operands[4]);
12453 if (positive_1 == positive_2)
12454 {
12455 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12456 operands[5] = constm1_rtx;
12457 }
12458 else
12459 {
12460 operands[5] = const1_rtx;
12461 }
12462 }")
12464 ;; Unconditional branch and return.
12466 (define_insn "jump"
12467 [(set (pc)
12468 (label_ref (match_operand 0 "" "")))]
12469 ""
12470 "b %l0"
12471 [(set_attr "type" "branch")])
12473 (define_insn "return"
12474 [(return)]
12475 "direct_return ()"
12476 "{br|blr}"
12477 [(set_attr "type" "jmpreg")])
12479 (define_expand "indirect_jump"
12480 [(set (pc) (match_operand 0 "register_operand" ""))]
12481 ""
12482 "
12483 {
12484 if (TARGET_32BIT)
12485 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
12486 else
12487 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
12488 DONE;
12489 }")
12491 (define_insn "indirect_jumpsi"
12492 [(set (pc) (match_operand:SI 0 "register_operand" "cl"))]
12493 "TARGET_32BIT"
12494 "b%T0"
12495 [(set_attr "type" "jmpreg")])
12497 (define_insn "indirect_jumpdi"
12498 [(set (pc) (match_operand:DI 0 "register_operand" "cl"))]
12499 "TARGET_64BIT"
12500 "b%T0"
12501 [(set_attr "type" "jmpreg")])
12503 ;; Table jump for switch statements:
12504 (define_expand "tablejump"
12505 [(use (match_operand 0 "" ""))
12506 (use (label_ref (match_operand 1 "" "")))]
12507 ""
12508 "
12509 {
12510 if (TARGET_32BIT)
12511 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12512 else
12513 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12514 DONE;
12515 }")
12517 (define_expand "tablejumpsi"
12518 [(set (match_dup 3)
12519 (plus:SI (match_operand:SI 0 "" "")
12520 (match_dup 2)))
12521 (parallel [(set (pc) (match_dup 3))
12522 (use (label_ref (match_operand 1 "" "")))])]
12523 "TARGET_32BIT"
12524 "
12525 { operands[0] = force_reg (SImode, operands[0]);
12526 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
12527 operands[3] = gen_reg_rtx (SImode);
12528 }")
12530 (define_expand "tablejumpdi"
12531 [(set (match_dup 4)
12532 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
12533 (set (match_dup 3)
12534 (plus:DI (match_dup 4)
12535 (match_dup 2)))
12536 (parallel [(set (pc) (match_dup 3))
12537 (use (label_ref (match_operand 1 "" "")))])]
12538 "TARGET_64BIT"
12539 "
12540 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
12541 operands[3] = gen_reg_rtx (DImode);
12542 operands[4] = gen_reg_rtx (DImode);
12543 }")
12545 (define_insn ""
12546 [(set (pc)
12547 (match_operand:SI 0 "register_operand" "cl"))
12548 (use (label_ref (match_operand 1 "" "")))]
12549 "TARGET_32BIT"
12550 "b%T0"
12551 [(set_attr "type" "jmpreg")])
12553 (define_insn ""
12554 [(set (pc)
12555 (match_operand:DI 0 "register_operand" "cl"))
12556 (use (label_ref (match_operand 1 "" "")))]
12557 "TARGET_64BIT"
12558 "b%T0"
12559 [(set_attr "type" "jmpreg")])
12561 (define_insn "nop"
12562 [(const_int 0)]
12563 ""
12564 "{cror 0,0,0|nop}")
12565 \f
12566 ;; Define the subtract-one-and-jump insns, starting with the template
12567 ;; so loop.c knows what to generate.
12569 (define_expand "doloop_end"
12570 [(use (match_operand 0 "" "")) ; loop pseudo
12571 (use (match_operand 1 "" "")) ; iterations; zero if unknown
12572 (use (match_operand 2 "" "")) ; max iterations
12573 (use (match_operand 3 "" "")) ; loop level
12574 (use (match_operand 4 "" ""))] ; label
12575 ""
12576 "
12577 {
12578 /* Only use this on innermost loops. */
12579 if (INTVAL (operands[3]) > 1)
12580 FAIL;
12581 if (TARGET_POWERPC64)
12582 {
12583 if (GET_MODE (operands[0]) != DImode)
12584 FAIL;
12585 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
12586 }
12587 else
12588 {
12589 if (GET_MODE (operands[0]) != SImode)
12590 FAIL;
12591 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
12592 }
12593 DONE;
12594 }")
12596 (define_expand "ctrsi"
12597 [(parallel [(set (pc)
12598 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
12599 (const_int 1))
12600 (label_ref (match_operand 1 "" ""))
12601 (pc)))
12602 (set (match_dup 0)
12603 (plus:SI (match_dup 0)
12604 (const_int -1)))
12605 (clobber (match_scratch:CC 2 ""))
12606 (clobber (match_scratch:SI 3 ""))])]
12607 "! TARGET_POWERPC64"
12608 "")
12610 (define_expand "ctrdi"
12611 [(parallel [(set (pc)
12612 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
12613 (const_int 1))
12614 (label_ref (match_operand 1 "" ""))
12615 (pc)))
12616 (set (match_dup 0)
12617 (plus:DI (match_dup 0)
12618 (const_int -1)))
12619 (clobber (match_scratch:CC 2 ""))
12620 (clobber (match_scratch:DI 3 ""))])]
12621 "TARGET_POWERPC64"
12622 "")
12624 ;; We need to be able to do this for any operand, including MEM, or we
12625 ;; will cause reload to blow up since we don't allow output reloads on
12626 ;; JUMP_INSNs.
12627 ;; For the length attribute to be calculated correctly, the
12628 ;; label MUST be operand 0.
12630 (define_insn "*ctrsi_internal1"
12631 [(set (pc)
12632 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12633 (const_int 1))
12634 (label_ref (match_operand 0 "" ""))
12635 (pc)))
12636 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12637 (plus:SI (match_dup 1)
12638 (const_int -1)))
12639 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12640 (clobber (match_scratch:SI 4 "=X,X,r"))]
12641 "! TARGET_POWERPC64"
12642 "*
12643 {
12644 if (which_alternative != 0)
12645 return \"#\";
12646 else if (get_attr_length (insn) == 4)
12647 return \"{bdn|bdnz} %l0\";
12648 else
12649 return \"bdz %$+8\;b %l0\";
12650 }"
12651 [(set_attr "type" "branch")
12652 (set_attr "length" "*,12,16")])
12654 (define_insn "*ctrsi_internal2"
12655 [(set (pc)
12656 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12657 (const_int 1))
12658 (pc)
12659 (label_ref (match_operand 0 "" ""))))
12660 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12661 (plus:SI (match_dup 1)
12662 (const_int -1)))
12663 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12664 (clobber (match_scratch:SI 4 "=X,X,r"))]
12665 "! TARGET_POWERPC64"
12666 "*
12667 {
12668 if (which_alternative != 0)
12669 return \"#\";
12670 else if (get_attr_length (insn) == 4)
12671 return \"bdz %l0\";
12672 else
12673 return \"{bdn|bdnz} %$+8\;b %l0\";
12674 }"
12675 [(set_attr "type" "branch")
12676 (set_attr "length" "*,12,16")])
12678 (define_insn "*ctrdi_internal1"
12679 [(set (pc)
12680 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
12681 (const_int 1))
12682 (label_ref (match_operand 0 "" ""))
12683 (pc)))
12684 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12685 (plus:DI (match_dup 1)
12686 (const_int -1)))
12687 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12688 (clobber (match_scratch:DI 4 "=X,X,r"))]
12689 "TARGET_POWERPC64"
12690 "*
12691 {
12692 if (which_alternative != 0)
12693 return \"#\";
12694 else if (get_attr_length (insn) == 4)
12695 return \"{bdn|bdnz} %l0\";
12696 else
12697 return \"bdz %$+8\;b %l0\";
12698 }"
12699 [(set_attr "type" "branch")
12700 (set_attr "length" "*,12,16")])
12702 (define_insn "*ctrdi_internal2"
12703 [(set (pc)
12704 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
12705 (const_int 1))
12706 (pc)
12707 (label_ref (match_operand 0 "" ""))))
12708 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12709 (plus:DI (match_dup 1)
12710 (const_int -1)))
12711 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12712 (clobber (match_scratch:DI 4 "=X,X,r"))]
12713 "TARGET_POWERPC64"
12714 "*
12715 {
12716 if (which_alternative != 0)
12717 return \"#\";
12718 else if (get_attr_length (insn) == 4)
12719 return \"bdz %l0\";
12720 else
12721 return \"{bdn|bdnz} %$+8\;b %l0\";
12722 }"
12723 [(set_attr "type" "branch")
12724 (set_attr "length" "*,12,16")])
12726 ;; Similar, but we can use GE since we have a REG_NONNEG.
12728 (define_insn "*ctrsi_internal3"
12729 [(set (pc)
12730 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12731 (const_int 0))
12732 (label_ref (match_operand 0 "" ""))
12733 (pc)))
12734 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12735 (plus:SI (match_dup 1)
12736 (const_int -1)))
12737 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12738 (clobber (match_scratch:SI 4 "=X,X,r"))]
12739 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12740 "*
12741 {
12742 if (which_alternative != 0)
12743 return \"#\";
12744 else if (get_attr_length (insn) == 4)
12745 return \"{bdn|bdnz} %l0\";
12746 else
12747 return \"bdz %$+8\;b %l0\";
12748 }"
12749 [(set_attr "type" "branch")
12750 (set_attr "length" "*,12,16")])
12752 (define_insn "*ctrsi_internal4"
12753 [(set (pc)
12754 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12755 (const_int 0))
12756 (pc)
12757 (label_ref (match_operand 0 "" ""))))
12758 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12759 (plus:SI (match_dup 1)
12760 (const_int -1)))
12761 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12762 (clobber (match_scratch:SI 4 "=X,X,r"))]
12763 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12764 "*
12765 {
12766 if (which_alternative != 0)
12767 return \"#\";
12768 else if (get_attr_length (insn) == 4)
12769 return \"bdz %l0\";
12770 else
12771 return \"{bdn|bdnz} %$+8\;b %l0\";
12772 }"
12773 [(set_attr "type" "branch")
12774 (set_attr "length" "*,12,16")])
12776 (define_insn "*ctrdi_internal3"
12777 [(set (pc)
12778 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
12779 (const_int 0))
12780 (label_ref (match_operand 0 "" ""))
12781 (pc)))
12782 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12783 (plus:DI (match_dup 1)
12784 (const_int -1)))
12785 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12786 (clobber (match_scratch:DI 4 "=X,X,r"))]
12787 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12788 "*
12789 {
12790 if (which_alternative != 0)
12791 return \"#\";
12792 else if (get_attr_length (insn) == 4)
12793 return \"{bdn|bdnz} %l0\";
12794 else
12795 return \"bdz %$+8\;b %l0\";
12796 }"
12797 [(set_attr "type" "branch")
12798 (set_attr "length" "*,12,16")])
12800 (define_insn "*ctrdi_internal4"
12801 [(set (pc)
12802 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
12803 (const_int 0))
12804 (pc)
12805 (label_ref (match_operand 0 "" ""))))
12806 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12807 (plus:DI (match_dup 1)
12808 (const_int -1)))
12809 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12810 (clobber (match_scratch:DI 4 "=X,X,r"))]
12811 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12812 "*
12813 {
12814 if (which_alternative != 0)
12815 return \"#\";
12816 else if (get_attr_length (insn) == 4)
12817 return \"bdz %l0\";
12818 else
12819 return \"{bdn|bdnz} %$+8\;b %l0\";
12820 }"
12821 [(set_attr "type" "branch")
12822 (set_attr "length" "*,12,16")])
12824 ;; Similar but use EQ
12826 (define_insn "*ctrsi_internal5"
12827 [(set (pc)
12828 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
12829 (const_int 1))
12830 (label_ref (match_operand 0 "" ""))
12831 (pc)))
12832 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12833 (plus:SI (match_dup 1)
12834 (const_int -1)))
12835 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12836 (clobber (match_scratch:SI 4 "=X,X,r"))]
12837 "! TARGET_POWERPC64"
12838 "*
12839 {
12840 if (which_alternative != 0)
12841 return \"#\";
12842 else if (get_attr_length (insn) == 4)
12843 return \"bdz %l0\";
12844 else
12845 return \"{bdn|bdnz} %$+8\;b %l0\";
12846 }"
12847 [(set_attr "type" "branch")
12848 (set_attr "length" "*,12,16")])
12850 (define_insn "*ctrsi_internal6"
12851 [(set (pc)
12852 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
12853 (const_int 1))
12854 (pc)
12855 (label_ref (match_operand 0 "" ""))))
12856 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12857 (plus:SI (match_dup 1)
12858 (const_int -1)))
12859 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12860 (clobber (match_scratch:SI 4 "=X,X,r"))]
12861 "! TARGET_POWERPC64"
12862 "*
12863 {
12864 if (which_alternative != 0)
12865 return \"#\";
12866 else if (get_attr_length (insn) == 4)
12867 return \"{bdn|bdnz} %l0\";
12868 else
12869 return \"bdz %$+8\;b %l0\";
12870 }"
12871 [(set_attr "type" "branch")
12872 (set_attr "length" "*,12,16")])
12874 (define_insn "*ctrdi_internal5"
12875 [(set (pc)
12876 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
12877 (const_int 1))
12878 (label_ref (match_operand 0 "" ""))
12879 (pc)))
12880 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12881 (plus:DI (match_dup 1)
12882 (const_int -1)))
12883 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12884 (clobber (match_scratch:DI 4 "=X,X,r"))]
12885 "TARGET_POWERPC64"
12886 "*
12887 {
12888 if (which_alternative != 0)
12889 return \"#\";
12890 else if (get_attr_length (insn) == 4)
12891 return \"bdz %l0\";
12892 else
12893 return \"{bdn|bdnz} %$+8\;b %l0\";
12894 }"
12895 [(set_attr "type" "branch")
12896 (set_attr "length" "*,12,16")])
12898 (define_insn "*ctrdi_internal6"
12899 [(set (pc)
12900 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
12901 (const_int 1))
12902 (pc)
12903 (label_ref (match_operand 0 "" ""))))
12904 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12905 (plus:DI (match_dup 1)
12906 (const_int -1)))
12907 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12908 (clobber (match_scratch:DI 4 "=X,X,r"))]
12909 "TARGET_POWERPC64"
12910 "*
12911 {
12912 if (which_alternative != 0)
12913 return \"#\";
12914 else if (get_attr_length (insn) == 4)
12915 return \"{bdn|bdnz} %l0\";
12916 else
12917 return \"bdz %$+8\;b %l0\";
12918 }"
12919 [(set_attr "type" "branch")
12920 (set_attr "length" "*,12,16")])
12922 ;; Now the splitters if we could not allocate the CTR register
12924 (define_split
12925 [(set (pc)
12926 (if_then_else (match_operator 2 "comparison_operator"
12927 [(match_operand:SI 1 "gpc_reg_operand" "")
12928 (const_int 1)])
12929 (match_operand 5 "" "")
12930 (match_operand 6 "" "")))
12931 (set (match_operand:SI 0 "gpc_reg_operand" "")
12932 (plus:SI (match_dup 1)
12933 (const_int -1)))
12934 (clobber (match_scratch:CC 3 ""))
12935 (clobber (match_scratch:SI 4 ""))]
12936 "! TARGET_POWERPC64 && reload_completed"
12937 [(parallel [(set (match_dup 3)
12938 (compare:CC (plus:SI (match_dup 1)
12939 (const_int -1))
12940 (const_int 0)))
12941 (set (match_dup 0)
12942 (plus:SI (match_dup 1)
12943 (const_int -1)))])
12944 (set (pc) (if_then_else (match_dup 7)
12945 (match_dup 5)
12946 (match_dup 6)))]
12947 "
12948 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
12949 const0_rtx); }")
12951 (define_split
12952 [(set (pc)
12953 (if_then_else (match_operator 2 "comparison_operator"
12954 [(match_operand:SI 1 "gpc_reg_operand" "")
12955 (const_int 1)])
12956 (match_operand 5 "" "")
12957 (match_operand 6 "" "")))
12958 (set (match_operand:SI 0 "nonimmediate_operand" "")
12959 (plus:SI (match_dup 1) (const_int -1)))
12960 (clobber (match_scratch:CC 3 ""))
12961 (clobber (match_scratch:SI 4 ""))]
12962 "! TARGET_POWERPC64 && reload_completed
12963 && ! gpc_reg_operand (operands[0], SImode)"
12964 [(parallel [(set (match_dup 3)
12965 (compare:CC (plus:SI (match_dup 1)
12966 (const_int -1))
12967 (const_int 0)))
12968 (set (match_dup 4)
12969 (plus:SI (match_dup 1)
12970 (const_int -1)))])
12971 (set (match_dup 0)
12972 (match_dup 4))
12973 (set (pc) (if_then_else (match_dup 7)
12974 (match_dup 5)
12975 (match_dup 6)))]
12976 "
12977 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
12978 const0_rtx); }")
12979 (define_split
12980 [(set (pc)
12981 (if_then_else (match_operator 2 "comparison_operator"
12982 [(match_operand:DI 1 "gpc_reg_operand" "")
12983 (const_int 1)])
12984 (match_operand 5 "" "")
12985 (match_operand 6 "" "")))
12986 (set (match_operand:DI 0 "gpc_reg_operand" "")
12987 (plus:DI (match_dup 1)
12988 (const_int -1)))
12989 (clobber (match_scratch:CC 3 ""))
12990 (clobber (match_scratch:DI 4 ""))]
12991 "TARGET_POWERPC64 && reload_completed"
12992 [(parallel [(set (match_dup 3)
12993 (compare:CC (plus:DI (match_dup 1)
12994 (const_int -1))
12995 (const_int 0)))
12996 (set (match_dup 0)
12997 (plus:DI (match_dup 1)
12998 (const_int -1)))])
12999 (set (pc) (if_then_else (match_dup 7)
13000 (match_dup 5)
13001 (match_dup 6)))]
13002 "
13003 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13004 const0_rtx); }")
13006 (define_split
13007 [(set (pc)
13008 (if_then_else (match_operator 2 "comparison_operator"
13009 [(match_operand:DI 1 "gpc_reg_operand" "")
13010 (const_int 1)])
13011 (match_operand 5 "" "")
13012 (match_operand 6 "" "")))
13013 (set (match_operand:DI 0 "nonimmediate_operand" "")
13014 (plus:DI (match_dup 1) (const_int -1)))
13015 (clobber (match_scratch:CC 3 ""))
13016 (clobber (match_scratch:DI 4 ""))]
13017 "TARGET_POWERPC64 && reload_completed
13018 && ! gpc_reg_operand (operands[0], DImode)"
13019 [(parallel [(set (match_dup 3)
13020 (compare:CC (plus:DI (match_dup 1)
13021 (const_int -1))
13022 (const_int 0)))
13023 (set (match_dup 4)
13024 (plus:DI (match_dup 1)
13025 (const_int -1)))])
13026 (set (match_dup 0)
13027 (match_dup 4))
13028 (set (pc) (if_then_else (match_dup 7)
13029 (match_dup 5)
13030 (match_dup 6)))]
13031 "
13032 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13033 const0_rtx); }")
13034 \f
13035 (define_insn "trap"
13036 [(trap_if (const_int 1) (const_int 0))]
13037 ""
13038 "{t 31,0,0|trap}")
13040 (define_expand "conditional_trap"
13041 [(trap_if (match_operator 0 "trap_comparison_operator"
13042 [(match_dup 2) (match_dup 3)])
13043 (match_operand 1 "const_int_operand" ""))]
13044 ""
13045 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13046 operands[2] = rs6000_compare_op0;
13047 operands[3] = rs6000_compare_op1;")
13049 (define_insn ""
13050 [(trap_if (match_operator 0 "trap_comparison_operator"
13051 [(match_operand:SI 1 "register_operand" "r")
13052 (match_operand:SI 2 "reg_or_short_operand" "rI")])
13053 (const_int 0))]
13054 ""
13055 "{t|tw}%V0%I2 %1,%2")
13057 (define_insn ""
13058 [(trap_if (match_operator 0 "trap_comparison_operator"
13059 [(match_operand:DI 1 "register_operand" "r")
13060 (match_operand:DI 2 "reg_or_short_operand" "rI")])
13061 (const_int 0))]
13062 "TARGET_POWERPC64"
13063 "td%V0%I2 %1,%2")
13064 \f
13065 ;; Insns related to generating the function prologue and epilogue.
13067 (define_expand "prologue"
13068 [(use (const_int 0))]
13069 "TARGET_SCHED_PROLOG"
13070 "
13071 {
13072 rs6000_emit_prologue ();
13073 DONE;
13074 }")
13076 (define_insn "movesi_from_cr"
13077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13078 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13079 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
13080 ""
13081 "mfcr %0")
13083 (define_insn "*stmw"
13084 [(match_parallel 0 "stmw_operation"
13085 [(set (match_operand:SI 1 "memory_operand" "=m")
13086 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13087 "TARGET_MULTIPLE"
13088 "{stm|stmw} %2,%1")
13090 (define_insn "*save_fpregs_si"
13091 [(match_parallel 0 "any_operand"
13092 [(clobber (match_operand:SI 1 "register_operand" "=l"))
13093 (use (match_operand:SI 2 "call_operand" "s"))
13094 (set (match_operand:DF 3 "memory_operand" "=m")
13095 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13096 "TARGET_32BIT"
13097 "bl %z2")
13099 (define_insn "*save_fpregs_di"
13100 [(match_parallel 0 "any_operand"
13101 [(clobber (match_operand:DI 1 "register_operand" "=l"))
13102 (use (match_operand:DI 2 "call_operand" "s"))
13103 (set (match_operand:DF 3 "memory_operand" "=m")
13104 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13105 "TARGET_64BIT"
13106 "bl %z2")
13108 ; These are to explain that changes to the stack pointer should
13109 ; not be moved over stores to stack memory.
13110 (define_insn "stack_tie"
13111 [(set (match_operand:BLK 0 "memory_operand" "+m")
13112 (unspec:BLK [(match_dup 0)] 5))]
13113 ""
13114 ""
13115 [(set_attr "length" "0")])
13118 (define_expand "epilogue"
13119 [(use (const_int 0))]
13120 "TARGET_SCHED_PROLOG"
13121 "
13122 {
13123 rs6000_emit_epilogue (FALSE);
13124 DONE;
13125 }")
13127 ; On some processors, doing the mtcrf one CC register at a time is
13128 ; faster (like on the 604e). On others, doing them all at once is
13129 ; faster; for instance, on the 601 and 750.
13131 (define_expand "movsi_to_cr_one"
13132 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13133 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13134 (match_dup 2)] 20))]
13135 ""
13136 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13138 (define_insn "*movsi_to_cr"
13139 [(match_parallel 0 "mtcrf_operation"
13140 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13141 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13142 (match_operand 3 "immediate_operand" "n")]
13143 20))])]
13144 ""
13145 "*
13146 {
13147 int mask = 0;
13148 int i;
13149 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13150 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13151 operands[4] = GEN_INT (mask);
13152 return \"mtcrf %4,%2\";
13153 }")
13155 (define_insn ""
13156 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13157 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13158 (match_operand 2 "immediate_operand" "n")] 20))]
13159 "GET_CODE (operands[0]) == REG
13160 && CR_REGNO_P (REGNO (operands[0]))
13161 && GET_CODE (operands[2]) == CONST_INT
13162 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13163 "mtcrf %R0,%1")
13165 ; The load-multiple instructions have similar properties.
13166 ; Note that "load_multiple" is a name known to the machine-independent
13167 ; code that actually corresponds to the powerpc load-string.
13169 (define_insn "*lmw"
13170 [(match_parallel 0 "lmw_operation"
13171 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13172 (match_operand:SI 2 "memory_operand" "m"))])]
13173 "TARGET_MULTIPLE"
13174 "{lm|lmw} %1,%2")
13176 (define_insn "*return_internal_si"
13177 [(return)
13178 (use (match_operand:SI 0 "register_operand" "lc"))]
13179 "TARGET_32BIT"
13180 "b%T0"
13181 [(set_attr "type" "jmpreg")])
13183 (define_insn "*return_internal_di"
13184 [(return)
13185 (use (match_operand:DI 0 "register_operand" "lc"))]
13186 "TARGET_64BIT"
13187 "b%T0"
13188 [(set_attr "type" "jmpreg")])
13190 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13191 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
13193 (define_insn "*return_and_restore_fpregs_si"
13194 [(match_parallel 0 "any_operand"
13195 [(return)
13196 (use (match_operand:SI 1 "register_operand" "l"))
13197 (use (match_operand:SI 2 "call_operand" "s"))
13198 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13199 (match_operand:DF 4 "memory_operand" "m"))])]
13200 "TARGET_32BIT"
13201 "b %z2")
13203 (define_insn "*return_and_restore_fpregs_di"
13204 [(match_parallel 0 "any_operand"
13205 [(return)
13206 (use (match_operand:DI 1 "register_operand" "l"))
13207 (use (match_operand:DI 2 "call_operand" "s"))
13208 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13209 (match_operand:DF 4 "memory_operand" "m"))])]
13210 "TARGET_64BIT"
13211 "b %z2")
13213 ; This is used in compiling the unwind routines.
13214 (define_expand "eh_return"
13215 [(use (match_operand 0 "general_operand" ""))
13216 (use (match_operand 1 "general_operand" ""))]
13217 ""
13218 "
13219 {
13220 #if TARGET_AIX
13221 rs6000_emit_eh_toc_restore (operands[0]);
13222 #endif
13223 if (TARGET_32BIT)
13224 emit_insn (gen_eh_set_lr_si (operands[1]));
13225 else
13226 emit_insn (gen_eh_set_lr_di (operands[1]));
13227 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
13228 DONE;
13229 }")
13231 ; We can't expand this before we know where the link register is stored.
13232 (define_insn "eh_set_lr_si"
13233 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
13234 (clobber (match_scratch:SI 1 "=&r"))]
13235 "TARGET_32BIT"
13236 "#")
13238 (define_insn "eh_set_lr_di"
13239 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
13240 (clobber (match_scratch:DI 1 "=&r"))]
13241 "TARGET_64BIT"
13242 "#")
13244 (define_split
13245 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
13246 (clobber (match_scratch 1 ""))]
13247 "reload_completed"
13248 [(const_int 0)]
13249 "
13250 {
13251 rs6000_stack_t *info = rs6000_stack_info ();
13253 if (info->lr_save_p)
13254 {
13255 rtx frame_rtx = stack_pointer_rtx;
13256 int sp_offset = 0;
13257 rtx tmp;
13259 if (frame_pointer_needed
13260 || current_function_calls_alloca
13261 || info->total_size > 32767)
13262 {
13263 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13264 frame_rtx = operands[1];
13265 }
13266 else if (info->push_p)
13267 sp_offset = info->total_size;
13269 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13270 tmp = gen_rtx_MEM (Pmode, tmp);
13271 emit_move_insn (tmp, operands[0]);
13272 }
13273 else
13274 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13275 DONE;
13276 }")