| blob | 7f806d4dcc64484ed3a51fe16c88499d9f20bed6 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
63 #endif
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
71 : 4)
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 const
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
107 in SFmode, DFmode and XFmode */
109 in SFmode, DFmode and XFmode */
112 in SImode and DImode */
114 in SImode and DImode */
117 in SImode, DImode and TImode */
119 in SImode, DImode and TImode */
147 };
149 /* Processor costs (relative to an add) */
150 static const
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
178 in SFmode, DFmode and XFmode */
180 in SFmode, DFmode and XFmode */
183 in SImode and DImode */
185 in SImode and DImode */
188 in SImode, DImode and TImode */
190 in SImode, DImode and TImode */
204 DUMMY_STRINGOP_ALGS},
206 DUMMY_STRINGOP_ALGS},
218 };
220 static const
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
248 in SFmode, DFmode and XFmode */
250 in SFmode, DFmode and XFmode */
253 in SImode and DImode */
255 in SImode and DImode */
258 in SImode, DImode and TImode */
260 in SImode, DImode and TImode */
263 shared for code and data, so 4kB is
264 not really precise. */
276 DUMMY_STRINGOP_ALGS},
278 DUMMY_STRINGOP_ALGS},
290 };
292 static const
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
320 in SFmode, DFmode and XFmode */
322 in SFmode, DFmode and XFmode */
325 in SImode and DImode */
327 in SImode and DImode */
330 in SImode, DImode and TImode */
332 in SImode, DImode and TImode */
346 DUMMY_STRINGOP_ALGS},
348 DUMMY_STRINGOP_ALGS},
360 };
362 static const
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
390 in SFmode, DFmode and XFmode */
392 in SFmode, DFmode and XFmode */
395 in SImode and DImode */
397 in SImode and DImode */
400 in SImode, DImode and TImode */
402 in SImode, DImode and TImode */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 */
422 DUMMY_STRINGOP_ALGS},
425 DUMMY_STRINGOP_ALGS},
437 };
439 static const
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
467 in SFmode, DFmode and XFmode */
469 in SFmode, DFmode and XFmode */
473 in SImode and DImode */
475 in SImode and DImode */
478 in SImode, DImode and TImode */
480 in SImode, DImode and TImode */
494 DUMMY_STRINGOP_ALGS},
496 DUMMY_STRINGOP_ALGS},
508 };
510 static const
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
538 in SFmode, DFmode and XFmode */
540 in SFmode, DFmode and XFmode */
543 in SImode and DImode */
545 in SImode and DImode */
548 in SImode, DImode and TImode */
550 in SImode, DImode and TImode */
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
567 DUMMY_STRINGOP_ALGS},
569 DUMMY_STRINGOP_ALGS},
581 };
583 static const
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
611 in SFmode, DFmode and XFmode */
613 in SFmode, DFmode and XFmode */
616 in SImode and DImode */
618 in SImode and DImode */
621 in SImode, DImode and TImode */
623 in SImode, DImode and TImode */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
640 DUMMY_STRINGOP_ALGS},
642 DUMMY_STRINGOP_ALGS},
654 };
656 static const
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
684 in SFmode, DFmode and XFmode */
686 in SFmode, DFmode and XFmode */
689 in SImode and DImode */
691 in SImode and DImode */
694 in SImode, DImode and TImode */
696 in SImode, DImode and TImode */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
705 time). */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
733 };
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
762 in SFmode, DFmode and XFmode */
764 in SFmode, DFmode and XFmode */
767 in SImode and DImode */
769 in SImode and DImode */
772 in SImode, DImode and TImode */
774 in SImode, DImode and TImode */
776 /* On K8
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
779 On AMDFAM10
780 MOVD reg64, xmmreg Double FADD 3
781 1/1 1/1
782 MOVD reg32, xmmreg Double FADD 3
783 1/1 1/1 */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
791 time). */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
820 };
822 static const
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
850 in SFmode, DFmode and XFmode */
852 in SFmode, DFmode and XFmode */
855 in SImode and DImode */
857 in SImode and DImode */
860 in SImode, DImode and TImode */
862 in SImode, DImode and TImode */
876 DUMMY_STRINGOP_ALGS},
879 DUMMY_STRINGOP_ALGS},
891 };
893 static const
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
921 in SFmode, DFmode and XFmode */
923 in SFmode, DFmode and XFmode */
926 in SImode and DImode */
928 in SImode and DImode */
931 in SImode, DImode and TImode */
933 in SImode, DImode and TImode */
964 };
966 static const
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
994 in SFmode, DFmode and XFmode */
996 in SFmode, DFmode and XFmode */
999 in SImode and DImode */
1001 in SImode and DImode */
1004 in SImode, DImode and TImode */
1006 in SImode, DImode and TImode */
1037 };
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1040 static const
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1072 in SFmode, DFmode and XFmode */
1074 in SFmode, DFmode and XFmode */
1077 in SImode and DImode */
1079 in SImode and DImode */
1082 in SImode, DImode and TImode */
1084 in SImode, DImode and TImode */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1114 };
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1117 static const
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1145 in SFmode, DFmode and XFmode */
1147 in SFmode, DFmode and XFmode */
1150 in SImode and DImode */
1152 in SImode and DImode */
1155 in SImode, DImode and TImode */
1157 in SImode, DImode and TImode */
1171 DUMMY_STRINGOP_ALGS},
1173 DUMMY_STRINGOP_ALGS},
1185 };
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1226 /* X86_TUNE_PUSH_MEMORY */
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1265 m_PPRO,
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1276 /* X86_TUNE_USE_MOV0 */
1277 m_K6,
1279 /* X86_TUNE_USE_CLTD */
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1283 m_PENT4,
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1286 m_PPRO,
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1298 /* X86_TUNE_FAST_PREFIX */
1301 /* X86_TUNE_SINGLE_STRINGOP */
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1317 m_PPRO,
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1322 /* X86_TUNE_ADD_ESP_8 */
1326 /* X86_TUNE_SUB_ESP_4 */
1329 /* X86_TUNE_SUB_ESP_8 */
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1353 m_AMDFAM10,
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1359 m_ATHLON_K8,
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1362 m_AMD_MULTIPLE,
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1380 m_AMD_MULTIPLE,
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1392 /* X86_TUNE_SCHEDULE */
1395 /* X86_TUNE_USE_BT */
1398 /* X86_TUNE_USE_INCDEC */
1401 /* X86_TUNE_PAD_RETURNS */
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1422 machines. */
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1426 than a MOV. */
1427 m_PENT,
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1431 m_PENT,
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1436 m_K6,
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1439 from FP to FP. */
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1444 m_AMDFAM10,
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1449 m_CORE2,
1450 };
1452 /* Feature tests against the various architecture variations. */
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1472 };
1474 static const unsigned int x86_accumulate_outgoing_args
1477 static const unsigned int x86_arch_always_fancy_math_387
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1485 epilogue code. */
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1497 {
1498 /* ax, dx, cx, bx */
1500 /* si, di, bp, sp */
1502 /* FP registers */
1505 /* arg pointer */
1506 NON_Q_REGS,
1507 /* flags, fpsr, fpcr, frame */
1509 /* SSE registers */
1512 /* MMX registers */
1515 /* REX registers */
1518 /* SSE REX registers */
1521 };
1523 /* The "default" register map used in 32bit mode. */
1526 {
1534 };
1537 {
1540 };
1543 {
1546 };
1549 {
1551 };
1553 /* The "default" register map used in 64bit mode. */
1555 {
1563 };
1565 /* Define the register numbers to be used in Dwarf debugging information.
1566 The SVR4 reference port C compiler uses the following register numbers
1567 in its Dwarf output code:
1568 0 for %eax (gcc regno = 0)
1569 1 for %ecx (gcc regno = 2)
1570 2 for %edx (gcc regno = 1)
1571 3 for %ebx (gcc regno = 3)
1572 4 for %esp (gcc regno = 7)
1573 5 for %ebp (gcc regno = 6)
1574 6 for %esi (gcc regno = 4)
1575 7 for %edi (gcc regno = 5)
1576 The following three DWARF register numbers are never generated by
1577 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1578 believes these numbers have these meanings.
1579 8 for %eip (no gcc equivalent)
1580 9 for %eflags (gcc regno = 17)
1581 10 for %trapno (no gcc equivalent)
1582 It is not at all clear how we should number the FP stack registers
1583 for the x86 architecture. If the version of SDB on x86/svr4 were
1584 a bit less brain dead with respect to floating-point then we would
1585 have a precedent to follow with respect to DWARF register numbers
1586 for x86 FP registers, but the SDB on x86/svr4 is so completely
1587 broken with respect to FP registers that it is hardly worth thinking
1588 of it as something to strive for compatibility with.
1589 The version of x86/svr4 SDB I have at the moment does (partially)
1590 seem to believe that DWARF register number 11 is associated with
1591 the x86 register %st(0), but that's about all. Higher DWARF
1592 register numbers don't seem to be associated with anything in
1593 particular, and even for DWARF regno 11, SDB only seems to under-
1594 stand that it should say that a variable lives in %st(0) (when
1595 asked via an `=' command) if we said it was in DWARF regno 11,
1596 but SDB still prints garbage when asked for the value of the
1597 variable in question (via a `/' command).
1598 (Also note that the labels SDB prints for various FP stack regs
1599 when doing an `x' command are all wrong.)
1600 Note that these problems generally don't affect the native SVR4
1601 C compiler because it doesn't allow the use of -O with -g and
1602 because when it is *not* optimizing, it allocates a memory
1603 location for each floating-point variable, and the memory
1604 location is what gets described in the DWARF AT_location
1605 attribute for the variable in question.
1606 Regardless of the severe mental illness of the x86/svr4 SDB, we
1607 do something sensible here and we use the following DWARF
1608 register numbers. Note that these are all stack-top-relative
1609 numbers.
1610 11 for %st(0) (gcc regno = 8)
1611 12 for %st(1) (gcc regno = 9)
1612 13 for %st(2) (gcc regno = 10)
1613 14 for %st(3) (gcc regno = 11)
1614 15 for %st(4) (gcc regno = 12)
1615 16 for %st(5) (gcc regno = 13)
1616 17 for %st(6) (gcc regno = 14)
1617 18 for %st(7) (gcc regno = 15)
1618 */
1620 {
1628 };
1630 /* Test and compare insns in i386.md store the information needed to
1631 generate branch and scc insns here. */
1637 /* Define the structure for the machine field in struct function. */
1640 {
1643 rtx rtl;
1645 };
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1650 [arguments]
1651 <- ARG_POINTER
1652 saved pc
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1656 [saved regs]
1658 [padding1] \
1659 )
1660 [va_arg registers] (
1661 > to_allocate <- FRAME_POINTER
1662 [frame] (
1663 )
1664 [padding2] /
1665 */
1666 struct ix86_frame
1667 {
1671 HOST_WIDE_INT frame;
1676 HOST_WIDE_INT to_allocate;
1677 /* The offsets relative to ARG_POINTER. */
1678 HOST_WIDE_INT frame_pointer_offset;
1679 HOST_WIDE_INT hard_frame_pointer_offset;
1680 HOST_WIDE_INT stack_pointer_offset;
1682 /* When save_regs_using_mov is set, emit prologue using
1683 move instead of push instructions. */
1685 };
1687 /* Code model option. */
1689 /* Asm dialect. */
1691 /* TLS dialects. */
1694 /* Which unit we are generating floating point math for. */
1697 /* Which cpu are we scheduling for. */
1700 /* Which cpu are we optimizing for. */
1703 /* Which instruction set architecture to use. */
1706 /* true if sse prefetch instruction is not NOOP. */
1709 /* ix86_regparm_string as a number */
1712 /* -mstackrealign option */
1726 /* Preferred alignment for stack boundary in bits. */
1729 /* Alignment for incoming stack boundary in bits specified at
1730 command line. */
1733 /* Default alignment for incoming stack boundary in bits. */
1736 /* Alignment for incoming stack boundary in bits. */
1739 /* Values 1-5: see jump.c */
1742 /* Calling abi specific va_list type nodes. */
1746 /* Variables which are this size or smaller are put in the data/bss
1747 or ldata/lbss sections. */
1751 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1755 /* Fence to use after loop using movnt. */
1756 tree x86_mfence;
1758 /* Register class used for passing given 64bit part of the argument.
1759 These represent classes as documented by the PS ABI, with the exception
1760 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1761 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1763 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1764 whenever possible (upper half does contain padding). */
1765 enum x86_64_reg_class
1766 {
1767 X86_64_NO_CLASS,
1768 X86_64_INTEGER_CLASS,
1769 X86_64_INTEGERSI_CLASS,
1770 X86_64_AVX_CLASS,
1771 X86_64_SSE_CLASS,
1772 X86_64_SSESF_CLASS,
1773 X86_64_SSEDF_CLASS,
1774 X86_64_SSEUP_CLASS,
1775 X86_64_X87_CLASS,
1776 X86_64_X87UP_CLASS,
1777 X86_64_COMPLEX_X87_CLASS,
1778 X86_64_MEMORY_CLASS
1779 };
1781 {
1784 };
1786 #define MAX_CLASSES 4
1788 /* Table of constants used by fldpi, fldln2, etc.... */
1792 \f
1801 enum ix86_function_specific_strings
1802 {
1803 IX86_FUNCTION_SPECIFIC_ARCH,
1804 IX86_FUNCTION_SPECIFIC_TUNE,
1805 IX86_FUNCTION_SPECIFIC_FPMATH,
1806 IX86_FUNCTION_SPECIFIC_MAX
1807 };
1821 \f
1822 /* The svr4 ABI for the i386 says that records and unions are returned
1823 in memory. */
1824 #ifndef DEFAULT_PCC_STRUCT_RETURN
1825 #define DEFAULT_PCC_STRUCT_RETURN 1
1826 #endif
1828 /* Whether -mtune= or -march= were specified */
1832 /* Bit flags that specify the ISA we are compiling for. */
1835 /* A mask of ix86_isa_flags that includes bit X if X
1836 was set or cleared on the command line. */
1839 /* Define a set of ISAs which are available when a given ISA is
1840 enabled. MMX and SSE ISAs are handled separately. */
1842 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1843 #define OPTION_MASK_ISA_3DNOW_SET \
1844 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1846 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1847 #define OPTION_MASK_ISA_SSE2_SET \
1848 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1849 #define OPTION_MASK_ISA_SSE3_SET \
1850 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1851 #define OPTION_MASK_ISA_SSSE3_SET \
1852 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1853 #define OPTION_MASK_ISA_SSE4_1_SET \
1854 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1855 #define OPTION_MASK_ISA_SSE4_2_SET \
1856 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1857 #define OPTION_MASK_ISA_AVX_SET \
1858 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1859 #define OPTION_MASK_ISA_FMA_SET \
1860 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1862 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1863 as -msse4.2. */
1864 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1866 #define OPTION_MASK_ISA_SSE4A_SET \
1867 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1868 #define OPTION_MASK_ISA_SSE5_SET \
1869 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1871 /* AES and PCLMUL need SSE2 because they use xmm registers */
1872 #define OPTION_MASK_ISA_AES_SET \
1873 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1874 #define OPTION_MASK_ISA_PCLMUL_SET \
1875 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1877 #define OPTION_MASK_ISA_ABM_SET \
1878 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1879 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1880 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1881 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1883 /* Define a set of ISAs which aren't available when a given ISA is
1884 disabled. MMX and SSE ISAs are handled separately. */
1886 #define OPTION_MASK_ISA_MMX_UNSET \
1887 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1888 #define OPTION_MASK_ISA_3DNOW_UNSET \
1889 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1890 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1892 #define OPTION_MASK_ISA_SSE_UNSET \
1893 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1894 #define OPTION_MASK_ISA_SSE2_UNSET \
1895 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1896 #define OPTION_MASK_ISA_SSE3_UNSET \
1897 (OPTION_MASK_ISA_SSE3 \
1898 | OPTION_MASK_ISA_SSSE3_UNSET \
1899 | OPTION_MASK_ISA_SSE4A_UNSET )
1900 #define OPTION_MASK_ISA_SSSE3_UNSET \
1901 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1902 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1903 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1904 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1905 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1906 #define OPTION_MASK_ISA_AVX_UNSET \
1907 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1908 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1910 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1911 as -mno-sse4.1. */
1912 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1914 #define OPTION_MASK_ISA_SSE4A_UNSET \
1915 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1916 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1917 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1918 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1919 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1920 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1921 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1922 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1924 /* Vectorization library interface and handlers. */
1929 /* Processor target table, indexed by processor number */
1930 struct ptt
1931 {
1938 };
1941 {
1956 };
1959 {
1980 "amdfam10"
1981 };
1982 \f
1983 /* Implement TARGET_HANDLE_OPTION. */
1985 static bool
1987 {
1989 {
1992 {
1995 }
1996 else
1997 {
2000 }
2005 {
2008 }
2009 else
2010 {
2013 }
2021 {
2024 }
2025 else
2026 {
2029 }
2034 {
2037 }
2038 else
2039 {
2042 }
2047 {
2050 }
2051 else
2052 {
2055 }
2060 {
2063 }
2064 else
2065 {
2068 }
2073 {
2076 }
2077 else
2078 {
2081 }
2086 {
2089 }
2090 else
2091 {
2094 }
2099 {
2102 }
2103 else
2104 {
2107 }
2112 {
2115 }
2116 else
2117 {
2120 }
2135 {
2138 }
2139 else
2140 {
2143 }
2148 {
2151 }
2152 else
2153 {
2156 }
2161 {
2164 }
2165 else
2166 {
2169 }
2174 {
2177 }
2178 else
2179 {
2182 }
2187 {
2190 }
2191 else
2192 {
2195 }
2200 {
2203 }
2204 else
2205 {
2208 }
2213 {
2216 }
2217 else
2218 {
2221 }
2226 {
2229 }
2230 else
2231 {
2234 }
2239 }
2240 }
2241 \f
2242 /* Return a string the documents the current -m options. The caller is
2243 responsible for freeing the string. */
2248 {
2249 struct ix86_target_opts
2250 {
2253 };
2255 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2256 preceding options while match those first. */
2258 {
2275 };
2277 /* Flag options. */
2279 {
2301 };
2319 /* Add -march= option. */
2321 {
2324 }
2326 /* Add -mtune= option. */
2328 {
2331 }
2333 /* Pick out the options in isa options. */
2335 {
2337 {
2340 }
2341 }
2344 {
2347 }
2349 /* Add flag options. */
2351 {
2353 {
2356 }
2357 }
2360 {
2363 }
2365 /* Add -fpmath= option. */
2367 {
2370 }
2372 /* Any options? */
2378 /* Size the string. */
2382 {
2387 }
2389 /* Build the string. */
2394 {
2401 {
2403 line_len++;
2406 {
2410 }
2411 }
2415 {
2419 }
2420 }
2426 }
2428 /* Function that is callable from the debugger to print the current
2429 options. */
2430 void
2432 {
2438 {
2441 }
2442 else
2446 }
2447 \f
2448 /* Sometimes certain combinations of command options do not make
2449 sense on a particular target machine. You can define a macro
2450 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2451 defined, is executed once just after all the command options have
2452 been parsed.
2454 Don't use this macro to turn on various extra optimizations for
2455 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 void
2459 {
2466 /* Comes from final.c -- no real reason to change it. */
2467 #define MAX_CODE_ALIGN 16
2469 enum pta_flags
2470 {
2492 };
2494 static struct pta
2495 {
2500 }
2502 {
2581 };
2585 /* Set up prefix/suffix so the error messages refer to either the command
2586 line argument, or the attribute(target). */
2588 {
2592 }
2593 else
2594 {
2598 }
2600 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2601 SUBTARGET_OVERRIDE_OPTIONS;
2602 #endif
2604 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2605 SUBSUBTARGET_OVERRIDE_OPTIONS;
2606 #endif
2608 /* -fPIC is the default for x86_64. */
2612 /* Set the default values for switches whose default depends on TARGET_64BIT
2613 in case they weren't overwritten by command line options. */
2615 {
2616 /* Mach-O doesn't support omitting the frame pointer for now. */
2623 }
2624 else
2625 {
2632 }
2634 /* Need to check -mtune=generic first. */
2636 {
2639 /* As special support for cross compilers we read -mtune=native
2640 as -mtune=generic. With native compilers we won't see the
2641 -mtune=native, as it was changed by the driver. */
2643 {
2646 else
2648 }
2649 /* If this call is for setting the option attribute, allow the
2650 generic32/generic64 that was previously set. */
2654 ;
2658 }
2659 else
2660 {
2664 {
2667 }
2669 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2670 need to use a sensible tune option. */
2674 {
2677 else
2679 }
2680 }
2682 {
2697 else
2700 }
2708 else
2719 {
2732 else
2735 }
2736 else
2737 {
2738 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2739 use of rip-relative addressing. This eliminates fixups that
2740 would otherwise be needed if this object is to be placed in a
2741 DLL, and is essentially just as efficient as direct addressing. */
2746 else
2748 }
2750 {
2756 else
2759 }
2769 {
2772 /* Default cpu tuning to the architecture. */
2840 }
2852 {
2856 {
2858 {
2866 }
2867 else
2870 }
2871 /* Intel CPUs have always interpreted SSE prefetch instructions as
2872 NOPs; so, we can enable SSE prefetch instructions even when
2873 -mtune (rather than -march) points us to a processor that has them.
2874 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2875 higher processors. */
2880 }
2891 else
2894 /* Arrange to set up i386_stack_locals for all functions. */
2897 /* Validate -mregparm= value. */
2899 {
2906 else
2908 }
2912 /* If the user has provided any of the -malign-* options,
2913 warn and use that value only if -falign-* is not set.
2914 Remove this code in GCC 3.2 or later. */
2916 {
2920 {
2925 else
2927 }
2928 }
2931 {
2935 {
2940 else
2942 }
2943 }
2946 {
2950 {
2955 else
2957 }
2958 }
2960 /* Default align_* from the processor table. */
2962 {
2965 }
2967 {
2970 }
2972 {
2974 }
2976 /* Validate -mbranch-cost= value, or provide default. */
2979 {
2983 else
2985 }
2987 {
2991 else
2993 }
2996 {
3003 else
3006 }
3009 {
3013 }
3016 {
3019 /* Enable by default the SSE and MMX builtins. Do allow the user to
3020 explicitly disable any of these. In particular, disabling SSE and
3021 MMX for kernel code is extremely useful. */
3023 ix86_isa_flags
3029 }
3030 else
3031 {
3035 ix86_isa_flags
3038 /* i386 ABI does not specify red zone. It still makes sense to use it
3039 when programmer takes care to stack from being destroyed. */
3042 }
3044 /* Keep nonleaf frame pointers. */
3050 /* If we're doing fast math, we don't care about comparison order
3051 wrt NaNs. This lets us use a shorter comparison sequence. */
3055 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3056 since the insns won't need emulation. */
3060 /* Likewise, if the target doesn't have a 387, or we've specified
3061 software floating point, don't use 387 inline intrinsics. */
3065 /* Turn on MMX builtins for -msse. */
3067 {
3070 }
3072 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3076 /* Validate -mpreferred-stack-boundary= value or default it to
3077 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3080 {
3085 else
3087 }
3089 /* Set the default value for -mstackrealign. */
3093 /* Validate -mincoming-stack-boundary= value or default it to
3094 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3097 else
3101 {
3106 else
3107 {
3109 ix86_incoming_stack_boundary
3111 }
3112 }
3114 /* Accept -msseregparm only if at least SSE support is enabled. */
3121 {
3125 {
3127 {
3130 }
3131 else
3133 }
3139 {
3141 {
3144 }
3146 {
3149 }
3150 else
3152 }
3153 else
3156 }
3158 /* If the i387 is disabled, then do not return values in it. */
3162 /* Use external vectorized library in vectorizing intrinsics. */
3164 {
3169 else
3173 }
3180 /* ??? Unwind info is not correct around the CFG unless either a frame
3181 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3182 unwind info generation to be aware of the CFG and propagating states
3183 around edges. */
3186 && flag_omit_frame_pointer
3188 {
3194 }
3196 /* If stack probes are required, the space used for large function
3197 arguments on the stack must also be probed, so enable
3198 -maccumulate-outgoing-args so this happens in the prologue. */
3201 {
3206 }
3208 /* For sane SSE instruction set generation we need fcomi instruction.
3209 It is safe to enable all CMOVE instructions. */
3213 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3214 {
3220 }
3222 /* When scheduling description is not available, disable scheduler pass
3223 so it won't slow down the compilation and make x87 code slower. */
3237 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3238 can be optimized to ap = __builtin_next_arg (0). */
3243 {
3252 }
3253 else
3254 {
3263 }
3265 #ifdef USE_IX86_CLD
3266 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 #endif
3271 /* Save the initial options in case the user does function specific options */
3273 target_option_default_node = target_option_current_node
3275 }
3276 \f
3277 /* Save the current options */
3279 static void
3281 {
3297 }
3299 /* Restore the current options */
3301 static void
3303 {
3319 /* Recreate the arch feature tests if the arch changed */
3321 {
3326 }
3328 /* Recreate the tune optimization tests */
3330 {
3335 }
3336 }
3338 /* Print the current options */
3340 static void
3343 {
3368 {
3371 }
3372 }
3374 \f
3375 /* Inner function to process the attribute((target(...))), take an argument and
3376 set the current options from the argument. If we have a list, recursively go
3377 over the list. */
3379 static bool
3381 {
3385 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3386 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3387 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3388 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3390 enum ix86_opt_type
3391 {
3392 ix86_opt_unknown,
3393 ix86_opt_yes,
3394 ix86_opt_no,
3395 ix86_opt_str,
3396 ix86_opt_isa
3397 };
3399 static const struct
3400 {
3407 /* isa options */
3424 /* string options */
3429 /* flag options */
3431 OPT_mcld,
3432 MASK_CLD),
3435 OPT_mfancy_math_387,
3436 MASK_NO_FANCY_MATH_387),
3439 OPT_mfused_madd,
3440 MASK_NO_FUSED_MADD),
3443 OPT_mieee_fp,
3444 MASK_IEEE_FP),
3447 OPT_minline_all_stringops,
3448 MASK_INLINE_ALL_STRINGOPS),
3451 OPT_minline_stringops_dynamically,
3452 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3455 OPT_mno_align_stringops,
3456 MASK_NO_ALIGN_STRINGOPS),
3459 OPT_mrecip,
3460 MASK_RECIP),
3462 };
3464 /* If this is a list, recurse to get the options. */
3466 {
3475 }
3480 /* Handle multiple arguments separated by commas. */
3484 {
3498 {
3502 }
3503 else
3504 {
3507 }
3509 /* Recognize no-xxx. */
3511 {
3515 }
3516 else
3519 /* Find the option. */
3523 {
3529 {
3534 }
3535 }
3537 /* Process the option. */
3539 {
3542 }
3548 {
3554 else
3556 }
3559 {
3561 {
3564 }
3565 else
3567 }
3569 else
3571 }
3574 }
3576 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3578 tree
3580 {
3592 /* Process each of the options on the chain. */
3596 /* If the changed options are different from the default, rerun override_options,
3597 and then save the options away. The string options are are attribute options,
3598 and will be undone when we copy the save structure. */
3604 {
3605 /* If we are using the default tune= or arch=, undo the string assigned,
3606 and use the default. */
3617 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3623 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3626 /* Add any builtin functions with the new isa if any. */
3629 /* Save the current options unless we are validating options for
3630 #pragma. */
3637 /* Free up memory allocated to hold the strings */
3641 }
3644 }
3646 /* Hook to validate attribute((target("string"))). */
3648 static bool
3651 tree args,
3653 {
3660 /* If the function changed the optimization levels as well as setting target
3661 options, start with the optimizations specified. */
3665 /* The target attributes may also change some optimization flags, so update
3666 the optimization options if necessary. */
3675 {
3680 }
3688 }
3690 \f
3691 /* Hook to determine if one function can safely inline another. */
3693 static bool
3695 {
3700 /* If callee has no option attributes, then it is ok to inline. */
3704 /* If caller has no option attributes, but callee does then it is not ok to
3705 inline. */
3709 else
3710 {
3714 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3715 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3716 function. */
3721 /* See if we have the same non-isa options. */
3725 /* See if arch, tune, etc. are the same. */
3738 else
3740 }
3743 }
3745 \f
3746 /* Remember the last target of ix86_set_current_function. */
3749 /* Establish appropriate back-end context for processing the function
3750 FNDECL. The argument might be NULL to indicate processing at top
3751 level, outside of any function scope. */
3752 static void
3754 {
3755 /* Only change the context if the function changes. This hook is called
3756 several times in the course of compiling a function, and we don't want to
3757 slow things down too much or call target_reinit when it isn't safe. */
3759 {
3760 tree old_tree = (ix86_previous_fndecl
3764 tree new_tree = (fndecl
3770 ;
3773 {
3776 }
3779 {
3785 }
3786 }
3787 }
3789 \f
3790 /* Return true if this goes in large data/bss. */
3792 static bool
3794 {
3798 /* Functions are never large data. */
3803 {
3809 }
3810 else
3811 {
3814 /* If this is an incomplete type with size 0, then we can't put it
3815 in data because it might be too big when completed. */
3818 }
3821 }
3823 /* Switch to the appropriate section for output of DECL.
3824 DECL is either a `VAR_DECL' node or a constant of some sort.
3825 RELOC indicates whether forming the initial value of DECL requires
3826 link-time relocations. */
3829 ATTRIBUTE_UNUSED;
3834 {
3837 {
3841 {
3875 /* We don't split these for medium model. Place them into
3876 default sections and hope for best. */
3881 }
3883 {
3884 /* We might get called with string constants, but get_named_section
3885 doesn't like them as they are not DECLs. Also, we need to set
3886 flags in that case. */
3890 }
3891 }
3893 }
3895 /* Build up a unique section name, expressed as a
3896 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3897 RELOC indicates whether the initial value of EXP requires
3898 link-time relocations. */
3900 static void ATTRIBUTE_UNUSED
3902 {
3905 {
3907 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3911 {
3935 /* We don't split these for medium model. Place them into
3936 default sections and hope for best. */
3944 }
3946 {
3953 /* If we're using one_only, then there needs to be a .gnu.linkonce
3954 prefix to the section name. */
3961 }
3962 }
3964 }
3966 #ifdef COMMON_ASM_OP
3967 /* This says how to output assembler code to declare an
3968 uninitialized external linkage data object.
3970 For medium model x86-64 we need to use .largecomm opcode for
3971 large objects. */
3972 void
3976 {
3980 else
3985 }
3986 #endif
3988 /* Utility function for targets to use in implementing
3989 ASM_OUTPUT_ALIGNED_BSS. */
3991 void
3995 {
3999 else
4002 #ifdef ASM_DECLARE_OBJECT_NAME
4005 #else
4006 /* Standard thing is just output label for the object. */
4010 }
4011 \f
4012 void
4014 {
4015 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4016 make the problem with not enough registers even worse. */
4017 #ifdef INSN_SCHEDULING
4020 #endif
4023 /* The Darwin libraries never set errno, so we might as well
4024 avoid calling them when that's the only reason we would. */
4027 /* The default values of these switches depend on the TARGET_64BIT
4028 that is not known at this moment. Mark these values with 2 and
4029 let user the to override these. In case there is no command line option
4030 specifying them, we will set the defaults in override_options. */
4036 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4037 SUBTARGET_OPTIMIZATION_OPTIONS;
4038 #endif
4039 }
4040 \f
4041 /* Decide whether we can make a sibling call to a function. DECL is the
4042 declaration of the function being targeted by the call and EXP is the
4043 CALL_EXPR representing the call. */
4045 static bool
4047 {
4048 tree func;
4051 /* If we are generating position-independent code, we cannot sibcall
4052 optimize any indirect call, or a direct call to a global function,
4053 as the PLT requires %ebx be live. */
4059 else
4060 {
4064 }
4066 /* Check that the return value locations are the same. Like
4067 if we are returning floats on the 80387 register stack, we cannot
4068 make a sibcall from a function that doesn't return a float to a
4069 function that does or, conversely, from a function that does return
4070 a float to a function that doesn't; the necessary stack adjustment
4071 would not be executed. This is also the place we notice
4072 differences in the return value ABI. Note that it is ok for one
4073 of the functions to have void return type as long as the return
4074 value of the other is passed in a register. */
4079 {
4082 }
4084 ;
4088 /* If this call is indirect, we'll need to be able to use a call-clobbered
4089 register for the address of the target function. Make sure that all
4090 such registers are not used for passing parameters. */
4092 {
4093 tree type;
4095 /* We're looking at the CALL_EXPR, we need the type of the function. */
4101 {
4102 /* ??? Need to count the actual number of registers to be used,
4103 not the possible number of registers. Fix later. */
4105 }
4106 }
4108 /* Dllimport'd functions are also called indirectly. */
4110 && !TARGET_64BIT
4115 /* If we need to align the outgoing stack, then sibcalling would
4116 unalign the stack, which may break the called function. */
4120 /* Otherwise okay. That also includes certain types of indirect calls. */
4122 }
4124 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4125 calling convention attributes;
4126 arguments as in struct attribute_spec.handler. */
4128 static tree
4130 tree args,
4133 {
4138 {
4143 }
4145 /* Can combine regparm with all attributes but fastcall. */
4147 {
4148 tree cst;
4151 {
4153 }
4157 {
4162 }
4164 {
4168 }
4171 }
4174 {
4175 /* Do not warn when emulating the MS ABI. */
4181 }
4183 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4185 {
4187 {
4189 }
4191 {
4193 }
4195 {
4197 }
4198 }
4200 /* Can combine stdcall with fastcall (redundant), regparm and
4201 sseregparm. */
4203 {
4205 {
4207 }
4209 {
4211 }
4212 }
4214 /* Can combine cdecl with regparm and sseregparm. */
4216 {
4218 {
4220 }
4222 {
4224 }
4225 }
4227 /* Can combine sseregparm with all attributes. */
4230 }
4232 /* Return 0 if the attributes for two types are incompatible, 1 if they
4233 are compatible, and 2 if they are nearly compatible (which causes a
4234 warning to be generated). */
4236 static int
4238 {
4239 /* Check for mismatch of non-default calling convention. */
4246 /* Check for mismatched fastcall/regparm types. */
4253 /* Check for mismatched sseregparm types. */
4258 /* Check for mismatched return types (cdecl vs stdcall). */
4264 }
4265 \f
4266 /* Return the regparm value for a function with the indicated TYPE and DECL.
4267 DECL may be NULL when calling function indirectly
4268 or considering a libcall. */
4270 static int
4272 {
4273 tree attr;
4279 {
4283 }
4287 {
4288 regparm
4292 {
4293 /* We can't use regparm(3) for nested functions because
4294 these pass static chain pointer in %ecx register. */
4298 {
4302 }
4303 }
4306 }
4311 /* Use register calling convention for local functions when possible. */
4314 {
4315 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4318 {
4322 /* Make sure no regparm register is taken by a
4323 fixed register variable. */
4328 /* We can't use regparm(3) for nested functions as these use
4329 static chain pointer in third argument. */
4335 /* If the function realigns its stackpointer, the prologue will
4336 clobber %ecx. If we've already generated code for the callee,
4337 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4338 scanning the attributes for the self-realigning property. */
4340 /* Since current internal arg pointer won't conflict with
4341 parameter passing regs, so no need to change stack
4342 realignment and adjust regparm number.
4344 Each fixed register usage increases register pressure,
4345 so less registers should be used for argument passing.
4346 This functionality can be overriden by an explicit
4347 regparm value. */
4350 globals++;
4352 local_regparm
4357 }
4358 }
4361 }
4363 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4364 DFmode (2) arguments in SSE registers for a function with the
4365 indicated TYPE and DECL. DECL may be NULL when calling function
4366 indirectly or considering a libcall. Otherwise return 0. */
4368 static int
4370 {
4373 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4374 by the sseregparm attribute. */
4377 {
4379 {
4381 {
4385 else
4388 }
4390 }
4393 }
4395 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4396 (and DFmode for SSE2) arguments in SSE registers. */
4398 {
4399 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4403 }
4406 }
4408 /* Return true if EAX is live at the start of the function. Used by
4409 ix86_expand_prologue to determine if we need special help before
4410 calling allocate_stack_worker. */
4412 static bool
4414 {
4415 /* Cheat. Don't bother working forward from ix86_function_regparm
4416 to the function type to whether an actual argument is located in
4417 eax. Instead just look at cfg info, which is still close enough
4418 to correct at this point. This gives false positives for broken
4419 functions that might use uninitialized data that happens to be
4420 allocated in eax, but who cares? */
4422 }
4424 /* Value is the number of bytes of arguments automatically
4425 popped when returning from a subroutine call.
4426 FUNDECL is the declaration node of the function (as a tree),
4427 FUNTYPE is the data type of the function (as a tree),
4428 or for a library call it is an identifier node for the subroutine name.
4429 SIZE is the number of bytes of arguments passed on the stack.
4431 On the 80386, the RTD insn may be used to pop them if the number
4432 of args is fixed, but if the number is variable then the caller
4433 must pop them all. RTD can't be used for library calls now
4434 because the library is compiled with the Unix compiler.
4435 Use of RTD is a selectable option, since it is incompatible with
4436 standard Unix calling sequences. If the option is not selected,
4437 the caller must always pop the args.
4439 The attribute stdcall is equivalent to RTD on a per module basis. */
4441 int
4443 {
4446 /* None of the 64-bit ABIs pop arguments. */
4452 /* Cdecl functions override -mrtd, and never pop the stack. */
4454 {
4455 /* Stdcall and fastcall functions will pop the stack if not
4456 variable args. */
4463 }
4465 /* Lose any fake structure return argument if it is passed on the stack. */
4468 {
4472 }
4475 }
4476 \f
4477 /* Argument support functions. */
4479 /* Return true when register may be used to pass function parameters. */
4480 bool
4482 {
4487 {
4491 else
4497 }
4500 {
4503 }
4504 else
4505 {
4509 }
4511 /* TODO: The function should depend on current function ABI but
4512 builtins.c would need updating then. Therefore we use the
4513 default ABI. */
4515 /* RAX is used as hidden argument to va_arg functions. */
4521 else
4528 }
4530 /* Return if we do not know how to pass TYPE solely in registers. */
4532 static bool
4534 {
4538 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4539 The layout_type routine is crafty and tries to trick us into passing
4540 currently unsupported vector types on the stack by using TImode. */
4543 }
4545 /* It returns the size, in bytes, of the area reserved for arguments passed
4546 in registers for the function represented by fndecl dependent to the used
4547 abi format. */
4548 int
4550 {
4552 /* For libcalls it is possible that there is no fndecl at hand.
4553 Therefore assume for this case the default abi of the target. */
4558 else
4563 }
4565 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4566 call abi used. */
4567 int
4569 {
4571 {
4575 else
4579 }
4581 }
4583 int
4585 {
4589 }
4591 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4592 call abi used. */
4593 int
4595 {
4599 }
4601 /* regclass.c */
4604 /* Implementation of call abi switching target hook. Specific to FNDECL
4605 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4606 for more details.
4607 To prevent redudant calls of costy function init_regs (), it checks not to
4608 reset register usage for default abi. */
4609 void
4611 {
4614 else
4617 {
4619 {
4623 }
4624 }
4626 {
4628 {
4632 }
4633 }
4634 }
4636 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4637 for a call to a function whose data type is FNTYPE.
4638 For a library call, FNTYPE is 0. */
4640 void
4644 tree fndecl)
4645 {
4650 /* Set up the number of registers to use for passing arguments. */
4653 {
4657 }
4659 {
4662 {
4666 }
4667 }
4674 /* Because type might mismatch in between caller and callee, we need to
4675 use actual type of function for local calls.
4676 FIXME: cgraph_analyze can be told to actually record if function uses
4677 va_start so for local functions maybe_vaarg can be made aggressive
4678 helping K&R code.
4679 FIXME: once typesytem is fixed, we won't need this code anymore. */
4687 {
4688 /* If there are variable arguments, then we won't pass anything
4689 in registers in 32-bit mode. */
4691 {
4699 }
4701 /* Use ecx and edx registers if function has fastcall attribute,
4702 else look for regparm information. */
4704 {
4706 {
4709 }
4710 else
4712 }
4714 /* Set up the number of SSE registers used for passing SFmode
4715 and DFmode arguments. Warn for mismatching ABI. */
4717 }
4718 }
4720 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4721 But in the case of vector types, it is some vector mode.
4723 When we have only some of our vector isa extensions enabled, then there
4724 are some modes for which vector_mode_supported_p is false. For these
4725 modes, the generic vector support in gcc will choose some non-vector mode
4726 in order to implement the type. By computing the natural mode, we'll
4727 select the proper ABI location for the operand and not depend on whatever
4728 the middle-end decides to do with these vector types. */
4730 static enum machine_mode
4732 {
4736 {
4739 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4741 {
4746 else
4749 /* Get the mode which has this inner mode and number of units. */
4756 }
4757 }
4760 }
4762 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4763 this may not agree with the mode that the type system has chosen for the
4764 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4765 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4767 static rtx
4770 {
4771 rtx tmp;
4775 else
4776 {
4780 }
4783 }
4785 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4786 of this code is to classify each 8bytes of incoming argument by the register
4787 class and assign registers accordingly. */
4789 /* Return the union class of CLASS1 and CLASS2.
4790 See the x86-64 PS ABI for details. */
4792 static enum x86_64_reg_class
4794 {
4795 /* Rule #1: If both classes are equal, this is the resulting class. */
4799 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4800 the other class. */
4806 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4810 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4818 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4819 MEMORY is used. */
4828 /* Rule #6: Otherwise class SSE is used. */
4830 }
4832 /* Classify the argument of type TYPE and mode MODE.
4833 CLASSES will be filled by the register class used to pass each word
4834 of the operand. The number of words is returned. In case the parameter
4835 should be passed in memory, 0 is returned. As a special case for zero
4836 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4838 BIT_OFFSET is used internally for handling records and specifies offset
4839 of the offset in bits modulo 256 to avoid overflow cases.
4841 See the x86-64 PS ABI for details.
4842 */
4844 static int
4847 {
4848 HOST_WIDE_INT bytes =
4852 /* Variable sized entities are always passed/returned in memory. */
4861 {
4863 tree field;
4866 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
4873 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4874 signalize memory class, so handle it as special case. */
4876 {
4879 }
4881 /* Classify each field of record and merge classes. */
4883 {
4885 /* And now merge the fields of structure. */
4887 {
4889 {
4895 /* Bitfields are always classified as integer. Handle them
4896 early, since later code would consider them to be
4897 misaligned integers. */
4899 {
4907 }
4908 else
4909 {
4917 {
4922 }
4923 }
4924 }
4925 }
4929 /* Arrays are handled as small records. */
4930 {
4937 /* The partial classes are now full classes. */
4948 }
4951 /* Unions are similar to RECORD_TYPE but offset is always 0.
4952 */
4954 {
4956 {
4964 bit_offset);
4969 }
4970 }
4975 }
4977 /* Final merger cleanup. */
4979 {
4980 /* If one class is MEMORY, everything should be passed in
4981 memory. */
4985 /* The X86_64_SSEUP_CLASS should be always preceded by
4986 X86_64_SSE_CLASS. */
4991 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4995 }
4997 }
4999 /* Compute alignment needed. We align all types to natural boundaries with
5000 exception of XFmode that is aligned to 64bits. */
5002 {
5011 /* Misaligned fields are always returned in memory. */
5014 }
5016 /* for V1xx modes, just use the base mode */
5021 /* Classification of atomic types. */
5023 {
5039 {
5043 {
5046 }
5048 {
5051 }
5053 {
5057 }
5059 {
5062 }
5063 else
5065 }
5077 else
5102 /* This modes is larger than 16 bytes. */
5141 else
5145 }
5146 }
5148 /* Examine the argument and return set number of register required in each
5149 class. Return 0 iff parameter should be passed in memory. */
5150 static int
5153 {
5163 {
5186 }
5188 }
5190 /* Construct container for the argument used by GCC interface. See
5191 FUNCTION_ARG for the detailed description. */
5193 static rtx
5197 {
5198 /* The following variables hold the static issued_error state. */
5212 rtx ret;
5223 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5224 some less clueful developer tries to use floating-point anyway. */
5226 {
5228 {
5230 {
5233 }
5234 }
5236 {
5239 }
5241 }
5243 /* Likewise, error if the ABI requires us to return values in the
5244 x87 registers and the user specified -mno-80387. */
5250 {
5252 {
5255 }
5257 }
5259 /* First construct simple cases. Avoid SCmode, since we want to use
5260 single register to pass this type. */
5263 {
5276 /* Zero sized array, struct or class. */
5280 }
5294 /* Otherwise figure out the entries of the PARALLEL. */
5296 {
5298 {
5303 /* Merge TImodes on aligned occasions here too. */
5308 else
5310 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5316 intreg++;
5323 sse_regno++;
5330 sse_regno++;
5335 else
5342 i++;
5343 sse_regno++;
5347 }
5348 }
5350 /* Empty aligned struct, union or class. */
5358 }
5360 /* Update the data in CUM to advance over an argument of mode MODE
5361 and data type TYPE. (TYPE is null for libcalls where that information
5362 may not be available.) */
5364 static void
5367 {
5369 {
5376 /* FALLTHRU */
5387 {
5390 }
5399 /* FALLTHRU */
5416 {
5421 {
5424 }
5425 }
5434 {
5439 {
5442 }
5443 }
5445 }
5446 }
5448 static void
5451 {
5454 /* Unnamed 256bit vector mode parameters are passed on stack. */
5461 {
5466 }
5467 else
5469 }
5471 static void
5473 HOST_WIDE_INT words)
5474 {
5475 /* Otherwise, this should be passed indirect. */
5480 {
5483 }
5484 }
5486 void
5489 {
5494 else
5505 else
5507 }
5509 /* Define where to put the arguments to a function.
5510 Value is zero to push the argument on the stack,
5511 or a hard register in which to store the argument.
5513 MODE is the argument's machine mode.
5514 TYPE is the data type of the argument (as a tree).
5515 This is null for libcalls where that information may
5516 not be available.
5517 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5518 the preceding args and about the function being called.
5519 NAMED is nonzero if this argument is a named parameter
5520 (otherwise it is an extra parameter matching an ellipsis). */
5522 static rtx
5526 {
5529 /* Avoid the AL settings for the Unix64 ABI. */
5534 {
5541 /* FALLTHRU */
5547 {
5550 /* Fastcall allocates the first two DWORD (SImode) or
5551 smaller arguments to ECX and EDX if it isn't an
5552 aggregate type . */
5554 {
5560 /* ECX not EAX is the first allocated register. */
5563 }
5565 }
5574 /* FALLTHRU */
5576 /* In 32bit, we pass TImode in xmm registers. */
5584 {
5586 {
5590 }
5594 }
5598 /* In 32bit, we pass OImode in ymm registers. */
5606 {
5608 {
5612 }
5616 }
5625 {
5627 {
5631 }
5635 }
5637 }
5640 }
5642 static rtx
5645 {
5648 /* Handle a hidden AL argument containing number of registers
5649 for varargs x86-64 functions. */
5654 ? SSE_REGPARM_MAX
5661 {
5671 /* In 64bit, we pass TImode in interger registers and OImode on
5672 stack. */
5674 {
5676 {
5680 }
5681 }
5683 /* Unnamed 256bit vector mode parameters are passed on stack. */
5687 }
5693 }
5695 static rtx
5698 HOST_WIDE_INT bytes)
5699 {
5702 /* Avoid the AL settings for the Unix64 ABI. */
5706 /* If we've run out of registers, it goes on the stack. */
5712 /* Only floating point modes are passed in anything but integer regs. */
5714 {
5717 else
5718 {
5721 /* Unnamed floating parameters are passed in both the
5722 SSE and integer registers. */
5728 }
5729 }
5730 /* Handle aggregated types passed in register. */
5732 {
5737 }
5740 }
5742 rtx
5745 {
5751 else
5755 /* To simplify the code below, represent vector types with a vector mode
5756 even if MMX/SSE are not active. */
5764 else
5766 }
5768 /* A C expression that indicates when an argument must be passed by
5769 reference. If nonzero for an argument, a copy of that argument is
5770 made in memory and a pointer to the argument is passed instead of
5771 the argument itself. The pointer is passed in whatever way is
5772 appropriate for passing a pointer to that type. */
5774 static bool
5778 {
5779 /* See Windows x64 Software Convention. */
5781 {
5784 {
5785 /* Arrays are passed by reference. */
5790 {
5791 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5792 are passed by reference. */
5794 }
5795 }
5797 /* __m128 is passed by reference. */
5803 }
5804 }
5809 }
5811 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5812 ABI. */
5813 static bool
5815 {
5827 {
5828 /* Walk the aggregates recursively. */
5830 {
5834 {
5835 tree field;
5837 /* Walk all the structure fields. */
5839 {
5843 }
5845 }
5848 /* Just for use if some languages passes arrays by value. */
5855 }
5856 }
5858 }
5860 /* Gives the alignment boundary, in bits, of an argument with the
5861 specified mode and type. */
5863 int
5865 {
5868 {
5869 /* Since canonical type is used for call, we convert it to
5870 canonical type if needed. */
5874 }
5875 else
5879 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5880 natural boundaries. */
5882 {
5883 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5884 make an exception for SSE modes since these require 128bit
5885 alignment.
5887 The handling here differs from field_alignment. ICC aligns MMX
5888 arguments to 4 byte boundaries, while structure fields are aligned
5889 to 8 byte boundaries. */
5891 {
5894 }
5895 else
5896 {
5899 }
5900 }
5904 }
5906 /* Return true if N is a possible register number of function value. */
5908 bool
5910 {
5912 {
5917 /* TODO: The function should depend on current function ABI but
5918 builtins.c would need updating then. Therefore we use the
5919 default ABI. */
5931 }
5934 }
5936 /* Define how to find the value returned by a function.
5937 VALTYPE is the data type of the value (as a tree).
5938 If the precise function being called is known, FUNC is its FUNCTION_DECL;
5939 otherwise, FUNC is 0. */
5941 static rtx
5944 {
5947 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
5948 we normally prevent this case when mmx is not available. However
5949 some ABIs may require the result to be returned like DImode. */
5953 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
5954 we prevent this case when sse is not available. However some ABIs
5955 may require the result to be returned like integer TImode. */
5960 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
5963 else
5964 /* Most things go in %eax. */
5967 /* Override FP return register with %xmm0 for local functions when
5968 SSE math is enabled or for functions with sseregparm attribute. */
5970 {
5975 }
5978 }
5980 static rtx
5982 const_tree valtype)
5983 {
5984 rtx ret;
5986 /* Handle libcalls, which don't provide a type node. */
5988 {
5990 {
6007 }
6008 }
6014 /* For zero sized structures, construct_container returns NULL, but we
6015 need to keep rest of compiler happy by returning meaningful value. */
6020 }
6022 static rtx
6024 {
6028 {
6030 {
6043 }
6044 }
6046 }
6048 static rtx
6051 {
6063 else
6065 }
6067 static rtx
6070 {
6076 }
6078 rtx
6080 {
6082 }
6084 /* Return true iff type is returned in memory. */
6086 static int ATTRIBUTE_UNUSED
6088 {
6089 HOST_WIDE_INT size;
6100 {
6101 /* User-created vectors small enough to fit in EAX. */
6105 /* MMX/3dNow values are returned in MM0,
6106 except when it doesn't exits. */
6110 /* SSE values are returned in XMM0, except when it doesn't exist. */
6113 }
6121 }
6123 static int ATTRIBUTE_UNUSED
6125 {
6128 }
6130 static int ATTRIBUTE_UNUSED
6132 {
6135 /* __m128 is returned in xmm0. */
6140 /* Otherwise, the size must be exactly in [1248]. */
6142 }
6144 static bool
6146 {
6147 #ifdef SUBTARGET_RETURN_IN_MEMORY
6149 #else
6156 else
6158 #endif
6159 }
6161 /* Return false iff TYPE is returned in memory. This version is used
6162 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6163 but differs notably in that when MMX is available, 8-byte vectors
6164 are returned in memory, rather than in MMX registers. */
6166 bool
6168 {
6181 {
6182 /* Return in memory only if MMX registers *are* available. This
6183 seems backwards, but it is consistent with the existing
6184 Solaris x86 ABI. */
6189 }
6196 }
6198 /* When returning SSE vector types, we have a choice of either
6199 (1) being abi incompatible with a -march switch, or
6200 (2) generating an error.
6201 Given no good solution, I think the safest thing is one warning.
6202 The user won't be able to use -Werror, but....
6204 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6205 called in response to actually generating a caller or callee that
6206 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6207 via aggregate_value_p for general type probing from tree-ssa. */
6209 static rtx
6211 {
6215 {
6216 /* Look at the return type of the function, not the function type. */
6220 {
6223 {
6227 }
6228 }
6231 {
6233 {
6237 }
6238 }
6239 }
6242 }
6244 \f
6245 /* Create the va_list data type. */
6247 /* Returns the calling convention specific va_list date type.
6248 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6250 static tree
6252 {
6255 /* For i386 we use plain pointer to argument area. */
6263 unsigned_type_node);
6265 unsigned_type_node);
6267 ptr_type_node);
6269 ptr_type_node);
6288 /* The correct type is an array type of one element. */
6290 }
6292 /* Setup the builtin va_list data type and for 64-bit the additional
6293 calling convention specific va_list data types. */
6295 static tree
6297 {
6300 /* Initialize abi specific va_list builtin types. */
6302 {
6303 tree t;
6305 {
6310 }
6311 else
6312 {
6317 }
6319 {
6324 }
6325 else
6326 {
6331 }
6332 }
6335 }
6337 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6339 static void
6341 {
6343 rtx label;
6344 rtx label_ref;
6345 rtx tmp_reg;
6346 rtx nsse_reg;
6347 alias_set_type set;
6354 /* GPR size of varargs save area. */
6357 else
6360 /* FPR size of varargs save area. We don't need it if we don't pass
6361 anything in SSE registers. */
6364 else
6374 i < regparm
6376 i++)
6377 {
6384 }
6387 {
6388 /* Now emit code to save SSE registers. The AX parameter contains number
6389 of SSE parameter registers used to call this function. We use
6390 sse_prologue_save insn template that produces computed jump across
6391 SSE saves. We need some preparation work to get this working. */
6396 /* Compute address to jump to :
6397 label - eax*4 + nnamed_sse_arguments*4 Or
6398 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6406 /* vmovaps is one byte longer than movaps. */
6410 nsse_reg)));
6413 emit_move_insn
6417 label_ref,
6420 else
6424 /* Compute address of memory block we save into. We always use pointer
6425 pointing 127 bytes after first byte to store - this is needed to keep
6426 instruction size limited by 4 bytes (5 bytes for AVX) with one
6427 byte displacement. */
6437 /* And finally do the dirty job! */
6440 }
6441 }
6443 static void
6445 {
6450 {
6461 }
6462 }
6464 static void
6468 {
6469 CUMULATIVE_ARGS next_cum;
6470 tree fntype;
6472 /* This argument doesn't appear to be used anymore. Which is good,
6473 because the old code here didn't suppress rtl generation. */
6481 /* For varargs, we do not want to skip the dummy va_dcl argument.
6482 For stdargs, we do want to skip the last named argument. */
6489 else
6491 }
6493 /* Checks if TYPE is of kind va_list char *. */
6495 static bool
6497 {
6498 tree canonic;
6500 /* For 32-bit it is always true. */
6506 }
6508 /* Implement va_start. */
6510 static void
6512 {
6516 tree type;
6518 /* Only 64bit target needs something special. */
6520 {
6523 }
6536 /* Count number of gp and fp argument registers used. */
6542 {
6548 }
6551 {
6557 }
6559 /* Find the overflow area. */
6570 {
6571 /* Find the register save area.
6572 Prologue of the function save it right above stack frame. */
6581 }
6582 }
6584 /* Implement va_arg. */
6586 static tree
6589 {
6596 rtx container;
6598 tree ptrtype;
6602 /* Only 64bit target needs something special. */
6626 {
6633 /* Unnamed 256bit vector mode parameters are passed on stack. */
6635 {
6638 }
6646 }
6648 /* Pull the value out of the saved registers. */
6654 {
6668 /* In case we are passing structure, verify that it is consecutive block
6669 on the register save area. If not we need to do moves. */
6671 {
6672 /* Verify that all registers are strictly consecutive */
6674 {
6678 {
6683 }
6684 }
6685 else
6686 {
6690 {
6695 }
6696 }
6697 }
6699 {
6702 }
6703 else
6704 {
6709 }
6711 /* First ensure that we fit completely in registers. */
6713 {
6720 }
6722 {
6730 }
6732 /* Compute index to start of area used for integer regs. */
6734 {
6735 /* int_addr = gpr + sav; */
6739 }
6741 {
6742 /* sse_addr = fpr + sav; */
6746 }
6748 {
6752 /* addr = &temp; */
6757 {
6770 {
6773 }
6774 else
6775 {
6778 }
6790 }
6791 }
6794 {
6798 }
6801 {
6805 }
6810 }
6812 /* ... otherwise out of the overflow area. */
6814 /* When we align parameter on stack for caller, if the parameter
6815 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6816 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6817 here with caller. */
6822 /* Care for on-stack alignment if needed. */
6826 else
6827 {
6835 }
6852 }
6853 \f
6854 /* Return nonzero if OPNUM's MEM should be matched
6855 in movabs* patterns. */
6857 int
6859 {
6871 }
6872 \f
6873 /* Initialize the table of extra 80387 mathematical constants. */
6875 static void
6877 {
6879 {
6885 };
6889 {
6891 /* Ensure each constant is rounded to XFmode precision. */
6894 }
6897 }
6899 /* Return true if the constant is something that can be loaded with
6900 a special instruction. */
6902 int
6904 {
6907 REAL_VALUE_TYPE r;
6919 /* For XFmode constants, try to find a special 80387 instruction when
6920 optimizing for size or on those CPUs that benefit from them. */
6923 {
6932 }
6934 /* Load of the constant -0.0 or -1.0 will be split as
6935 fldz;fchs or fld1;fchs sequence. */
6942 }
6944 /* Return the opcode of the special instruction to be used to load
6945 the constant X. */
6949 {
6951 {
6971 }
6972 }
6974 /* Return the CONST_DOUBLE representing the 80387 constant that is
6975 loaded by the specified special instruction. The argument IDX
6976 matches the return value from standard_80387_constant_p. */
6978 rtx
6980 {
6987 {
6998 }
7001 XFmode);
7002 }
7004 /* Return 1 if mode is a valid mode for sse. */
7005 static int
7007 {
7009 {
7020 }
7021 }
7023 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7024 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7025 modes and AVX is enabled. */
7027 int
7029 {
7035 {
7040 }
7043 }
7045 /* Return the opcode of the special instruction to be used to load
7046 the constant X. */
7050 {
7052 {
7055 {
7070 }
7074 {
7082 }
7083 else
7085 }
7087 }
7089 /* Returns 1 if OP contains a symbol reference */
7091 int
7093 {
7102 {
7104 {
7110 }
7114 }
7117 }
7119 /* Return 1 if it is appropriate to emit `ret' instructions in the
7120 body of a function. Do this only if the epilogue is simple, needing a
7121 couple of insns. Prior to reloading, we can't tell how many registers
7122 must be saved, so return 0 then. Return 0 if there is no frame
7123 marker to de-allocate. */
7125 int
7127 {
7133 /* Don't allow more than 32 pop, since that's all we can do
7134 with one instruction. */
7141 }
7142 \f
7143 /* Value should be nonzero if functions must have frame pointers.
7144 Zero means the frame pointer need not be set up (and parms may
7145 be accessed via the stack pointer) in functions that seem suitable. */
7147 int
7149 {
7150 /* If we accessed previous frames, then the generated code expects
7151 to be able to access the saved ebp value in our frame. */
7155 /* Several x86 os'es need a frame pointer for other reasons,
7156 usually pertaining to setjmp. */
7160 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7161 the frame pointer by default. Turn it back on now if we've not
7162 got a leaf function. */
7164 && (!current_function_is_leaf
7172 }
7174 /* Record that the current function accesses previous call frames. */
7176 void
7178 {
7180 }
7181 \f
7182 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7183 # define USE_HIDDEN_LINKONCE 1
7184 #else
7185 # define USE_HIDDEN_LINKONCE 0
7186 #endif
7190 /* Fills in the label name that should be used for a pc thunk for
7191 the given register. */
7193 static void
7195 {
7200 else
7202 }
7205 /* This function generates code for -fpic that loads %ebx with
7206 the return address of the caller and then returns. */
7208 void
7210 {
7215 {
7223 #if TARGET_MACHO
7225 {
7233 }
7234 else
7235 #endif
7237 {
7238 tree decl;
7241 error_mark_node);
7254 }
7255 else
7256 {
7259 }
7265 }
7269 }
7271 /* Emit code for the SET_GOT patterns. */
7275 {
7281 {
7282 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7287 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7288 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7289 an unadorned address. */
7294 }
7299 {
7304 else
7307 #if TARGET_MACHO
7308 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7309 is what will be referenced by the Mach-O PIC subsystem. */
7312 #endif
7319 }
7320 else
7321 {
7329 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7330 is what will be referenced by the Mach-O PIC subsystem. */
7331 #if TARGET_MACHO
7334 else
7337 #endif
7338 }
7345 else
7349 }
7351 /* Generate an "push" pattern for input ARG. */
7353 static rtx
7355 {
7359 stack_pointer_rtx)),
7360 arg);
7361 }
7363 /* Return >= 0 if there is an unused call-clobbered register available
7364 for the entire function. */
7366 static unsigned int
7368 {
7371 {
7373 /* Can't use the same register for both PIC and DRAP. */
7376 else
7381 }
7384 }
7386 /* Return 1 if we need to save REGNO. */
7387 static int
7389 {
7396 {
7400 }
7403 {
7406 {
7412 }
7413 }
7423 }
7425 /* Return number of registers to be saved on the stack. */
7427 static int
7429 {
7435 nregs++;
7437 }
7439 /* Given FROM and TO register numbers, say whether this elimination is
7440 allowed. If stack alignment is needed, we can only replace argument
7441 pointer with hard frame pointer, or replace frame pointer with stack
7442 pointer. Otherwise, frame pointer elimination is automatically
7443 handled and all other eliminations are valid. */
7445 int
7447 {
7453 else
7455 }
7457 /* Return the offset between two registers, one to be eliminated, and the other
7458 its replacement, at the start of a routine. */
7460 HOST_WIDE_INT
7462 {
7471 else
7472 {
7480 }
7481 }
7483 /* Fill structure ix86_frame about frame of currently computed function. */
7485 static void
7487 {
7488 HOST_WIDE_INT total_size;
7490 HOST_WIDE_INT offset;
7504 /* During reload iteration the amount of registers saved can change.
7505 Recompute the value as needed. Do not recompute when amount of registers
7506 didn't change as reload does multiple calls to the function and does not
7507 expect the decision to change within single iteration. */
7510 {
7514 /* The fast prologue uses move instead of push to save registers. This
7515 is significantly longer, but also executes faster as modern hardware
7516 can execute the moves in parallel, but can't do that for push/pop.
7518 Be careful about choosing what prologue to emit: When function takes
7519 many instructions to execute we may use slow version as well as in
7520 case function is known to be outside hot spot (this is known with
7521 feedback only). Weight the size of function by number of registers
7522 to save as it is cheap to use one or two push instructions but very
7523 slow to use many of them. */
7527 || (flag_branch_probabilities
7530 else
7533 }
7537 else
7541 /* Skip return address and saved base pointer. */
7546 /* Set offset to aligned because the realigned frame starts from
7547 here. */
7551 /* Register save area */
7554 /* Va-arg area */
7558 /* Align start of frame for local function. */
7564 /* Frame pointer points here. */
7569 /* Add outgoing arguments area. Can be skipped if we eliminated
7570 all the function calls as dead code.
7571 Skipping is however impossible when function calls alloca. Alloca
7572 expander assumes that last crtl->outgoing_args_size
7573 of stack frame are unused. */
7577 {
7580 }
7581 else
7584 /* Align stack boundary. Only needed if we're calling another function
7585 or using alloca. */
7590 else
7595 /* We've reached end of stack frame. */
7598 /* Size prologue needs to allocate. */
7608 && current_function_is_leaf
7610 {
7616 }
7617 else
7621 #if 0
7637 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7638 #endif
7639 }
7641 /* Emit code to save registers in the prologue. */
7643 static void
7645 {
7647 rtx insn;
7651 {
7654 }
7655 }
7657 /* Emit code to save registers using MOV insns. First register
7658 is restored from POINTER + OFFSET. */
7659 static void
7661 {
7663 rtx insn;
7667 {
7673 }
7674 }
7676 /* Expand prologue or epilogue stack adjustment.
7677 The pattern exist to put a dependency on all ebp-based memory accesses.
7678 STYLE should be negative if instructions should be marked as frame related,
7679 zero if %r11 register is live and cannot be freely used and positive
7680 otherwise. */
7682 static void
7684 {
7685 rtx insn;
7691 else
7692 {
7693 rtx r11;
7694 /* r11 is used by indirect sibcall return as well, set before the
7695 epilogue and used after the epilogue. ATM indirect sibcall
7696 shouldn't be used together with huge frame sizes in one
7697 function because of the frame_size check in sibcall.c. */
7704 offset));
7705 }
7708 }
7710 /* Find an available register to be used as dynamic realign argument
7711 pointer regsiter. Such a register will be written in prologue and
7712 used in begin of body, so it must not be
7713 1. parameter passing register.
7714 2. GOT pointer.
7715 We reuse static-chain register if it is available. Otherwise, we
7716 use DI for i386 and R13 for x86-64. We chose R13 since it has
7717 shorter encoding.
7719 Return: the regno of chosen register. */
7721 static unsigned int
7723 {
7727 {
7728 /* Use R13 for nested function or function need static chain.
7729 Since function with tail call may use any caller-saved
7730 registers in epilogue, DRAP must not use caller-saved
7731 register in such case. */
7738 }
7739 else
7740 {
7741 /* Use DI for nested function or function need static chain.
7742 Since function with tail call may use any caller-saved
7743 registers in epilogue, DRAP must not use caller-saved
7744 register in such case. */
7750 /* Reuse static chain register if it isn't used for parameter
7751 passing. */
7756 else
7758 }
7759 }
7761 /* Update incoming stack boundary and estimated stack alignment. */
7763 static void
7765 {
7766 /* Prefer the one specified at command line. */
7767 ix86_incoming_stack_boundary
7768 = (ix86_user_incoming_stack_boundary
7769 ? ix86_user_incoming_stack_boundary
7772 /* Incoming stack alignment can be changed on individual functions
7773 via force_align_arg_pointer attribute. We use the smallest
7774 incoming stack boundary. */
7780 /* The incoming stack frame has to be aligned at least at
7781 parm_stack_boundary. */
7785 /* Stack at entrance of main is aligned by runtime. We use the
7786 smallest incoming stack boundary. */
7793 /* x86_64 vararg needs 16byte stack alignment for register save
7794 area. */
7799 }
7801 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7802 needed or an rtx for DRAP otherwise. */
7804 static rtx
7806 {
7811 {
7812 /* Assign DRAP to vDRAP and returns vDRAP */
7814 rtx drap_vreg;
7815 rtx arg_ptr;
7829 }
7830 else
7832 }
7834 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7836 static rtx
7838 {
7840 }
7842 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7843 This is called from dwarf2out.c to emit call frame instructions
7844 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7845 static void
7847 {
7852 {
7863 }
7864 }
7866 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
7867 to be generated in correct form. */
7868 static void
7870 {
7871 /* Check if stack realign is really needed after reload, and
7872 stores result in cfun */
7873 unsigned int incoming_stack_boundary
7877 < (current_function_is_leaf
7882 {
7883 /* After stack_realign_needed is finalized, we can't no longer
7884 change it. */
7886 }
7887 else
7888 {
7891 }
7892 }
7894 /* Expand the prologue into a bunch of separate insns. */
7896 void
7898 {
7899 rtx insn;
7902 HOST_WIDE_INT allocate;
7906 /* DRAP should not coexist with stack_realign_fp */
7911 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
7912 of DRAP is needed and stack realignment is really needed after reload */
7914 {
7922 /* Grab the argument pointer. */
7927 /* Only need to push parameter pointer reg if it is caller
7928 saved reg */
7930 {
7931 /* Push arg pointer reg */
7934 }
7939 /* Align the stack. */
7941 stack_pointer_rtx,
7945 /* Replicate the return address on the stack so that return
7946 address can be reached via (argp - 1) slot. This is needed
7947 to implement macro RETURN_ADDR_RTX and intrinsic function
7948 expand_builtin_return_addr etc. */
7954 }
7956 /* Note: AT&T enter does NOT have reversed args. Enter is probably
7957 slower on all targets. Also sdb doesn't like it. */
7960 {
7966 }
7969 {
7973 /* Align the stack. */
7975 stack_pointer_rtx,
7978 }
7984 else
7987 /* When using red zone we may start register saving before allocating
7988 the stack frame saving one cycle of the prologue. However I will
7989 avoid doing this if I am going to have to probe the stack since
7990 at least on x86_64 the stack probe can turn into a call that clobbers
7991 a red zone location */
7996 ? hard_frame_pointer_rtx
8001 ;
8005 else
8006 {
8007 /* Only valid for Win32. */
8010 rtx t;
8016 else
8020 {
8023 }
8029 else
8039 {
8042 allocate
8045 else
8048 }
8049 }
8054 {
8060 else
8063 }
8069 {
8076 }
8079 {
8081 {
8083 {
8093 }
8094 else
8096 }
8097 else
8099 }
8101 /* Prevent function calls from being scheduled before the call to mcount.
8102 In the pic_reg_used case, make sure that the got load isn't deleted. */
8104 {
8108 }
8111 {
8112 /* vDRAP is setup but after reload it turns out stack realign
8113 isn't necessary, here we will emit prologue to setup DRAP
8114 without stack realign adjustment */
8118 }
8120 /* Emit cld instruction if stringops are used in the function. */
8123 }
8125 /* Emit code to restore saved registers using MOV insns. First register
8126 is restored from POINTER + OFFSET. */
8127 static void
8130 {
8136 {
8137 /* Ensure that adjust_address won't be forced to produce pointer
8138 out of range allowed by x86-64 instruction set. */
8140 {
8141 rtx r11;
8148 }
8152 }
8153 }
8155 /* Restore function stack, frame, and registers. */
8157 void
8159 {
8163 HOST_WIDE_INT offset;
8167 /* When stack is realigned, SP must be valid. */
8168 sp_valid = (!frame_pointer_needed
8169 || current_function_sp_is_unchanging
8174 /* Calculate start of saved registers relative to ebp. Special care
8175 must be taken for the normal return case of a function using
8176 eh_return: the eax and edx registers are marked as saved, but not
8177 restored along this path. */
8183 /* If we're only restoring one register and sp is not valid then
8184 using a move instruction to restore the register since it's
8185 less work than reloading sp and popping the register.
8187 The default code result in stack adjustment using add/lea instruction,
8188 while this code results in LEAVE instruction (or discrete equivalent),
8189 so it is profitable in some other cases as well. Especially when there
8190 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8191 and there is exactly one register to pop. This heuristic may need some
8192 tuning in future. */
8194 || (TARGET_EPILOGUE_USING_MOVE
8202 {
8203 /* Restore registers. We can use ebp or esp to address the memory
8204 locations. If both are available, default to ebp, since offsets
8205 are known to be small. Only exception is esp pointing directly
8206 to the end of block of saved registers, where we may simplify
8207 addressing mode.
8209 If we are realigning stack with bp and sp, regs restore can't
8210 be addressed by bp. sp must be used instead. */
8217 else
8221 /* eh_return epilogues need %ecx added to the stack pointer. */
8223 {
8226 /* Stack align doesn't work with eh_return. */
8230 {
8240 }
8241 else
8242 {
8247 }
8248 }
8253 style);
8254 /* If not an i386, mov & pop is faster than "leave". */
8258 else
8259 {
8261 hard_frame_pointer_rtx,
8265 }
8266 }
8267 else
8268 {
8269 /* First step is to deallocate the stack frame so that we can
8270 pop the registers.
8272 If we realign stack with frame pointer, then stack pointer
8273 won't be able to recover via lea $offset(%bp), %sp, because
8274 there is a padding area between bp and sp for realign.
8275 "add $to_allocate, %sp" must be used instead. */
8277 {
8281 hard_frame_pointer_rtx,
8283 }
8292 {
8293 /* Leave results in shorter dependency chains on CPUs that are
8294 able to grok it fast. */
8297 else
8298 {
8299 /* For stack realigned really happens, recover stack
8300 pointer to hard frame pointer is a must, if not using
8301 leave. */
8304 hard_frame_pointer_rtx,
8307 }
8308 }
8309 }
8312 {
8323 }
8325 /* Sibcall epilogues don't want a return instruction. */
8330 {
8333 /* i386 can only pop 64K bytes. If asked to pop more, pop
8334 return address, do explicit add, and jump indirectly to the
8335 caller. */
8338 {
8341 /* There is no "pascal" calling convention in any 64bit ABI. */
8347 }
8348 else
8350 }
8351 else
8353 }
8355 /* Reset from the function's potential modifications. */
8357 static void
8359 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8360 {
8363 #if TARGET_MACHO
8364 /* Mach-O doesn't support labels at the end of objects, so if
8365 it looks like we might want one, insert a NOP. */
8366 {
8377 }
8378 #endif
8380 }
8381 \f
8382 /* Extract the parts of an RTL expression that is a valid memory address
8383 for an instruction. Return 0 if the structure of the address is
8384 grossly off. Return -1 if the address contains ASHIFT, so it is not
8385 strictly valid, but still used for computing length of lea instruction. */
8387 int
8389 {
8400 {
8405 do
8406 {
8411 }
8418 {
8421 {
8431 && TARGET_TLS_DIRECT_SEG_REFS
8434 else
8444 else
8459 }
8460 }
8461 }
8463 {
8466 }
8468 {
8469 rtx tmp;
8471 /* We're called for lea too, which implements ashift on occasion. */
8481 }
8482 else
8485 /* Extract the integral value of scale. */
8487 {
8491 }
8496 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8501 {
8502 rtx tmp;
8505 }
8507 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8513 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8514 Avoid this by transforming to [%esi+0].
8515 Reload calls address legitimization without cfun defined, so we need
8516 to test cfun for being non-NULL. */
8523 /* Special case: encode reg+reg instead of reg*2. */
8527 /* Special case: scaling cannot be encoded without base or displacement. */
8538 }
8539 \f
8540 /* Return cost of the memory address x.
8541 For i386, it is better to use a complex address than let gcc copy
8542 the address into a reg and make a new pseudo. But not if the address
8543 requires to two regs - that would mean more pseudos with longer
8544 lifetimes. */
8545 static int
8547 {
8559 /* Attempt to minimize number of registers in the address. */
8565 cost++;
8572 cost++;
8574 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8575 since it's predecode logic can't detect the length of instructions
8576 and it degenerates to vector decoded. Increase cost of such
8577 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8578 to split such addresses or even refuse such addresses at all.
8580 Following addressing modes are affected:
8581 [base+scale*index]
8582 [scale*index+disp]
8583 [base+index]
8585 The first and last case may be avoidable by explicitly coding the zero in
8586 memory address, but I don't have AMD-K6 machine handy to check this
8587 theory. */
8596 }
8597 \f
8598 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8599 this is used for to form addresses to local data when -fPIC is in
8600 use. */
8602 static bool
8604 {
8607 }
8609 /* Determine if a given RTX is a valid constant. We already know this
8610 satisfies CONSTANT_P. */
8612 bool
8614 {
8616 {
8621 {
8625 }
8630 /* Only some unspecs are valid as "constants". */
8633 {
8649 }
8651 /* We must have drilled down to a symbol. */
8656 /* FALLTHRU */
8659 /* TLS symbols are never valid. */
8663 /* DLLIMPORT symbols are never valid. */
8683 }
8685 /* Otherwise we handle everything else in the move patterns. */
8687 }
8689 /* Determine if it's legal to put X into the constant pool. This
8690 is not possible for the address of thread-local symbols, which
8691 is checked above. */
8693 static bool
8695 {
8696 /* We can always put integral constants and vectors in memory. */
8698 {
8706 }
8708 }
8710 /* Determine if a given RTX is a valid constant address. */
8712 bool
8714 {
8716 }
8718 /* Nonzero if the constant value X is a legitimate general operand
8719 when generating PIC code. It is given that flag_pic is on and
8720 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8722 bool
8724 {
8725 rtx inner;
8728 {
8735 /* Only some unspecs are valid as "constants". */
8738 {
8751 }
8752 /* FALLTHRU */
8760 }
8761 }
8763 /* Determine if a given CONST RTX is a valid memory displacement
8764 in PIC mode. */
8766 int
8768 {
8771 /* In 64bit mode we can allow direct addresses of symbols and labels
8772 when they are not dynamic symbols. */
8774 {
8778 {
8795 /* FALLTHRU */
8798 /* TLS references should always be enclosed in UNSPEC. */
8808 }
8809 }
8815 {
8816 /* We are unsafe to allow PLUS expressions. This limit allowed distance
8817 of GOT tables. We should not need these anyway. */
8828 }
8832 {
8837 }
8846 {
8850 /* We need to check for both symbols and labels because VxWorks loads
8851 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
8852 details. */
8856 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
8857 While ABI specify also 32bit relocation but we don't produce it in
8858 small PIC model at all. */
8880 }
8883 }
8885 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
8886 memory address for an instruction. The MODE argument is the machine mode
8887 for the MEM expression that wants to use this address.
8889 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
8890 convert common non-canonical forms to canonical form so that they will
8891 be recognized. */
8893 int
8896 {
8899 HOST_WIDE_INT scale;
8904 {
8907 }
8914 /* Validate base register.
8916 Don't allow SUBREG's that span more than a word here. It can lead to spill
8917 failures when the base is one word out of a two word structure, which is
8918 represented internally as a DImode int. */
8921 {
8922 rtx reg;
8932 else
8933 {
8936 }
8939 {
8942 }
8946 {
8949 }
8950 }
8952 /* Validate index register.
8954 Don't allow SUBREG's that span more than a word here -- same as above. */
8957 {
8958 rtx reg;
8968 else
8969 {
8972 }
8975 {
8978 }
8982 {
8985 }
8986 }
8988 /* Validate scale factor. */
8990 {
8993 {
8996 }
8999 {
9002 }
9003 }
9005 /* Validate displacement. */
9007 {
9014 {
9015 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9016 used. While ABI specify also 32bit relocations, we don't produce
9017 them at all and use IP relative instead. */
9040 }
9043 && (flag_pic
9044 || (TARGET_MACHO
9045 #if TARGET_MACHO
9046 && MACHOPIC_INDIRECT
9048 #endif
9049 )))
9050 {
9052 is_legitimate_pic:
9054 {
9055 /* foo@dtpoff(%rX) is ok. */
9062 {
9065 }
9066 }
9068 {
9071 }
9073 /* This code used to verify that a symbolic pic displacement
9074 includes the pic_offset_table_rtx register.
9076 While this is good idea, unfortunately these constructs may
9077 be created by "adds using lea" optimization for incorrect
9078 code like:
9080 int a;
9081 int foo(int i)
9082 {
9083 return *(&a+i);
9084 }
9086 This code is nonsensical, but results in addressing
9087 GOT table with pic_offset_table_rtx base. We can't
9088 just refuse it easily, since it gets matched by
9089 "addsi3" pattern, that later gets split to lea in the
9090 case output register differs from input. While this
9091 can be handled by separate addsi pattern for this case
9092 that never results in lea, this seems to be easier and
9093 correct fix for crash to disable this test. */
9094 }
9101 {
9104 }
9107 {
9110 }
9111 }
9113 /* Everything looks valid. */
9116 report_error:
9118 }
9119 \f
9120 /* Return a unique alias set for the GOT. */
9122 static alias_set_type
9124 {
9129 }
9131 /* Return a legitimate reference for ORIG (an address) using the
9132 register REG. If REG is 0, a new pseudo is generated.
9134 There are two types of references that must be handled:
9136 1. Global data references must load the address from the GOT, via
9137 the PIC reg. An insn is emitted to do this load, and the reg is
9138 returned.
9140 2. Static data references, constant pool addresses, and code labels
9141 compute the address as an offset from the GOT, whose base is in
9142 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9143 differentiate them from global data objects. The returned
9144 address is the PIC reg + an unspec constant.
9146 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9147 reg also appears in the address. */
9149 static rtx
9151 {
9154 rtx base;
9156 #if TARGET_MACHO
9158 {
9161 /* Use the generic Mach-O PIC machinery. */
9163 }
9164 #endif
9171 {
9172 rtx tmpreg;
9173 /* This symbol may be referenced via a displacement from the PIC
9174 base address (@GOTOFF). */
9181 {
9183 UNSPEC_GOTOFF);
9185 }
9186 else
9191 else
9196 {
9200 }
9202 }
9204 {
9205 /* This symbol may be referenced via a displacement from the PIC
9206 base address (@GOTOFF). */
9213 {
9215 UNSPEC_GOTOFF);
9217 }
9218 else
9224 {
9227 }
9228 }
9230 /* We can't use @GOTOFF for text labels on VxWorks;
9231 see gotoff_operand. */
9233 {
9235 {
9241 {
9244 }
9245 }
9248 {
9256 /* Use directly gen_movsi, otherwise the address is loaded
9257 into register for CSE. We don't want to CSE this addresses,
9258 instead we CSE addresses from the GOT table, so skip this. */
9261 }
9262 else
9263 {
9264 /* This symbol must be referenced via a load from the
9265 Global Offset Table (@GOT). */
9281 }
9282 }
9283 else
9284 {
9287 {
9289 {
9292 }
9293 else
9295 }
9297 {
9300 /* We must match stuff we generate before. Assume the only
9301 unspecs that can get here are ours. Not that we could do
9302 anything with them anyway.... */
9308 }
9310 {
9313 /* Check first to see if this is a constant offset from a @GOTOFF
9314 symbol reference. */
9317 {
9319 {
9323 UNSPEC_GOTOFF);
9329 {
9332 }
9333 }
9334 else
9335 {
9338 {
9342 }
9343 }
9344 }
9345 else
9346 {
9353 else
9354 {
9356 {
9359 }
9361 }
9362 }
9363 }
9364 }
9366 }
9367 \f
9368 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9370 static rtx
9372 {
9384 }
9386 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9387 false if we expect this to be used for a memory address and true if
9388 we expect to load the address into a register. */
9390 static rtx
9392 {
9397 {
9403 {
9413 }
9416 else
9420 {
9424 }
9432 {
9444 }
9447 else
9451 {
9456 }
9464 {
9468 }
9474 {
9477 }
9479 {
9484 }
9486 {
9490 }
9491 else
9492 {
9495 }
9505 {
9509 }
9510 else
9511 {
9515 }
9525 {
9528 }
9529 else
9530 {
9534 }
9539 }
9542 }
9544 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9545 to symbol DECL. */
9548 htab_t dllimport_map;
9550 static tree
9552 {
9559 tree to;
9560 rtx rtl;
9603 }
9605 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9606 true if we require the result be a register. */
9608 static rtx
9610 {
9611 tree imp_decl;
9612 rtx x;
9621 }
9623 /* Try machine-dependent ways of modifying an illegitimate address
9624 to be legitimate. If we find one, return the new, valid address.
9625 This macro is used in only one place: `memory_address' in explow.c.
9627 OLDX is the address as it was before break_out_memory_refs was called.
9628 In some cases it is useful to look at this to decide what needs to be done.
9630 MODE and WIN are passed so that this macro can use
9631 GO_IF_LEGITIMATE_ADDRESS.
9633 It is always safe for this macro to do nothing. It exists to recognize
9634 opportunities to optimize the output.
9636 For the 80386, we handle X+REG by loading X into a register R and
9637 using R+REG. R will go in a general reg and indexing will be used.
9638 However, if REG is a broken-out memory address or multiplication,
9639 nothing needs to be done because REG can certainly go in a general reg.
9641 When -fpic is used, special handling is needed for symbolic references.
9642 See comments by legitimize_pic_address in i386.c for details. */
9644 rtx
9646 {
9657 {
9661 }
9664 {
9671 {
9674 }
9675 }
9680 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9684 {
9689 }
9692 {
9693 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9698 {
9704 }
9709 {
9715 }
9717 /* Put multiply first if it isn't already. */
9719 {
9724 }
9726 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9727 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9728 created by virtual register instantiation, register elimination, and
9729 similar optimizations. */
9731 {
9737 }
9739 /* Canonicalize
9740 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9741 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9746 {
9747 rtx constant;
9751 {
9754 }
9756 {
9759 }
9760 else
9764 {
9770 }
9771 }
9777 {
9780 }
9783 {
9786 }
9794 {
9797 }
9803 {
9811 }
9814 {
9822 }
9823 }
9826 }
9827 \f
9828 /* Print an integer constant expression in assembler syntax. Addition
9829 and subtraction are the only arithmetic that may appear in these
9830 expressions. FILE is the stdio stream to write to, X is the rtx, and
9831 CODE is the operand print code from the output string. */
9833 static void
9835 {
9839 {
9848 else
9849 {
9852 /* Mark the decl as referenced so that cgraph will
9853 output the function. */
9857 #if TARGET_MACHO
9861 #endif
9863 }
9871 /* FALLTHRU */
9882 /* This used to output parentheses around the expression,
9883 but that does not work on the 386 (either ATT or BSD assembler). */
9889 {
9890 /* We can use %d if the number is <32 bits and positive. */
9895 else
9897 }
9898 else
9899 /* We can't handle floating point constants;
9900 PRINT_OPERAND must handle them. */
9905 /* Some assemblers need integer constants to appear first. */
9907 {
9911 }
9912 else
9913 {
9918 }
9935 {
9950 /* FIXME: This might be @TPOFF in Sun ld too. */
9959 else
9969 else
9975 #if TARGET_MACHO
9980 #endif
9984 }
9989 }
9990 }
9992 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9993 We need to emit DTP-relative relocations. */
9995 static void ATTRIBUTE_UNUSED
9997 {
10002 {
10010 }
10011 }
10013 /* Return true if X is a representation of the PIC register. This copes
10014 with calls from ix86_find_base_term, where the register might have
10015 been replaced by a cselib value. */
10017 static bool
10019 {
10023 else
10025 }
10027 /* In the name of slightly smaller debug output, and to cater to
10028 general assembler lossage, recognize PIC+GOTOFF and turn it back
10029 into a direct symbol reference.
10031 On Darwin, this is necessary to avoid a crash, because Darwin
10032 has a different PIC label for each routine but the DWARF debugging
10033 information is not associated with any particular routine, so it's
10034 necessary to remove references to the PIC label from RTL stored by
10035 the DWARF output code. */
10037 static rtx
10039 {
10041 /* reg_addend is NULL or a multiple of some register. */
10043 /* const_addend is NULL or a const_int. */
10045 /* This is the result, or NULL. */
10052 {
10059 }
10066 /* %ebx + GOT/GOTOFF */
10067 ;
10069 {
10070 /* %ebx + %reg * scale + GOT/GOTOFF */
10076 else
10082 }
10083 else
10089 {
10092 }
10111 }
10113 /* If X is a machine specific address (i.e. a symbol or label being
10114 referenced as a displacement from the GOT implemented using an
10115 UNSPEC), then return the base term. Otherwise return X. */
10117 rtx
10119 {
10120 rtx term;
10123 {
10136 }
10139 }
10140 \f
10141 static void
10144 {
10148 {
10154 }
10159 {
10162 {
10181 }
10185 {
10204 }
10211 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10212 Those same assemblers have the same but opposite lossage on cmov. */
10217 else
10222 {
10235 }
10243 {
10256 }
10259 /* ??? As above. */
10268 /* ??? As above. */
10273 else
10284 }
10286 }
10288 /* Print the name of register X to FILE based on its machine mode and number.
10289 If CODE is 'w', pretend the mode is HImode.
10290 If CODE is 'b', pretend the mode is QImode.
10291 If CODE is 'k', pretend the mode is SImode.
10292 If CODE is 'q', pretend the mode is DImode.
10293 If CODE is 'x', pretend the mode is V4SFmode.
10294 If CODE is 't', pretend the mode is V8SFmode.
10295 If CODE is 'h', pretend the reg is the 'high' byte register.
10296 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10297 If CODE is 'd', duplicate the operand for AVX instruction.
10298 */
10300 void
10302 {
10317 {
10321 }
10339 else
10342 /* Irritatingly, AMD extended registers use different naming convention
10343 from the normal registers. */
10345 {
10348 {
10367 }
10369 }
10373 {
10376 {
10379 }
10380 /* FALLTHRU */
10386 /* FALLTHRU */
10389 normal:
10404 {
10409 }
10413 }
10417 {
10420 else
10422 }
10423 }
10425 /* Locate some local-dynamic symbol still in use by this function
10426 so that we can print its name in some tls_local_dynamic_base
10427 pattern. */
10429 static int
10431 {
10436 {
10439 }
10442 }
10446 {
10447 rtx insn;
10458 }
10460 /* Meaning of CODE:
10461 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10462 C -- print opcode suffix for set/cmov insn.
10463 c -- like C, but print reversed condition
10464 E,e -- likewise, but for compare-and-branch fused insn.
10465 F,f -- likewise, but for floating-point.
10466 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10467 otherwise nothing
10468 R -- print the prefix for register names.
10469 z -- print the opcode suffix for the size of the current operand.
10470 * -- print a star (in certain assembler syntax)
10471 A -- print an absolute memory reference.
10472 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10473 s -- print a shift double count, followed by the assemblers argument
10474 delimiter.
10475 b -- print the QImode name of the register for the indicated operand.
10476 %b0 would print %al if operands[0] is reg 0.
10477 w -- likewise, print the HImode name of the register.
10478 k -- likewise, print the SImode name of the register.
10479 q -- likewise, print the DImode name of the register.
10480 x -- likewise, print the V4SFmode name of the register.
10481 t -- likewise, print the V8SFmode name of the register.
10482 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10483 y -- print "st(0)" instead of "st" as a register.
10484 d -- print duplicated register operand for AVX instruction.
10485 D -- print condition for SSE cmp instruction.
10486 P -- if PIC, print an @PLT suffix.
10487 X -- don't print any sort of PIC '@' suffix for a symbol.
10488 & -- print some in-use local-dynamic symbol name.
10489 H -- print a memory address offset by 8; used for sse high-parts
10490 Y -- print condition for SSE5 com* instruction.
10491 + -- print a branch hint as 'cs' or 'ds' prefix
10492 ; -- print a semicolon (after prefixes due to bug in older gas).
10493 */
10495 void
10497 {
10499 {
10501 {
10513 {
10519 /* Intel syntax. For absolute addresses, registers should not
10520 be surrounded by braces. */
10522 {
10527 }
10532 }
10569 /* 387 opcodes don't get size suffixes if the operands are
10570 registers. */
10574 /* Likewise if using Intel opcodes. */
10578 /* This is the size of op from size of operand. */
10580 {
10587 {
10588 #ifdef HAVE_GAS_FILDS_FISTS
10590 #endif
10592 }
10593 else
10599 {
10602 }
10603 else
10614 {
10616 {
10617 #ifdef GAS_MNEMONICS
10619 #else
10622 #endif
10623 }
10624 else
10626 }
10627 else
10633 }
10650 {
10653 }
10657 /* Little bit of braindamage here. The SSE compare instructions
10658 does use completely different names for the comparisons that the
10659 fp conditional moves. */
10661 {
10663 {
10708 }
10709 }
10710 else
10711 {
10713 {
10746 }
10747 }
10750 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10752 {
10754 {
10761 }
10763 }
10764 #endif
10770 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10773 #endif
10777 /* Like above, but reverse condition */
10779 /* Check to see if argument to %c is really a constant
10780 and not a condition code which needs to be reversed. */
10782 {
10783 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
10785 }
10789 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10792 #endif
10805 /* It doesn't actually matter what mode we use here, as we're
10806 only going to use this for printing. */
10811 {
10812 rtx x;
10820 {
10825 {
10829 /* Emit hints only in the case default branch prediction
10830 heuristics would fail. */
10832 {
10833 /* We use 3e (DS) prefix for taken branches and
10834 2e (CS) prefix for not taken branches. */
10837 else
10839 }
10840 }
10841 }
10843 }
10847 {
10896 }
10900 #if TARGET_MACHO
10902 #else
10904 #endif
10909 }
10910 }
10916 {
10917 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
10920 {
10923 {
10932 else
10937 }
10939 /* Check for explicit size override (codes 'b', 'w' and 'k') */
10949 }
10952 /* Avoid (%rip) for call operands. */
10958 else
10960 }
10963 {
10964 REAL_VALUE_TYPE r;
10973 }
10975 /* These float cases don't actually occur as immediate operands. */
10977 {
10982 }
10986 {
10991 }
10993 else
10994 {
10995 /* We have patterns that allow zero sets of memory, for instance.
10996 In 64-bit mode, we should probably support all 8-byte vectors,
10997 since we can in fact encode that into an immediate. */
10999 {
11002 }
11005 {
11007 {
11010 }
11013 {
11016 else
11018 }
11019 }
11024 else
11026 }
11027 }
11028 \f
11029 /* Print a memory operand whose address is ADDR. */
11031 void
11033 {
11047 {
11058 }
11060 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11062 {
11074 }
11076 {
11077 /* Displacement only requires special attention. */
11080 {
11084 }
11087 else
11089 }
11090 else
11091 {
11093 {
11095 {
11100 else
11102 }
11108 {
11113 }
11115 }
11116 else
11117 {
11121 {
11122 /* Pull out the offset of a symbol; print any symbol itself. */
11126 {
11130 }
11138 else
11140 }
11144 {
11147 {
11151 }
11152 }
11155 else
11159 {
11164 }
11166 }
11167 }
11168 }
11170 bool
11172 {
11173 rtx op;
11180 {
11183 /* FIXME: This might be @TPOFF in Sun ld. */
11194 else
11206 else
11213 #if TARGET_MACHO
11219 #endif
11223 }
11226 }
11227 \f
11228 /* Split one or more DImode RTL references into pairs of SImode
11229 references. The RTL can be REG, offsettable MEM, integer constant, or
11230 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11231 split and "num" is its length. lo_half and hi_half are output arrays
11232 that parallel "operands". */
11234 void
11236 {
11238 {
11241 /* simplify_subreg refuse to split volatile memory addresses,
11242 but we still have to handle it. */
11244 {
11247 }
11248 else
11249 {
11256 }
11257 }
11258 }
11259 /* Split one or more TImode RTL references into pairs of DImode
11260 references. The RTL can be REG, offsettable MEM, integer constant, or
11261 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11262 split and "num" is its length. lo_half and hi_half are output arrays
11263 that parallel "operands". */
11265 void
11267 {
11269 {
11272 /* simplify_subreg refuse to split volatile memory addresses, but we
11273 still have to handle it. */
11275 {
11278 }
11279 else
11280 {
11283 }
11284 }
11285 }
11286 \f
11287 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11288 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11289 is the expression of the binary operation. The output may either be
11290 emitted here, or returned to the caller, like all output_* functions.
11292 There is no guarantee that the operands are the same mode, as they
11293 might be within FLOAT or FLOAT_EXTEND expressions. */
11295 #ifndef SYSV386_COMPAT
11296 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11297 wants to fix the assemblers because that causes incompatibility
11298 with gcc. No-one wants to fix gcc because that causes
11299 incompatibility with assemblers... You can use the option of
11300 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11301 #define SYSV386_COMPAT 1
11302 #endif
11306 {
11312 #ifdef ENABLE_CHECKING
11313 /* Even if we do not want to check the inputs, this documents input
11314 constraints. Which helps in understanding the following code. */
11324 else
11326 #endif
11329 {
11334 else
11343 else
11352 else
11361 else
11368 }
11371 {
11373 {
11377 else
11379 }
11380 else
11381 {
11385 else
11387 }
11389 }
11393 {
11397 {
11401 }
11403 /* know operands[0] == operands[1]. */
11406 {
11409 }
11412 {
11414 /* How is it that we are storing to a dead operand[2]?
11415 Well, presumably operands[1] is dead too. We can't
11416 store the result to st(0) as st(0) gets popped on this
11417 instruction. Instead store to operands[2] (which I
11418 think has to be st(1)). st(1) will be popped later.
11419 gcc <= 2.8.1 didn't have this check and generated
11420 assembly code that the Unixware assembler rejected. */
11422 else
11425 }
11429 else
11436 {
11439 }
11442 {
11445 }
11448 {
11449 #if SYSV386_COMPAT
11450 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11451 derived assemblers, confusingly reverse the direction of
11452 the operation for fsub{r} and fdiv{r} when the
11453 destination register is not st(0). The Intel assembler
11454 doesn't have this brain damage. Read !SYSV386_COMPAT to
11455 figure out what the hardware really does. */
11458 else
11460 #else
11462 /* As above for fmul/fadd, we can't store to st(0). */
11464 else
11466 #endif
11468 }
11471 {
11472 #if SYSV386_COMPAT
11475 else
11477 #else
11480 else
11482 #endif
11484 }
11487 {
11490 else
11493 }
11495 {
11496 #if SYSV386_COMPAT
11498 #else
11500 #endif
11501 }
11502 else
11503 {
11504 #if SYSV386_COMPAT
11506 #else
11508 #endif
11509 }
11514 }
11518 }
11520 /* Return needed mode for entity in optimize_mode_switching pass. */
11522 int
11524 {
11527 /* The mode UNINITIALIZED is used to store control word after a
11528 function call or ASM pattern. The mode ANY specify that function
11529 has no requirements on the control word and make no changes in the
11530 bits we are interested in. */
11544 {
11567 }
11570 }
11572 /* Output code to initialize control word copies used by trunc?f?i and
11573 rounding patterns. CURRENT_MODE is set to current control word,
11574 while NEW_MODE is set to new control word. */
11576 void
11578 {
11580 rtx new_mode;
11591 {
11593 {
11595 /* round toward zero (truncate) */
11601 /* round down toward -oo */
11608 /* round up toward +oo */
11615 /* mask precision exception for nearbyint() */
11622 }
11623 }
11624 else
11625 {
11627 {
11629 /* round toward zero (truncate) */
11635 /* round down toward -oo */
11641 /* round up toward +oo */
11647 /* mask precision exception for nearbyint() */
11654 }
11655 }
11661 }
11663 /* Output code for INSN to convert a float to a signed int. OPERANDS
11664 are the insn operands. The output may be [HSD]Imode and the input
11665 operand may be [SDX]Fmode. */
11669 {
11674 /* Jump through a hoop or two for DImode, since the hardware has no
11675 non-popping instruction. We used to do this a different way, but
11676 that was somewhat fragile and broke with post-reload splitters. */
11686 else
11687 {
11692 else
11696 }
11699 }
11701 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11702 have the values zero or one, indicates the ffreep insn's operand
11703 from the OPERANDS array. */
11707 {
11709 #if HAVE_AS_IX86_FFREEP
11711 #else
11712 {
11720 }
11721 #endif
11724 }
11727 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11728 should be used. UNORDERED_P is true when fucom should be used. */
11732 {
11738 {
11741 }
11742 else
11743 {
11746 }
11749 {
11758 else
11760 else
11763 else
11765 }
11772 {
11774 {
11777 }
11778 else
11780 }
11783 && stack_top_dies
11786 {
11787 /* If both the top of the 387 stack dies, and the other operand
11788 is also a stack register that dies, then this must be a
11789 `fcompp' float compare */
11792 {
11793 /* There is no double popping fcomi variant. Fortunately,
11794 eflags is immune from the fstp's cc clobbering. */
11797 else
11800 }
11801 else
11802 {
11805 else
11807 }
11808 }
11809 else
11810 {
11811 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
11814 {
11822 NULL,
11823 NULL,
11830 NULL,
11831 NULL,
11832 NULL,
11833 NULL
11834 };
11849 }
11850 }
11852 void
11854 {
11857 #ifdef ASM_QUAD
11860 #else
11862 #endif
11865 }
11867 void
11869 {
11872 #ifdef ASM_QUAD
11875 #else
11877 #endif
11878 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
11884 #if TARGET_MACHO
11886 {
11890 }
11891 #endif
11892 else
11895 }
11896 \f
11897 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
11898 for the target. */
11900 void
11902 {
11903 rtx tmp;
11905 /* We play register width games, which are only valid after reload. */
11908 /* Avoid HImode and its attendant prefix byte. */
11913 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
11915 {
11918 }
11921 }
11923 /* X is an unchanging MEM. If it is a constant pool reference, return
11924 the constant pool rtx, else NULL. */
11926 rtx
11928 {
11935 }
11937 void
11939 {
11947 {
11950 {
11955 }
11959 }
11963 {
11976 {
11982 }
11983 }
11986 {
11988 {
11989 #if TARGET_MACHO
11991 {
11992 rtx temp = ((reload_in_progress
11999 }
12004 #endif
12005 }
12006 else
12007 {
12011 {
12016 }
12017 }
12018 }
12019 else
12020 {
12031 /* Force large constants in 64bit compilation into register
12032 to get them CSEed. */
12044 {
12045 /* If we are loading a floating point constant to a register,
12046 force the value to memory now, since we'll get better code
12047 out the back end. */
12051 {
12056 }
12057 }
12058 }
12061 }
12063 void
12065 {
12069 /* Force constants other than zero into memory. We do not know how
12070 the instructions used to build constants modify the upper 64 bits
12071 of the register, once we have that information we may be able
12072 to handle some of them more efficiently. */
12081 /* We need to check memory alignment for SSE mode since attribute
12082 can make operands unaligned. */
12087 {
12090 /* ix86_expand_vector_move_misalign() does not like constants ... */
12096 /* ... nor both arguments in memory. */
12104 }
12106 /* Make operand1 a register if it isn't already. */
12110 {
12113 }
12116 }
12118 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12119 straight to ix86_expand_vector_move. */
12120 /* Code generation for scalar reg-reg moves of single and double precision data:
12121 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12122 movaps reg, reg
12123 else
12124 movss reg, reg
12125 if (x86_sse_partial_reg_dependency == true)
12126 movapd reg, reg
12127 else
12128 movsd reg, reg
12130 Code generation for scalar loads of double precision data:
12131 if (x86_sse_split_regs == true)
12132 movlpd mem, reg (gas syntax)
12133 else
12134 movsd mem, reg
12136 Code generation for unaligned packed loads of single precision data
12137 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12138 if (x86_sse_unaligned_move_optimal)
12139 movups mem, reg
12141 if (x86_sse_partial_reg_dependency == true)
12142 {
12143 xorps reg, reg
12144 movlps mem, reg
12145 movhps mem+8, reg
12146 }
12147 else
12148 {
12149 movlps mem, reg
12150 movhps mem+8, reg
12151 }
12153 Code generation for unaligned packed loads of double precision data
12154 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12155 if (x86_sse_unaligned_move_optimal)
12156 movupd mem, reg
12158 if (x86_sse_split_regs == true)
12159 {
12160 movlpd mem, reg
12161 movhpd mem+8, reg
12162 }
12163 else
12164 {
12165 movsd mem, reg
12166 movhpd mem+8, reg
12167 }
12168 */
12170 void
12172 {
12179 {
12181 {
12185 {
12198 }
12205 {
12220 }
12225 }
12228 }
12231 {
12232 /* If we're optimizing for size, movups is the smallest. */
12234 {
12239 }
12241 /* ??? If we have typed data, then it would appear that using
12242 movdqu is the only way to get unaligned data loaded with
12243 integer type. */
12245 {
12250 }
12253 {
12254 rtx zero;
12257 {
12262 }
12264 /* When SSE registers are split into halves, we can avoid
12265 writing to the top half twice. */
12267 {
12270 }
12271 else
12272 {
12273 /* ??? Not sure about the best option for the Intel chips.
12274 The following would seem to satisfy; the register is
12275 entirely cleared, breaking the dependency chain. We
12276 then store to the upper half, with a dependency depth
12277 of one. A rumor has it that Intel recommends two movsd
12278 followed by an unpacklpd, but this is unconfirmed. And
12279 given that the dependency depth of the unpacklpd would
12280 still be one, I'm not sure why this would be better. */
12282 }
12288 }
12289 else
12290 {
12292 {
12297 }
12301 else
12310 }
12311 }
12313 {
12314 /* If we're optimizing for size, movups is the smallest. */
12316 {
12321 }
12323 /* ??? Similar to above, only less clear because of quote
12324 typeless stores unquote. */
12327 {
12332 }
12335 {
12340 }
12341 else
12342 {
12349 }
12350 }
12351 else
12353 }
12355 /* Expand a push in MODE. This is some mode for which we do not support
12356 proper push instructions, at least from the registers that we expect
12357 the value to live in. */
12359 void
12361 {
12362 rtx tmp;
12372 }
12374 /* Helper function of ix86_fixup_binary_operands to canonicalize
12375 operand order. Returns true if the operands should be swapped. */
12377 static bool
12379 rtx operands[])
12380 {
12385 /* If the operation is not commutative, we can't do anything. */
12389 /* Highest priority is that src1 should match dst. */
12395 /* Next highest priority is that immediate constants come second. */
12401 /* Lowest priority is that memory references should come second. */
12408 }
12411 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12412 destination to use for the operation. If different from the true
12413 destination in operands[0], a copy operation will be required. */
12415 rtx
12417 rtx operands[])
12418 {
12423 /* Canonicalize operand order. */
12425 {
12426 rtx temp;
12428 /* It is invalid to swap operands of different modes. */
12434 }
12436 /* Both source operands cannot be in memory. */
12438 {
12439 /* Optimization: Only read from memory once. */
12441 {
12444 }
12445 else
12447 }
12449 /* If the destination is memory, and we do not have matching source
12450 operands, do things in registers. */
12454 /* Source 1 cannot be a constant. */
12458 /* Source 1 cannot be a non-matching memory. */
12465 }
12467 /* Similarly, but assume that the destination has already been
12468 set up properly. */
12470 void
12473 {
12476 }
12478 /* Attempt to expand a binary operator. Make the expansion closer to the
12479 actual machine, then just general_operand, which will allow 3 separate
12480 memory references (one output, two input) in a single insn. */
12482 void
12484 rtx operands[])
12485 {
12492 /* Emit the instruction. */
12496 {
12497 /* Reload doesn't know about the flags register, and doesn't know that
12498 it doesn't want to clobber it. We can only do this with PLUS. */
12501 }
12502 else
12503 {
12506 }
12508 /* Fix up the destination if needed. */
12511 }
12513 /* Return TRUE or FALSE depending on whether the binary operator meets the
12514 appropriate constraints. */
12516 int
12519 {
12524 /* Both source operands cannot be in memory. */
12528 /* Canonicalize operand order for commutative operators. */
12530 {
12534 }
12536 /* If the destination is memory, we must have a matching source operand. */
12540 /* Source 1 cannot be a constant. */
12544 /* Source 1 cannot be a non-matching memory. */
12549 }
12551 /* Attempt to expand a unary operator. Make the expansion closer to the
12552 actual machine, then just general_operand, which will allow 2 separate
12553 memory references (one output, one input) in a single insn. */
12555 void
12557 rtx operands[])
12558 {
12565 /* If the destination is memory, and we do not have matching source
12566 operands, do things in registers. */
12569 {
12572 else
12574 }
12576 /* When source operand is memory, destination must match. */
12580 /* Emit the instruction. */
12584 {
12585 /* Reload doesn't know about the flags register, and doesn't know that
12586 it doesn't want to clobber it. */
12589 }
12590 else
12591 {
12594 }
12596 /* Fix up the destination if needed. */
12599 }
12601 /* Return TRUE or FALSE depending on whether the unary operator meets the
12602 appropriate constraints. */
12604 int
12608 {
12609 /* If one of operands is memory, source and destination must match. */
12615 }
12617 /* Post-reload splitter for converting an SF or DFmode value in an
12618 SSE register into an unsigned SImode. */
12620 void
12622 {
12633 /* Load up the value into the low element. We must ensure that the other
12634 elements are valid floats -- zero is the easiest such value. */
12636 {
12639 else
12641 }
12642 else
12643 {
12648 else
12650 }
12670 else
12675 }
12677 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12678 Expects the 64-bit DImode to be supplied in a pair of integral
12679 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12680 -mfpmath=sse, !optimize_size only. */
12682 void
12684 {
12688 rtx x;
12694 {
12697 }
12698 else
12699 {
12703 }
12711 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12714 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12715 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12716 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12717 (0x1.0p84 + double(fp_value_hi_xmm)).
12718 Note these exponents differ by 32. */
12722 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12723 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12732 /* Add the upper and lower DFmode values together. */
12735 else
12736 {
12740 }
12743 }
12745 /* Not used, but eases macroization of patterns. */
12746 void
12748 rtx input ATTRIBUTE_UNUSED)
12749 {
12751 }
12753 /* Convert an unsigned SImode value into a DFmode. Only currently used
12754 for SSE, but applicable anywhere. */
12756 void
12758 {
12759 REAL_VALUE_TYPE TWO31r;
12774 }
12776 /* Convert a signed DImode value into a DFmode. Only used for SSE in
12777 32-bit mode; otherwise we have a direct convert instruction. */
12779 void
12781 {
12782 REAL_VALUE_TYPE TWO32r;
12800 }
12802 /* Convert an unsigned SImode value into a SFmode, using only SSE.
12803 For x86_32, -mfpmath=sse, !optimize_size only. */
12804 void
12806 {
12807 REAL_VALUE_TYPE ONE16r;
12826 }
12828 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
12829 then replicate the value for all elements of the vector
12830 register. */
12832 rtx
12834 {
12835 rtvec v;
12837 {
12851 else
12859 else
12865 }
12866 }
12868 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
12869 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
12870 for an SSE register. If VECT is true, then replicate the mask for
12871 all elements of the vector register. If INVERT is true, then create
12872 a mask excluding the sign bit. */
12874 rtx
12876 {
12880 rtx v;
12881 rtx mask;
12883 /* Find the sign bit, sign extended to 2*HWI. */
12885 {
12899 else
12907 {
12910 }
12911 else
12912 {
12913 rtvec vec;
12919 {
12922 }
12923 else
12933 }
12938 }
12943 /* Force this value into the low part of a fp vector constant. */
12952 }
12954 /* Generate code for floating point ABS or NEG. */
12956 void
12958 rtx operands[])
12959 {
12966 {
12969 }
12975 /* NEG and ABS performed with SSE use bitwise mask operations.
12976 Create the appropriate mask now. */
12979 else
12986 {
12990 }
12991 else
12992 {
12996 {
13001 }
13002 else
13004 }
13005 }
13007 /* Expand a copysign operation. Special case operand 0 being a constant. */
13009 void
13011 {
13022 {
13029 {
13036 else
13037 {
13038 rtvec v;
13043 else
13047 }
13048 }
13058 else
13062 }
13063 else
13064 {
13074 else
13078 }
13079 }
13081 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13082 be a constant, and so has already been expanded into a vector constant. */
13084 void
13086 {
13103 {
13106 }
13107 }
13109 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13110 so we have to do two masks. */
13112 void
13114 {
13129 {
13130 /* Shouldn't happen often (it's useless, obviously), but when it does
13131 we'd generate incorrect code if we continue below. */
13134 }
13137 {
13148 }
13149 else
13150 {
13152 {
13154 }
13156 {
13160 }
13164 {
13167 }
13169 {
13174 }
13176 }
13180 }
13182 /* Return TRUE or FALSE depending on whether the first SET in INSN
13183 has source and destination with matching CC modes, and that the
13184 CC mode is at least as constrained as REQ_MODE. */
13186 int
13188 {
13189 rtx set;
13200 {
13210 /* FALLTHRU */
13214 /* FALLTHRU */
13218 /* FALLTHRU */
13228 }
13231 }
13233 /* Generate insn patterns to do an integer compare of OPERANDS. */
13235 static rtx
13237 {
13244 /* This is very simple, but making the interface the same as in the
13245 FP case makes the rest of the code easier. */
13249 /* Return the test that should be put into the flags user, i.e.
13250 the bcc, scc, or cmov instruction. */
13252 }
13254 /* Figure out whether to use ordered or unordered fp comparisons.
13255 Return the appropriate mode to use. */
13257 enum machine_mode
13259 {
13260 /* ??? In order to make all comparisons reversible, we do all comparisons
13261 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13262 all forms trapping and nontrapping comparisons, we can make inequality
13263 comparisons trapping again, since it results in better code when using
13264 FCOM based compares. */
13266 }
13268 enum machine_mode
13270 {
13274 {
13277 }
13280 {
13281 /* Only zero flag is needed. */
13285 /* Codes needing carry flag. */
13288 /* Detect overflow checks. They need just the carry flag. */
13292 else
13296 /* Detect overflow checks. They need just the carry flag. */
13300 else
13302 /* Codes possibly doable only with sign flag when
13303 comparing against zero. */
13308 else
13309 /* For other cases Carry flag is not required. */
13311 /* Codes doable only with sign flag when comparing
13312 against zero, but we miss jump instruction for it
13313 so we need to use relational tests against overflow
13314 that thus needs to be zero. */
13319 else
13321 /* strcmp pattern do (use flags) and combine may ask us for proper
13322 mode. */
13327 }
13328 }
13330 /* Return the fixed registers used for condition codes. */
13332 static bool
13334 {
13338 }
13340 /* If two condition code modes are compatible, return a condition code
13341 mode which is compatible with both. Otherwise, return
13342 VOIDmode. */
13344 static enum machine_mode
13346 {
13358 {
13372 {
13386 }
13390 /* These are only compatible with themselves, which we already
13391 checked above. */
13393 }
13394 }
13396 /* Split comparison code CODE into comparisons we can do using branch
13397 instructions. BYPASS_CODE is comparison code for branch that will
13398 branch around FIRST_CODE and SECOND_CODE. If some of branches
13399 is not required, set value to UNKNOWN.
13400 We never require more than two branches. */
13402 void
13406 {
13411 /* The fcomi comparison sets flags as follows:
13413 cmp ZF PF CF
13414 > 0 0 0
13415 < 0 0 1
13416 = 1 0 0
13417 un 1 1 1 */
13420 {
13456 }
13458 {
13461 }
13462 }
13464 /* Return cost of comparison done fcom + arithmetics operations on AX.
13465 All following functions do use number of instructions as a cost metrics.
13466 In future this should be tweaked to compute bytes for optimize_size and
13467 take into account performance of various instructions on various CPUs. */
13468 static int
13470 {
13473 /* The cost of code output by ix86_expand_fp_compare. */
13475 {
13498 }
13499 }
13501 /* Return cost of comparison done using fcomi operation.
13502 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13503 static int
13505 {
13507 /* Return arbitrarily high cost when instruction is not supported - this
13508 prevents gcc from using it. */
13513 }
13515 /* Return cost of comparison done using sahf operation.
13516 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13517 static int
13519 {
13521 /* Return arbitrarily high cost when instruction is not preferred - this
13522 avoids gcc from using it. */
13527 }
13529 /* Compute cost of the comparison done using any method.
13530 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13531 static int
13533 {
13546 }
13548 /* Return true if we should use an FCOMI instruction for this
13549 fp comparison. */
13551 int
13553 {
13560 }
13562 /* Swap, force into registers, or otherwise massage the two operands
13563 to a fp comparison. The operands are updated in place; the new
13564 comparison code is returned. */
13566 static enum rtx_code
13568 {
13574 /* All of the unordered compare instructions only work on registers.
13575 The same is true of the fcomi compare instructions. The XFmode
13576 compare instructions require registers except when comparing
13577 against zero or when converting operand 1 from fixed point to
13578 floating point. */
13587 {
13590 }
13591 else
13592 {
13593 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13594 things around if they appear profitable, otherwise force op0
13595 into a register. */
13601 {
13602 rtx tmp;
13605 }
13611 {
13616 {
13619 }
13620 else
13622 }
13623 }
13625 /* Try to rearrange the comparison to make it cheaper. */
13629 {
13630 rtx tmp;
13635 }
13640 }
13642 /* Convert comparison codes we use to represent FP comparison to integer
13643 code that will result in proper branch. Return UNKNOWN if no such code
13644 is available. */
13646 enum rtx_code
13648 {
13650 {
13673 }
13674 }
13676 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13678 static rtx
13681 {
13697 /* Do fcomi/sahf based test when profitable. */
13701 {
13704 tmp);
13707 else
13708 {
13716 }
13718 /* The FP codes work out to act like unsigned. */
13724 const0_rtx);
13728 const0_rtx);
13729 }
13730 else
13731 {
13732 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13739 /* In the unordered case, we have to check C2 for NaN's, which
13740 doesn't happen to work out to anything nice combination-wise.
13741 So do some bit twiddling on the value we've got in AH to come
13742 up with an appropriate set of condition codes. */
13746 {
13750 {
13753 }
13754 else
13755 {
13761 }
13766 {
13771 }
13772 else
13773 {
13776 }
13781 {
13784 }
13785 else
13786 {
13791 }
13796 {
13802 }
13803 else
13804 {
13807 }
13812 {
13817 }
13818 else
13819 {
13823 }
13828 {
13833 }
13834 else
13835 {
13838 }
13852 }
13853 }
13855 /* Return the test that should be put into the flags user, i.e.
13856 the bcc, scc, or cmov instruction. */
13859 const0_rtx);
13860 }
13862 rtx
13864 {
13875 {
13878 }
13880 {
13884 }
13885 else
13889 }
13891 /* Return true if the CODE will result in nontrivial jump sequence. */
13892 bool
13894 {
13900 }
13902 void
13904 {
13905 rtx tmp;
13907 /* If we have emitted a compare insn, go straight to simple.
13908 ix86_expand_compare won't emit anything if ix86_compare_emitted
13909 is non NULL. */
13914 {
13918 simple:
13922 pc_rtx);
13929 {
13930 rtvec vec;
13939 /* Check whether we will use the natural sequence with one jump. If
13940 so, we can expand jump early. Otherwise delay expansion by
13941 creating compound insn to not confuse optimizers. */
13943 {
13947 }
13948 else
13949 {
13954 pc_rtx);
13969 }
13971 }
13977 /* Expand DImode branch into multiple compare+branch. */
13978 {
13984 {
13989 }
13991 {
13995 }
13996 else
13997 {
14001 }
14003 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14004 avoid two branches. This costs one extra insn, so disable when
14005 optimizing for size. */
14010 {
14030 }
14032 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14033 op1 is a constant and the low word is zero, then we can just
14034 examine the high word. Similarly for low word -1 and
14035 less-or-equal-than or greater-than. */
14039 {
14042 {
14047 }
14051 {
14056 }
14060 }
14062 /* Otherwise, we need two or three jumps. */
14071 {
14085 }
14087 /*
14088 * a < b =>
14089 * if (hi(a) < hi(b)) goto true;
14090 * if (hi(a) > hi(b)) goto false;
14091 * if (lo(a) < lo(b)) goto true;
14092 * false:
14093 */
14110 }
14114 }
14115 }
14117 /* Split branch based on floating point condition. */
14118 void
14121 {
14124 rtx condition;
14126 rtx i;
14129 {
14134 }
14139 /* Remove pushed operand from stack. */
14144 {
14145 /* Distribute the probabilities across the jumps.
14146 Assume the BYPASS and SECOND to be always test
14147 for UNORDERED. */
14150 /* Value of 1 is low enough to make no need for probability
14151 to be updated. Later we may run some experiments and see
14152 if unordered values are more frequent in practice. */
14157 }
14159 {
14164 bypass,
14166 label),
14167 pc_rtx)));
14173 }
14184 {
14188 target2)));
14194 }
14197 }
14199 int
14201 {
14218 {
14223 {
14228 }
14234 else
14236 }
14238 /* Attach a REG_EQUAL note describing the comparison result. */
14240 {
14245 }
14248 }
14250 /* Expand comparison setting or clearing carry flag. Return true when
14251 successful and set pop for the operation. */
14252 static bool
14254 {
14258 /* Do not handle DImode compares that go through special path. */
14263 {
14269 /* Shortcut: following common codes never translate
14270 into carry flag compares. */
14275 /* These comparisons require zero flag; swap operands so they won't. */
14278 {
14283 }
14285 /* Try to expand the comparison and verify that we end up with
14286 carry flag based comparison. This fails to be true only when
14287 we decide to expand comparison using arithmetic that is not
14288 too common scenario. */
14301 else
14310 }
14316 {
14321 /* Convert a==0 into (unsigned)a<1. */
14330 /* Convert a>b into b<a or a>=b-1. */
14334 {
14336 /* Bail out on overflow. We still can swap operands but that
14337 would force loading of the constant into register. */
14342 }
14343 else
14344 {
14349 }
14352 /* Convert a>=0 into (unsigned)a<0x80000000. */
14370 }
14371 /* Swapping operands may cause constant to appear as first operand. */
14373 {
14377 }
14383 }
14385 int
14387 {
14405 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14406 HImode insns, we'd be swallowed in word prefix ops. */
14412 {
14416 HOST_WIDE_INT diff;
14419 /* Sign bit compares are better done using shifts than we do by using
14420 sbb. */
14424 {
14425 /* Detect overlap between destination and compare sources. */
14429 {
14436 {
14439 }
14441 /* To simplify rest of code, restrict to the GEU case. */
14443 {
14449 }
14450 else
14451 {
14454 reverse_condition_maybe_unordered
14456 else
14458 }
14467 else
14469 }
14470 else
14471 {
14474 else
14475 {
14480 }
14483 }
14486 {
14487 /*
14488 * cmpl op0,op1
14489 * sbbl dest,dest
14490 * [addl dest, ct]
14491 *
14492 * Size 5 - 8.
14493 */
14498 }
14500 {
14501 /*
14502 * cmpl op0,op1
14503 * sbbl dest,dest
14504 * orl $ct, dest
14505 *
14506 * Size 8.
14507 */
14511 }
14513 {
14514 /*
14515 * cmpl op0,op1
14516 * sbbl dest,dest
14517 * notl dest
14518 * [addl dest, cf]
14519 *
14520 * Size 8 - 11.
14521 */
14527 }
14528 else
14529 {
14530 /*
14531 * cmpl op0,op1
14532 * sbbl dest,dest
14533 * [notl dest]
14534 * andl cf - ct, dest
14535 * [addl dest, ct]
14536 *
14537 * Size 8 - 11.
14538 */
14541 {
14545 }
14555 }
14561 }
14564 {
14567 HOST_WIDE_INT tmp;
14572 {
14575 /* We may be reversing unordered compare to normal compare, that
14576 is not valid in general (we may convert non-trapping condition
14577 to trapping one), however on i386 we currently emit all
14578 comparisons unordered. */
14581 }
14582 else
14583 {
14586 }
14587 }
14592 {
14597 {
14602 }
14603 }
14605 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14609 {
14610 /* If lea code below could be used, only optimize
14611 if it results in a 2 insn sequence. */
14617 {
14618 /*
14619 * notl op1 (if necessary)
14620 * sarl $31, op1
14621 * orl cf, op1
14622 */
14624 {
14628 }
14640 }
14641 }
14649 {
14650 /*
14651 * xorl dest,dest
14652 * cmpl op1,op2
14653 * setcc dest
14654 * lea cf(dest*(ct-cf)),dest
14655 *
14656 * Size 14.
14657 *
14658 * This also catches the degenerate setcc-only case.
14659 */
14661 rtx tmp;
14668 /* On x86_64 the lea instruction operates on Pmode, so we need
14669 to get arithmetics done in proper mode to match. */
14672 else
14673 {
14674 rtx out1;
14677 nops++;
14679 {
14681 nops++;
14682 }
14683 }
14685 {
14687 nops++;
14688 }
14690 {
14693 else
14695 }
14700 }
14702 /*
14703 * General case: Jumpful:
14704 * xorl dest,dest cmpl op1, op2
14705 * cmpl op1, op2 movl ct, dest
14706 * setcc dest jcc 1f
14707 * decl dest movl cf, dest
14708 * andl (cf-ct),dest 1:
14709 * addl ct,dest
14710 *
14711 * Size 20. Size 14.
14712 *
14713 * This is reasonably steep, but branch mispredict costs are
14714 * high on modern cpus, so consider failing only if optimizing
14715 * for space.
14716 */
14721 {
14723 {
14730 {
14733 /* We may be reversing unordered compare to normal compare,
14734 that is not valid in general (we may convert non-trapping
14735 condition to trapping one), however on i386 we currently
14736 emit all comparisons unordered. */
14738 }
14739 else
14740 {
14744 }
14745 }
14748 {
14749 /* notl op1 (if needed)
14750 sarl $31, op1
14751 andl (cf-ct), op1
14752 addl ct, op1
14754 For x < 0 (resp. x <= -1) there will be no notl,
14755 so if possible swap the constants to get rid of the
14756 complement.
14757 True/false will be -1/0 while code below (store flag
14758 followed by decrement) is 0/-1, so the constants need
14759 to be exchanged once more. */
14762 {
14765 }
14766 else
14767 {
14771 }
14775 }
14776 else
14777 {
14783 }
14795 }
14796 }
14799 {
14800 /* Try a few things more with specific constants and a variable. */
14802 optab op;
14808 /* If one of the two operands is an interesting constant, load a
14809 constant with the above and mask it in with a logical operation. */
14812 {
14818 else
14820 }
14822 {
14828 else
14830 }
14831 else
14838 /* Recurse to get the constant loaded. */
14842 /* Mask in the interesting variable. */
14844 OPTAB_WIDEN);
14849 }
14851 /*
14852 * For comparison with above,
14853 *
14854 * movl cf,dest
14855 * movl ct,tmp
14856 * cmpl op1,op2
14857 * cmovcc tmp,dest
14858 *
14859 * Size 15.
14860 */
14868 {
14872 }
14874 {
14878 }
14897 bypass_test,
14903 second_test,
14908 }
14910 /* Swap, force into registers, or otherwise massage the two operands
14911 to an sse comparison with a mask result. Thus we differ a bit from
14912 ix86_prepare_fp_compare_args which expects to produce a flags result.
14914 The DEST operand exists to help determine whether to commute commutative
14915 operators. The POP0/POP1 operands are updated in place. The new
14916 comparison code is returned, or UNKNOWN if not implementable. */
14918 static enum rtx_code
14921 {
14922 rtx tmp;
14925 {
14928 /* We have no LTGT as an operator. We could implement it with
14929 NE & ORDERED, but this requires an extra temporary. It's
14930 not clear that it's worth it. */
14937 /* These are supported directly. */
14944 /* For commutative operators, try to canonicalize the destination
14945 operand to be first in the comparison - this helps reload to
14946 avoid extra moves. */
14949 /* FALLTHRU */
14955 /* These are not supported directly. Swap the comparison operands
14956 to transform into something that is supported. */
14965 }
14968 }
14970 /* Detect conditional moves that exactly match min/max operational
14971 semantics. Note that this is IEEE safe, as long as we don't
14972 interchange the operands.
14974 Returns FALSE if this conditional move doesn't match a MIN/MAX,
14975 and TRUE if the operation is successful and instructions are emitted. */
14977 static bool
14980 {
14983 rtx tmp;
14986 ;
14988 {
14992 }
14993 else
15000 else
15005 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15006 but MODE may be a vector mode and thus not appropriate. */
15008 {
15010 rtvec v;
15015 }
15016 else
15017 {
15020 }
15024 }
15026 /* Expand an sse vector comparison. Return the register with the result. */
15028 static rtx
15031 {
15033 rtx x;
15048 }
15050 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15051 operations. This is used for both scalar and vector conditional moves. */
15053 static void
15055 {
15060 {
15064 }
15066 {
15071 }
15073 {
15076 op_true,
15077 op_false));
15079 }
15080 else
15081 {
15088 else
15100 }
15101 }
15103 /* Expand a floating-point conditional move. Return true if successful. */
15105 int
15107 {
15113 {
15116 /* Since we've no cmove for sse registers, don't force bad register
15117 allocation just to gain access to it. Deny movcc when the
15118 comparison mode doesn't match the move mode. */
15140 }
15142 /* The floating point conditional move instructions don't directly
15143 support conditions resulting from a signed integer comparison. */
15147 /* The floating point conditional move instructions don't directly
15148 support signed integer comparisons. */
15151 {
15159 }
15161 {
15165 }
15167 {
15171 }
15186 }
15188 /* Expand a floating-point vector conditional move; a vcond operation
15189 rather than a movcc operation. */
15191 bool
15193 {
15195 rtx cmp;
15210 }
15212 /* Expand a signed/unsigned integral vector conditional move. */
15214 bool
15216 {
15225 /* SSE5 supports all of the comparisons on all vector int types. */
15227 {
15228 /* Canonicalize the comparison to EQ, GT, GTU. */
15230 {
15247 /* FALLTHRU */
15257 }
15259 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15261 {
15263 {
15265 /* SSE4.1 supports EQ. */
15272 /* SSE4.2 supports GT/GTU. */
15279 }
15280 }
15282 /* Unsigned parallel compare is not supported by the hardware. Play some
15283 tricks to turn this into a signed comparison against 0. */
15285 {
15289 {
15292 {
15295 /* Perform a parallel modulo subtraction. */
15298 ? gen_subv4si3
15301 /* Extract the original sign bit of op0. */
15306 ? gen_andv4si3
15309 /* XOR it back into the result of the subtraction. This results
15310 in the sign bit set iff we saw unsigned underflow. */
15313 ? gen_xorv4si3
15317 }
15322 /* Perform a parallel unsigned saturating subtraction. */
15333 }
15337 }
15338 }
15346 }
15348 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15349 true if we should do zero extension, else sign extension. HIGH_P is
15350 true if we want the N/2 high elements, else the low elements. */
15352 void
15354 {
15360 {
15364 else
15370 else
15376 else
15381 }
15387 else
15392 }
15394 /* This function performs the same task as ix86_expand_sse_unpack,
15395 but with SSE4.1 instructions. */
15397 void
15399 {
15405 {
15409 else
15415 else
15421 else
15426 }
15430 {
15431 /* Shift higher 8 bytes to lower 8 bytes. */
15436 }
15437 else
15441 }
15443 /* This function performs the same task as ix86_expand_sse_unpack,
15444 but with sse5 instructions. */
15446 void
15448 {
15456 rtvec vs;
15461 {
15466 {
15469 ? PPERM_ZERO
15471 }
15483 else
15491 {
15493 ? PPERM_ZERO
15499 }
15511 else
15519 {
15521 ? PPERM_ZERO
15531 }
15543 else
15549 }
15552 }
15554 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15555 next narrower integer vector type */
15556 void
15558 {
15563 rtx x;
15569 {
15572 {
15575 }
15586 {
15591 }
15602 {
15611 }
15622 }
15625 }
15627 /* Expand conditional increment or decrement using adb/sbb instructions.
15628 The default case using setcc followed by the conditional move can be
15629 done by generic code. */
15630 int
15632 {
15634 rtx compare_op;
15649 {
15652 }
15655 {
15659 reverse_condition_maybe_unordered
15661 else
15663 }
15666 /* Construct either adc or sbb insn. */
15668 {
15670 {
15685 }
15686 }
15687 else
15688 {
15690 {
15705 }
15706 }
15708 }
15711 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15712 works for floating pointer parameters and nonoffsetable memories.
15713 For pushes, it returns just stack offsets; the values will be saved
15714 in the right order. Maximally three parts are generated. */
15716 static int
15718 {
15723 else
15729 /* Optimize constant pool reference to immediates. This is used by fp
15730 moves, that force all constants to memory to allow combining. */
15732 {
15736 }
15739 {
15740 /* The only non-offsetable memories we handle are pushes. */
15749 }
15752 {
15754 /* Caution: if we looked through a constant pool memory above,
15755 the operand may actually have a different mode now. That's
15756 ok, since we want to pun this all the way back to an integer. */
15760 }
15763 {
15766 else
15767 {
15771 {
15775 }
15777 {
15782 }
15784 {
15785 REAL_VALUE_TYPE r;
15790 {
15805 }
15808 }
15809 else
15811 }
15812 }
15813 else
15814 {
15818 {
15821 {
15825 }
15827 {
15831 }
15833 {
15834 REAL_VALUE_TYPE r;
15840 /* Do not use shift by 32 to avoid warning on 32bit systems. */
15843 = gen_int_mode
15846 DImode);
15847 else
15854 = gen_int_mode
15857 DImode);
15858 else
15860 }
15861 else
15863 }
15864 }
15867 }
15869 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
15870 Return false when normal moves are needed; true when all required
15871 insns have been emitted. Operands 2-4 contain the input values
15872 int the correct order; operands 5-7 contain the output values. */
15874 void
15876 {
15884 /* The DFmode expanders may ask us to move double.
15885 For 64bit target this is single move. By hiding the fact
15886 here we simplify i386.md splitters. */
15888 {
15889 /* Optimize constant pool reference to immediates. This is used by
15890 fp moves, that force all constants to memory to allow combining. */
15897 {
15900 }
15901 else
15906 }
15908 /* The only non-offsettable memory we handle is push. */
15911 else
15918 /* When emitting push, take care for source operands on the stack. */
15926 /* We need to do copy in the right order in case an address register
15927 of the source overlaps the destination. */
15929 {
15930 rtx tmp;
15933 {
15937 collisions++;
15938 }
15940 /* Collision in the middle part can be handled by reordering. */
15942 {
15945 }
15949 {
15951 {
15954 }
15955 else
15956 {
15959 }
15960 }
15962 /* If there are more collisions, we can't handle it by reordering.
15963 Do an lea to the last part and use only one colliding move. */
15965 {
15966 rtx base;
15972 /* Handle the case when the last part isn't valid for lea.
15973 Happens in 64-bit mode storing the 12-byte XFmode. */
15980 {
15983 }
15984 }
15985 }
15988 {
15990 {
15992 {
15996 }
15998 {
16001 }
16002 }
16003 else
16004 {
16005 /* In 64bit mode we don't have 32bit push available. In case this is
16006 register, it is OK - we will just use larger counterpart. We also
16007 retype memory - these comes from attempt to avoid REX prefix on
16008 moving of second half of TFmode value. */
16010 {
16012 {
16023 }
16027 }
16028 }
16032 }
16034 /* Choose correct order to not overwrite the source before it is copied. */
16044 {
16046 {
16049 }
16050 }
16051 else
16052 {
16054 {
16057 }
16058 }
16060 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16062 {
16071 }
16077 }
16079 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16080 left shift by a constant, either using a single shift or
16081 a sequence of add instructions. */
16083 static void
16085 {
16087 {
16089 ? gen_addsi3
16091 }
16094 {
16097 {
16099 ? gen_addsi3
16101 }
16102 }
16103 else
16105 ? gen_ashlsi3
16107 }
16109 void
16111 {
16117 {
16122 {
16128 }
16129 else
16130 {
16134 ? gen_x86_shld
16137 }
16139 }
16144 {
16145 /* Assuming we've chosen a QImode capable registers, then 1 << N
16146 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16148 {
16164 }
16166 /* Otherwise, we can get the same results by manually performing
16167 a bit extract operation on bit 5/6, and then performing the two
16168 shifts. The two methods of getting 0/1 into low/high are exactly
16169 the same size. Avoiding the shift in the bit extract case helps
16170 pentium4 a bit; no one else seems to care much either way. */
16171 else
16172 {
16173 rtx x;
16177 else
16182 ? gen_lshrsi3
16185 ? gen_andsi3
16189 ? gen_xorsi3
16191 }
16194 ? gen_ashlsi3
16197 ? gen_ashlsi3
16200 }
16203 {
16204 /* For -1 << N, we can avoid the shld instruction, because we
16205 know that we're shifting 0...31/63 ones into a -1. */
16209 else
16211 }
16212 else
16213 {
16219 ? gen_x86_shld
16221 }
16226 {
16229 ? gen_x86_shift_adj_1
16231 scratch));
16232 }
16233 else
16235 ? gen_x86_shift_adj_2
16237 }
16239 void
16241 {
16247 {
16252 {
16255 ? gen_ashrsi3
16260 }
16262 {
16266 ? gen_ashrsi3
16271 ? gen_ashrsi3
16274 }
16275 else
16276 {
16280 ? gen_x86_shrd
16283 ? gen_ashrsi3
16285 }
16286 }
16287 else
16288 {
16295 ? gen_x86_shrd
16298 ? gen_ashrsi3
16302 {
16305 ? gen_ashrsi3
16309 ? gen_x86_shift_adj_1
16311 scratch));
16312 }
16313 else
16315 ? gen_x86_shift_adj_3
16317 }
16318 }
16320 void
16322 {
16328 {
16333 {
16339 ? gen_lshrsi3
16342 }
16343 else
16344 {
16348 ? gen_x86_shrd
16351 ? gen_lshrsi3
16353 }
16354 }
16355 else
16356 {
16363 ? gen_x86_shrd
16366 ? gen_lshrsi3
16369 /* Heh. By reversing the arguments, we can reuse this pattern. */
16371 {
16374 ? gen_x86_shift_adj_1
16376 scratch));
16377 }
16378 else
16380 ? gen_x86_shift_adj_2
16382 }
16383 }
16385 /* Predict just emitted jump instruction to be taken with probability PROB. */
16386 static void
16388 {
16395 }
16397 /* Helper function for the string operations below. Dest VARIABLE whether
16398 it is aligned to VALUE bytes. If true, jump to the label. */
16399 static rtx
16401 {
16406 else
16412 else
16415 }
16417 /* Adjust COUNTER by the VALUE. */
16418 static void
16420 {
16423 else
16425 }
16427 /* Zero extend possibly SImode EXP to Pmode register. */
16428 rtx
16430 {
16431 rtx r;
16439 }
16441 /* Divide COUNTREG by SCALE. */
16442 static rtx
16444 {
16445 rtx sc;
16446 rtx piece_size_mask;
16459 }
16461 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16462 DImode for constant loop counts. */
16464 static enum machine_mode
16466 {
16474 }
16476 /* When SRCPTR is non-NULL, output simple loop to move memory
16477 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16478 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16479 equivalent loop to set memory by VALUE (supposed to be in MODE).
16481 The size is rounded down to whole number of chunk size moved at once.
16482 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16485 static void
16490 {
16495 rtx size;
16496 rtx x_addr;
16497 rtx y_addr;
16506 /* Those two should combine. */
16508 {
16512 }
16522 {
16526 /* When unrolling for chips that reorder memory reads and writes,
16527 we can save registers by using single temporary.
16528 Also using 4 temporaries is overkill in 32bit mode. */
16530 {
16532 {
16534 {
16535 destmem =
16537 srcmem =
16539 }
16541 }
16542 }
16543 else
16544 {
16548 {
16551 {
16552 srcmem =
16554 }
16556 }
16558 {
16560 {
16561 destmem =
16563 }
16565 }
16566 }
16567 }
16568 else
16570 {
16572 destmem =
16575 }
16585 {
16591 else
16593 }
16594 else
16602 {
16607 }
16609 }
16611 /* Output "rep; mov" instruction.
16612 Arguments have same meaning as for previous function */
16613 static void
16616 rtx count,
16618 {
16619 rtx destexp;
16620 rtx srcexp;
16621 rtx countreg;
16623 /* If the size is known, it is shorter to use rep movs. */
16634 {
16641 }
16642 else
16643 {
16646 }
16649 }
16651 /* Output "rep; stos" instruction.
16652 Arguments have same meaning as for previous function */
16653 static void
16655 rtx count,
16657 {
16658 rtx destexp;
16659 rtx countreg;
16666 {
16670 }
16671 else
16674 }
16676 static void
16679 {
16683 }
16685 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16686 static void
16689 {
16692 {
16697 {
16699 {
16702 }
16703 else
16706 }
16708 {
16711 else
16712 {
16715 }
16717 }
16719 {
16722 }
16724 {
16727 }
16729 {
16732 }
16734 }
16736 {
16742 }
16744 /* When there are stringops, we can cheaply increase dest and src pointers.
16745 Otherwise we save code size by maintaining offset (zero is readily
16746 available from preceding rep operation) and using x86 addressing modes.
16747 */
16749 {
16751 {
16758 }
16760 {
16767 }
16769 {
16776 }
16777 }
16778 else
16779 {
16781 rtx tmp;
16784 {
16795 }
16797 {
16810 }
16812 {
16821 }
16822 }
16823 }
16825 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16826 static void
16829 {
16830 count =
16836 }
16838 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16839 static void
16841 {
16842 rtx dest;
16845 {
16850 {
16852 {
16857 }
16858 else
16861 }
16863 {
16865 {
16868 }
16869 else
16870 {
16875 }
16877 }
16879 {
16883 }
16885 {
16889 }
16891 {
16895 }
16897 }
16899 {
16902 }
16904 {
16907 {
16911 }
16912 else
16913 {
16919 }
16922 }
16924 {
16927 {
16930 }
16931 else
16932 {
16936 }
16939 }
16941 {
16947 }
16949 {
16955 }
16957 {
16963 }
16964 }
16966 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
16967 DESIRED_ALIGNMENT. */
16968 static void
16972 {
16974 {
16982 }
16984 {
16992 }
16994 {
17002 }
17004 }
17006 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17007 DESIRED_ALIGNMENT. */
17008 static void
17011 {
17013 {
17020 }
17022 {
17029 }
17031 {
17038 }
17040 }
17042 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17043 static enum stringop_alg
17046 {
17049 /* Algorithms using the rep prefix want at least edi and ecx;
17050 additionally, memset wants eax and memcpy wants esi. Don't
17051 consider such algorithms if the user has appropriated those
17052 registers for their own purposes. */
17054 || (memset
17057 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17058 || (alg != rep_prefix_1_byte \
17059 && alg != rep_prefix_4_byte \
17060 && alg != rep_prefix_8_byte))
17063 /* Even if the string operation call is cold, we still might spend a lot
17064 of time processing large blocks. */
17069 else
17077 else
17081 /* rep; movq or rep; movl is the smallest variant. */
17083 {
17086 else
17088 }
17089 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17090 */
17094 {
17098 {
17099 /* We get here if the algorithms that were not libcall-based
17100 were rep-prefix based and we are unable to use rep prefixes
17101 based on global register usage. Break out of the loop and
17102 use the heuristic below. */
17106 {
17111 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17112 last non-libcall inline algorithm. */
17114 {
17115 /* When the current size is best to be copied by a libcall,
17116 but we are still forced to inline, run the heuristic below
17117 that will pick code for medium sized blocks. */
17121 }
17124 }
17125 }
17127 }
17128 /* When asked to inline the call anyway, try to pick meaningful choice.
17129 We look for maximal size of block that is faster to copy by hand and
17130 take blocks of at most of that size guessing that average size will
17131 be roughly half of the block.
17133 If this turns out to be bad, we might simply specify the preferred
17134 choice in ix86_costs. */
17137 {
17144 {
17151 }
17152 /* If there aren't any usable algorithms, then recursing on
17153 smaller sizes isn't going to find anything. Just return the
17154 simple byte-at-a-time copy loop. */
17156 {
17157 /* Pick something reasonable. */
17161 }
17170 }
17172 #undef ALG_USABLE_P
17173 }
17175 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17176 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17177 static int
17181 {
17184 {
17195 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17196 copying whole cacheline at once. */
17199 else
17203 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17204 copying whole cacheline at once. */
17207 else
17215 }
17224 }
17226 /* Return the smallest power of 2 greater than VAL. */
17227 static int
17229 {
17234 }
17236 /* Expand string move (memcpy) operation. Use i386 string operations when
17237 profitable. expand_setmem contains similar code. The code depends upon
17238 architecture, block size and alignment, but always has the same
17239 overall structure:
17241 1) Prologue guard: Conditional that jumps up to epilogues for small
17242 blocks that can be handled by epilogue alone. This is faster but
17243 also needed for correctness, since prologue assume the block is larger
17244 than the desired alignment.
17246 Optional dynamic check for size and libcall for large
17247 blocks is emitted here too, with -minline-stringops-dynamically.
17249 2) Prologue: copy first few bytes in order to get destination aligned
17250 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17251 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17252 We emit either a jump tree on power of two sized blocks, or a byte loop.
17254 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17255 with specified algorithm.
17257 4) Epilogue: code copying tail of the block that is too small to be
17258 handled by main body (or up to size guarded by prologue guard). */
17260 int
17263 {
17264 rtx destreg;
17265 rtx srcreg;
17267 rtx tmp;
17280 /* i386 can do misaligned access on reasonably increased cost. */
17289 /* Make sure we don't need to care about overflow later on. */
17293 /* Step 0: Decide on preferred algorithm, desired alignment and
17294 size of chunks to be copied by main loop. */
17310 {
17335 }
17339 /* Step 1: Prologue guard. */
17341 /* Alignment code needs count to be in register. */
17346 /* Ensure that alignment prologue won't copy past end of block. */
17348 {
17350 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17351 Make sure it is power of 2. */
17355 {
17358 }
17359 else
17360 {
17367 else
17369 }
17370 }
17372 /* Emit code to decide on runtime whether library call or inline should be
17373 used. */
17375 {
17377 {
17379 {
17383 }
17384 }
17385 else
17386 {
17395 }
17396 }
17398 /* Step 2: Alignment prologue. */
17401 {
17402 /* Except for the first move in epilogue, we no longer know
17403 constant offset in aliasing info. It don't seems to worth
17404 the pain to maintain it for the first move, so throw away
17405 the info early. */
17409 desired_align);
17411 {
17412 /* It is possible that we copied enough so the main loop will not
17413 execute. */
17420 else
17422 }
17423 }
17425 {
17429 }
17431 /* Step 3: Main loop. */
17434 {
17447 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17448 registers for 4 temporaries anyway. */
17451 expected_size);
17455 DImode);
17459 SImode);
17463 QImode);
17465 }
17466 /* Adjust properly the offset of src and dest memory for aliasing. */
17468 {
17473 }
17474 else
17475 {
17478 }
17480 /* Step 4: Epilogue to copy the remaining bytes. */
17481 epilogue:
17483 {
17484 /* When the main loop is done, COUNT_EXP might hold original count,
17485 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17486 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17487 bytes. Compensate if needed. */
17490 {
17491 tmp =
17494 OPTAB_DIRECT);
17497 }
17500 }
17504 epilogue_size_needed);
17508 }
17510 /* Helper function for memcpy. For QImode value 0xXY produce
17511 0xXYXYXYXY of wide specified by MODE. This is essentially
17512 a * 0x10101010, but we can do slightly better than
17513 synth_mult by unwinding the sequence by hand on CPUs with
17514 slow multiply. */
17515 static rtx
17517 {
17519 rtx tmp;
17526 {
17534 }
17543 nops--;
17548 {
17552 OPTAB_DIRECT);
17553 }
17554 else
17555 {
17561 else
17563 else
17564 {
17567 reg =
17569 }
17579 }
17580 }
17582 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
17583 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
17584 alignment from ALIGN to DESIRED_ALIGN. */
17585 static rtx
17587 {
17588 rtx promoted_val;
17597 else
17601 }
17603 /* Expand string clear operation (bzero). Use i386 string operations when
17604 profitable. See expand_movmem comment for explanation of individual
17605 steps performed. */
17606 int
17609 {
17610 rtx destreg;
17612 rtx tmp;
17627 /* i386 can do misaligned access on reasonably increased cost. */
17636 /* Make sure we don't need to care about overflow later on. */
17640 /* Step 0: Decide on preferred algorithm, desired alignment and
17641 size of chunks to be copied by main loop. */
17656 {
17681 }
17684 /* Step 1: Prologue guard. */
17686 /* Alignment code needs count to be in register. */
17688 {
17693 }
17694 /* Do the cheap promotion to allow better CSE across the
17695 main loop and epilogue (ie one load of the big constant in the
17696 front of all code. */
17700 /* Ensure that alignment prologue won't copy past end of block. */
17702 {
17704 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17705 Make sure it is power of 2. */
17708 /* To improve performance of small blocks, we jump around the VAL
17709 promoting mode. This mean that if the promoted VAL is not constant,
17710 we might not use it in the epilogue and have to use byte
17711 loop variant. */
17719 ;
17722 else
17724 }
17726 {
17735 }
17737 /* Step 2: Alignment prologue. */
17739 /* Do the expensive promotion once we branched off the small blocks. */
17746 {
17747 /* Except for the first move in epilogue, we no longer know
17748 constant offset in aliasing info. It don't seems to worth
17749 the pain to maintain it for the first move, so throw away
17750 the info early. */
17753 desired_align);
17755 {
17756 /* It is possible that we copied enough so the main loop will not
17757 execute. */
17764 else
17766 }
17767 }
17769 {
17773 }
17775 /* Step 3: Main loop. */
17778 {
17796 DImode);
17800 SImode);
17804 QImode);
17806 }
17807 /* Adjust properly the offset of src and dest memory for aliasing. */
17811 else
17814 /* Step 4: Epilogue to copy the remaining bytes. */
17817 {
17818 /* When the main loop is done, COUNT_EXP might hold original count,
17819 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17820 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17821 bytes. Compensate if needed. */
17824 {
17825 tmp =
17828 OPTAB_DIRECT);
17832 }
17835 }
17837 {
17840 size_needed);
17841 else
17843 size_needed);
17844 }
17848 }
17850 /* Expand the appropriate insns for doing strlen if not just doing
17851 repnz; scasb
17853 out = result, initialized with the start address
17854 align_rtx = alignment of the address.
17855 scratch = scratch register, initialized with the startaddress when
17856 not aligned, otherwise undefined
17858 This is just the body. It needs the initializations mentioned above and
17859 some address computing at the end. These things are done in i386.md. */
17861 static void
17863 {
17865 rtx tmp;
17870 rtx mem;
17873 rtx cmp;
17879 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
17881 /* Is there a known alignment and is it less than 4? */
17883 {
17886 /* Is there a known alignment and is it not 2? */
17888 {
17892 /* Leave just the 3 lower bits. */
17902 }
17903 else
17904 {
17905 /* Since the alignment is 2, we have to check 2 or 0 bytes;
17906 check if is aligned to 4 - byte. */
17913 }
17917 /* Now compare the bytes. */
17919 /* Compare the first n unaligned byte on a byte per byte basis. */
17923 /* Increment the address. */
17926 /* Not needed with an alignment of 2 */
17928 {
17932 end_0_label);
17937 }
17940 end_0_label);
17943 }
17945 /* Generate loop to check 4 bytes at a time. It is not a good idea to
17946 align this loop. It gives only huge programs, but does not help to
17947 speed up. */
17954 /* This formula yields a nonzero result iff one of the bytes is zero.
17955 This saves three branches inside loop and many cycles. */
17963 align_4_label);
17966 {
17972 /* If zero is not in the first two bytes, move two bytes forward. */
17978 reg,
17979 tmpreg)));
17980 /* Emit lea manually to avoid clobbering of flags. */
17988 reg2,
17989 out)));
17991 }
17992 else
17993 {
17995 /* Is zero in the first two bytes? */
18002 pc_rtx);
18006 /* Not in the first two. Move two bytes forward. */
18012 }
18014 /* Avoid branch in fixing the byte. */
18021 }
18023 /* Expand strlen. */
18025 int
18027 {
18030 /* The generic case of strlen expander is long. Avoid it's
18031 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18034 && !TARGET_INLINE_ALL_STRINGOPS
18044 {
18045 /* Well it seems that some optimizer does not combine a call like
18046 foo(strlen(bar), strlen(bar));
18047 when the move and the subtraction is done here. It does calculate
18048 the length just once when these instructions are done inside of
18049 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18050 often used and I use one fewer register for the lifetime of
18051 output_strlen_unroll() this is better. */
18057 /* strlensi_unroll_1 returns the address of the zero at the end of
18058 the string, like memchr(), so compute the length by subtracting
18059 the start address. */
18061 }
18062 else
18063 {
18064 rtx unspec;
18066 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18079 /* If .md starts supporting :P, this can be done in .md. */
18085 }
18087 }
18089 /* For given symbol (function) construct code to compute address of it's PLT
18090 entry in large x86-64 PIC model. */
18091 rtx
18093 {
18103 }
18105 void
18107 rtx callarg2 ATTRIBUTE_UNUSED,
18109 {
18117 {
18118 #if TARGET_MACHO
18121 #endif
18122 }
18123 else
18124 {
18125 /* Static functions and indirect calls don't need the pic register. */
18130 }
18133 {
18137 }
18145 {
18148 }
18151 {
18152 rtx addr;
18157 }
18163 {
18167 }
18172 }
18174 \f
18175 /* Clear stack slot assignments remembered from previous functions.
18176 This is called from INIT_EXPANDERS once before RTL is emitted for each
18177 function. */
18181 {
18190 }
18192 /* Return a MEM corresponding to a stack slot with mode MODE.
18193 Allocate a new slot if necessary.
18195 The RTL for a function can have several slots available: N is
18196 which slot to use. */
18198 rtx
18200 {
18205 /* Virtual slot is valid only before vregs are instantiated. */
18221 }
18223 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18226 rtx
18228 {
18231 {
18233 (TARGET_ANY_GNU_TLS
18237 }
18240 }
18242 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18245 rtx
18247 {
18250 {
18255 }
18258 }
18259 \f
18260 /* Calculate the length of the memory address in the instruction
18261 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18263 int
18265 {
18290 /* Rule of thumb:
18291 - esp as the base always wants an index,
18292 - ebp as the base always wants a displacement. */
18294 /* Register Indirect. */
18296 {
18297 /* esp (for its index) and ebp (for its displacement) need
18298 the two-byte modrm form. */
18304 }
18306 /* Direct Addressing. */
18310 else
18311 {
18312 /* Find the length of the displacement constant. */
18314 {
18317 else
18319 }
18320 /* ebp always wants a displacement. */
18324 /* An index requires the two-byte modrm form.... */
18326 /* ...like esp, which always wants an index. */
18331 }
18334 }
18336 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18337 is set, expect that insn have 8bit immediate alternative. */
18338 int
18340 {
18346 {
18350 else
18351 {
18353 {
18363 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18369 }
18370 }
18371 }
18373 }
18374 /* Compute default value for "length_address" attribute. */
18375 int
18377 {
18381 {
18390 }
18395 {
18398 }
18400 }
18402 /* Compute default value for "length_vex" attribute. It includes
18403 2 or 3 byte VEX prefix and 1 opcode byte. */
18405 int
18408 {
18411 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18412 byte VEX prefix. */
18416 /* We can always use 2 byte VEX prefix in 32bit. */
18424 {
18425 /* REX.W bit uses 3 byte VEX prefix. */
18428 }
18429 else
18430 {
18431 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18435 }
18438 }
18439 \f
18440 /* Return the maximum number of instructions a cpu can issue. */
18442 static int
18444 {
18446 {
18466 }
18467 }
18469 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
18470 by DEP_INSN and nothing set by DEP_INSN. */
18472 static int
18474 {
18477 /* Simplify the test for uninteresting insns. */
18485 {
18488 }
18493 {
18496 }
18497 else
18503 /* This test is true if the dependent insn reads the flags but
18504 not any other potentially set register. */
18512 }
18514 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
18515 address with operands set by DEP_INSN. */
18517 static int
18519 {
18520 rtx addr;
18524 {
18533 }
18534 else
18535 {
18540 {
18543 }
18545 found:;
18546 }
18549 }
18551 static int
18553 {
18559 /* Anti and output dependencies have zero cost on all CPUs. */
18565 /* If we can't recognize the insns, we can't really do anything. */
18573 {
18575 /* Address Generation Interlock adds a cycle of latency. */
18579 /* ??? Compares pair with jump/setcc. */
18583 /* Floating point stores require value to be ready one cycle earlier. */
18593 /* INT->FP conversion is expensive. */
18597 /* There is one cycle extra latency between an FP op and a store. */
18605 /* Show ability of reorder buffer to hide latency of load by executing
18606 in parallel with previous instruction in case
18607 previous instruction is not needed to compute the address. */
18610 {
18611 /* Claim moves to take one cycle, as core can issue one load
18612 at time and the next load can start cycle later. */
18617 cost--;
18618 }
18624 /* The esp dependency is resolved before the instruction is really
18625 finished. */
18630 /* INT->FP conversion is expensive. */
18634 /* Show ability of reorder buffer to hide latency of load by executing
18635 in parallel with previous instruction in case
18636 previous instruction is not needed to compute the address. */
18639 {
18640 /* Claim moves to take one cycle, as core can issue one load
18641 at time and the next load can start cycle later. */
18647 else
18649 }
18659 /* Show ability of reorder buffer to hide latency of load by executing
18660 in parallel with previous instruction in case
18661 previous instruction is not needed to compute the address. */
18664 {
18668 /* Because of the difference between the length of integer and
18669 floating unit pipeline preparation stages, the memory operands
18670 for floating point are cheaper.
18672 ??? For Athlon it the difference is most probably 2. */
18675 else
18680 else
18682 }
18686 }
18689 }
18691 /* How many alternative schedules to try. This should be as wide as the
18692 scheduling freedom in the DFA, but no wider. Making this value too
18693 large results extra work for the scheduler. */
18695 static int
18697 {
18699 {
18709 }
18710 }
18712 \f
18713 /* Compute the alignment given to a constant that is being placed in memory.
18714 EXP is the constant and ALIGN is the alignment that the object would
18715 ordinarily have.
18716 The value of this function is used instead of that alignment to align
18717 the object. */
18719 int
18721 {
18724 {
18729 }
18735 }
18737 /* Compute the alignment for a static variable.
18738 TYPE is the data type, and ALIGN is the alignment that
18739 the object would ordinarily have. The value of this function is used
18740 instead of that alignment to align the object. */
18742 int
18744 {
18755 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18756 to 16byte boundary. */
18758 {
18765 }
18768 {
18773 }
18775 {
18782 }
18787 {
18792 }
18795 {
18800 }
18803 }
18805 /* Compute the alignment for a local variable or a stack slot. TYPE is
18806 the data type, MODE is the widest mode available and ALIGN is the
18807 alignment that the object would ordinarily have. The value of this
18808 macro is used instead of that alignment to align the object. */
18810 unsigned int
18813 {
18814 /* If TYPE is NULL, we are allocating a stack slot for caller-save
18815 register in MODE. We will return the largest alignment of XF
18816 and DF. */
18818 {
18822 }
18824 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18825 to 16byte boundary. */
18827 {
18834 }
18836 {
18841 }
18843 {
18849 }
18854 {
18859 }
18862 {
18868 }
18870 }
18871 \f
18872 /* Emit RTL insns to initialize the variable parts of a trampoline.
18873 FNADDR is an RTX for the address of the function's pure code.
18874 CXT is an RTX for the static chain value for the function. */
18875 void
18877 {
18879 {
18880 /* Compute offset from the end of the jmp to the target function. */
18890 }
18891 else
18892 {
18894 /* Try to load address using shorter movl instead of movabs.
18895 We may want to support movq for kernel mode, but kernel does not use
18896 trampolines at the moment. */
18898 {
18905 }
18906 else
18907 {
18911 fnaddr);
18913 }
18914 /* Load static chain using movabs to r10. */
18918 cxt);
18920 /* Jump to the r11 */
18927 }
18929 #ifdef ENABLE_EXECUTE_STACK
18932 #endif
18933 }
18934 \f
18935 /* Codes for all the SSE/MMX builtins. */
18936 enum ix86_builtins
18937 {
18938 IX86_BUILTIN_ADDPS,
18939 IX86_BUILTIN_ADDSS,
18940 IX86_BUILTIN_DIVPS,
18941 IX86_BUILTIN_DIVSS,
18942 IX86_BUILTIN_MULPS,
18943 IX86_BUILTIN_MULSS,
18944 IX86_BUILTIN_SUBPS,
18945 IX86_BUILTIN_SUBSS,
18947 IX86_BUILTIN_CMPEQPS,
18948 IX86_BUILTIN_CMPLTPS,
18949 IX86_BUILTIN_CMPLEPS,
18950 IX86_BUILTIN_CMPGTPS,
18951 IX86_BUILTIN_CMPGEPS,
18952 IX86_BUILTIN_CMPNEQPS,
18953 IX86_BUILTIN_CMPNLTPS,
18954 IX86_BUILTIN_CMPNLEPS,
18955 IX86_BUILTIN_CMPNGTPS,
18956 IX86_BUILTIN_CMPNGEPS,
18957 IX86_BUILTIN_CMPORDPS,
18958 IX86_BUILTIN_CMPUNORDPS,
18959 IX86_BUILTIN_CMPEQSS,
18960 IX86_BUILTIN_CMPLTSS,
18961 IX86_BUILTIN_CMPLESS,
18962 IX86_BUILTIN_CMPNEQSS,
18963 IX86_BUILTIN_CMPNLTSS,
18964 IX86_BUILTIN_CMPNLESS,
18965 IX86_BUILTIN_CMPNGTSS,
18966 IX86_BUILTIN_CMPNGESS,
18967 IX86_BUILTIN_CMPORDSS,
18968 IX86_BUILTIN_CMPUNORDSS,
18970 IX86_BUILTIN_COMIEQSS,
18971 IX86_BUILTIN_COMILTSS,
18972 IX86_BUILTIN_COMILESS,
18973 IX86_BUILTIN_COMIGTSS,
18974 IX86_BUILTIN_COMIGESS,
18975 IX86_BUILTIN_COMINEQSS,
18976 IX86_BUILTIN_UCOMIEQSS,
18977 IX86_BUILTIN_UCOMILTSS,
18978 IX86_BUILTIN_UCOMILESS,
18979 IX86_BUILTIN_UCOMIGTSS,
18980 IX86_BUILTIN_UCOMIGESS,
18981 IX86_BUILTIN_UCOMINEQSS,
18983 IX86_BUILTIN_CVTPI2PS,
18984 IX86_BUILTIN_CVTPS2PI,
18985 IX86_BUILTIN_CVTSI2SS,
18986 IX86_BUILTIN_CVTSI642SS,
18987 IX86_BUILTIN_CVTSS2SI,
18988 IX86_BUILTIN_CVTSS2SI64,
18989 IX86_BUILTIN_CVTTPS2PI,
18990 IX86_BUILTIN_CVTTSS2SI,
18991 IX86_BUILTIN_CVTTSS2SI64,
18993 IX86_BUILTIN_MAXPS,
18994 IX86_BUILTIN_MAXSS,
18995 IX86_BUILTIN_MINPS,
18996 IX86_BUILTIN_MINSS,
18998 IX86_BUILTIN_LOADUPS,
18999 IX86_BUILTIN_STOREUPS,
19000 IX86_BUILTIN_MOVSS,
19002 IX86_BUILTIN_MOVHLPS,
19003 IX86_BUILTIN_MOVLHPS,
19004 IX86_BUILTIN_LOADHPS,
19005 IX86_BUILTIN_LOADLPS,
19006 IX86_BUILTIN_STOREHPS,
19007 IX86_BUILTIN_STORELPS,
19009 IX86_BUILTIN_MASKMOVQ,
19010 IX86_BUILTIN_MOVMSKPS,
19011 IX86_BUILTIN_PMOVMSKB,
19013 IX86_BUILTIN_MOVNTPS,
19014 IX86_BUILTIN_MOVNTQ,
19016 IX86_BUILTIN_LOADDQU,
19017 IX86_BUILTIN_STOREDQU,
19019 IX86_BUILTIN_PACKSSWB,
19020 IX86_BUILTIN_PACKSSDW,
19021 IX86_BUILTIN_PACKUSWB,
19023 IX86_BUILTIN_PADDB,
19024 IX86_BUILTIN_PADDW,
19025 IX86_BUILTIN_PADDD,
19026 IX86_BUILTIN_PADDQ,
19027 IX86_BUILTIN_PADDSB,
19028 IX86_BUILTIN_PADDSW,
19029 IX86_BUILTIN_PADDUSB,
19030 IX86_BUILTIN_PADDUSW,
19031 IX86_BUILTIN_PSUBB,
19032 IX86_BUILTIN_PSUBW,
19033 IX86_BUILTIN_PSUBD,
19034 IX86_BUILTIN_PSUBQ,
19035 IX86_BUILTIN_PSUBSB,
19036 IX86_BUILTIN_PSUBSW,
19037 IX86_BUILTIN_PSUBUSB,
19038 IX86_BUILTIN_PSUBUSW,
19040 IX86_BUILTIN_PAND,
19041 IX86_BUILTIN_PANDN,
19042 IX86_BUILTIN_POR,
19043 IX86_BUILTIN_PXOR,
19045 IX86_BUILTIN_PAVGB,
19046 IX86_BUILTIN_PAVGW,
19048 IX86_BUILTIN_PCMPEQB,
19049 IX86_BUILTIN_PCMPEQW,
19050 IX86_BUILTIN_PCMPEQD,
19051 IX86_BUILTIN_PCMPGTB,
19052 IX86_BUILTIN_PCMPGTW,
19053 IX86_BUILTIN_PCMPGTD,
19055 IX86_BUILTIN_PMADDWD,
19057 IX86_BUILTIN_PMAXSW,
19058 IX86_BUILTIN_PMAXUB,
19059 IX86_BUILTIN_PMINSW,
19060 IX86_BUILTIN_PMINUB,
19062 IX86_BUILTIN_PMULHUW,
19063 IX86_BUILTIN_PMULHW,
19064 IX86_BUILTIN_PMULLW,
19066 IX86_BUILTIN_PSADBW,
19067 IX86_BUILTIN_PSHUFW,
19069 IX86_BUILTIN_PSLLW,
19070 IX86_BUILTIN_PSLLD,
19071 IX86_BUILTIN_PSLLQ,
19072 IX86_BUILTIN_PSRAW,
19073 IX86_BUILTIN_PSRAD,
19074 IX86_BUILTIN_PSRLW,
19075 IX86_BUILTIN_PSRLD,
19076 IX86_BUILTIN_PSRLQ,
19077 IX86_BUILTIN_PSLLWI,
19078 IX86_BUILTIN_PSLLDI,
19079 IX86_BUILTIN_PSLLQI,
19080 IX86_BUILTIN_PSRAWI,
19081 IX86_BUILTIN_PSRADI,
19082 IX86_BUILTIN_PSRLWI,
19083 IX86_BUILTIN_PSRLDI,
19084 IX86_BUILTIN_PSRLQI,
19086 IX86_BUILTIN_PUNPCKHBW,
19087 IX86_BUILTIN_PUNPCKHWD,
19088 IX86_BUILTIN_PUNPCKHDQ,
19089 IX86_BUILTIN_PUNPCKLBW,
19090 IX86_BUILTIN_PUNPCKLWD,
19091 IX86_BUILTIN_PUNPCKLDQ,
19093 IX86_BUILTIN_SHUFPS,
19095 IX86_BUILTIN_RCPPS,
19096 IX86_BUILTIN_RCPSS,
19097 IX86_BUILTIN_RSQRTPS,
19098 IX86_BUILTIN_RSQRTPS_NR,
19099 IX86_BUILTIN_RSQRTSS,
19100 IX86_BUILTIN_RSQRTF,
19101 IX86_BUILTIN_SQRTPS,
19102 IX86_BUILTIN_SQRTPS_NR,
19103 IX86_BUILTIN_SQRTSS,
19105 IX86_BUILTIN_UNPCKHPS,
19106 IX86_BUILTIN_UNPCKLPS,
19108 IX86_BUILTIN_ANDPS,
19109 IX86_BUILTIN_ANDNPS,
19110 IX86_BUILTIN_ORPS,
19111 IX86_BUILTIN_XORPS,
19113 IX86_BUILTIN_EMMS,
19114 IX86_BUILTIN_LDMXCSR,
19115 IX86_BUILTIN_STMXCSR,
19116 IX86_BUILTIN_SFENCE,
19118 /* 3DNow! Original */
19119 IX86_BUILTIN_FEMMS,
19120 IX86_BUILTIN_PAVGUSB,
19121 IX86_BUILTIN_PF2ID,
19122 IX86_BUILTIN_PFACC,
19123 IX86_BUILTIN_PFADD,
19124 IX86_BUILTIN_PFCMPEQ,
19125 IX86_BUILTIN_PFCMPGE,
19126 IX86_BUILTIN_PFCMPGT,
19127 IX86_BUILTIN_PFMAX,
19128 IX86_BUILTIN_PFMIN,
19129 IX86_BUILTIN_PFMUL,
19130 IX86_BUILTIN_PFRCP,
19131 IX86_BUILTIN_PFRCPIT1,
19132 IX86_BUILTIN_PFRCPIT2,
19133 IX86_BUILTIN_PFRSQIT1,
19134 IX86_BUILTIN_PFRSQRT,
19135 IX86_BUILTIN_PFSUB,
19136 IX86_BUILTIN_PFSUBR,
19137 IX86_BUILTIN_PI2FD,
19138 IX86_BUILTIN_PMULHRW,
19140 /* 3DNow! Athlon Extensions */
19141 IX86_BUILTIN_PF2IW,
19142 IX86_BUILTIN_PFNACC,
19143 IX86_BUILTIN_PFPNACC,
19144 IX86_BUILTIN_PI2FW,
19145 IX86_BUILTIN_PSWAPDSI,
19146 IX86_BUILTIN_PSWAPDSF,
19148 /* SSE2 */
19149 IX86_BUILTIN_ADDPD,
19150 IX86_BUILTIN_ADDSD,
19151 IX86_BUILTIN_DIVPD,
19152 IX86_BUILTIN_DIVSD,
19153 IX86_BUILTIN_MULPD,
19154 IX86_BUILTIN_MULSD,
19155 IX86_BUILTIN_SUBPD,
19156 IX86_BUILTIN_SUBSD,
19158 IX86_BUILTIN_CMPEQPD,
19159 IX86_BUILTIN_CMPLTPD,
19160 IX86_BUILTIN_CMPLEPD,
19161 IX86_BUILTIN_CMPGTPD,
19162 IX86_BUILTIN_CMPGEPD,
19163 IX86_BUILTIN_CMPNEQPD,
19164 IX86_BUILTIN_CMPNLTPD,
19165 IX86_BUILTIN_CMPNLEPD,
19166 IX86_BUILTIN_CMPNGTPD,
19167 IX86_BUILTIN_CMPNGEPD,
19168 IX86_BUILTIN_CMPORDPD,
19169 IX86_BUILTIN_CMPUNORDPD,
19170 IX86_BUILTIN_CMPEQSD,
19171 IX86_BUILTIN_CMPLTSD,
19172 IX86_BUILTIN_CMPLESD,
19173 IX86_BUILTIN_CMPNEQSD,
19174 IX86_BUILTIN_CMPNLTSD,
19175 IX86_BUILTIN_CMPNLESD,
19176 IX86_BUILTIN_CMPORDSD,
19177 IX86_BUILTIN_CMPUNORDSD,
19179 IX86_BUILTIN_COMIEQSD,
19180 IX86_BUILTIN_COMILTSD,
19181 IX86_BUILTIN_COMILESD,
19182 IX86_BUILTIN_COMIGTSD,
19183 IX86_BUILTIN_COMIGESD,
19184 IX86_BUILTIN_COMINEQSD,
19185 IX86_BUILTIN_UCOMIEQSD,
19186 IX86_BUILTIN_UCOMILTSD,
19187 IX86_BUILTIN_UCOMILESD,
19188 IX86_BUILTIN_UCOMIGTSD,
19189 IX86_BUILTIN_UCOMIGESD,
19190 IX86_BUILTIN_UCOMINEQSD,
19192 IX86_BUILTIN_MAXPD,
19193 IX86_BUILTIN_MAXSD,
19194 IX86_BUILTIN_MINPD,
19195 IX86_BUILTIN_MINSD,
19197 IX86_BUILTIN_ANDPD,
19198 IX86_BUILTIN_ANDNPD,
19199 IX86_BUILTIN_ORPD,
19200 IX86_BUILTIN_XORPD,
19202 IX86_BUILTIN_SQRTPD,
19203 IX86_BUILTIN_SQRTSD,
19205 IX86_BUILTIN_UNPCKHPD,
19206 IX86_BUILTIN_UNPCKLPD,
19208 IX86_BUILTIN_SHUFPD,
19210 IX86_BUILTIN_LOADUPD,
19211 IX86_BUILTIN_STOREUPD,
19212 IX86_BUILTIN_MOVSD,
19214 IX86_BUILTIN_LOADHPD,
19215 IX86_BUILTIN_LOADLPD,
19217 IX86_BUILTIN_CVTDQ2PD,
19218 IX86_BUILTIN_CVTDQ2PS,
19220 IX86_BUILTIN_CVTPD2DQ,
19221 IX86_BUILTIN_CVTPD2PI,
19222 IX86_BUILTIN_CVTPD2PS,
19223 IX86_BUILTIN_CVTTPD2DQ,
19224 IX86_BUILTIN_CVTTPD2PI,
19226 IX86_BUILTIN_CVTPI2PD,
19227 IX86_BUILTIN_CVTSI2SD,
19228 IX86_BUILTIN_CVTSI642SD,
19230 IX86_BUILTIN_CVTSD2SI,
19231 IX86_BUILTIN_CVTSD2SI64,
19232 IX86_BUILTIN_CVTSD2SS,
19233 IX86_BUILTIN_CVTSS2SD,
19234 IX86_BUILTIN_CVTTSD2SI,
19235 IX86_BUILTIN_CVTTSD2SI64,
19237 IX86_BUILTIN_CVTPS2DQ,
19238 IX86_BUILTIN_CVTPS2PD,
19239 IX86_BUILTIN_CVTTPS2DQ,
19241 IX86_BUILTIN_MOVNTI,
19242 IX86_BUILTIN_MOVNTPD,
19243 IX86_BUILTIN_MOVNTDQ,
19245 IX86_BUILTIN_MOVQ128,
19247 /* SSE2 MMX */
19248 IX86_BUILTIN_MASKMOVDQU,
19249 IX86_BUILTIN_MOVMSKPD,
19250 IX86_BUILTIN_PMOVMSKB128,
19252 IX86_BUILTIN_PACKSSWB128,
19253 IX86_BUILTIN_PACKSSDW128,
19254 IX86_BUILTIN_PACKUSWB128,
19256 IX86_BUILTIN_PADDB128,
19257 IX86_BUILTIN_PADDW128,
19258 IX86_BUILTIN_PADDD128,
19259 IX86_BUILTIN_PADDQ128,
19260 IX86_BUILTIN_PADDSB128,
19261 IX86_BUILTIN_PADDSW128,
19262 IX86_BUILTIN_PADDUSB128,
19263 IX86_BUILTIN_PADDUSW128,
19264 IX86_BUILTIN_PSUBB128,
19265 IX86_BUILTIN_PSUBW128,
19266 IX86_BUILTIN_PSUBD128,
19267 IX86_BUILTIN_PSUBQ128,
19268 IX86_BUILTIN_PSUBSB128,
19269 IX86_BUILTIN_PSUBSW128,
19270 IX86_BUILTIN_PSUBUSB128,
19271 IX86_BUILTIN_PSUBUSW128,
19273 IX86_BUILTIN_PAND128,
19274 IX86_BUILTIN_PANDN128,
19275 IX86_BUILTIN_POR128,
19276 IX86_BUILTIN_PXOR128,
19278 IX86_BUILTIN_PAVGB128,
19279 IX86_BUILTIN_PAVGW128,
19281 IX86_BUILTIN_PCMPEQB128,
19282 IX86_BUILTIN_PCMPEQW128,
19283 IX86_BUILTIN_PCMPEQD128,
19284 IX86_BUILTIN_PCMPGTB128,
19285 IX86_BUILTIN_PCMPGTW128,
19286 IX86_BUILTIN_PCMPGTD128,
19288 IX86_BUILTIN_PMADDWD128,
19290 IX86_BUILTIN_PMAXSW128,
19291 IX86_BUILTIN_PMAXUB128,
19292 IX86_BUILTIN_PMINSW128,
19293 IX86_BUILTIN_PMINUB128,
19295 IX86_BUILTIN_PMULUDQ,
19296 IX86_BUILTIN_PMULUDQ128,
19297 IX86_BUILTIN_PMULHUW128,
19298 IX86_BUILTIN_PMULHW128,
19299 IX86_BUILTIN_PMULLW128,
19301 IX86_BUILTIN_PSADBW128,
19302 IX86_BUILTIN_PSHUFHW,
19303 IX86_BUILTIN_PSHUFLW,
19304 IX86_BUILTIN_PSHUFD,
19306 IX86_BUILTIN_PSLLDQI128,
19307 IX86_BUILTIN_PSLLWI128,
19308 IX86_BUILTIN_PSLLDI128,
19309 IX86_BUILTIN_PSLLQI128,
19310 IX86_BUILTIN_PSRAWI128,
19311 IX86_BUILTIN_PSRADI128,
19312 IX86_BUILTIN_PSRLDQI128,
19313 IX86_BUILTIN_PSRLWI128,
19314 IX86_BUILTIN_PSRLDI128,
19315 IX86_BUILTIN_PSRLQI128,
19317 IX86_BUILTIN_PSLLDQ128,
19318 IX86_BUILTIN_PSLLW128,
19319 IX86_BUILTIN_PSLLD128,
19320 IX86_BUILTIN_PSLLQ128,
19321 IX86_BUILTIN_PSRAW128,
19322 IX86_BUILTIN_PSRAD128,
19323 IX86_BUILTIN_PSRLW128,
19324 IX86_BUILTIN_PSRLD128,
19325 IX86_BUILTIN_PSRLQ128,
19327 IX86_BUILTIN_PUNPCKHBW128,
19328 IX86_BUILTIN_PUNPCKHWD128,
19329 IX86_BUILTIN_PUNPCKHDQ128,
19330 IX86_BUILTIN_PUNPCKHQDQ128,
19331 IX86_BUILTIN_PUNPCKLBW128,
19332 IX86_BUILTIN_PUNPCKLWD128,
19333 IX86_BUILTIN_PUNPCKLDQ128,
19334 IX86_BUILTIN_PUNPCKLQDQ128,
19336 IX86_BUILTIN_CLFLUSH,
19337 IX86_BUILTIN_MFENCE,
19338 IX86_BUILTIN_LFENCE,
19340 /* SSE3. */
19341 IX86_BUILTIN_ADDSUBPS,
19342 IX86_BUILTIN_HADDPS,
19343 IX86_BUILTIN_HSUBPS,
19344 IX86_BUILTIN_MOVSHDUP,
19345 IX86_BUILTIN_MOVSLDUP,
19346 IX86_BUILTIN_ADDSUBPD,
19347 IX86_BUILTIN_HADDPD,
19348 IX86_BUILTIN_HSUBPD,
19349 IX86_BUILTIN_LDDQU,
19351 IX86_BUILTIN_MONITOR,
19352 IX86_BUILTIN_MWAIT,
19354 /* SSSE3. */
19355 IX86_BUILTIN_PHADDW,
19356 IX86_BUILTIN_PHADDD,
19357 IX86_BUILTIN_PHADDSW,
19358 IX86_BUILTIN_PHSUBW,
19359 IX86_BUILTIN_PHSUBD,
19360 IX86_BUILTIN_PHSUBSW,
19361 IX86_BUILTIN_PMADDUBSW,
19362 IX86_BUILTIN_PMULHRSW,
19363 IX86_BUILTIN_PSHUFB,
19364 IX86_BUILTIN_PSIGNB,
19365 IX86_BUILTIN_PSIGNW,
19366 IX86_BUILTIN_PSIGND,
19367 IX86_BUILTIN_PALIGNR,
19368 IX86_BUILTIN_PABSB,
19369 IX86_BUILTIN_PABSW,
19370 IX86_BUILTIN_PABSD,
19372 IX86_BUILTIN_PHADDW128,
19373 IX86_BUILTIN_PHADDD128,
19374 IX86_BUILTIN_PHADDSW128,
19375 IX86_BUILTIN_PHSUBW128,
19376 IX86_BUILTIN_PHSUBD128,
19377 IX86_BUILTIN_PHSUBSW128,
19378 IX86_BUILTIN_PMADDUBSW128,
19379 IX86_BUILTIN_PMULHRSW128,
19380 IX86_BUILTIN_PSHUFB128,
19381 IX86_BUILTIN_PSIGNB128,
19382 IX86_BUILTIN_PSIGNW128,
19383 IX86_BUILTIN_PSIGND128,
19384 IX86_BUILTIN_PALIGNR128,
19385 IX86_BUILTIN_PABSB128,
19386 IX86_BUILTIN_PABSW128,
19387 IX86_BUILTIN_PABSD128,
19389 /* AMDFAM10 - SSE4A New Instructions. */
19390 IX86_BUILTIN_MOVNTSD,
19391 IX86_BUILTIN_MOVNTSS,
19392 IX86_BUILTIN_EXTRQI,
19393 IX86_BUILTIN_EXTRQ,
19394 IX86_BUILTIN_INSERTQI,
19395 IX86_BUILTIN_INSERTQ,
19397 /* SSE4.1. */
19398 IX86_BUILTIN_BLENDPD,
19399 IX86_BUILTIN_BLENDPS,
19400 IX86_BUILTIN_BLENDVPD,
19401 IX86_BUILTIN_BLENDVPS,
19402 IX86_BUILTIN_PBLENDVB128,
19403 IX86_BUILTIN_PBLENDW128,
19405 IX86_BUILTIN_DPPD,
19406 IX86_BUILTIN_DPPS,
19408 IX86_BUILTIN_INSERTPS128,
19410 IX86_BUILTIN_MOVNTDQA,
19411 IX86_BUILTIN_MPSADBW128,
19412 IX86_BUILTIN_PACKUSDW128,
19413 IX86_BUILTIN_PCMPEQQ,
19414 IX86_BUILTIN_PHMINPOSUW128,
19416 IX86_BUILTIN_PMAXSB128,
19417 IX86_BUILTIN_PMAXSD128,
19418 IX86_BUILTIN_PMAXUD128,
19419 IX86_BUILTIN_PMAXUW128,
19421 IX86_BUILTIN_PMINSB128,
19422 IX86_BUILTIN_PMINSD128,
19423 IX86_BUILTIN_PMINUD128,
19424 IX86_BUILTIN_PMINUW128,
19426 IX86_BUILTIN_PMOVSXBW128,
19427 IX86_BUILTIN_PMOVSXBD128,
19428 IX86_BUILTIN_PMOVSXBQ128,
19429 IX86_BUILTIN_PMOVSXWD128,
19430 IX86_BUILTIN_PMOVSXWQ128,
19431 IX86_BUILTIN_PMOVSXDQ128,
19433 IX86_BUILTIN_PMOVZXBW128,
19434 IX86_BUILTIN_PMOVZXBD128,
19435 IX86_BUILTIN_PMOVZXBQ128,
19436 IX86_BUILTIN_PMOVZXWD128,
19437 IX86_BUILTIN_PMOVZXWQ128,
19438 IX86_BUILTIN_PMOVZXDQ128,
19440 IX86_BUILTIN_PMULDQ128,
19441 IX86_BUILTIN_PMULLD128,
19443 IX86_BUILTIN_ROUNDPD,
19444 IX86_BUILTIN_ROUNDPS,
19445 IX86_BUILTIN_ROUNDSD,
19446 IX86_BUILTIN_ROUNDSS,
19448 IX86_BUILTIN_PTESTZ,
19449 IX86_BUILTIN_PTESTC,
19450 IX86_BUILTIN_PTESTNZC,
19452 IX86_BUILTIN_VEC_INIT_V2SI,
19453 IX86_BUILTIN_VEC_INIT_V4HI,
19454 IX86_BUILTIN_VEC_INIT_V8QI,
19455 IX86_BUILTIN_VEC_EXT_V2DF,
19456 IX86_BUILTIN_VEC_EXT_V2DI,
19457 IX86_BUILTIN_VEC_EXT_V4SF,
19458 IX86_BUILTIN_VEC_EXT_V4SI,
19459 IX86_BUILTIN_VEC_EXT_V8HI,
19460 IX86_BUILTIN_VEC_EXT_V2SI,
19461 IX86_BUILTIN_VEC_EXT_V4HI,
19462 IX86_BUILTIN_VEC_EXT_V16QI,
19463 IX86_BUILTIN_VEC_SET_V2DI,
19464 IX86_BUILTIN_VEC_SET_V4SF,
19465 IX86_BUILTIN_VEC_SET_V4SI,
19466 IX86_BUILTIN_VEC_SET_V8HI,
19467 IX86_BUILTIN_VEC_SET_V4HI,
19468 IX86_BUILTIN_VEC_SET_V16QI,
19470 IX86_BUILTIN_VEC_PACK_SFIX,
19472 /* SSE4.2. */
19473 IX86_BUILTIN_CRC32QI,
19474 IX86_BUILTIN_CRC32HI,
19475 IX86_BUILTIN_CRC32SI,
19476 IX86_BUILTIN_CRC32DI,
19478 IX86_BUILTIN_PCMPESTRI128,
19479 IX86_BUILTIN_PCMPESTRM128,
19480 IX86_BUILTIN_PCMPESTRA128,
19481 IX86_BUILTIN_PCMPESTRC128,
19482 IX86_BUILTIN_PCMPESTRO128,
19483 IX86_BUILTIN_PCMPESTRS128,
19484 IX86_BUILTIN_PCMPESTRZ128,
19485 IX86_BUILTIN_PCMPISTRI128,
19486 IX86_BUILTIN_PCMPISTRM128,
19487 IX86_BUILTIN_PCMPISTRA128,
19488 IX86_BUILTIN_PCMPISTRC128,
19489 IX86_BUILTIN_PCMPISTRO128,
19490 IX86_BUILTIN_PCMPISTRS128,
19491 IX86_BUILTIN_PCMPISTRZ128,
19493 IX86_BUILTIN_PCMPGTQ,
19495 /* AES instructions */
19496 IX86_BUILTIN_AESENC128,
19497 IX86_BUILTIN_AESENCLAST128,
19498 IX86_BUILTIN_AESDEC128,
19499 IX86_BUILTIN_AESDECLAST128,
19500 IX86_BUILTIN_AESIMC128,
19501 IX86_BUILTIN_AESKEYGENASSIST128,
19503 /* PCLMUL instruction */
19504 IX86_BUILTIN_PCLMULQDQ128,
19506 /* AVX */
19507 IX86_BUILTIN_ADDPD256,
19508 IX86_BUILTIN_ADDPS256,
19509 IX86_BUILTIN_ADDSUBPD256,
19510 IX86_BUILTIN_ADDSUBPS256,
19511 IX86_BUILTIN_ANDPD256,
19512 IX86_BUILTIN_ANDPS256,
19513 IX86_BUILTIN_ANDNPD256,
19514 IX86_BUILTIN_ANDNPS256,
19515 IX86_BUILTIN_BLENDPD256,
19516 IX86_BUILTIN_BLENDPS256,
19517 IX86_BUILTIN_BLENDVPD256,
19518 IX86_BUILTIN_BLENDVPS256,
19519 IX86_BUILTIN_DIVPD256,
19520 IX86_BUILTIN_DIVPS256,
19521 IX86_BUILTIN_DPPS256,
19522 IX86_BUILTIN_HADDPD256,
19523 IX86_BUILTIN_HADDPS256,
19524 IX86_BUILTIN_HSUBPD256,
19525 IX86_BUILTIN_HSUBPS256,
19526 IX86_BUILTIN_MAXPD256,
19527 IX86_BUILTIN_MAXPS256,
19528 IX86_BUILTIN_MINPD256,
19529 IX86_BUILTIN_MINPS256,
19530 IX86_BUILTIN_MULPD256,
19531 IX86_BUILTIN_MULPS256,
19532 IX86_BUILTIN_ORPD256,
19533 IX86_BUILTIN_ORPS256,
19534 IX86_BUILTIN_SHUFPD256,
19535 IX86_BUILTIN_SHUFPS256,
19536 IX86_BUILTIN_SUBPD256,
19537 IX86_BUILTIN_SUBPS256,
19538 IX86_BUILTIN_XORPD256,
19539 IX86_BUILTIN_XORPS256,
19540 IX86_BUILTIN_CMPSD,
19541 IX86_BUILTIN_CMPSS,
19542 IX86_BUILTIN_CMPPD,
19543 IX86_BUILTIN_CMPPS,
19544 IX86_BUILTIN_CMPPD256,
19545 IX86_BUILTIN_CMPPS256,
19546 IX86_BUILTIN_CVTDQ2PD256,
19547 IX86_BUILTIN_CVTDQ2PS256,
19548 IX86_BUILTIN_CVTPD2PS256,
19549 IX86_BUILTIN_CVTPS2DQ256,
19550 IX86_BUILTIN_CVTPS2PD256,
19551 IX86_BUILTIN_CVTTPD2DQ256,
19552 IX86_BUILTIN_CVTPD2DQ256,
19553 IX86_BUILTIN_CVTTPS2DQ256,
19554 IX86_BUILTIN_EXTRACTF128PD256,
19555 IX86_BUILTIN_EXTRACTF128PS256,
19556 IX86_BUILTIN_EXTRACTF128SI256,
19557 IX86_BUILTIN_VZEROALL,
19558 IX86_BUILTIN_VZEROUPPER,
19559 IX86_BUILTIN_VZEROUPPER_REX64,
19560 IX86_BUILTIN_VPERMILVARPD,
19561 IX86_BUILTIN_VPERMILVARPS,
19562 IX86_BUILTIN_VPERMILVARPD256,
19563 IX86_BUILTIN_VPERMILVARPS256,
19564 IX86_BUILTIN_VPERMILPD,
19565 IX86_BUILTIN_VPERMILPS,
19566 IX86_BUILTIN_VPERMILPD256,
19567 IX86_BUILTIN_VPERMILPS256,
19568 IX86_BUILTIN_VPERMIL2PD,
19569 IX86_BUILTIN_VPERMIL2PS,
19570 IX86_BUILTIN_VPERMIL2PD256,
19571 IX86_BUILTIN_VPERMIL2PS256,
19572 IX86_BUILTIN_VPERM2F128PD256,
19573 IX86_BUILTIN_VPERM2F128PS256,
19574 IX86_BUILTIN_VPERM2F128SI256,
19575 IX86_BUILTIN_VBROADCASTSS,
19576 IX86_BUILTIN_VBROADCASTSD256,
19577 IX86_BUILTIN_VBROADCASTSS256,
19578 IX86_BUILTIN_VBROADCASTPD256,
19579 IX86_BUILTIN_VBROADCASTPS256,
19580 IX86_BUILTIN_VINSERTF128PD256,
19581 IX86_BUILTIN_VINSERTF128PS256,
19582 IX86_BUILTIN_VINSERTF128SI256,
19583 IX86_BUILTIN_LOADUPD256,
19584 IX86_BUILTIN_LOADUPS256,
19585 IX86_BUILTIN_STOREUPD256,
19586 IX86_BUILTIN_STOREUPS256,
19587 IX86_BUILTIN_LDDQU256,
19588 IX86_BUILTIN_LOADDQU256,
19589 IX86_BUILTIN_STOREDQU256,
19590 IX86_BUILTIN_MASKLOADPD,
19591 IX86_BUILTIN_MASKLOADPS,
19592 IX86_BUILTIN_MASKSTOREPD,
19593 IX86_BUILTIN_MASKSTOREPS,
19594 IX86_BUILTIN_MASKLOADPD256,
19595 IX86_BUILTIN_MASKLOADPS256,
19596 IX86_BUILTIN_MASKSTOREPD256,
19597 IX86_BUILTIN_MASKSTOREPS256,
19598 IX86_BUILTIN_MOVSHDUP256,
19599 IX86_BUILTIN_MOVSLDUP256,
19600 IX86_BUILTIN_MOVDDUP256,
19602 IX86_BUILTIN_SQRTPD256,
19603 IX86_BUILTIN_SQRTPS256,
19604 IX86_BUILTIN_SQRTPS_NR256,
19605 IX86_BUILTIN_RSQRTPS256,
19606 IX86_BUILTIN_RSQRTPS_NR256,
19608 IX86_BUILTIN_RCPPS256,
19610 IX86_BUILTIN_ROUNDPD256,
19611 IX86_BUILTIN_ROUNDPS256,
19613 IX86_BUILTIN_UNPCKHPD256,
19614 IX86_BUILTIN_UNPCKLPD256,
19615 IX86_BUILTIN_UNPCKHPS256,
19616 IX86_BUILTIN_UNPCKLPS256,
19618 IX86_BUILTIN_SI256_SI,
19619 IX86_BUILTIN_PS256_PS,
19620 IX86_BUILTIN_PD256_PD,
19621 IX86_BUILTIN_SI_SI256,
19622 IX86_BUILTIN_PS_PS256,
19623 IX86_BUILTIN_PD_PD256,
19625 IX86_BUILTIN_VTESTZPD,
19626 IX86_BUILTIN_VTESTCPD,
19627 IX86_BUILTIN_VTESTNZCPD,
19628 IX86_BUILTIN_VTESTZPS,
19629 IX86_BUILTIN_VTESTCPS,
19630 IX86_BUILTIN_VTESTNZCPS,
19631 IX86_BUILTIN_VTESTZPD256,
19632 IX86_BUILTIN_VTESTCPD256,
19633 IX86_BUILTIN_VTESTNZCPD256,
19634 IX86_BUILTIN_VTESTZPS256,
19635 IX86_BUILTIN_VTESTCPS256,
19636 IX86_BUILTIN_VTESTNZCPS256,
19637 IX86_BUILTIN_PTESTZ256,
19638 IX86_BUILTIN_PTESTC256,
19639 IX86_BUILTIN_PTESTNZC256,
19641 IX86_BUILTIN_MOVMSKPD256,
19642 IX86_BUILTIN_MOVMSKPS256,
19644 /* TFmode support builtins. */
19645 IX86_BUILTIN_INFQ,
19646 IX86_BUILTIN_FABSQ,
19647 IX86_BUILTIN_COPYSIGNQ,
19649 /* SSE5 instructions */
19650 IX86_BUILTIN_FMADDSS,
19651 IX86_BUILTIN_FMADDSD,
19652 IX86_BUILTIN_FMADDPS,
19653 IX86_BUILTIN_FMADDPD,
19654 IX86_BUILTIN_FMSUBSS,
19655 IX86_BUILTIN_FMSUBSD,
19656 IX86_BUILTIN_FMSUBPS,
19657 IX86_BUILTIN_FMSUBPD,
19658 IX86_BUILTIN_FNMADDSS,
19659 IX86_BUILTIN_FNMADDSD,
19660 IX86_BUILTIN_FNMADDPS,
19661 IX86_BUILTIN_FNMADDPD,
19662 IX86_BUILTIN_FNMSUBSS,
19663 IX86_BUILTIN_FNMSUBSD,
19664 IX86_BUILTIN_FNMSUBPS,
19665 IX86_BUILTIN_FNMSUBPD,
19666 IX86_BUILTIN_PCMOV,
19667 IX86_BUILTIN_PCMOV_V2DI,
19668 IX86_BUILTIN_PCMOV_V4SI,
19669 IX86_BUILTIN_PCMOV_V8HI,
19670 IX86_BUILTIN_PCMOV_V16QI,
19671 IX86_BUILTIN_PCMOV_V4SF,
19672 IX86_BUILTIN_PCMOV_V2DF,
19673 IX86_BUILTIN_PPERM,
19674 IX86_BUILTIN_PERMPS,
19675 IX86_BUILTIN_PERMPD,
19676 IX86_BUILTIN_PMACSSWW,
19677 IX86_BUILTIN_PMACSWW,
19678 IX86_BUILTIN_PMACSSWD,
19679 IX86_BUILTIN_PMACSWD,
19680 IX86_BUILTIN_PMACSSDD,
19681 IX86_BUILTIN_PMACSDD,
19682 IX86_BUILTIN_PMACSSDQL,
19683 IX86_BUILTIN_PMACSSDQH,
19684 IX86_BUILTIN_PMACSDQL,
19685 IX86_BUILTIN_PMACSDQH,
19686 IX86_BUILTIN_PMADCSSWD,
19687 IX86_BUILTIN_PMADCSWD,
19688 IX86_BUILTIN_PHADDBW,
19689 IX86_BUILTIN_PHADDBD,
19690 IX86_BUILTIN_PHADDBQ,
19691 IX86_BUILTIN_PHADDWD,
19692 IX86_BUILTIN_PHADDWQ,
19693 IX86_BUILTIN_PHADDDQ,
19694 IX86_BUILTIN_PHADDUBW,
19695 IX86_BUILTIN_PHADDUBD,
19696 IX86_BUILTIN_PHADDUBQ,
19697 IX86_BUILTIN_PHADDUWD,
19698 IX86_BUILTIN_PHADDUWQ,
19699 IX86_BUILTIN_PHADDUDQ,
19700 IX86_BUILTIN_PHSUBBW,
19701 IX86_BUILTIN_PHSUBWD,
19702 IX86_BUILTIN_PHSUBDQ,
19703 IX86_BUILTIN_PROTB,
19704 IX86_BUILTIN_PROTW,
19705 IX86_BUILTIN_PROTD,
19706 IX86_BUILTIN_PROTQ,
19707 IX86_BUILTIN_PROTB_IMM,
19708 IX86_BUILTIN_PROTW_IMM,
19709 IX86_BUILTIN_PROTD_IMM,
19710 IX86_BUILTIN_PROTQ_IMM,
19711 IX86_BUILTIN_PSHLB,
19712 IX86_BUILTIN_PSHLW,
19713 IX86_BUILTIN_PSHLD,
19714 IX86_BUILTIN_PSHLQ,
19715 IX86_BUILTIN_PSHAB,
19716 IX86_BUILTIN_PSHAW,
19717 IX86_BUILTIN_PSHAD,
19718 IX86_BUILTIN_PSHAQ,
19719 IX86_BUILTIN_FRCZSS,
19720 IX86_BUILTIN_FRCZSD,
19721 IX86_BUILTIN_FRCZPS,
19722 IX86_BUILTIN_FRCZPD,
19723 IX86_BUILTIN_CVTPH2PS,
19724 IX86_BUILTIN_CVTPS2PH,
19726 IX86_BUILTIN_COMEQSS,
19727 IX86_BUILTIN_COMNESS,
19728 IX86_BUILTIN_COMLTSS,
19729 IX86_BUILTIN_COMLESS,
19730 IX86_BUILTIN_COMGTSS,
19731 IX86_BUILTIN_COMGESS,
19732 IX86_BUILTIN_COMUEQSS,
19733 IX86_BUILTIN_COMUNESS,
19734 IX86_BUILTIN_COMULTSS,
19735 IX86_BUILTIN_COMULESS,
19736 IX86_BUILTIN_COMUGTSS,
19737 IX86_BUILTIN_COMUGESS,
19738 IX86_BUILTIN_COMORDSS,
19739 IX86_BUILTIN_COMUNORDSS,
19740 IX86_BUILTIN_COMFALSESS,
19741 IX86_BUILTIN_COMTRUESS,
19743 IX86_BUILTIN_COMEQSD,
19744 IX86_BUILTIN_COMNESD,
19745 IX86_BUILTIN_COMLTSD,
19746 IX86_BUILTIN_COMLESD,
19747 IX86_BUILTIN_COMGTSD,
19748 IX86_BUILTIN_COMGESD,
19749 IX86_BUILTIN_COMUEQSD,
19750 IX86_BUILTIN_COMUNESD,
19751 IX86_BUILTIN_COMULTSD,
19752 IX86_BUILTIN_COMULESD,
19753 IX86_BUILTIN_COMUGTSD,
19754 IX86_BUILTIN_COMUGESD,
19755 IX86_BUILTIN_COMORDSD,
19756 IX86_BUILTIN_COMUNORDSD,
19757 IX86_BUILTIN_COMFALSESD,
19758 IX86_BUILTIN_COMTRUESD,
19760 IX86_BUILTIN_COMEQPS,
19761 IX86_BUILTIN_COMNEPS,
19762 IX86_BUILTIN_COMLTPS,
19763 IX86_BUILTIN_COMLEPS,
19764 IX86_BUILTIN_COMGTPS,
19765 IX86_BUILTIN_COMGEPS,
19766 IX86_BUILTIN_COMUEQPS,
19767 IX86_BUILTIN_COMUNEPS,
19768 IX86_BUILTIN_COMULTPS,
19769 IX86_BUILTIN_COMULEPS,
19770 IX86_BUILTIN_COMUGTPS,
19771 IX86_BUILTIN_COMUGEPS,
19772 IX86_BUILTIN_COMORDPS,
19773 IX86_BUILTIN_COMUNORDPS,
19774 IX86_BUILTIN_COMFALSEPS,
19775 IX86_BUILTIN_COMTRUEPS,
19777 IX86_BUILTIN_COMEQPD,
19778 IX86_BUILTIN_COMNEPD,
19779 IX86_BUILTIN_COMLTPD,
19780 IX86_BUILTIN_COMLEPD,
19781 IX86_BUILTIN_COMGTPD,
19782 IX86_BUILTIN_COMGEPD,
19783 IX86_BUILTIN_COMUEQPD,
19784 IX86_BUILTIN_COMUNEPD,
19785 IX86_BUILTIN_COMULTPD,
19786 IX86_BUILTIN_COMULEPD,
19787 IX86_BUILTIN_COMUGTPD,
19788 IX86_BUILTIN_COMUGEPD,
19789 IX86_BUILTIN_COMORDPD,
19790 IX86_BUILTIN_COMUNORDPD,
19791 IX86_BUILTIN_COMFALSEPD,
19792 IX86_BUILTIN_COMTRUEPD,
19794 IX86_BUILTIN_PCOMEQUB,
19795 IX86_BUILTIN_PCOMNEUB,
19796 IX86_BUILTIN_PCOMLTUB,
19797 IX86_BUILTIN_PCOMLEUB,
19798 IX86_BUILTIN_PCOMGTUB,
19799 IX86_BUILTIN_PCOMGEUB,
19800 IX86_BUILTIN_PCOMFALSEUB,
19801 IX86_BUILTIN_PCOMTRUEUB,
19802 IX86_BUILTIN_PCOMEQUW,
19803 IX86_BUILTIN_PCOMNEUW,
19804 IX86_BUILTIN_PCOMLTUW,
19805 IX86_BUILTIN_PCOMLEUW,
19806 IX86_BUILTIN_PCOMGTUW,
19807 IX86_BUILTIN_PCOMGEUW,
19808 IX86_BUILTIN_PCOMFALSEUW,
19809 IX86_BUILTIN_PCOMTRUEUW,
19810 IX86_BUILTIN_PCOMEQUD,
19811 IX86_BUILTIN_PCOMNEUD,
19812 IX86_BUILTIN_PCOMLTUD,
19813 IX86_BUILTIN_PCOMLEUD,
19814 IX86_BUILTIN_PCOMGTUD,
19815 IX86_BUILTIN_PCOMGEUD,
19816 IX86_BUILTIN_PCOMFALSEUD,
19817 IX86_BUILTIN_PCOMTRUEUD,
19818 IX86_BUILTIN_PCOMEQUQ,
19819 IX86_BUILTIN_PCOMNEUQ,
19820 IX86_BUILTIN_PCOMLTUQ,
19821 IX86_BUILTIN_PCOMLEUQ,
19822 IX86_BUILTIN_PCOMGTUQ,
19823 IX86_BUILTIN_PCOMGEUQ,
19824 IX86_BUILTIN_PCOMFALSEUQ,
19825 IX86_BUILTIN_PCOMTRUEUQ,
19827 IX86_BUILTIN_PCOMEQB,
19828 IX86_BUILTIN_PCOMNEB,
19829 IX86_BUILTIN_PCOMLTB,
19830 IX86_BUILTIN_PCOMLEB,
19831 IX86_BUILTIN_PCOMGTB,
19832 IX86_BUILTIN_PCOMGEB,
19833 IX86_BUILTIN_PCOMFALSEB,
19834 IX86_BUILTIN_PCOMTRUEB,
19835 IX86_BUILTIN_PCOMEQW,
19836 IX86_BUILTIN_PCOMNEW,
19837 IX86_BUILTIN_PCOMLTW,
19838 IX86_BUILTIN_PCOMLEW,
19839 IX86_BUILTIN_PCOMGTW,
19840 IX86_BUILTIN_PCOMGEW,
19841 IX86_BUILTIN_PCOMFALSEW,
19842 IX86_BUILTIN_PCOMTRUEW,
19843 IX86_BUILTIN_PCOMEQD,
19844 IX86_BUILTIN_PCOMNED,
19845 IX86_BUILTIN_PCOMLTD,
19846 IX86_BUILTIN_PCOMLED,
19847 IX86_BUILTIN_PCOMGTD,
19848 IX86_BUILTIN_PCOMGED,
19849 IX86_BUILTIN_PCOMFALSED,
19850 IX86_BUILTIN_PCOMTRUED,
19851 IX86_BUILTIN_PCOMEQQ,
19852 IX86_BUILTIN_PCOMNEQ,
19853 IX86_BUILTIN_PCOMLTQ,
19854 IX86_BUILTIN_PCOMLEQ,
19855 IX86_BUILTIN_PCOMGTQ,
19856 IX86_BUILTIN_PCOMGEQ,
19857 IX86_BUILTIN_PCOMFALSEQ,
19858 IX86_BUILTIN_PCOMTRUEQ,
19860 IX86_BUILTIN_MAX
19861 };
19863 /* Table for the ix86 builtin decls. */
19866 /* Table of all of the builtin functions that are possible with different ISA's
19867 but are waiting to be built until a function is declared to use that
19868 ISA. */
19870 {
19875 };
19880 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
19881 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
19882 * function decl in the ix86_builtins array. Returns the function decl or
19883 * NULL_TREE, if the builtin was not added.
19884 *
19885 * If the front end has a special hook for builtin functions, delay adding
19886 * builtin functions that aren't in the current ISA until the ISA is changed
19887 * with function specific optimization. Doing so, can save about 300K for the
19888 * default compiler. When the builtin is expanded, check at that time whether
19889 * it is valid.
19890 *
19891 * If the front end doesn't have a special hook, record all builtins, even if
19892 * it isn't an instruction set in the current ISA in case the user uses
19893 * function specific options for a different ISA, so that we don't get scope
19894 * errors if a builtin is added in the middle of a function scope. */
19898 {
19902 {
19909 {
19911 NULL_TREE);
19914 }
19915 else
19916 {
19921 }
19922 }
19925 }
19927 /* Like def_builtin, but also marks the function decl "const". */
19932 {
19936 else
19940 }
19942 /* Add any new builtin functions for a given ISA that may not have been
19943 declared. This saves a bit of space compared to adding all of the
19944 declarations to the tree, even if we didn't use them. */
19946 static void
19948 {
19950 tree decl;
19953 {
19956 {
19960 NULL_TREE);
19966 }
19967 }
19968 }
19970 /* Bits for builtin_description.flag. */
19972 /* Set when we don't support the comparison natively, and should
19973 swap_comparison in order to support it. */
19974 #define BUILTIN_DESC_SWAP_OPERANDS 1
19976 struct builtin_description
19977 {
19984 };
19987 {
19988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
19989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
19990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
19991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
19992 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
19993 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
19994 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
19995 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
19996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
19997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
19998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
19999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20000 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20002 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20003 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20004 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20005 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20006 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20007 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20008 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20009 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20012 };
20015 {
20016 /* SSE4.2 */
20017 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20018 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20019 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20020 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20021 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20022 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20023 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20024 };
20027 {
20028 /* SSE4.2 */
20029 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20030 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20031 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20032 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20033 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20034 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20035 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20036 };
20038 /* Special builtin types */
20039 enum ix86_special_builtin_type
20040 {
20041 SPECIAL_FTYPE_UNKNOWN,
20042 VOID_FTYPE_VOID,
20043 V32QI_FTYPE_PCCHAR,
20044 V16QI_FTYPE_PCCHAR,
20045 V8SF_FTYPE_PCV4SF,
20046 V8SF_FTYPE_PCFLOAT,
20047 V4DF_FTYPE_PCV2DF,
20048 V4DF_FTYPE_PCDOUBLE,
20049 V4SF_FTYPE_PCFLOAT,
20050 V2DF_FTYPE_PCDOUBLE,
20051 V8SF_FTYPE_PCV8SF_V8SF,
20052 V4DF_FTYPE_PCV4DF_V4DF,
20053 V4SF_FTYPE_V4SF_PCV2SF,
20054 V4SF_FTYPE_PCV4SF_V4SF,
20055 V2DF_FTYPE_V2DF_PCDOUBLE,
20056 V2DF_FTYPE_PCV2DF_V2DF,
20057 V2DI_FTYPE_PV2DI,
20058 VOID_FTYPE_PV2SF_V4SF,
20059 VOID_FTYPE_PV2DI_V2DI,
20060 VOID_FTYPE_PCHAR_V32QI,
20061 VOID_FTYPE_PCHAR_V16QI,
20062 VOID_FTYPE_PFLOAT_V8SF,
20063 VOID_FTYPE_PFLOAT_V4SF,
20064 VOID_FTYPE_PDOUBLE_V4DF,
20065 VOID_FTYPE_PDOUBLE_V2DF,
20066 VOID_FTYPE_PDI_DI,
20067 VOID_FTYPE_PINT_INT,
20068 VOID_FTYPE_PV8SF_V8SF_V8SF,
20069 VOID_FTYPE_PV4DF_V4DF_V4DF,
20070 VOID_FTYPE_PV4SF_V4SF_V4SF,
20071 VOID_FTYPE_PV2DF_V2DF_V2DF
20072 };
20074 /* Builtin types */
20075 enum ix86_builtin_type
20076 {
20077 FTYPE_UNKNOWN,
20078 FLOAT128_FTYPE_FLOAT128,
20079 FLOAT_FTYPE_FLOAT,
20080 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20081 INT_FTYPE_V8SF_V8SF_PTEST,
20082 INT_FTYPE_V4DI_V4DI_PTEST,
20083 INT_FTYPE_V4DF_V4DF_PTEST,
20084 INT_FTYPE_V4SF_V4SF_PTEST,
20085 INT_FTYPE_V2DI_V2DI_PTEST,
20086 INT_FTYPE_V2DF_V2DF_PTEST,
20087 INT64_FTYPE_V4SF,
20088 INT64_FTYPE_V2DF,
20089 INT_FTYPE_V16QI,
20090 INT_FTYPE_V8QI,
20091 INT_FTYPE_V8SF,
20092 INT_FTYPE_V4DF,
20093 INT_FTYPE_V4SF,
20094 INT_FTYPE_V2DF,
20095 V16QI_FTYPE_V16QI,
20096 V8SI_FTYPE_V8SF,
20097 V8SI_FTYPE_V4SI,
20098 V8HI_FTYPE_V8HI,
20099 V8HI_FTYPE_V16QI,
20100 V8QI_FTYPE_V8QI,
20101 V8SF_FTYPE_V8SF,
20102 V8SF_FTYPE_V8SI,
20103 V8SF_FTYPE_V4SF,
20104 V4SI_FTYPE_V4SI,
20105 V4SI_FTYPE_V16QI,
20106 V4SI_FTYPE_V8SI,
20107 V4SI_FTYPE_V8HI,
20108 V4SI_FTYPE_V4DF,
20109 V4SI_FTYPE_V4SF,
20110 V4SI_FTYPE_V2DF,
20111 V4HI_FTYPE_V4HI,
20112 V4DF_FTYPE_V4DF,
20113 V4DF_FTYPE_V4SI,
20114 V4DF_FTYPE_V4SF,
20115 V4DF_FTYPE_V2DF,
20116 V4SF_FTYPE_V4DF,
20117 V4SF_FTYPE_V4SF,
20118 V4SF_FTYPE_V4SF_VEC_MERGE,
20119 V4SF_FTYPE_V8SF,
20120 V4SF_FTYPE_V4SI,
20121 V4SF_FTYPE_V2DF,
20122 V2DI_FTYPE_V2DI,
20123 V2DI_FTYPE_V16QI,
20124 V2DI_FTYPE_V8HI,
20125 V2DI_FTYPE_V4SI,
20126 V2DF_FTYPE_V2DF,
20127 V2DF_FTYPE_V2DF_VEC_MERGE,
20128 V2DF_FTYPE_V4SI,
20129 V2DF_FTYPE_V4DF,
20130 V2DF_FTYPE_V4SF,
20131 V2DF_FTYPE_V2SI,
20132 V2SI_FTYPE_V2SI,
20133 V2SI_FTYPE_V4SF,
20134 V2SI_FTYPE_V2SF,
20135 V2SI_FTYPE_V2DF,
20136 V2SF_FTYPE_V2SF,
20137 V2SF_FTYPE_V2SI,
20138 V16QI_FTYPE_V16QI_V16QI,
20139 V16QI_FTYPE_V8HI_V8HI,
20140 V8QI_FTYPE_V8QI_V8QI,
20141 V8QI_FTYPE_V4HI_V4HI,
20142 V8HI_FTYPE_V8HI_V8HI,
20143 V8HI_FTYPE_V8HI_V8HI_COUNT,
20144 V8HI_FTYPE_V16QI_V16QI,
20145 V8HI_FTYPE_V4SI_V4SI,
20146 V8HI_FTYPE_V8HI_SI_COUNT,
20147 V8SF_FTYPE_V8SF_V8SF,
20148 V8SF_FTYPE_V8SF_V8SI,
20149 V4SI_FTYPE_V4SI_V4SI,
20150 V4SI_FTYPE_V4SI_V4SI_COUNT,
20151 V4SI_FTYPE_V8HI_V8HI,
20152 V4SI_FTYPE_V4SF_V4SF,
20153 V4SI_FTYPE_V2DF_V2DF,
20154 V4SI_FTYPE_V4SI_SI_COUNT,
20155 V4HI_FTYPE_V4HI_V4HI,
20156 V4HI_FTYPE_V4HI_V4HI_COUNT,
20157 V4HI_FTYPE_V8QI_V8QI,
20158 V4HI_FTYPE_V2SI_V2SI,
20159 V4HI_FTYPE_V4HI_SI_COUNT,
20160 V4DF_FTYPE_V4DF_V4DF,
20161 V4DF_FTYPE_V4DF_V4DI,
20162 V4SF_FTYPE_V4SF_V4SF,
20163 V4SF_FTYPE_V4SF_V4SF_SWAP,
20164 V4SF_FTYPE_V4SF_V4SI,
20165 V4SF_FTYPE_V4SF_V2SI,
20166 V4SF_FTYPE_V4SF_V2DF,
20167 V4SF_FTYPE_V4SF_DI,
20168 V4SF_FTYPE_V4SF_SI,
20169 V2DI_FTYPE_V2DI_V2DI,
20170 V2DI_FTYPE_V2DI_V2DI_COUNT,
20171 V2DI_FTYPE_V16QI_V16QI,
20172 V2DI_FTYPE_V4SI_V4SI,
20173 V2DI_FTYPE_V2DI_V16QI,
20174 V2DI_FTYPE_V2DF_V2DF,
20175 V2DI_FTYPE_V2DI_SI_COUNT,
20176 V2SI_FTYPE_V2SI_V2SI,
20177 V2SI_FTYPE_V2SI_V2SI_COUNT,
20178 V2SI_FTYPE_V4HI_V4HI,
20179 V2SI_FTYPE_V2SF_V2SF,
20180 V2SI_FTYPE_V2SI_SI_COUNT,
20181 V2DF_FTYPE_V2DF_V2DF,
20182 V2DF_FTYPE_V2DF_V2DF_SWAP,
20183 V2DF_FTYPE_V2DF_V4SF,
20184 V2DF_FTYPE_V2DF_V2DI,
20185 V2DF_FTYPE_V2DF_DI,
20186 V2DF_FTYPE_V2DF_SI,
20187 V2SF_FTYPE_V2SF_V2SF,
20188 V1DI_FTYPE_V1DI_V1DI,
20189 V1DI_FTYPE_V1DI_V1DI_COUNT,
20190 V1DI_FTYPE_V8QI_V8QI,
20191 V1DI_FTYPE_V2SI_V2SI,
20192 V1DI_FTYPE_V1DI_SI_COUNT,
20193 UINT64_FTYPE_UINT64_UINT64,
20194 UINT_FTYPE_UINT_UINT,
20195 UINT_FTYPE_UINT_USHORT,
20196 UINT_FTYPE_UINT_UCHAR,
20197 V8HI_FTYPE_V8HI_INT,
20198 V4SI_FTYPE_V4SI_INT,
20199 V4HI_FTYPE_V4HI_INT,
20200 V8SF_FTYPE_V8SF_INT,
20201 V4SI_FTYPE_V8SI_INT,
20202 V4SF_FTYPE_V8SF_INT,
20203 V2DF_FTYPE_V4DF_INT,
20204 V4DF_FTYPE_V4DF_INT,
20205 V4SF_FTYPE_V4SF_INT,
20206 V2DI_FTYPE_V2DI_INT,
20207 V2DI2TI_FTYPE_V2DI_INT,
20208 V2DF_FTYPE_V2DF_INT,
20209 V16QI_FTYPE_V16QI_V16QI_V16QI,
20210 V8SF_FTYPE_V8SF_V8SF_V8SF,
20211 V4DF_FTYPE_V4DF_V4DF_V4DF,
20212 V4SF_FTYPE_V4SF_V4SF_V4SF,
20213 V2DF_FTYPE_V2DF_V2DF_V2DF,
20214 V16QI_FTYPE_V16QI_V16QI_INT,
20215 V8SI_FTYPE_V8SI_V8SI_INT,
20216 V8SI_FTYPE_V8SI_V4SI_INT,
20217 V8HI_FTYPE_V8HI_V8HI_INT,
20218 V8SF_FTYPE_V8SF_V8SF_INT,
20219 V8SF_FTYPE_V8SF_V4SF_INT,
20220 V4SI_FTYPE_V4SI_V4SI_INT,
20221 V4DF_FTYPE_V4DF_V4DF_INT,
20222 V4DF_FTYPE_V4DF_V2DF_INT,
20223 V4SF_FTYPE_V4SF_V4SF_INT,
20224 V2DI_FTYPE_V2DI_V2DI_INT,
20225 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20226 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20227 V2DF_FTYPE_V2DF_V2DF_INT,
20228 V8SF_FTYPE_V8SF_V8SF_V8SI_INT,
20229 V4DF_FTYPE_V4DF_V4DF_V4DI_INT,
20230 V4SF_FTYPE_V4SF_V4SF_V4SI_INT,
20231 V2DF_FTYPE_V2DF_V2DF_V2DI_INT,
20232 V2DI_FTYPE_V2DI_UINT_UINT,
20233 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20234 };
20236 /* Special builtins with variable number of arguments. */
20238 {
20239 /* MMX */
20240 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20242 /* 3DNow! */
20243 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20245 /* SSE */
20246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20255 /* SSE or 3DNow!A */
20256 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20257 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20259 /* SSE2 */
20260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20273 /* SSE3 */
20274 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20276 /* SSE4.1 */
20277 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20279 /* SSE4A */
20280 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20281 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20283 /* AVX */
20284 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20285 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20286 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20288 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20289 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20290 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20291 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20292 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20294 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20295 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20296 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20297 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20298 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20299 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20300 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20302 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20303 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20304 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20305 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20306 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20307 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20308 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20309 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20310 };
20312 /* Builtins with variable number of arguments. */
20314 {
20315 /* MMX */
20316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20321 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20328 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20330 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20333 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20335 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20337 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20338 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20340 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20342 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20343 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20344 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20345 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20347 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20348 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20349 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20350 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20351 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20352 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20354 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20355 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20356 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20358 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20360 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20361 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20362 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20363 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20364 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20365 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20367 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20368 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20369 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20370 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20371 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20372 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20374 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20375 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20376 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20377 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20379 /* 3DNow! */
20380 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20381 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20382 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20383 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20385 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20386 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20387 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20388 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20389 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20390 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20391 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20392 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20393 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20394 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20395 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20396 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20397 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20398 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20399 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20401 /* 3DNow!A */
20402 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20403 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20404 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20405 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20406 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20407 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20409 /* SSE */
20410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20412 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20413 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20414 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20418 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20419 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20420 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20421 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20423 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20425 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20426 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20427 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20428 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20429 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20430 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20432 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20435 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20440 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20441 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
20445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20446 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20447 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20448 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20449 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20450 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20451 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20452 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20453 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20454 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20455 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20457 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20458 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20459 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20460 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20462 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20463 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20464 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20465 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20467 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20468 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20469 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20470 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20471 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20473 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
20474 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
20475 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
20477 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
20479 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20480 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20481 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20483 /* SSE MMX or 3Dnow!A */
20484 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20485 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20486 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20488 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20489 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20490 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20491 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20493 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
20494 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
20496 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
20498 /* SSE2 */
20499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
20502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
20503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
20504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
20505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
20507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
20510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
20515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20517 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20518 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
20522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20524 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20525 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20526 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20527 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
20538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20555 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20559 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20560 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20561 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20562 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20564 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20565 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20566 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20568 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
20570 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20571 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20572 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20573 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20574 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20575 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20576 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20577 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20581 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20588 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20589 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
20591 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20593 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20594 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20597 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20600 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20602 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20606 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20607 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20608 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20618 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20622 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20624 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20625 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
20627 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
20628 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20630 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
20632 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
20633 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
20634 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
20635 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
20637 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20638 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20639 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20640 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20641 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20642 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20643 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20645 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20646 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20647 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20648 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20649 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20650 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20651 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20653 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20654 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20655 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20656 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
20659 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
20660 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
20662 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
20664 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
20665 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
20667 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
20669 /* SSE2 MMX */
20670 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
20671 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
20673 /* SSE3 */
20674 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
20675 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20677 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20678 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20679 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20680 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20681 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20682 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20684 /* SSSE3 */
20685 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
20686 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
20687 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
20688 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
20689 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
20690 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20692 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20693 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20694 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20695 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20696 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20697 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20698 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20699 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20700 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20701 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20702 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20703 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20704 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
20705 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
20706 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20707 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20708 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20709 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20710 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20711 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20712 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20713 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20714 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20715 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20717 /* SSSE3. */
20718 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
20719 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
20721 /* SSE4.1 */
20722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20723 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20724 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
20725 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
20726 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20727 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20728 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20729 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
20730 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
20731 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
20733 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
20734 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
20735 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
20736 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
20737 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
20738 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
20739 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
20740 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
20741 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
20742 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
20743 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
20744 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
20745 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
20747 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20748 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20749 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20750 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20751 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20752 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20753 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20754 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20755 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20756 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20757 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20758 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20760 /* SSE4.1 and SSE5 */
20761 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
20762 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
20763 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20764 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20766 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20767 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20768 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20770 /* SSE4.2 */
20771 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20772 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
20773 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
20774 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
20775 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
20777 /* SSE4A */
20778 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
20779 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
20780 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
20781 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20783 /* AES */
20784 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
20785 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
20787 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20788 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20789 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20790 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20792 /* PCLMUL */
20793 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
20795 /* AVX */
20796 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20797 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20800 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20801 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20804 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20810 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20811 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20812 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20813 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20814 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20815 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20816 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20817 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20818 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20819 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20820 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20821 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
20824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
20825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
20826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
20828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
20831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
20832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
20842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
20843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
20844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
20845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
20846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
20847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
20848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
20849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
20850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
20851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
20852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
20855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
20856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
20857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
20858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
20859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT },
20860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT },
20861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT },
20862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT },
20863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
20864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
20865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
20867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
20871 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
20872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20873 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20875 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
20880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
20882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
20888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
20889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
20890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
20891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
20892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
20894 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20895 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20896 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
20911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
20912 };
20914 /* SSE5 */
20916 MULTI_ARG_UNKNOWN,
20917 MULTI_ARG_3_SF,
20918 MULTI_ARG_3_DF,
20919 MULTI_ARG_3_DI,
20920 MULTI_ARG_3_SI,
20921 MULTI_ARG_3_SI_DI,
20922 MULTI_ARG_3_HI,
20923 MULTI_ARG_3_HI_SI,
20924 MULTI_ARG_3_QI,
20925 MULTI_ARG_3_PERMPS,
20926 MULTI_ARG_3_PERMPD,
20927 MULTI_ARG_2_SF,
20928 MULTI_ARG_2_DF,
20929 MULTI_ARG_2_DI,
20930 MULTI_ARG_2_SI,
20931 MULTI_ARG_2_HI,
20932 MULTI_ARG_2_QI,
20933 MULTI_ARG_2_DI_IMM,
20934 MULTI_ARG_2_SI_IMM,
20935 MULTI_ARG_2_HI_IMM,
20936 MULTI_ARG_2_QI_IMM,
20937 MULTI_ARG_2_SF_CMP,
20938 MULTI_ARG_2_DF_CMP,
20939 MULTI_ARG_2_DI_CMP,
20940 MULTI_ARG_2_SI_CMP,
20941 MULTI_ARG_2_HI_CMP,
20942 MULTI_ARG_2_QI_CMP,
20943 MULTI_ARG_2_DI_TF,
20944 MULTI_ARG_2_SI_TF,
20945 MULTI_ARG_2_HI_TF,
20946 MULTI_ARG_2_QI_TF,
20947 MULTI_ARG_2_SF_TF,
20948 MULTI_ARG_2_DF_TF,
20949 MULTI_ARG_1_SF,
20950 MULTI_ARG_1_DF,
20951 MULTI_ARG_1_DI,
20952 MULTI_ARG_1_SI,
20953 MULTI_ARG_1_HI,
20954 MULTI_ARG_1_QI,
20955 MULTI_ARG_1_SI_DI,
20956 MULTI_ARG_1_HI_DI,
20957 MULTI_ARG_1_HI_SI,
20958 MULTI_ARG_1_QI_DI,
20959 MULTI_ARG_1_QI_SI,
20960 MULTI_ARG_1_QI_HI,
20961 MULTI_ARG_1_PH2PS,
20962 MULTI_ARG_1_PS2PH
20963 };
20966 {
20967 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
20968 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
20969 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
20970 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
20971 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
20972 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
20973 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
20974 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
20975 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
20976 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
20977 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
20978 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
20979 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
20980 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
20981 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
20982 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
20983 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
20984 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
20985 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
20986 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
20987 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
20988 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
20989 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
20990 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
20991 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
20992 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
20993 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
20994 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
20995 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20996 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
20997 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
20998 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
20999 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21000 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21001 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21002 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21003 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21004 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21005 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21006 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21007 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21008 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21009 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21010 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21011 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21012 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21013 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21014 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21015 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21016 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21017 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21018 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21019 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21020 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21021 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21022 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21023 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21024 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21025 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21026 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21027 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21028 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21029 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21030 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21031 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21032 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21033 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21034 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21035 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21036 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21037 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21038 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21039 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21040 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21043 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21046 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21048 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21052 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21053 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21054 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21055 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21056 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21057 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21058 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21060 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21061 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21062 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21063 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21064 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21065 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21066 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21067 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21068 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21069 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21070 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21071 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21072 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21073 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21074 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21075 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21077 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21078 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21079 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21080 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21081 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21082 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21083 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21084 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21085 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21086 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21087 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21088 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21089 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21090 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21091 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21092 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21094 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21095 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21096 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21097 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21098 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21099 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21100 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21101 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21102 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21103 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21104 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21105 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21106 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21107 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21108 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21109 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21111 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21112 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21113 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21114 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21115 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21116 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21117 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21119 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21120 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21121 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21122 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21123 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21124 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21125 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21127 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21128 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21129 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21130 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21131 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21132 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21133 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21135 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21136 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21137 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21138 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21139 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21140 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21141 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21143 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21144 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21145 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21146 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21147 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21148 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21149 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21151 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21152 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21153 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21154 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21155 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21156 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21157 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21159 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21160 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21161 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21162 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21163 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21164 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21165 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21167 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21168 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21169 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21170 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21171 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21172 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21173 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21175 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21176 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21177 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21178 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21179 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21180 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21181 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21182 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21184 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21185 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21186 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21187 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21188 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21189 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21190 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21191 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21193 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21194 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21195 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21196 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21197 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21198 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21199 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21200 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21201 };
21203 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21204 in the current target ISA to allow the user to compile particular modules
21205 with different target specific options that differ from the command line
21206 options. */
21207 static void
21209 {
21215 tree V1DI_type_node
21218 tree V2DI_type_node
21228 tree pcchar_type_node
21231 tree pcfloat_type_node
21234 tree pcv2sf_type_node
21239 /* Comparisons. */
21240 tree int_ftype_v4sf_v4sf
21243 tree v4si_ftype_v4sf_v4sf
21246 /* MMX/SSE/integer conversions. */
21247 tree int_ftype_v4sf
21250 tree int64_ftype_v4sf
21253 tree int_ftype_v8qi
21255 tree v4sf_ftype_v4sf_int
21258 tree v4sf_ftype_v4sf_int64
21261 NULL_TREE);
21262 tree v4sf_ftype_v4sf_v2si
21266 /* Miscellaneous. */
21267 tree v8qi_ftype_v4hi_v4hi
21270 tree v4hi_ftype_v2si_v2si
21273 tree v4sf_ftype_v4sf_v4sf_int
21277 tree v2si_ftype_v4hi_v4hi
21280 tree v4hi_ftype_v4hi_int
21283 tree v2si_ftype_v2si_int
21286 tree v1di_ftype_v1di_int
21290 tree void_ftype_void
21292 tree void_ftype_unsigned
21294 tree void_ftype_unsigned_unsigned
21297 tree void_ftype_pcvoid_unsigned_unsigned
21300 NULL_TREE);
21301 tree unsigned_ftype_void
21303 tree v2si_ftype_v4sf
21305 /* Loads/stores. */
21306 tree void_ftype_v8qi_v8qi_pchar
21310 tree v4sf_ftype_pcfloat
21312 tree v4sf_ftype_v4sf_pcv2sf
21315 tree void_ftype_pv2sf_v4sf
21318 tree void_ftype_pfloat_v4sf
21321 tree void_ftype_pdi_di
21324 NULL_TREE);
21325 tree void_ftype_pv2di_v2di
21328 /* Normal vector unops. */
21329 tree v4sf_ftype_v4sf
21331 tree v16qi_ftype_v16qi
21333 tree v8hi_ftype_v8hi
21335 tree v4si_ftype_v4si
21337 tree v8qi_ftype_v8qi
21339 tree v4hi_ftype_v4hi
21342 /* Normal vector binops. */
21343 tree v4sf_ftype_v4sf_v4sf
21346 tree v8qi_ftype_v8qi_v8qi
21349 tree v4hi_ftype_v4hi_v4hi
21352 tree v2si_ftype_v2si_v2si
21355 tree v1di_ftype_v1di_v1di
21358 tree v1di_ftype_v1di_v1di_int
21362 tree v2si_ftype_v2sf
21364 tree v2sf_ftype_v2si
21366 tree v2si_ftype_v2si
21368 tree v2sf_ftype_v2sf
21370 tree v2sf_ftype_v2sf_v2sf
21373 tree v2si_ftype_v2sf_v2sf
21380 tree int_ftype_v2df_v2df
21384 tree void_ftype_pcvoid
21386 tree v4sf_ftype_v4si
21388 tree v4si_ftype_v4sf
21390 tree v2df_ftype_v4si
21392 tree v4si_ftype_v2df
21394 tree v4si_ftype_v2df_v2df
21397 tree v2si_ftype_v2df
21399 tree v4sf_ftype_v2df
21401 tree v2df_ftype_v2si
21403 tree v2df_ftype_v4sf
21405 tree int_ftype_v2df
21407 tree int64_ftype_v2df
21410 tree v2df_ftype_v2df_int
21413 tree v2df_ftype_v2df_int64
21416 NULL_TREE);
21417 tree v4sf_ftype_v4sf_v2df
21420 tree v2df_ftype_v2df_v4sf
21423 tree v2df_ftype_v2df_v2df_int
21426 integer_type_node,
21427 NULL_TREE);
21428 tree v2df_ftype_v2df_pcdouble
21431 tree void_ftype_pdouble_v2df
21434 tree void_ftype_pint_int
21437 tree void_ftype_v16qi_v16qi_pchar
21441 tree v2df_ftype_pcdouble
21443 tree v2df_ftype_v2df_v2df
21446 tree v16qi_ftype_v16qi_v16qi
21449 tree v8hi_ftype_v8hi_v8hi
21452 tree v4si_ftype_v4si_v4si
21455 tree v2di_ftype_v2di_v2di
21458 tree v2di_ftype_v2df_v2df
21461 tree v2df_ftype_v2df
21463 tree v2di_ftype_v2di_int
21466 tree v2di_ftype_v2di_v2di_int
21469 tree v4si_ftype_v4si_int
21472 tree v8hi_ftype_v8hi_int
21475 tree v4si_ftype_v8hi_v8hi
21478 tree v1di_ftype_v8qi_v8qi
21481 tree v1di_ftype_v2si_v2si
21484 tree v2di_ftype_v16qi_v16qi
21487 tree v2di_ftype_v4si_v4si
21490 tree int_ftype_v16qi
21492 tree v16qi_ftype_pcchar
21494 tree void_ftype_pchar_v16qi
21498 tree v2di_ftype_v2di_unsigned_unsigned
21501 NULL_TREE);
21502 tree v2di_ftype_v2di_v2di_unsigned_unsigned
21505 NULL_TREE);
21506 tree v2di_ftype_v2di_v16qi
21508 NULL_TREE);
21509 tree v2df_ftype_v2df_v2df_v2df
21513 tree v4sf_ftype_v4sf_v4sf_v4sf
21517 tree v8hi_ftype_v16qi
21519 NULL_TREE);
21520 tree v4si_ftype_v16qi
21522 NULL_TREE);
21523 tree v2di_ftype_v16qi
21525 NULL_TREE);
21526 tree v4si_ftype_v8hi
21528 NULL_TREE);
21529 tree v2di_ftype_v8hi
21531 NULL_TREE);
21532 tree v2di_ftype_v4si
21534 NULL_TREE);
21535 tree v2di_ftype_pv2di
21537 NULL_TREE);
21538 tree v16qi_ftype_v16qi_v16qi_int
21541 NULL_TREE);
21542 tree v16qi_ftype_v16qi_v16qi_v16qi
21545 NULL_TREE);
21546 tree v8hi_ftype_v8hi_v8hi_int
21549 NULL_TREE);
21550 tree v4si_ftype_v4si_v4si_int
21553 NULL_TREE);
21554 tree int_ftype_v2di_v2di
21557 NULL_TREE);
21558 tree int_ftype_v16qi_int_v16qi_int_int
21560 V16QI_type_node,
21561 integer_type_node,
21562 V16QI_type_node,
21563 integer_type_node,
21564 integer_type_node,
21565 NULL_TREE);
21566 tree v16qi_ftype_v16qi_int_v16qi_int_int
21568 V16QI_type_node,
21569 integer_type_node,
21570 V16QI_type_node,
21571 integer_type_node,
21572 integer_type_node,
21573 NULL_TREE);
21574 tree int_ftype_v16qi_v16qi_int
21576 V16QI_type_node,
21577 V16QI_type_node,
21578 integer_type_node,
21579 NULL_TREE);
21581 /* SSE5 instructions */
21582 tree v2di_ftype_v2di_v2di_v2di
21584 V2DI_type_node,
21585 V2DI_type_node,
21586 V2DI_type_node,
21587 NULL_TREE);
21589 tree v4si_ftype_v4si_v4si_v4si
21591 V4SI_type_node,
21592 V4SI_type_node,
21593 V4SI_type_node,
21594 NULL_TREE);
21596 tree v4si_ftype_v4si_v4si_v2di
21598 V4SI_type_node,
21599 V4SI_type_node,
21600 V2DI_type_node,
21601 NULL_TREE);
21603 tree v8hi_ftype_v8hi_v8hi_v8hi
21605 V8HI_type_node,
21606 V8HI_type_node,
21607 V8HI_type_node,
21608 NULL_TREE);
21610 tree v8hi_ftype_v8hi_v8hi_v4si
21612 V8HI_type_node,
21613 V8HI_type_node,
21614 V4SI_type_node,
21615 NULL_TREE);
21617 tree v2df_ftype_v2df_v2df_v16qi
21619 V2DF_type_node,
21620 V2DF_type_node,
21621 V16QI_type_node,
21622 NULL_TREE);
21624 tree v4sf_ftype_v4sf_v4sf_v16qi
21626 V4SF_type_node,
21627 V4SF_type_node,
21628 V16QI_type_node,
21629 NULL_TREE);
21631 tree v2di_ftype_v2di_si
21633 V2DI_type_node,
21634 integer_type_node,
21635 NULL_TREE);
21637 tree v4si_ftype_v4si_si
21639 V4SI_type_node,
21640 integer_type_node,
21641 NULL_TREE);
21643 tree v8hi_ftype_v8hi_si
21645 V8HI_type_node,
21646 integer_type_node,
21647 NULL_TREE);
21649 tree v16qi_ftype_v16qi_si
21651 V16QI_type_node,
21652 integer_type_node,
21653 NULL_TREE);
21654 tree v4sf_ftype_v4hi
21656 V4HI_type_node,
21657 NULL_TREE);
21659 tree v4hi_ftype_v4sf
21661 V4SF_type_node,
21662 NULL_TREE);
21664 tree v2di_ftype_v2di
21667 tree v16qi_ftype_v8hi_v8hi
21670 NULL_TREE);
21671 tree v8hi_ftype_v4si_v4si
21674 NULL_TREE);
21675 tree v8hi_ftype_v16qi_v16qi
21678 NULL_TREE);
21679 tree v4hi_ftype_v8qi_v8qi
21682 NULL_TREE);
21683 tree unsigned_ftype_unsigned_uchar
21685 unsigned_type_node,
21686 unsigned_char_type_node,
21687 NULL_TREE);
21688 tree unsigned_ftype_unsigned_ushort
21690 unsigned_type_node,
21691 short_unsigned_type_node,
21692 NULL_TREE);
21693 tree unsigned_ftype_unsigned_unsigned
21695 unsigned_type_node,
21696 unsigned_type_node,
21697 NULL_TREE);
21698 tree uint64_ftype_uint64_uint64
21700 long_long_unsigned_type_node,
21701 long_long_unsigned_type_node,
21702 NULL_TREE);
21703 tree float_ftype_float
21705 float_type_node,
21706 NULL_TREE);
21708 /* AVX builtins */
21710 V32QImode);
21712 V8SImode);
21714 V8SFmode);
21716 V4DImode);
21718 V4DFmode);
21719 tree v8sf_ftype_v8sf
21721 V8SF_type_node,
21722 NULL_TREE);
21723 tree v8si_ftype_v8sf
21725 V8SF_type_node,
21726 NULL_TREE);
21727 tree v8sf_ftype_v8si
21729 V8SI_type_node,
21730 NULL_TREE);
21731 tree v4si_ftype_v4df
21733 V4DF_type_node,
21734 NULL_TREE);
21735 tree v4df_ftype_v4df
21737 V4DF_type_node,
21738 NULL_TREE);
21739 tree v4df_ftype_v4si
21741 V4SI_type_node,
21742 NULL_TREE);
21743 tree v4df_ftype_v4sf
21745 V4SF_type_node,
21746 NULL_TREE);
21747 tree v4sf_ftype_v4df
21749 V4DF_type_node,
21750 NULL_TREE);
21751 tree v8sf_ftype_v8sf_v8sf
21754 NULL_TREE);
21755 tree v4df_ftype_v4df_v4df
21758 NULL_TREE);
21759 tree v8sf_ftype_v8sf_int
21762 NULL_TREE);
21763 tree v4si_ftype_v8si_int
21766 NULL_TREE);
21767 tree v4df_ftype_v4df_int
21770 NULL_TREE);
21771 tree v4sf_ftype_v8sf_int
21774 NULL_TREE);
21775 tree v2df_ftype_v4df_int
21778 NULL_TREE);
21779 tree v8sf_ftype_v8sf_v8sf_int
21782 integer_type_node,
21783 NULL_TREE);
21784 tree v8sf_ftype_v8sf_v8sf_v8sf
21787 V8SF_type_node,
21788 NULL_TREE);
21789 tree v4df_ftype_v4df_v4df_v4df
21792 V4DF_type_node,
21793 NULL_TREE);
21794 tree v8si_ftype_v8si_v8si_int
21797 integer_type_node,
21798 NULL_TREE);
21799 tree v4df_ftype_v4df_v4df_int
21802 integer_type_node,
21803 NULL_TREE);
21804 tree v8sf_ftype_v8sf_v8sf_v8si_int
21808 NULL_TREE);
21809 tree v4df_ftype_v4df_v4df_v4di_int
21813 NULL_TREE);
21814 tree v4sf_ftype_v4sf_v4sf_v4si_int
21818 NULL_TREE);
21819 tree v2df_ftype_v2df_v2df_v2di_int
21823 NULL_TREE);
21824 tree v8sf_ftype_pcfloat
21826 pcfloat_type_node,
21827 NULL_TREE);
21828 tree v4df_ftype_pcdouble
21830 pcdouble_type_node,
21831 NULL_TREE);
21832 tree pcv4sf_type_node
21834 tree pcv2df_type_node
21836 tree v8sf_ftype_pcv4sf
21838 pcv4sf_type_node,
21839 NULL_TREE);
21840 tree v4df_ftype_pcv2df
21842 pcv2df_type_node,
21843 NULL_TREE);
21844 tree v32qi_ftype_pcchar
21846 pcchar_type_node,
21847 NULL_TREE);
21848 tree void_ftype_pchar_v32qi
21851 NULL_TREE);
21852 tree v8si_ftype_v8si_v4si_int
21855 integer_type_node,
21856 NULL_TREE);
21857 tree v8sf_ftype_v8sf_v4sf_int
21860 integer_type_node,
21861 NULL_TREE);
21862 tree v4df_ftype_v4df_v2df_int
21865 integer_type_node,
21866 NULL_TREE);
21867 tree void_ftype_pfloat_v8sf
21870 NULL_TREE);
21871 tree void_ftype_pdouble_v4df
21874 NULL_TREE);
21879 tree pcv8sf_type_node
21881 tree pcv4df_type_node
21883 tree v8sf_ftype_pcv8sf_v8sf
21886 NULL_TREE);
21887 tree v4df_ftype_pcv4df_v4df
21890 NULL_TREE);
21891 tree v4sf_ftype_pcv4sf_v4sf
21894 NULL_TREE);
21895 tree v2df_ftype_pcv2df_v2df
21898 NULL_TREE);
21899 tree void_ftype_pv8sf_v8sf_v8sf
21902 V8SF_type_node,
21903 NULL_TREE);
21904 tree void_ftype_pv4df_v4df_v4df
21907 V4DF_type_node,
21908 NULL_TREE);
21909 tree void_ftype_pv4sf_v4sf_v4sf
21912 V4SF_type_node,
21913 NULL_TREE);
21914 tree void_ftype_pv2df_v2df_v2df
21917 V2DF_type_node,
21918 NULL_TREE);
21919 tree v4df_ftype_v2df
21921 V2DF_type_node,
21922 NULL_TREE);
21923 tree v8sf_ftype_v4sf
21925 V4SF_type_node,
21926 NULL_TREE);
21927 tree v8si_ftype_v4si
21929 V4SI_type_node,
21930 NULL_TREE);
21931 tree v2df_ftype_v4df
21933 V4DF_type_node,
21934 NULL_TREE);
21935 tree v4sf_ftype_v8sf
21937 V8SF_type_node,
21938 NULL_TREE);
21939 tree v4si_ftype_v8si
21941 V8SI_type_node,
21942 NULL_TREE);
21943 tree int_ftype_v4df
21945 V4DF_type_node,
21946 NULL_TREE);
21947 tree int_ftype_v8sf
21949 V8SF_type_node,
21950 NULL_TREE);
21951 tree int_ftype_v8sf_v8sf
21954 NULL_TREE);
21955 tree int_ftype_v4di_v4di
21958 NULL_TREE);
21959 tree int_ftype_v4df_v4df
21962 NULL_TREE);
21963 tree v8sf_ftype_v8sf_v8si
21966 NULL_TREE);
21967 tree v4df_ftype_v4df_v4di
21970 NULL_TREE);
21971 tree v4sf_ftype_v4sf_v4si
21974 tree v2df_ftype_v2df_v2di
21978 tree ftype;
21980 /* Add all special builtins with variable number of operands. */
21984 {
21985 tree type;
21991 {
22084 }
22087 }
22089 /* Add all builtins with variable number of operands. */
22093 {
22094 tree type;
22100 {
22541 }
22544 }
22546 /* pcmpestr[im] insns. */
22550 {
22553 else
22556 }
22558 /* pcmpistr[im] insns. */
22562 {
22565 else
22568 }
22570 /* comi/ucomi insns. */
22574 else
22577 /* SSE */
22578 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
22579 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
22581 /* SSE or 3DNow!A */
22582 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
22584 /* SSE2 */
22585 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
22587 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
22588 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
22590 /* SSE3. */
22591 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
22592 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
22594 /* AES */
22595 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
22596 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
22597 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
22598 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
22599 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
22600 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
22602 /* PCLMUL */
22603 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
22605 /* AVX */
22609 /* Access to the vec_init patterns. */
22612 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
22615 short_integer_type_node,
22616 short_integer_type_node,
22618 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
22625 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
22627 /* Access to the vec_extract patterns. */
22630 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
22634 NULL_TREE);
22635 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
22639 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
22643 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
22647 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
22651 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
22655 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
22659 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
22661 /* Access to the vec_set patterns. */
22663 intDI_type_node,
22665 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
22668 float_type_node,
22670 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
22673 intSI_type_node,
22675 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
22678 intHI_type_node,
22680 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
22683 intHI_type_node,
22685 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
22688 intQI_type_node,
22690 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
22692 /* Add SSE5 multi-arg argument instructions */
22694 {
22701 {
22751 }
22755 }
22756 }
22758 /* Internal method for ix86_init_builtins. */
22760 static void
22762 {
22774 sysv_va_ref =
22777 fnvoid_va_end_ms =
22779 fnvoid_va_start_ms =
22781 fnvoid_va_end_sysv =
22783 fnvoid_va_start_sysv =
22785 NULL_TREE);
22786 fnvoid_va_copy_ms =
22788 NULL_TREE);
22789 fnvoid_va_copy_sysv =
22805 }
22807 static void
22809 {
22813 /* The __float80 type. */
22817 else
22818 {
22819 /* The __float80 type. */
22826 }
22828 /* The __float128 type. */
22834 /* TFmode support builtins. */
22841 /* We will expand them to normal call if SSE2 isn't available since
22842 they are used by libgcc. */
22844 float128_type_node,
22845 NULL_TREE);
22853 float128_type_node,
22854 float128_type_node,
22855 NULL_TREE);
22865 }
22867 /* Errors in the source file can cause expand_expr to return const0_rtx
22868 where we expect a vector. To avoid crashing, use one of the vector
22869 clear instructions. */
22870 static rtx
22872 {
22876 }
22878 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
22880 static rtx
22882 {
22883 rtx pat;
22903 {
22907 }
22921 }
22923 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
22925 static rtx
22929 {
22930 rtx pat;
22938 rtx op;
22945 {
23016 }
23026 {
23033 {
23035 {
23038 }
23039 }
23040 else
23041 {
23045 /* If we aren't optimizing, only allow one memory operand to be
23046 generated. */
23048 num_memory++;
23056 }
23060 }
23063 {
23074 else
23075 {
23081 }
23090 }
23097 }
23099 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23100 insns with vec_merge. */
23102 static rtx
23104 rtx target)
23105 {
23106 rtx pat;
23133 }
23135 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23137 static rtx
23140 {
23141 rtx pat;
23146 rtx op2;
23157 /* Swap operands if we have a comparison that isn't available in
23158 hardware. */
23160 {
23165 }
23185 }
23187 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23189 static rtx
23191 rtx target)
23192 {
23193 rtx pat;
23207 /* Swap operands if we have a comparison that isn't available in
23208 hardware. */
23210 {
23214 }
23235 const0_rtx)));
23238 }
23240 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23242 static rtx
23244 rtx target)
23245 {
23246 rtx pat;
23279 const0_rtx)));
23282 }
23284 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23286 static rtx
23289 {
23290 rtx pat;
23328 {
23331 }
23334 {
23343 }
23345 {
23354 }
23355 else
23356 {
23363 }
23371 {
23376 emit_insn
23380 FLAGS_REG),
23381 const0_rtx)));
23383 }
23384 else
23386 }
23389 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23391 static rtx
23394 {
23395 rtx pat;
23423 {
23426 }
23429 {
23438 }
23440 {
23449 }
23450 else
23451 {
23458 }
23466 {
23471 emit_insn
23475 FLAGS_REG),
23476 const0_rtx)));
23478 }
23479 else
23481 }
23483 /* Subroutine of ix86_expand_builtin to take care of insns with
23484 variable number of operands. */
23486 static rtx
23489 {
23494 struct
23495 {
23496 rtx op;
23508 {
23713 }
23718 {
23721 }
23724 {
23731 }
23732 else
23733 {
23736 }
23739 {
23746 {
23747 /* SIMD shift insns take either an 8-bit immediate or
23748 register as count. But builtin functions take int as
23749 count. If count doesn't match, we put it in register. */
23751 {
23755 }
23756 }
23758 {
23761 {
23803 {
23806 {
23809 }
23815 }
23817 }
23818 }
23819 else
23820 {
23824 /* If we aren't optimizing, only allow one memory operand to
23825 be generated. */
23827 num_memory++;
23830 {
23833 }
23834 else
23835 {
23838 }
23839 }
23843 }
23846 {
23863 }
23870 }
23872 /* Subroutine of ix86_expand_builtin to take care of special insns
23873 with variable number of operands. */
23875 static rtx
23878 {
23879 tree arg;
23882 struct
23883 {
23884 rtx op;
23894 {
23923 /* Reserve memory operand for target. */
23946 /* Reserve memory operand for target. */
23951 }
23956 {
23962 }
23963 else
23964 {
23971 }
23974 {
23983 {
23986 {
23990 }
23991 }
23992 else
23993 {
23995 {
23996 /* This must be the memory operand. */
24000 }
24001 else
24002 {
24003 /* This must be register. */
24010 }
24011 }
24015 }
24018 {
24027 }
24033 }
24035 /* Return the integer constant in ARG. Constrain it to be in the range
24036 of the subparts of VEC_TYPE; issue an error if not. */
24038 static int
24040 {
24045 {
24048 }
24051 }
24053 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24054 ix86_expand_vector_init. We DO have language-level syntax for this, in
24055 the form of (type){ init-list }. Except that since we can't place emms
24056 instructions from inside the compiler, we can't allow the use of MMX
24057 registers unless the user explicitly asks for it. So we do *not* define
24058 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24059 we have builtins invoked by mmintrin.h that gives us license to emit
24060 these sorts of instructions. */
24062 static rtx
24064 {
24074 {
24077 }
24084 }
24086 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24087 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24088 had a language-level syntax for referencing vector elements. */
24090 static rtx
24092 {
24096 rtx op0;
24116 }
24118 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24119 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24120 a language-level syntax for referencing vector elements. */
24122 static rtx
24124 {
24148 /* OP0 is the source of these builtin functions and shouldn't be
24149 modified. Create a copy, use it and return it as target. */
24155 }
24157 /* Expand an expression EXP that calls a built-in function,
24158 with result going to TARGET if that's convenient
24159 (and in mode MODE if that's convenient).
24160 SUBTARGET may be used as the target for computing one of EXP's operands.
24161 IGNORE is nonzero if the value is to be ignored. */
24163 static rtx
24167 {
24177 /* Determine whether the builtin function is available under the current ISA.
24178 Originally the builtin was not created if it wasn't applicable to the
24179 current ISA based on the command line switches. With function specific
24180 options, we need to check in the context of the function making the call
24181 whether it is supported. */
24184 {
24190 else
24191 {
24195 }
24197 }
24200 {
24204 ? CODE_FOR_mmx_maskmovq
24206 /* Note the arg order is different from the operand order. */
24306 {
24307 REAL_VALUE_TYPE inf;
24308 rtx tmp;
24320 }
24324 }
24337 {
24341 /* Emit a normal call if SSE2 isn't available. */
24345 }
24370 }
24372 /* Returns a function decl for a vectorized version of the builtin function
24373 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24374 if it is not available. */
24376 static tree
24378 tree type_in)
24379 {
24393 {
24419 ;
24420 }
24422 /* Dispatch to a handler for a vectorization library. */
24427 }
24429 /* Handler for an SVML-style interface to
24430 a library with vectorized intrinsics. */
24432 static tree
24434 {
24442 /* The SVML is suitable for unsafe math only. */
24455 {
24502 }
24511 {
24514 }
24515 else
24518 /* Convert to uppercase. */
24524 arity++;
24528 else
24531 /* Build a function declaration for the vectorized function. */
24539 }
24541 /* Handler for an ACML-style interface to
24542 a library with vectorized intrinsics. */
24544 static tree
24546 {
24554 /* The ACML is 64bits only and suitable for unsafe math only as
24555 it does not correctly support parts of IEEE with the required
24556 precision such as denormals. */
24570 {
24600 }
24608 arity++;
24612 else
24615 /* Build a function declaration for the vectorized function. */
24623 }
24626 /* Returns a decl of a function that implements conversion of an integer vector
24627 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24628 side of the conversion.
24629 Return NULL_TREE if it is not available. */
24631 static tree
24633 {
24638 {
24641 {
24646 }
24650 {
24655 }
24659 }
24660 }
24662 /* Returns a code for a target-specific builtin that implements
24663 reciprocal of the function, or NULL_TREE if not available. */
24665 static tree
24668 {
24675 /* Machine dependent builtins. */
24677 {
24678 /* Vectorized version of sqrt to rsqrt conversion. */
24684 }
24685 else
24686 /* Normal builtins. */
24688 {
24689 /* Sqrt to rsqrt conversion. */
24695 }
24696 }
24698 /* Store OPERAND to the memory after reload is completed. This means
24699 that we can't easily use assign_stack_local. */
24700 rtx
24702 {
24703 rtx result;
24707 {
24710 stack_pointer_rtx,
24713 }
24715 {
24717 {
24721 /* FALLTHRU */
24727 stack_pointer_rtx)),
24728 operand));
24732 }
24734 }
24735 else
24736 {
24738 {
24740 {
24747 stack_pointer_rtx)),
24753 stack_pointer_rtx)),
24755 }
24758 /* Store HImodes as SImodes. */
24760 /* FALLTHRU */
24766 stack_pointer_rtx)),
24767 operand));
24771 }
24773 }
24775 }
24777 /* Free operand from the memory. */
24778 void
24780 {
24782 {
24787 else
24789 /* Use LEA to deallocate stack space. In peephole2 it will be converted
24790 to pop or add instruction if registers are available. */
24794 }
24795 }
24797 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
24798 QImode must go into class Q_REGS.
24799 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
24800 movdf to do mem-to-mem moves through integer regs. */
24801 enum reg_class
24803 {
24806 /* We're only allowed to return a subclass of CLASS. Many of the
24807 following checks fail for NO_REGS, so eliminate that early. */
24811 /* All classes can load zeros. */
24815 /* Force constants into memory if we are loading a (nonzero) constant into
24816 an MMX or SSE register. This is because there are no MMX/SSE instructions
24817 to load from a constant. */
24822 /* Prefer SSE regs only, if we can use them for math. */
24826 /* Floating-point constants need more complex checks. */
24828 {
24829 /* General regs can load everything. */
24833 /* Floats can load 0 and 1 plus some others. Note that we eliminated
24834 zero above. We only want to wind up preferring 80387 registers if
24835 we plan on doing computation with them. */
24838 {
24839 /* Limit class to non-sse. */
24848 }
24851 }
24853 /* Generally when we see PLUS here, it's the function invariant
24854 (plus soft-fp const_int). Which can only be computed into general
24855 regs. */
24859 /* QImode constants are easy to load, but non-constant QImode data
24860 must go into Q_REGS. */
24862 {
24868 }
24871 }
24873 /* Discourage putting floating-point values in SSE registers unless
24874 SSE math is being used, and likewise for the 387 registers. */
24875 enum reg_class
24877 {
24880 /* Restrict the output reload class to the register bank that we are doing
24881 math on. If we would like not to return a subset of CLASS, reject this
24882 alternative: if reload cannot do this, it will still use its choice. */
24888 {
24893 else
24895 }
24898 }
24900 static enum reg_class
24904 {
24905 /* QImode spills from non-QI registers require
24906 intermediate register on 32bit targets. */
24911 {
24916 else
24922 /* Return Q_REGS if the operand is in memory. */
24925 }
24928 }
24930 /* If we are copying between general and FP registers, we need a memory
24931 location. The same is true for SSE and MMX registers.
24933 To optimize register_move_cost performance, allow inline variant.
24935 The macro can't work reliably when one of the CLASSES is class containing
24936 registers from multiple units (SSE, MMX, integer). We avoid this by never
24937 combining those units in single alternative in the machine description.
24938 Ensure that this constraint holds to avoid unexpected surprises.
24940 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
24941 enforce these sanity checks. */
24946 {
24953 {
24956 }
24961 /* ??? This is a lie. We do have moves between mmx/general, and for
24962 mmx/sse2. But by saying we need secondary memory we discourage the
24963 register allocator from using the mmx registers unless needed. */
24968 {
24969 /* SSE1 doesn't have any direct moves from other classes. */
24973 /* If the target says that inter-unit moves are more expensive
24974 than moving through memory, then don't generate them. */
24978 /* Between SSE and general, we have moves no larger than word size. */
24981 }
24984 }
24986 int
24989 {
24991 }
24993 /* Return true if the registers in CLASS cannot represent the change from
24994 modes FROM to TO. */
24996 bool
24999 {
25003 /* x87 registers can't do subreg at all, as all values are reformatted
25004 to extended precision. */
25009 {
25010 /* Vector registers do not support QI or HImode loads. If we don't
25011 disallow a change to these modes, reload will assume it's ok to
25012 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25013 the vec_dupv4hi pattern. */
25017 /* Vector registers do not support subreg with nonzero offsets, which
25018 are otherwise valid for integer registers. Since we can't see
25019 whether we have a nonzero offset from here, prohibit all
25020 nonparadoxical subregs changing size. */
25023 }
25026 }
25028 /* Return the cost of moving data of mode M between a
25029 register and memory. A value of 2 is the default; this cost is
25030 relative to those in `REGISTER_MOVE_COST'.
25032 This function is used extensively by register_move_cost that is used to
25033 build tables at startup. Make it inline in this case.
25034 When IN is 2, return maximum of in and out move cost.
25036 If moving between registers and memory is more expensive than
25037 between two registers, you should define this macro to express the
25038 relative cost.
25040 Model also increased moving costs of QImode registers in non
25041 Q_REGS classes.
25042 */
25046 {
25049 {
25052 {
25064 }
25068 }
25070 {
25073 {
25085 }
25089 }
25091 {
25094 {
25103 }
25107 }
25109 {
25112 {
25118 else
25123 }
25124 else
25125 {
25130 else
25132 }
25139 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25146 else
25150 }
25151 }
25153 int
25155 {
25157 }
25160 /* Return the cost of moving data from a register in class CLASS1 to
25161 one in class CLASS2.
25163 It is not required that the cost always equal 2 when FROM is the same as TO;
25164 on some machines it is expensive to move between registers if they are not
25165 general registers. */
25167 int
25170 {
25171 /* In case we require secondary memory, compute cost of the store followed
25172 by load. In order to avoid bad register allocation choices, we need
25173 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25176 {
25182 /* In case of copying from general_purpose_register we may emit multiple
25183 stores followed by single load causing memory size mismatch stall.
25184 Count this as arbitrarily high cost of 20. */
25188 /* In the case of FP/MMX moves, the registers actually overlap, and we
25189 have to switch modes in order to treat them differently. */
25195 }
25197 /* Moves between SSE/MMX and integer unit are expensive. */
25201 /* ??? By keeping returned value relatively high, we limit the number
25202 of moves between integer and MMX/SSE registers for all targets.
25203 Additionally, high value prevents problem with x86_modes_tieable_p(),
25204 where integer modes in MMX/SSE registers are not tieable
25205 because of missing QImode and HImode moves to, from or between
25206 MMX/SSE registers. */
25216 }
25218 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25220 bool
25222 {
25223 /* Flags and only flags can only hold CCmode values. */
25233 {
25234 /* We implement the move patterns for all vector modes into and
25235 out of SSE registers, even when no operation instructions
25236 are available. OImode move is available only when AVX is
25237 enabled. */
25244 }
25246 {
25247 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25248 so if the register is available at all, then we can move data of
25249 the given mode into or out of it. */
25252 }
25255 {
25256 /* Take care for QImode values - they can be in non-QI regs,
25257 but then they do cause partial register stalls. */
25263 }
25264 /* We handle both integer and floats in the general purpose registers. */
25271 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25272 on to use that value in smaller contexts, this can easily force a
25273 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25274 supporting DImode, allow it. */
25279 }
25281 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25282 tieable integer mode. */
25284 static bool
25286 {
25288 {
25301 }
25302 }
25304 /* Return true if MODE1 is accessible in a register that can hold MODE2
25305 without copying. That is, all register classes that can hold MODE2
25306 can also hold MODE1. */
25308 bool
25310 {
25318 /* MODE2 being XFmode implies fp stack or general regs, which means we
25319 can tie any smaller floating point modes to it. Note that we do not
25320 tie this with TFmode. */
25324 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25325 that we can tie it with SFmode. */
25329 /* If MODE2 is only appropriate for an SSE register, then tie with
25330 any other mode acceptable to SSE registers. */
25336 /* If MODE2 is appropriate for an MMX register, then tie
25337 with any other mode acceptable to MMX registers. */
25344 }
25346 /* Compute a (partial) cost for rtx X. Return true if the complete
25347 cost has been computed, and false if subexpressions should be
25348 scanned. In either case, *TOTAL contains the cost result. */
25350 static bool
25352 {
25358 {
25368 && (!TARGET_64BIT
25373 else
25380 else
25382 {
25391 /* Start with (MEM (SYMBOL_REF)), since that's where
25392 it'll probably end up. Add a penalty for size. */
25397 }
25401 /* The zero extensions is often completely free on x86_64, so make
25402 it as cheap as possible. */
25408 else
25419 {
25422 {
25425 }
25428 {
25431 }
25432 }
25433 /* FALLTHRU */
25440 {
25442 {
25445 else
25447 }
25448 else
25449 {
25452 else
25454 }
25455 }
25456 else
25457 {
25460 else
25462 }
25467 {
25468 /* ??? SSE scalar cost should be used here. */
25471 }
25473 {
25476 }
25478 {
25479 /* ??? SSE vector cost should be used here. */
25482 }
25483 else
25484 {
25489 {
25492 nbits++;
25493 }
25494 else
25495 /* This is arbitrary. */
25498 /* Compute costs correctly for widening multiplication. */
25502 {
25509 {
25513 else
25515 }
25519 }
25526 }
25533 /* ??? SSE cost should be used here. */
25538 /* ??? SSE vector cost should be used here. */
25540 else
25547 {
25552 {
25555 {
25562 }
25563 }
25566 {
25569 {
25574 }
25575 }
25577 {
25583 }
25584 }
25585 /* FALLTHRU */
25589 {
25590 /* ??? SSE cost should be used here. */
25593 }
25595 {
25598 }
25600 {
25601 /* ??? SSE vector cost should be used here. */
25604 }
25605 /* FALLTHRU */
25611 {
25618 }
25619 /* FALLTHRU */
25623 {
25624 /* ??? SSE cost should be used here. */
25627 }
25629 {
25632 }
25634 {
25635 /* ??? SSE vector cost should be used here. */
25638 }
25639 /* FALLTHRU */
25644 else
25653 {
25654 /* This kind of construct is implemented using test[bwl].
25655 Treat it as if we had an AND. */
25660 }
25670 /* ??? SSE cost should be used here. */
25675 /* ??? SSE vector cost should be used here. */
25681 /* ??? SSE cost should be used here. */
25686 /* ??? SSE vector cost should be used here. */
25697 }
25698 }
25700 #if TARGET_MACHO
25704 /* Given a symbol name and its associated stub, write out the
25705 definition of the stub. */
25707 void
25709 {
25714 /* For 64-bit we shouldn't get here. */
25717 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25732 else
25739 {
25743 }
25744 else
25750 {
25753 }
25754 else
25763 }
25765 void
25767 {
25770 }
25773 /* Order the registers for register allocator. */
25775 void
25777 {
25781 /* First allocate the local general purpose registers. */
25786 /* Global general purpose registers. */
25791 /* x87 registers come first in case we are doing FP math
25792 using them. */
25797 /* SSE registers. */
25803 /* x87 registers. */
25811 /* Initialize the rest of array as we do not allocate some registers
25812 at all. */
25815 }
25817 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
25818 struct attribute_spec.handler. */
25819 static tree
25821 tree args ATTRIBUTE_UNUSED,
25823 {
25828 {
25833 }
25835 {
25840 }
25842 /* Can combine regparm with all attributes but fastcall. */
25844 {
25846 {
25848 }
25851 }
25853 {
25855 {
25857 }
25860 }
25863 }
25865 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
25866 struct attribute_spec.handler. */
25867 static tree
25869 tree args ATTRIBUTE_UNUSED,
25871 {
25874 {
25877 }
25878 else
25883 {
25887 }
25893 {
25897 }
25900 }
25902 static bool
25904 {
25908 }
25910 /* Returns an expression indicating where the this parameter is
25911 located on entry to the FUNCTION. */
25913 static rtx
25915 {
25921 {
25926 else
25929 }
25934 {
25939 else
25940 {
25943 {
25948 }
25949 }
25951 }
25954 }
25956 /* Determine whether x86_output_mi_thunk can succeed. */
25958 static bool
25960 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
25962 {
25963 /* 64-bit can handle anything. */
25967 /* For 32-bit, everything's fine if we have one free register. */
25971 /* Need a free register for vcall_offset. */
25975 /* Need a free register for GOT references. */
25979 /* Otherwise ok. */
25981 }
25983 /* Output the assembler code for a thunk function. THUNK_DECL is the
25984 declaration for the thunk function itself, FUNCTION is the decl for
25985 the target function. DELTA is an immediate constant offset to be
25986 added to THIS. If VCALL_OFFSET is nonzero, the word at
25987 *(*this + vcall_offset) should be added to THIS. */
25989 static void
25993 {
25998 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
25999 pull it in now and let DELTA benefit. */
26003 {
26004 /* Put the this parameter into %eax. */
26008 }
26009 else
26012 /* Adjust the this parameter by a fixed constant. */
26014 {
26018 {
26020 {
26026 }
26028 }
26029 else
26031 }
26033 /* Adjust the this parameter by a value stored in the vtable. */
26035 {
26038 else
26039 {
26045 }
26051 /* Adjust the this parameter. */
26054 {
26060 }
26063 }
26065 /* If necessary, drop THIS back to its stack slot. */
26067 {
26071 }
26075 {
26078 /* All thunks should be in the same object as their target,
26079 and thus binds_local_p should be true. */
26082 else
26083 {
26089 }
26090 }
26091 else
26092 {
26095 else
26096 #if TARGET_MACHO
26098 {
26100 tmp = (gen_rtx_SYMBOL_REF
26106 }
26107 else
26109 {
26116 }
26117 }
26118 }
26120 static void
26122 {
26124 #if TARGET_MACHO
26126 #endif
26133 }
26135 int
26137 {
26149 }
26151 /* Output assembler code to FILE to increment profiler label # LABELNO
26152 for profiling a function entry. */
26153 void
26155 {
26157 {
26158 #ifndef NO_PROFILE_COUNTERS
26160 #endif
26164 else
26166 }
26168 {
26169 #ifndef NO_PROFILE_COUNTERS
26172 #endif
26174 }
26175 else
26176 {
26177 #ifndef NO_PROFILE_COUNTERS
26179 PROFILE_COUNT_REGISTER);
26180 #endif
26182 }
26183 }
26185 /* We don't have exact information about the insn sizes, but we may assume
26186 quite safely that we are informed about all 1 byte insns and memory
26187 address sizes. This is enough to eliminate unnecessary padding in
26188 99% of cases. */
26190 static int
26192 {
26198 /* Discard alignments we've emit and jump instructions. */
26207 /* Important case - calls are always 5 bytes.
26208 It is common to have many calls in the row. */
26216 /* For normal instructions we may rely on the sizes of addresses
26217 and the presence of symbol to require 4 bytes of encoding.
26218 This is not the case for jumps where references are PC relative. */
26220 {
26224 }
26227 else
26229 }
26231 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26232 window. */
26234 static void
26236 {
26241 /* Look for all minimal intervals of instructions containing 4 jumps.
26242 The intervals are bounded by START and INSN. NBYTES is the total
26243 size of instructions in the interval including INSN and not including
26244 START. When the NBYTES is smaller than 16 bytes, it is possible
26245 that the end of START and INSN ends up in the same 16byte page.
26247 The smallest offset in the page INSN can start is the case where START
26248 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26249 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26250 */
26252 {
26262 njumps++;
26263 else
26267 {
26274 else
26277 }
26284 {
26291 }
26292 }
26293 }
26295 /* AMD Athlon works faster
26296 when RET is not destination of conditional jump or directly preceded
26297 by other jump instruction. We avoid the penalty by inserting NOP just
26298 before the RET instructions in such cases. */
26299 static void
26301 {
26302 edge e;
26303 edge_iterator ei;
26306 {
26309 rtx prev;
26319 {
26320 edge e;
26321 edge_iterator ei;
26327 }
26329 {
26335 /* Empty functions get branch mispredict even when the jump destination
26336 is not visible to us. */
26339 }
26341 {
26344 }
26345 }
26346 }
26348 /* Implement machine specific optimizations. We implement padding of returns
26349 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26350 static void
26352 {
26359 }
26361 /* Return nonzero when QImode register that must be represented via REX prefix
26362 is used. */
26363 bool
26365 {
26373 }
26375 /* Return nonzero when P points to register encoded via REX prefix.
26376 Called via for_each_rtx. */
26377 static int
26379 {
26385 }
26387 /* Return true when INSN mentions register that must be encoded using REX
26388 prefix. */
26389 bool
26391 {
26394 }
26396 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26397 optabs would emit if we didn't have TFmode patterns. */
26399 void
26401 {
26435 }
26436 \f
26437 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26438 with all elements equal to VAR. Return true if successful. */
26440 static bool
26443 {
26445 rtx x;
26448 {
26453 /* FALLTHRU */
26468 {
26474 }
26475 else
26476 {
26481 }
26492 {
26494 /* Extend HImode to SImode using a paradoxical SUBREG. */
26497 /* Insert the SImode value as low element of V4SImode vector. */
26502 const1_rtx);
26504 /* Cast the V4SImode vector back to a V8HImode vector. */
26507 /* Duplicate the low short through the whole low SImode word. */
26509 /* Cast the V8HImode vector back to a V4SImode vector. */
26512 /* Replicate the low element of the V4SImode vector. */
26514 /* Cast the V2SImode back to V8HImode, and store in target. */
26517 }
26524 {
26526 /* Extend QImode to SImode using a paradoxical SUBREG. */
26529 /* Insert the SImode value as low element of V4SImode vector. */
26534 const1_rtx);
26536 /* Cast the V4SImode vector back to a V16QImode vector. */
26539 /* Duplicate the low byte through the whole low SImode word. */
26542 /* Cast the V16QImode vector back to a V4SImode vector. */
26545 /* Replicate the low element of the V4SImode vector. */
26547 /* Cast the V2SImode back to V16QImode, and store in target. */
26550 }
26555 widen:
26556 /* Replicate the value once into the next wider mode and recurse. */
26587 half:
26588 {
26593 }
26598 }
26599 }
26601 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26602 whose ONE_VAR element is VAR, and other elements are zero. Return true
26603 if successful. */
26605 static bool
26608 {
26610 rtx new_target;
26615 {
26617 /* For SSE4.1, we normally use vector set. But if the second
26618 element is zero and inter-unit moves are OK, we use movq
26619 instead. */
26620 use_vector_set = (TARGET_64BIT
26621 && TARGET_SSE4_1
26622 && !(TARGET_INTER_UNIT_MOVES
26646 }
26649 {
26654 }
26657 {
26662 /* FALLTHRU */
26677 else
26684 {
26685 /* We need to shuffle the value to the correct position, so
26686 create a new pseudo to store the intermediate result. */
26688 /* With SSE2, we can use the integer shuffle insns. */
26690 {
26699 }
26701 /* Otherwise convert the intermediate result to V4SFmode and
26702 use the SSE1 shuffle instructions. */
26704 {
26707 }
26708 else
26721 }
26736 widen:
26740 /* Zero extend the variable element to SImode and recurse. */
26753 }
26754 }
26756 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26757 consisting of the values in VALS. It is known that all elements
26758 except ONE_VAR are constants. Return true if successful. */
26760 static bool
26763 {
26773 {
26778 /* For the two element vectors, it's just as easy to use
26779 the general case. */
26802 widen:
26803 /* There's no way to set one QImode entry easily. Combine
26804 the variable value with its adjacent constant value, and
26805 promote to an HImode set. */
26808 {
26813 }
26814 else
26815 {
26818 }
26832 }
26837 }
26839 /* A subroutine of ix86_expand_vector_init_general. Use vector
26840 concatenate to handle the most general case: all values variable,
26841 and none identical. */
26843 static void
26846 {
26849 rtvec v;
26853 {
26856 {
26889 }
26902 {
26917 }
26922 {
26933 }
26936 half:
26937 /* FIXME: We process inputs backward to help RA. PR 36222. */
26941 {
26946 }
26950 {
26953 {
26957 }
26960 }
26961 else
26967 }
26968 }
26970 /* A subroutine of ix86_expand_vector_init_general. Use vector
26971 interleave to handle the most general case: all values variable,
26972 and none identical. */
26974 static void
26977 {
26986 {
27007 }
27010 {
27011 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27015 /* Insert the SImode value as low element of V4SImode vector. */
27019 op0),
27021 const1_rtx);
27024 /* Cast the V4SImode vector back to a vector in orignal mode. */
27028 /* Load even elements into the second positon. */
27032 const1_rtx));
27034 /* Cast vector to FIRST_IMODE vector. */
27037 }
27039 /* Interleave low FIRST_IMODE vectors. */
27041 {
27045 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27048 }
27050 /* Interleave low SECOND_IMODE vectors. */
27052 {
27055 {
27060 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27061 vector. */
27064 }
27067 /* FALLTHRU */
27074 /* Cast the SECOND_IMODE vector back to a vector on original
27075 mode. */
27082 }
27083 }
27085 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27086 all values variable, and none identical. */
27088 static void
27091 {
27097 {
27102 /* FALLTHRU */
27126 half:
27143 /* FALLTHRU */
27149 /* Don't use ix86_expand_vector_init_interleave if we can't
27150 move from GPR to SSE register directly. */
27166 }
27168 {
27180 {
27184 {
27190 else
27191 {
27196 }
27197 }
27200 }
27205 {
27211 }
27213 {
27219 }
27220 else
27222 }
27223 }
27225 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27226 instructions unless MMX_OK is true. */
27228 void
27230 {
27237 rtx x;
27240 {
27250 }
27252 /* Constants are best loaded from the constant pool. */
27254 {
27257 }
27259 /* If all values are identical, broadcast the value. */
27265 /* Values where only one field is non-constant are best loaded from
27266 the pool and overwritten via move later. */
27268 {
27272 one_var))
27277 }
27280 }
27282 void
27284 {
27289 rtx tmp;
27291 = {
27298 };
27300 = {
27307 };
27311 {
27315 {
27320 else
27324 }
27333 {
27336 /* For the two element vectors, we implement a VEC_CONCAT with
27337 the extraction of the other element. */
27344 else
27349 }
27358 {
27364 /* tmp = target = A B C D */
27366 /* target = A A B B */
27368 /* target = X A B B */
27370 /* target = A X C D */
27377 /* tmp = target = A B C D */
27379 /* tmp = X B C D */
27381 /* target = A B X D */
27388 /* tmp = target = A B C D */
27390 /* tmp = X B C D */
27392 /* target = A B X D */
27400 }
27408 /* Element 0 handled by vec_merge below. */
27410 {
27413 }
27416 {
27417 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27418 store into element 0, then shuffle them back. */
27435 }
27436 else
27437 {
27438 /* For SSE1, we have to reuse the V4SF code. */
27441 }
27494 half:
27495 /* Compute offset. */
27501 /* Extract the half. */
27505 /* Put val in tmp at elt. */
27508 /* Put it back. */
27514 }
27517 {
27521 }
27522 else
27523 {
27532 }
27533 }
27535 void
27537 {
27541 rtx tmp;
27544 {
27549 /* FALLTHRU */
27562 {
27582 }
27594 {
27596 {
27616 }
27620 }
27621 else
27622 {
27623 /* For SSE1, we have to reuse the V4SF code. */
27627 }
27642 /* ??? Could extract the appropriate HImode element and shift. */
27645 }
27648 {
27652 /* Let the rtl optimizers know about the zero extension performed. */
27654 {
27657 }
27660 }
27661 else
27662 {
27669 }
27670 }
27672 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27673 pattern to reduce; DEST is the destination; IN is the input vector. */
27675 void
27677 {
27691 }
27692 \f
27693 /* Target hook for scalar_mode_supported_p. */
27694 static bool
27696 {
27701 else
27703 }
27705 /* Implements target hook vector_mode_supported_p. */
27706 static bool
27708 {
27720 }
27722 /* Target hook for c_mode_for_suffix. */
27723 static enum machine_mode
27725 {
27732 }
27734 /* Worker function for TARGET_MD_ASM_CLOBBERS.
27736 We do this in the new i386 backend to maintain source compatibility
27737 with the old cc0-based compiler. */
27739 static tree
27741 tree inputs ATTRIBUTE_UNUSED,
27742 tree clobbers)
27743 {
27745 clobbers);
27747 clobbers);
27749 }
27751 /* Implements target vector targetm.asm.encode_section_info. This
27752 is not used by netware. */
27754 static void ATTRIBUTE_UNUSED
27756 {
27763 }
27765 /* Worker function for REVERSE_CONDITION. */
27767 enum rtx_code
27769 {
27773 }
27775 /* Output code to perform an x87 FP register move, from OPERANDS[1]
27776 to OPERANDS[0]. */
27780 {
27782 {
27785 {
27789 }
27793 }
27795 {
27799 else
27800 {
27801 /* There is no non-popping store to memory for XFmode.
27802 So if we need one, follow the store with a load. */
27805 else
27807 }
27808 }
27809 else
27811 }
27813 /* Output code to perform a conditional jump to LABEL, if C2 flag in
27814 FP status register is set. */
27816 void
27818 {
27820 rtx temp;
27825 {
27830 }
27831 else
27832 {
27837 }
27841 pc_rtx);
27846 }
27848 /* Output code to perform a log1p XFmode calculation. */
27851 {
27862 XFmode)));
27876 }
27878 /* Output code to perform a Newton-Rhapson approximation of a single precision
27879 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
27882 {
27897 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
27899 /* x0 = rcp(b) estimate */
27902 UNSPEC_RCP)));
27903 /* e0 = x0 * b */
27906 /* e1 = 2. - e0 */
27909 /* x1 = x0 * e1 */
27912 /* res = a * x1 */
27915 }
27917 /* Output code to perform a Newton-Rhapson approximation of a
27918 single precision floating point [reciprocal] square root. */
27922 {
27924 REAL_VALUE_TYPE r;
27939 {
27942 }
27944 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
27945 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
27947 /* x0 = rsqrt(a) estimate */
27950 UNSPEC_RSQRT)));
27952 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
27954 {
27966 }
27968 /* e0 = x0 * a */
27971 /* e1 = e0 * x0 */
27975 /* e2 = e1 - 3. */
27982 /* e3 = -.5 * x0 */
27985 else
27986 /* e3 = -.5 * e0 */
27989 /* ret = e2 * e3 */
27992 }
27994 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
27996 static void ATTRIBUTE_UNUSED
27998 tree decl)
27999 {
28000 /* With Binutils 2.15, the "@unwind" marker must be specified on
28001 every occurrence of the ".eh_frame" section, not just the first
28002 one. */
28005 {
28009 }
28011 }
28013 /* Return the mangling of TYPE if it is an extended fundamental type. */
28017 {
28025 {
28027 /* __float128 is "g". */
28030 /* "long double" or __float80 is "e". */
28034 }
28035 }
28037 /* For 32-bit code we can save PIC register setup by using
28038 __stack_chk_fail_local hidden function instead of calling
28039 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28040 register, so it is better to call __stack_chk_fail directly. */
28042 static tree
28044 {
28045 return TARGET_64BIT
28048 }
28050 /* Select a format to encode pointers in exception handling data. CODE
28051 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28052 true if the symbol may be affected by dynamic relocations.
28054 ??? All x86 object file formats are capable of representing this.
28055 After all, the relocation needed is the same as for the call insn.
28056 Whether or not a particular assembler allows us to enter such, I
28057 guess we'll have to see. */
28058 int
28060 {
28062 {
28069 }
28074 }
28075 \f
28076 /* Expand copysign from SIGN to the positive value ABS_VALUE
28077 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28078 the sign-bit. */
28079 static void
28081 {
28085 {
28088 {
28089 /* We need to generate a scalar mode mask in this case. */
28094 }
28095 }
28096 else
28102 }
28104 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28105 mask for masking out the sign-bit is stored in *SMASK, if that is
28106 non-null. */
28107 static rtx
28109 {
28116 {
28117 /* We need to generate a scalar mode mask in this case. */
28122 }
28130 }
28132 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28133 swapping the operands if SWAP_OPERANDS is true. The expanded
28134 code is a forward jump to a newly created label in case the
28135 comparison is true. The generated label rtx is returned. */
28136 static rtx
28139 {
28143 {
28147 }
28160 }
28162 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28163 using comparison code CODE. Operands are swapped for the comparison if
28164 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28165 static rtx
28168 {
28173 {
28177 }
28182 else
28187 }
28189 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28190 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28191 static rtx
28193 {
28194 REAL_VALUE_TYPE TWO52r;
28195 rtx TWO52;
28202 }
28204 /* Expand SSE sequence for computing lround from OP1 storing
28205 into OP0. */
28206 void
28208 {
28209 /* C code for the stuff we're doing below:
28210 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28211 return (long)tmp;
28212 */
28216 rtx adj;
28218 /* load nextafter (0.5, 0.0) */
28223 /* adj = copysign (0.5, op1) */
28227 /* adj = op1 + adj */
28230 /* op0 = (imode)adj */
28232 }
28234 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28235 into OPERAND0. */
28236 void
28238 {
28239 /* C code for the stuff we're doing below (for do_floor):
28240 xi = (long)op1;
28241 xi -= (double)xi > op1 ? 1 : 0;
28242 return xi;
28243 */
28248 /* reg = (long)op1 */
28252 /* freg = (double)reg */
28256 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28267 }
28269 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28270 result in OPERAND0. */
28271 void
28273 {
28274 /* C code for the stuff we're doing below:
28275 xa = fabs (operand1);
28276 if (!isless (xa, 2**52))
28277 return operand1;
28278 xa = xa + 2**52 - 2**52;
28279 return copysign (xa, operand1);
28280 */
28287 /* xa = abs (operand1) */
28290 /* if (!isless (xa, TWO52)) goto label; */
28303 }
28305 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28306 into OPERAND0. */
28307 void
28309 {
28310 /* C code for the stuff we expand below.
28311 double xa = fabs (x), x2;
28312 if (!isless (xa, TWO52))
28313 return x;
28314 xa = xa + TWO52 - TWO52;
28315 x2 = copysign (xa, x);
28316 Compensate. Floor:
28317 if (x2 > x)
28318 x2 -= 1;
28319 Compensate. Ceil:
28320 if (x2 < x)
28321 x2 -= -1;
28322 return x2;
28323 */
28329 /* Temporary for holding the result, initialized to the input
28330 operand to ease control flow. */
28334 /* xa = abs (operand1) */
28337 /* if (!isless (xa, TWO52)) goto label; */
28340 /* xa = xa + TWO52 - TWO52; */
28344 /* xa = copysign (xa, operand1) */
28347 /* generate 1.0 or -1.0 */
28352 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28356 /* We always need to subtract here to preserve signed zero. */
28365 }
28367 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28368 into OPERAND0. */
28369 void
28371 {
28372 /* C code for the stuff we expand below.
28373 double xa = fabs (x), x2;
28374 if (!isless (xa, TWO52))
28375 return x;
28376 x2 = (double)(long)x;
28377 Compensate. Floor:
28378 if (x2 > x)
28379 x2 -= 1;
28380 Compensate. Ceil:
28381 if (x2 < x)
28382 x2 += 1;
28383 if (HONOR_SIGNED_ZEROS (mode))
28384 return copysign (x2, x);
28385 return x2;
28386 */
28392 /* Temporary for holding the result, initialized to the input
28393 operand to ease control flow. */
28397 /* xa = abs (operand1) */
28400 /* if (!isless (xa, TWO52)) goto label; */
28403 /* xa = (double)(long)x */
28408 /* generate 1.0 */
28411 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28426 }
28428 /* Expand SSE sequence for computing round from OPERAND1 storing
28429 into OPERAND0. Sequence that works without relying on DImode truncation
28430 via cvttsd2siq that is only available on 64bit targets. */
28431 void
28433 {
28434 /* C code for the stuff we expand below.
28435 double xa = fabs (x), xa2, x2;
28436 if (!isless (xa, TWO52))
28437 return x;
28438 Using the absolute value and copying back sign makes
28439 -0.0 -> -0.0 correct.
28440 xa2 = xa + TWO52 - TWO52;
28441 Compensate.
28442 dxa = xa2 - xa;
28443 if (dxa <= -0.5)
28444 xa2 += 1;
28445 else if (dxa > 0.5)
28446 xa2 -= 1;
28447 x2 = copysign (xa2, x);
28448 return x2;
28449 */
28455 /* Temporary for holding the result, initialized to the input
28456 operand to ease control flow. */
28460 /* xa = abs (operand1) */
28463 /* if (!isless (xa, TWO52)) goto label; */
28466 /* xa2 = xa + TWO52 - TWO52; */
28470 /* dxa = xa2 - xa; */
28473 /* generate 0.5, 1.0 and -0.5 */
28479 /* Compensate. */
28481 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28486 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28492 /* res = copysign (xa2, operand1) */
28499 }
28501 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28502 into OPERAND0. */
28503 void
28505 {
28506 /* C code for SSE variant we expand below.
28507 double xa = fabs (x), x2;
28508 if (!isless (xa, TWO52))
28509 return x;
28510 x2 = (double)(long)x;
28511 if (HONOR_SIGNED_ZEROS (mode))
28512 return copysign (x2, x);
28513 return x2;
28514 */
28520 /* Temporary for holding the result, initialized to the input
28521 operand to ease control flow. */
28525 /* xa = abs (operand1) */
28528 /* if (!isless (xa, TWO52)) goto label; */
28531 /* x = (double)(long)x */
28543 }
28545 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28546 into OPERAND0. */
28547 void
28549 {
28553 /* C code for SSE variant we expand below.
28554 double xa = fabs (x), x2;
28555 if (!isless (xa, TWO52))
28556 return x;
28557 xa2 = xa + TWO52 - TWO52;
28558 Compensate:
28559 if (xa2 > xa)
28560 xa2 -= 1.0;
28561 x2 = copysign (xa2, x);
28562 return x2;
28563 */
28567 /* Temporary for holding the result, initialized to the input
28568 operand to ease control flow. */
28572 /* xa = abs (operand1) */
28575 /* if (!isless (xa, TWO52)) goto label; */
28578 /* res = xa + TWO52 - TWO52; */
28583 /* generate 1.0 */
28586 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28594 /* res = copysign (res, operand1) */
28601 }
28603 /* Expand SSE sequence for computing round from OPERAND1 storing
28604 into OPERAND0. */
28605 void
28607 {
28608 /* C code for the stuff we're doing below:
28609 double xa = fabs (x);
28610 if (!isless (xa, TWO52))
28611 return x;
28612 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28613 return copysign (xa, x);
28614 */
28620 /* Temporary for holding the result, initialized to the input
28621 operand to ease control flow. */
28629 /* load nextafter (0.5, 0.0) */
28634 /* xa = xa + 0.5 */
28638 /* xa = (double)(int64_t)xa */
28643 /* res = copysign (xa, operand1) */
28650 }
28652 \f
28653 /* Validate whether a SSE5 instruction is valid or not.
28654 OPERANDS is the array of operands.
28655 NUM is the number of operands.
28656 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
28657 NUM_MEMORY is the maximum number of memory operands to accept.
28658 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
28660 bool
28663 {
28668 /* Count the number of memory arguments */
28672 {
28675 ;
28678 {
28680 mem_count++;
28681 }
28683 else
28684 {
28687 /* allow 0 for pcmov */
28693 }
28694 }
28696 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
28697 a memory operation. */
28699 {
28702 {
28704 mem_count--;
28705 }
28706 }
28708 /* If there were no memory operations, allow the insn */
28712 /* Do not allow the destination register to be a memory operand. */
28716 /* If there are too many memory operations, disallow the instruction. While
28717 the hardware only allows 1 memory reference, before register allocation
28718 for some insns, we allow two memory operations sometimes in order to allow
28719 code like the following to be optimized:
28721 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
28723 or similar cases that are vectorized into using the fmaddss
28724 instruction. */
28728 /* Don't allow more than one memory operation if not optimizing. */
28733 {
28734 /* formats (destination is the first argument), example fmaddss:
28735 xmm1, xmm1, xmm2, xmm3/mem
28736 xmm1, xmm1, xmm2/mem, xmm3
28737 xmm1, xmm2, xmm3/mem, xmm1
28738 xmm1, xmm2/mem, xmm3, xmm1 */
28744 /* format, example pmacsdd:
28745 xmm1, xmm2, xmm3/mem, xmm1 */
28748 else
28750 }
28753 {
28754 /* If there are two memory operations, we can load one of the memory ops
28755 into the destination register. This is for optimizing the
28756 multiply/add ops, which the combiner has optimized both the multiply
28757 and the add insns to have a memory operation. We have to be careful
28758 that the destination doesn't overlap with the inputs. */
28766 /* formats (destination is the first argument), example fmaddss:
28767 xmm1, xmm1, xmm2, xmm3/mem
28768 xmm1, xmm1, xmm2/mem, xmm3
28769 xmm1, xmm2, xmm3/mem, xmm1
28770 xmm1, xmm2/mem, xmm3, xmm1
28772 For the oc0 case, we will load either operands[1] or operands[3] into
28773 operands[0], so any combination of 2 memory operands is ok. */
28777 /* format, example pmacsdd:
28778 xmm1, xmm2, xmm3/mem, xmm1
28780 For the integer multiply/add instructions be more restrictive and
28781 require operands[2] and operands[3] to be the memory operands. */
28784 else
28786 }
28789 {
28790 /* formats, example protb:
28791 xmm1, xmm2, xmm3/mem
28792 xmm1, xmm2/mem, xmm3 */
28796 /* format, example comeq:
28797 xmm1, xmm2, xmm3/mem */
28798 else
28800 }
28802 else
28806 }
28808 \f
28809 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
28810 hardware will allow by using the destination register to load one of the
28811 memory operations. Presently this is used by the multiply/add routines to
28812 allow 2 memory references. */
28814 void
28818 {
28827 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
28828 the destination register. */
28830 {
28833 }
28835 {
28838 }
28839 else
28843 }
28845 \f
28846 /* Table of valid machine attributes. */
28848 {
28849 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
28850 /* Stdcall attribute says callee is responsible for popping arguments
28851 if they are not variable. */
28853 /* Fastcall attribute says callee is responsible for popping arguments
28854 if they are not variable. */
28856 /* Cdecl attribute says the callee is a normal C declaration */
28858 /* Regparm attribute specifies how many integer arguments are to be
28859 passed in registers. */
28861 /* Sseregparm attribute says we are using x86_64 calling conventions
28862 for FP arguments. */
28864 /* force_align_arg_pointer says this function realigns the stack at entry. */
28867 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28871 #endif
28874 #ifdef SUBTARGET_ATTRIBUTE_TABLE
28875 SUBTARGET_ATTRIBUTE_TABLE,
28876 #endif
28877 /* ms_abi and sysv_abi calling convention function attributes. */
28880 /* End element. */
28882 };
28884 /* Implement targetm.vectorize.builtin_vectorization_cost. */
28885 static int
28887 {
28888 /* If the branch of the runtime test is taken - i.e. - the vectorized
28889 version is skipped - this incurs a misprediction cost (because the
28890 vectorized version is expected to be the fall-through). So we subtract
28891 the latency of a mispredicted branch from the costs that are incured
28892 when the vectorized version is executed.
28894 TODO: The values in individual target tables have to be tuned or new
28895 fields may be needed. For eg. on K8, the default branch path is the
28896 not-taken path. If the taken path is predicted correctly, the minimum
28897 penalty of going down the taken-path is 1 cycle. If the taken-path is
28898 not predicted correctly, then the minimum penalty is 10 cycles. */
28901 {
28903 }
28904 else
28906 }
28908 /* This function returns the calling abi specific va_list type node.
28909 It returns the FNDECL specific va_list type. */
28911 tree
28913 {
28923 else
28925 }
28927 /* Returns the canonical va_list type specified by TYPE. If there
28928 is no valid TYPE provided, it return NULL_TREE. */
28930 tree
28932 {
28935 /* Resolve references and pointers to va_list type. */
28942 {
28947 {
28948 /* If va_list is an array type, the argument may have decayed
28949 to a pointer type, e.g. by being passed to another function.
28950 In that case, unwrap both types so that we can compare the
28951 underlying records. */
28954 {
28957 }
28958 }
28965 {
28966 /* If va_list is an array type, the argument may have decayed
28967 to a pointer type, e.g. by being passed to another function.
28968 In that case, unwrap both types so that we can compare the
28969 underlying records. */
28972 {
28975 }
28976 }
28983 {
28984 /* If va_list is an array type, the argument may have decayed
28985 to a pointer type, e.g. by being passed to another function.
28986 In that case, unwrap both types so that we can compare the
28987 underlying records. */
28990 {
28993 }
28994 }
28998 }
29000 }
29002 /* Iterate through the target-specific builtin types for va_list.
29003 IDX denotes the iterator, *PTREE is set to the result type of
29004 the va_list builtin, and *PNAME to its internal type.
29005 Returns zero if there is no element for this index, otherwise
29006 IDX should be increased upon the next call.
29007 Note, do not iterate a base builtin's name like __builtin_va_list.
29008 Used from c_common_nodes_and_builtins. */
29010 int
29012 {
29026 }
29028 }
29030 /* Initialize the GCC target structure. */
29031 #undef TARGET_RETURN_IN_MEMORY
29032 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29034 #undef TARGET_ATTRIBUTE_TABLE
29035 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29036 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29037 # undef TARGET_MERGE_DECL_ATTRIBUTES
29038 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29039 #endif
29041 #undef TARGET_COMP_TYPE_ATTRIBUTES
29042 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29044 #undef TARGET_INIT_BUILTINS
29045 #define TARGET_INIT_BUILTINS ix86_init_builtins
29046 #undef TARGET_EXPAND_BUILTIN
29047 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29049 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29050 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29051 ix86_builtin_vectorized_function
29053 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29054 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29056 #undef TARGET_BUILTIN_RECIPROCAL
29057 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29059 #undef TARGET_ASM_FUNCTION_EPILOGUE
29060 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29062 #undef TARGET_ENCODE_SECTION_INFO
29063 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29064 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29065 #else
29066 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29067 #endif
29069 #undef TARGET_ASM_OPEN_PAREN
29071 #undef TARGET_ASM_CLOSE_PAREN
29074 #undef TARGET_ASM_ALIGNED_HI_OP
29075 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29076 #undef TARGET_ASM_ALIGNED_SI_OP
29077 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29078 #ifdef ASM_QUAD
29079 #undef TARGET_ASM_ALIGNED_DI_OP
29080 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29081 #endif
29083 #undef TARGET_ASM_UNALIGNED_HI_OP
29084 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29085 #undef TARGET_ASM_UNALIGNED_SI_OP
29086 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29087 #undef TARGET_ASM_UNALIGNED_DI_OP
29088 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29090 #undef TARGET_SCHED_ADJUST_COST
29091 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29092 #undef TARGET_SCHED_ISSUE_RATE
29093 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29094 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29095 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29096 ia32_multipass_dfa_lookahead
29098 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29099 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29101 #ifdef HAVE_AS_TLS
29102 #undef TARGET_HAVE_TLS
29103 #define TARGET_HAVE_TLS true
29104 #endif
29105 #undef TARGET_CANNOT_FORCE_CONST_MEM
29106 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29107 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29108 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29110 #undef TARGET_DELEGITIMIZE_ADDRESS
29111 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29113 #undef TARGET_MS_BITFIELD_LAYOUT_P
29114 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29116 #if TARGET_MACHO
29117 #undef TARGET_BINDS_LOCAL_P
29118 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29119 #endif
29120 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29121 #undef TARGET_BINDS_LOCAL_P
29122 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29123 #endif
29125 #undef TARGET_ASM_OUTPUT_MI_THUNK
29126 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29127 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29128 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29130 #undef TARGET_ASM_FILE_START
29131 #define TARGET_ASM_FILE_START x86_file_start
29133 #undef TARGET_DEFAULT_TARGET_FLAGS
29134 #define TARGET_DEFAULT_TARGET_FLAGS \
29135 (TARGET_DEFAULT \
29136 | TARGET_SUBTARGET_DEFAULT \
29137 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29139 #undef TARGET_HANDLE_OPTION
29140 #define TARGET_HANDLE_OPTION ix86_handle_option
29142 #undef TARGET_RTX_COSTS
29143 #define TARGET_RTX_COSTS ix86_rtx_costs
29144 #undef TARGET_ADDRESS_COST
29145 #define TARGET_ADDRESS_COST ix86_address_cost
29147 #undef TARGET_FIXED_CONDITION_CODE_REGS
29148 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29149 #undef TARGET_CC_MODES_COMPATIBLE
29150 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29152 #undef TARGET_MACHINE_DEPENDENT_REORG
29153 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29155 #undef TARGET_BUILD_BUILTIN_VA_LIST
29156 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29158 #undef TARGET_FN_ABI_VA_LIST
29159 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29161 #undef TARGET_CANONICAL_VA_LIST_TYPE
29162 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29164 #undef TARGET_EXPAND_BUILTIN_VA_START
29165 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29167 #undef TARGET_MD_ASM_CLOBBERS
29168 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29170 #undef TARGET_PROMOTE_PROTOTYPES
29171 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29172 #undef TARGET_STRUCT_VALUE_RTX
29173 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29174 #undef TARGET_SETUP_INCOMING_VARARGS
29175 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29176 #undef TARGET_MUST_PASS_IN_STACK
29177 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29178 #undef TARGET_PASS_BY_REFERENCE
29179 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29180 #undef TARGET_INTERNAL_ARG_POINTER
29181 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29182 #undef TARGET_UPDATE_STACK_BOUNDARY
29183 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29184 #undef TARGET_GET_DRAP_RTX
29185 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29186 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29187 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29188 #undef TARGET_STRICT_ARGUMENT_NAMING
29189 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29191 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29192 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29194 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29195 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29197 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29198 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29200 #undef TARGET_C_MODE_FOR_SUFFIX
29201 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29203 #ifdef HAVE_AS_TLS
29204 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29205 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29206 #endif
29208 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29209 #undef TARGET_INSERT_ATTRIBUTES
29210 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29211 #endif
29213 #undef TARGET_MANGLE_TYPE
29214 #define TARGET_MANGLE_TYPE ix86_mangle_type
29216 #undef TARGET_STACK_PROTECT_FAIL
29217 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29219 #undef TARGET_FUNCTION_VALUE
29220 #define TARGET_FUNCTION_VALUE ix86_function_value
29222 #undef TARGET_SECONDARY_RELOAD
29223 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29225 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29226 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29228 #undef TARGET_SET_CURRENT_FUNCTION
29229 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29231 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29232 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29234 #undef TARGET_OPTION_SAVE
29235 #define TARGET_OPTION_SAVE ix86_function_specific_save
29237 #undef TARGET_OPTION_RESTORE
29238 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29240 #undef TARGET_OPTION_PRINT
29241 #define TARGET_OPTION_PRINT ix86_function_specific_print
29243 #undef TARGET_OPTION_CAN_INLINE_P
29244 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29247 \f