| blob | 0d30eb017b3395398eaff8b3ec7b937f3e57d666 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
89 #ifndef CHECK_STACK_LIMIT
90 #define CHECK_STACK_LIMIT (-1)
91 #endif
93 /* Return index of given mode in mult and division cost tables. */
94 #define MODE_INDEX(mode) \
95 ((mode) == QImode ? 0 \
96 : (mode) == HImode ? 1 \
97 : (mode) == SImode ? 2 \
98 : (mode) == DImode ? 3 \
99 : 4)
101 /* Processor costs (relative to an add) */
102 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
103 #define COSTS_N_BYTES(N) ((N) * 2)
105 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
114 const
137 in QImode, HImode and SImode.
138 Relative to reg-reg move (2). */
142 in SFmode, DFmode and XFmode */
144 in SFmode, DFmode and XFmode */
147 in SImode and DImode */
149 in SImode and DImode */
152 in SImode, DImode and TImode */
154 in SImode, DImode and TImode */
167 ix86_size_memcpy,
168 ix86_size_memset,
180 };
182 /* Processor costs (relative to an add) */
185 DUMMY_STRINGOP_ALGS};
188 DUMMY_STRINGOP_ALGS};
190 static const
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
218 in SFmode, DFmode and XFmode */
220 in SFmode, DFmode and XFmode */
223 in SImode and DImode */
225 in SImode and DImode */
228 in SImode, DImode and TImode */
230 in SImode, DImode and TImode */
243 i386_memcpy,
244 i386_memset,
256 };
260 DUMMY_STRINGOP_ALGS};
263 DUMMY_STRINGOP_ALGS};
265 static const
288 in QImode, HImode and SImode.
289 Relative to reg-reg move (2). */
293 in SFmode, DFmode and XFmode */
295 in SFmode, DFmode and XFmode */
298 in SImode and DImode */
300 in SImode and DImode */
303 in SImode, DImode and TImode */
305 in SImode, DImode and TImode */
308 shared for code and data, so 4kB is
309 not really precise. */
320 i486_memcpy,
321 i486_memset,
333 };
337 DUMMY_STRINGOP_ALGS};
340 DUMMY_STRINGOP_ALGS};
342 static const
365 in QImode, HImode and SImode.
366 Relative to reg-reg move (2). */
370 in SFmode, DFmode and XFmode */
372 in SFmode, DFmode and XFmode */
375 in SImode and DImode */
377 in SImode and DImode */
380 in SImode, DImode and TImode */
382 in SImode, DImode and TImode */
395 pentium_memcpy,
396 pentium_memset,
408 };
410 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
411 (we ensure the alignment). For small blocks inline loop is still a
412 noticeable win, for bigger blocks either rep movsl or rep movsb is
413 way to go. Rep movsb has apparently more expensive startup time in CPU,
414 but after 4K the difference is down in the noise. */
419 DUMMY_STRINGOP_ALGS};
424 DUMMY_STRINGOP_ALGS};
425 static const
448 in QImode, HImode and SImode.
449 Relative to reg-reg move (2). */
453 in SFmode, DFmode and XFmode */
455 in SFmode, DFmode and XFmode */
458 in SImode and DImode */
460 in SImode and DImode */
463 in SImode, DImode and TImode */
465 in SImode, DImode and TImode */
478 pentiumpro_memcpy,
479 pentiumpro_memset,
491 };
495 DUMMY_STRINGOP_ALGS};
498 DUMMY_STRINGOP_ALGS};
499 static const
522 in QImode, HImode and SImode.
523 Relative to reg-reg move (2). */
527 in SFmode, DFmode and XFmode */
529 in SFmode, DFmode and XFmode */
533 in SImode and DImode */
535 in SImode and DImode */
538 in SImode, DImode and TImode */
540 in SImode, DImode and TImode */
553 geode_memcpy,
554 geode_memset,
566 };
570 DUMMY_STRINGOP_ALGS};
573 DUMMY_STRINGOP_ALGS};
574 static const
597 in QImode, HImode and SImode.
598 Relative to reg-reg move (2). */
602 in SFmode, DFmode and XFmode */
604 in SFmode, DFmode and XFmode */
607 in SImode and DImode */
609 in SImode and DImode */
612 in SImode, DImode and TImode */
614 in SImode, DImode and TImode */
618 have integrated l2 cache, but
619 optimizing for k6 is not important
620 enough to worry about that. */
630 k6_memcpy,
631 k6_memset,
643 };
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
650 DUMMY_STRINGOP_ALGS};
653 DUMMY_STRINGOP_ALGS};
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
707 athlon_memcpy,
708 athlon_memset,
720 };
722 /* K8 has optimized REP instruction for medium sized blocks, but for very
723 small blocks it is better to use loop. For large blocks, libcall can
724 do nontemporary accesses and beat inline considerably. */
735 static const
758 in QImode, HImode and SImode.
759 Relative to reg-reg move (2). */
763 in SFmode, DFmode and XFmode */
765 in SFmode, DFmode and XFmode */
768 in SImode and DImode */
770 in SImode and DImode */
773 in SImode, DImode and TImode */
775 in SImode, DImode and TImode */
780 /* New AMD processors never drop prefetches; if they cannot be performed
781 immediately, they are queued. We set number of simultaneous prefetches
782 to a large constant to reflect this (it probably is not a good idea not
783 to limit number of prefetches at all, as their execution also takes some
784 time). */
794 k8_memcpy,
795 k8_memset,
807 };
809 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
810 very small blocks it is better to use loop. For large blocks, libcall can
811 do nontemporary accesses and beat inline considerably. */
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
863 /* On K8:
864 MOVD reg64, xmmreg Double FSTORE 4
865 MOVD reg32, xmmreg Double FSTORE 4
866 On AMDFAM10:
867 MOVD reg64, xmmreg Double FADD 3
868 1/1 1/1
869 MOVD reg32, xmmreg Double FADD 3
870 1/1 1/1 */
874 /* New AMD processors never drop prefetches; if they cannot be performed
875 immediately, they are queued. We set number of simultaneous prefetches
876 to a large constant to reflect this (it probably is not a good idea not
877 to limit number of prefetches at all, as their execution also takes some
878 time). */
888 amdfam10_memcpy,
889 amdfam10_memset,
901 };
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
939 in QImode, HImode and SImode.
940 Relative to reg-reg move (2). */
944 in SFmode, DFmode and XFmode */
946 in SFmode, DFmode and XFmode */
949 in SImode and DImode */
951 in SImode and DImode */
954 in SImode, DImode and TImode */
956 in SImode, DImode and TImode */
958 /* On K8:
959 MOVD reg64, xmmreg Double FSTORE 4
960 MOVD reg32, xmmreg Double FSTORE 4
961 On AMDFAM10:
962 MOVD reg64, xmmreg Double FADD 3
963 1/1 1/1
964 MOVD reg32, xmmreg Double FADD 3
965 1/1 1/1 */
969 /* New AMD processors never drop prefetches; if they cannot be performed
970 immediately, they are queued. We set number of simultaneous prefetches
971 to a large constant to reflect this (it probably is not a good idea not
972 to limit number of prefetches at all, as their execution also takes some
973 time). */
983 bdver1_memcpy,
984 bdver1_memset,
996 };
998 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
999 very small blocks it is better to use loop. For large blocks, libcall
1000 can do nontemporary accesses and beat inline considerably. */
1035 in QImode, HImode and SImode.
1036 Relative to reg-reg move (2). */
1040 in SFmode, DFmode and XFmode */
1042 in SFmode, DFmode and XFmode */
1045 in SImode and DImode */
1047 in SImode and DImode */
1050 in SImode, DImode and TImode */
1052 in SImode, DImode and TImode */
1054 /* On K8:
1055 MOVD reg64, xmmreg Double FSTORE 4
1056 MOVD reg32, xmmreg Double FSTORE 4
1057 On AMDFAM10:
1058 MOVD reg64, xmmreg Double FADD 3
1059 1/1 1/1
1060 MOVD reg32, xmmreg Double FADD 3
1061 1/1 1/1 */
1065 /* New AMD processors never drop prefetches; if they cannot be performed
1066 immediately, they are queued. We set number of simultaneous prefetches
1067 to a large constant to reflect this (it probably is not a good idea not
1068 to limit number of prefetches at all, as their execution also takes some
1069 time). */
1079 bdver2_memcpy,
1080 bdver2_memset,
1092 };
1095 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1096 very small blocks it is better to use loop. For large blocks, libcall
1097 can do nontemporary accesses and beat inline considerably. */
1130 in QImode, HImode and SImode.
1131 Relative to reg-reg move (2). */
1135 in SFmode, DFmode and XFmode */
1137 in SFmode, DFmode and XFmode */
1140 in SImode and DImode */
1142 in SImode and DImode */
1145 in SImode, DImode and TImode */
1147 in SImode, DImode and TImode */
1152 /* New AMD processors never drop prefetches; if they cannot be performed
1153 immediately, they are queued. We set number of simultaneous prefetches
1154 to a large constant to reflect this (it probably is not a good idea not
1155 to limit number of prefetches at all, as their execution also takes some
1156 time). */
1166 bdver3_memcpy,
1167 bdver3_memset,
1179 };
1181 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1182 very small blocks it is better to use loop. For large blocks, libcall
1183 can do nontemporary accesses and beat inline considerably. */
1216 in QImode, HImode and SImode.
1217 Relative to reg-reg move (2). */
1221 in SFmode, DFmode and XFmode */
1223 in SFmode, DFmode and XFmode */
1226 in SImode and DImode */
1228 in SImode and DImode */
1231 in SImode, DImode and TImode */
1233 in SImode, DImode and TImode */
1238 /* New AMD processors never drop prefetches; if they cannot be performed
1239 immediately, they are queued. We set number of simultaneous prefetches
1240 to a large constant to reflect this (it probably is not a good idea not
1241 to limit number of prefetches at all, as their execution also takes some
1242 time). */
1252 bdver4_memcpy,
1253 bdver4_memset,
1265 };
1267 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1268 very small blocks it is better to use loop. For large blocks, libcall can
1269 do nontemporary accesses and beat inline considerably. */
1302 in QImode, HImode and SImode.
1303 Relative to reg-reg move (2). */
1307 in SFmode, DFmode and XFmode */
1309 in SFmode, DFmode and XFmode */
1312 in SImode and DImode */
1314 in SImode and DImode */
1317 in SImode, DImode and TImode */
1319 in SImode, DImode and TImode */
1321 /* On K8:
1322 MOVD reg64, xmmreg Double FSTORE 4
1323 MOVD reg32, xmmreg Double FSTORE 4
1324 On AMDFAM10:
1325 MOVD reg64, xmmreg Double FADD 3
1326 1/1 1/1
1327 MOVD reg32, xmmreg Double FADD 3
1328 1/1 1/1 */
1341 btver1_memcpy,
1342 btver1_memset,
1354 };
1388 in QImode, HImode and SImode.
1389 Relative to reg-reg move (2). */
1393 in SFmode, DFmode and XFmode */
1395 in SFmode, DFmode and XFmode */
1398 in SImode and DImode */
1400 in SImode and DImode */
1403 in SImode, DImode and TImode */
1405 in SImode, DImode and TImode */
1407 /* On K8:
1408 MOVD reg64, xmmreg Double FSTORE 4
1409 MOVD reg32, xmmreg Double FSTORE 4
1410 On AMDFAM10:
1411 MOVD reg64, xmmreg Double FADD 3
1412 1/1 1/1
1413 MOVD reg32, xmmreg Double FADD 3
1414 1/1 1/1 */
1426 btver2_memcpy,
1427 btver2_memset,
1439 };
1443 DUMMY_STRINGOP_ALGS};
1447 DUMMY_STRINGOP_ALGS};
1449 static const
1472 in QImode, HImode and SImode.
1473 Relative to reg-reg move (2). */
1477 in SFmode, DFmode and XFmode */
1479 in SFmode, DFmode and XFmode */
1482 in SImode and DImode */
1484 in SImode and DImode */
1487 in SImode, DImode and TImode */
1489 in SImode, DImode and TImode */
1502 pentium4_memcpy,
1503 pentium4_memset,
1515 };
1528 static const
1551 in QImode, HImode and SImode.
1552 Relative to reg-reg move (2). */
1556 in SFmode, DFmode and XFmode */
1558 in SFmode, DFmode and XFmode */
1561 in SImode and DImode */
1563 in SImode and DImode */
1566 in SImode, DImode and TImode */
1568 in SImode, DImode and TImode */
1581 nocona_memcpy,
1582 nocona_memset,
1594 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 atom_memcpy,
1659 atom_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 slm_memcpy,
1736 slm_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 intel_memcpy,
1813 intel_memset,
1825 };
1827 /* Generic should produce code tuned for Core-i7 (and newer chips)
1828 and btver1 (and newer chips). */
1840 static const
1843 /* On all chips taken into consideration lea is 2 cycles and more. With
1844 this cost however our current implementation of synth_mult results in
1845 use of unnecessary temporary registers causing regression on several
1846 SPECfp benchmarks. */
1867 in QImode, HImode and SImode.
1868 Relative to reg-reg move (2). */
1872 in SFmode, DFmode and XFmode */
1874 in SFmode, DFmode and XFmode */
1877 in SImode and DImode */
1879 in SImode and DImode */
1882 in SImode, DImode and TImode */
1884 in SImode, DImode and TImode */
1890 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1891 value is increased to perhaps more appropriate value of 5. */
1899 generic_memcpy,
1900 generic_memset,
1912 };
1914 /* core_cost should produce code tuned for Core familly of CPUs. */
1927 static const
1930 /* On all chips taken into consideration lea is 2 cycles and more. With
1931 this cost however our current implementation of synth_mult results in
1932 use of unnecessary temporary registers causing regression on several
1933 SPECfp benchmarks. */
1954 in QImode, HImode and SImode.
1955 Relative to reg-reg move (2). */
1959 in SFmode, DFmode and XFmode */
1961 in SFmode, DFmode and XFmode */
1964 in SImode and DImode */
1966 in SImode and DImode */
1969 in SImode, DImode and TImode */
1971 in SImode, DImode and TImode */
1977 /* FIXME perhaps more appropriate value is 5. */
1985 core_memcpy,
1986 core_memset,
1998 };
2001 /* Set by -mtune. */
2004 /* Set by -mtune or -Os. */
2007 /* Processor feature/optimization bitmasks. */
2008 #define m_386 (1<<PROCESSOR_I386)
2009 #define m_486 (1<<PROCESSOR_I486)
2010 #define m_PENT (1<<PROCESSOR_PENTIUM)
2011 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2012 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2013 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2014 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2015 #define m_CORE2 (1<<PROCESSOR_CORE2)
2016 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2017 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2018 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2019 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2020 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2021 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2022 #define m_INTEL (1<<PROCESSOR_INTEL)
2024 #define m_GEODE (1<<PROCESSOR_GEODE)
2025 #define m_K6 (1<<PROCESSOR_K6)
2026 #define m_K6_GEODE (m_K6 | m_GEODE)
2027 #define m_K8 (1<<PROCESSOR_K8)
2028 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2029 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2030 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2031 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2032 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2033 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2034 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2035 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2036 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2037 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2038 #define m_BTVER (m_BTVER1 | m_BTVER2)
2039 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2041 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2044 #undef DEF_TUNE
2045 #define DEF_TUNE(tune, name, selector) name,
2047 #undef DEF_TUNE
2048 };
2050 /* Feature tests against the various tunings. */
2053 /* Feature tests against the various tunings used to create ix86_tune_features
2054 based on the processor mask. */
2056 #undef DEF_TUNE
2057 #define DEF_TUNE(tune, name, selector) selector,
2059 #undef DEF_TUNE
2060 };
2062 /* Feature tests against the various architecture variations. */
2065 /* Feature tests against the various architecture variations, used to create
2066 ix86_arch_features based on the processor mask. */
2068 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2071 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2074 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2077 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2080 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2082 };
2084 /* In case the average insn count for single function invocation is
2085 lower than this constant, emit fast (but longer) prologue and
2086 epilogue code. */
2087 #define FAST_PROLOGUE_INSN_COUNT 20
2089 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2094 /* Array of the smallest class containing reg number REGNO, indexed by
2095 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2098 {
2099 /* ax, dx, cx, bx */
2101 /* si, di, bp, sp */
2103 /* FP registers */
2106 /* arg pointer */
2107 NON_Q_REGS,
2108 /* flags, fpsr, fpcr, frame */
2110 /* SSE registers */
2113 /* MMX registers */
2116 /* REX registers */
2119 /* SSE REX registers */
2122 /* AVX-512 SSE registers */
2127 /* Mask registers. */
2130 };
2132 /* The "default" register map used in 32bit mode. */
2135 {
2146 };
2148 /* The "default" register map used in 64bit mode. */
2151 {
2162 };
2164 /* Define the register numbers to be used in Dwarf debugging information.
2165 The SVR4 reference port C compiler uses the following register numbers
2166 in its Dwarf output code:
2167 0 for %eax (gcc regno = 0)
2168 1 for %ecx (gcc regno = 2)
2169 2 for %edx (gcc regno = 1)
2170 3 for %ebx (gcc regno = 3)
2171 4 for %esp (gcc regno = 7)
2172 5 for %ebp (gcc regno = 6)
2173 6 for %esi (gcc regno = 4)
2174 7 for %edi (gcc regno = 5)
2175 The following three DWARF register numbers are never generated by
2176 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2177 believes these numbers have these meanings.
2178 8 for %eip (no gcc equivalent)
2179 9 for %eflags (gcc regno = 17)
2180 10 for %trapno (no gcc equivalent)
2181 It is not at all clear how we should number the FP stack registers
2182 for the x86 architecture. If the version of SDB on x86/svr4 were
2183 a bit less brain dead with respect to floating-point then we would
2184 have a precedent to follow with respect to DWARF register numbers
2185 for x86 FP registers, but the SDB on x86/svr4 is so completely
2186 broken with respect to FP registers that it is hardly worth thinking
2187 of it as something to strive for compatibility with.
2188 The version of x86/svr4 SDB I have at the moment does (partially)
2189 seem to believe that DWARF register number 11 is associated with
2190 the x86 register %st(0), but that's about all. Higher DWARF
2191 register numbers don't seem to be associated with anything in
2192 particular, and even for DWARF regno 11, SDB only seems to under-
2193 stand that it should say that a variable lives in %st(0) (when
2194 asked via an `=' command) if we said it was in DWARF regno 11,
2195 but SDB still prints garbage when asked for the value of the
2196 variable in question (via a `/' command).
2197 (Also note that the labels SDB prints for various FP stack regs
2198 when doing an `x' command are all wrong.)
2199 Note that these problems generally don't affect the native SVR4
2200 C compiler because it doesn't allow the use of -O with -g and
2201 because when it is *not* optimizing, it allocates a memory
2202 location for each floating-point variable, and the memory
2203 location is what gets described in the DWARF AT_location
2204 attribute for the variable in question.
2205 Regardless of the severe mental illness of the x86/svr4 SDB, we
2206 do something sensible here and we use the following DWARF
2207 register numbers. Note that these are all stack-top-relative
2208 numbers.
2209 11 for %st(0) (gcc regno = 8)
2210 12 for %st(1) (gcc regno = 9)
2211 13 for %st(2) (gcc regno = 10)
2212 14 for %st(3) (gcc regno = 11)
2213 15 for %st(4) (gcc regno = 12)
2214 16 for %st(5) (gcc regno = 13)
2215 17 for %st(6) (gcc regno = 14)
2216 18 for %st(7) (gcc regno = 15)
2217 */
2219 {
2230 };
2232 /* Define parameter passing and return registers. */
2235 {
2237 };
2240 {
2242 };
2245 {
2247 };
2249 /* Additional registers that are clobbered by SYSV calls. */
2252 {
2257 };
2259 /* Define the structure for the machine field in struct function. */
2264 rtx rtl;
2266 };
2268 /* Structure describing stack frame layout.
2269 Stack grows downward:
2271 [arguments]
2272 <- ARG_POINTER
2273 saved pc
2275 saved static chain if ix86_static_chain_on_stack
2277 saved frame pointer if frame_pointer_needed
2278 <- HARD_FRAME_POINTER
2279 [saved regs]
2280 <- regs_save_offset
2281 [padding0]
2283 [saved SSE regs]
2284 <- sse_regs_save_offset
2285 [padding1] |
2286 | <- FRAME_POINTER
2287 [va_arg registers] |
2288 |
2289 [frame] |
2290 |
2291 [padding2] | = to_allocate
2292 <- STACK_POINTER
2293 */
2294 struct ix86_frame
2295 {
2302 /* The offsets relative to ARG_POINTER. */
2303 HOST_WIDE_INT frame_pointer_offset;
2304 HOST_WIDE_INT hard_frame_pointer_offset;
2305 HOST_WIDE_INT stack_pointer_offset;
2306 HOST_WIDE_INT hfp_save_offset;
2307 HOST_WIDE_INT reg_save_offset;
2308 HOST_WIDE_INT sse_reg_save_offset;
2310 /* When save_regs_using_mov is set, emit prologue using
2311 move instead of push instructions. */
2313 };
2315 /* Which cpu are we scheduling for. */
2318 /* Which cpu are we optimizing for. */
2321 /* Which instruction set architecture to use. */
2324 /* True if processor has SSE prefetch instruction. */
2327 /* -mstackrealign option */
2344 /* Preferred alignment for stack boundary in bits. */
2347 /* Alignment for incoming stack boundary in bits specified at
2348 command line. */
2351 /* Default alignment for incoming stack boundary in bits. */
2354 /* Alignment for incoming stack boundary in bits. */
2357 /* Calling abi specific va_list type nodes. */
2361 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2365 /* Fence to use after loop using movnt. */
2366 tree x86_mfence;
2368 /* Register class used for passing given 64bit part of the argument.
2369 These represent classes as documented by the PS ABI, with the exception
2370 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2371 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2373 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2374 whenever possible (upper half does contain padding). */
2375 enum x86_64_reg_class
2376 {
2377 X86_64_NO_CLASS,
2378 X86_64_INTEGER_CLASS,
2379 X86_64_INTEGERSI_CLASS,
2380 X86_64_SSE_CLASS,
2381 X86_64_SSESF_CLASS,
2382 X86_64_SSEDF_CLASS,
2383 X86_64_SSEUP_CLASS,
2384 X86_64_X87_CLASS,
2385 X86_64_X87UP_CLASS,
2386 X86_64_COMPLEX_X87_CLASS,
2387 X86_64_MEMORY_CLASS
2388 };
2390 #define MAX_CLASSES 8
2392 /* Table of constants used by fldpi, fldln2, etc.... */
2396 \f
2401 const_tree);
2413 enum ix86_function_specific_strings
2414 {
2415 IX86_FUNCTION_SPECIFIC_ARCH,
2416 IX86_FUNCTION_SPECIFIC_TUNE,
2417 IX86_FUNCTION_SPECIFIC_MAX
2418 };
2439 \f
2440 #ifndef SUBTARGET32_DEFAULT_CPU
2442 #endif
2444 /* Whether -mtune= or -march= were specified */
2448 /* Vectorization library interface and handlers. */
2454 /* Processor target table, indexed by processor number */
2455 struct ptt
2456 {
2464 };
2466 /* This table must be in sync with enum processor_type in i386.h. */
2468 {
2494 };
2495 \f
2496 static bool
2498 {
2500 }
2502 static unsigned int
2504 {
2507 /* vzeroupper instructions are inserted immediately after reload to
2508 account for possible spills from 256bit registers. The pass
2509 reuses mode switching infrastructure by re-running mode insertion
2510 pass, so disable entities that have already been processed. */
2516 /* Call optimize_mode_switching. */
2519 }
2524 {
2536 };
2539 {
2543 {}
2545 /* opt_pass methods: */
2553 rtl_opt_pass *
2555 {
2557 }
2559 /* Return true if a red-zone is in use. */
2563 {
2565 }
2566 \f
2567 /* Return a string that documents the current -m options. The caller is
2568 responsible for freeing the string. */
2574 {
2575 struct ix86_target_opts
2576 {
2579 };
2581 /* This table is ordered so that options like -msse4.2 that imply
2582 preceding options while match those first. */
2584 {
2625 };
2627 /* Flag options. */
2629 {
2658 };
2675 /* Add -march= option. */
2677 {
2680 }
2682 /* Add -mtune= option. */
2684 {
2687 }
2689 /* Add -m32/-m64/-mx32. */
2691 {
2694 else
2696 isa &= ~ (OPTION_MASK_ISA_64BIT
2697 | OPTION_MASK_ABI_64
2699 }
2700 else
2704 /* Pick out the options in isa options. */
2706 {
2708 {
2711 }
2712 }
2715 {
2718 isa);
2719 }
2721 /* Add flag options. */
2723 {
2725 {
2728 }
2729 }
2732 {
2735 }
2737 /* Add -fpmath= option. */
2739 {
2742 {
2757 }
2758 }
2760 /* Any options? */
2766 /* Size the string. */
2770 {
2775 }
2777 /* Build the string. */
2782 {
2789 {
2791 line_len++;
2794 {
2798 }
2799 }
2803 {
2807 }
2808 }
2814 }
2816 /* Return true, if profiling code should be emitted before
2817 prologue. Otherwise it returns false.
2818 Note: For x86 with "hotfix" it is sorried. */
2819 static bool
2821 {
2823 }
2825 /* Function that is callable from the debugger to print the current
2826 options. */
2827 void ATTRIBUTE_UNUSED
2829 {
2835 {
2838 }
2839 else
2843 }
2846 #define DEF_ENUM
2847 #define DEF_ALG(alg, name) #name,
2849 #undef DEF_ENUM
2850 #undef DEF_ALG
2851 };
2853 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2854 The string is of the following form (or comma separated list of it):
2856 strategy_alg:max_size:[align|noalign]
2858 where the full size range for the strategy is either [0, max_size] or
2859 [min_size, max_size], in which min_size is the max_size + 1 of the
2860 preceding range. The last size range must have max_size == -1.
2862 Examples:
2864 1.
2865 -mmemcpy-strategy=libcall:-1:noalign
2867 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2870 2.
2871 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2873 This is to tell the compiler to use the following strategy for memset
2874 1) when the expected size is between [1, 16], use rep_8byte strategy;
2875 2) when the size is between [17, 2048], use vector_loop;
2876 3) when the size is > 2048, use libcall. */
2878 struct stringop_size_range
2879 {
2881 stringop_alg alg;
2883 };
2885 static void
2887 {
2895 else
2900 do
2901 {
2911 {
2915 }
2918 {
2922 }
2929 {
2931 alg_name,
2934 }
2942 else
2943 {
2947 }
2948 n++;
2950 }
2954 {
2959 }
2962 {
2966 }
2968 /* Now override the default algs array. */
2970 {
2976 }
2977 }
2979 \f
2980 /* parse -mtune-ctrl= option. When DUMP is true,
2981 print the features that are explicitly set. */
2983 static void
2985 {
2993 do
2994 {
3001 {
3002 curr_feature_string++;
3004 }
3006 {
3008 {
3014 }
3015 }
3020 }
3023 }
3025 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3026 processor type. */
3028 static void
3030 {
3035 {
3038 else
3040 }
3043 {
3048 }
3051 }
3054 /* Override various settings based on options. If MAIN_ARGS_P, the
3055 options are from the command line, otherwise they are from
3056 attributes. */
3058 static void
3062 {
3070 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3071 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3072 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3073 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3074 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3075 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3076 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3077 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3078 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3079 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3080 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3081 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3082 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3083 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3084 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3085 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3086 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3087 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3088 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3089 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3090 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3091 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3092 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3093 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3094 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3095 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3096 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3097 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3098 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3099 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3100 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3101 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3102 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3103 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3104 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3105 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3106 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3107 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3108 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3109 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3110 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3111 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3112 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3113 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3114 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3116 #define PTA_CORE2 \
3117 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3118 | PTA_CX16 | PTA_FXSR)
3119 #define PTA_NEHALEM \
3120 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3121 #define PTA_WESTMERE \
3122 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3123 #define PTA_SANDYBRIDGE \
3124 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3125 #define PTA_IVYBRIDGE \
3126 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3127 #define PTA_HASWELL \
3128 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3129 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE)
3130 #define PTA_BROADWELL \
3131 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3132 #define PTA_BONNELL \
3133 (PTA_CORE2 | PTA_MOVBE)
3134 #define PTA_SILVERMONT \
3135 (PTA_WESTMERE | PTA_MOVBE)
3137 /* if this reaches 64, need to widen struct pta flags below */
3139 static struct pta
3140 {
3145 }
3147 {
3181 PTA_SANDYBRIDGE},
3183 PTA_SANDYBRIDGE},
3185 PTA_IVYBRIDGE},
3187 PTA_IVYBRIDGE},
3277 PTA_64BIT
3279 };
3281 /* -mrecip options. */
3282 static struct
3283 {
3286 }
3288 {
3295 };
3299 /* Set up prefix/suffix so the error messages refer to either the command
3300 line argument, or the attribute(target). */
3302 {
3306 }
3307 else
3308 {
3312 }
3314 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3315 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3318 #ifdef TARGET_BI_ARCH
3319 else
3320 {
3321 #if TARGET_BI_ARCH == 1
3322 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3323 is on and OPTION_MASK_ABI_X32 is off. We turn off
3324 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3325 -mx32. */
3328 #else
3329 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3330 on and OPTION_MASK_ABI_64 is off. We turn off
3331 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3332 -m64. */
3335 #endif
3336 }
3337 #endif
3340 {
3341 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3342 OPTION_MASK_ABI_64 for TARGET_X32. */
3345 }
3348 | OPTION_MASK_ABI_X32
3351 {
3352 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3353 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3356 }
3358 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3359 SUBTARGET_OVERRIDE_OPTIONS;
3360 #endif
3362 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3363 SUBSUBTARGET_OVERRIDE_OPTIONS;
3364 #endif
3366 /* -fPIC is the default for x86_64. */
3370 /* Need to check -mtune=generic first. */
3372 {
3373 /* As special support for cross compilers we read -mtune=native
3374 as -mtune=generic. With native compilers we won't see the
3375 -mtune=native, as it was changed by the driver. */
3377 {
3379 }
3384 }
3385 else
3386 {
3390 {
3391 opts->x_ix86_tune_string
3394 }
3396 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3397 or defaulted. We need to use a sensible tune option. */
3399 {
3401 }
3402 }
3406 {
3407 /* rep; movq isn't available in 32-bit code. */
3410 }
3413 opts->x_ix86_arch_string
3416 else
3420 {
3428 }
3429 else
3436 /* For targets using ms ABI enable ms-extensions, if not
3437 explicit turned off. For non-ms ABI we turn off this
3438 option. */
3443 {
3445 {
3489 {
3492 }
3500 }
3501 }
3502 else
3503 {
3504 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3505 use of rip-relative addressing. This eliminates fixups that
3506 would otherwise be needed if this object is to be placed in a
3507 DLL, and is essentially just as efficient as direct addressing. */
3513 else
3515 }
3517 {
3520 }
3528 {
3531 /* Default cpu tuning to the architecture. */
3673 }
3691 {
3695 {
3697 {
3699 {
3707 }
3708 else
3711 }
3712 }
3713 /* Intel CPUs have always interpreted SSE prefetch instructions as
3714 NOPs; so, we can enable SSE prefetch instructions even when
3715 -mtune (rather than -march) points us to a processor that has them.
3716 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3717 higher processors. */
3722 }
3730 #ifndef USE_IX86_FRAME_POINTER
3731 #define USE_IX86_FRAME_POINTER 0
3732 #endif
3734 #ifndef USE_X86_64_FRAME_POINTER
3735 #define USE_X86_64_FRAME_POINTER 0
3736 #endif
3738 /* Set the default values for switches whose default depends on TARGET_64BIT
3739 in case they weren't overwritten by command line options. */
3741 {
3749 opts->x_flag_unwind_tables
3753 }
3754 else
3755 {
3757 opts->x_flag_omit_frame_pointer
3763 }
3768 else
3771 /* Arrange to set up i386_stack_locals for all functions. */
3774 /* Validate -mregparm= value. */
3776 {
3780 {
3784 }
3785 }
3789 /* Default align_* from the processor table. */
3791 {
3794 }
3796 {
3799 }
3801 {
3803 }
3805 /* Provide default for -mbranch-cost= value. */
3810 {
3811 opts->x_target_flags
3814 /* Enable by default the SSE and MMX builtins. Do allow the user to
3815 explicitly disable any of these. In particular, disabling SSE and
3816 MMX for kernel code is extremely useful. */
3818 opts->x_ix86_isa_flags
3825 }
3826 else
3827 {
3828 opts->x_target_flags
3832 opts->x_ix86_isa_flags
3835 /* i386 ABI does not specify red zone. It still makes sense to use it
3836 when programmer takes care to stack from being destroyed. */
3839 }
3841 /* Keep nonleaf frame pointers. */
3847 /* If we're doing fast math, we don't care about comparison order
3848 wrt NaNs. This lets us use a shorter comparison sequence. */
3852 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3853 since the insns won't need emulation. */
3857 /* Likewise, if the target doesn't have a 387, or we've specified
3858 software floating point, don't use 387 inline intrinsics. */
3862 /* Turn on MMX builtins for -msse. */
3864 opts->x_ix86_isa_flags
3867 /* Enable SSE prefetch. */
3872 /* Enable prefetch{,w} instructions for -m3dnow. */
3874 opts->x_ix86_isa_flags
3877 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3880 opts->x_ix86_isa_flags
3883 /* Enable lzcnt instruction for -mabm. */
3885 opts->x_ix86_isa_flags
3888 /* Validate -mpreferred-stack-boundary= value or default it to
3889 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3892 {
3899 {
3903 else
3906 }
3907 else
3908 ix86_preferred_stack_boundary
3910 }
3912 /* Set the default value for -mstackrealign. */
3918 /* Validate -mincoming-stack-boundary= value or default it to
3919 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3922 {
3929 else
3930 {
3931 ix86_user_incoming_stack_boundary
3933 ix86_incoming_stack_boundary
3935 }
3936 }
3938 /* Accept -msseregparm only if at least SSE support is enabled. */
3944 {
3946 {
3948 {
3951 }
3954 {
3957 }
3958 }
3959 }
3960 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3961 fpmath=387. The second is however default at many targets since the
3962 extra 80bit precision of temporaries is considered to be part of ABI.
3963 Overwrite the default at least for -ffast-math.
3964 TODO: -mfpmath=both seems to produce same performing code with bit
3965 smaller binaries. It is however not clear if register allocation is
3966 ready for this setting.
3967 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3968 codegen. We may switch to 387 with -ffast-math for size optimized
3969 functions. */
3973 else
3976 /* If the i387 is disabled, then do not return values in it. */
3980 /* Use external vectorized library in vectorizing intrinsics. */
3983 {
3994 }
4001 /* If stack probes are required, the space used for large function
4002 arguments on the stack must also be probed, so enable
4003 -maccumulate-outgoing-args so this happens in the prologue. */
4006 {
4011 }
4013 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4014 {
4020 }
4022 /* When scheduling description is not available, disable scheduler pass
4023 so it won't slow down the compilation and make x87 code slower. */
4044 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4046 && HAVE_prefetch
4051 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4052 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4057 {
4060 {
4062 ix86_gen_tls_local_dynamic_base_64
4064 }
4065 else
4066 {
4068 ix86_gen_tls_local_dynamic_base_64
4070 }
4071 }
4072 else
4076 {
4086 }
4087 else
4088 {
4098 }
4100 #ifdef USE_IX86_CLD
4101 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4104 #endif
4107 {
4112 }
4114 {
4118 }
4120 {
4121 #if defined(PROFILE_BEFORE_PROLOGUE)
4123 #else
4125 #endif
4126 }
4128 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4129 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4130 AVX unaligned load/store. */
4132 {
4142 /* Enable 128-bit AVX instruction generation
4143 for the auto-vectorizer. */
4147 }
4150 {
4157 {
4160 {
4162 q++;
4163 }
4164 else
4169 else
4170 {
4173 {
4176 }
4179 {
4183 }
4184 }
4189 else
4191 }
4192 }
4199 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4200 for 64-bit Bionic. */
4205 ? MASK_LONG_DOUBLE_128
4208 /* Only one of them can be active. */
4212 /* Save the initial options in case the user does function specific
4213 options. */
4215 target_option_default_node = target_option_current_node
4218 /* Handle stack protector */
4220 opts->x_ix86_stack_protector_guard
4223 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4225 {
4229 }
4232 {
4236 }
4237 }
4239 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4241 static void
4243 {
4245 static struct register_pass_info insert_vzeroupper_info
4248 };
4253 /* This needs to be done at start up. It's convenient to do it here. */
4255 }
4257 /* Update register usage after having seen the compiler flags. */
4259 static void
4261 {
4265 /* The PIC register, if it exists, is fixed. */
4270 /* For 32-bit targets, squash the REX registers. */
4272 {
4279 }
4281 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4289 {
4290 /* Set/reset conditionally defined registers from
4291 CALL_USED_REGISTERS initializer. */
4295 /* Calculate registers of CLOBBERED_REGS register set
4296 as call used registers from GENERAL_REGS register set. */
4300 }
4302 /* If MMX is disabled, squash the registers. */
4308 /* If SSE is disabled, squash the registers. */
4314 /* If the FPU is disabled, squash the registers. */
4320 /* If AVX512F is disabled, squash the registers. */
4322 {
4328 }
4329 }
4331 \f
4332 /* Save the current options */
4334 static void
4337 {
4372 /* The fields are char but the variables are not; make sure the
4373 values fit in the fields. */
4378 }
4380 /* Restore the current options */
4382 static void
4385 {
4391 /* We don't change -fPIC. */
4428 /* Recreate the arch feature tests if the arch changed */
4430 {
4435 }
4437 /* Recreate the tune optimization tests */
4440 }
4442 /* Print the current options */
4444 static void
4447 {
4465 {
4468 }
4469 }
4471 \f
4472 /* Inner function to process the attribute((target(...))), take an argument and
4473 set the current options from the argument. If we have a list, recursively go
4474 over the list. */
4476 static bool
4481 {
4485 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4486 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4487 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4488 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4489 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4491 enum ix86_opt_type
4492 {
4493 ix86_opt_unknown,
4494 ix86_opt_yes,
4495 ix86_opt_no,
4496 ix86_opt_str,
4497 ix86_opt_enum,
4498 ix86_opt_isa
4499 };
4501 static const struct
4502 {
4509 /* isa options */
4551 /* enum options */
4554 /* string options */
4558 /* flag options */
4560 OPT_mcld,
4561 MASK_CLD),
4564 OPT_mfancy_math_387,
4565 MASK_NO_FANCY_MATH_387),
4568 OPT_mieee_fp,
4569 MASK_IEEE_FP),
4572 OPT_minline_all_stringops,
4573 MASK_INLINE_ALL_STRINGOPS),
4576 OPT_minline_stringops_dynamically,
4577 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4580 OPT_mno_align_stringops,
4581 MASK_NO_ALIGN_STRINGOPS),
4584 OPT_mrecip,
4585 MASK_RECIP),
4587 };
4589 /* If this is a list, recurse to get the options. */
4591 {
4598 enum_opts_set))
4602 }
4605 {
4608 }
4610 /* Handle multiple arguments separated by commas. */
4614 {
4628 {
4632 }
4633 else
4634 {
4637 }
4639 /* Recognize no-xxx. */
4641 {
4645 }
4646 else
4649 /* Find the option. */
4653 {
4661 {
4666 }
4667 }
4669 /* Process the option. */
4671 {
4674 }
4677 {
4683 }
4686 {
4692 else
4694 }
4697 {
4699 {
4702 }
4703 else
4705 }
4708 {
4716 global_dc);
4717 else
4718 {
4721 }
4722 }
4724 else
4726 }
4729 }
4731 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4733 tree
4737 {
4752 /* Process each of the options on the chain. */
4757 /* If the changed options are different from the default, rerun
4758 ix86_option_override_internal, and then save the options away.
4759 The string options are are attribute options, and will be undone
4760 when we copy the save structure. */
4766 {
4767 /* If we are using the default tune= or arch=, undo the string assigned,
4768 and use the default. */
4779 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4784 {
4787 }
4789 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4792 /* Add any builtin functions with the new isa if any. */
4795 /* Save the current options unless we are validating options for
4796 #pragma. */
4803 /* Free up memory allocated to hold the strings */
4806 }
4809 }
4811 /* Hook to validate attribute((target("string"))). */
4813 static bool
4816 tree args,
4818 {
4823 /* attribute((target("default"))) does nothing, beyond
4824 affecting multi-versioning. */
4833 /* Get the optimization options of the current function. */
4839 /* Init func_options. */
4847 /* Initialize func_options to the default before its target options can
4848 be set. */
4861 {
4866 }
4869 }
4871 \f
4872 /* Hook to determine if one function can safely inline another. */
4874 static bool
4876 {
4881 /* If callee has no option attributes, then it is ok to inline. */
4885 /* If caller has no option attributes, but callee does then it is not ok to
4886 inline. */
4890 else
4891 {
4895 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4896 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4897 function. */
4902 /* See if we have the same non-isa options. */
4906 /* See if arch, tune, etc. are the same. */
4919 else
4921 }
4924 }
4926 \f
4927 /* Remember the last target of ix86_set_current_function. */
4930 /* Invalidate ix86_previous_fndecl cache. */
4931 void
4933 {
4935 }
4937 /* Establish appropriate back-end context for processing the function
4938 FNDECL. The argument might be NULL to indicate processing at top
4939 level, outside of any function scope. */
4940 static void
4942 {
4943 /* Only change the context if the function changes. This hook is called
4944 several times in the course of compiling a function, and we don't want to
4945 slow things down too much or call target_reinit when it isn't safe. */
4947 {
4948 tree old_tree = (ix86_previous_fndecl
4952 tree new_tree = (fndecl
4958 ;
4961 {
4966 else
4969 }
4972 {
4980 else
4983 }
4984 }
4985 }
4987 \f
4988 /* Return true if this goes in large data/bss. */
4990 static bool
4992 {
4996 /* Functions are never large data. */
5001 {
5007 }
5008 else
5009 {
5012 /* If this is an incomplete type with size 0, then we can't put it
5013 in data because it might be too big when completed. */
5016 }
5019 }
5021 /* Switch to the appropriate section for output of DECL.
5022 DECL is either a `VAR_DECL' node or a constant of some sort.
5023 RELOC indicates whether forming the initial value of DECL requires
5024 link-time relocations. */
5029 {
5032 {
5036 {
5070 /* We don't split these for medium model. Place them into
5071 default sections and hope for best. */
5073 }
5075 {
5076 /* We might get called with string constants, but get_named_section
5077 doesn't like them as they are not DECLs. Also, we need to set
5078 flags in that case. */
5082 }
5083 }
5085 }
5087 /* Select a set of attributes for section NAME based on the properties
5088 of DECL and whether or not RELOC indicates that DECL's initializer
5089 might contain runtime relocations. */
5091 static unsigned int ATTRIBUTE_UNUSED
5093 {
5107 }
5109 /* Build up a unique section name, expressed as a
5110 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5111 RELOC indicates whether the initial value of EXP requires
5112 link-time relocations. */
5114 static void ATTRIBUTE_UNUSED
5116 {
5119 {
5121 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5125 {
5149 /* We don't split these for medium model. Place them into
5150 default sections and hope for best. */
5152 }
5154 {
5161 /* If we're using one_only, then there needs to be a .gnu.linkonce
5162 prefix to the section name. */
5169 }
5170 }
5172 }
5174 #ifdef COMMON_ASM_OP
5175 /* This says how to output assembler code to declare an
5176 uninitialized external linkage data object.
5178 For medium model x86-64 we need to use .largecomm opcode for
5179 large objects. */
5180 void
5184 {
5188 else
5193 }
5194 #endif
5196 /* Utility function for targets to use in implementing
5197 ASM_OUTPUT_ALIGNED_BSS. */
5199 void
5203 {
5207 else
5210 #ifdef ASM_DECLARE_OBJECT_NAME
5213 #else
5214 /* Standard thing is just output label for the object. */
5218 }
5219 \f
5220 /* Decide whether we must probe the stack before any space allocation
5221 on this target. It's essentially TARGET_STACK_PROBE except when
5222 -fstack-check causes the stack to be already probed differently. */
5224 bool
5226 {
5227 /* Do not probe the stack twice if static stack checking is enabled. */
5232 }
5233 \f
5234 /* Decide whether we can make a sibling call to a function. DECL is the
5235 declaration of the function being targeted by the call and EXP is the
5236 CALL_EXPR representing the call. */
5238 static bool
5240 {
5244 /* If we are generating position-independent code, we cannot sibcall
5245 optimize any indirect call, or a direct call to a global function,
5246 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5248 && !TARGET_64BIT
5249 && flag_pic
5253 /* If we need to align the outgoing stack, then sibcalling would
5254 unalign the stack, which may break the called function. */
5260 {
5263 }
5264 else
5265 {
5266 /* We're looking at the CALL_EXPR, we need the type of the function. */
5271 }
5273 /* Check that the return value locations are the same. Like
5274 if we are returning floats on the 80387 register stack, we cannot
5275 make a sibcall from a function that doesn't return a float to a
5276 function that does or, conversely, from a function that does return
5277 a float to a function that doesn't; the necessary stack adjustment
5278 would not be executed. This is also the place we notice
5279 differences in the return value ABI. Note that it is ok for one
5280 of the functions to have void return type as long as the return
5281 value of the other is passed in a register. */
5286 {
5289 }
5291 ;
5296 {
5297 /* The SYSV ABI has more call-clobbered registers;
5298 disallow sibcalls from MS to SYSV. */
5302 }
5303 else
5304 {
5305 /* If this call is indirect, we'll need to be able to use a
5306 call-clobbered register for the address of the target function.
5307 Make sure that all such registers are not used for passing
5308 parameters. Note that DLLIMPORT functions are indirect. */
5311 {
5313 {
5314 /* ??? Need to count the actual number of registers to be used,
5315 not the possible number of registers. Fix later. */
5317 }
5318 }
5319 }
5321 /* Otherwise okay. That also includes certain types of indirect calls. */
5323 }
5325 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5326 and "sseregparm" calling convention attributes;
5327 arguments as in struct attribute_spec.handler. */
5329 static tree
5331 tree args,
5334 {
5339 {
5341 name);
5344 }
5346 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5348 {
5349 tree cst;
5352 {
5354 }
5357 {
5359 }
5363 {
5366 name);
5368 }
5370 {
5374 }
5377 }
5380 {
5381 /* Do not warn when emulating the MS ABI. */
5386 name);
5389 }
5391 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5393 {
5395 {
5397 }
5399 {
5401 }
5403 {
5405 }
5407 {
5409 }
5410 }
5412 /* Can combine stdcall with fastcall (redundant), regparm and
5413 sseregparm. */
5415 {
5417 {
5419 }
5421 {
5423 }
5425 {
5427 }
5428 }
5430 /* Can combine cdecl with regparm and sseregparm. */
5432 {
5434 {
5436 }
5438 {
5440 }
5442 {
5444 }
5445 }
5447 {
5450 name);
5452 {
5454 }
5456 {
5458 }
5460 {
5462 }
5463 }
5465 /* Can combine sseregparm with all attributes. */
5468 }
5470 /* The transactional memory builtins are implicitly regparm or fastcall
5471 depending on the ABI. Override the generic do-nothing attribute that
5472 these builtins were declared with, and replace it with one of the two
5473 attributes that we expect elsewhere. */
5475 static tree
5477 tree args ATTRIBUTE_UNUSED,
5479 {
5480 tree alt;
5482 /* In no case do we want to add the placeholder attribute. */
5485 /* The 64-bit ABI is unchanged for transactional memory. */
5489 /* ??? Is there a better way to validate 32-bit windows? We have
5490 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5493 else
5494 {
5497 }
5501 }
5503 /* This function determines from TYPE the calling-convention. */
5505 unsigned int
5507 {
5510 tree attrs;
5517 {
5527 /* Regparam isn't allowed for thiscall and fastcall. */
5529 {
5534 }
5538 }
5545 || is_stdarg
5551 }
5553 /* Return 0 if the attributes for two types are incompatible, 1 if they
5554 are compatible, and 2 if they are nearly compatible (which causes a
5555 warning to be generated). */
5557 static int
5559 {
5575 }
5576 \f
5577 /* Return the regparm value for a function with the indicated TYPE and DECL.
5578 DECL may be NULL when calling function indirectly
5579 or considering a libcall. */
5581 static int
5583 {
5584 tree attr;
5595 {
5598 {
5601 }
5602 }
5608 /* Use register calling convention for local functions when possible. */
5611 /* Caller and callee must agree on the calling convention, so
5612 checking here just optimize means that with
5613 __attribute__((optimize (...))) caller could use regparm convention
5614 and callee not, or vice versa. Instead look at whether the callee
5615 is optimized or not. */
5618 {
5619 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5622 {
5625 /* Make sure no regparm register is taken by a
5626 fixed register variable. */
5631 /* We don't want to use regparm(3) for nested functions as
5632 these use a static chain pointer in the third argument. */
5636 /* In 32-bit mode save a register for the split stack. */
5640 /* Each fixed register usage increases register pressure,
5641 so less registers should be used for argument passing.
5642 This functionality can be overriden by an explicit
5643 regparm value. */
5646 globals++;
5648 local_regparm
5653 }
5654 }
5657 }
5659 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5660 DFmode (2) arguments in SSE registers for a function with the
5661 indicated TYPE and DECL. DECL may be NULL when calling function
5662 indirectly or considering a libcall. Otherwise return 0. */
5664 static int
5666 {
5669 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5670 by the sseregparm attribute. */
5673 {
5675 {
5677 {
5681 else
5684 }
5686 }
5689 }
5691 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5692 (and DFmode for SSE2) arguments in SSE registers. */
5695 {
5696 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5700 }
5703 }
5705 /* Return true if EAX is live at the start of the function. Used by
5706 ix86_expand_prologue to determine if we need special help before
5707 calling allocate_stack_worker. */
5709 static bool
5711 {
5712 /* Cheat. Don't bother working forward from ix86_function_regparm
5713 to the function type to whether an actual argument is located in
5714 eax. Instead just look at cfg info, which is still close enough
5715 to correct at this point. This gives false positives for broken
5716 functions that might use uninitialized data that happens to be
5717 allocated in eax, but who cares? */
5719 }
5721 static bool
5723 {
5724 tree attr;
5727 {
5733 /* For 32-bit MS-ABI the default is to keep aggregate
5734 return pointer. */
5737 }
5739 }
5741 /* Value is the number of bytes of arguments automatically
5742 popped when returning from a subroutine call.
5743 FUNDECL is the declaration node of the function (as a tree),
5744 FUNTYPE is the data type of the function (as a tree),
5745 or for a library call it is an identifier node for the subroutine name.
5746 SIZE is the number of bytes of arguments passed on the stack.
5748 On the 80386, the RTD insn may be used to pop them if the number
5749 of args is fixed, but if the number is variable then the caller
5750 must pop them all. RTD can't be used for library calls now
5751 because the library is compiled with the Unix compiler.
5752 Use of RTD is a selectable option, since it is incompatible with
5753 standard Unix calling sequences. If the option is not selected,
5754 the caller must always pop the args.
5756 The attribute stdcall is equivalent to RTD on a per module basis. */
5758 static int
5760 {
5763 /* None of the 64-bit ABIs pop arguments. */
5774 /* Lose any fake structure return argument if it is passed on the stack. */
5777 {
5781 }
5784 }
5786 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5788 static bool
5790 {
5791 /* Check operand constraints in case hard registers were propagated
5792 into insn pattern. This check prevents combine pass from
5793 generating insn patterns with invalid hard register operands.
5794 These invalid insns can eventually confuse reload to error out
5795 with a spill failure. See also PRs 46829 and 46843. */
5797 {
5804 {
5812 /* For pre-AVX disallow unaligned loads/stores where the
5813 instructions don't support it. */
5817 {
5821 }
5823 /* A unary operator may be accepted by the predicate, but it
5824 is irrelevant for matching constraints. */
5829 {
5837 }
5844 /* Operand has no constraints, anything is OK. */
5848 {
5851 && operands_match_p
5855 {
5858 }
5859 }
5863 }
5864 }
5867 }
5868 \f
5869 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5871 static unsigned HOST_WIDE_INT
5873 {
5877 }
5878 \f
5879 /* Argument support functions. */
5881 /* Return true when register may be used to pass function parameters. */
5882 bool
5884 {
5889 {
5893 else
5899 }
5905 /* TODO: The function should depend on current function ABI but
5906 builtins.c would need updating then. Therefore we use the
5907 default ABI. */
5909 /* RAX is used as hidden argument to va_arg functions. */
5915 else
5922 }
5924 /* Return if we do not know how to pass TYPE solely in registers. */
5926 static bool
5928 {
5932 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5933 The layout_type routine is crafty and tries to trick us into passing
5934 currently unsupported vector types on the stack by using TImode. */
5937 }
5939 /* It returns the size, in bytes, of the area reserved for arguments passed
5940 in registers for the function represented by fndecl dependent to the used
5941 abi format. */
5942 int
5944 {
5948 else
5953 }
5955 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5956 call abi used. */
5957 enum calling_abi
5959 {
5961 {
5964 {
5967 }
5971 }
5973 }
5975 /* We add this as a workaround in order to use libc_has_function
5976 hook in i386.md. */
5977 bool
5979 {
5981 }
5983 static bool
5985 {
5987 {
5991 else
5993 }
5995 }
5997 static enum calling_abi
5999 {
6003 }
6005 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6006 call abi used. */
6007 enum calling_abi
6009 {
6013 }
6015 /* Write the extra assembler code needed to declare a function properly. */
6017 void
6019 tree decl)
6020 {
6024 {
6030 }
6032 #ifdef SUBTARGET_ASM_UNWIND_INIT
6034 #endif
6038 /* Output magic byte marker, if hot-patch attribute is set. */
6040 {
6042 {
6043 /* leaq [%rsp + 0], %rsp */
6046 }
6047 else
6048 {
6049 /* movl.s %edi, %edi
6050 push %ebp
6051 movl.s %esp, %ebp */
6054 }
6055 }
6056 }
6058 /* regclass.c */
6061 /* Implementation of call abi switching target hook. Specific to FNDECL
6062 the specific call register sets are set. See also
6063 ix86_conditional_register_usage for more details. */
6064 void
6066 {
6069 else
6071 }
6073 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6074 expensive re-initialization of init_regs each time we switch function context
6075 since this is needed only during RTL expansion. */
6076 static void
6078 {
6082 }
6084 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6085 for a call to a function whose data type is FNTYPE.
6086 For a library call, FNTYPE is 0. */
6088 void
6092 tree fndecl,
6094 {
6100 {
6103 }
6104 else
6105 {
6108 }
6112 /* Set up the number of registers to use for passing arguments. */
6115 {
6117 ? X86_64_REGPARM_MAX
6119 }
6121 {
6124 {
6126 ? X86_64_SSE_REGPARM_MAX
6128 }
6129 }
6137 /* Because type might mismatch in between caller and callee, we need to
6138 use actual type of function for local calls.
6139 FIXME: cgraph_analyze can be told to actually record if function uses
6140 va_start so for local functions maybe_vaarg can be made aggressive
6141 helping K&R code.
6142 FIXME: once typesytem is fixed, we won't need this code anymore. */
6150 {
6151 /* If there are variable arguments, then we won't pass anything
6152 in registers in 32-bit mode. */
6154 {
6163 }
6165 /* Use ecx and edx registers if function has fastcall attribute,
6166 else look for regparm information. */
6168 {
6171 {
6174 }
6176 {
6179 }
6180 else
6182 }
6184 /* Set up the number of SSE registers used for passing SFmode
6185 and DFmode arguments. Warn for mismatching ABI. */
6187 }
6188 }
6190 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6191 But in the case of vector types, it is some vector mode.
6193 When we have only some of our vector isa extensions enabled, then there
6194 are some modes for which vector_mode_supported_p is false. For these
6195 modes, the generic vector support in gcc will choose some non-vector mode
6196 in order to implement the type. By computing the natural mode, we'll
6197 select the proper ABI location for the operand and not depend on whatever
6198 the middle-end decides to do with these vector types.
6200 The midde-end can't deal with the vector types > 16 bytes. In this
6201 case, we return the original mode and warn ABI change if CUM isn't
6202 NULL.
6204 If INT_RETURN is true, warn ABI change if the vector mode isn't
6205 available for function return value. */
6207 static enum machine_mode
6210 {
6214 {
6217 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6219 {
6224 else
6227 /* Get the mode which has this inner mode and number of units. */
6231 {
6233 {
6238 {
6242 }
6244 {
6248 }
6251 }
6253 {
6258 {
6262 }
6264 {
6268 }
6271 }
6274 {
6279 {
6283 }
6285 {
6289 }
6290 }
6292 {
6297 {
6301 }
6303 {
6307 }
6308 }
6310 }
6313 }
6314 }
6317 }
6319 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6320 this may not agree with the mode that the type system has chosen for the
6321 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6322 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6324 static rtx
6327 {
6328 rtx tmp;
6332 else
6333 {
6337 }
6340 }
6342 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6343 of this code is to classify each 8bytes of incoming argument by the register
6344 class and assign registers accordingly. */
6346 /* Return the union class of CLASS1 and CLASS2.
6347 See the x86-64 PS ABI for details. */
6349 static enum x86_64_reg_class
6351 {
6352 /* Rule #1: If both classes are equal, this is the resulting class. */
6356 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6357 the other class. */
6363 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6367 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6375 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6376 MEMORY is used. */
6385 /* Rule #6: Otherwise class SSE is used. */
6387 }
6389 /* Classify the argument of type TYPE and mode MODE.
6390 CLASSES will be filled by the register class used to pass each word
6391 of the operand. The number of words is returned. In case the parameter
6392 should be passed in memory, 0 is returned. As a special case for zero
6393 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6395 BIT_OFFSET is used internally for handling records and specifies offset
6396 of the offset in bits modulo 512 to avoid overflow cases.
6398 See the x86-64 PS ABI for details.
6399 */
6401 static int
6404 {
6405 HOST_WIDE_INT bytes =
6407 int words
6410 /* Variable sized entities are always passed/returned in memory. */
6419 {
6421 tree field;
6424 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6431 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6432 signalize memory class, so handle it as special case. */
6434 {
6437 }
6439 /* Classify each field of record and merge classes. */
6441 {
6443 /* And now merge the fields of structure. */
6445 {
6447 {
6453 /* Bitfields are always classified as integer. Handle them
6454 early, since later code would consider them to be
6455 misaligned integers. */
6457 {
6466 }
6467 else
6468 {
6473 /* Flexible array member is ignored. */
6480 {
6484 {
6487 "the ABI of passing struct with"
6488 " a flexible array member has"
6490 }
6492 }
6494 subclasses,
6504 }
6505 }
6506 }
6510 /* Arrays are handled as small records. */
6511 {
6518 /* The partial classes are now full classes. */
6529 }
6532 /* Unions are similar to RECORD_TYPE but offset is always 0.
6533 */
6535 {
6537 {
6545 bit_offset);
6550 }
6551 }
6556 }
6559 {
6560 /* When size > 16 bytes, if the first one isn't
6561 X86_64_SSE_CLASS or any other ones aren't
6562 X86_64_SSEUP_CLASS, everything should be passed in
6563 memory. */
6570 }
6572 /* Final merger cleanup. */
6574 {
6575 /* If one class is MEMORY, everything should be passed in
6576 memory. */
6580 /* The X86_64_SSEUP_CLASS should be always preceded by
6581 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6585 {
6586 /* The first one should never be X86_64_SSEUP_CLASS. */
6589 }
6591 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6592 everything should be passed in memory. */
6595 {
6598 /* The first one should never be X86_64_X87UP_CLASS. */
6601 {
6604 "the ABI of passing union with long double"
6606 }
6608 }
6609 }
6611 }
6613 /* Compute alignment needed. We align all types to natural boundaries with
6614 exception of XFmode that is aligned to 64bits. */
6616 {
6625 /* Misaligned fields are always returned in memory. */
6628 }
6630 /* for V1xx modes, just use the base mode */
6635 /* Classification of atomic types. */
6637 {
6653 {
6656 /* Analyze last 128 bits only. */
6660 {
6663 }
6665 {
6668 }
6670 {
6674 }
6676 {
6679 }
6680 else
6682 }
6689 /* OImode shouldn't be used directly. */
6696 else
6714 else
6715 {
6719 {
6722 "the ABI of passing structure with complex float"
6724 }
6727 }
6736 /* This modes is larger than 16 bytes. */
6794 else
6798 }
6799 }
6801 /* Examine the argument and return set number of register required in each
6802 class. Return 0 iff parameter should be passed in memory. */
6803 static int
6806 {
6816 {
6838 }
6840 }
6842 /* Construct container for the argument used by GCC interface. See
6843 FUNCTION_ARG for the detailed description. */
6845 static rtx
6849 {
6850 /* The following variables hold the static issued_error state. */
6864 rtx ret;
6875 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6876 some less clueful developer tries to use floating-point anyway. */
6878 {
6880 {
6882 {
6885 }
6886 }
6888 {
6891 }
6893 }
6895 /* Likewise, error if the ABI requires us to return values in the
6896 x87 registers and the user specified -mno-80387. */
6902 {
6904 {
6907 }
6909 }
6911 /* First construct simple cases. Avoid SCmode, since we want to use
6912 single register to pass this type. */
6915 {
6930 /* Zero sized array, struct or class. */
6934 }
6973 /* Otherwise figure out the entries of the PARALLEL. */
6975 {
6979 {
6984 /* Merge TImodes on aligned occasions here too. */
6986 tmpmode
6990 else
6992 /* We've requested 24 bytes we
6993 don't have mode for. Use DImode. */
7000 intreg++;
7008 sse_regno++;
7016 sse_regno++;
7021 {
7027 {
7029 i++;
7030 }
7031 else
7056 }
7062 sse_regno++;
7066 }
7067 }
7069 /* Empty aligned struct, union or class. */
7077 }
7079 /* Update the data in CUM to advance over an argument of mode MODE
7080 and data type TYPE. (TYPE is null for libcalls where that information
7081 may not be available.) */
7083 static void
7086 HOST_WIDE_INT words)
7087 {
7089 {
7096 /* FALLTHRU */
7107 {
7110 }
7114 /* OImode shouldn't be used directly. */
7123 /* FALLTHRU */
7145 {
7150 {
7153 }
7154 }
7164 {
7169 {
7172 }
7173 }
7175 }
7176 }
7178 static void
7181 {
7184 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7191 {
7196 }
7197 else
7198 {
7202 }
7203 }
7205 static void
7207 HOST_WIDE_INT words)
7208 {
7209 /* Otherwise, this should be passed indirect. */
7214 {
7217 }
7218 }
7220 /* Update the data in CUM to advance over an argument of mode MODE and
7221 data type TYPE. (TYPE is null for libcalls where that information
7222 may not be available.) */
7224 static void
7227 {
7233 else
7244 else
7246 }
7248 /* Define where to put the arguments to a function.
7249 Value is zero to push the argument on the stack,
7250 or a hard register in which to store the argument.
7252 MODE is the argument's machine mode.
7253 TYPE is the data type of the argument (as a tree).
7254 This is null for libcalls where that information may
7255 not be available.
7256 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7257 the preceding args and about the function being called.
7258 NAMED is nonzero if this argument is a named parameter
7259 (otherwise it is an extra parameter matching an ellipsis). */
7261 static rtx
7265 {
7266 /* Avoid the AL settings for the Unix64 ABI. */
7271 {
7278 /* FALLTHRU */
7284 {
7287 /* Fastcall allocates the first two DWORD (SImode) or
7288 smaller arguments to ECX and EDX if it isn't an
7289 aggregate type . */
7291 {
7297 /* ECX not EAX is the first allocated register. */
7300 }
7302 }
7311 /* FALLTHRU */
7313 /* In 32bit, we pass TImode in xmm registers. */
7321 {
7325 }
7330 /* OImode and XImode shouldn't be used directly. */
7346 {
7350 }
7360 {
7364 }
7366 }
7369 }
7371 static rtx
7374 {
7375 /* Handle a hidden AL argument containing number of registers
7376 for varargs x86-64 functions. */
7380 ? X86_64_SSE_REGPARM_MAX
7385 {
7401 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7405 }
7411 }
7413 static rtx
7416 HOST_WIDE_INT bytes)
7417 {
7420 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7421 We use value of -2 to specify that current function call is MSABI. */
7425 /* If we've run out of registers, it goes on the stack. */
7431 /* Only floating point modes are passed in anything but integer regs. */
7433 {
7436 else
7437 {
7440 /* Unnamed floating parameters are passed in both the
7441 SSE and integer registers. */
7447 }
7448 }
7449 /* Handle aggregated types passed in register. */
7451 {
7456 }
7459 }
7461 /* Return where to put the arguments to a function.
7462 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7464 MODE is the argument's machine mode. TYPE is the data type of the
7465 argument. It is null for libcalls where that information may not be
7466 available. CUM gives information about the preceding args and about
7467 the function being called. NAMED is nonzero if this argument is a
7468 named parameter (otherwise it is an extra parameter matching an
7469 ellipsis). */
7471 static rtx
7474 {
7478 rtx arg;
7482 else
7486 /* To simplify the code below, represent vector types with a vector mode
7487 even if MMX/SSE are not active. */
7495 else
7499 }
7501 /* A C expression that indicates when an argument must be passed by
7502 reference. If nonzero for an argument, a copy of that argument is
7503 made in memory and a pointer to the argument is passed instead of
7504 the argument itself. The pointer is passed in whatever way is
7505 appropriate for passing a pointer to that type. */
7507 static bool
7510 {
7513 /* See Windows x64 Software Convention. */
7515 {
7518 {
7519 /* Arrays are passed by reference. */
7524 {
7525 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7526 are passed by reference. */
7528 }
7529 }
7531 /* __m128 is passed by reference. */
7537 }
7538 }
7543 }
7545 /* Return true when TYPE should be 128bit aligned for 32bit argument
7546 passing ABI. XXX: This function is obsolete and is only used for
7547 checking psABI compatibility with previous versions of GCC. */
7549 static bool
7551 {
7563 {
7564 /* Walk the aggregates recursively. */
7566 {
7570 {
7571 tree field;
7573 /* Walk all the structure fields. */
7575 {
7579 }
7581 }
7584 /* Just for use if some languages passes arrays by value. */
7591 }
7592 }
7594 }
7596 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7597 XXX: This function is obsolete and is only used for checking psABI
7598 compatibility with previous versions of GCC. */
7600 static unsigned int
7603 {
7604 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7605 natural boundaries. */
7607 {
7608 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7609 make an exception for SSE modes since these require 128bit
7610 alignment.
7612 The handling here differs from field_alignment. ICC aligns MMX
7613 arguments to 4 byte boundaries, while structure fields are aligned
7614 to 8 byte boundaries. */
7616 {
7619 }
7620 else
7621 {
7624 }
7625 }
7629 }
7631 /* Return true when TYPE should be 128bit aligned for 32bit argument
7632 passing ABI. */
7634 static bool
7636 {
7646 {
7647 /* Walk the aggregates recursively. */
7649 {
7653 {
7654 tree field;
7656 /* Walk all the structure fields. */
7658 field;
7660 {
7664 }
7666 }
7669 /* Just for use if some languages passes arrays by value. */
7676 }
7677 }
7678 else
7682 }
7684 /* Gives the alignment boundary, in bits, of an argument with the
7685 specified mode and type. */
7687 static unsigned int
7689 {
7692 {
7693 /* Since the main variant type is used for call, we convert it to
7694 the main variant type. */
7697 }
7698 else
7702 else
7703 {
7708 {
7709 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7711 {
7714 }
7720 }
7723 && !warned
7725 saved_align))
7726 {
7729 "The ABI for passing parameters with %d-byte"
7732 }
7733 }
7736 }
7738 /* Return true if N is a possible register number of function value. */
7740 static bool
7742 {
7744 {
7752 /* Complex values are returned in %st(0)/%st(1) pair. */
7755 /* TODO: The function should depend on current function ABI but
7756 builtins.c would need updating then. Therefore we use the
7757 default ABI. */
7762 /* Complex values are returned in %xmm0/%xmm1 pair. */
7771 }
7774 }
7776 /* Define how to find the value returned by a function.
7777 VALTYPE is the data type of the value (as a tree).
7778 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7779 otherwise, FUNC is 0. */
7781 static rtx
7784 {
7787 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7788 we normally prevent this case when mmx is not available. However
7789 some ABIs may require the result to be returned like DImode. */
7793 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7794 we prevent this case when sse is not available. However some ABIs
7795 may require the result to be returned like integer TImode. */
7800 /* 32-byte vector modes in %ymm0. */
7804 /* 64-byte vector modes in %zmm0. */
7808 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7811 else
7812 /* Most things go in %eax. */
7815 /* Override FP return register with %xmm0 for local functions when
7816 SSE math is enabled or for functions with sseregparm attribute. */
7818 {
7823 }
7825 /* OImode shouldn't be used directly. */
7829 }
7831 static rtx
7833 const_tree valtype)
7834 {
7835 rtx ret;
7837 /* Handle libcalls, which don't provide a type node. */
7839 {
7843 {
7862 }
7865 }
7867 {
7868 /* Pointers are always returned in word_mode. */
7870 }
7876 /* For zero sized structures, construct_container returns NULL, but we
7877 need to keep rest of compiler happy by returning meaningful value. */
7882 }
7884 static rtx
7886 const_tree valtype)
7887 {
7891 {
7893 {
7912 }
7913 }
7915 }
7917 static rtx
7920 {
7932 else
7934 }
7936 static rtx
7939 {
7945 }
7947 /* Pointer function arguments and return values are promoted to
7948 word_mode. */
7950 static enum machine_mode
7954 {
7956 {
7959 }
7961 for_return);
7962 }
7964 /* Return true if a structure, union or array with MODE containing FIELD
7965 should be accessed using BLKmode. */
7967 static bool
7969 {
7970 /* Union with XFmode must be in BLKmode. */
7974 }
7976 rtx
7978 {
7980 }
7982 /* Return true iff type is returned in memory. */
7984 static bool ATTRIBUTE_UNUSED
7986 {
7987 HOST_WIDE_INT size;
7998 {
7999 /* User-created vectors small enough to fit in EAX. */
8003 /* MMX/3dNow values are returned in MM0,
8004 except when it doesn't exits or the ABI prescribes otherwise. */
8008 /* SSE values are returned in XMM0, except when it doesn't exist. */
8012 /* AVX values are returned in YMM0, except when it doesn't exist. */
8016 /* AVX512F values are returned in ZMM0, except when it doesn't exist. */
8019 }
8027 /* OImode shouldn't be used directly. */
8031 }
8033 static bool ATTRIBUTE_UNUSED
8035 {
8038 }
8040 static bool ATTRIBUTE_UNUSED
8042 {
8045 /* __m128 is returned in xmm0. */
8052 /* Otherwise, the size must be exactly in [1248]. */
8054 }
8056 static bool
8058 {
8059 #ifdef SUBTARGET_RETURN_IN_MEMORY
8061 #else
8065 {
8068 else
8070 }
8071 else
8073 #endif
8074 }
8076 \f
8077 /* Create the va_list data type. */
8079 /* Returns the calling convention specific va_list date type.
8080 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8082 static tree
8084 {
8087 /* For i386 we use plain pointer to argument area. */
8097 unsigned_type_node);
8100 unsigned_type_node);
8103 ptr_type_node);
8106 ptr_type_node);
8125 /* The correct type is an array type of one element. */
8127 }
8129 /* Setup the builtin va_list data type and for 64-bit the additional
8130 calling convention specific va_list data types. */
8132 static tree
8134 {
8137 /* Initialize abi specific va_list builtin types. */
8139 {
8140 tree t;
8142 {
8147 }
8148 else
8149 {
8154 }
8156 {
8161 }
8162 else
8163 {
8168 }
8169 }
8172 }
8174 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8176 static void
8178 {
8180 alias_set_type set;
8183 /* GPR size of varargs save area. */
8186 else
8189 /* FPR size of varargs save area. We don't need it if we don't pass
8190 anything in SSE registers. */
8193 else
8207 {
8215 }
8218 {
8222 /* Now emit code to save SSE registers. The AX parameter contains number
8223 of SSE parameter registers used to call this function, though all we
8224 actually check here is the zero/non-zero status. */
8229 label));
8231 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8232 we used movdqa (i.e. TImode) instead? Perhaps even better would
8233 be if we could determine the real mode of the data, via a hook
8234 into pass_stdarg. Ignore all that for now. */
8244 {
8253 }
8256 }
8257 }
8259 static void
8261 {
8265 /* Reset to zero, as there might be a sysv vaarg used
8266 before. */
8271 {
8282 }
8283 }
8285 static void
8289 {
8291 CUMULATIVE_ARGS next_cum;
8292 tree fntype;
8294 /* This argument doesn't appear to be used anymore. Which is good,
8295 because the old code here didn't suppress rtl generation. */
8303 /* For varargs, we do not want to skip the dummy va_dcl argument.
8304 For stdargs, we do want to skip the last named argument. */
8312 else
8314 }
8316 /* Checks if TYPE is of kind va_list char *. */
8318 static bool
8320 {
8321 tree canonic;
8323 /* For 32-bit it is always true. */
8329 }
8331 /* Implement va_start. */
8333 static void
8335 {
8339 tree type;
8340 rtx ovf_rtx;
8344 {
8347 /* When we are splitting the stack, we can't refer to the stack
8348 arguments using internal_arg_pointer, because they may be on
8349 the old stack. The split stack prologue will arrange to
8350 leave a pointer to the old stack arguments in a scratch
8351 register, which we here copy to a pseudo-register. The split
8352 stack prologue can't set the pseudo-register directly because
8353 it (the prologue) runs before any registers have been saved. */
8357 {
8371 }
8372 }
8374 /* Only 64bit target needs something special. */
8376 {
8379 else
8380 {
8389 }
8391 }
8400 /* The following should be folded into the MEM_REF offset. */
8410 /* Count number of gp and fp argument registers used. */
8416 {
8422 }
8425 {
8431 }
8433 /* Find the overflow area. */
8437 else
8447 {
8448 /* Find the register save area.
8449 Prologue of the function save it right above stack frame. */
8457 }
8458 }
8460 /* Implement va_arg. */
8462 static tree
8465 {
8472 rtx container;
8474 tree ptrtype;
8478 /* Only 64bit target needs something special. */
8502 {
8515 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8517 {
8520 }
8528 }
8530 /* Pull the value out of the saved registers. */
8535 {
8549 /* In case we are passing structure, verify that it is consecutive block
8550 on the register save area. If not we need to do moves. */
8552 {
8553 /* Verify that all registers are strictly consecutive */
8555 {
8559 {
8564 }
8565 }
8566 else
8567 {
8571 {
8576 }
8577 }
8578 }
8580 {
8583 }
8584 else
8585 {
8588 }
8590 /* First ensure that we fit completely in registers. */
8592 {
8599 }
8601 {
8609 }
8611 /* Compute index to start of area used for integer regs. */
8613 {
8614 /* int_addr = gpr + sav; */
8617 }
8619 {
8620 /* sse_addr = fpr + sav; */
8623 }
8625 {
8629 /* addr = &temp; */
8634 {
8638 tree piece_type;
8639 tree addr_type;
8640 tree daddr_type;
8649 {
8654 }
8658 else
8665 {
8668 }
8669 else
8670 {
8673 }
8680 {
8685 }
8686 else
8687 {
8688 tree copy
8693 }
8695 }
8696 }
8699 {
8703 }
8706 {
8710 }
8715 }
8717 /* ... otherwise out of the overflow area. */
8719 /* When we align parameter on stack for caller, if the parameter
8720 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8721 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8722 here with caller. */
8727 /* Care for on-stack alignment if needed. */
8730 else
8731 {
8736 }
8753 }
8754 \f
8755 /* Return true if OPNUM's MEM should be matched
8756 in movabs* patterns. */
8758 bool
8760 {
8772 }
8773 \f
8774 /* Initialize the table of extra 80387 mathematical constants. */
8776 static void
8778 {
8780 {
8786 };
8790 {
8792 /* Ensure each constant is rounded to XFmode precision. */
8795 }
8798 }
8800 /* Return non-zero if the constant is something that
8801 can be loaded with a special instruction. */
8803 int
8805 {
8808 REAL_VALUE_TYPE r;
8820 /* For XFmode constants, try to find a special 80387 instruction when
8821 optimizing for size or on those CPUs that benefit from them. */
8824 {
8833 }
8835 /* Load of the constant -0.0 or -1.0 will be split as
8836 fldz;fchs or fld1;fchs sequence. */
8843 }
8845 /* Return the opcode of the special instruction to be used to load
8846 the constant X. */
8850 {
8852 {
8872 }
8873 }
8875 /* Return the CONST_DOUBLE representing the 80387 constant that is
8876 loaded by the specified special instruction. The argument IDX
8877 matches the return value from standard_80387_constant_p. */
8879 rtx
8881 {
8888 {
8899 }
8902 XFmode);
8903 }
8905 /* Return 1 if X is all 0s and 2 if x is all 1s
8906 in supported SSE/AVX vector mode. */
8908 int
8910 {
8917 {
8938 }
8941 }
8943 /* Return the opcode of the special instruction to be used to load
8944 the constant X. */
8948 {
8950 {
8953 {
8975 }
8984 else
8989 }
8991 }
8993 /* Returns true if OP contains a symbol reference */
8995 bool
8997 {
9006 {
9008 {
9014 }
9018 }
9021 }
9023 /* Return true if it is appropriate to emit `ret' instructions in the
9024 body of a function. Do this only if the epilogue is simple, needing a
9025 couple of insns. Prior to reloading, we can't tell how many registers
9026 must be saved, so return false then. Return false if there is no frame
9027 marker to de-allocate. */
9029 bool
9031 {
9037 /* Don't allow more than 32k pop, since that's all we can do
9038 with one instruction. */
9045 }
9046 \f
9047 /* Value should be nonzero if functions must have frame pointers.
9048 Zero means the frame pointer need not be set up (and parms may
9049 be accessed via the stack pointer) in functions that seem suitable. */
9051 static bool
9053 {
9054 /* If we accessed previous frames, then the generated code expects
9055 to be able to access the saved ebp value in our frame. */
9059 /* Several x86 os'es need a frame pointer for other reasons,
9060 usually pertaining to setjmp. */
9064 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9068 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9069 allocation is 4GB. */
9073 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9074 turns off the frame pointer by default. Turn it back on now if
9075 we've not got a leaf function. */
9085 }
9087 /* Record that the current function accesses previous call frames. */
9089 void
9091 {
9093 }
9094 \f
9095 #ifndef USE_HIDDEN_LINKONCE
9096 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9097 # define USE_HIDDEN_LINKONCE 1
9098 # else
9099 # define USE_HIDDEN_LINKONCE 0
9100 # endif
9101 #endif
9105 /* Fills in the label name that should be used for a pc thunk for
9106 the given register. */
9108 static void
9110 {
9115 else
9117 }
9120 /* This function generates code for -fpic that loads %ebx with
9121 the return address of the caller and then returns. */
9123 static void
9125 {
9130 {
9132 tree decl;
9148 #if TARGET_MACHO
9150 {
9159 }
9160 else
9161 #endif
9163 {
9174 }
9175 else
9176 {
9179 }
9185 /* Make sure unwind info is emitted for the thunk if needed. */
9188 /* Pad stack IP move with 4 instructions (two NOPs count
9189 as one instruction). */
9191 {
9196 }
9207 }
9211 }
9213 /* Emit code for the SET_GOT patterns. */
9217 {
9223 {
9224 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9229 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9230 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9231 an unadorned address. */
9236 }
9241 {
9243 /* We don't need a pic base, we're not producing pic. */
9250 }
9251 else
9252 {
9261 #if TARGET_MACHO
9262 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9263 This is what will be referenced by the Mach-O PIC subsystem. */
9267 /* When we are restoring the pic base at the site of a nonlocal label,
9268 and we decided to emit the pic base above, we will still output a
9269 local label used for calculating the correction offset (even though
9270 the offset will be 0 in that case). */
9274 #endif
9275 }
9281 }
9283 /* Generate an "push" pattern for input ARG. */
9285 static rtx
9287 {
9300 stack_pointer_rtx)),
9301 arg);
9302 }
9304 /* Generate an "pop" pattern for input ARG. */
9306 static rtx
9308 {
9313 arg,
9316 stack_pointer_rtx)));
9317 }
9319 /* Return >= 0 if there is an unused call-clobbered register available
9320 for the entire function. */
9322 static unsigned int
9324 {
9328 {
9330 /* Can't use the same register for both PIC and DRAP. */
9333 else
9338 }
9341 }
9343 /* Return TRUE if we need to save REGNO. */
9345 static bool
9347 {
9358 {
9361 {
9367 }
9368 }
9379 }
9381 /* Return number of saved general prupose registers. */
9383 static int
9385 {
9391 nregs ++;
9393 }
9395 /* Return number of saved SSE registrers. */
9397 static int
9399 {
9407 nregs ++;
9409 }
9411 /* Given FROM and TO register numbers, say whether this elimination is
9412 allowed. If stack alignment is needed, we can only replace argument
9413 pointer with hard frame pointer, or replace frame pointer with stack
9414 pointer. Otherwise, frame pointer elimination is automatically
9415 handled and all other eliminations are valid. */
9417 static bool
9419 {
9425 else
9427 }
9429 /* Return the offset between two registers, one to be eliminated, and the other
9430 its replacement, at the start of a routine. */
9432 HOST_WIDE_INT
9434 {
9443 else
9444 {
9452 }
9453 }
9455 /* In a dynamically-aligned function, we can't know the offset from
9456 stack pointer to frame pointer, so we must ensure that setjmp
9457 eliminates fp against the hard fp (%ebp) rather than trying to
9458 index from %esp up to the top of the frame across a gap that is
9459 of unknown (at compile-time) size. */
9460 static rtx
9462 {
9464 }
9466 /* When using -fsplit-stack, the allocation routines set a field in
9467 the TCB to the bottom of the stack plus this much space, measured
9468 in bytes. */
9470 #define SPLIT_STACK_AVAILABLE 256
9472 /* Fill structure ix86_frame about frame of currently computed function. */
9474 static void
9476 {
9478 HOST_WIDE_INT offset;
9481 HOST_WIDE_INT to_allocate;
9489 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9490 function prologues and leaf. */
9494 {
9499 }
9505 /* For SEH we have to limit the amount of code movement into the prologue.
9506 At present we do this via a BLOCKAGE, at which point there's very little
9507 scheduling that can be done, which means that there's very little point
9508 in doing anything except PUSHs. */
9512 /* During reload iteration the amount of registers saved can change.
9513 Recompute the value as needed. Do not recompute when amount of registers
9514 didn't change as reload does multiple calls to the function and does not
9515 expect the decision to change within single iteration. */
9518 {
9524 /* The fast prologue uses move instead of push to save registers. This
9525 is significantly longer, but also executes faster as modern hardware
9526 can execute the moves in parallel, but can't do that for push/pop.
9528 Be careful about choosing what prologue to emit: When function takes
9529 many instructions to execute we may use slow version as well as in
9530 case function is known to be outside hot spot (this is known with
9531 feedback only). Weight the size of function by number of registers
9532 to save as it is cheap to use one or two push instructions but very
9533 slow to use many of them. */
9537 || (flag_branch_probabilities
9540 else
9543 }
9545 frame->save_regs_using_mov
9547 /* If static stack checking is enabled and done with probes,
9548 the registers need to be saved before allocating the frame. */
9551 /* Skip return address. */
9554 /* Skip pushed static chain. */
9558 /* Skip saved base pointer. */
9563 /* The traditional frame pointer location is at the top of the frame. */
9566 /* Register save area */
9570 /* On SEH target, registers are pushed just before the frame pointer
9571 location. */
9575 /* Align and set SSE register save area. */
9577 {
9578 /* The only ABI that has saved SSE registers (Win64) also has a
9579 16-byte aligned default stack, and thus we don't need to be
9580 within the re-aligned local stack frame to save them. */
9584 }
9587 /* The re-aligned stack starts here. Values before this point are not
9588 directly comparable with values below this point. In order to make
9589 sure that no value happens to be the same before and after, force
9590 the alignment computation below to add a non-zero value. */
9594 /* Va-arg area */
9598 /* Align start of frame for local function. */
9607 /* Frame pointer points here. */
9612 /* Add outgoing arguments area. Can be skipped if we eliminated
9613 all the function calls as dead code.
9614 Skipping is however impossible when function calls alloca. Alloca
9615 expander assumes that last crtl->outgoing_args_size
9616 of stack frame are unused. */
9620 {
9623 }
9624 else
9627 /* Align stack boundary. Only needed if we're calling another function
9628 or using alloca. */
9633 /* We've reached end of stack frame. */
9636 /* Size prologue needs to allocate. */
9647 {
9653 }
9654 else
9658 /* The SEH frame pointer location is near the bottom of the frame.
9659 This is enforced by the fact that the difference between the
9660 stack pointer and the frame pointer is limited to 240 bytes in
9661 the unwind data structure. */
9663 {
9664 HOST_WIDE_INT diff;
9666 /* If we can leave the frame pointer where it is, do so. Also, returns
9667 the establisher frame for __builtin_frame_address (0). */
9672 {
9673 /* Ideally we'd determine what portion of the local stack frame
9674 (within the constraint of the lowest 240) is most heavily used.
9675 But without that complication, simply bias the frame pointer
9676 by 128 bytes so as to maximize the amount of the local stack
9677 frame that is addressable with 8-bit offsets. */
9679 }
9680 }
9681 }
9683 /* This is semi-inlined memory_address_length, but simplified
9684 since we know that we're always dealing with reg+offset, and
9685 to avoid having to create and discard all that rtl. */
9689 {
9693 {
9694 /* EBP and R13 cannot be encoded without an offset. */
9696 }
9700 /* ESP and R12 must be encoded with a SIB byte. */
9702 len++;
9705 }
9707 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9708 The valid base registers are taken from CFUN->MACHINE->FS. */
9710 static rtx
9712 {
9718 {
9719 /* Choose the base register most likely to allow the most scheduling
9720 opportunities. Generally FP is valid throughout the function,
9721 while DRAP must be reloaded within the epilogue. But choose either
9722 over the SP due to increased encoding size. */
9725 {
9728 }
9730 {
9733 }
9735 {
9738 }
9739 }
9740 else
9741 {
9742 HOST_WIDE_INT toffset;
9745 /* Choose the base register with the smallest address encoding.
9746 With a tie, choose FP > DRAP > SP. */
9748 {
9752 }
9754 {
9758 {
9762 }
9763 }
9765 {
9769 {
9773 }
9774 }
9775 }
9779 }
9781 /* Emit code to save registers in the prologue. */
9783 static void
9785 {
9787 rtx insn;
9791 {
9794 }
9795 }
9797 /* Emit a single register save at CFA - CFA_OFFSET. */
9799 static void
9801 HOST_WIDE_INT cfa_offset)
9802 {
9810 /* For SSE saves, we need to indicate the 128-bit alignment. */
9821 /* When saving registers into a re-aligned local stack frame, avoid
9822 any tricky guessing by dwarf2out. */
9824 {
9828 {
9829 /* A bit of a hack. We force the DRAP register to be saved in
9830 the re-aligned stack frame, which provides us with a copy
9831 of the CFA that will last past the prologue. Install it. */
9837 }
9838 else
9839 {
9840 /* The frame pointer is a stable reference within the
9841 aligned frame. Use it. */
9848 }
9849 }
9851 /* The memory may not be relative to the current CFA register,
9852 which means that we may need to generate a new pattern for
9853 use by the unwind info. */
9855 {
9860 }
9861 }
9863 /* Emit code to save registers using MOV insns.
9864 First register is stored at CFA - CFA_OFFSET. */
9865 static void
9867 {
9872 {
9875 }
9876 }
9878 /* Emit code to save SSE registers using MOV insns.
9879 First register is stored at CFA - CFA_OFFSET. */
9880 static void
9882 {
9887 {
9890 }
9891 }
9895 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9896 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9897 Don't add the note if the previously saved value will be left untouched
9898 within stack red-zone till return, as unwinders can find the same value
9899 in the register and on the stack. */
9901 static void
9903 {
9909 {
9912 }
9913 else
9914 queued_cfa_restores
9916 }
9918 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9920 static void
9922 {
9923 rtx last;
9927 ;
9932 }
9934 /* Expand prologue or epilogue stack adjustment.
9935 The pattern exist to put a dependency on all ebp-based memory accesses.
9936 STYLE should be negative if instructions should be marked as frame related,
9937 zero if %r11 register is live and cannot be freely used and positive
9938 otherwise. */
9940 static void
9943 {
9945 rtx insn;
9952 else
9953 {
9954 rtx tmp;
9955 /* r11 is used by indirect sibcall return as well, set before the
9956 epilogue and used after the epilogue. */
9959 else
9960 {
9964 }
9970 }
9977 {
9978 rtx r;
9988 }
9990 {
9993 {
9997 }
9998 }
10001 {
10006 {
10009 }
10011 {
10014 }
10015 else
10016 {
10017 /* Else there are two possibilities: SP itself, which we set
10018 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10019 taken care of this by hand along the eh_return path. */
10022 }
10026 }
10027 }
10029 /* Find an available register to be used as dynamic realign argument
10030 pointer regsiter. Such a register will be written in prologue and
10031 used in begin of body, so it must not be
10032 1. parameter passing register.
10033 2. GOT pointer.
10034 We reuse static-chain register if it is available. Otherwise, we
10035 use DI for i386 and R13 for x86-64. We chose R13 since it has
10036 shorter encoding.
10038 Return: the regno of chosen register. */
10040 static unsigned int
10042 {
10046 {
10047 /* Use R13 for nested function or function need static chain.
10048 Since function with tail call may use any caller-saved
10049 registers in epilogue, DRAP must not use caller-saved
10050 register in such case. */
10055 }
10056 else
10057 {
10058 /* Use DI for nested function or function need static chain.
10059 Since function with tail call may use any caller-saved
10060 registers in epilogue, DRAP must not use caller-saved
10061 register in such case. */
10065 /* Reuse static chain register if it isn't used for parameter
10066 passing. */
10068 {
10072 }
10074 }
10075 }
10077 /* Return minimum incoming stack alignment. */
10079 static unsigned int
10081 {
10084 /* Prefer the one specified at command line. */
10087 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10088 if -mstackrealign is used, it isn't used for sibcall check and
10089 estimated stack alignment is 128bit. */
10091 && !TARGET_64BIT
10092 && ix86_force_align_arg_pointer
10095 else
10098 /* Incoming stack alignment can be changed on individual functions
10099 via force_align_arg_pointer attribute. We use the smallest
10100 incoming stack boundary. */
10106 /* The incoming stack frame has to be aligned at least at
10107 parm_stack_boundary. */
10111 /* Stack at entrance of main is aligned by runtime. We use the
10112 smallest incoming stack boundary. */
10120 }
10122 /* Update incoming stack boundary and estimated stack alignment. */
10124 static void
10126 {
10127 ix86_incoming_stack_boundary
10130 /* x86_64 vararg needs 16byte stack alignment for register save
10131 area. */
10136 }
10138 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10139 needed or an rtx for DRAP otherwise. */
10141 static rtx
10143 {
10148 {
10149 /* Assign DRAP to vDRAP and returns vDRAP */
10151 rtx drap_vreg;
10152 rtx arg_ptr;
10165 {
10168 }
10170 }
10171 else
10173 }
10175 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10177 static rtx
10179 {
10181 }
10184 rtx reg;
10186 };
10188 /* Return a short-lived scratch register for use on function entry.
10189 In 32-bit mode, it is valid only after the registers are saved
10190 in the prologue. This register must be released by means of
10191 release_scratch_register_on_entry once it is dead. */
10193 static void
10195 {
10201 {
10202 /* We always use R11 in 64-bit mode. */
10204 }
10205 else
10206 {
10208 bool fastcall_p
10210 bool thiscall_p
10214 int drap_regno
10217 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10218 for the static chain register. */
10222 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10223 for the static chain register. */
10228 /* ecx is the static chain register. */
10230 && !static_chain_p
10235 /* esi is the static chain register. */
10241 else
10242 {
10245 }
10246 }
10250 {
10253 }
10254 }
10256 /* Release a scratch register obtained from the preceding function. */
10258 static void
10260 {
10262 {
10266 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10272 }
10273 }
10275 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10277 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10279 static void
10281 {
10282 /* We skip the probe for the first interval + a small dope of 4 words and
10283 probe that many bytes past the specified size to maintain a protection
10284 area at the botton of the stack. */
10288 /* See if we have a constant small number of probes to generate. If so,
10289 that's the easy case. The run-time loop is made up of 11 insns in the
10290 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10291 for n # of intervals. */
10293 {
10297 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10298 values of N from 1 until it exceeds SIZE. If only one probe is
10299 needed, this will not generate any code. Then adjust and probe
10300 to PROBE_INTERVAL + SIZE. */
10302 {
10304 {
10307 }
10308 else
10315 }
10319 else
10327 /* Adjust back to account for the additional first interval. */
10331 }
10333 /* Otherwise, do the same as above, but in a loop. Note that we must be
10334 extra careful with variables wrapping around because we might be at
10335 the very top (or the very bottom) of the address space and we have
10336 to be able to handle this case properly; in particular, we use an
10337 equality test for the loop condition. */
10338 else
10339 {
10340 HOST_WIDE_INT rounded_size;
10346 /* Step 1: round SIZE to the previous multiple of the interval. */
10351 /* Step 2: compute initial and final value of the loop counter. */
10353 /* SP = SP_0 + PROBE_INTERVAL. */
10358 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10362 stack_pointer_rtx)));
10365 /* Step 3: the loop
10367 while (SP != LAST_ADDR)
10368 {
10369 SP = SP + PROBE_INTERVAL
10370 probe at SP
10371 }
10373 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10374 values of N from 1 until it is equal to ROUNDED_SIZE. */
10379 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10380 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10383 {
10388 }
10390 /* Adjust back to account for the additional first interval. */
10396 }
10400 /* Even if the stack pointer isn't the CFA register, we need to correctly
10401 describe the adjustments made to it, in particular differentiate the
10402 frame-related ones from the frame-unrelated ones. */
10404 {
10417 }
10419 /* Make sure nothing is scheduled before we are done. */
10421 }
10423 /* Adjust the stack pointer up to REG while probing it. */
10427 {
10437 /* Jump to END_LAB if SP == LAST_ADDR. */
10445 /* SP = SP + PROBE_INTERVAL. */
10449 /* Probe at SP. */
10460 }
10462 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10463 inclusive. These are offsets from the current stack pointer. */
10465 static void
10467 {
10468 /* See if we have a constant small number of probes to generate. If so,
10469 that's the easy case. The run-time loop is made up of 7 insns in the
10470 generic case while the compile-time loop is made up of n insns for n #
10471 of intervals. */
10473 {
10474 HOST_WIDE_INT i;
10476 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10477 it exceeds SIZE. If only one probe is needed, this will not
10478 generate any code. Then probe at FIRST + SIZE. */
10485 }
10487 /* Otherwise, do the same as above, but in a loop. Note that we must be
10488 extra careful with variables wrapping around because we might be at
10489 the very top (or the very bottom) of the address space and we have
10490 to be able to handle this case properly; in particular, we use an
10491 equality test for the loop condition. */
10492 else
10493 {
10500 /* Step 1: round SIZE to the previous multiple of the interval. */
10505 /* Step 2: compute initial and final value of the loop counter. */
10507 /* TEST_OFFSET = FIRST. */
10510 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10514 /* Step 3: the loop
10516 while (TEST_ADDR != LAST_ADDR)
10517 {
10518 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10519 probe at TEST_ADDR
10520 }
10522 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10523 until it is equal to ROUNDED_SIZE. */
10528 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10529 that SIZE is equal to ROUNDED_SIZE. */
10534 stack_pointer_rtx,
10539 }
10541 /* Make sure nothing is scheduled before we are done. */
10543 }
10545 /* Probe a range of stack addresses from REG to END, inclusive. These are
10546 offsets from the current stack pointer. */
10550 {
10560 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10568 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10572 /* Probe at TEST_ADDR. */
10585 }
10587 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10588 to be generated in correct form. */
10589 static void
10591 {
10592 /* Check if stack realign is really needed after reload, and
10593 stores result in cfun */
10594 unsigned int incoming_stack_boundary
10603 {
10604 /* After stack_realign_needed is finalized, we can't no longer
10605 change it. */
10608 }
10610 /* If the only reason for frame_pointer_needed is that we conservatively
10611 assumed stack realignment might be needed, but in the end nothing that
10612 needed the stack alignment had been spilled, clear frame_pointer_needed
10613 and say we don't need stack realignment. */
10615 && frame_pointer_needed
10617 && flag_omit_frame_pointer
10619 && !ix86_current_function_calls_tls_descriptor
10628 {
10630 basic_block bb;
10637 HARD_FRAME_POINTER_REGNUM);
10639 {
10640 rtx insn;
10644 set_up_by_prologue))
10645 {
10649 }
10650 }
10652 /* If drap has been set, but it actually isn't live at the start
10653 of the function, there is no reason to set it up. */
10655 {
10658 {
10661 }
10662 }
10663 else
10678 }
10682 }
10684 /* Expand the prologue into a bunch of separate insns. */
10686 void
10688 {
10693 HOST_WIDE_INT allocate;
10699 /* DRAP should not coexist with stack_realign_fp */
10704 /* Initialize CFA state for before the prologue. */
10708 /* Track SP offset to the CFA. We continue tracking this after we've
10709 swapped the CFA register away from SP. In the case of re-alignment
10710 this is fudged; we're interested to offsets within the local frame. */
10717 {
10718 /* We should have already generated an error for any use of
10719 ms_hook on a nested function. */
10722 /* Check if profiling is active and we shall use profiling before
10723 prologue variant. If so sorry. */
10728 /* In ix86_asm_output_function_label we emitted:
10729 8b ff movl.s %edi,%edi
10730 55 push %ebp
10731 8b ec movl.s %esp,%ebp
10733 This matches the hookable function prologue in Win32 API
10734 functions in Microsoft Windows XP Service Pack 2 and newer.
10735 Wine uses this to enable Windows apps to hook the Win32 API
10736 functions provided by Wine.
10738 What that means is that we've already set up the frame pointer. */
10742 {
10745 /* We've decided to use the frame pointer already set up.
10746 Describe this to the unwinder by pretending that both
10747 push and mov insns happen right here.
10749 Putting the unwind info here at the end of the ms_hook
10750 is done so that we can make absolutely certain we get
10751 the required byte sequence at the start of the function,
10752 rather than relying on an assembler that can produce
10753 the exact encoding required.
10755 However it does mean (in the unpatched case) that we have
10756 a 1 insn window where the asynchronous unwind info is
10757 incorrect. However, if we placed the unwind info at
10758 its correct location we would have incorrect unwind info
10759 in the patched case. Which is probably all moot since
10760 I don't expect Wine generates dwarf2 unwind info for the
10761 system libraries that use this feature. */
10767 stack_pointer_rtx);
10775 /* Note that gen_push incremented m->fs.cfa_offset, even
10776 though we didn't emit the push insn here. */
10780 }
10781 else
10782 {
10783 /* The frame pointer is not needed so pop %ebp again.
10784 This leaves us with a pristine state. */
10786 }
10787 }
10789 /* The first insn of a function that accepts its static chain on the
10790 stack is to push the register that would be filled in by a direct
10791 call. This insn will be skipped by the trampoline. */
10793 {
10797 /* We don't want to interpret this push insn as a register save,
10798 only as a stack adjustment. The real copy of the register as
10799 a save will be done later, if needed. */
10804 }
10806 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10807 of DRAP is needed and stack realignment is really needed after reload */
10809 {
10812 /* Only need to push parameter pointer reg if it is caller saved. */
10814 {
10815 /* Push arg pointer reg */
10818 }
10820 /* Grab the argument pointer. */
10827 /* Align the stack. */
10829 stack_pointer_rtx,
10833 /* Replicate the return address on the stack so that return
10834 address can be reached via (argp - 1) slot. This is needed
10835 to implement macro RETURN_ADDR_RTX and intrinsic function
10836 expand_builtin_return_addr etc. */
10842 /* For the purposes of frame and register save area addressing,
10843 we've started over with a new frame. */
10846 }
10852 {
10853 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10854 slower on all targets. Also sdb doesn't like it. */
10858 /* Push registers now, before setting the frame pointer
10859 on SEH target. */
10861 && TARGET_SEH
10863 {
10867 }
10870 {
10878 }
10879 }
10882 {
10883 /* If saving registers via PUSH, do so now. */
10885 {
10889 }
10891 /* When using red zone we may start register saving before allocating
10892 the stack frame saving one cycle of the prologue. However, avoid
10893 doing this if we have to probe the stack; at least on x86_64 the
10894 stack probe can turn into a call that clobbers a red zone location. */
10896 && (! TARGET_STACK_PROBE
10898 {
10901 }
10902 }
10905 {
10909 /* The computation of the size of the re-aligned stack frame means
10910 that we must allocate the size of the register save area before
10911 performing the actual alignment. Otherwise we cannot guarantee
10912 that there's enough storage above the realignment point. */
10919 /* Align the stack. */
10921 stack_pointer_rtx,
10924 /* For the purposes of register save area addressing, the stack
10925 pointer is no longer valid. As for the value of sp_offset,
10926 see ix86_compute_frame_layout, which we need to match in order
10927 to pass verification of stack_pointer_offset at the end. */
10930 }
10935 {
10936 /* We start to count from ARG_POINTER. */
10939 /* If it was realigned, take into account the fake frame. */
10941 {
10948 /* This over-estimates by 1 minimal-stack-alignment-unit but
10949 mitigates that by counting in the new return address slot. */
10950 current_function_dynamic_stack_size
10952 }
10955 }
10957 /* On SEH target with very large frame size, allocate an area to save
10958 SSE registers (as the very large allocation won't be described). */
10962 {
10963 HOST_WIDE_INT sse_size =
10968 /* No need to do stack checking as the area will be immediately
10969 written. */
10976 }
10978 /* The stack has already been decremented by the instruction calling us
10979 so probe if the size is non-negative to preserve the protection area. */
10981 {
10982 /* We expect the registers to be saved when probes are used. */
10986 {
10989 {
10992 }
10993 }
10994 else
10995 {
11002 {
11004 {
11007 }
11008 else
11010 }
11011 else
11012 {
11014 {
11018 }
11019 else
11021 }
11022 }
11023 }
11026 ;
11029 {
11033 }
11034 else
11035 {
11047 {
11050 /* Note that SEH directives need to continue tracking the stack
11051 pointer even after the frame pointer has been set up. */
11053 {
11057 }
11058 }
11061 {
11066 {
11070 }
11071 }
11076 /* Use the fact that AX still contains ALLOCATE. */
11078 ? gen_pro_epilogue_adjust_stack_di_sub
11085 {
11093 }
11096 /* Use stack_pointer_rtx for relative addressing so that code
11097 works for realigned stack, too. */
11099 {
11106 }
11108 {
11113 }
11114 }
11117 /* If we havn't already set up the frame pointer, do so now. */
11119 {
11131 }
11139 /* We don't use pic-register for pe-coff target. */
11141 && !TARGET_PECOFF
11144 {
11151 }
11154 {
11156 {
11158 {
11168 label));
11172 }
11173 else
11175 }
11176 else
11177 {
11181 }
11182 }
11184 /* In the pic_reg_used case, make sure that the got load isn't deleted
11185 when mcount needs it. Blockage to avoid call movement across mcount
11186 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11187 note. */
11192 {
11193 /* vDRAP is setup but after reload it turns out stack realign
11194 isn't necessary, here we will emit prologue to setup DRAP
11195 without stack realign adjustment */
11198 }
11200 /* Prevent instructions from being scheduled into register save push
11201 sequence when access to the redzone area is done through frame pointer.
11202 The offset between the frame pointer and the stack pointer is calculated
11203 relative to the value of the stack pointer at the end of the function
11204 prologue, and moving instructions that access redzone area via frame
11205 pointer inside push sequence violates this assumption. */
11209 /* Emit cld instruction if stringops are used in the function. */
11213 /* SEH requires that the prologue end within 256 bytes of the start of
11214 the function. Prevent instruction schedules that would extend that.
11215 Further, prevent alloca modifications to the stack pointer from being
11216 combined with prologue modifications. */
11219 }
11221 /* Emit code to restore REG using a POP insn. */
11223 static void
11225 {
11234 {
11235 /* Previously we'd represented the CFA as an expression
11236 like *(%ebp - 8). We've just popped that value from
11237 the stack, which means we need to reset the CFA to
11238 the drap register. This will remain until we restore
11239 the stack pointer. */
11243 /* This means that the DRAP register is valid for addressing too. */
11246 }
11249 {
11256 }
11258 /* When the frame pointer is the CFA, and we pop it, we are
11259 swapping back to the stack pointer as the CFA. This happens
11260 for stack frames that don't allocate other data, so we assume
11261 the stack pointer is now pointing at the return address, i.e.
11262 the function entry state, which makes the offset be 1 word. */
11264 {
11267 {
11275 }
11276 }
11277 }
11279 /* Emit code to restore saved registers using POP insns. */
11281 static void
11283 {
11289 }
11291 /* Emit code and notes for the LEAVE instruction. */
11293 static void
11295 {
11307 {
11315 }
11318 }
11320 /* Emit code to restore saved registers using MOV insns.
11321 First register is restored from CFA - CFA_OFFSET. */
11322 static void
11325 {
11331 {
11340 {
11341 /* Previously we'd represented the CFA as an expression
11342 like *(%ebp - 8). We've just popped that value from
11343 the stack, which means we need to reset the CFA to
11344 the drap register. This will remain until we restore
11345 the stack pointer. */
11349 /* This means that the DRAP register is valid for addressing. */
11351 }
11352 else
11356 }
11357 }
11359 /* Emit code to restore saved registers using MOV insns.
11360 First register is restored from CFA - CFA_OFFSET. */
11361 static void
11364 {
11369 {
11371 rtx mem;
11381 }
11382 }
11384 /* Restore function stack, frame, and registers. */
11386 void
11388 {
11404 /* The FP must be valid if the frame pointer is present. */
11409 /* We must have *some* valid pointer to the stack frame. */
11412 /* The DRAP is never valid at this point. */
11415 /* See the comment about red zone and frame
11416 pointer usage in ix86_expand_prologue. */
11423 /* Determine the CFA offset of the end of the red-zone. */
11426 {
11427 /* The red-zone begins below the return address. */
11430 /* When the register save area is in the aligned portion of
11431 the stack, determine the maximum runtime displacement that
11432 matches up with the aligned frame. */
11436 }
11438 /* Special care must be taken for the normal return case of a function
11439 using eh_return: the eax and edx registers are marked as saved, but
11440 not restored along this path. Adjust the save location to match. */
11444 /* EH_RETURN requires the use of moves to function properly. */
11447 /* SEH requires the use of pops to identify the epilogue. */
11450 /* If we're only restoring one register and sp is not valid then
11451 using a move instruction to restore the register since it's
11452 less work than reloading sp and popping the register. */
11465 && TARGET_USE_LEAVE
11469 else
11473 {
11474 /* Ensure that the entire register save area is addressable via
11475 the stack pointer, if we will restore via sp. */
11480 {
11484 style,
11486 }
11487 }
11489 /* If there are any SSE registers to restore, then we have to do it
11490 via moves, since there's obviously no pop for SSE regs. */
11496 {
11497 rtx t;
11502 /* eh_return epilogues need %ecx added to the stack pointer. */
11504 {
11507 /* Stack align doesn't work with eh_return. */
11509 /* Neither does regparm nested functions. */
11513 {
11521 /* Note that we use SA as a temporary CFA, as the return
11522 address is at the proper place relative to it. We
11523 pretend this happens at the FP restore insn because
11524 prior to this insn the FP would be stored at the wrong
11525 offset relative to SA, and after this insn we have no
11526 other reasonable register to use for the CFA. We don't
11527 bother resetting the CFA to the SP for the duration of
11528 the return insn. */
11541 }
11542 else
11543 {
11551 {
11555 UNITS_PER_WORD));
11557 }
11558 }
11561 }
11562 }
11563 else
11564 {
11565 /* SEH requires that the function end with (1) a stack adjustment
11566 if necessary, (2) a sequence of pops, and (3) a return or
11567 jump instruction. Prevent insns from the function body from
11568 being scheduled into this sequence. */
11570 {
11571 /* Prevent a catch region from being adjacent to the standard
11572 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11573 several other flags that would be interesting to test are
11574 not yet set up. */
11577 else
11579 }
11581 /* First step is to deallocate the stack frame so that we can
11582 pop the registers. Also do it on SEH target for very large
11583 frame as the emitted instructions aren't allowed by the ABI in
11584 epilogues. */
11586 || (TARGET_SEH
11589 {
11594 }
11596 {
11600 style,
11602 }
11605 }
11607 /* If we used a stack pointer and haven't already got rid of it,
11608 then do so now. */
11610 {
11611 /* If the stack pointer is valid and pointing at the frame
11612 pointer store address, then we only need a pop. */
11615 /* Leave results in shorter dependency chains on CPUs that are
11616 able to grok it fast. */
11621 else
11622 {
11624 hard_frame_pointer_rtx,
11627 }
11628 }
11631 {
11633 rtx insn;
11659 }
11661 /* At this point the stack pointer must be valid, and we must have
11662 restored all of the registers. We may not have deallocated the
11663 entire stack frame. We've delayed this until now because it may
11664 be possible to merge the local stack deallocation with the
11665 deallocation forced by ix86_static_chain_on_stack. */
11670 {
11674 }
11675 else
11678 /* Sibcall epilogues don't want a return instruction. */
11680 {
11683 }
11686 {
11689 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11690 address, do explicit add, and jump indirectly to the caller. */
11693 {
11695 rtx insn;
11697 /* There is no "pascal" calling convention in any 64bit ABI. */
11713 }
11714 else
11716 }
11717 else
11720 /* Restore the state back to the state from the prologue,
11721 so that it's correct for the next epilogue. */
11723 }
11725 /* Reset from the function's potential modifications. */
11727 static void
11729 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11730 {
11733 #if TARGET_MACHO
11734 /* Mach-O doesn't support labels at the end of objects, so if
11735 it looks like we might want one, insert a NOP. */
11736 {
11742 {
11743 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11744 notes only, instead set their CODE_LABEL_NUMBER to -1,
11745 otherwise there would be code generation differences
11746 in between -g and -g0. */
11750 }
11760 }
11761 #endif
11763 }
11765 /* Return a scratch register to use in the split stack prologue. The
11766 split stack prologue is used for -fsplit-stack. It is the first
11767 instructions in the function, even before the regular prologue.
11768 The scratch register can be any caller-saved register which is not
11769 used for parameters or for the static chain. */
11771 static unsigned int
11773 {
11776 else
11777 {
11790 {
11792 {
11796 }
11798 }
11800 {
11804 }
11806 {
11809 else
11810 {
11812 {
11816 }
11818 }
11819 }
11820 else
11821 {
11822 /* FIXME: We could make this work by pushing a register
11823 around the addition and comparison. */
11826 }
11827 }
11828 }
11830 /* A SYMBOL_REF for the function which allocates new stackspace for
11831 -fsplit-stack. */
11835 /* A SYMBOL_REF for the more stack function when using the large
11836 model. */
11840 /* Handle -fsplit-stack. These are the first instructions in the
11841 function, even before the regular prologue. */
11843 void
11845 {
11847 HOST_WIDE_INT allocate;
11852 rtx fn;
11860 /* This is the label we will branch to if we have enough stack
11861 space. We expect the basic block reordering pass to reverse this
11862 branch if optimizing, so that we branch in the unlikely case. */
11865 /* We need to compare the stack pointer minus the frame size with
11866 the stack boundary in the TCB. The stack boundary always gives
11867 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11868 can compare directly. Otherwise we need to do an addition. */
11871 UNSPEC_STACK_CHECK);
11876 else
11877 {
11879 rtx offset;
11881 /* We need a scratch register to hold the stack pointer minus
11882 the required frame size. Since this is the very start of the
11883 function, the scratch register can be any caller-saved
11884 register which is not used for parameters. */
11891 {
11892 /* We don't use ix86_gen_add3 in this case because it will
11893 want to split to lea, but when not optimizing the insn
11894 will not be split after this point. */
11897 offset)));
11898 }
11899 else
11900 {
11903 stack_pointer_rtx));
11904 }
11906 }
11912 /* Mark the jump as very likely to be taken. */
11920 /* Get more stack space. We pass in the desired stack space and the
11921 size of the arguments to copy to the new stack. In 32-bit mode
11922 we push the parameters; __morestack will return on a new stack
11923 anyhow. In 64-bit mode we pass the parameters in r10 and
11924 r11. */
11929 {
11935 /* If this function uses a static chain, it will be in %r10.
11936 Preserve it across the call to __morestack. */
11938 {
11939 rtx rax;
11944 }
11948 {
11949 HOST_WIDE_INT argval;
11952 /* When using the large model we need to load the address
11953 into a register, and we've run out of registers. So we
11954 switch to a different calling convention, and we call a
11955 different function: __morestack_large. We pass the
11956 argument size in the upper 32 bits of r10 and pass the
11957 frame size in the lower 32 bits. */
11962 split_stack_fn_large =
11966 {
11976 UNSPEC_GOT);
11982 }
11983 else
11990 }
11991 else
11992 {
11996 }
11999 }
12000 else
12001 {
12004 }
12010 /* In order to make call/return prediction work right, we now need
12011 to execute a return instruction. See
12012 libgcc/config/i386/morestack.S for the details on how this works.
12014 For flow purposes gcc must not see this as a return
12015 instruction--we need control flow to continue at the subsequent
12016 label. Therefore, we use an unspec. */
12020 /* If we are in 64-bit mode and this function uses a static chain,
12021 we saved %r10 in %rax before calling _morestack. */
12026 /* If this function calls va_start, we need to store a pointer to
12027 the arguments on the old stack, because they may not have been
12028 all copied to the new stack. At this point the old stack can be
12029 found at the frame pointer value used by __morestack, because
12030 __morestack has set that up before calling back to us. Here we
12031 store that pointer in a scratch register, and in
12032 ix86_expand_prologue we store the scratch register in a stack
12033 slot. */
12035 {
12037 rtx frame_reg;
12044 /* 64-bit:
12045 fp -> old fp value
12046 return address within this function
12047 return address of caller of this function
12048 stack arguments
12049 So we add three words to get to the stack arguments.
12051 32-bit:
12052 fp -> old fp value
12053 return address within this function
12054 first argument to __morestack
12055 second argument to __morestack
12056 return address of caller of this function
12057 stack arguments
12058 So we add five words to get to the stack arguments.
12059 */
12070 }
12075 /* If this function calls va_start, we now have to set the scratch
12076 register for the case where we do not call __morestack. In this
12077 case we need to set it based on the stack pointer. */
12079 {
12086 }
12087 }
12089 /* We may have to tell the dataflow pass that the split stack prologue
12090 is initializing a scratch register. */
12092 static void
12094 {
12096 {
12099 }
12100 }
12101 \f
12102 /* Extract the parts of an RTL expression that is a valid memory address
12103 for an instruction. Return 0 if the structure of the address is
12104 grossly off. Return -1 if the address contains ASHIFT, so it is not
12105 strictly valid, but still used for computing length of lea instruction. */
12107 int
12109 {
12114 rtx tmp;
12118 /* Allow zero-extended SImode addresses,
12119 they will be emitted with addr32 prefix. */
12121 {
12124 {
12128 }
12131 {
12138 }
12139 }
12141 /* Allow SImode subregs of DImode addresses,
12142 they will be emitted with addr32 prefix. */
12144 {
12147 {
12151 }
12152 }
12157 {
12160 else
12162 }
12164 {
12169 do
12170 {
12175 }
12182 {
12185 {
12210 /* FALLTHRU */
12214 && TARGET_TLS_DIRECT_SEG_REFS
12217 else
12224 /* FALLTHRU */
12231 else
12246 }
12247 }
12248 }
12250 {
12253 }
12255 {
12256 /* We're called for lea too, which implements ashift on occasion. */
12266 }
12267 else
12271 {
12273 ;
12276 ;
12277 else
12279 }
12281 /* Extract the integral value of scale. */
12283 {
12287 }
12292 /* Avoid useless 0 displacement. */
12296 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12301 {
12302 rtx tmp;
12305 }
12307 /* Special case: %ebp cannot be encoded as a base without a displacement.
12308 Similarly %r13. */
12310 && base_reg
12319 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12320 Avoid this by transforming to [%esi+0].
12321 Reload calls address legitimization without cfun defined, so we need
12322 to test cfun for being non-NULL. */
12328 /* Special case: encode reg+reg instead of reg*2. */
12332 /* Special case: scaling cannot be encoded without base or displacement. */
12343 }
12344 \f
12345 /* Return cost of the memory address x.
12346 For i386, it is better to use a complex address than let gcc copy
12347 the address into a reg and make a new pseudo. But not if the address
12348 requires to two regs - that would mean more pseudos with longer
12349 lifetimes. */
12350 static int
12352 addr_space_t as ATTRIBUTE_UNUSED,
12354 {
12366 /* Attempt to minimize number of registers in the address. */
12372 cost++;
12379 cost++;
12381 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12382 since it's predecode logic can't detect the length of instructions
12383 and it degenerates to vector decoded. Increase cost of such
12384 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12385 to split such addresses or even refuse such addresses at all.
12387 Following addressing modes are affected:
12388 [base+scale*index]
12389 [scale*index+disp]
12390 [base+index]
12392 The first and last case may be avoidable by explicitly coding the zero in
12393 memory address, but I don't have AMD-K6 machine handy to check this
12394 theory. */
12403 }
12404 \f
12405 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12406 this is used for to form addresses to local data when -fPIC is in
12407 use. */
12409 static bool
12411 {
12414 }
12416 /* Determine if a given RTX is a valid constant. We already know this
12417 satisfies CONSTANT_P. */
12419 static bool
12421 {
12423 {
12428 {
12432 }
12437 /* Only some unspecs are valid as "constants". */
12440 {
12456 }
12458 /* We must have drilled down to a symbol. */
12463 /* FALLTHRU */
12466 /* TLS symbols are never valid. */
12470 /* DLLIMPORT symbols are never valid. */
12475 #if TARGET_MACHO
12476 /* mdynamic-no-pic */
12479 #endif
12495 }
12497 /* Otherwise we handle everything else in the move patterns. */
12499 }
12501 /* Determine if it's legal to put X into the constant pool. This
12502 is not possible for the address of thread-local symbols, which
12503 is checked above. */
12505 static bool
12507 {
12508 /* We can always put integral constants and vectors in memory. */
12510 {
12518 }
12520 }
12522 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12523 otherwise zero. */
12525 static bool
12527 {
12533 }
12536 /* Nonzero if the constant value X is a legitimate general operand
12537 when generating PIC code. It is given that flag_pic is on and
12538 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12540 bool
12542 {
12543 rtx inner;
12546 {
12553 /* Only some unspecs are valid as "constants". */
12556 {
12569 }
12570 /* FALLTHRU */
12578 }
12579 }
12581 /* Determine if a given CONST RTX is a valid memory displacement
12582 in PIC mode. */
12584 bool
12586 {
12589 /* In 64bit mode we can allow direct addresses of symbols and labels
12590 when they are not dynamic symbols. */
12592 {
12596 {
12620 /* FALLTHRU */
12623 /* TLS references should always be enclosed in UNSPEC.
12624 The dllimported symbol needs always to be resolved. */
12630 {
12638 /* Function-symbols need to be resolved only for
12639 large-model.
12640 For the small-model we don't need to resolve anything
12641 here. */
12646 /* Non-external symbols don't need to be resolved for
12647 large, and medium-model. */
12652 }
12661 }
12662 }
12668 {
12669 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12670 of GOT tables. We should not need these anyway. */
12682 }
12686 {
12691 }
12700 {
12704 /* We need to check for both symbols and labels because VxWorks loads
12705 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12706 details. */
12710 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12711 While ABI specify also 32bit relocation but we don't produce it in
12712 small PIC model at all. */
12734 }
12737 }
12739 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12740 replace the input X, or the original X if no replacement is called for.
12741 The output parameter *WIN is 1 if the calling macro should goto WIN,
12742 0 if it should not. */
12744 bool
12749 {
12750 /* Reload can generate:
12752 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12753 (reg:DI 97))
12754 (reg:DI 2 cx))
12756 This RTX is rejected from ix86_legitimate_address_p due to
12757 non-strictness of base register 97. Following this rejection,
12758 reload pushes all three components into separate registers,
12759 creating invalid memory address RTX.
12761 Following code reloads only the invalid part of the
12762 memory address RTX. */
12768 {
12774 {
12779 }
12783 {
12788 }
12792 }
12795 }
12797 /* Determine if op is suitable RTX for an address register.
12798 Return naked register if a register or a register subreg is
12799 found, otherwise return NULL_RTX. */
12801 static rtx
12803 {
12806 /* Only SImode or DImode registers can form the address. */
12813 {
12821 /* Don't allow SUBREGs that span more than a word. It can
12822 lead to spill failures when the register is one word out
12823 of a two word structure. */
12827 /* Allow only SUBREGs of non-eliminable hard registers. */
12830 }
12832 /* Op is not a register. */
12834 }
12836 /* Recognizes RTL expressions that are valid memory addresses for an
12837 instruction. The MODE argument is the machine mode for the MEM
12838 expression that wants to use this address.
12840 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12841 convert common non-canonical forms to canonical form so that they will
12842 be recognized. */
12844 static bool
12847 {
12850 HOST_WIDE_INT scale;
12854 /* Decomposition failed. */
12863 /* Validate base register. */
12865 {
12873 /* Base is not valid. */
12875 }
12877 /* Validate index register. */
12879 {
12887 /* Index is not valid. */
12889 }
12891 /* Index and base should have the same mode. */
12896 /* Address override works only on the (%reg) part of %fs:(%reg). */
12902 /* Validate scale factor. */
12904 {
12906 /* Scale without index. */
12910 /* Scale is not a valid multiplier. */
12912 }
12914 /* Validate displacement. */
12916 {
12921 {
12922 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12923 used. While ABI specify also 32bit relocations, we don't produce
12924 them at all and use IP relative instead. */
12931 /* 64bit address unspec. */
12951 /* Invalid address unspec. */
12953 }
12956 && (flag_pic
12957 || (TARGET_MACHO
12958 #if TARGET_MACHO
12959 && MACHOPIC_INDIRECT
12961 #endif
12962 )))
12963 {
12965 is_legitimate_pic:
12967 {
12968 /* foo@dtpoff(%rX) is ok. */
12975 /* Non-constant pic memory reference. */
12977 }
12980 /* Displacement is an invalid pic construct. */
12982 #if TARGET_MACHO
12985 /* displacment must be referenced via non_lazy_pointer */
12987 #endif
12989 /* This code used to verify that a symbolic pic displacement
12990 includes the pic_offset_table_rtx register.
12992 While this is good idea, unfortunately these constructs may
12993 be created by "adds using lea" optimization for incorrect
12994 code like:
12996 int a;
12997 int foo(int i)
12998 {
12999 return *(&a+i);
13000 }
13002 This code is nonsensical, but results in addressing
13003 GOT table with pic_offset_table_rtx base. We can't
13004 just refuse it easily, since it gets matched by
13005 "addsi3" pattern, that later gets split to lea in the
13006 case output register differs from input. While this
13007 can be handled by separate addsi pattern for this case
13008 that never results in lea, this seems to be easier and
13009 correct fix for crash to disable this test. */
13010 }
13017 /* Displacement is not constant. */
13021 /* Displacement is out of range. */
13023 /* In x32 mode, constant addresses are sign extended to 64bit, so
13024 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13029 }
13031 /* Everything looks valid. */
13033 }
13035 /* Determine if a given RTX is a valid constant address. */
13037 bool
13039 {
13041 }
13042 \f
13043 /* Return a unique alias set for the GOT. */
13045 static alias_set_type
13047 {
13052 }
13054 /* Return a legitimate reference for ORIG (an address) using the
13055 register REG. If REG is 0, a new pseudo is generated.
13057 There are two types of references that must be handled:
13059 1. Global data references must load the address from the GOT, via
13060 the PIC reg. An insn is emitted to do this load, and the reg is
13061 returned.
13063 2. Static data references, constant pool addresses, and code labels
13064 compute the address as an offset from the GOT, whose base is in
13065 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13066 differentiate them from global data objects. The returned
13067 address is the PIC reg + an unspec constant.
13069 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13070 reg also appears in the address. */
13072 static rtx
13074 {
13078 #if TARGET_MACHO
13080 {
13083 /* Use the generic Mach-O PIC machinery. */
13085 }
13086 #endif
13089 {
13093 }
13099 {
13100 rtx tmpreg;
13101 /* This symbol may be referenced via a displacement from the PIC
13102 base address (@GOTOFF). */
13109 {
13111 UNSPEC_GOTOFF);
13113 }
13114 else
13119 else
13124 {
13128 }
13129 else
13131 }
13133 {
13134 /* This symbol may be referenced via a displacement from the PIC
13135 base address (@GOTOFF). */
13142 {
13144 UNSPEC_GOTOFF);
13146 }
13147 else
13153 {
13156 }
13157 }
13159 /* We can't use @GOTOFF for text labels on VxWorks;
13160 see gotoff_operand. */
13162 {
13167 /* For x64 PE-COFF there is no GOT table. So we use address
13168 directly. */
13170 {
13178 }
13180 {
13188 /* Use directly gen_movsi, otherwise the address is loaded
13189 into register for CSE. We don't want to CSE this addresses,
13190 instead we CSE addresses from the GOT table, so skip this. */
13193 }
13194 else
13195 {
13196 /* This symbol must be referenced via a load from the
13197 Global Offset Table (@GOT). */
13213 }
13214 }
13215 else
13216 {
13219 {
13221 {
13224 }
13225 else
13227 }
13229 {
13232 /* We must match stuff we generate before. Assume the only
13233 unspecs that can get here are ours. Not that we could do
13234 anything with them anyway.... */
13240 }
13242 {
13245 /* Check first to see if this is a constant offset from a @GOTOFF
13246 symbol reference. */
13249 {
13251 {
13255 UNSPEC_GOTOFF);
13261 {
13264 }
13265 }
13266 else
13267 {
13270 {
13274 }
13275 }
13276 }
13277 else
13278 {
13281 new_rtx
13285 {
13288 {
13291 new_rtx
13293 }
13294 else
13296 }
13297 else
13298 {
13301 {
13304 }
13306 }
13307 }
13308 }
13309 }
13311 }
13312 \f
13313 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13315 static rtx
13317 {
13321 {
13326 }
13332 }
13334 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13338 static rtx
13340 {
13342 {
13348 }
13351 {
13353 UNSPEC_PLTOFF);
13356 }
13359 }
13361 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13365 rtx
13367 {
13369 {
13370 ix86_tls_module_base_symbol
13375 }
13378 }
13380 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13381 false if we expect this to be used for a memory address and true if
13382 we expect to load the address into a register. */
13384 static rtx
13386 {
13393 {
13398 {
13401 else
13402 {
13405 }
13406 }
13409 {
13412 else
13422 }
13423 else
13424 {
13428 {
13430 rtx insns;
13433 emit_call_insn
13443 }
13444 else
13446 }
13453 {
13456 else
13457 {
13460 }
13461 }
13464 {
13469 else
13475 }
13476 else
13477 {
13481 {
13486 emit_call_insn
13491 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13492 share the LD_BASE result with other LD model accesses. */
13494 UNSPEC_TLS_LD_BASE);
13498 }
13499 else
13501 }
13509 {
13516 }
13521 {
13523 {
13524 /* The Sun linker took the AMD64 TLS spec literally
13525 and can only handle %rax as destination of the
13526 initial executable code sequence. */
13531 }
13533 /* Generate DImode references to avoid %fs:(%reg32)
13534 problems and linker IE->LE relaxation bug. */
13538 }
13540 {
13545 }
13547 {
13551 }
13552 else
13553 {
13556 }
13566 {
13571 }
13572 else
13573 {
13577 }
13587 {
13591 }
13592 else
13593 {
13597 }
13602 }
13605 }
13607 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13608 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13609 unique refptr-DECL symbol corresponding to symbol DECL. */
13612 htab_t dllimport_map;
13614 static tree
13616 {
13623 tree to;
13624 rtx rtl;
13651 else
13664 {
13666 #ifdef SUB_TARGET_RECORD_STUB
13668 #endif
13669 }
13678 }
13680 /* Expand SYMBOL into its corresponding far-addresse symbol.
13681 WANT_REG is true if we require the result be a register. */
13683 static rtx
13685 {
13686 tree imp_decl;
13687 rtx x;
13696 }
13698 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13699 true if we require the result be a register. */
13701 static rtx
13703 {
13704 tree imp_decl;
13705 rtx x;
13714 }
13716 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13717 is true if we require the result be a register. */
13719 static rtx
13721 {
13726 {
13733 {
13736 }
13737 }
13753 {
13756 }
13758 }
13760 /* Try machine-dependent ways of modifying an illegitimate address
13761 to be legitimate. If we find one, return the new, valid address.
13762 This macro is used in only one place: `memory_address' in explow.c.
13764 OLDX is the address as it was before break_out_memory_refs was called.
13765 In some cases it is useful to look at this to decide what needs to be done.
13767 It is always safe for this macro to do nothing. It exists to recognize
13768 opportunities to optimize the output.
13770 For the 80386, we handle X+REG by loading X into a register R and
13771 using R+REG. R will go in a general reg and indexing will be used.
13772 However, if REG is a broken-out memory address or multiplication,
13773 nothing needs to be done because REG can certainly go in a general reg.
13775 When -fpic is used, special handling is needed for symbolic references.
13776 See comments by legitimize_pic_address in i386.c for details. */
13778 static rtx
13781 {
13792 {
13796 }
13799 {
13803 }
13808 #if TARGET_MACHO
13811 #endif
13813 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13817 {
13822 }
13825 {
13826 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13831 {
13837 }
13842 {
13848 }
13850 /* Put multiply first if it isn't already. */
13852 {
13857 }
13859 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13860 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13861 created by virtual register instantiation, register elimination, and
13862 similar optimizations. */
13864 {
13870 }
13872 /* Canonicalize
13873 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13874 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13879 {
13880 rtx constant;
13884 {
13887 }
13889 {
13892 }
13893 else
13897 {
13904 }
13905 }
13911 {
13914 }
13917 {
13920 }
13928 {
13931 }
13937 {
13941 {
13944 }
13948 }
13951 {
13955 {
13958 }
13962 }
13963 }
13966 }
13967 \f
13968 /* Print an integer constant expression in assembler syntax. Addition
13969 and subtraction are the only arithmetic that may appear in these
13970 expressions. FILE is the stdio stream to write to, X is the rtx, and
13971 CODE is the operand print code from the output string. */
13973 static void
13975 {
13979 {
13988 else
13989 {
13992 /* Mark the decl as referenced so that cgraph will
13993 output the function. */
13997 #if TARGET_MACHO
14001 #endif
14003 }
14011 /* FALLTHRU */
14022 /* This used to output parentheses around the expression,
14023 but that does not work on the 386 (either ATT or BSD assembler). */
14029 {
14030 /* We can use %d if the number is <32 bits and positive. */
14035 else
14037 }
14038 else
14039 /* We can't handle floating point constants;
14040 TARGET_PRINT_OPERAND must handle them. */
14045 /* Some assemblers need integer constants to appear first. */
14047 {
14051 }
14052 else
14053 {
14058 }
14073 {
14077 }
14082 {
14101 /* FIXME: This might be @TPOFF in Sun ld too. */
14110 else
14120 else
14126 #if TARGET_MACHO
14131 #endif
14135 }
14140 }
14141 }
14143 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14144 We need to emit DTP-relative relocations. */
14146 static void ATTRIBUTE_UNUSED
14148 {
14153 {
14161 }
14162 }
14164 /* Return true if X is a representation of the PIC register. This copes
14165 with calls from ix86_find_base_term, where the register might have
14166 been replaced by a cselib value. */
14168 static bool
14170 {
14174 else
14176 }
14178 /* Helper function for ix86_delegitimize_address.
14179 Attempt to delegitimize TLS local-exec accesses. */
14181 static rtx
14183 {
14208 {
14213 }
14219 }
14221 /* In the name of slightly smaller debug output, and to cater to
14222 general assembler lossage, recognize PIC+GOTOFF and turn it back
14223 into a direct symbol reference.
14225 On Darwin, this is necessary to avoid a crash, because Darwin
14226 has a different PIC label for each routine but the DWARF debugging
14227 information is not associated with any particular routine, so it's
14228 necessary to remove references to the PIC label from RTL stored by
14229 the DWARF output code. */
14231 static rtx
14233 {
14235 /* addend is NULL or some rtx if x is something+GOTOFF where
14236 something doesn't include the PIC register. */
14238 /* reg_addend is NULL or a multiple of some register. */
14240 /* const_addend is NULL or a const_int. */
14242 /* This is the result, or NULL. */
14251 {
14258 {
14264 }
14271 {
14274 {
14279 }
14281 }
14286 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14287 and -mcmodel=medium -fpic. */
14288 }
14295 /* %ebx + GOT/GOTOFF */
14296 ;
14298 {
14299 /* %ebx + %reg * scale + GOT/GOTOFF */
14305 else
14306 {
14309 }
14310 }
14311 else
14317 {
14320 }
14341 {
14342 /* If the rest of original X doesn't involve the PIC register, add
14343 addend and subtract pic_offset_table_rtx. This can happen e.g.
14344 for code like:
14345 leal (%ebx, %ecx, 4), %ecx
14346 ...
14347 movl foo@GOTOFF(%ecx), %edx
14348 in which case we return (%ecx - %ebx) + foo. */
14351 pic_offset_table_rtx),
14352 result);
14353 else
14355 }
14357 {
14361 }
14363 }
14365 /* If X is a machine specific address (i.e. a symbol or label being
14366 referenced as a displacement from the GOT implemented using an
14367 UNSPEC), then return the base term. Otherwise return X. */
14369 rtx
14371 {
14372 rtx term;
14375 {
14389 }
14392 }
14393 \f
14394 static void
14397 {
14401 {
14404 }
14409 {
14412 {
14431 }
14435 {
14454 }
14461 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14462 Those same assemblers have the same but opposite lossage on cmov. */
14465 else
14470 {
14483 }
14490 else
14495 {
14508 }
14515 else
14525 else
14536 }
14538 }
14540 /* Print the name of register X to FILE based on its machine mode and number.
14541 If CODE is 'w', pretend the mode is HImode.
14542 If CODE is 'b', pretend the mode is QImode.
14543 If CODE is 'k', pretend the mode is SImode.
14544 If CODE is 'q', pretend the mode is DImode.
14545 If CODE is 'x', pretend the mode is V4SFmode.
14546 If CODE is 't', pretend the mode is V8SFmode.
14547 If CODE is 'g', pretend the mode is V16SFmode.
14548 If CODE is 'h', pretend the reg is the 'high' byte register.
14549 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14550 If CODE is 'd', duplicate the operand for AVX instruction.
14551 */
14553 void
14555 {
14564 {
14568 }
14595 else
14598 /* Irritatingly, AMD extended registers use different naming convention
14599 from the normal registers: "r%d[bwd]" */
14601 {
14606 {
14620 /* no suffix */
14625 }
14627 }
14631 {
14634 {
14637 }
14638 /* FALLTHRU */
14644 /* FALLTHRU */
14647 normal:
14662 {
14667 }
14670 {
14675 }
14679 }
14683 {
14686 else
14688 }
14689 }
14691 /* Locate some local-dynamic symbol still in use by this function
14692 so that we can print its name in some tls_local_dynamic_base
14693 pattern. */
14695 static int
14697 {
14702 {
14705 }
14708 }
14712 {
14713 rtx insn;
14724 }
14726 /* Meaning of CODE:
14727 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14728 C -- print opcode suffix for set/cmov insn.
14729 c -- like C, but print reversed condition
14730 F,f -- likewise, but for floating-point.
14731 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14732 otherwise nothing
14733 R -- print embeded rounding and sae.
14734 r -- print only sae.
14735 z -- print the opcode suffix for the size of the current operand.
14736 Z -- likewise, with special suffixes for x87 instructions.
14737 * -- print a star (in certain assembler syntax)
14738 A -- print an absolute memory reference.
14739 E -- print address with DImode register names if TARGET_64BIT.
14740 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14741 s -- print a shift double count, followed by the assemblers argument
14742 delimiter.
14743 b -- print the QImode name of the register for the indicated operand.
14744 %b0 would print %al if operands[0] is reg 0.
14745 w -- likewise, print the HImode name of the register.
14746 k -- likewise, print the SImode name of the register.
14747 q -- likewise, print the DImode name of the register.
14748 x -- likewise, print the V4SFmode name of the register.
14749 t -- likewise, print the V8SFmode name of the register.
14750 g -- likewise, print the V16SFmode name of the register.
14751 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14752 y -- print "st(0)" instead of "st" as a register.
14753 d -- print duplicated register operand for AVX instruction.
14754 D -- print condition for SSE cmp instruction.
14755 P -- if PIC, print an @PLT suffix.
14756 p -- print raw symbol name.
14757 X -- don't print any sort of PIC '@' suffix for a symbol.
14758 & -- print some in-use local-dynamic symbol name.
14759 H -- print a memory address offset by 8; used for sse high-parts
14760 Y -- print condition for XOP pcom* instruction.
14761 + -- print a branch hint as 'cs' or 'ds' prefix
14762 ; -- print a semicolon (after prefixes due to bug in older gas).
14763 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14764 @ -- print a segment register of thread base pointer load
14765 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14766 */
14768 void
14770 {
14772 {
14774 {
14777 {
14783 /* Intel syntax. For absolute addresses, registers should not
14784 be surrounded by braces. */
14786 {
14791 }
14796 }
14802 /* Wrap address in an UNSPEC to declare special handling. */
14840 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14845 {
14859 output_operand_lossage
14862 }
14865 #endif
14870 {
14871 /* Opcodes don't get size suffixes if using Intel opcodes. */
14876 {
14894 output_operand_lossage
14897 }
14898 }
14901 warning
14903 /* FALLTHRU */
14906 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14911 {
14913 {
14915 #ifdef HAVE_AS_IX86_FILDS
14917 #endif
14925 #ifdef HAVE_AS_IX86_FILDQ
14927 #else
14929 #endif
14934 }
14935 }
14937 {
14938 /* 387 opcodes don't get size suffixes
14939 if the operands are registers. */
14944 {
14960 }
14961 }
14962 else
14963 {
14964 output_operand_lossage
14967 }
14969 output_operand_lossage
14990 {
14993 }
14998 {
15049 }
15053 /* Little bit of braindamage here. The SSE compare instructions
15054 does use completely different names for the comparisons that the
15055 fp conditional moves. */
15057 {
15060 {
15063 }
15069 {
15072 }
15078 {
15081 }
15090 {
15093 }
15099 {
15102 }
15108 {
15111 }
15122 }
15127 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15130 #endif
15135 {
15139 }
15143 file);
15148 {
15152 }
15153 /* It doesn't actually matter what mode we use here, as we're
15154 only going to use this for printing. */
15156 /* Output 'qword ptr' for intel assembler dialect. */
15165 #ifdef HAVE_AS_IX86_HLE
15167 #else
15169 #endif
15171 #ifdef HAVE_AS_IX86_HLE
15173 #else
15175 #endif
15176 /* We do not want to print value of the operand. */
15205 {
15220 }
15233 {
15238 else
15241 }
15244 {
15245 rtx x;
15254 {
15259 {
15261 bool cputaken
15264 /* Emit hints only in the case default branch prediction
15265 heuristics would fail. */
15267 {
15268 /* We use 3e (DS) prefix for taken branches and
15269 2e (CS) prefix for not taken branches. */
15272 else
15274 }
15275 }
15276 }
15278 }
15281 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15283 #endif
15290 /* The kernel uses a different segment register for performance
15291 reasons; a system call would not have to trash the userspace
15292 segment register, which would be expensive. */
15295 else
15310 }
15311 }
15317 {
15318 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15321 {
15324 {
15333 else
15340 }
15342 /* Check for explicit size override (codes 'b', 'w', 'k',
15343 'q' and 'x') */
15357 }
15360 /* Avoid (%rip) for call operands. */
15366 else
15368 }
15371 {
15372 REAL_VALUE_TYPE r;
15380 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15384 else
15386 }
15389 {
15390 REAL_VALUE_TYPE r;
15399 }
15401 /* These float cases don't actually occur as immediate operands. */
15403 {
15408 }
15410 else
15411 {
15412 /* We have patterns that allow zero sets of memory, for instance.
15413 In 64-bit mode, we should probably support all 8-byte vectors,
15414 since we can in fact encode that into an immediate. */
15416 {
15419 }
15422 {
15424 {
15427 }
15430 {
15433 else
15435 }
15436 }
15441 else
15443 }
15444 }
15446 static bool
15448 {
15451 }
15452 \f
15453 /* Print a memory operand whose address is ADDR. */
15455 static void
15457 {
15466 {
15473 }
15475 {
15479 }
15480 else
15491 {
15502 }
15504 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15506 {
15518 }
15520 {
15521 /* Displacement only requires special attention. */
15524 {
15528 }
15531 else
15533 }
15534 else
15535 {
15536 /* Print SImode register names to force addr32 prefix. */
15538 {
15539 #ifdef ENABLE_CHECKING
15542 {
15553 }
15554 #endif
15557 }
15559 && TARGET_X32
15560 && disp
15563 {
15564 /* X32 runs in 64-bit mode, where displacement, DISP, in
15565 address DISP(%r64), is encoded as 32-bit immediate sign-
15566 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15567 address is %r64 + 0xffffffffbffffd00. When %r64 <
15568 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15569 which is invalid for x32. The correct address is %r64
15570 - 0x40000300 == 0xf7ffdd64. To properly encode
15571 -0x40000300(%r64) for x32, we zero-extend negative
15572 displacement by forcing addr32 prefix which truncates
15573 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15574 zero-extend all negative displacements, including -1(%rsp).
15575 However, for small negative displacements, sign-extension
15576 won't cause overflow. We only zero-extend negative
15577 displacements if they < -16*1024*1024, which is also used
15578 to check legitimate address displacements for PIC. */
15580 }
15583 {
15585 {
15590 else
15592 }
15598 {
15603 }
15605 }
15606 else
15607 {
15611 {
15612 /* Pull out the offset of a symbol; print any symbol itself. */
15616 {
15620 }
15628 else
15630 }
15634 {
15637 {
15641 }
15642 }
15645 else
15649 {
15654 }
15656 }
15657 }
15658 }
15660 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15662 static bool
15664 {
15665 rtx op;
15672 {
15675 /* FIXME: This might be @TPOFF in Sun ld. */
15686 else
15698 else
15705 #if TARGET_MACHO
15711 #endif
15714 {
15719 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15721 #else
15723 #endif
15726 }
15731 }
15734 }
15735 \f
15736 /* Split one or more double-mode RTL references into pairs of half-mode
15737 references. The RTL can be REG, offsettable MEM, integer constant, or
15738 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15739 split and "num" is its length. lo_half and hi_half are output arrays
15740 that parallel "operands". */
15742 void
15745 {
15750 {
15759 }
15764 {
15767 /* simplify_subreg refuse to split volatile memory addresses,
15768 but we still have to handle it. */
15770 {
15773 }
15774 else
15775 {
15782 }
15783 }
15784 }
15785 \f
15786 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15787 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15788 is the expression of the binary operation. The output may either be
15789 emitted here, or returned to the caller, like all output_* functions.
15791 There is no guarantee that the operands are the same mode, as they
15792 might be within FLOAT or FLOAT_EXTEND expressions. */
15794 #ifndef SYSV386_COMPAT
15795 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15796 wants to fix the assemblers because that causes incompatibility
15797 with gcc. No-one wants to fix gcc because that causes
15798 incompatibility with assemblers... You can use the option of
15799 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15800 #define SYSV386_COMPAT 1
15801 #endif
15805 {
15811 #ifdef ENABLE_CHECKING
15812 /* Even if we do not want to check the inputs, this documents input
15813 constraints. Which helps in understanding the following code. */
15823 else
15825 #endif
15828 {
15833 else
15842 else
15851 else
15860 else
15867 }
15870 {
15872 {
15876 else
15878 }
15879 else
15880 {
15884 else
15886 }
15888 }
15892 {
15896 {
15900 }
15902 /* know operands[0] == operands[1]. */
15905 {
15908 }
15911 {
15913 /* How is it that we are storing to a dead operand[2]?
15914 Well, presumably operands[1] is dead too. We can't
15915 store the result to st(0) as st(0) gets popped on this
15916 instruction. Instead store to operands[2] (which I
15917 think has to be st(1)). st(1) will be popped later.
15918 gcc <= 2.8.1 didn't have this check and generated
15919 assembly code that the Unixware assembler rejected. */
15921 else
15924 }
15928 else
15935 {
15938 }
15941 {
15944 }
15947 {
15948 #if SYSV386_COMPAT
15949 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15950 derived assemblers, confusingly reverse the direction of
15951 the operation for fsub{r} and fdiv{r} when the
15952 destination register is not st(0). The Intel assembler
15953 doesn't have this brain damage. Read !SYSV386_COMPAT to
15954 figure out what the hardware really does. */
15957 else
15959 #else
15961 /* As above for fmul/fadd, we can't store to st(0). */
15963 else
15965 #endif
15967 }
15970 {
15971 #if SYSV386_COMPAT
15974 else
15976 #else
15979 else
15981 #endif
15983 }
15986 {
15989 else
15992 }
15994 {
15995 #if SYSV386_COMPAT
15997 #else
15999 #endif
16000 }
16001 else
16002 {
16003 #if SYSV386_COMPAT
16005 #else
16007 #endif
16008 }
16013 }
16017 }
16019 /* Check if a 256bit AVX register is referenced inside of EXP. */
16021 static int
16023 {
16034 }
16036 /* Return needed mode for entity in optimize_mode_switching pass. */
16038 static int
16040 {
16042 {
16043 rtx link;
16045 /* Needed mode is set to AVX_U128_CLEAN if there are
16046 no 256bit modes used in function arguments. */
16048 link;
16050 {
16052 {
16057 }
16058 }
16061 }
16063 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16064 changes state only when a 256bit register is written to, but we need
16065 to prevent the compiler from moving optimal insertion point above
16066 eventual read from 256bit register. */
16071 }
16073 /* Return mode that i387 must be switched into
16074 prior to the execution of insn. */
16076 static int
16078 {
16081 /* The mode UNINITIALIZED is used to store control word after a
16082 function call or ASM pattern. The mode ANY specify that function
16083 has no requirements on the control word and make no changes in the
16084 bits we are interested in. */
16098 {
16121 }
16124 }
16126 /* Return mode that entity must be switched into
16127 prior to the execution of insn. */
16129 int
16131 {
16133 {
16143 }
16145 }
16147 /* Check if a 256bit AVX register is referenced in stores. */
16149 static void
16151 {
16153 {
16156 }
16157 }
16159 /* Calculate mode of upper 128bit AVX registers after the insn. */
16161 static int
16163 {
16170 /* We know that state is clean after CALL insn if there are no
16171 256bit registers used in the function return register. */
16173 {
16178 }
16180 /* Otherwise, return current mode. Remember that if insn
16181 references AVX 256bit registers, the mode was already changed
16182 to DIRTY from MODE_NEEDED. */
16184 }
16186 /* Return the mode that an insn results in. */
16188 int
16190 {
16192 {
16202 }
16203 }
16205 static int
16207 {
16208 tree arg;
16210 /* Entry mode is set to AVX_U128_DIRTY if there are
16211 256bit modes used in function arguments. */
16214 {
16219 }
16222 }
16224 /* Return a mode that ENTITY is assumed to be
16225 switched to at function entry. */
16227 int
16229 {
16231 {
16241 }
16242 }
16244 static int
16246 {
16249 /* Exit mode is set to AVX_U128_DIRTY if there are
16250 256bit modes used in the function return register. */
16255 }
16257 /* Return a mode that ENTITY is assumed to be
16258 switched to at function exit. */
16260 int
16262 {
16264 {
16274 }
16275 }
16277 /* Output code to initialize control word copies used by trunc?f?i and
16278 rounding patterns. CURRENT_MODE is set to current control word,
16279 while NEW_MODE is set to new control word. */
16281 static void
16283 {
16285 rtx new_mode;
16296 {
16298 {
16300 /* round toward zero (truncate) */
16306 /* round down toward -oo */
16313 /* round up toward +oo */
16320 /* mask precision exception for nearbyint() */
16327 }
16328 }
16329 else
16330 {
16332 {
16334 /* round toward zero (truncate) */
16340 /* round down toward -oo */
16346 /* round up toward +oo */
16352 /* mask precision exception for nearbyint() */
16359 }
16360 }
16366 }
16368 /* Emit vzeroupper. */
16370 void
16372 {
16375 /* Cancel automatic vzeroupper insertion if there are
16376 live call-saved SSE registers at the insertion point. */
16388 }
16390 /* Generate one or more insns to set ENTITY to MODE. */
16392 void
16394 {
16396 {
16411 }
16412 }
16414 /* Output code for INSN to convert a float to a signed int. OPERANDS
16415 are the insn operands. The output may be [HSD]Imode and the input
16416 operand may be [SDX]Fmode. */
16420 {
16425 /* Jump through a hoop or two for DImode, since the hardware has no
16426 non-popping instruction. We used to do this a different way, but
16427 that was somewhat fragile and broke with post-reload splitters. */
16437 else
16438 {
16443 else
16447 }
16450 }
16452 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16453 have the values zero or one, indicates the ffreep insn's operand
16454 from the OPERANDS array. */
16458 {
16460 #ifdef HAVE_AS_IX86_FFREEP
16462 #else
16463 {
16473 }
16474 #endif
16477 }
16480 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16481 should be used. UNORDERED_P is true when fucom should be used. */
16485 {
16491 {
16494 }
16495 else
16496 {
16499 }
16502 {
16506 else
16508 else
16511 else
16513 }
16520 {
16522 {
16525 }
16526 else
16528 }
16531 && stack_top_dies
16534 {
16535 /* If both the top of the 387 stack dies, and the other operand
16536 is also a stack register that dies, then this must be a
16537 `fcompp' float compare */
16540 {
16541 /* There is no double popping fcomi variant. Fortunately,
16542 eflags is immune from the fstp's cc clobbering. */
16545 else
16548 }
16549 else
16550 {
16553 else
16555 }
16556 }
16557 else
16558 {
16559 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16562 {
16570 NULL,
16571 NULL,
16578 NULL,
16579 NULL,
16580 NULL,
16581 NULL
16582 };
16597 }
16598 }
16600 void
16602 {
16605 #ifdef ASM_QUAD
16608 #else
16610 #endif
16613 }
16615 void
16617 {
16620 #ifdef ASM_QUAD
16623 #else
16625 #endif
16626 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16632 #if TARGET_MACHO
16634 {
16638 }
16639 #endif
16640 else
16643 }
16644 \f
16645 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16646 for the target. */
16648 void
16650 {
16651 rtx tmp;
16653 /* We play register width games, which are only valid after reload. */
16656 /* Avoid HImode and its attendant prefix byte. */
16661 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16663 {
16666 }
16669 }
16671 /* X is an unchanging MEM. If it is a constant pool reference, return
16672 the constant pool rtx, else NULL. */
16674 rtx
16676 {
16683 }
16685 void
16687 {
16695 {
16696 rtx tmp;
16700 {
16706 }
16709 }
16713 {
16716 rtx tmp;
16721 else
16725 {
16732 }
16733 }
16737 {
16739 {
16740 #if TARGET_MACHO
16741 /* dynamic-no-pic */
16743 {
16744 rtx temp = ((reload_in_progress
16752 }
16754 {
16758 }
16761 else
16762 {
16770 }
16771 /* dynamic-no-pic */
16772 #endif
16773 }
16774 else
16775 {
16779 {
16785 }
16786 }
16787 }
16788 else
16789 {
16800 /* Force large constants in 64bit compilation into register
16801 to get them CSEed. */
16813 {
16814 /* If we are loading a floating point constant to a register,
16815 force the value to memory now, since we'll get better code
16816 out the back end. */
16820 {
16825 }
16826 }
16827 }
16830 }
16832 void
16834 {
16841 /* Force constants other than zero into memory. We do not know how
16842 the instructions used to build constants modify the upper 64 bits
16843 of the register, once we have that information we may be able
16844 to handle some of them more efficiently. */
16853 /* We need to check memory alignment for SSE mode since attribute
16854 can make operands unaligned. */
16859 {
16862 /* ix86_expand_vector_move_misalign() does not like constants ... */
16868 /* ... nor both arguments in memory. */
16876 }
16878 /* Make operand1 a register if it isn't already. */
16882 {
16885 }
16888 }
16890 /* Split 32-byte AVX unaligned load and store if needed. */
16892 static void
16894 {
16895 rtx m;
16902 {
16923 }
16926 {
16928 {
16935 }
16936 /* Normal *mov<mode>_internal pattern will handle
16937 unaligned loads just fine if misaligned_operand
16938 is true, and without the UNSPEC it can be combined
16939 with arithmetic instructions. */
16942 else
16944 }
16946 {
16948 {
16953 }
16954 else
16956 }
16957 else
16959 }
16961 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16962 straight to ix86_expand_vector_move. */
16963 /* Code generation for scalar reg-reg moves of single and double precision data:
16964 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16965 movaps reg, reg
16966 else
16967 movss reg, reg
16968 if (x86_sse_partial_reg_dependency == true)
16969 movapd reg, reg
16970 else
16971 movsd reg, reg
16973 Code generation for scalar loads of double precision data:
16974 if (x86_sse_split_regs == true)
16975 movlpd mem, reg (gas syntax)
16976 else
16977 movsd mem, reg
16979 Code generation for unaligned packed loads of single precision data
16980 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16981 if (x86_sse_unaligned_move_optimal)
16982 movups mem, reg
16984 if (x86_sse_partial_reg_dependency == true)
16985 {
16986 xorps reg, reg
16987 movlps mem, reg
16988 movhps mem+8, reg
16989 }
16990 else
16991 {
16992 movlps mem, reg
16993 movhps mem+8, reg
16994 }
16996 Code generation for unaligned packed loads of double precision data
16997 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16998 if (x86_sse_unaligned_move_optimal)
16999 movupd mem, reg
17001 if (x86_sse_split_regs == true)
17002 {
17003 movlpd mem, reg
17004 movhpd mem+8, reg
17005 }
17006 else
17007 {
17008 movsd mem, reg
17009 movhpd mem+8, reg
17010 }
17011 */
17013 void
17015 {
17024 {
17026 {
17030 {
17032 {
17035 }
17036 else
17038 }
17040 /* FALLTHRU */
17044 {
17059 }
17065 else
17073 }
17076 }
17080 {
17082 {
17086 {
17088 {
17091 }
17092 else
17094 }
17096 /* FALLTHRU */
17106 }
17109 }
17112 {
17113 /* Normal *mov<mode>_internal pattern will handle
17114 unaligned loads just fine if misaligned_operand
17115 is true, and without the UNSPEC it can be combined
17116 with arithmetic instructions. */
17122 /* ??? If we have typed data, then it would appear that using
17123 movdqu is the only way to get unaligned data loaded with
17124 integer type. */
17126 {
17128 {
17131 }
17133 /* We will eventually emit movups based on insn attributes. */
17137 }
17139 {
17140 rtx zero;
17143 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17144 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17146 {
17147 /* We will eventually emit movups based on insn attributes. */
17150 }
17152 /* When SSE registers are split into halves, we can avoid
17153 writing to the top half twice. */
17155 {
17158 }
17159 else
17160 {
17161 /* ??? Not sure about the best option for the Intel chips.
17162 The following would seem to satisfy; the register is
17163 entirely cleared, breaking the dependency chain. We
17164 then store to the upper half, with a dependency depth
17165 of one. A rumor has it that Intel recommends two movsd
17166 followed by an unpacklpd, but this is unconfirmed. And
17167 given that the dependency depth of the unpacklpd would
17168 still be one, I'm not sure why this would be better. */
17170 }
17176 }
17177 else
17178 {
17179 rtx t;
17182 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17183 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17185 {
17187 {
17190 }
17197 }
17201 else
17206 else
17215 }
17216 }
17218 {
17220 {
17223 /* We will eventually emit movups based on insn attributes. */
17225 }
17227 {
17229 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17230 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17232 /* We will eventually emit movups based on insn attributes. */
17234 else
17235 {
17240 }
17241 }
17242 else
17243 {
17248 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17249 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17251 {
17254 }
17255 else
17256 {
17261 }
17262 }
17263 }
17264 else
17266 }
17268 /* Helper function of ix86_fixup_binary_operands to canonicalize
17269 operand order. Returns true if the operands should be swapped. */
17271 static bool
17273 rtx operands[])
17274 {
17279 /* If the operation is not commutative, we can't do anything. */
17283 /* Highest priority is that src1 should match dst. */
17289 /* Next highest priority is that immediate constants come second. */
17295 /* Lowest priority is that memory references should come second. */
17302 }
17305 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17306 destination to use for the operation. If different from the true
17307 destination in operands[0], a copy operation will be required. */
17309 rtx
17311 rtx operands[])
17312 {
17317 /* Canonicalize operand order. */
17319 {
17320 rtx temp;
17322 /* It is invalid to swap operands of different modes. */
17328 }
17330 /* Both source operands cannot be in memory. */
17332 {
17333 /* Optimization: Only read from memory once. */
17335 {
17338 }
17341 else
17343 }
17345 /* If the destination is memory, and we do not have matching source
17346 operands, do things in registers. */
17350 /* Source 1 cannot be a constant. */
17354 /* Source 1 cannot be a non-matching memory. */
17358 /* Improve address combine. */
17367 }
17369 /* Similarly, but assume that the destination has already been
17370 set up properly. */
17372 void
17375 {
17378 }
17380 /* Attempt to expand a binary operator. Make the expansion closer to the
17381 actual machine, then just general_operand, which will allow 3 separate
17382 memory references (one output, two input) in a single insn. */
17384 void
17386 rtx operands[])
17387 {
17394 /* Emit the instruction. */
17398 {
17399 /* Reload doesn't know about the flags register, and doesn't know that
17400 it doesn't want to clobber it. We can only do this with PLUS. */
17403 }
17407 {
17408 /* This is going to be an LEA; avoid splitting it later. */
17410 }
17411 else
17412 {
17415 }
17417 /* Fix up the destination if needed. */
17420 }
17422 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17423 the given OPERANDS. */
17425 void
17427 rtx operands[])
17428 {
17431 {
17434 }
17436 {
17439 }
17440 /* Optimize (__m128i) d | (__m128i) e and similar code
17441 when d and e are float vectors into float vector logical
17442 insn. In C/C++ without using intrinsics there is no other way
17443 to express vector logical operation on float vectors than
17444 to cast them temporarily to integer vectors. */
17446 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17455 {
17456 rtx dst;
17458 {
17465 {
17468 }
17469 else
17470 {
17475 }
17486 }
17487 }
17496 }
17498 /* Return TRUE or FALSE depending on whether the binary operator meets the
17499 appropriate constraints. */
17501 bool
17504 {
17509 /* Both source operands cannot be in memory. */
17513 /* Canonicalize operand order for commutative operators. */
17515 {
17519 }
17521 /* If the destination is memory, we must have a matching source operand. */
17525 /* Source 1 cannot be a constant. */
17529 /* Source 1 cannot be a non-matching memory. */
17531 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17539 }
17541 /* Attempt to expand a unary operator. Make the expansion closer to the
17542 actual machine, then just general_operand, which will allow 2 separate
17543 memory references (one output, one input) in a single insn. */
17545 void
17547 rtx operands[])
17548 {
17555 /* If the destination is memory, and we do not have matching source
17556 operands, do things in registers. */
17559 {
17562 else
17564 }
17566 /* When source operand is memory, destination must match. */
17570 /* Emit the instruction. */
17574 {
17575 /* Reload doesn't know about the flags register, and doesn't know that
17576 it doesn't want to clobber it. */
17579 }
17580 else
17581 {
17584 }
17586 /* Fix up the destination if needed. */
17589 }
17591 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17592 divisor are within the range [0-255]. */
17594 void
17597 {
17606 {
17619 }
17626 /* Use 8bit unsigned divimod if dividend and divisor are within
17627 the range [0-255]. */
17636 pc_rtx);
17641 /* Generate original signed/unsigned divimod. */
17646 /* Branch to the end. */
17650 /* Generate 8bit unsigned divide. */
17652 /* Don't use operands[0] for result of 8bit divide since not all
17653 registers support QImode ZERO_EXTRACT. */
17660 {
17663 }
17664 else
17665 {
17668 }
17670 /* Extract remainder from AH. */
17674 else
17675 {
17676 /* Need a new scratch register since the old one has result
17677 of 8bit divide. */
17681 }
17684 /* Zero extend quotient from AL. */
17690 }
17692 /* Whether it is OK to emit CFI directives when emitting asm code. */
17694 bool
17696 {
17698 }
17700 #define LEA_MAX_STALL (3)
17701 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17703 /* Increase given DISTANCE in half-cycles according to
17704 dependencies between PREV and NEXT instructions.
17705 Add 1 half-cycle if there is no dependency and
17706 go to next cycle if there is some dependecy. */
17708 static unsigned int
17710 {
17727 }
17729 /* Function checks if instruction INSN defines register number
17730 REGNO1 or REGNO2. */
17732 static bool
17734 rtx insn)
17735 {
17743 {
17745 }
17748 }
17750 /* Function checks if instruction INSN uses register number
17751 REGNO as a part of address expression. */
17753 static bool
17755 {
17763 }
17765 /* Search backward for non-agu definition of register number REGNO1
17766 or register number REGNO2 in basic block starting from instruction
17767 START up to head of basic block or instruction INSN.
17769 Function puts true value into *FOUND var if definition was found
17770 and false otherwise.
17772 Distance in half-cycles between START and found instruction or head
17773 of BB is added to DISTANCE and returned. */
17775 static int
17779 {
17789 {
17791 {
17794 {
17797 {
17800 }
17801 }
17804 }
17809 }
17812 }
17814 /* Search backward for non-agu definition of register number REGNO1
17815 or register number REGNO2 in INSN's basic block until
17816 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17817 2. Reach neighbour BBs boundary, or
17818 3. Reach agu definition.
17819 Returns the distance between the non-agu definition point and INSN.
17820 If no definition point, returns -1. */
17822 static int
17824 rtx insn)
17825 {
17836 {
17837 edge e;
17838 edge_iterator ei;
17843 {
17846 }
17852 else
17853 {
17858 {
17859 int bb_dist
17865 {
17872 }
17873 }
17876 }
17877 }
17879 /* get_attr_type may modify recog data. We want to make sure
17880 that recog data is valid for instruction INSN, on which
17881 distance_non_agu_define is called. INSN is unchanged here. */
17888 }
17890 /* Return the distance in half-cycles between INSN and the next
17891 insn that uses register number REGNO in memory address added
17892 to DISTANCE. Return -1 if REGNO0 is set.
17894 Put true value into *FOUND if register usage was found and
17895 false otherwise.
17896 Put true value into *REDEFINED if register redefinition was
17897 found and false otherwise. */
17899 static int
17903 {
17912 {
17915 /* If insn and start belong to the same bb, set prev to insn,
17916 so the call to increase_distance will increase the distance
17917 between insns by 1. */
17919 }
17924 {
17926 {
17929 {
17930 /* Return DISTANCE if OP0 is used in memory
17931 address in NEXT. */
17934 }
17937 {
17938 /* Return -1 if OP0 is set in NEXT. */
17941 }
17944 }
17950 }
17953 }
17955 /* Return the distance between INSN and the next insn that uses
17956 register number REGNO0 in memory address. Return -1 if no such
17957 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17959 static int
17961 {
17973 {
17974 edge e;
17975 edge_iterator ei;
17980 {
17983 }
17989 else
17990 {
17996 {
17997 int bb_dist
18002 {
18009 }
18010 }
18013 }
18014 }
18020 }
18022 /* Define this macro to tune LEA priority vs ADD, it take effect when
18023 there is a dilemma of choicing LEA or ADD
18024 Negative value: ADD is more preferred than LEA
18025 Zero: Netrual
18026 Positive value: LEA is more preferred than ADD*/
18027 #define IX86_LEA_PRIORITY 0
18029 /* Return true if usage of lea INSN has performance advantage
18030 over a sequence of instructions. Instructions sequence has
18031 SPLIT_COST cycles higher latency than lea latency. */
18033 static bool
18036 {
18039 /* For Silvermont if using a 2-source or 3-source LEA for
18040 non-destructive destination purposes, or due to wanting
18041 ability to use SCALE, the use of LEA is justified. */
18043 {
18051 }
18057 {
18058 /* If there is no non AGU operand definition, no AGU
18059 operand usage and split cost is 0 then both lea
18060 and non lea variants have same priority. Currently
18061 we prefer lea for 64 bit code and non lea on 32 bit
18062 code. */
18065 else
18067 }
18069 /* With longer definitions distance lea is more preferable.
18070 Here we change it to take into account splitting cost and
18071 lea priority. */
18074 /* If there is no use in memory addess then we just check
18075 that split cost exceeds AGU stall. */
18079 /* If this insn has both backward non-agu dependence and forward
18080 agu dependence, the one with short distance takes effect. */
18082 }
18084 /* Return true if it is legal to clobber flags by INSN and
18085 false otherwise. */
18087 static bool
18089 {
18092 bitmap live;
18095 {
18097 {
18104 }
18110 }
18114 }
18116 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18117 move and add to avoid AGU stalls. */
18119 bool
18121 {
18124 /* Check if we need to optimize. */
18128 /* Check it is correct to split here. */
18136 /* We need to split only adds with non destructive
18137 destination operand. */
18140 else
18142 }
18144 /* Return true if we should emit lea instruction instead of mov
18145 instruction. */
18147 bool
18149 {
18152 /* Check if we need to optimize. */
18156 /* Use lea for reg to reg moves only. */
18164 }
18166 /* Return true if we need to split lea into a sequence of
18167 instructions to avoid AGU stalls. */
18169 bool
18171 {
18177 /* Check we need to optimize. */
18181 /* The "at least two components" test below might not catch simple
18182 move or zero extension insns if parts.base is non-NULL and parts.disp
18183 is const0_rtx as the only components in the address, e.g. if the
18184 register is %rbp or %r13. As this test is much cheaper and moves or
18185 zero extensions are the common case, do this check first. */
18191 /* Check if it is OK to split here. */
18198 /* There should be at least two components in the address. */
18203 /* We should not split into add if non legitimate pic
18204 operand is used as displacement. */
18219 /* Compute how many cycles we will add to execution time
18220 if split lea into a sequence of instructions. */
18222 {
18223 /* Have to use mov instruction if non desctructive
18224 destination form is used. */
18228 /* Have to add index to base if both exist. */
18232 /* Have to use shift and adds if scale is 2 or greater. */
18234 {
18239 else
18241 }
18243 /* Have to use add instruction with immediate if
18244 disp is non zero. */
18248 /* Subtract the price of lea. */
18250 }
18254 }
18256 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18257 matches destination. RTX includes clobber of FLAGS_REG. */
18259 static void
18262 {
18269 }
18271 /* Return true if regno1 def is nearest to the insn. */
18273 static bool
18275 {
18282 {
18284 {
18287 }
18293 }
18295 /* None of the regs is defined in the bb. */
18297 }
18299 /* Split lea instructions into a sequence of instructions
18300 which are executed on ALU to avoid AGU stalls.
18301 It is assumed that it is allowed to clobber flags register
18302 at lea position. */
18304 void
18306 {
18322 {
18325 }
18328 {
18331 }
18337 {
18338 /* Case r1 = r1 + ... */
18340 {
18341 /* If we have a case r1 = r1 + C * r2 then we
18342 should use multiplication which is very
18343 expensive. Assume cost model is wrong if we
18344 have such case here. */
18349 }
18350 else
18351 {
18352 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18356 /* Use shift for scaling. */
18365 }
18366 }
18368 {
18371 }
18372 else
18373 {
18375 {
18378 }
18380 {
18383 }
18384 else
18385 {
18390 else
18391 {
18392 rtx tmp1;
18394 /* Find better operand for SET instruction, depending
18395 on which definition is farther from the insn. */
18398 else
18408 }
18411 }
18415 }
18416 }
18418 /* Return true if it is ok to optimize an ADD operation to LEA
18419 operation to avoid flag register consumation. For most processors,
18420 ADD is faster than LEA. For the processors like BONNELL, if the
18421 destination register of LEA holds an actual address which will be
18422 used soon, LEA is better and otherwise ADD is better. */
18424 bool
18426 {
18431 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18439 }
18441 /* Return true if destination reg of SET_BODY is shift count of
18442 USE_BODY. */
18444 static bool
18446 {
18447 rtx set_dest;
18448 rtx shift_rtx;
18451 /* Retrieve destination of SET_BODY. */
18453 {
18462 use_body))
18467 }
18469 /* Retrieve shift count of USE_BODY. */
18471 {
18483 }
18491 {
18494 /* Return true if shift count is dest of SET_BODY. */
18496 {
18497 /* Add check since it can be invoked before register
18498 allocation in pre-reload schedule. */
18504 }
18505 }
18508 }
18510 /* Return true if destination reg of SET_INSN is shift count of
18511 USE_INSN. */
18513 bool
18515 {
18518 }
18520 /* Return TRUE or FALSE depending on whether the unary operator meets the
18521 appropriate constraints. */
18523 bool
18527 {
18528 /* If one of operands is memory, source and destination must match. */
18534 }
18536 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18537 are ok, keeping in mind the possible movddup alternative. */
18539 bool
18541 {
18547 }
18549 /* Post-reload splitter for converting an SF or DFmode value in an
18550 SSE register into an unsigned SImode. */
18552 void
18554 {
18565 /* Load up the value into the low element. We must ensure that the other
18566 elements are valid floats -- zero is the easiest such value. */
18568 {
18571 else
18573 }
18574 else
18575 {
18580 else
18582 }
18602 else
18607 }
18609 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18610 Expects the 64-bit DImode to be supplied in a pair of integral
18611 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18612 -mfpmath=sse, !optimize_size only. */
18614 void
18616 {
18620 rtx x;
18626 {
18629 }
18630 else
18631 {
18635 }
18643 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18646 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18647 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18648 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18649 (0x1.0p84 + double(fp_value_hi_xmm)).
18650 Note these exponents differ by 32. */
18654 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18655 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18664 /* Add the upper and lower DFmode values together. */
18667 else
18668 {
18672 }
18675 }
18677 /* Not used, but eases macroization of patterns. */
18678 void
18680 rtx input ATTRIBUTE_UNUSED)
18681 {
18683 }
18685 /* Convert an unsigned SImode value into a DFmode. Only currently used
18686 for SSE, but applicable anywhere. */
18688 void
18690 {
18691 REAL_VALUE_TYPE TWO31r;
18706 }
18708 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18709 32-bit mode; otherwise we have a direct convert instruction. */
18711 void
18713 {
18714 REAL_VALUE_TYPE TWO32r;
18732 }
18734 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18735 For x86_32, -mfpmath=sse, !optimize_size only. */
18736 void
18738 {
18739 REAL_VALUE_TYPE ONE16r;
18758 }
18760 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18761 a vector of unsigned ints VAL to vector of floats TARGET. */
18763 void
18765 {
18767 REAL_VALUE_TYPE TWO16r;
18774 else
18779 OPTAB_DIRECT);
18790 OPTAB_DIRECT);
18792 OPTAB_DIRECT);
18795 }
18797 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18798 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18799 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18800 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18802 rtx
18804 {
18805 REAL_VALUE_TYPE TWO31r;
18820 {
18826 }
18835 OPTAB_DIRECT);
18836 else
18837 {
18843 OPTAB_DIRECT);
18844 }
18847 }
18849 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18850 then replicate the value for all elements of the vector
18851 register. */
18853 rtx
18855 {
18857 rtvec v;
18861 {
18894 }
18895 }
18897 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18898 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18899 for an SSE register. If VECT is true, then replicate the mask for
18900 all elements of the vector register. If INVERT is true, then create
18901 a mask excluding the sign bit. */
18903 rtx
18905 {
18909 rtx v;
18910 rtx mask;
18912 /* Find the sign bit, sign extended to 2*HWI. */
18914 {
18938 else
18946 {
18949 }
18950 else
18951 {
18952 rtvec vec;
18958 {
18961 }
18962 else
18972 }
18977 }
18982 /* Force this value into the low part of a fp vector constant. */
18991 }
18993 /* Generate code for floating point ABS or NEG. */
18995 void
18997 rtx operands[])
18998 {
19009 {
19015 }
19017 /* NEG and ABS performed with SSE use bitwise mask operations.
19018 Create the appropriate mask now. */
19021 else
19031 {
19033 rtvec par;
19038 else
19039 {
19042 }
19044 }
19045 else
19047 }
19049 /* Expand a copysign operation. Special case operand 0 being a constant. */
19051 void
19053 {
19067 else
19071 {
19078 {
19081 else
19082 {
19086 }
19087 }
19097 else
19101 }
19102 else
19103 {
19113 else
19117 }
19118 }
19120 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19121 be a constant, and so has already been expanded into a vector constant. */
19123 void
19125 {
19141 {
19144 }
19145 }
19147 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19148 so we have to do two masks. */
19150 void
19152 {
19167 {
19168 /* Shouldn't happen often (it's useless, obviously), but when it does
19169 we'd generate incorrect code if we continue below. */
19172 }
19175 {
19186 }
19187 else
19188 {
19190 {
19192 }
19194 {
19198 }
19202 {
19205 }
19207 {
19212 }
19214 }
19218 }
19220 /* Return TRUE or FALSE depending on whether the first SET in INSN
19221 has source and destination with matching CC modes, and that the
19222 CC mode is at least as constrained as REQ_MODE. */
19224 bool
19226 {
19227 rtx set;
19238 {
19248 /* FALLTHRU */
19252 /* FALLTHRU */
19256 /* FALLTHRU */
19270 }
19273 }
19275 /* Generate insn patterns to do an integer compare of OPERANDS. */
19277 static rtx
19279 {
19286 /* This is very simple, but making the interface the same as in the
19287 FP case makes the rest of the code easier. */
19291 /* Return the test that should be put into the flags user, i.e.
19292 the bcc, scc, or cmov instruction. */
19294 }
19296 /* Figure out whether to use ordered or unordered fp comparisons.
19297 Return the appropriate mode to use. */
19299 enum machine_mode
19301 {
19302 /* ??? In order to make all comparisons reversible, we do all comparisons
19303 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19304 all forms trapping and nontrapping comparisons, we can make inequality
19305 comparisons trapping again, since it results in better code when using
19306 FCOM based compares. */
19308 }
19310 enum machine_mode
19312 {
19316 {
19319 }
19322 {
19323 /* Only zero flag is needed. */
19327 /* Codes needing carry flag. */
19330 /* Detect overflow checks. They need just the carry flag. */
19334 else
19339 /* Codes possibly doable only with sign flag when
19340 comparing against zero. */
19345 else
19346 /* For other cases Carry flag is not required. */
19348 /* Codes doable only with sign flag when comparing
19349 against zero, but we miss jump instruction for it
19350 so we need to use relational tests against overflow
19351 that thus needs to be zero. */
19356 else
19358 /* strcmp pattern do (use flags) and combine may ask us for proper
19359 mode. */
19364 }
19365 }
19367 /* Return the fixed registers used for condition codes. */
19369 static bool
19371 {
19375 }
19377 /* If two condition code modes are compatible, return a condition code
19378 mode which is compatible with both. Otherwise, return
19379 VOIDmode. */
19381 static enum machine_mode
19383 {
19400 {
19414 {
19428 }
19432 /* These are only compatible with themselves, which we already
19433 checked above. */
19435 }
19436 }
19439 /* Return a comparison we can do and that it is equivalent to
19440 swap_condition (code) apart possibly from orderedness.
19441 But, never change orderedness if TARGET_IEEE_FP, returning
19442 UNKNOWN in that case if necessary. */
19444 static enum rtx_code
19446 {
19448 {
19459 }
19460 }
19462 /* Return cost of comparison CODE using the best strategy for performance.
19463 All following functions do use number of instructions as a cost metrics.
19464 In future this should be tweaked to compute bytes for optimize_size and
19465 take into account performance of various instructions on various CPUs. */
19467 static int
19469 {
19472 /* The cost of code using bit-twiddling on %ah. */
19474 {
19497 }
19500 {
19507 }
19508 }
19510 /* Return strategy to use for floating-point. We assume that fcomi is always
19511 preferrable where available, since that is also true when looking at size
19512 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19514 enum ix86_fpcmp_strategy
19516 {
19517 /* Do fcomi/sahf based test when profitable. */
19526 }
19528 /* Swap, force into registers, or otherwise massage the two operands
19529 to a fp comparison. The operands are updated in place; the new
19530 comparison code is returned. */
19532 static enum rtx_code
19534 {
19540 /* All of the unordered compare instructions only work on registers.
19541 The same is true of the fcomi compare instructions. The XFmode
19542 compare instructions require registers except when comparing
19543 against zero or when converting operand 1 from fixed point to
19544 floating point. */
19553 {
19556 }
19557 else
19558 {
19559 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19560 things around if they appear profitable, otherwise force op0
19561 into a register. */
19567 {
19570 {
19571 rtx tmp;
19574 }
19575 }
19581 {
19586 {
19589 }
19590 else
19592 }
19593 }
19595 /* Try to rearrange the comparison to make it cheaper. */
19599 {
19600 rtx tmp;
19605 }
19610 }
19612 /* Convert comparison codes we use to represent FP comparison to integer
19613 code that will result in proper branch. Return UNKNOWN if no such code
19614 is available. */
19616 enum rtx_code
19618 {
19620 {
19643 }
19644 }
19646 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19648 static rtx
19650 {
19657 /* Do fcomi/sahf based test when profitable. */
19659 {
19664 tmp);
19672 tmp);
19681 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19688 /* In the unordered case, we have to check C2 for NaN's, which
19689 doesn't happen to work out to anything nice combination-wise.
19690 So do some bit twiddling on the value we've got in AH to come
19691 up with an appropriate set of condition codes. */
19695 {
19699 {
19702 }
19703 else
19704 {
19710 }
19715 {
19720 }
19721 else
19722 {
19725 }
19730 {
19733 }
19734 else
19735 {
19739 }
19744 {
19750 }
19751 else
19752 {
19755 }
19760 {
19765 }
19766 else
19767 {
19770 }
19775 {
19780 }
19781 else
19782 {
19785 }
19799 }
19804 }
19806 /* Return the test that should be put into the flags user, i.e.
19807 the bcc, scc, or cmov instruction. */
19810 const0_rtx);
19811 }
19813 static rtx
19815 {
19816 rtx ret;
19822 {
19825 }
19826 else
19830 }
19832 void
19834 {
19836 rtx tmp;
19839 {
19846 simple:
19850 pc_rtx);
19858 /* Expand DImode branch into multiple compare+branch. */
19859 {
19865 {
19868 }
19875 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19876 avoid two branches. This costs one extra insn, so disable when
19877 optimizing for size. */
19882 {
19900 }
19902 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19903 op1 is a constant and the low word is zero, then we can just
19904 examine the high word. Similarly for low word -1 and
19905 less-or-equal-than or greater-than. */
19909 {
19912 {
19915 }
19919 {
19922 }
19926 }
19928 /* Otherwise, we need two or three jumps. */
19937 {
19951 }
19953 /*
19954 * a < b =>
19955 * if (hi(a) < hi(b)) goto true;
19956 * if (hi(a) > hi(b)) goto false;
19957 * if (lo(a) < lo(b)) goto true;
19958 * false:
19959 */
19971 }
19976 }
19977 }
19979 /* Split branch based on floating point condition. */
19980 void
19983 {
19984 rtx condition;
19985 rtx i;
19988 {
19993 }
19996 tmp);
19998 /* Remove pushed operand from stack. */
20008 }
20010 void
20012 {
20013 rtx ret;
20020 }
20022 /* Expand comparison setting or clearing carry flag. Return true when
20023 successful and set pop for the operation. */
20024 static bool
20026 {
20030 /* Do not handle double-mode compares that go through special path. */
20035 {
20040 /* Shortcut: following common codes never translate
20041 into carry flag compares. */
20046 /* These comparisons require zero flag; swap operands so they won't. */
20049 {
20054 }
20056 /* Try to expand the comparison and verify that we end up with
20057 carry flag based comparison. This fails to be true only when
20058 we decide to expand comparison using arithmetic that is not
20059 too common scenario. */
20068 else
20077 }
20083 {
20088 /* Convert a==0 into (unsigned)a<1. */
20097 /* Convert a>b into b<a or a>=b-1. */
20101 {
20103 /* Bail out on overflow. We still can swap operands but that
20104 would force loading of the constant into register. */
20109 }
20110 else
20111 {
20116 }
20119 /* Convert a>=0 into (unsigned)a<0x80000000. */
20137 }
20138 /* Swapping operands may cause constant to appear as first operand. */
20140 {
20144 }
20148 }
20150 bool
20152 {
20176 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20177 HImode insns, we'd be swallowed in word prefix ops. */
20183 {
20187 HOST_WIDE_INT diff;
20190 /* Sign bit compares are better done using shifts than we do by using
20191 sbb. */
20194 {
20195 /* Detect overlap between destination and compare sources. */
20199 {
20200 rtx flags;
20209 {
20211 compare_code
20213 }
20215 /* To simplify rest of code, restrict to the GEU case. */
20217 {
20223 }
20224 else
20225 {
20228 reverse_condition_maybe_unordered
20230 else
20233 }
20242 else
20245 }
20246 else
20247 {
20250 else
20251 {
20256 }
20258 }
20261 {
20262 /*
20263 * cmpl op0,op1
20264 * sbbl dest,dest
20265 * [addl dest, ct]
20266 *
20267 * Size 5 - 8.
20268 */
20273 }
20275 {
20276 /*
20277 * cmpl op0,op1
20278 * sbbl dest,dest
20279 * orl $ct, dest
20280 *
20281 * Size 8.
20282 */
20286 }
20288 {
20289 /*
20290 * cmpl op0,op1
20291 * sbbl dest,dest
20292 * notl dest
20293 * [addl dest, cf]
20294 *
20295 * Size 8 - 11.
20296 */
20302 }
20303 else
20304 {
20305 /*
20306 * cmpl op0,op1
20307 * sbbl dest,dest
20308 * [notl dest]
20309 * andl cf - ct, dest
20310 * [addl dest, ct]
20311 *
20312 * Size 8 - 11.
20313 */
20316 {
20320 }
20330 }
20336 }
20339 {
20342 HOST_WIDE_INT tmp;
20347 {
20350 /* We may be reversing unordered compare to normal compare, that
20351 is not valid in general (we may convert non-trapping condition
20352 to trapping one), however on i386 we currently emit all
20353 comparisons unordered. */
20356 }
20357 else
20358 {
20361 }
20362 }
20367 {
20372 {
20377 }
20378 }
20380 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20384 {
20385 /* If lea code below could be used, only optimize
20386 if it results in a 2 insn sequence. */
20392 {
20393 /*
20394 * notl op1 (if necessary)
20395 * sarl $31, op1
20396 * orl cf, op1
20397 */
20399 {
20403 }
20414 }
20415 }
20423 {
20424 /*
20425 * xorl dest,dest
20426 * cmpl op1,op2
20427 * setcc dest
20428 * lea cf(dest*(ct-cf)),dest
20429 *
20430 * Size 14.
20431 *
20432 * This also catches the degenerate setcc-only case.
20433 */
20435 rtx tmp;
20441 /* On x86_64 the lea instruction operates on Pmode, so we need
20442 to get arithmetics done in proper mode to match. */
20445 else
20446 {
20447 rtx out1;
20450 nops++;
20452 {
20454 nops++;
20455 }
20456 }
20458 {
20460 nops++;
20461 }
20463 {
20466 else
20468 }
20473 }
20475 /*
20476 * General case: Jumpful:
20477 * xorl dest,dest cmpl op1, op2
20478 * cmpl op1, op2 movl ct, dest
20479 * setcc dest jcc 1f
20480 * decl dest movl cf, dest
20481 * andl (cf-ct),dest 1:
20482 * addl ct,dest
20483 *
20484 * Size 20. Size 14.
20485 *
20486 * This is reasonably steep, but branch mispredict costs are
20487 * high on modern cpus, so consider failing only if optimizing
20488 * for space.
20489 */
20494 {
20496 {
20503 {
20506 /* We may be reversing unordered compare to normal compare,
20507 that is not valid in general (we may convert non-trapping
20508 condition to trapping one), however on i386 we currently
20509 emit all comparisons unordered. */
20511 }
20512 else
20513 {
20517 }
20518 }
20521 {
20522 /* notl op1 (if needed)
20523 sarl $31, op1
20524 andl (cf-ct), op1
20525 addl ct, op1
20527 For x < 0 (resp. x <= -1) there will be no notl,
20528 so if possible swap the constants to get rid of the
20529 complement.
20530 True/false will be -1/0 while code below (store flag
20531 followed by decrement) is 0/-1, so the constants need
20532 to be exchanged once more. */
20535 {
20538 }
20539 else
20540 {
20544 }
20547 }
20548 else
20549 {
20553 constm1_rtx,
20555 }
20567 }
20568 }
20571 {
20572 /* Try a few things more with specific constants and a variable. */
20574 optab op;
20580 /* If one of the two operands is an interesting constant, load a
20581 constant with the above and mask it in with a logical operation. */
20584 {
20590 else
20592 }
20594 {
20600 else
20602 }
20603 else
20610 /* Recurse to get the constant loaded. */
20614 /* Mask in the interesting variable. */
20616 OPTAB_WIDEN);
20621 }
20623 /*
20624 * For comparison with above,
20625 *
20626 * movl cf,dest
20627 * movl ct,tmp
20628 * cmpl op1,op2
20629 * cmovcc tmp,dest
20630 *
20631 * Size 15.
20632 */
20654 }
20656 /* Swap, force into registers, or otherwise massage the two operands
20657 to an sse comparison with a mask result. Thus we differ a bit from
20658 ix86_prepare_fp_compare_args which expects to produce a flags result.
20660 The DEST operand exists to help determine whether to commute commutative
20661 operators. The POP0/POP1 operands are updated in place. The new
20662 comparison code is returned, or UNKNOWN if not implementable. */
20664 static enum rtx_code
20667 {
20668 rtx tmp;
20671 {
20674 /* AVX supports all the needed comparisons. */
20677 /* We have no LTGT as an operator. We could implement it with
20678 NE & ORDERED, but this requires an extra temporary. It's
20679 not clear that it's worth it. */
20686 /* These are supported directly. */
20693 /* AVX has 3 operand comparisons, no need to swap anything. */
20696 /* For commutative operators, try to canonicalize the destination
20697 operand to be first in the comparison - this helps reload to
20698 avoid extra moves. */
20701 /* FALLTHRU */
20707 /* These are not supported directly before AVX, and furthermore
20708 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20709 comparison operands to transform into something that is
20710 supported. */
20719 }
20722 }
20724 /* Detect conditional moves that exactly match min/max operational
20725 semantics. Note that this is IEEE safe, as long as we don't
20726 interchange the operands.
20728 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20729 and TRUE if the operation is successful and instructions are emitted. */
20731 static bool
20734 {
20737 rtx tmp;
20740 ;
20742 {
20746 }
20747 else
20754 else
20759 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20760 but MODE may be a vector mode and thus not appropriate. */
20762 {
20764 rtvec v;
20769 }
20770 else
20771 {
20774 }
20778 }
20780 /* Expand an sse vector comparison. Return the register with the result. */
20782 static rtx
20785 {
20789 /* In general case result of comparison can differ from operands' type. */
20792 /* In AVX512F the result of comparison is an integer mask. */
20794 rtx x;
20797 {
20802 }
20803 else
20816 /* Compare patterns for int modes are unspec in AVX512F only. */
20818 {
20822 {
20831 }
20834 {
20837 }
20838 }
20842 {
20845 }
20846 else
20850 }
20852 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20853 operations. This is used for both scalar and vector conditional moves. */
20855 static void
20857 {
20861 /* In AVX512F the result of comparison is an integer mask. */
20869 {
20871 }
20874 {
20878 }
20881 {
20886 }
20889 {
20893 }
20896 {
20904 op_true,
20905 op_false)));
20906 }
20907 else
20908 {
20918 {
20932 {
20939 }
20954 {
20961 }
20979 }
20982 {
20986 }
20987 else
20988 {
20994 else
21006 }
21007 }
21008 }
21010 /* Expand a floating-point conditional move. Return true if successful. */
21012 bool
21014 {
21022 {
21025 /* Since we've no cmove for sse registers, don't force bad register
21026 allocation just to gain access to it. Deny movcc when the
21027 comparison mode doesn't match the move mode. */
21046 }
21053 /* The floating point conditional move instructions don't directly
21054 support conditions resulting from a signed integer comparison. */
21058 {
21063 }
21070 }
21072 /* Expand a floating-point vector conditional move; a vcond operation
21073 rather than a movcc operation. */
21075 bool
21077 {
21079 rtx cmp;
21084 {
21085 rtx temp;
21087 {
21104 }
21106 OPTAB_DIRECT);
21109 }
21119 }
21121 /* Expand a signed/unsigned integral vector conditional move. */
21123 bool
21125 {
21135 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21136 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21145 {
21149 {
21155 }
21158 {
21164 }
21165 }
21174 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21178 ;
21179 else
21180 {
21181 /* Canonicalize the comparison to EQ, GT, GTU. */
21183 {
21200 /* FALLTHRU */
21210 }
21212 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21214 {
21216 {
21218 /* SSE4.1 supports EQ. */
21225 /* SSE4.2 supports GT/GTU. */
21232 }
21233 }
21235 /* Unsigned parallel compare is not supported by the hardware.
21236 Play some tricks to turn this into a signed comparison
21237 against 0. */
21239 {
21243 {
21250 {
21255 {
21264 }
21265 /* Subtract (-(INT MAX) - 1) from both operands to make
21266 them signed. */
21277 }
21284 /* Perform a parallel unsigned saturating subtraction. */
21297 }
21298 }
21299 }
21301 /* Allow the comparison to be done in one mode, but the movcc to
21302 happen in another mode. */
21304 {
21307 }
21308 else
21309 {
21315 }
21320 }
21322 static bool
21324 {
21327 {
21331 op1));
21336 op1));
21348 }
21349 }
21351 /* Expand a variable vector permutation. */
21353 void
21355 {
21366 /* Number of elements in the vector. */
21375 {
21377 {
21378 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21379 an constant shuffle operand. With a tiny bit of effort we can
21380 use VPERMD instead. A re-interpretation stall for V4DFmode is
21381 unfortunate but there's no avoiding it.
21382 Similarly for V16HImode we don't have instructions for variable
21383 shuffling, while for V32QImode we can use after preparing suitable
21384 masks vpshufb; vpshufb; vpermq; vpor. */
21387 {
21391 }
21392 else
21393 {
21397 }
21400 /* Replicate the low bits of the V4DImode mask into V8SImode:
21401 mask = { A B C D }
21402 t1 = { A A B B C C D D }. */
21410 else
21413 /* Multiply the shuffle indicies by two. */
21415 OPTAB_DIRECT);
21417 /* Add one to the odd shuffle indicies:
21418 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21420 {
21423 }
21427 OPTAB_DIRECT);
21429 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21434 }
21437 {
21439 /* The VPERMD and VPERMPS instructions already properly ignore
21440 the high bits of the shuffle elements. No need for us to
21441 perform an AND ourselves. */
21443 {
21448 }
21449 else
21450 {
21456 }
21463 else
21464 {
21470 }
21474 /* By combining the two 128-bit input vectors into one 256-bit
21475 input vector, we can use VPERMD and VPERMPS for the full
21476 two-operand shuffle. */
21508 /* From mask create two adjusted masks, which contain the same
21509 bits as mask in the low 7 bits of each vector element.
21510 The first mask will have the most significant bit clear
21511 if it requests element from the same 128-bit lane
21512 and MSB set if it requests element from the other 128-bit lane.
21513 The second mask will have the opposite values of the MSB,
21514 and additionally will have its 128-bit lanes swapped.
21515 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21516 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21517 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21518 stands for other 12 bytes. */
21519 /* The bit whether element is from the same lane or the other
21520 lane is bit 4, so shift it up by 3 to the MSB position. */
21524 /* Clear MSB bits from the mask just in case it had them set. */
21526 /* After this t1 will have MSB set for elements from other lane. */
21528 /* Clear bits other than MSB. */
21530 /* Or in the lower bits from mask into t3. */
21532 /* And invert MSB bits in t1, so MSB is set for elements from the same
21533 lane. */
21535 /* Swap 128-bit lanes in t3. */
21540 /* And or in the lower bits from mask into t1. */
21543 {
21544 /* Each of these shuffles will put 0s in places where
21545 element from the other 128-bit lane is needed, otherwise
21546 will shuffle in the requested value. */
21550 /* For t3 the 128-bit lanes are swapped again. */
21555 /* And oring both together leads to the result. */
21562 }
21565 /* Similarly to the above one_operand_shuffle code,
21566 just for repeated twice for each operand. merge_two:
21567 code will merge the two results together. */
21591 }
21592 }
21595 {
21596 /* The XOP VPPERM insn supports three inputs. By ignoring the
21597 one_operand_shuffle special case, we avoid creating another
21598 set of constant vectors in memory. */
21601 /* mask = mask & {2*w-1, ...} */
21603 }
21604 else
21605 {
21606 /* mask = mask & {w-1, ...} */
21608 }
21616 /* For non-QImode operations, convert the word permutation control
21617 into a byte permutation control. */
21619 {
21624 /* Convert mask to vector of chars. */
21627 /* Replicate each of the input bytes into byte positions:
21628 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21629 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21630 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21637 else
21640 /* Convert it into the byte positions by doing
21641 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21647 }
21649 /* The actual shuffle operations all operate on V16QImode. */
21654 {
21661 }
21663 {
21670 }
21671 else
21672 {
21676 /* Shuffle the two input vectors independently. */
21682 merge_two:
21683 /* Then merge them together. The key is whether any given control
21684 element contained a bit set that indicates the second word. */
21688 {
21689 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21690 more shuffle to convert the V2DI input mask into a V4SI
21691 input mask. At which point the masking that expand_int_vcond
21692 will work as desired. */
21700 }
21722 }
21723 }
21725 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21726 true if we should do zero extension, else sign extension. HIGH_P is
21727 true if we want the N/2 high elements, else the low elements. */
21729 void
21731 {
21733 rtx tmp;
21736 {
21742 {
21746 else
21749 extract
21755 else
21758 extract
21764 else
21767 extract
21773 else
21776 extract
21782 else
21785 extract
21791 else
21797 else
21803 else
21808 }
21811 {
21814 }
21816 {
21817 /* Shift higher 8 bytes to lower 8 bytes. */
21822 }
21823 else
21827 }
21828 else
21829 {
21833 {
21837 else
21843 else
21849 else
21854 }
21858 else
21865 }
21866 }
21868 /* Expand conditional increment or decrement using adb/sbb instructions.
21869 The default case using setcc followed by the conditional move can be
21870 done by generic code. */
21871 bool
21873 {
21875 rtx flags;
21877 rtx compare_op;
21895 {
21898 }
21901 {
21905 reverse_condition_maybe_unordered
21907 else
21909 }
21913 /* Construct either adc or sbb insn. */
21915 {
21917 {
21932 }
21933 }
21934 else
21935 {
21937 {
21952 }
21953 }
21957 }
21960 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21961 but works for floating pointer parameters and nonoffsetable memories.
21962 For pushes, it returns just stack offsets; the values will be saved
21963 in the right order. Maximally three parts are generated. */
21965 static int
21967 {
21972 else
21978 /* Optimize constant pool reference to immediates. This is used by fp
21979 moves, that force all constants to memory to allow combining. */
21981 {
21985 }
21988 {
21989 /* The only non-offsetable memories we handle are pushes. */
21998 }
22001 {
22003 /* Caution: if we looked through a constant pool memory above,
22004 the operand may actually have a different mode now. That's
22005 ok, since we want to pun this all the way back to an integer. */
22009 }
22012 {
22015 else
22016 {
22020 {
22024 }
22026 {
22031 }
22033 {
22034 REAL_VALUE_TYPE r;
22039 {
22046 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22047 long double may not be 80-bit. */
22056 }
22059 }
22060 else
22062 }
22063 }
22064 else
22065 {
22069 {
22072 {
22076 }
22078 {
22082 }
22084 {
22085 REAL_VALUE_TYPE r;
22091 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22094 = gen_int_mode
22097 DImode);
22098 else
22105 = gen_int_mode
22108 DImode);
22109 else
22111 }
22112 else
22114 }
22115 }
22118 }
22120 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22121 Return false when normal moves are needed; true when all required
22122 insns have been emitted. Operands 2-4 contain the input values
22123 int the correct order; operands 5-7 contain the output values. */
22125 void
22127 {
22135 /* The DFmode expanders may ask us to move double.
22136 For 64bit target this is single move. By hiding the fact
22137 here we simplify i386.md splitters. */
22139 {
22140 /* Optimize constant pool reference to immediates. This is used by
22141 fp moves, that force all constants to memory to allow combining. */
22148 {
22151 }
22152 else
22157 }
22159 /* The only non-offsettable memory we handle is push. */
22162 else
22169 /* When emitting push, take care for source operands on the stack. */
22172 {
22175 /* Compensate for the stack decrement by 4. */
22180 /* src_base refers to the stack pointer and is
22181 automatically decreased by emitted push. */
22185 }
22187 /* We need to do copy in the right order in case an address register
22188 of the source overlaps the destination. */
22190 {
22191 rtx tmp;
22194 {
22198 collisions++;
22199 }
22201 /* Collision in the middle part can be handled by reordering. */
22203 {
22206 }
22210 {
22212 {
22215 }
22216 else
22217 {
22220 }
22221 }
22223 /* If there are more collisions, we can't handle it by reordering.
22224 Do an lea to the last part and use only one colliding move. */
22226 {
22227 rtx base;
22233 /* Handle the case when the last part isn't valid for lea.
22234 Happens in 64-bit mode storing the 12-byte XFmode. */
22241 {
22244 }
22245 }
22246 }
22249 {
22251 {
22253 {
22258 }
22260 {
22263 }
22264 }
22265 else
22266 {
22267 /* In 64bit mode we don't have 32bit push available. In case this is
22268 register, it is OK - we will just use larger counterpart. We also
22269 retype memory - these comes from attempt to avoid REX prefix on
22270 moving of second half of TFmode value. */
22272 {
22274 {
22285 }
22289 }
22290 }
22294 }
22296 /* Choose correct order to not overwrite the source before it is copied. */
22306 {
22308 {
22311 }
22312 }
22313 else
22314 {
22316 {
22319 }
22320 }
22322 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22324 {
22333 }
22339 }
22341 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22342 left shift by a constant, either using a single shift or
22343 a sequence of add instructions. */
22345 static void
22347 {
22353 {
22357 }
22358 else
22359 {
22362 }
22363 }
22365 void
22367 {
22376 {
22381 {
22387 }
22388 else
22389 {
22397 }
22399 }
22406 {
22407 /* Assuming we've chosen a QImode capable registers, then 1 << N
22408 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22410 {
22426 }
22428 /* Otherwise, we can get the same results by manually performing
22429 a bit extract operation on bit 5/6, and then performing the two
22430 shifts. The two methods of getting 0/1 into low/high are exactly
22431 the same size. Avoiding the shift in the bit extract case helps
22432 pentium4 a bit; no one else seems to care much either way. */
22433 else
22434 {
22439 HOST_WIDE_INT bits;
22440 rtx x;
22443 {
22449 }
22450 else
22451 {
22457 }
22461 else
22469 }
22474 }
22477 {
22478 /* For -1 << N, we can avoid the shld instruction, because we
22479 know that we're shifting 0...31/63 ones into a -1. */
22483 else
22485 }
22486 else
22487 {
22495 }
22500 {
22506 }
22507 else
22508 {
22513 }
22514 }
22516 void
22518 {
22528 {
22533 {
22539 }
22541 {
22550 }
22551 else
22552 {
22560 }
22561 }
22562 else
22563 {
22575 {
22583 scratch));
22584 }
22585 else
22586 {
22591 }
22592 }
22593 }
22595 void
22597 {
22607 {
22612 {
22619 }
22620 else
22621 {
22629 }
22630 }
22631 else
22632 {
22644 {
22650 scratch));
22651 }
22652 else
22653 {
22658 }
22659 }
22660 }
22662 /* Predict just emitted jump instruction to be taken with probability PROB. */
22663 static void
22665 {
22669 }
22671 /* Helper function for the string operations below. Dest VARIABLE whether
22672 it is aligned to VALUE bytes. If true, jump to the label. */
22673 static rtx
22675 {
22680 else
22686 else
22689 }
22691 /* Adjust COUNTER by the VALUE. */
22692 static void
22694 {
22699 }
22701 /* Zero extend possibly SImode EXP to Pmode register. */
22702 rtx
22704 {
22706 }
22708 /* Divide COUNTREG by SCALE. */
22709 static rtx
22711 {
22712 rtx sc;
22724 }
22726 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22727 DImode for constant loop counts. */
22729 static enum machine_mode
22731 {
22739 }
22741 /* Copy the address to a Pmode register. This is used for x32 to
22742 truncate DImode TLS address to a SImode register. */
22744 static rtx
22746 {
22749 else
22750 {
22753 }
22754 }
22756 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22757 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22758 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22759 memory by VALUE (supposed to be in MODE).
22761 The size is rounded down to whole number of chunk size moved at once.
22762 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22765 static void
22770 {
22776 rtx size;
22785 /* Those two should combine. */
22787 {
22791 }
22798 /* This assert could be relaxed - in this case we'll need to compute
22799 smallest power of two, containing in PIECE_SIZE_N and pass it to
22800 offset_address. */
22806 {
22810 /* When unrolling for chips that reorder memory reads and writes,
22811 we can save registers by using single temporary.
22812 Also using 4 temporaries is overkill in 32bit mode. */
22814 {
22816 {
22818 {
22819 destmem =
22821 srcmem =
22823 }
22825 }
22826 }
22827 else
22828 {
22832 {
22835 {
22836 srcmem =
22838 }
22840 }
22842 {
22844 {
22845 destmem =
22847 }
22849 }
22850 }
22851 }
22852 else
22854 {
22856 destmem =
22859 }
22869 {
22875 else
22877 }
22878 else
22886 {
22891 }
22893 }
22895 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22896 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22897 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22898 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22899 ORIG_VALUE is the original value passed to memset to fill the memory with.
22900 Other arguments have same meaning as for previous function. */
22902 static void
22905 rtx count,
22907 {
22908 rtx destexp;
22909 rtx srcexp;
22910 rtx countreg;
22911 HOST_WIDE_INT rounded_count;
22913 /* If possible, it is shorter to use rep movs.
22914 TODO: Maybe it is better to move this logic to decide_alg. */
22925 {
22929 }
22930 else
22933 {
22938 }
22943 {
22946 }
22947 else
22948 {
22952 {
22956 }
22957 else
22960 {
22965 }
22966 else
22967 {
22970 }
22973 }
22974 }
22976 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
22977 DESTMEM.
22978 SRC is passed by pointer to be updated on return.
22979 Return value is updated DST. */
22980 static rtx
22982 HOST_WIDE_INT size_to_move)
22983 {
22989 /* Find the widest mode in which we could perform moves.
22990 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
22991 it until move of such size is supported. */
22996 {
23000 }
23002 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23003 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23005 {
23010 {
23014 }
23015 }
23021 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23025 {
23026 /* We move from memory to memory, so we'll need to do it via
23027 a temporary register. */
23038 piece_size);
23040 piece_size);
23041 }
23043 /* Update DST and SRC rtx. */
23046 }
23048 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23049 static void
23052 {
23055 {
23060 /* For now MAX_SIZE should be a power of 2. This assert could be
23061 relaxed, but it'll require a bit more complicated epilogue
23062 expanding. */
23065 {
23068 }
23070 }
23072 {
23078 }
23080 /* When there are stringops, we can cheaply increase dest and src pointers.
23081 Otherwise we save code size by maintaining offset (zero is readily
23082 available from preceding rep operation) and using x86 addressing modes.
23083 */
23085 {
23087 {
23094 }
23096 {
23103 }
23105 {
23112 }
23113 }
23114 else
23115 {
23117 rtx tmp;
23120 {
23131 }
23133 {
23146 }
23148 {
23157 }
23158 }
23159 }
23161 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23162 with value PROMOTED_VAL.
23163 SRC is passed by pointer to be updated on return.
23164 Return value is updated DST. */
23165 static rtx
23167 HOST_WIDE_INT size_to_move)
23168 {
23174 /* Find the widest mode in which we could perform moves.
23175 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23176 it until move of such size is supported. */
23181 {
23184 }
23191 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23195 {
23197 {
23200 piece_size);
23202 }
23210 piece_size);
23211 }
23213 /* Update DST rtx. */
23215 }
23216 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23217 static void
23220 {
23221 count =
23227 }
23229 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23230 static void
23233 {
23234 rtx dest;
23237 {
23242 /* For now MAX_SIZE should be a power of 2. This assert could be
23243 relaxed, but it'll require a bit more complicated epilogue
23244 expanding. */
23247 {
23249 {
23252 else
23254 }
23255 }
23257 }
23259 {
23262 }
23264 {
23267 {
23272 }
23273 else
23274 {
23283 }
23286 }
23288 {
23291 {
23294 }
23295 else
23296 {
23301 }
23304 }
23306 {
23312 }
23314 {
23320 }
23322 {
23328 }
23329 }
23331 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23332 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23333 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23334 ignored.
23335 Return value is updated DESTMEM. */
23336 static rtx
23341 {
23344 {
23346 {
23349 {
23352 else
23354 }
23355 else
23361 }
23362 }
23364 }
23366 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23367 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23368 and jump to DONE_LABEL. */
23369 static void
23375 {
23378 rtx modesize;
23381 /* If we do not have vector value to copy, we must reduce size. */
23383 {
23385 {
23390 }
23391 else
23393 }
23394 else
23395 {
23396 /* Choose appropriate vector mode. */
23402 }
23407 {
23410 else
23411 {
23414 }
23416 }
23422 {
23426 }
23428 {
23431 else
23432 {
23435 }
23437 }
23443 }
23445 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23446 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23447 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23448 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23449 DONE_LABEL is a label after the whole copying sequence. The label is created
23450 on demand if *DONE_LABEL is NULL.
23451 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23452 bounds after the initial copies.
23454 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23455 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23456 we will dispatch to a library call for large blocks.
23458 In pseudocode we do:
23460 if (COUNT < SIZE)
23461 {
23462 Assume that SIZE is 4. Bigger sizes are handled analogously
23463 if (COUNT & 4)
23464 {
23465 copy 4 bytes from SRCPTR to DESTPTR
23466 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23467 goto done_label
23468 }
23469 if (!COUNT)
23470 goto done_label;
23471 copy 1 byte from SRCPTR to DESTPTR
23472 if (COUNT & 2)
23473 {
23474 copy 2 bytes from SRCPTR to DESTPTR
23475 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23476 }
23477 }
23478 else
23479 {
23480 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23481 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23483 OLD_DESPTR = DESTPTR;
23484 Align DESTPTR up to DESIRED_ALIGN
23485 SRCPTR += DESTPTR - OLD_DESTPTR
23486 COUNT -= DEST_PTR - OLD_DESTPTR
23487 if (DYNAMIC_CHECK)
23488 Round COUNT down to multiple of SIZE
23489 << optional caller supplied zero size guard is here >>
23490 << optional caller suppplied dynamic check is here >>
23491 << caller supplied main copy loop is here >>
23492 }
23493 done_label:
23494 */
23495 static void
23508 {
23511 rtx modesize;
23513 rtx mode_value;
23515 /* Chose proper value to copy. */
23518 else
23522 /* See if block is big or small, handle small blocks. */
23524 {
23535 /* Handle sizes > 3. */
23542 /* Nothing to copy? Jump to DONE_LABEL if so */
23546 /* Do a byte copy. */
23550 else
23551 {
23554 }
23556 /* Handle sizes 2 and 3. */
23563 else
23564 {
23569 }
23575 }
23576 else
23580 /* Start memcpy for COUNT >= SIZE. */
23582 {
23585 }
23587 /* Copy first desired_align bytes. */
23593 {
23596 else
23597 {
23600 }
23603 }
23606 /* Copy last SIZE bytes. */
23613 else
23614 {
23620 }
23622 {
23626 else
23627 {
23630 }
23631 }
23633 /* Align destination. */
23635 {
23639 /* Align destptr up, place it to new register. */
23646 /* See how many bytes we skipped. */
23650 /* Adjust srcptr and count. */
23656 /* We copied at most size + prolog_size. */
23659 else
23662 /* Our loops always round down the bock size, but for dispatch to library
23663 we need precise value. */
23667 }
23668 else
23669 {
23671 /* Decrease count, so we won't end up copying last word twice. */
23675 else
23679 }
23680 }
23683 /* This function is like the previous one, except here we know how many bytes
23684 need to be copied. That allows us to update alignment not only of DST, which
23685 is returned, but also of SRC, which is passed as a pointer for that
23686 reason. */
23687 static rtx
23692 {
23700 {
23704 }
23709 {
23711 {
23713 {
23716 else
23718 }
23719 else
23722 }
23723 }
23730 {
23736 {
23739 {
23743 }
23748 }
23752 }
23755 }
23757 /* Return true if ALG can be used in current context.
23758 Assume we expand memset if MEMSET is true. */
23759 static bool
23761 {
23766 /* Algorithms using the rep prefix want at least edi and ecx;
23767 additionally, memset wants eax and memcpy wants esi. Don't
23768 consider such algorithms if the user has appropriated those
23769 registers for their own purposes. */
23776 }
23778 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23779 static enum stringop_alg
23783 {
23794 /* Even if the string operation call is cold, we still might spend a lot
23795 of time processing large blocks. */
23801 else
23807 else
23810 /* See maximal size for user defined algorithm. */
23812 {
23819 }
23821 /* If expected size is not known but max size is small enough
23822 so inline version is a win, set expected size into
23823 the range. */
23828 /* If user specified the algorithm, honnor it if possible. */
23832 /* rep; movq or rep; movl is the smallest variant. */
23834 {
23839 else
23842 }
23843 /* Very tiny blocks are best handled via the loop, REP is expensive to
23844 setup. */
23848 {
23852 {
23853 /* We get here if the algorithms that were not libcall-based
23854 were rep-prefix based and we are unable to use rep prefixes
23855 based on global register usage. Break out of the loop and
23856 use the heuristic below. */
23860 {
23864 {
23867 }
23868 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23869 last non-libcall inline algorithm. */
23871 {
23872 /* When the current size is best to be copied by a libcall,
23873 but we are still forced to inline, run the heuristic below
23874 that will pick code for medium sized blocks. */
23876 {
23879 }
23881 }
23883 {
23886 }
23887 }
23888 }
23889 }
23890 /* When asked to inline the call anyway, try to pick meaningful choice.
23891 We look for maximal size of block that is faster to copy by hand and
23892 take blocks of at most of that size guessing that average size will
23893 be roughly half of the block.
23895 If this turns out to be bad, we might simply specify the preferred
23896 choice in ix86_costs. */
23900 {
23903 /* If there aren't any usable algorithms, then recursing on
23904 smaller sizes isn't going to find anything. Just return the
23905 simple byte-at-a-time copy loop. */
23907 {
23908 /* Pick something reasonable. */
23912 }
23922 }
23925 }
23927 /* Decide on alignment. We know that the operand is already aligned to ALIGN
23928 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
23929 static int
23934 {
23945 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
23946 copying whole cacheline at once. */
23959 }
23962 /* Helper function for memcpy. For QImode value 0xXY produce
23963 0xXYXYXYXY of wide specified by MODE. This is essentially
23964 a * 0x10101010, but we can do slightly better than
23965 synth_mult by unwinding the sequence by hand on CPUs with
23966 slow multiply. */
23967 static rtx
23969 {
23971 rtx tmp;
23978 {
23986 }
23995 nops--;
24000 {
24004 OPTAB_DIRECT);
24005 }
24006 else
24007 {
24013 else
24015 else
24016 {
24019 reg =
24021 }
24031 }
24032 }
24034 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24035 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24036 alignment from ALIGN to DESIRED_ALIGN. */
24037 static rtx
24040 {
24041 rtx promoted_val;
24050 else
24054 }
24056 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24057 operations when profitable. The code depends upon architecture, block size
24058 and alignment, but always has one of the following overall structures:
24060 Aligned move sequence:
24062 1) Prologue guard: Conditional that jumps up to epilogues for small
24063 blocks that can be handled by epilogue alone. This is faster
24064 but also needed for correctness, since prologue assume the block
24065 is larger than the desired alignment.
24067 Optional dynamic check for size and libcall for large
24068 blocks is emitted here too, with -minline-stringops-dynamically.
24070 2) Prologue: copy first few bytes in order to get destination
24071 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24072 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24073 copied. We emit either a jump tree on power of two sized
24074 blocks, or a byte loop.
24076 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24077 with specified algorithm.
24079 4) Epilogue: code copying tail of the block that is too small to be
24080 handled by main body (or up to size guarded by prologue guard).
24082 Misaligned move sequence
24084 1) missaligned move prologue/epilogue containing:
24085 a) Prologue handling small memory blocks and jumping to done_label
24086 (skipped if blocks are known to be large enough)
24087 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24088 needed by single possibly misaligned move
24089 (skipped if alignment is not needed)
24090 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24092 2) Zero size guard dispatching to done_label, if needed
24094 3) dispatch to library call, if needed,
24096 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24097 with specified algorithm. */
24098 bool
24104 {
24105 rtx destreg;
24108 rtx tmp;
24124 /* TODO: Once value ranges are available, fill in proper data. */
24132 /* i386 can do misaligned access on reasonably increased cost. */
24136 /* ALIGN is the minimum of destination and source alignment, but we care here
24137 just about destination alignment. */
24145 else
24146 {
24155 }
24157 /* Make sure we don't need to care about overflow later on. */
24161 /* Step 0: Decide on preferred algorithm, desired alignment and
24162 size of chunks to be copied by main loop. */
24164 issetmem,
24171 /* For now vector-version of memset is generated only for memory zeroing, as
24172 creating of promoted vector value is very cheap in this case. */
24185 {
24204 /* Find the widest supported mode. */
24210 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24211 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24213 {
24218 }
24230 }
24238 /* Step 1: Prologue guard. */
24240 /* Alignment code needs count to be in register. */
24242 {
24245 {
24246 align_bytes
24250 else
24252 }
24255 }
24258 /* Misaligned move sequences handle both prologue and epilogue at once.
24259 Default code generation results in a smaller code for large alignments
24260 and also avoids redundant job when sizes are known precisely. */
24261 misaligned_prologue_used
24262 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24268 /* Do the cheap promotion to allow better CSE across the
24269 main loop and epilogue (ie one load of the big constant in the
24270 front of all code.
24271 For now the misaligned move sequences do not have fast path
24272 without broadcasting. */
24274 {
24276 {
24282 }
24283 else
24284 {
24287 }
24288 }
24289 /* Misaligned move sequences handles both prologues and epilogues at once.
24290 Default code generation results in smaller code for large alignments and
24291 also avoids redundant job when sizes are known precisely. */
24293 {
24294 /* Misaligned move prologue handled small blocks by itself. */
24295 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24300 desired_align < align
24309 {
24310 /* It is possible that we copied enough so the main loop will not
24311 execute. */
24321 else
24323 }
24324 }
24325 /* Ensure that alignment prologue won't copy past end of block. */
24327 {
24329 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24330 Make sure it is power of 2. */
24333 /* To improve performance of small blocks, we jump around the VAL
24334 promoting mode. This mean that if the promoted VAL is not constant,
24335 we might not use it in the epilogue and have to use byte
24336 loop variant. */
24341 {
24342 /* If main algorithm works on QImode, no epilogue is needed.
24343 For small sizes just don't align anything. */
24346 else
24348 }
24351 {
24358 else
24360 }
24361 }
24363 /* Emit code to decide on runtime whether library call or inline should be
24364 used. */
24366 {
24368 {
24370 {
24374 }
24375 }
24376 else
24377 {
24386 else
24390 }
24391 }
24393 /* Step 2: Alignment prologue. */
24394 /* Do the expensive promotion once we branched off the small blocks. */
24400 {
24402 {
24403 /* Except for the first move in prologue, we no longer know
24404 constant offset in aliasing info. It don't seems to worth
24405 the pain to maintain it for the first move, so throw away
24406 the info early. */
24413 issetmem);
24414 /* At most desired_align - align bytes are copied. */
24417 else
24419 }
24420 else
24421 {
24422 /* If we know how many bytes need to be stored before dst is
24423 sufficiently aligned, maintain aliasing info accurately. */
24425 srcreg,
24426 promoted_val,
24427 vec_promoted_val,
24428 desired_align,
24429 align_bytes,
24430 issetmem);
24437 }
24439 && !min_size
24444 {
24445 /* It is possible that we copied enough so the main loop will not
24446 execute. */
24456 else
24458 }
24459 }
24461 {
24468 }
24472 /* Step 3: Main loop. */
24475 {
24498 }
24499 /* Adjust properly the offset of src and dest memory for aliasing. */
24501 {
24507 }
24508 else
24509 {
24513 }
24515 /* Step 4: Epilogue to copy the remaining bytes. */
24516 epilogue:
24518 {
24519 /* When the main loop is done, COUNT_EXP might hold original count,
24520 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24521 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24522 bytes. Compensate if needed. */
24525 {
24526 tmp =
24529 OPTAB_DIRECT);
24532 }
24535 }
24538 {
24541 epilogue_size_needed);
24542 else
24543 {
24547 epilogue_size_needed);
24548 else
24550 epilogue_size_needed);
24551 }
24552 }
24556 }
24559 /* Expand the appropriate insns for doing strlen if not just doing
24560 repnz; scasb
24562 out = result, initialized with the start address
24563 align_rtx = alignment of the address.
24564 scratch = scratch register, initialized with the startaddress when
24565 not aligned, otherwise undefined
24567 This is just the body. It needs the initializations mentioned above and
24568 some address computing at the end. These things are done in i386.md. */
24570 static void
24572 {
24574 rtx tmp;
24579 rtx mem;
24582 rtx cmp;
24588 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24590 /* Is there a known alignment and is it less than 4? */
24592 {
24595 /* Is there a known alignment and is it not 2? */
24597 {
24601 /* Leave just the 3 lower bits. */
24611 }
24612 else
24613 {
24614 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24615 check if is aligned to 4 - byte. */
24622 }
24626 /* Now compare the bytes. */
24628 /* Compare the first n unaligned byte on a byte per byte basis. */
24632 /* Increment the address. */
24635 /* Not needed with an alignment of 2 */
24637 {
24641 end_0_label);
24646 }
24649 end_0_label);
24652 }
24654 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24655 align this loop. It gives only huge programs, but does not help to
24656 speed up. */
24663 /* This formula yields a nonzero result iff one of the bytes is zero.
24664 This saves three branches inside loop and many cycles. */
24672 align_4_label);
24675 {
24681 /* If zero is not in the first two bytes, move two bytes forward. */
24687 reg,
24688 tmpreg)));
24689 /* Emit lea manually to avoid clobbering of flags. */
24697 reg2,
24698 out)));
24699 }
24700 else
24701 {
24703 /* Is zero in the first two bytes? */
24710 pc_rtx);
24714 /* Not in the first two. Move two bytes forward. */
24720 }
24722 /* Avoid branch in fixing the byte. */
24730 }
24732 /* Expand strlen. */
24734 bool
24736 {
24739 /* The generic case of strlen expander is long. Avoid it's
24740 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24743 && !TARGET_INLINE_ALL_STRINGOPS
24753 {
24754 /* Well it seems that some optimizer does not combine a call like
24755 foo(strlen(bar), strlen(bar));
24756 when the move and the subtraction is done here. It does calculate
24757 the length just once when these instructions are done inside of
24758 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24759 often used and I use one fewer register for the lifetime of
24760 output_strlen_unroll() this is better. */
24766 /* strlensi_unroll_1 returns the address of the zero at the end of
24767 the string, like memchr(), so compute the length by subtracting
24768 the start address. */
24770 }
24771 else
24772 {
24773 rtx unspec;
24775 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24788 /* If .md starts supporting :P, this can be done in .md. */
24794 }
24796 }
24798 /* For given symbol (function) construct code to compute address of it's PLT
24799 entry in large x86-64 PIC model. */
24800 static rtx
24802 {
24815 }
24817 rtx
24819 rtx callarg2,
24821 {
24822 unsigned int const cregs_size
24833 {
24834 #if TARGET_MACHO
24837 #endif
24838 }
24839 else
24840 {
24841 /* Static functions and indirect calls don't need the pic register. */
24843 && (!TARGET_64BIT
24849 }
24852 {
24856 }
24859 && !TARGET_PECOFF
24867 {
24870 }
24878 {
24882 }
24886 {
24890 UNSPEC_MS_TO_SYSV_CALL);
24893 {
24899 }
24900 }
24909 }
24911 /* Output the assembly for a call instruction. */
24915 {
24921 {
24924 /* SEH epilogue detection requires the indirect branch case
24925 to include REX.W. */
24928 else
24933 }
24935 /* SEH unwinding can require an extra nop to be emitted in several
24936 circumstances. Determine if we have one of those. */
24938 {
24939 rtx i;
24942 {
24943 /* If we get to another real insn, we don't need the nop. */
24947 /* If we get to the epilogue note, prevent a catch region from
24948 being adjacent to the standard epilogue sequence. If non-
24949 call-exceptions, we'll have done this during epilogue emission. */
24951 && !flag_non_call_exceptions
24953 {
24956 }
24957 }
24959 /* If we didn't find a real insn following the call, prevent the
24960 unwinder from looking into the next function. */
24963 }
24967 else
24976 }
24977 \f
24978 /* Clear stack slot assignments remembered from previous functions.
24979 This is called from INIT_EXPANDERS once before RTL is emitted for each
24980 function. */
24984 {
24992 }
24994 /* Return a MEM corresponding to a stack slot with mode MODE.
24995 Allocate a new slot if necessary.
24997 The RTL for a function can have several slots available: N is
24998 which slot to use. */
25000 rtx
25002 {
25019 }
25021 static void
25023 {
25029 }
25030 \f
25031 /* Check whether x86 address PARTS is a pc-relative address. */
25033 static bool
25035 {
25043 {
25045 {
25062 }
25063 }
25065 }
25067 /* Calculate the length of the memory address in the instruction encoding.
25068 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25069 or other prefixes. We never generate addr32 prefix for LEA insn. */
25071 int
25073 {
25090 /* If this is not LEA instruction, add the length of addr32 prefix. */
25095 len++;
25109 /* Rule of thumb:
25110 - esp as the base always wants an index,
25111 - ebp as the base always wants a displacement,
25112 - r12 as the base always wants an index,
25113 - r13 as the base always wants a displacement. */
25115 /* Register Indirect. */
25117 {
25118 /* esp (for its index) and ebp (for its displacement) need
25119 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25120 code. */
25127 len++;
25128 }
25130 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25131 is not disp32, but disp32(%rip), so for disp32
25132 SIB byte is needed, unless print_operand_address
25133 optimizes it into disp32(%rip) or (%rip) is implied
25134 by UNSPEC. */
25136 {
25139 len++;
25140 }
25141 else
25142 {
25143 /* Find the length of the displacement constant. */
25145 {
25148 else
25150 }
25151 /* ebp always wants a displacement. Similarly r13. */
25153 len++;
25155 /* An index requires the two-byte modrm form.... */
25157 /* ...like esp (or r12), which always wants an index. */
25161 len++;
25162 }
25165 }
25167 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25168 is set, expect that insn have 8bit immediate alternative. */
25169 int
25171 {
25177 {
25182 {
25185 {
25197 }
25199 {
25202 }
25203 }
25205 {
25215 /* Immediates for DImode instructions are encoded
25216 as 32bit sign extended values. */
25222 }
25223 }
25225 }
25227 /* Compute default value for "length_address" attribute. */
25228 int
25230 {
25234 {
25245 }
25250 {
25253 {
25258 constraints++;
25261 ;
25262 /* Skip ignored operands. */
25265 }
25267 }
25269 }
25271 /* Compute default value for "length_vex" attribute. It includes
25272 2 or 3 byte VEX prefix and 1 opcode byte. */
25274 int
25276 {
25279 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25280 byte VEX prefix. */
25284 /* We can always use 2 byte VEX prefix in 32bit. */
25292 {
25293 /* REX.W bit uses 3 byte VEX prefix. */
25297 }
25298 else
25299 {
25300 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25304 }
25307 }
25308 \f
25309 /* Return the maximum number of instructions a cpu can issue. */
25311 static int
25313 {
25315 {
25346 }
25347 }
25349 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25350 by DEP_INSN and nothing set by DEP_INSN. */
25352 static bool
25354 {
25357 /* Simplify the test for uninteresting insns. */
25365 {
25368 }
25373 {
25376 }
25377 else
25383 /* This test is true if the dependent insn reads the flags but
25384 not any other potentially set register. */
25392 }
25394 /* Return true iff USE_INSN has a memory address with operands set by
25395 SET_INSN. */
25397 bool
25399 {
25404 {
25407 }
25409 }
25411 /* Helper function for exact_store_load_dependency.
25412 Return true if addr is found in insn. */
25413 static bool
25415 {
25422 {
25428 CASE_CONST_ANY:
25437 }
25441 {
25443 {
25453 }
25454 }
25456 }
25458 /* Return true if there exists exact dependency for store & load, i.e.
25459 the same memory address is used in them. */
25460 static bool
25462 {
25476 }
25478 static int
25480 {
25486 /* Anti and output dependencies have zero cost on all CPUs. */
25492 /* If we can't recognize the insns, we can't really do anything. */
25500 {
25502 /* Address Generation Interlock adds a cycle of latency. */
25504 {
25515 }
25519 /* ??? Compares pair with jump/setcc. */
25523 /* Floating point stores require value to be ready one cycle earlier. */
25531 /* INT->FP conversion is expensive. */
25535 /* There is one cycle extra latency between an FP op and a store. */
25545 /* Show ability of reorder buffer to hide latency of load by executing
25546 in parallel with previous instruction in case
25547 previous instruction is not needed to compute the address. */
25550 {
25551 /* Claim moves to take one cycle, as core can issue one load
25552 at time and the next load can start cycle later. */
25557 cost--;
25558 }
25562 /* The esp dependency is resolved before
25563 the instruction is really finished. */
25568 /* INT->FP conversion is expensive. */
25574 /* Show ability of reorder buffer to hide latency of load by executing
25575 in parallel with previous instruction in case
25576 previous instruction is not needed to compute the address. */
25579 {
25580 /* Claim moves to take one cycle, as core can issue one load
25581 at time and the next load can start cycle later. */
25587 else
25589 }
25600 /* Stack engine allows to execute push&pop instructions in parall. */
25604 /* FALLTHRU */
25610 /* Show ability of reorder buffer to hide latency of load by executing
25611 in parallel with previous instruction in case
25612 previous instruction is not needed to compute the address. */
25615 {
25619 /* Because of the difference between the length of integer and
25620 floating unit pipeline preparation stages, the memory operands
25621 for floating point are cheaper.
25623 ??? For Athlon it the difference is most probably 2. */
25626 else
25631 else
25633 }
25640 /* Stack engine allows to execute push&pop instructions in parall. */
25647 /* Show ability of reorder buffer to hide latency of load by executing
25648 in parallel with previous instruction in case
25649 previous instruction is not needed to compute the address. */
25652 {
25655 else
25657 }
25665 /* Increase cost of integer loads. */
25668 {
25671 {
25674 else
25675 {
25676 /* Increase cost of ld/st for short int types only
25677 because of store forwarding issue. */
25681 {
25682 /* Increase cost of store/load insn if exact
25683 dependence exists and it is load insn. */
25688 }
25689 }
25690 }
25691 }
25695 }
25698 }
25700 /* How many alternative schedules to try. This should be as wide as the
25701 scheduling freedom in the DFA, but no wider. Making this value too
25702 large results extra work for the scheduler. */
25704 static int
25706 {
25708 {
25720 /* We use lookahead value 4 for BD both before and after reload
25721 schedules. Plan is to have value 8 included for O3. */
25731 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25732 as many instructions can be executed on a cycle, i.e.,
25733 issue_rate. I wonder why tuning for many CPUs does not do this. */
25736 /* Don't use lookahead for pre-reload schedule to save compile time. */
25741 }
25742 }
25744 /* Return true if target platform supports macro-fusion. */
25746 static bool
25748 {
25750 }
25752 /* Check whether current microarchitecture support macro fusion
25753 for insn pair "CONDGEN + CONDJMP". Refer to
25754 "Intel Architectures Optimization Reference Manual". */
25756 static bool
25758 {
25777 else
25778 {
25783 {
25787 else
25789 }
25790 }
25797 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25798 supported. */
25805 /* No fusion for RIP-relative address. */
25812 ix86_address parts;
25818 }
25823 /* Check whether conditional jump use Sign or Overflow Flags. */
25831 /* Return true for TYPE_TEST and TYPE_ICMP. */
25836 /* The following is the case that macro-fusion for alu + jmp. */
25840 /* No fusion for alu op with memory destination operand. */
25845 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25846 supported. */
25855 }
25857 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25858 execution. It is applied if
25859 (1) IMUL instruction is on the top of list;
25860 (2) There exists the only producer of independent IMUL instruction in
25861 ready list.
25862 Return index of IMUL producer if it was found and -1 otherwise. */
25863 static int
25865 {
25867 sd_iterator_def sd_it;
25868 dep_t dep;
25875 /* Check that IMUL instruction is on the top of ready list. */
25884 /* Search for producer of independent IMUL instruction. */
25886 {
25890 /* Skip IMUL instruction. */
25900 {
25901 rtx con;
25912 {
25913 sd_iterator_def sd_it1;
25914 dep_t dep1;
25915 /* Check if there is no other dependee for IMUL. */
25918 {
25919 rtx pro;
25925 }
25928 }
25929 }
25932 }
25934 }
25936 /* Try to find the best candidate on the top of ready list if two insns
25937 have the same priority - candidate is best if its dependees were
25938 scheduled earlier. Applied for Silvermont only.
25939 Return true if top 2 insns must be interchanged. */
25940 static bool
25942 {
25945 rtx set;
25946 sd_iterator_def sd_it;
25947 dep_t dep;
25950 #define INSN_TICK(INSN) (HID (INSN)->tick)
25971 {
25974 /* Determine winner more precise. */
25976 {
25977 rtx pro;
25983 }
25985 {
25986 rtx pro;
25992 }
25995 {
25996 /* Determine winner - load must win. */
26002 }
26004 }
26006 #undef INSN_TICK
26007 }
26009 /* Perform possible reodering of ready list for Atom/Silvermont only.
26010 Return issue rate. */
26011 static int
26014 {
26018 rtx insn;
26021 /* Set up issue rate. */
26024 /* Do reodering for BONNELL/SILVERMONT only. */
26028 /* Nothing to do if ready list contains only 1 instruction. */
26032 /* Do reodering for post-reload scheduler only. */
26037 {
26042 /* Put IMUL producer (ready[index]) at the top of ready list. */
26048 }
26050 {
26054 /* Swap 2 top elements of ready list. */
26058 }
26060 }
26062 static bool
26065 /* Returns true if lhs of insn is HW function argument register and set up
26066 is_spilled to true if it is likely spilled HW register. */
26067 static bool
26069 {
26070 rtx dst;
26074 /* Call instructions are not movable, ignore it. */
26085 {
26086 /* Is it likely spilled HW register? */
26091 }
26093 }
26095 /* Add output dependencies for chain of function adjacent arguments if only
26096 there is a move to likely spilled HW register. Return first argument
26097 if at least one dependence was added or NULL otherwise. */
26098 static rtx
26100 {
26101 rtx insn;
26108 /* Find nearest to call argument passing instruction. */
26110 {
26119 }
26123 {
26130 {
26133 }
26135 {
26136 /* Add output depdendence between two function arguments if chain
26137 of output arguments contains likely spilled HW registers. */
26141 }
26142 else
26144 }
26148 }
26150 /* Add output or anti dependency from insn to first_arg to restrict its code
26151 motion. */
26152 static void
26154 {
26155 rtx set;
26156 rtx tmp;
26163 {
26164 /* Add output dependency to the first function argument. */
26167 }
26168 /* Add anti dependency. */
26170 }
26172 /* Avoid cross block motion of function argument through adding dependency
26173 from the first non-jump instruction in bb. */
26174 static void
26176 {
26180 {
26182 {
26185 {
26188 }
26189 }
26193 }
26194 }
26196 /* Hook for pre-reload schedule - avoid motion of function arguments
26197 passed in likely spilled HW registers. */
26198 static void
26200 {
26201 rtx insn;
26209 {
26212 {
26213 /* Add dependee for first argument to predecessors if only
26214 region contains more than one block. */
26218 /* Skip trivial regions and region head blocks that can have
26219 predecessors outside of region. */
26221 {
26222 edge e;
26223 edge_iterator ei;
26224 /* Assume that region is SCC, i.e. all immediate predecessors
26225 of non-head block are in the same region. */
26227 {
26228 /* Avoid creating of loop-carried dependencies through
26229 using topological odering in region. */
26232 }
26233 }
26237 }
26238 }
26241 }
26243 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26244 HW registers to maximum, to schedule them at soon as possible. These are
26245 moves from function argument registers at the top of the function entry
26246 and moves from function return value registers after call. */
26247 static int
26249 {
26250 rtx set;
26260 {
26267 }
26270 }
26272 /* Model decoder of Core 2/i7.
26273 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26274 track the instruction fetch block boundaries and make sure that long
26275 (9+ bytes) instructions are assigned to D0. */
26277 /* Maximum length of an insn that can be handled by
26278 a secondary decoder unit. '8' for Core 2/i7. */
26281 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26282 '16' for Core 2/i7. */
26285 /* Maximum number of instructions decoder can handle per cycle.
26286 '6' for Core 2/i7. */
26290 ix86_first_cycle_multipass_data_t;
26292 const_ix86_first_cycle_multipass_data_t;
26294 /* A variable to store target state across calls to max_issue within
26295 one cycle. */
26299 /* Initialize DATA. */
26300 static void
26302 {
26303 ix86_first_cycle_multipass_data_t data
26310 }
26312 /* Advancing the cycle; reset ifetch block counts. */
26313 static void
26315 {
26322 }
26326 /* Filter out insns from ready_try that the core will not be able to issue
26327 on current cycle due to decoder. */
26328 static void
26329 core2i7_first_cycle_multipass_filter_ready_try
26332 {
26334 {
26335 rtx insn;
26345 (!first_cycle_insn_p
26347 /* ... or it would not fit into the ifetch block ... */
26349 /* ... or the decoder is full already ... */
26351 /* ... mask the insn out. */
26352 {
26357 }
26358 }
26359 }
26361 /* Prepare for a new round of multipass lookahead scheduling. */
26362 static void
26365 {
26366 ix86_first_cycle_multipass_data_t data
26368 const_ix86_first_cycle_multipass_data_t prev_data
26371 /* Restore the state from the end of the previous round. */
26375 /* Filter instructions that cannot be issued on current cycle due to
26376 decoder restrictions. */
26378 first_cycle_insn_p);
26379 }
26381 /* INSN is being issued in current solution. Account for its impact on
26382 the decoder model. */
26383 static void
26386 {
26387 ix86_first_cycle_multipass_data_t data
26389 const_ix86_first_cycle_multipass_data_t prev_data
26399 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26401 {
26404 }
26406 {
26410 }
26413 /* Filter out insns from ready_try that the core will not be able to issue
26414 on current cycle due to decoder. */
26417 }
26419 /* Revert the effect on ready_try. */
26420 static void
26424 {
26425 const_ix86_first_cycle_multipass_data_t data
26428 sbitmap_iterator sbi;
26432 {
26434 }
26435 }
26437 /* Save the result of multipass lookahead scheduling for the next round. */
26438 static void
26440 {
26441 const_ix86_first_cycle_multipass_data_t data
26443 ix86_first_cycle_multipass_data_t next_data
26447 {
26450 }
26451 }
26453 /* Deallocate target data. */
26454 static void
26456 {
26457 ix86_first_cycle_multipass_data_t data
26461 {
26465 }
26466 }
26468 /* Prepare for scheduling pass. */
26469 static void
26473 {
26474 /* Install scheduling hooks for current CPU. Some of these hooks are used
26475 in time-critical parts of the scheduler, so we only set them up when
26476 they are actually used. */
26478 {
26483 /* Do not perform multipass scheduling for pre-reload schedule
26484 to save compile time. */
26486 {
26502 /* Set decoder parameters. */
26507 }
26508 /* ... Fall through ... */
26518 }
26519 }
26521 \f
26522 /* Compute the alignment given to a constant that is being placed in memory.
26523 EXP is the constant and ALIGN is the alignment that the object would
26524 ordinarily have.
26525 The value of this function is used instead of that alignment to align
26526 the object. */
26528 int
26530 {
26533 {
26538 }
26544 }
26546 /* Compute the alignment for a static variable.
26547 TYPE is the data type, and ALIGN is the alignment that
26548 the object would ordinarily have. The value of this function is used
26549 instead of that alignment to align the object. */
26551 int
26553 {
26554 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26555 for symbols from other compilation units or symbols that don't need
26556 to bind locally. In order to preserve some ABI compatibility with
26557 those compilers, ensure we don't decrease alignment from what we
26558 used to assume. */
26560 int max_align_compat
26563 /* A data structure, equal or greater than the size of a cache line
26564 (64 bytes in the Pentium 4 and other recent Intel processors, including
26565 processors based on Intel Core microarchitecture) should be aligned
26566 so that its base address is a multiple of a cache line size. */
26568 int max_align
26578 {
26587 }
26589 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26590 to 16byte boundary. */
26592 {
26599 }
26605 {
26610 }
26612 {
26619 }
26624 {
26629 }
26632 {
26637 }
26640 }
26642 /* Compute the alignment for a local variable or a stack slot. EXP is
26643 the data type or decl itself, MODE is the widest mode available and
26644 ALIGN is the alignment that the object would ordinarily have. The
26645 value of this macro is used instead of that alignment to align the
26646 object. */
26648 unsigned int
26651 {
26655 {
26658 }
26659 else
26660 {
26663 }
26665 /* Don't do dynamic stack realignment for long long objects with
26666 -mpreferred-stack-boundary=2. */
26675 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26676 register in MODE. We will return the largest alignment of XF
26677 and DF. */
26679 {
26683 }
26685 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26686 to 16byte boundary. Exact wording is:
26688 An array uses the same alignment as its elements, except that a local or
26689 global array variable of length at least 16 bytes or
26690 a C99 variable-length array variable always has alignment of at least 16 bytes.
26692 This was added to allow use of aligned SSE instructions at arrays. This
26693 rule is meant for static storage (where compiler can not do the analysis
26694 by itself). We follow it for automatic variables only when convenient.
26695 We fully control everything in the function compiled and functions from
26696 other unit can not rely on the alignment.
26698 Exclude va_list type. It is the common case of local array where
26699 we can not benefit from the alignment.
26701 TODO: Probably one should optimize for size only when var is not escaping. */
26704 {
26714 }
26716 {
26721 }
26723 {
26729 }
26734 {
26739 }
26742 {
26748 }
26750 }
26752 /* Compute the minimum required alignment for dynamic stack realignment
26753 purposes for a local variable, parameter or a stack slot. EXP is
26754 the data type or decl itself, MODE is its mode and ALIGN is the
26755 alignment that the object would ordinarily have. */
26757 unsigned int
26760 {
26764 {
26767 }
26768 else
26769 {
26772 }
26777 /* Don't do dynamic stack realignment for long long objects with
26778 -mpreferred-stack-boundary=2. */
26785 }
26786 \f
26787 /* Find a location for the static chain incoming to a nested function.
26788 This is a register, unless all free registers are used by arguments. */
26790 static rtx
26792 {
26799 {
26800 /* We always use R10 in 64-bit mode. */
26802 }
26803 else
26804 {
26805 tree fntype;
26808 /* By default in 32-bit mode we use ECX to pass the static chain. */
26814 {
26815 /* Fastcall functions use ecx/edx for arguments, which leaves
26816 us with EAX for the static chain.
26817 Thiscall functions use ecx for arguments, which also
26818 leaves us with EAX for the static chain. */
26820 }
26822 {
26823 /* Thiscall functions use ecx for arguments, which leaves
26824 us with EAX and EDX for the static chain.
26825 We are using for abi-compatibility EAX. */
26827 }
26829 {
26830 /* For regparm 3, we have no free call-clobbered registers in
26831 which to store the static chain. In order to implement this,
26832 we have the trampoline push the static chain to the stack.
26833 However, we can't push a value below the return address when
26834 we call the nested function directly, so we have to use an
26835 alternate entry point. For this we use ESI, and have the
26836 alternate entry point push ESI, so that things appear the
26837 same once we're executing the nested function. */
26839 {
26845 }
26847 }
26848 }
26851 }
26853 /* Emit RTL insns to initialize the variable parts of a trampoline.
26854 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26855 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26856 to be passed to the target function. */
26858 static void
26860 {
26868 {
26871 /* Load the function address to r11. Try to load address using
26872 the shorter movl instead of movabs. We may want to support
26873 movq for kernel mode, but kernel does not use trampolines at
26874 the moment. FNADDR is a 32bit address and may not be in
26875 DImode when ptr_mode == SImode. Always use movl in this
26876 case. */
26879 {
26888 }
26889 else
26890 {
26897 }
26899 /* Load static chain using movabs to r10. Use the shorter movl
26900 instead of movabs when ptr_mode == SImode. */
26902 {
26905 }
26906 else
26907 {
26910 }
26919 /* Jump to r11; the last (unused) byte is a nop, only there to
26920 pad the write out to a single 32-bit store. */
26924 }
26925 else
26926 {
26929 /* Depending on the static chain location, either load a register
26930 with a constant, or push the constant to the stack. All of the
26931 instructions are the same size. */
26934 {
26936 {
26943 }
26944 }
26945 else
26960 /* Compute offset from the end of the jmp to the target function.
26961 In the case in which the trampoline stores the static chain on
26962 the stack, we need to skip the first insn which pushes the
26963 (call-saved) register static chain; this push is 1 byte. */
26970 }
26974 #ifdef HAVE_ENABLE_EXECUTE_STACK
26975 #ifdef CHECK_EXECUTE_STACK_ENABLED
26977 #endif
26980 #endif
26981 }
26982 \f
26983 /* The following file contains several enumerations and data structures
26984 built from the definitions in i386-builtin-types.def. */
26988 /* Table for the ix86 builtin non-function types. */
26991 /* Retrieve an element from the above table, building some of
26992 the types lazily. */
26994 static tree
26996 {
27008 {
27016 }
27017 else
27018 {
27024 else
27032 }
27036 }
27038 /* Table for the ix86 builtin function types. */
27041 /* Retrieve an element from the above table, building some of
27042 the types lazily. */
27044 static tree
27046 {
27047 tree type;
27056 {
27064 {
27067 }
27070 }
27071 else
27072 {
27078 }
27082 }
27085 /* Codes for all the SSE/MMX builtins. */
27086 enum ix86_builtins
27087 {
27088 IX86_BUILTIN_ADDPS,
27089 IX86_BUILTIN_ADDSS,
27090 IX86_BUILTIN_DIVPS,
27091 IX86_BUILTIN_DIVSS,
27092 IX86_BUILTIN_MULPS,
27093 IX86_BUILTIN_MULSS,
27094 IX86_BUILTIN_SUBPS,
27095 IX86_BUILTIN_SUBSS,
27097 IX86_BUILTIN_CMPEQPS,
27098 IX86_BUILTIN_CMPLTPS,
27099 IX86_BUILTIN_CMPLEPS,
27100 IX86_BUILTIN_CMPGTPS,
27101 IX86_BUILTIN_CMPGEPS,
27102 IX86_BUILTIN_CMPNEQPS,
27103 IX86_BUILTIN_CMPNLTPS,
27104 IX86_BUILTIN_CMPNLEPS,
27105 IX86_BUILTIN_CMPNGTPS,
27106 IX86_BUILTIN_CMPNGEPS,
27107 IX86_BUILTIN_CMPORDPS,
27108 IX86_BUILTIN_CMPUNORDPS,
27109 IX86_BUILTIN_CMPEQSS,
27110 IX86_BUILTIN_CMPLTSS,
27111 IX86_BUILTIN_CMPLESS,
27112 IX86_BUILTIN_CMPNEQSS,
27113 IX86_BUILTIN_CMPNLTSS,
27114 IX86_BUILTIN_CMPNLESS,
27115 IX86_BUILTIN_CMPORDSS,
27116 IX86_BUILTIN_CMPUNORDSS,
27118 IX86_BUILTIN_COMIEQSS,
27119 IX86_BUILTIN_COMILTSS,
27120 IX86_BUILTIN_COMILESS,
27121 IX86_BUILTIN_COMIGTSS,
27122 IX86_BUILTIN_COMIGESS,
27123 IX86_BUILTIN_COMINEQSS,
27124 IX86_BUILTIN_UCOMIEQSS,
27125 IX86_BUILTIN_UCOMILTSS,
27126 IX86_BUILTIN_UCOMILESS,
27127 IX86_BUILTIN_UCOMIGTSS,
27128 IX86_BUILTIN_UCOMIGESS,
27129 IX86_BUILTIN_UCOMINEQSS,
27131 IX86_BUILTIN_CVTPI2PS,
27132 IX86_BUILTIN_CVTPS2PI,
27133 IX86_BUILTIN_CVTSI2SS,
27134 IX86_BUILTIN_CVTSI642SS,
27135 IX86_BUILTIN_CVTSS2SI,
27136 IX86_BUILTIN_CVTSS2SI64,
27137 IX86_BUILTIN_CVTTPS2PI,
27138 IX86_BUILTIN_CVTTSS2SI,
27139 IX86_BUILTIN_CVTTSS2SI64,
27141 IX86_BUILTIN_MAXPS,
27142 IX86_BUILTIN_MAXSS,
27143 IX86_BUILTIN_MINPS,
27144 IX86_BUILTIN_MINSS,
27146 IX86_BUILTIN_LOADUPS,
27147 IX86_BUILTIN_STOREUPS,
27148 IX86_BUILTIN_MOVSS,
27150 IX86_BUILTIN_MOVHLPS,
27151 IX86_BUILTIN_MOVLHPS,
27152 IX86_BUILTIN_LOADHPS,
27153 IX86_BUILTIN_LOADLPS,
27154 IX86_BUILTIN_STOREHPS,
27155 IX86_BUILTIN_STORELPS,
27157 IX86_BUILTIN_MASKMOVQ,
27158 IX86_BUILTIN_MOVMSKPS,
27159 IX86_BUILTIN_PMOVMSKB,
27161 IX86_BUILTIN_MOVNTPS,
27162 IX86_BUILTIN_MOVNTQ,
27164 IX86_BUILTIN_LOADDQU,
27165 IX86_BUILTIN_STOREDQU,
27167 IX86_BUILTIN_PACKSSWB,
27168 IX86_BUILTIN_PACKSSDW,
27169 IX86_BUILTIN_PACKUSWB,
27171 IX86_BUILTIN_PADDB,
27172 IX86_BUILTIN_PADDW,
27173 IX86_BUILTIN_PADDD,
27174 IX86_BUILTIN_PADDQ,
27175 IX86_BUILTIN_PADDSB,
27176 IX86_BUILTIN_PADDSW,
27177 IX86_BUILTIN_PADDUSB,
27178 IX86_BUILTIN_PADDUSW,
27179 IX86_BUILTIN_PSUBB,
27180 IX86_BUILTIN_PSUBW,
27181 IX86_BUILTIN_PSUBD,
27182 IX86_BUILTIN_PSUBQ,
27183 IX86_BUILTIN_PSUBSB,
27184 IX86_BUILTIN_PSUBSW,
27185 IX86_BUILTIN_PSUBUSB,
27186 IX86_BUILTIN_PSUBUSW,
27188 IX86_BUILTIN_PAND,
27189 IX86_BUILTIN_PANDN,
27190 IX86_BUILTIN_POR,
27191 IX86_BUILTIN_PXOR,
27193 IX86_BUILTIN_PAVGB,
27194 IX86_BUILTIN_PAVGW,
27196 IX86_BUILTIN_PCMPEQB,
27197 IX86_BUILTIN_PCMPEQW,
27198 IX86_BUILTIN_PCMPEQD,
27199 IX86_BUILTIN_PCMPGTB,
27200 IX86_BUILTIN_PCMPGTW,
27201 IX86_BUILTIN_PCMPGTD,
27203 IX86_BUILTIN_PMADDWD,
27205 IX86_BUILTIN_PMAXSW,
27206 IX86_BUILTIN_PMAXUB,
27207 IX86_BUILTIN_PMINSW,
27208 IX86_BUILTIN_PMINUB,
27210 IX86_BUILTIN_PMULHUW,
27211 IX86_BUILTIN_PMULHW,
27212 IX86_BUILTIN_PMULLW,
27214 IX86_BUILTIN_PSADBW,
27215 IX86_BUILTIN_PSHUFW,
27217 IX86_BUILTIN_PSLLW,
27218 IX86_BUILTIN_PSLLD,
27219 IX86_BUILTIN_PSLLQ,
27220 IX86_BUILTIN_PSRAW,
27221 IX86_BUILTIN_PSRAD,
27222 IX86_BUILTIN_PSRLW,
27223 IX86_BUILTIN_PSRLD,
27224 IX86_BUILTIN_PSRLQ,
27225 IX86_BUILTIN_PSLLWI,
27226 IX86_BUILTIN_PSLLDI,
27227 IX86_BUILTIN_PSLLQI,
27228 IX86_BUILTIN_PSRAWI,
27229 IX86_BUILTIN_PSRADI,
27230 IX86_BUILTIN_PSRLWI,
27231 IX86_BUILTIN_PSRLDI,
27232 IX86_BUILTIN_PSRLQI,
27234 IX86_BUILTIN_PUNPCKHBW,
27235 IX86_BUILTIN_PUNPCKHWD,
27236 IX86_BUILTIN_PUNPCKHDQ,
27237 IX86_BUILTIN_PUNPCKLBW,
27238 IX86_BUILTIN_PUNPCKLWD,
27239 IX86_BUILTIN_PUNPCKLDQ,
27241 IX86_BUILTIN_SHUFPS,
27243 IX86_BUILTIN_RCPPS,
27244 IX86_BUILTIN_RCPSS,
27245 IX86_BUILTIN_RSQRTPS,
27246 IX86_BUILTIN_RSQRTPS_NR,
27247 IX86_BUILTIN_RSQRTSS,
27248 IX86_BUILTIN_RSQRTF,
27249 IX86_BUILTIN_SQRTPS,
27250 IX86_BUILTIN_SQRTPS_NR,
27251 IX86_BUILTIN_SQRTSS,
27253 IX86_BUILTIN_UNPCKHPS,
27254 IX86_BUILTIN_UNPCKLPS,
27256 IX86_BUILTIN_ANDPS,
27257 IX86_BUILTIN_ANDNPS,
27258 IX86_BUILTIN_ORPS,
27259 IX86_BUILTIN_XORPS,
27261 IX86_BUILTIN_EMMS,
27262 IX86_BUILTIN_LDMXCSR,
27263 IX86_BUILTIN_STMXCSR,
27264 IX86_BUILTIN_SFENCE,
27266 IX86_BUILTIN_FXSAVE,
27267 IX86_BUILTIN_FXRSTOR,
27268 IX86_BUILTIN_FXSAVE64,
27269 IX86_BUILTIN_FXRSTOR64,
27271 IX86_BUILTIN_XSAVE,
27272 IX86_BUILTIN_XRSTOR,
27273 IX86_BUILTIN_XSAVE64,
27274 IX86_BUILTIN_XRSTOR64,
27276 IX86_BUILTIN_XSAVEOPT,
27277 IX86_BUILTIN_XSAVEOPT64,
27279 /* 3DNow! Original */
27280 IX86_BUILTIN_FEMMS,
27281 IX86_BUILTIN_PAVGUSB,
27282 IX86_BUILTIN_PF2ID,
27283 IX86_BUILTIN_PFACC,
27284 IX86_BUILTIN_PFADD,
27285 IX86_BUILTIN_PFCMPEQ,
27286 IX86_BUILTIN_PFCMPGE,
27287 IX86_BUILTIN_PFCMPGT,
27288 IX86_BUILTIN_PFMAX,
27289 IX86_BUILTIN_PFMIN,
27290 IX86_BUILTIN_PFMUL,
27291 IX86_BUILTIN_PFRCP,
27292 IX86_BUILTIN_PFRCPIT1,
27293 IX86_BUILTIN_PFRCPIT2,
27294 IX86_BUILTIN_PFRSQIT1,
27295 IX86_BUILTIN_PFRSQRT,
27296 IX86_BUILTIN_PFSUB,
27297 IX86_BUILTIN_PFSUBR,
27298 IX86_BUILTIN_PI2FD,
27299 IX86_BUILTIN_PMULHRW,
27301 /* 3DNow! Athlon Extensions */
27302 IX86_BUILTIN_PF2IW,
27303 IX86_BUILTIN_PFNACC,
27304 IX86_BUILTIN_PFPNACC,
27305 IX86_BUILTIN_PI2FW,
27306 IX86_BUILTIN_PSWAPDSI,
27307 IX86_BUILTIN_PSWAPDSF,
27309 /* SSE2 */
27310 IX86_BUILTIN_ADDPD,
27311 IX86_BUILTIN_ADDSD,
27312 IX86_BUILTIN_DIVPD,
27313 IX86_BUILTIN_DIVSD,
27314 IX86_BUILTIN_MULPD,
27315 IX86_BUILTIN_MULSD,
27316 IX86_BUILTIN_SUBPD,
27317 IX86_BUILTIN_SUBSD,
27319 IX86_BUILTIN_CMPEQPD,
27320 IX86_BUILTIN_CMPLTPD,
27321 IX86_BUILTIN_CMPLEPD,
27322 IX86_BUILTIN_CMPGTPD,
27323 IX86_BUILTIN_CMPGEPD,
27324 IX86_BUILTIN_CMPNEQPD,
27325 IX86_BUILTIN_CMPNLTPD,
27326 IX86_BUILTIN_CMPNLEPD,
27327 IX86_BUILTIN_CMPNGTPD,
27328 IX86_BUILTIN_CMPNGEPD,
27329 IX86_BUILTIN_CMPORDPD,
27330 IX86_BUILTIN_CMPUNORDPD,
27331 IX86_BUILTIN_CMPEQSD,
27332 IX86_BUILTIN_CMPLTSD,
27333 IX86_BUILTIN_CMPLESD,
27334 IX86_BUILTIN_CMPNEQSD,
27335 IX86_BUILTIN_CMPNLTSD,
27336 IX86_BUILTIN_CMPNLESD,
27337 IX86_BUILTIN_CMPORDSD,
27338 IX86_BUILTIN_CMPUNORDSD,
27340 IX86_BUILTIN_COMIEQSD,
27341 IX86_BUILTIN_COMILTSD,
27342 IX86_BUILTIN_COMILESD,
27343 IX86_BUILTIN_COMIGTSD,
27344 IX86_BUILTIN_COMIGESD,
27345 IX86_BUILTIN_COMINEQSD,
27346 IX86_BUILTIN_UCOMIEQSD,
27347 IX86_BUILTIN_UCOMILTSD,
27348 IX86_BUILTIN_UCOMILESD,
27349 IX86_BUILTIN_UCOMIGTSD,
27350 IX86_BUILTIN_UCOMIGESD,
27351 IX86_BUILTIN_UCOMINEQSD,
27353 IX86_BUILTIN_MAXPD,
27354 IX86_BUILTIN_MAXSD,
27355 IX86_BUILTIN_MINPD,
27356 IX86_BUILTIN_MINSD,
27358 IX86_BUILTIN_ANDPD,
27359 IX86_BUILTIN_ANDNPD,
27360 IX86_BUILTIN_ORPD,
27361 IX86_BUILTIN_XORPD,
27363 IX86_BUILTIN_SQRTPD,
27364 IX86_BUILTIN_SQRTSD,
27366 IX86_BUILTIN_UNPCKHPD,
27367 IX86_BUILTIN_UNPCKLPD,
27369 IX86_BUILTIN_SHUFPD,
27371 IX86_BUILTIN_LOADUPD,
27372 IX86_BUILTIN_STOREUPD,
27373 IX86_BUILTIN_MOVSD,
27375 IX86_BUILTIN_LOADHPD,
27376 IX86_BUILTIN_LOADLPD,
27378 IX86_BUILTIN_CVTDQ2PD,
27379 IX86_BUILTIN_CVTDQ2PS,
27381 IX86_BUILTIN_CVTPD2DQ,
27382 IX86_BUILTIN_CVTPD2PI,
27383 IX86_BUILTIN_CVTPD2PS,
27384 IX86_BUILTIN_CVTTPD2DQ,
27385 IX86_BUILTIN_CVTTPD2PI,
27387 IX86_BUILTIN_CVTPI2PD,
27388 IX86_BUILTIN_CVTSI2SD,
27389 IX86_BUILTIN_CVTSI642SD,
27391 IX86_BUILTIN_CVTSD2SI,
27392 IX86_BUILTIN_CVTSD2SI64,
27393 IX86_BUILTIN_CVTSD2SS,
27394 IX86_BUILTIN_CVTSS2SD,
27395 IX86_BUILTIN_CVTTSD2SI,
27396 IX86_BUILTIN_CVTTSD2SI64,
27398 IX86_BUILTIN_CVTPS2DQ,
27399 IX86_BUILTIN_CVTPS2PD,
27400 IX86_BUILTIN_CVTTPS2DQ,
27402 IX86_BUILTIN_MOVNTI,
27403 IX86_BUILTIN_MOVNTI64,
27404 IX86_BUILTIN_MOVNTPD,
27405 IX86_BUILTIN_MOVNTDQ,
27407 IX86_BUILTIN_MOVQ128,
27409 /* SSE2 MMX */
27410 IX86_BUILTIN_MASKMOVDQU,
27411 IX86_BUILTIN_MOVMSKPD,
27412 IX86_BUILTIN_PMOVMSKB128,
27414 IX86_BUILTIN_PACKSSWB128,
27415 IX86_BUILTIN_PACKSSDW128,
27416 IX86_BUILTIN_PACKUSWB128,
27418 IX86_BUILTIN_PADDB128,
27419 IX86_BUILTIN_PADDW128,
27420 IX86_BUILTIN_PADDD128,
27421 IX86_BUILTIN_PADDQ128,
27422 IX86_BUILTIN_PADDSB128,
27423 IX86_BUILTIN_PADDSW128,
27424 IX86_BUILTIN_PADDUSB128,
27425 IX86_BUILTIN_PADDUSW128,
27426 IX86_BUILTIN_PSUBB128,
27427 IX86_BUILTIN_PSUBW128,
27428 IX86_BUILTIN_PSUBD128,
27429 IX86_BUILTIN_PSUBQ128,
27430 IX86_BUILTIN_PSUBSB128,
27431 IX86_BUILTIN_PSUBSW128,
27432 IX86_BUILTIN_PSUBUSB128,
27433 IX86_BUILTIN_PSUBUSW128,
27435 IX86_BUILTIN_PAND128,
27436 IX86_BUILTIN_PANDN128,
27437 IX86_BUILTIN_POR128,
27438 IX86_BUILTIN_PXOR128,
27440 IX86_BUILTIN_PAVGB128,
27441 IX86_BUILTIN_PAVGW128,
27443 IX86_BUILTIN_PCMPEQB128,
27444 IX86_BUILTIN_PCMPEQW128,
27445 IX86_BUILTIN_PCMPEQD128,
27446 IX86_BUILTIN_PCMPGTB128,
27447 IX86_BUILTIN_PCMPGTW128,
27448 IX86_BUILTIN_PCMPGTD128,
27450 IX86_BUILTIN_PMADDWD128,
27452 IX86_BUILTIN_PMAXSW128,
27453 IX86_BUILTIN_PMAXUB128,
27454 IX86_BUILTIN_PMINSW128,
27455 IX86_BUILTIN_PMINUB128,
27457 IX86_BUILTIN_PMULUDQ,
27458 IX86_BUILTIN_PMULUDQ128,
27459 IX86_BUILTIN_PMULHUW128,
27460 IX86_BUILTIN_PMULHW128,
27461 IX86_BUILTIN_PMULLW128,
27463 IX86_BUILTIN_PSADBW128,
27464 IX86_BUILTIN_PSHUFHW,
27465 IX86_BUILTIN_PSHUFLW,
27466 IX86_BUILTIN_PSHUFD,
27468 IX86_BUILTIN_PSLLDQI128,
27469 IX86_BUILTIN_PSLLWI128,
27470 IX86_BUILTIN_PSLLDI128,
27471 IX86_BUILTIN_PSLLQI128,
27472 IX86_BUILTIN_PSRAWI128,
27473 IX86_BUILTIN_PSRADI128,
27474 IX86_BUILTIN_PSRLDQI128,
27475 IX86_BUILTIN_PSRLWI128,
27476 IX86_BUILTIN_PSRLDI128,
27477 IX86_BUILTIN_PSRLQI128,
27479 IX86_BUILTIN_PSLLDQ128,
27480 IX86_BUILTIN_PSLLW128,
27481 IX86_BUILTIN_PSLLD128,
27482 IX86_BUILTIN_PSLLQ128,
27483 IX86_BUILTIN_PSRAW128,
27484 IX86_BUILTIN_PSRAD128,
27485 IX86_BUILTIN_PSRLW128,
27486 IX86_BUILTIN_PSRLD128,
27487 IX86_BUILTIN_PSRLQ128,
27489 IX86_BUILTIN_PUNPCKHBW128,
27490 IX86_BUILTIN_PUNPCKHWD128,
27491 IX86_BUILTIN_PUNPCKHDQ128,
27492 IX86_BUILTIN_PUNPCKHQDQ128,
27493 IX86_BUILTIN_PUNPCKLBW128,
27494 IX86_BUILTIN_PUNPCKLWD128,
27495 IX86_BUILTIN_PUNPCKLDQ128,
27496 IX86_BUILTIN_PUNPCKLQDQ128,
27498 IX86_BUILTIN_CLFLUSH,
27499 IX86_BUILTIN_MFENCE,
27500 IX86_BUILTIN_LFENCE,
27501 IX86_BUILTIN_PAUSE,
27503 IX86_BUILTIN_FNSTENV,
27504 IX86_BUILTIN_FLDENV,
27505 IX86_BUILTIN_FNSTSW,
27506 IX86_BUILTIN_FNCLEX,
27508 IX86_BUILTIN_BSRSI,
27509 IX86_BUILTIN_BSRDI,
27510 IX86_BUILTIN_RDPMC,
27511 IX86_BUILTIN_RDTSC,
27512 IX86_BUILTIN_RDTSCP,
27513 IX86_BUILTIN_ROLQI,
27514 IX86_BUILTIN_ROLHI,
27515 IX86_BUILTIN_RORQI,
27516 IX86_BUILTIN_RORHI,
27518 /* SSE3. */
27519 IX86_BUILTIN_ADDSUBPS,
27520 IX86_BUILTIN_HADDPS,
27521 IX86_BUILTIN_HSUBPS,
27522 IX86_BUILTIN_MOVSHDUP,
27523 IX86_BUILTIN_MOVSLDUP,
27524 IX86_BUILTIN_ADDSUBPD,
27525 IX86_BUILTIN_HADDPD,
27526 IX86_BUILTIN_HSUBPD,
27527 IX86_BUILTIN_LDDQU,
27529 IX86_BUILTIN_MONITOR,
27530 IX86_BUILTIN_MWAIT,
27532 /* SSSE3. */
27533 IX86_BUILTIN_PHADDW,
27534 IX86_BUILTIN_PHADDD,
27535 IX86_BUILTIN_PHADDSW,
27536 IX86_BUILTIN_PHSUBW,
27537 IX86_BUILTIN_PHSUBD,
27538 IX86_BUILTIN_PHSUBSW,
27539 IX86_BUILTIN_PMADDUBSW,
27540 IX86_BUILTIN_PMULHRSW,
27541 IX86_BUILTIN_PSHUFB,
27542 IX86_BUILTIN_PSIGNB,
27543 IX86_BUILTIN_PSIGNW,
27544 IX86_BUILTIN_PSIGND,
27545 IX86_BUILTIN_PALIGNR,
27546 IX86_BUILTIN_PABSB,
27547 IX86_BUILTIN_PABSW,
27548 IX86_BUILTIN_PABSD,
27550 IX86_BUILTIN_PHADDW128,
27551 IX86_BUILTIN_PHADDD128,
27552 IX86_BUILTIN_PHADDSW128,
27553 IX86_BUILTIN_PHSUBW128,
27554 IX86_BUILTIN_PHSUBD128,
27555 IX86_BUILTIN_PHSUBSW128,
27556 IX86_BUILTIN_PMADDUBSW128,
27557 IX86_BUILTIN_PMULHRSW128,
27558 IX86_BUILTIN_PSHUFB128,
27559 IX86_BUILTIN_PSIGNB128,
27560 IX86_BUILTIN_PSIGNW128,
27561 IX86_BUILTIN_PSIGND128,
27562 IX86_BUILTIN_PALIGNR128,
27563 IX86_BUILTIN_PABSB128,
27564 IX86_BUILTIN_PABSW128,
27565 IX86_BUILTIN_PABSD128,
27567 /* AMDFAM10 - SSE4A New Instructions. */
27568 IX86_BUILTIN_MOVNTSD,
27569 IX86_BUILTIN_MOVNTSS,
27570 IX86_BUILTIN_EXTRQI,
27571 IX86_BUILTIN_EXTRQ,
27572 IX86_BUILTIN_INSERTQI,
27573 IX86_BUILTIN_INSERTQ,
27575 /* SSE4.1. */
27576 IX86_BUILTIN_BLENDPD,
27577 IX86_BUILTIN_BLENDPS,
27578 IX86_BUILTIN_BLENDVPD,
27579 IX86_BUILTIN_BLENDVPS,
27580 IX86_BUILTIN_PBLENDVB128,
27581 IX86_BUILTIN_PBLENDW128,
27583 IX86_BUILTIN_DPPD,
27584 IX86_BUILTIN_DPPS,
27586 IX86_BUILTIN_INSERTPS128,
27588 IX86_BUILTIN_MOVNTDQA,
27589 IX86_BUILTIN_MPSADBW128,
27590 IX86_BUILTIN_PACKUSDW128,
27591 IX86_BUILTIN_PCMPEQQ,
27592 IX86_BUILTIN_PHMINPOSUW128,
27594 IX86_BUILTIN_PMAXSB128,
27595 IX86_BUILTIN_PMAXSD128,
27596 IX86_BUILTIN_PMAXUD128,
27597 IX86_BUILTIN_PMAXUW128,
27599 IX86_BUILTIN_PMINSB128,
27600 IX86_BUILTIN_PMINSD128,
27601 IX86_BUILTIN_PMINUD128,
27602 IX86_BUILTIN_PMINUW128,
27604 IX86_BUILTIN_PMOVSXBW128,
27605 IX86_BUILTIN_PMOVSXBD128,
27606 IX86_BUILTIN_PMOVSXBQ128,
27607 IX86_BUILTIN_PMOVSXWD128,
27608 IX86_BUILTIN_PMOVSXWQ128,
27609 IX86_BUILTIN_PMOVSXDQ128,
27611 IX86_BUILTIN_PMOVZXBW128,
27612 IX86_BUILTIN_PMOVZXBD128,
27613 IX86_BUILTIN_PMOVZXBQ128,
27614 IX86_BUILTIN_PMOVZXWD128,
27615 IX86_BUILTIN_PMOVZXWQ128,
27616 IX86_BUILTIN_PMOVZXDQ128,
27618 IX86_BUILTIN_PMULDQ128,
27619 IX86_BUILTIN_PMULLD128,
27621 IX86_BUILTIN_ROUNDSD,
27622 IX86_BUILTIN_ROUNDSS,
27624 IX86_BUILTIN_ROUNDPD,
27625 IX86_BUILTIN_ROUNDPS,
27627 IX86_BUILTIN_FLOORPD,
27628 IX86_BUILTIN_CEILPD,
27629 IX86_BUILTIN_TRUNCPD,
27630 IX86_BUILTIN_RINTPD,
27631 IX86_BUILTIN_ROUNDPD_AZ,
27633 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27634 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27635 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27637 IX86_BUILTIN_FLOORPS,
27638 IX86_BUILTIN_CEILPS,
27639 IX86_BUILTIN_TRUNCPS,
27640 IX86_BUILTIN_RINTPS,
27641 IX86_BUILTIN_ROUNDPS_AZ,
27643 IX86_BUILTIN_FLOORPS_SFIX,
27644 IX86_BUILTIN_CEILPS_SFIX,
27645 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27647 IX86_BUILTIN_PTESTZ,
27648 IX86_BUILTIN_PTESTC,
27649 IX86_BUILTIN_PTESTNZC,
27651 IX86_BUILTIN_VEC_INIT_V2SI,
27652 IX86_BUILTIN_VEC_INIT_V4HI,
27653 IX86_BUILTIN_VEC_INIT_V8QI,
27654 IX86_BUILTIN_VEC_EXT_V2DF,
27655 IX86_BUILTIN_VEC_EXT_V2DI,
27656 IX86_BUILTIN_VEC_EXT_V4SF,
27657 IX86_BUILTIN_VEC_EXT_V4SI,
27658 IX86_BUILTIN_VEC_EXT_V8HI,
27659 IX86_BUILTIN_VEC_EXT_V2SI,
27660 IX86_BUILTIN_VEC_EXT_V4HI,
27661 IX86_BUILTIN_VEC_EXT_V16QI,
27662 IX86_BUILTIN_VEC_SET_V2DI,
27663 IX86_BUILTIN_VEC_SET_V4SF,
27664 IX86_BUILTIN_VEC_SET_V4SI,
27665 IX86_BUILTIN_VEC_SET_V8HI,
27666 IX86_BUILTIN_VEC_SET_V4HI,
27667 IX86_BUILTIN_VEC_SET_V16QI,
27669 IX86_BUILTIN_VEC_PACK_SFIX,
27670 IX86_BUILTIN_VEC_PACK_SFIX256,
27672 /* SSE4.2. */
27673 IX86_BUILTIN_CRC32QI,
27674 IX86_BUILTIN_CRC32HI,
27675 IX86_BUILTIN_CRC32SI,
27676 IX86_BUILTIN_CRC32DI,
27678 IX86_BUILTIN_PCMPESTRI128,
27679 IX86_BUILTIN_PCMPESTRM128,
27680 IX86_BUILTIN_PCMPESTRA128,
27681 IX86_BUILTIN_PCMPESTRC128,
27682 IX86_BUILTIN_PCMPESTRO128,
27683 IX86_BUILTIN_PCMPESTRS128,
27684 IX86_BUILTIN_PCMPESTRZ128,
27685 IX86_BUILTIN_PCMPISTRI128,
27686 IX86_BUILTIN_PCMPISTRM128,
27687 IX86_BUILTIN_PCMPISTRA128,
27688 IX86_BUILTIN_PCMPISTRC128,
27689 IX86_BUILTIN_PCMPISTRO128,
27690 IX86_BUILTIN_PCMPISTRS128,
27691 IX86_BUILTIN_PCMPISTRZ128,
27693 IX86_BUILTIN_PCMPGTQ,
27695 /* AES instructions */
27696 IX86_BUILTIN_AESENC128,
27697 IX86_BUILTIN_AESENCLAST128,
27698 IX86_BUILTIN_AESDEC128,
27699 IX86_BUILTIN_AESDECLAST128,
27700 IX86_BUILTIN_AESIMC128,
27701 IX86_BUILTIN_AESKEYGENASSIST128,
27703 /* PCLMUL instruction */
27704 IX86_BUILTIN_PCLMULQDQ128,
27706 /* AVX */
27707 IX86_BUILTIN_ADDPD256,
27708 IX86_BUILTIN_ADDPS256,
27709 IX86_BUILTIN_ADDSUBPD256,
27710 IX86_BUILTIN_ADDSUBPS256,
27711 IX86_BUILTIN_ANDPD256,
27712 IX86_BUILTIN_ANDPS256,
27713 IX86_BUILTIN_ANDNPD256,
27714 IX86_BUILTIN_ANDNPS256,
27715 IX86_BUILTIN_BLENDPD256,
27716 IX86_BUILTIN_BLENDPS256,
27717 IX86_BUILTIN_BLENDVPD256,
27718 IX86_BUILTIN_BLENDVPS256,
27719 IX86_BUILTIN_DIVPD256,
27720 IX86_BUILTIN_DIVPS256,
27721 IX86_BUILTIN_DPPS256,
27722 IX86_BUILTIN_HADDPD256,
27723 IX86_BUILTIN_HADDPS256,
27724 IX86_BUILTIN_HSUBPD256,
27725 IX86_BUILTIN_HSUBPS256,
27726 IX86_BUILTIN_MAXPD256,
27727 IX86_BUILTIN_MAXPS256,
27728 IX86_BUILTIN_MINPD256,
27729 IX86_BUILTIN_MINPS256,
27730 IX86_BUILTIN_MULPD256,
27731 IX86_BUILTIN_MULPS256,
27732 IX86_BUILTIN_ORPD256,
27733 IX86_BUILTIN_ORPS256,
27734 IX86_BUILTIN_SHUFPD256,
27735 IX86_BUILTIN_SHUFPS256,
27736 IX86_BUILTIN_SUBPD256,
27737 IX86_BUILTIN_SUBPS256,
27738 IX86_BUILTIN_XORPD256,
27739 IX86_BUILTIN_XORPS256,
27740 IX86_BUILTIN_CMPSD,
27741 IX86_BUILTIN_CMPSS,
27742 IX86_BUILTIN_CMPPD,
27743 IX86_BUILTIN_CMPPS,
27744 IX86_BUILTIN_CMPPD256,
27745 IX86_BUILTIN_CMPPS256,
27746 IX86_BUILTIN_CVTDQ2PD256,
27747 IX86_BUILTIN_CVTDQ2PS256,
27748 IX86_BUILTIN_CVTPD2PS256,
27749 IX86_BUILTIN_CVTPS2DQ256,
27750 IX86_BUILTIN_CVTPS2PD256,
27751 IX86_BUILTIN_CVTTPD2DQ256,
27752 IX86_BUILTIN_CVTPD2DQ256,
27753 IX86_BUILTIN_CVTTPS2DQ256,
27754 IX86_BUILTIN_EXTRACTF128PD256,
27755 IX86_BUILTIN_EXTRACTF128PS256,
27756 IX86_BUILTIN_EXTRACTF128SI256,
27757 IX86_BUILTIN_VZEROALL,
27758 IX86_BUILTIN_VZEROUPPER,
27759 IX86_BUILTIN_VPERMILVARPD,
27760 IX86_BUILTIN_VPERMILVARPS,
27761 IX86_BUILTIN_VPERMILVARPD256,
27762 IX86_BUILTIN_VPERMILVARPS256,
27763 IX86_BUILTIN_VPERMILPD,
27764 IX86_BUILTIN_VPERMILPS,
27765 IX86_BUILTIN_VPERMILPD256,
27766 IX86_BUILTIN_VPERMILPS256,
27767 IX86_BUILTIN_VPERMIL2PD,
27768 IX86_BUILTIN_VPERMIL2PS,
27769 IX86_BUILTIN_VPERMIL2PD256,
27770 IX86_BUILTIN_VPERMIL2PS256,
27771 IX86_BUILTIN_VPERM2F128PD256,
27772 IX86_BUILTIN_VPERM2F128PS256,
27773 IX86_BUILTIN_VPERM2F128SI256,
27774 IX86_BUILTIN_VBROADCASTSS,
27775 IX86_BUILTIN_VBROADCASTSD256,
27776 IX86_BUILTIN_VBROADCASTSS256,
27777 IX86_BUILTIN_VBROADCASTPD256,
27778 IX86_BUILTIN_VBROADCASTPS256,
27779 IX86_BUILTIN_VINSERTF128PD256,
27780 IX86_BUILTIN_VINSERTF128PS256,
27781 IX86_BUILTIN_VINSERTF128SI256,
27782 IX86_BUILTIN_LOADUPD256,
27783 IX86_BUILTIN_LOADUPS256,
27784 IX86_BUILTIN_STOREUPD256,
27785 IX86_BUILTIN_STOREUPS256,
27786 IX86_BUILTIN_LDDQU256,
27787 IX86_BUILTIN_MOVNTDQ256,
27788 IX86_BUILTIN_MOVNTPD256,
27789 IX86_BUILTIN_MOVNTPS256,
27790 IX86_BUILTIN_LOADDQU256,
27791 IX86_BUILTIN_STOREDQU256,
27792 IX86_BUILTIN_MASKLOADPD,
27793 IX86_BUILTIN_MASKLOADPS,
27794 IX86_BUILTIN_MASKSTOREPD,
27795 IX86_BUILTIN_MASKSTOREPS,
27796 IX86_BUILTIN_MASKLOADPD256,
27797 IX86_BUILTIN_MASKLOADPS256,
27798 IX86_BUILTIN_MASKSTOREPD256,
27799 IX86_BUILTIN_MASKSTOREPS256,
27800 IX86_BUILTIN_MOVSHDUP256,
27801 IX86_BUILTIN_MOVSLDUP256,
27802 IX86_BUILTIN_MOVDDUP256,
27804 IX86_BUILTIN_SQRTPD256,
27805 IX86_BUILTIN_SQRTPS256,
27806 IX86_BUILTIN_SQRTPS_NR256,
27807 IX86_BUILTIN_RSQRTPS256,
27808 IX86_BUILTIN_RSQRTPS_NR256,
27810 IX86_BUILTIN_RCPPS256,
27812 IX86_BUILTIN_ROUNDPD256,
27813 IX86_BUILTIN_ROUNDPS256,
27815 IX86_BUILTIN_FLOORPD256,
27816 IX86_BUILTIN_CEILPD256,
27817 IX86_BUILTIN_TRUNCPD256,
27818 IX86_BUILTIN_RINTPD256,
27819 IX86_BUILTIN_ROUNDPD_AZ256,
27821 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27822 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27823 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27825 IX86_BUILTIN_FLOORPS256,
27826 IX86_BUILTIN_CEILPS256,
27827 IX86_BUILTIN_TRUNCPS256,
27828 IX86_BUILTIN_RINTPS256,
27829 IX86_BUILTIN_ROUNDPS_AZ256,
27831 IX86_BUILTIN_FLOORPS_SFIX256,
27832 IX86_BUILTIN_CEILPS_SFIX256,
27833 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27835 IX86_BUILTIN_UNPCKHPD256,
27836 IX86_BUILTIN_UNPCKLPD256,
27837 IX86_BUILTIN_UNPCKHPS256,
27838 IX86_BUILTIN_UNPCKLPS256,
27840 IX86_BUILTIN_SI256_SI,
27841 IX86_BUILTIN_PS256_PS,
27842 IX86_BUILTIN_PD256_PD,
27843 IX86_BUILTIN_SI_SI256,
27844 IX86_BUILTIN_PS_PS256,
27845 IX86_BUILTIN_PD_PD256,
27847 IX86_BUILTIN_VTESTZPD,
27848 IX86_BUILTIN_VTESTCPD,
27849 IX86_BUILTIN_VTESTNZCPD,
27850 IX86_BUILTIN_VTESTZPS,
27851 IX86_BUILTIN_VTESTCPS,
27852 IX86_BUILTIN_VTESTNZCPS,
27853 IX86_BUILTIN_VTESTZPD256,
27854 IX86_BUILTIN_VTESTCPD256,
27855 IX86_BUILTIN_VTESTNZCPD256,
27856 IX86_BUILTIN_VTESTZPS256,
27857 IX86_BUILTIN_VTESTCPS256,
27858 IX86_BUILTIN_VTESTNZCPS256,
27859 IX86_BUILTIN_PTESTZ256,
27860 IX86_BUILTIN_PTESTC256,
27861 IX86_BUILTIN_PTESTNZC256,
27863 IX86_BUILTIN_MOVMSKPD256,
27864 IX86_BUILTIN_MOVMSKPS256,
27866 /* AVX2 */
27867 IX86_BUILTIN_MPSADBW256,
27868 IX86_BUILTIN_PABSB256,
27869 IX86_BUILTIN_PABSW256,
27870 IX86_BUILTIN_PABSD256,
27871 IX86_BUILTIN_PACKSSDW256,
27872 IX86_BUILTIN_PACKSSWB256,
27873 IX86_BUILTIN_PACKUSDW256,
27874 IX86_BUILTIN_PACKUSWB256,
27875 IX86_BUILTIN_PADDB256,
27876 IX86_BUILTIN_PADDW256,
27877 IX86_BUILTIN_PADDD256,
27878 IX86_BUILTIN_PADDQ256,
27879 IX86_BUILTIN_PADDSB256,
27880 IX86_BUILTIN_PADDSW256,
27881 IX86_BUILTIN_PADDUSB256,
27882 IX86_BUILTIN_PADDUSW256,
27883 IX86_BUILTIN_PALIGNR256,
27884 IX86_BUILTIN_AND256I,
27885 IX86_BUILTIN_ANDNOT256I,
27886 IX86_BUILTIN_PAVGB256,
27887 IX86_BUILTIN_PAVGW256,
27888 IX86_BUILTIN_PBLENDVB256,
27889 IX86_BUILTIN_PBLENDVW256,
27890 IX86_BUILTIN_PCMPEQB256,
27891 IX86_BUILTIN_PCMPEQW256,
27892 IX86_BUILTIN_PCMPEQD256,
27893 IX86_BUILTIN_PCMPEQQ256,
27894 IX86_BUILTIN_PCMPGTB256,
27895 IX86_BUILTIN_PCMPGTW256,
27896 IX86_BUILTIN_PCMPGTD256,
27897 IX86_BUILTIN_PCMPGTQ256,
27898 IX86_BUILTIN_PHADDW256,
27899 IX86_BUILTIN_PHADDD256,
27900 IX86_BUILTIN_PHADDSW256,
27901 IX86_BUILTIN_PHSUBW256,
27902 IX86_BUILTIN_PHSUBD256,
27903 IX86_BUILTIN_PHSUBSW256,
27904 IX86_BUILTIN_PMADDUBSW256,
27905 IX86_BUILTIN_PMADDWD256,
27906 IX86_BUILTIN_PMAXSB256,
27907 IX86_BUILTIN_PMAXSW256,
27908 IX86_BUILTIN_PMAXSD256,
27909 IX86_BUILTIN_PMAXUB256,
27910 IX86_BUILTIN_PMAXUW256,
27911 IX86_BUILTIN_PMAXUD256,
27912 IX86_BUILTIN_PMINSB256,
27913 IX86_BUILTIN_PMINSW256,
27914 IX86_BUILTIN_PMINSD256,
27915 IX86_BUILTIN_PMINUB256,
27916 IX86_BUILTIN_PMINUW256,
27917 IX86_BUILTIN_PMINUD256,
27918 IX86_BUILTIN_PMOVMSKB256,
27919 IX86_BUILTIN_PMOVSXBW256,
27920 IX86_BUILTIN_PMOVSXBD256,
27921 IX86_BUILTIN_PMOVSXBQ256,
27922 IX86_BUILTIN_PMOVSXWD256,
27923 IX86_BUILTIN_PMOVSXWQ256,
27924 IX86_BUILTIN_PMOVSXDQ256,
27925 IX86_BUILTIN_PMOVZXBW256,
27926 IX86_BUILTIN_PMOVZXBD256,
27927 IX86_BUILTIN_PMOVZXBQ256,
27928 IX86_BUILTIN_PMOVZXWD256,
27929 IX86_BUILTIN_PMOVZXWQ256,
27930 IX86_BUILTIN_PMOVZXDQ256,
27931 IX86_BUILTIN_PMULDQ256,
27932 IX86_BUILTIN_PMULHRSW256,
27933 IX86_BUILTIN_PMULHUW256,
27934 IX86_BUILTIN_PMULHW256,
27935 IX86_BUILTIN_PMULLW256,
27936 IX86_BUILTIN_PMULLD256,
27937 IX86_BUILTIN_PMULUDQ256,
27938 IX86_BUILTIN_POR256,
27939 IX86_BUILTIN_PSADBW256,
27940 IX86_BUILTIN_PSHUFB256,
27941 IX86_BUILTIN_PSHUFD256,
27942 IX86_BUILTIN_PSHUFHW256,
27943 IX86_BUILTIN_PSHUFLW256,
27944 IX86_BUILTIN_PSIGNB256,
27945 IX86_BUILTIN_PSIGNW256,
27946 IX86_BUILTIN_PSIGND256,
27947 IX86_BUILTIN_PSLLDQI256,
27948 IX86_BUILTIN_PSLLWI256,
27949 IX86_BUILTIN_PSLLW256,
27950 IX86_BUILTIN_PSLLDI256,
27951 IX86_BUILTIN_PSLLD256,
27952 IX86_BUILTIN_PSLLQI256,
27953 IX86_BUILTIN_PSLLQ256,
27954 IX86_BUILTIN_PSRAWI256,
27955 IX86_BUILTIN_PSRAW256,
27956 IX86_BUILTIN_PSRADI256,
27957 IX86_BUILTIN_PSRAD256,
27958 IX86_BUILTIN_PSRLDQI256,
27959 IX86_BUILTIN_PSRLWI256,
27960 IX86_BUILTIN_PSRLW256,
27961 IX86_BUILTIN_PSRLDI256,
27962 IX86_BUILTIN_PSRLD256,
27963 IX86_BUILTIN_PSRLQI256,
27964 IX86_BUILTIN_PSRLQ256,
27965 IX86_BUILTIN_PSUBB256,
27966 IX86_BUILTIN_PSUBW256,
27967 IX86_BUILTIN_PSUBD256,
27968 IX86_BUILTIN_PSUBQ256,
27969 IX86_BUILTIN_PSUBSB256,
27970 IX86_BUILTIN_PSUBSW256,
27971 IX86_BUILTIN_PSUBUSB256,
27972 IX86_BUILTIN_PSUBUSW256,
27973 IX86_BUILTIN_PUNPCKHBW256,
27974 IX86_BUILTIN_PUNPCKHWD256,
27975 IX86_BUILTIN_PUNPCKHDQ256,
27976 IX86_BUILTIN_PUNPCKHQDQ256,
27977 IX86_BUILTIN_PUNPCKLBW256,
27978 IX86_BUILTIN_PUNPCKLWD256,
27979 IX86_BUILTIN_PUNPCKLDQ256,
27980 IX86_BUILTIN_PUNPCKLQDQ256,
27981 IX86_BUILTIN_PXOR256,
27982 IX86_BUILTIN_MOVNTDQA256,
27983 IX86_BUILTIN_VBROADCASTSS_PS,
27984 IX86_BUILTIN_VBROADCASTSS_PS256,
27985 IX86_BUILTIN_VBROADCASTSD_PD256,
27986 IX86_BUILTIN_VBROADCASTSI256,
27987 IX86_BUILTIN_PBLENDD256,
27988 IX86_BUILTIN_PBLENDD128,
27989 IX86_BUILTIN_PBROADCASTB256,
27990 IX86_BUILTIN_PBROADCASTW256,
27991 IX86_BUILTIN_PBROADCASTD256,
27992 IX86_BUILTIN_PBROADCASTQ256,
27993 IX86_BUILTIN_PBROADCASTB128,
27994 IX86_BUILTIN_PBROADCASTW128,
27995 IX86_BUILTIN_PBROADCASTD128,
27996 IX86_BUILTIN_PBROADCASTQ128,
27997 IX86_BUILTIN_VPERMVARSI256,
27998 IX86_BUILTIN_VPERMDF256,
27999 IX86_BUILTIN_VPERMVARSF256,
28000 IX86_BUILTIN_VPERMDI256,
28001 IX86_BUILTIN_VPERMTI256,
28002 IX86_BUILTIN_VEXTRACT128I256,
28003 IX86_BUILTIN_VINSERT128I256,
28004 IX86_BUILTIN_MASKLOADD,
28005 IX86_BUILTIN_MASKLOADQ,
28006 IX86_BUILTIN_MASKLOADD256,
28007 IX86_BUILTIN_MASKLOADQ256,
28008 IX86_BUILTIN_MASKSTORED,
28009 IX86_BUILTIN_MASKSTOREQ,
28010 IX86_BUILTIN_MASKSTORED256,
28011 IX86_BUILTIN_MASKSTOREQ256,
28012 IX86_BUILTIN_PSLLVV4DI,
28013 IX86_BUILTIN_PSLLVV2DI,
28014 IX86_BUILTIN_PSLLVV8SI,
28015 IX86_BUILTIN_PSLLVV4SI,
28016 IX86_BUILTIN_PSRAVV8SI,
28017 IX86_BUILTIN_PSRAVV4SI,
28018 IX86_BUILTIN_PSRLVV4DI,
28019 IX86_BUILTIN_PSRLVV2DI,
28020 IX86_BUILTIN_PSRLVV8SI,
28021 IX86_BUILTIN_PSRLVV4SI,
28023 IX86_BUILTIN_GATHERSIV2DF,
28024 IX86_BUILTIN_GATHERSIV4DF,
28025 IX86_BUILTIN_GATHERDIV2DF,
28026 IX86_BUILTIN_GATHERDIV4DF,
28027 IX86_BUILTIN_GATHERSIV4SF,
28028 IX86_BUILTIN_GATHERSIV8SF,
28029 IX86_BUILTIN_GATHERDIV4SF,
28030 IX86_BUILTIN_GATHERDIV8SF,
28031 IX86_BUILTIN_GATHERSIV2DI,
28032 IX86_BUILTIN_GATHERSIV4DI,
28033 IX86_BUILTIN_GATHERDIV2DI,
28034 IX86_BUILTIN_GATHERDIV4DI,
28035 IX86_BUILTIN_GATHERSIV4SI,
28036 IX86_BUILTIN_GATHERSIV8SI,
28037 IX86_BUILTIN_GATHERDIV4SI,
28038 IX86_BUILTIN_GATHERDIV8SI,
28040 /* AVX512F */
28041 IX86_BUILTIN_ADDPD512,
28042 IX86_BUILTIN_ADDPS512,
28043 IX86_BUILTIN_ADDSD_ROUND,
28044 IX86_BUILTIN_ADDSS_ROUND,
28045 IX86_BUILTIN_ALIGND512,
28046 IX86_BUILTIN_ALIGNQ512,
28047 IX86_BUILTIN_BLENDMD512,
28048 IX86_BUILTIN_BLENDMPD512,
28049 IX86_BUILTIN_BLENDMPS512,
28050 IX86_BUILTIN_BLENDMQ512,
28051 IX86_BUILTIN_BROADCASTF32X4_512,
28052 IX86_BUILTIN_BROADCASTF64X4_512,
28053 IX86_BUILTIN_BROADCASTI32X4_512,
28054 IX86_BUILTIN_BROADCASTI64X4_512,
28055 IX86_BUILTIN_BROADCASTSD512,
28056 IX86_BUILTIN_BROADCASTSS512,
28057 IX86_BUILTIN_CMPD512,
28058 IX86_BUILTIN_CMPPD512,
28059 IX86_BUILTIN_CMPPS512,
28060 IX86_BUILTIN_CMPQ512,
28061 IX86_BUILTIN_CMPSD_MASK,
28062 IX86_BUILTIN_CMPSS_MASK,
28063 IX86_BUILTIN_COMIDF,
28064 IX86_BUILTIN_COMISF,
28065 IX86_BUILTIN_COMPRESSPD512,
28066 IX86_BUILTIN_COMPRESSPDSTORE512,
28067 IX86_BUILTIN_COMPRESSPS512,
28068 IX86_BUILTIN_COMPRESSPSSTORE512,
28069 IX86_BUILTIN_CVTDQ2PD512,
28070 IX86_BUILTIN_CVTDQ2PS512,
28071 IX86_BUILTIN_CVTPD2DQ512,
28072 IX86_BUILTIN_CVTPD2PS512,
28073 IX86_BUILTIN_CVTPD2UDQ512,
28074 IX86_BUILTIN_CVTPH2PS512,
28075 IX86_BUILTIN_CVTPS2DQ512,
28076 IX86_BUILTIN_CVTPS2PD512,
28077 IX86_BUILTIN_CVTPS2PH512,
28078 IX86_BUILTIN_CVTPS2UDQ512,
28079 IX86_BUILTIN_CVTSD2SS_ROUND,
28080 IX86_BUILTIN_CVTSI2SD64,
28081 IX86_BUILTIN_CVTSI2SS32,
28082 IX86_BUILTIN_CVTSI2SS64,
28083 IX86_BUILTIN_CVTSS2SD_ROUND,
28084 IX86_BUILTIN_CVTTPD2DQ512,
28085 IX86_BUILTIN_CVTTPD2UDQ512,
28086 IX86_BUILTIN_CVTTPS2DQ512,
28087 IX86_BUILTIN_CVTTPS2UDQ512,
28088 IX86_BUILTIN_CVTUDQ2PD512,
28089 IX86_BUILTIN_CVTUDQ2PS512,
28090 IX86_BUILTIN_CVTUSI2SD32,
28091 IX86_BUILTIN_CVTUSI2SD64,
28092 IX86_BUILTIN_CVTUSI2SS32,
28093 IX86_BUILTIN_CVTUSI2SS64,
28094 IX86_BUILTIN_DIVPD512,
28095 IX86_BUILTIN_DIVPS512,
28096 IX86_BUILTIN_DIVSD_ROUND,
28097 IX86_BUILTIN_DIVSS_ROUND,
28098 IX86_BUILTIN_EXPANDPD512,
28099 IX86_BUILTIN_EXPANDPD512Z,
28100 IX86_BUILTIN_EXPANDPDLOAD512,
28101 IX86_BUILTIN_EXPANDPDLOAD512Z,
28102 IX86_BUILTIN_EXPANDPS512,
28103 IX86_BUILTIN_EXPANDPS512Z,
28104 IX86_BUILTIN_EXPANDPSLOAD512,
28105 IX86_BUILTIN_EXPANDPSLOAD512Z,
28106 IX86_BUILTIN_EXTRACTF32X4,
28107 IX86_BUILTIN_EXTRACTF64X4,
28108 IX86_BUILTIN_EXTRACTI32X4,
28109 IX86_BUILTIN_EXTRACTI64X4,
28110 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28111 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28112 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28113 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28114 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28115 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28116 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28117 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28118 IX86_BUILTIN_GETEXPPD512,
28119 IX86_BUILTIN_GETEXPPS512,
28120 IX86_BUILTIN_GETEXPSD128,
28121 IX86_BUILTIN_GETEXPSS128,
28122 IX86_BUILTIN_GETMANTPD512,
28123 IX86_BUILTIN_GETMANTPS512,
28124 IX86_BUILTIN_GETMANTSD128,
28125 IX86_BUILTIN_GETMANTSS128,
28126 IX86_BUILTIN_INSERTF32X4,
28127 IX86_BUILTIN_INSERTF64X4,
28128 IX86_BUILTIN_INSERTI32X4,
28129 IX86_BUILTIN_INSERTI64X4,
28130 IX86_BUILTIN_LOADAPD512,
28131 IX86_BUILTIN_LOADAPS512,
28132 IX86_BUILTIN_LOADDQUDI512,
28133 IX86_BUILTIN_LOADDQUSI512,
28134 IX86_BUILTIN_LOADUPD512,
28135 IX86_BUILTIN_LOADUPS512,
28136 IX86_BUILTIN_MAXPD512,
28137 IX86_BUILTIN_MAXPS512,
28138 IX86_BUILTIN_MAXSD_ROUND,
28139 IX86_BUILTIN_MAXSS_ROUND,
28140 IX86_BUILTIN_MINPD512,
28141 IX86_BUILTIN_MINPS512,
28142 IX86_BUILTIN_MINSD_ROUND,
28143 IX86_BUILTIN_MINSS_ROUND,
28144 IX86_BUILTIN_MOVAPD512,
28145 IX86_BUILTIN_MOVAPS512,
28146 IX86_BUILTIN_MOVDDUP512,
28147 IX86_BUILTIN_MOVDQA32LOAD512,
28148 IX86_BUILTIN_MOVDQA32STORE512,
28149 IX86_BUILTIN_MOVDQA32_512,
28150 IX86_BUILTIN_MOVDQA64LOAD512,
28151 IX86_BUILTIN_MOVDQA64STORE512,
28152 IX86_BUILTIN_MOVDQA64_512,
28153 IX86_BUILTIN_MOVNTDQ512,
28154 IX86_BUILTIN_MOVNTDQA512,
28155 IX86_BUILTIN_MOVNTPD512,
28156 IX86_BUILTIN_MOVNTPS512,
28157 IX86_BUILTIN_MOVSHDUP512,
28158 IX86_BUILTIN_MOVSLDUP512,
28159 IX86_BUILTIN_MULPD512,
28160 IX86_BUILTIN_MULPS512,
28161 IX86_BUILTIN_MULSD_ROUND,
28162 IX86_BUILTIN_MULSS_ROUND,
28163 IX86_BUILTIN_PABSD512,
28164 IX86_BUILTIN_PABSQ512,
28165 IX86_BUILTIN_PADDD512,
28166 IX86_BUILTIN_PADDQ512,
28167 IX86_BUILTIN_PANDD512,
28168 IX86_BUILTIN_PANDND512,
28169 IX86_BUILTIN_PANDNQ512,
28170 IX86_BUILTIN_PANDQ512,
28171 IX86_BUILTIN_PBROADCASTD512,
28172 IX86_BUILTIN_PBROADCASTD512_GPR,
28173 IX86_BUILTIN_PBROADCASTMB512,
28174 IX86_BUILTIN_PBROADCASTMW512,
28175 IX86_BUILTIN_PBROADCASTQ512,
28176 IX86_BUILTIN_PBROADCASTQ512_GPR,
28177 IX86_BUILTIN_PBROADCASTQ512_MEM,
28178 IX86_BUILTIN_PCMPEQD512_MASK,
28179 IX86_BUILTIN_PCMPEQQ512_MASK,
28180 IX86_BUILTIN_PCMPGTD512_MASK,
28181 IX86_BUILTIN_PCMPGTQ512_MASK,
28182 IX86_BUILTIN_PCOMPRESSD512,
28183 IX86_BUILTIN_PCOMPRESSDSTORE512,
28184 IX86_BUILTIN_PCOMPRESSQ512,
28185 IX86_BUILTIN_PCOMPRESSQSTORE512,
28186 IX86_BUILTIN_PEXPANDD512,
28187 IX86_BUILTIN_PEXPANDD512Z,
28188 IX86_BUILTIN_PEXPANDDLOAD512,
28189 IX86_BUILTIN_PEXPANDDLOAD512Z,
28190 IX86_BUILTIN_PEXPANDQ512,
28191 IX86_BUILTIN_PEXPANDQ512Z,
28192 IX86_BUILTIN_PEXPANDQLOAD512,
28193 IX86_BUILTIN_PEXPANDQLOAD512Z,
28194 IX86_BUILTIN_PMAXSD512,
28195 IX86_BUILTIN_PMAXSQ512,
28196 IX86_BUILTIN_PMAXUD512,
28197 IX86_BUILTIN_PMAXUQ512,
28198 IX86_BUILTIN_PMINSD512,
28199 IX86_BUILTIN_PMINSQ512,
28200 IX86_BUILTIN_PMINUD512,
28201 IX86_BUILTIN_PMINUQ512,
28202 IX86_BUILTIN_PMOVDB512,
28203 IX86_BUILTIN_PMOVDB512_MEM,
28204 IX86_BUILTIN_PMOVDW512,
28205 IX86_BUILTIN_PMOVDW512_MEM,
28206 IX86_BUILTIN_PMOVQB512,
28207 IX86_BUILTIN_PMOVQB512_MEM,
28208 IX86_BUILTIN_PMOVQD512,
28209 IX86_BUILTIN_PMOVQD512_MEM,
28210 IX86_BUILTIN_PMOVQW512,
28211 IX86_BUILTIN_PMOVQW512_MEM,
28212 IX86_BUILTIN_PMOVSDB512,
28213 IX86_BUILTIN_PMOVSDB512_MEM,
28214 IX86_BUILTIN_PMOVSDW512,
28215 IX86_BUILTIN_PMOVSDW512_MEM,
28216 IX86_BUILTIN_PMOVSQB512,
28217 IX86_BUILTIN_PMOVSQB512_MEM,
28218 IX86_BUILTIN_PMOVSQD512,
28219 IX86_BUILTIN_PMOVSQD512_MEM,
28220 IX86_BUILTIN_PMOVSQW512,
28221 IX86_BUILTIN_PMOVSQW512_MEM,
28222 IX86_BUILTIN_PMOVSXBD512,
28223 IX86_BUILTIN_PMOVSXBQ512,
28224 IX86_BUILTIN_PMOVSXDQ512,
28225 IX86_BUILTIN_PMOVSXWD512,
28226 IX86_BUILTIN_PMOVSXWQ512,
28227 IX86_BUILTIN_PMOVUSDB512,
28228 IX86_BUILTIN_PMOVUSDB512_MEM,
28229 IX86_BUILTIN_PMOVUSDW512,
28230 IX86_BUILTIN_PMOVUSDW512_MEM,
28231 IX86_BUILTIN_PMOVUSQB512,
28232 IX86_BUILTIN_PMOVUSQB512_MEM,
28233 IX86_BUILTIN_PMOVUSQD512,
28234 IX86_BUILTIN_PMOVUSQD512_MEM,
28235 IX86_BUILTIN_PMOVUSQW512,
28236 IX86_BUILTIN_PMOVUSQW512_MEM,
28237 IX86_BUILTIN_PMOVZXBD512,
28238 IX86_BUILTIN_PMOVZXBQ512,
28239 IX86_BUILTIN_PMOVZXDQ512,
28240 IX86_BUILTIN_PMOVZXWD512,
28241 IX86_BUILTIN_PMOVZXWQ512,
28242 IX86_BUILTIN_PMULDQ512,
28243 IX86_BUILTIN_PMULLD512,
28244 IX86_BUILTIN_PMULUDQ512,
28245 IX86_BUILTIN_PORD512,
28246 IX86_BUILTIN_PORQ512,
28247 IX86_BUILTIN_PROLD512,
28248 IX86_BUILTIN_PROLQ512,
28249 IX86_BUILTIN_PROLVD512,
28250 IX86_BUILTIN_PROLVQ512,
28251 IX86_BUILTIN_PRORD512,
28252 IX86_BUILTIN_PRORQ512,
28253 IX86_BUILTIN_PRORVD512,
28254 IX86_BUILTIN_PRORVQ512,
28255 IX86_BUILTIN_PSHUFD512,
28256 IX86_BUILTIN_PSLLD512,
28257 IX86_BUILTIN_PSLLDI512,
28258 IX86_BUILTIN_PSLLQ512,
28259 IX86_BUILTIN_PSLLQI512,
28260 IX86_BUILTIN_PSLLVV16SI,
28261 IX86_BUILTIN_PSLLVV8DI,
28262 IX86_BUILTIN_PSRAD512,
28263 IX86_BUILTIN_PSRADI512,
28264 IX86_BUILTIN_PSRAQ512,
28265 IX86_BUILTIN_PSRAQI512,
28266 IX86_BUILTIN_PSRAVV16SI,
28267 IX86_BUILTIN_PSRAVV8DI,
28268 IX86_BUILTIN_PSRLD512,
28269 IX86_BUILTIN_PSRLDI512,
28270 IX86_BUILTIN_PSRLQ512,
28271 IX86_BUILTIN_PSRLQI512,
28272 IX86_BUILTIN_PSRLVV16SI,
28273 IX86_BUILTIN_PSRLVV8DI,
28274 IX86_BUILTIN_PSUBD512,
28275 IX86_BUILTIN_PSUBQ512,
28276 IX86_BUILTIN_PTESTMD512,
28277 IX86_BUILTIN_PTESTMQ512,
28278 IX86_BUILTIN_PTESTNMD512,
28279 IX86_BUILTIN_PTESTNMQ512,
28280 IX86_BUILTIN_PUNPCKHDQ512,
28281 IX86_BUILTIN_PUNPCKHQDQ512,
28282 IX86_BUILTIN_PUNPCKLDQ512,
28283 IX86_BUILTIN_PUNPCKLQDQ512,
28284 IX86_BUILTIN_PXORD512,
28285 IX86_BUILTIN_PXORQ512,
28286 IX86_BUILTIN_RCP14PD512,
28287 IX86_BUILTIN_RCP14PS512,
28288 IX86_BUILTIN_RCP14SD,
28289 IX86_BUILTIN_RCP14SS,
28290 IX86_BUILTIN_RNDSCALEPD,
28291 IX86_BUILTIN_RNDSCALEPS,
28292 IX86_BUILTIN_RNDSCALESD,
28293 IX86_BUILTIN_RNDSCALESS,
28294 IX86_BUILTIN_RSQRT14PD512,
28295 IX86_BUILTIN_RSQRT14PS512,
28296 IX86_BUILTIN_RSQRT14SD,
28297 IX86_BUILTIN_RSQRT14SS,
28298 IX86_BUILTIN_SCALEFPD512,
28299 IX86_BUILTIN_SCALEFPS512,
28300 IX86_BUILTIN_SCALEFSD,
28301 IX86_BUILTIN_SCALEFSS,
28302 IX86_BUILTIN_SHUFPD512,
28303 IX86_BUILTIN_SHUFPS512,
28304 IX86_BUILTIN_SHUF_F32x4,
28305 IX86_BUILTIN_SHUF_F64x2,
28306 IX86_BUILTIN_SHUF_I32x4,
28307 IX86_BUILTIN_SHUF_I64x2,
28308 IX86_BUILTIN_SQRTPD512,
28309 IX86_BUILTIN_SQRTPD512_MASK,
28310 IX86_BUILTIN_SQRTPS512_MASK,
28311 IX86_BUILTIN_SQRTPS_NR512,
28312 IX86_BUILTIN_SQRTSD_ROUND,
28313 IX86_BUILTIN_SQRTSS_ROUND,
28314 IX86_BUILTIN_STOREAPD512,
28315 IX86_BUILTIN_STOREAPS512,
28316 IX86_BUILTIN_STOREDQUDI512,
28317 IX86_BUILTIN_STOREDQUSI512,
28318 IX86_BUILTIN_STOREUPD512,
28319 IX86_BUILTIN_STOREUPS512,
28320 IX86_BUILTIN_SUBPD512,
28321 IX86_BUILTIN_SUBPS512,
28322 IX86_BUILTIN_SUBSD_ROUND,
28323 IX86_BUILTIN_SUBSS_ROUND,
28324 IX86_BUILTIN_UCMPD512,
28325 IX86_BUILTIN_UCMPQ512,
28326 IX86_BUILTIN_UNPCKHPD512,
28327 IX86_BUILTIN_UNPCKHPS512,
28328 IX86_BUILTIN_UNPCKLPD512,
28329 IX86_BUILTIN_UNPCKLPS512,
28330 IX86_BUILTIN_VCVTSD2SI32,
28331 IX86_BUILTIN_VCVTSD2SI64,
28332 IX86_BUILTIN_VCVTSD2USI32,
28333 IX86_BUILTIN_VCVTSD2USI64,
28334 IX86_BUILTIN_VCVTSS2SI32,
28335 IX86_BUILTIN_VCVTSS2SI64,
28336 IX86_BUILTIN_VCVTSS2USI32,
28337 IX86_BUILTIN_VCVTSS2USI64,
28338 IX86_BUILTIN_VCVTTSD2SI32,
28339 IX86_BUILTIN_VCVTTSD2SI64,
28340 IX86_BUILTIN_VCVTTSD2USI32,
28341 IX86_BUILTIN_VCVTTSD2USI64,
28342 IX86_BUILTIN_VCVTTSS2SI32,
28343 IX86_BUILTIN_VCVTTSS2SI64,
28344 IX86_BUILTIN_VCVTTSS2USI32,
28345 IX86_BUILTIN_VCVTTSS2USI64,
28346 IX86_BUILTIN_VFMADDPD512_MASK,
28347 IX86_BUILTIN_VFMADDPD512_MASK3,
28348 IX86_BUILTIN_VFMADDPD512_MASKZ,
28349 IX86_BUILTIN_VFMADDPS512_MASK,
28350 IX86_BUILTIN_VFMADDPS512_MASK3,
28351 IX86_BUILTIN_VFMADDPS512_MASKZ,
28352 IX86_BUILTIN_VFMADDSD3_ROUND,
28353 IX86_BUILTIN_VFMADDSS3_ROUND,
28354 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28355 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28356 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28357 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28358 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28359 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28360 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28361 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28362 IX86_BUILTIN_VFMSUBPD512_MASK3,
28363 IX86_BUILTIN_VFMSUBPS512_MASK3,
28364 IX86_BUILTIN_VFMSUBSD3_MASK3,
28365 IX86_BUILTIN_VFMSUBSS3_MASK3,
28366 IX86_BUILTIN_VFNMADDPD512_MASK,
28367 IX86_BUILTIN_VFNMADDPS512_MASK,
28368 IX86_BUILTIN_VFNMSUBPD512_MASK,
28369 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28370 IX86_BUILTIN_VFNMSUBPS512_MASK,
28371 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28372 IX86_BUILTIN_VPCLZCNTD512,
28373 IX86_BUILTIN_VPCLZCNTQ512,
28374 IX86_BUILTIN_VPCONFLICTD512,
28375 IX86_BUILTIN_VPCONFLICTQ512,
28376 IX86_BUILTIN_VPERMDF512,
28377 IX86_BUILTIN_VPERMDI512,
28378 IX86_BUILTIN_VPERMI2VARD512,
28379 IX86_BUILTIN_VPERMI2VARPD512,
28380 IX86_BUILTIN_VPERMI2VARPS512,
28381 IX86_BUILTIN_VPERMI2VARQ512,
28382 IX86_BUILTIN_VPERMILPD512,
28383 IX86_BUILTIN_VPERMILPS512,
28384 IX86_BUILTIN_VPERMILVARPD512,
28385 IX86_BUILTIN_VPERMILVARPS512,
28386 IX86_BUILTIN_VPERMT2VARD512,
28387 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28388 IX86_BUILTIN_VPERMT2VARPD512,
28389 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28390 IX86_BUILTIN_VPERMT2VARPS512,
28391 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28392 IX86_BUILTIN_VPERMT2VARQ512,
28393 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28394 IX86_BUILTIN_VPERMVARDF512,
28395 IX86_BUILTIN_VPERMVARDI512,
28396 IX86_BUILTIN_VPERMVARSF512,
28397 IX86_BUILTIN_VPERMVARSI512,
28398 IX86_BUILTIN_VTERNLOGD512_MASK,
28399 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28400 IX86_BUILTIN_VTERNLOGQ512_MASK,
28401 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28403 /* Mask arithmetic operations */
28404 IX86_BUILTIN_KAND16,
28405 IX86_BUILTIN_KANDN16,
28406 IX86_BUILTIN_KNOT16,
28407 IX86_BUILTIN_KOR16,
28408 IX86_BUILTIN_KORTESTC16,
28409 IX86_BUILTIN_KORTESTZ16,
28410 IX86_BUILTIN_KUNPCKBW,
28411 IX86_BUILTIN_KXNOR16,
28412 IX86_BUILTIN_KXOR16,
28413 IX86_BUILTIN_KMOV16,
28415 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28416 where all operands are 32-byte or 64-byte wide respectively. */
28417 IX86_BUILTIN_GATHERALTSIV4DF,
28418 IX86_BUILTIN_GATHERALTDIV8SF,
28419 IX86_BUILTIN_GATHERALTSIV4DI,
28420 IX86_BUILTIN_GATHERALTDIV8SI,
28421 IX86_BUILTIN_GATHER3ALTDIV16SF,
28422 IX86_BUILTIN_GATHER3ALTDIV16SI,
28423 IX86_BUILTIN_GATHER3ALTSIV8DF,
28424 IX86_BUILTIN_GATHER3ALTSIV8DI,
28425 IX86_BUILTIN_GATHER3DIV16SF,
28426 IX86_BUILTIN_GATHER3DIV16SI,
28427 IX86_BUILTIN_GATHER3DIV8DF,
28428 IX86_BUILTIN_GATHER3DIV8DI,
28429 IX86_BUILTIN_GATHER3SIV16SF,
28430 IX86_BUILTIN_GATHER3SIV16SI,
28431 IX86_BUILTIN_GATHER3SIV8DF,
28432 IX86_BUILTIN_GATHER3SIV8DI,
28433 IX86_BUILTIN_SCATTERDIV16SF,
28434 IX86_BUILTIN_SCATTERDIV16SI,
28435 IX86_BUILTIN_SCATTERDIV8DF,
28436 IX86_BUILTIN_SCATTERDIV8DI,
28437 IX86_BUILTIN_SCATTERSIV16SF,
28438 IX86_BUILTIN_SCATTERSIV16SI,
28439 IX86_BUILTIN_SCATTERSIV8DF,
28440 IX86_BUILTIN_SCATTERSIV8DI,
28442 /* AVX512PF */
28443 IX86_BUILTIN_GATHERPFQPD,
28444 IX86_BUILTIN_GATHERPFDPS,
28445 IX86_BUILTIN_GATHERPFDPD,
28446 IX86_BUILTIN_GATHERPFQPS,
28447 IX86_BUILTIN_SCATTERPFDPD,
28448 IX86_BUILTIN_SCATTERPFDPS,
28449 IX86_BUILTIN_SCATTERPFQPD,
28450 IX86_BUILTIN_SCATTERPFQPS,
28452 /* AVX-512ER */
28453 IX86_BUILTIN_EXP2PD_MASK,
28454 IX86_BUILTIN_EXP2PS_MASK,
28455 IX86_BUILTIN_EXP2PS,
28456 IX86_BUILTIN_RCP28PD,
28457 IX86_BUILTIN_RCP28PS,
28458 IX86_BUILTIN_RCP28SD,
28459 IX86_BUILTIN_RCP28SS,
28460 IX86_BUILTIN_RSQRT28PD,
28461 IX86_BUILTIN_RSQRT28PS,
28462 IX86_BUILTIN_RSQRT28SD,
28463 IX86_BUILTIN_RSQRT28SS,
28465 /* SHA builtins. */
28466 IX86_BUILTIN_SHA1MSG1,
28467 IX86_BUILTIN_SHA1MSG2,
28468 IX86_BUILTIN_SHA1NEXTE,
28469 IX86_BUILTIN_SHA1RNDS4,
28470 IX86_BUILTIN_SHA256MSG1,
28471 IX86_BUILTIN_SHA256MSG2,
28472 IX86_BUILTIN_SHA256RNDS2,
28474 /* TFmode support builtins. */
28475 IX86_BUILTIN_INFQ,
28476 IX86_BUILTIN_HUGE_VALQ,
28477 IX86_BUILTIN_FABSQ,
28478 IX86_BUILTIN_COPYSIGNQ,
28480 /* Vectorizer support builtins. */
28481 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28482 IX86_BUILTIN_CPYSGNPS,
28483 IX86_BUILTIN_CPYSGNPD,
28484 IX86_BUILTIN_CPYSGNPS256,
28485 IX86_BUILTIN_CPYSGNPS512,
28486 IX86_BUILTIN_CPYSGNPD256,
28487 IX86_BUILTIN_CPYSGNPD512,
28488 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28489 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28492 /* FMA4 instructions. */
28493 IX86_BUILTIN_VFMADDSS,
28494 IX86_BUILTIN_VFMADDSD,
28495 IX86_BUILTIN_VFMADDPS,
28496 IX86_BUILTIN_VFMADDPD,
28497 IX86_BUILTIN_VFMADDPS256,
28498 IX86_BUILTIN_VFMADDPD256,
28499 IX86_BUILTIN_VFMADDSUBPS,
28500 IX86_BUILTIN_VFMADDSUBPD,
28501 IX86_BUILTIN_VFMADDSUBPS256,
28502 IX86_BUILTIN_VFMADDSUBPD256,
28504 /* FMA3 instructions. */
28505 IX86_BUILTIN_VFMADDSS3,
28506 IX86_BUILTIN_VFMADDSD3,
28508 /* XOP instructions. */
28509 IX86_BUILTIN_VPCMOV,
28510 IX86_BUILTIN_VPCMOV_V2DI,
28511 IX86_BUILTIN_VPCMOV_V4SI,
28512 IX86_BUILTIN_VPCMOV_V8HI,
28513 IX86_BUILTIN_VPCMOV_V16QI,
28514 IX86_BUILTIN_VPCMOV_V4SF,
28515 IX86_BUILTIN_VPCMOV_V2DF,
28516 IX86_BUILTIN_VPCMOV256,
28517 IX86_BUILTIN_VPCMOV_V4DI256,
28518 IX86_BUILTIN_VPCMOV_V8SI256,
28519 IX86_BUILTIN_VPCMOV_V16HI256,
28520 IX86_BUILTIN_VPCMOV_V32QI256,
28521 IX86_BUILTIN_VPCMOV_V8SF256,
28522 IX86_BUILTIN_VPCMOV_V4DF256,
28524 IX86_BUILTIN_VPPERM,
28526 IX86_BUILTIN_VPMACSSWW,
28527 IX86_BUILTIN_VPMACSWW,
28528 IX86_BUILTIN_VPMACSSWD,
28529 IX86_BUILTIN_VPMACSWD,
28530 IX86_BUILTIN_VPMACSSDD,
28531 IX86_BUILTIN_VPMACSDD,
28532 IX86_BUILTIN_VPMACSSDQL,
28533 IX86_BUILTIN_VPMACSSDQH,
28534 IX86_BUILTIN_VPMACSDQL,
28535 IX86_BUILTIN_VPMACSDQH,
28536 IX86_BUILTIN_VPMADCSSWD,
28537 IX86_BUILTIN_VPMADCSWD,
28539 IX86_BUILTIN_VPHADDBW,
28540 IX86_BUILTIN_VPHADDBD,
28541 IX86_BUILTIN_VPHADDBQ,
28542 IX86_BUILTIN_VPHADDWD,
28543 IX86_BUILTIN_VPHADDWQ,
28544 IX86_BUILTIN_VPHADDDQ,
28545 IX86_BUILTIN_VPHADDUBW,
28546 IX86_BUILTIN_VPHADDUBD,
28547 IX86_BUILTIN_VPHADDUBQ,
28548 IX86_BUILTIN_VPHADDUWD,
28549 IX86_BUILTIN_VPHADDUWQ,
28550 IX86_BUILTIN_VPHADDUDQ,
28551 IX86_BUILTIN_VPHSUBBW,
28552 IX86_BUILTIN_VPHSUBWD,
28553 IX86_BUILTIN_VPHSUBDQ,
28555 IX86_BUILTIN_VPROTB,
28556 IX86_BUILTIN_VPROTW,
28557 IX86_BUILTIN_VPROTD,
28558 IX86_BUILTIN_VPROTQ,
28559 IX86_BUILTIN_VPROTB_IMM,
28560 IX86_BUILTIN_VPROTW_IMM,
28561 IX86_BUILTIN_VPROTD_IMM,
28562 IX86_BUILTIN_VPROTQ_IMM,
28564 IX86_BUILTIN_VPSHLB,
28565 IX86_BUILTIN_VPSHLW,
28566 IX86_BUILTIN_VPSHLD,
28567 IX86_BUILTIN_VPSHLQ,
28568 IX86_BUILTIN_VPSHAB,
28569 IX86_BUILTIN_VPSHAW,
28570 IX86_BUILTIN_VPSHAD,
28571 IX86_BUILTIN_VPSHAQ,
28573 IX86_BUILTIN_VFRCZSS,
28574 IX86_BUILTIN_VFRCZSD,
28575 IX86_BUILTIN_VFRCZPS,
28576 IX86_BUILTIN_VFRCZPD,
28577 IX86_BUILTIN_VFRCZPS256,
28578 IX86_BUILTIN_VFRCZPD256,
28580 IX86_BUILTIN_VPCOMEQUB,
28581 IX86_BUILTIN_VPCOMNEUB,
28582 IX86_BUILTIN_VPCOMLTUB,
28583 IX86_BUILTIN_VPCOMLEUB,
28584 IX86_BUILTIN_VPCOMGTUB,
28585 IX86_BUILTIN_VPCOMGEUB,
28586 IX86_BUILTIN_VPCOMFALSEUB,
28587 IX86_BUILTIN_VPCOMTRUEUB,
28589 IX86_BUILTIN_VPCOMEQUW,
28590 IX86_BUILTIN_VPCOMNEUW,
28591 IX86_BUILTIN_VPCOMLTUW,
28592 IX86_BUILTIN_VPCOMLEUW,
28593 IX86_BUILTIN_VPCOMGTUW,
28594 IX86_BUILTIN_VPCOMGEUW,
28595 IX86_BUILTIN_VPCOMFALSEUW,
28596 IX86_BUILTIN_VPCOMTRUEUW,
28598 IX86_BUILTIN_VPCOMEQUD,
28599 IX86_BUILTIN_VPCOMNEUD,
28600 IX86_BUILTIN_VPCOMLTUD,
28601 IX86_BUILTIN_VPCOMLEUD,
28602 IX86_BUILTIN_VPCOMGTUD,
28603 IX86_BUILTIN_VPCOMGEUD,
28604 IX86_BUILTIN_VPCOMFALSEUD,
28605 IX86_BUILTIN_VPCOMTRUEUD,
28607 IX86_BUILTIN_VPCOMEQUQ,
28608 IX86_BUILTIN_VPCOMNEUQ,
28609 IX86_BUILTIN_VPCOMLTUQ,
28610 IX86_BUILTIN_VPCOMLEUQ,
28611 IX86_BUILTIN_VPCOMGTUQ,
28612 IX86_BUILTIN_VPCOMGEUQ,
28613 IX86_BUILTIN_VPCOMFALSEUQ,
28614 IX86_BUILTIN_VPCOMTRUEUQ,
28616 IX86_BUILTIN_VPCOMEQB,
28617 IX86_BUILTIN_VPCOMNEB,
28618 IX86_BUILTIN_VPCOMLTB,
28619 IX86_BUILTIN_VPCOMLEB,
28620 IX86_BUILTIN_VPCOMGTB,
28621 IX86_BUILTIN_VPCOMGEB,
28622 IX86_BUILTIN_VPCOMFALSEB,
28623 IX86_BUILTIN_VPCOMTRUEB,
28625 IX86_BUILTIN_VPCOMEQW,
28626 IX86_BUILTIN_VPCOMNEW,
28627 IX86_BUILTIN_VPCOMLTW,
28628 IX86_BUILTIN_VPCOMLEW,
28629 IX86_BUILTIN_VPCOMGTW,
28630 IX86_BUILTIN_VPCOMGEW,
28631 IX86_BUILTIN_VPCOMFALSEW,
28632 IX86_BUILTIN_VPCOMTRUEW,
28634 IX86_BUILTIN_VPCOMEQD,
28635 IX86_BUILTIN_VPCOMNED,
28636 IX86_BUILTIN_VPCOMLTD,
28637 IX86_BUILTIN_VPCOMLED,
28638 IX86_BUILTIN_VPCOMGTD,
28639 IX86_BUILTIN_VPCOMGED,
28640 IX86_BUILTIN_VPCOMFALSED,
28641 IX86_BUILTIN_VPCOMTRUED,
28643 IX86_BUILTIN_VPCOMEQQ,
28644 IX86_BUILTIN_VPCOMNEQ,
28645 IX86_BUILTIN_VPCOMLTQ,
28646 IX86_BUILTIN_VPCOMLEQ,
28647 IX86_BUILTIN_VPCOMGTQ,
28648 IX86_BUILTIN_VPCOMGEQ,
28649 IX86_BUILTIN_VPCOMFALSEQ,
28650 IX86_BUILTIN_VPCOMTRUEQ,
28652 /* LWP instructions. */
28653 IX86_BUILTIN_LLWPCB,
28654 IX86_BUILTIN_SLWPCB,
28655 IX86_BUILTIN_LWPVAL32,
28656 IX86_BUILTIN_LWPVAL64,
28657 IX86_BUILTIN_LWPINS32,
28658 IX86_BUILTIN_LWPINS64,
28660 IX86_BUILTIN_CLZS,
28662 /* RTM */
28663 IX86_BUILTIN_XBEGIN,
28664 IX86_BUILTIN_XEND,
28665 IX86_BUILTIN_XABORT,
28666 IX86_BUILTIN_XTEST,
28668 /* BMI instructions. */
28669 IX86_BUILTIN_BEXTR32,
28670 IX86_BUILTIN_BEXTR64,
28671 IX86_BUILTIN_CTZS,
28673 /* TBM instructions. */
28674 IX86_BUILTIN_BEXTRI32,
28675 IX86_BUILTIN_BEXTRI64,
28677 /* BMI2 instructions. */
28678 IX86_BUILTIN_BZHI32,
28679 IX86_BUILTIN_BZHI64,
28680 IX86_BUILTIN_PDEP32,
28681 IX86_BUILTIN_PDEP64,
28682 IX86_BUILTIN_PEXT32,
28683 IX86_BUILTIN_PEXT64,
28685 /* ADX instructions. */
28686 IX86_BUILTIN_ADDCARRYX32,
28687 IX86_BUILTIN_ADDCARRYX64,
28689 /* FSGSBASE instructions. */
28690 IX86_BUILTIN_RDFSBASE32,
28691 IX86_BUILTIN_RDFSBASE64,
28692 IX86_BUILTIN_RDGSBASE32,
28693 IX86_BUILTIN_RDGSBASE64,
28694 IX86_BUILTIN_WRFSBASE32,
28695 IX86_BUILTIN_WRFSBASE64,
28696 IX86_BUILTIN_WRGSBASE32,
28697 IX86_BUILTIN_WRGSBASE64,
28699 /* RDRND instructions. */
28700 IX86_BUILTIN_RDRAND16_STEP,
28701 IX86_BUILTIN_RDRAND32_STEP,
28702 IX86_BUILTIN_RDRAND64_STEP,
28704 /* RDSEED instructions. */
28705 IX86_BUILTIN_RDSEED16_STEP,
28706 IX86_BUILTIN_RDSEED32_STEP,
28707 IX86_BUILTIN_RDSEED64_STEP,
28709 /* F16C instructions. */
28710 IX86_BUILTIN_CVTPH2PS,
28711 IX86_BUILTIN_CVTPH2PS256,
28712 IX86_BUILTIN_CVTPS2PH,
28713 IX86_BUILTIN_CVTPS2PH256,
28715 /* CFString built-in for darwin */
28716 IX86_BUILTIN_CFSTRING,
28718 /* Builtins to get CPU type and supported features. */
28719 IX86_BUILTIN_CPU_INIT,
28720 IX86_BUILTIN_CPU_IS,
28721 IX86_BUILTIN_CPU_SUPPORTS,
28723 /* Read/write FLAGS register built-ins. */
28724 IX86_BUILTIN_READ_FLAGS,
28725 IX86_BUILTIN_WRITE_FLAGS,
28727 IX86_BUILTIN_MAX
28728 };
28730 /* Table for the ix86 builtin decls. */
28733 /* Table of all of the builtin functions that are possible with different ISA's
28734 but are waiting to be built until a function is declared to use that
28735 ISA. */
28742 };
28747 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28748 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28749 function decl in the ix86_builtins array. Returns the function decl or
28750 NULL_TREE, if the builtin was not added.
28752 If the front end has a special hook for builtin functions, delay adding
28753 builtin functions that aren't in the current ISA until the ISA is changed
28754 with function specific optimization. Doing so, can save about 300K for the
28755 default compiler. When the builtin is expanded, check at that time whether
28756 it is valid.
28758 If the front end doesn't have a special hook, record all builtins, even if
28759 it isn't an instruction set in the current ISA in case the user uses
28760 function specific options for a different ISA, so that we don't get scope
28761 errors if a builtin is added in the middle of a function scope. */
28767 {
28771 {
28780 {
28786 }
28787 else
28788 {
28794 }
28795 }
28798 }
28800 /* Like def_builtin, but also marks the function decl "const". */
28805 {
28809 else
28813 }
28815 /* Add any new builtin functions for a given ISA that may not have been
28816 declared. This saves a bit of space compared to adding all of the
28817 declarations to the tree, even if we didn't use them. */
28819 static void
28821 {
28825 {
28828 {
28831 /* Don't define the builtin again. */
28837 NULL_TREE);
28842 }
28843 }
28844 }
28846 /* Bits for builtin_description.flag. */
28848 /* Set when we don't support the comparison natively, and should
28849 swap_comparison in order to support it. */
28850 #define BUILTIN_DESC_SWAP_OPERANDS 1
28852 struct builtin_description
28853 {
28860 };
28863 {
28864 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28865 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28866 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28867 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28868 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28869 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28870 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28874 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28876 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28878 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28879 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28880 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28881 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
28886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
28887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
28888 };
28891 {
28892 /* SSE4.2 */
28893 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
28894 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
28895 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
28896 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
28897 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
28898 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
28899 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
28900 };
28903 {
28904 /* SSE4.2 */
28905 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
28906 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
28907 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
28908 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
28909 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
28910 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
28911 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
28912 };
28914 /* Special builtins with variable number of arguments. */
28916 {
28917 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
28918 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
28919 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
28921 /* 80387 (for use internally for atomic compound assignment). */
28922 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
28923 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
28924 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
28925 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
28927 /* MMX */
28928 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28930 /* 3DNow! */
28931 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28933 /* FXSR, XSAVE and XSAVEOPT */
28934 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
28935 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
28936 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28937 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28938 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28940 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28941 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28942 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28943 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28944 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28946 /* SSE */
28947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28949 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28956 /* SSE or 3DNow!A */
28957 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28958 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
28960 /* SSE2 */
28961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
28965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
28967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
28968 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
28969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
28970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
28972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
28973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
28975 /* SSE3 */
28976 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
28978 /* SSE4.1 */
28979 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
28981 /* SSE4A */
28982 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28983 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28985 /* AVX */
28986 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
28987 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
28989 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28990 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
28991 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
28992 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
28993 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
28995 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
28996 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
28997 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
28998 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
28999 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29007 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29013 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29016 /* AVX2 */
29017 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29018 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29019 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29020 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29021 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29022 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29023 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29024 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29025 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29027 /* AVX512F */
29028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29076 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29077 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29078 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29079 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29080 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29081 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29083 /* FSGSBASE */
29084 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29085 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29086 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29087 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29088 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29089 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29090 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29091 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29093 /* RTM */
29094 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29095 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29096 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29097 };
29099 /* Builtins with variable number of arguments. */
29101 {
29102 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29103 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29104 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29105 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29106 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29107 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29108 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29110 /* MMX */
29111 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29112 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29113 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29114 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29136 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29157 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29159 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29163 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29166 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29174 /* 3DNow! */
29175 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29176 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29177 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29178 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29180 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29181 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29182 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29183 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29184 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29186 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29188 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29189 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29196 /* 3DNow!A */
29197 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29198 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29199 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29200 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29201 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29202 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29204 /* SSE */
29205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29206 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29207 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29209 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29213 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29216 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29220 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29221 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29222 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29226 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29250 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29251 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29255 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29257 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29258 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29260 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29262 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29263 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29264 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29265 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29266 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29268 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29270 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29272 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29275 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29276 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29278 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29279 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29281 /* SSE MMX or 3Dnow!A */
29282 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29283 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29284 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29286 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29287 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29288 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29291 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29292 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29294 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29296 /* SSE2 */
29297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29303 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29315 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29316 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29320 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29322 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29323 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29324 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29325 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29353 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29357 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29359 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29360 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29362 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29365 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29366 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29368 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29370 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29371 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29372 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29373 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29374 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29375 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29376 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29377 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29388 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29389 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29391 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29393 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29394 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29406 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29407 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29408 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29412 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29415 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29416 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29417 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29418 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29424 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29428 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29433 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29438 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29439 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29440 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29441 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29443 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29454 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29464 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29466 /* SSE2 MMX */
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29468 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29470 /* SSE3 */
29471 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29472 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29474 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29475 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29476 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29477 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29478 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29479 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29481 /* SSSE3 */
29482 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29483 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29484 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29485 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29486 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29514 /* SSSE3. */
29515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29518 /* SSE4.1 */
29519 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29520 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29521 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29522 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29523 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29525 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29548 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29557 /* SSE4.1 */
29558 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29559 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29560 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29561 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29563 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29564 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29565 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29566 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29569 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29571 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29572 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29574 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29575 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29576 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29577 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29579 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29580 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29582 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29583 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29585 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29586 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29587 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29589 /* SSE4.2 */
29590 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29591 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29592 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29593 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29594 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29596 /* SSE4A */
29597 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29598 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29599 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29600 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29602 /* AES */
29603 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29604 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29606 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29607 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29608 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29609 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29611 /* PCLMUL */
29612 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29614 /* AVX */
29615 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29616 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29619 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29620 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29623 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29629 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29630 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29631 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29632 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29633 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29634 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29635 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29636 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29637 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29638 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29639 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29640 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29663 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29664 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29668 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29670 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29673 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29675 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29686 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29688 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29690 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29695 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29702 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29703 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29716 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29717 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29727 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29728 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29753 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29755 /* AVX2 */
29756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29757 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29758 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29759 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29764 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29765 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29766 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29767 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29773 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29795 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29796 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29797 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29798 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29799 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29800 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29801 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29802 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29803 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29804 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29805 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29806 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29807 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29808 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29809 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29810 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29811 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29820 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29822 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29823 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29824 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29825 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29826 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29827 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29828 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29829 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29830 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29831 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29832 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29833 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29834 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29835 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29837 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29838 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29839 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29840 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29841 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29842 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29843 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29844 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29845 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29846 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29847 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29848 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29849 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29850 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29851 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29852 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29853 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29854 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29855 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29856 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29857 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29858 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29859 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29903 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29905 /* BMI */
29906 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29907 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29908 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29910 /* TBM */
29911 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29912 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29914 /* F16C */
29915 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
29916 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
29917 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
29918 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
29920 /* BMI2 */
29921 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29922 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29923 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29924 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29925 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29926 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29928 /* AVX512F */
29929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
29930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
29931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
29937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
29939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
29940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
29942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
29943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
29947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
29949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
29954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
29955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
29956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
29957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
29958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
29959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
29960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
29961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
29978 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
29979 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
29980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
29981 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
29982 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
29983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
29984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
29985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
29986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
29987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30062 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30063 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30090 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30091 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30092 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30093 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30125 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30130 /* Mask arithmetic operations */
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30142 /* SHA */
30143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30150 };
30152 /* Builtins with rounding support. */
30154 {
30155 /* AVX512F */
30156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30175 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30177 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30184 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30186 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30236 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30238 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30240 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30242 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30244 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30246 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30248 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30250 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30276 /* AVX512ER */
30277 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30278 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30279 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30280 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30281 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30282 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30283 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30284 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30285 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30286 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30287 };
30289 /* FMA4 and XOP. */
30290 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30291 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30292 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30293 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30294 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30295 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30296 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30297 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30298 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30299 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30300 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30301 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30302 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30303 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30304 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30305 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30306 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30307 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30308 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30309 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30310 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30311 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30312 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30313 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30314 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30315 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30316 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30317 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30318 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30319 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30320 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30321 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30322 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30323 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30324 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30325 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30326 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30327 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30328 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30329 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30330 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30331 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30332 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30333 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30334 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30335 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30336 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30337 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30338 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30339 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30340 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30341 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30344 {
30385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30543 };
30544 \f
30545 /* TM vector builtins. */
30547 /* Reuse the existing x86-specific `struct builtin_description' cause
30548 we're lazy. Add casts to make them fit. */
30550 {
30551 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30552 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30553 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30554 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30555 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30556 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30557 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30559 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30560 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30561 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30562 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30563 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30564 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30565 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30567 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30568 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30569 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30570 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30571 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30572 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30573 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30575 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30576 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30577 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30578 };
30580 /* TM callbacks. */
30582 /* Return the builtin decl needed to load a vector of TYPE. */
30584 static tree
30586 {
30588 {
30590 {
30597 }
30598 }
30600 }
30602 /* Return the builtin decl needed to store a vector of TYPE. */
30604 static tree
30606 {
30608 {
30610 {
30617 }
30618 }
30620 }
30621 \f
30622 /* Initialize the transactional memory vector load/store builtins. */
30624 static void
30626 {
30630 tree decl;
30637 /* If there are no builtins defined, we must be compiling in a
30638 language without trans-mem support. */
30642 /* Use whatever attributes a normal TM load has. */
30646 /* Use whatever attributes a normal TM store has. */
30650 /* Use whatever attributes a normal TM log has. */
30658 {
30662 {
30670 {
30673 }
30675 {
30678 }
30679 else
30680 {
30683 }
30685 /* The builtin without the prefix for
30686 calling it directly. */
30688 attrs);
30689 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30690 set the TYPE_ATTRIBUTES. */
30694 }
30695 }
30696 }
30698 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30699 in the current target ISA to allow the user to compile particular modules
30700 with different target specific options that differ from the command line
30701 options. */
30702 static void
30704 {
30709 /* Add all special builtins with variable number of operands. */
30713 {
30719 }
30721 /* Add all builtins with variable number of operands. */
30725 {
30731 }
30733 /* Add all builtins with rounding. */
30737 {
30743 }
30745 /* pcmpestr[im] insns. */
30749 {
30752 else
30755 }
30757 /* pcmpistr[im] insns. */
30761 {
30764 else
30767 }
30769 /* comi/ucomi insns. */
30771 {
30774 else
30777 }
30779 /* SSE */
30785 /* SSE or 3DNow!A */
30788 IX86_BUILTIN_MASKMOVQ);
30790 /* SSE2 */
30799 /* SSE3. */
30805 /* AES */
30819 /* PCLMUL */
30823 /* RDRND */
30830 IX86_BUILTIN_RDRAND64_STEP);
30832 /* AVX2 */
30834 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30835 IX86_BUILTIN_GATHERSIV2DF);
30838 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30839 IX86_BUILTIN_GATHERSIV4DF);
30842 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30843 IX86_BUILTIN_GATHERDIV2DF);
30846 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30847 IX86_BUILTIN_GATHERDIV4DF);
30850 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30851 IX86_BUILTIN_GATHERSIV4SF);
30854 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30855 IX86_BUILTIN_GATHERSIV8SF);
30858 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30859 IX86_BUILTIN_GATHERDIV4SF);
30862 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30863 IX86_BUILTIN_GATHERDIV8SF);
30866 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30867 IX86_BUILTIN_GATHERSIV2DI);
30870 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30871 IX86_BUILTIN_GATHERSIV4DI);
30874 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30875 IX86_BUILTIN_GATHERDIV2DI);
30878 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30879 IX86_BUILTIN_GATHERDIV4DI);
30882 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30883 IX86_BUILTIN_GATHERSIV4SI);
30886 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
30887 IX86_BUILTIN_GATHERSIV8SI);
30890 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
30891 IX86_BUILTIN_GATHERDIV4SI);
30894 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
30895 IX86_BUILTIN_GATHERDIV8SI);
30898 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
30899 IX86_BUILTIN_GATHERALTSIV4DF);
30902 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
30903 IX86_BUILTIN_GATHERALTDIV8SF);
30906 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
30907 IX86_BUILTIN_GATHERALTSIV4DI);
30910 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
30911 IX86_BUILTIN_GATHERALTDIV8SI);
30913 /* AVX512F */
30915 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
30916 IX86_BUILTIN_GATHER3SIV16SF);
30919 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
30920 IX86_BUILTIN_GATHER3SIV8DF);
30923 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
30924 IX86_BUILTIN_GATHER3DIV16SF);
30927 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
30928 IX86_BUILTIN_GATHER3DIV8DF);
30931 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
30932 IX86_BUILTIN_GATHER3SIV16SI);
30935 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
30936 IX86_BUILTIN_GATHER3SIV8DI);
30939 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
30940 IX86_BUILTIN_GATHER3DIV16SI);
30943 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
30944 IX86_BUILTIN_GATHER3DIV8DI);
30947 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
30948 IX86_BUILTIN_GATHER3ALTSIV8DF);
30951 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
30952 IX86_BUILTIN_GATHER3ALTDIV16SF);
30955 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
30956 IX86_BUILTIN_GATHER3ALTSIV8DI);
30959 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
30960 IX86_BUILTIN_GATHER3ALTDIV16SI);
30963 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
30964 IX86_BUILTIN_SCATTERSIV16SF);
30967 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
30968 IX86_BUILTIN_SCATTERSIV8DF);
30971 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
30972 IX86_BUILTIN_SCATTERDIV16SF);
30975 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
30976 IX86_BUILTIN_SCATTERDIV8DF);
30979 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
30980 IX86_BUILTIN_SCATTERSIV16SI);
30983 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
30984 IX86_BUILTIN_SCATTERSIV8DI);
30987 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
30988 IX86_BUILTIN_SCATTERDIV16SI);
30991 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
30992 IX86_BUILTIN_SCATTERDIV8DI);
30994 /* AVX512PF */
30996 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
30997 IX86_BUILTIN_GATHERPFDPD);
30999 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31000 IX86_BUILTIN_GATHERPFDPS);
31002 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31003 IX86_BUILTIN_GATHERPFQPD);
31005 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31006 IX86_BUILTIN_GATHERPFQPS);
31008 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31009 IX86_BUILTIN_SCATTERPFDPD);
31011 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31012 IX86_BUILTIN_SCATTERPFDPS);
31014 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31015 IX86_BUILTIN_SCATTERPFQPD);
31017 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31018 IX86_BUILTIN_SCATTERPFQPS);
31020 /* SHA */
31036 /* RTM. */
31040 /* MMX access to the vec_init patterns. */
31045 V4HI_FTYPE_HI_HI_HI_HI,
31046 IX86_BUILTIN_VEC_INIT_V4HI);
31049 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31050 IX86_BUILTIN_VEC_INIT_V8QI);
31052 /* Access to the vec_extract patterns. */
31074 /* Access to the vec_set patterns. */
31095 /* RDSEED */
31104 /* ADCX */
31109 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31110 IX86_BUILTIN_ADDCARRYX64);
31112 /* Read/write FLAGS. */
31123 /* Add FMA4 multi-arg argument instructions */
31125 {
31131 }
31132 }
31134 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31135 to return a pointer to VERSION_DECL if the outcome of the expression
31136 formed by PREDICATE_CHAIN is true. This function will be called during
31137 version dispatch to decide which function version to execute. It returns
31138 the basic block at the end, to which more conditions can be added. */
31140 static basic_block
31143 {
31144 gimple return_stmt;
31146 gimple convert_stmt;
31147 gimple call_cond_stmt;
31148 gimple if_else_stmt;
31154 gimple_seq gseq;
31171 {
31179 }
31182 {
31197 else
31198 {
31199 gimple assign_stmt;
31200 /* Use MIN_EXPR to check if any integer is zero?.
31201 and_expr_var = min_expr <cond_var, and_expr_var> */
31209 }
31210 }
31213 integer_zero_node,
31243 }
31245 /* This parses the attribute arguments to target in DECL and determines
31246 the right builtin to use to match the platform specification.
31247 It returns the priority value for this version decl. If PREDICATE_LIST
31248 is not NULL, it stores the list of cpu features that need to be checked
31249 before dispatching this function. */
31251 static unsigned int
31253 {
31254 tree attrs;
31256 tree target_node;
31263 /* Priority of i386 features, greater value is higher priority. This is
31264 used to decide the order in which function dispatch must happen. For
31265 instance, a version specialized for SSE4.2 should be checked for dispatch
31266 before a version for SSE3, as SSE4.2 implies SSE3. */
31267 enum feature_priority
31268 {
31270 P_MMX,
31271 P_SSE,
31272 P_SSE2,
31273 P_SSE3,
31274 P_SSSE3,
31275 P_PROC_SSSE3,
31276 P_SSE4_A,
31277 P_PROC_SSE4_A,
31278 P_SSE4_1,
31279 P_SSE4_2,
31280 P_PROC_SSE4_2,
31281 P_POPCNT,
31282 P_AVX,
31283 P_PROC_AVX,
31284 P_FMA4,
31285 P_XOP,
31286 P_PROC_XOP,
31287 P_FMA,
31288 P_PROC_FMA,
31289 P_AVX2,
31290 P_PROC_AVX2
31291 };
31295 /* These are the target attribute strings for which a dispatcher is
31296 available, from fold_builtin_cpu. */
31298 static struct _feature_list
31299 {
31302 }
31304 {
31319 };
31322 static unsigned int NUM_FEATURES
31338 /* Return priority zero for default function. */
31342 /* Handle arch= if specified. For priority, set it to be 1 more than
31343 the best instruction set the processor can handle. For instance, if
31344 there is a version for atom and a version for ssse3 (the highest ISA
31345 priority for atom), the atom version must be checked for dispatch
31346 before the ssse3 version. */
31348 {
31358 {
31360 {
31368 else
31369 /* We translate "arch=corei7" and "arch=nehalem" to
31370 "corei7" so that it will be mapped to M_INTEL_COREI7
31371 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31378 else
31385 else
31425 }
31426 }
31431 {
31435 }
31438 {
31440 /* For a C string literal the length includes the trailing NULL. */
31443 predicate_chain);
31444 }
31445 }
31447 /* Process feature name. */
31454 {
31455 /* Do not process "arch=" */
31457 {
31460 }
31462 {
31464 {
31466 {
31471 predicate_chain);
31472 }
31473 /* Find the maximum priority feature. */
31478 }
31479 }
31481 {
31485 }
31487 }
31491 {
31494 attrs_str);
31496 }
31498 {
31501 }
31504 }
31506 /* This compares the priority of target features in function DECL1
31507 and DECL2. It returns positive value if DECL1 is higher priority,
31508 negative value if DECL2 is higher priority and 0 if they are the
31509 same. */
31511 static int
31513 {
31518 }
31520 /* V1 and V2 point to function versions with different priorities
31521 based on the target ISA. This function compares their priorities. */
31523 static int
31525 {
31527 {
31528 tree version_decl;
31529 tree predicate_chain;
31536 }
31538 /* This function generates the dispatch function for
31539 multi-versioned functions. DISPATCH_DECL is the function which will
31540 contain the dispatch logic. FNDECLS are the function choices for
31541 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31542 in DISPATCH_DECL in which the dispatch code is generated. */
31544 static int
31548 {
31549 tree default_decl;
31550 gimple ifunc_cpu_init_stmt;
31551 gimple_seq gseq;
31553 tree ele;
31559 struct _function_version_info
31560 {
31561 tree version_decl;
31562 tree predicate_chain;
31570 /*fndecls_p is actually a vector. */
31573 /* At least one more version other than the default. */
31580 /* The first version in the vector is the default decl. */
31586 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31587 constructors, so explicity call __builtin_cpu_init here. */
31598 {
31602 /* Get attribute string, parse it and find the right predicate decl.
31603 The predicate function could be a lengthy combination of many
31604 features, like arch-type and various isa-variants. */
31615 actual_versions++;
31616 }
31618 /* Sort the versions according to descending order of dispatch priority. The
31619 priority is based on the ISA. This is not a perfect solution. There
31620 could still be ambiguity. If more than one function version is suitable
31621 to execute, which one should be dispatched? In future, allow the user
31622 to specify a dispatch priority next to the version. */
31632 /* dispatch default version at the end. */
31638 }
31640 /* Comparator function to be used in qsort routine to sort attribute
31641 specification strings to "target". */
31643 static int
31645 {
31649 }
31651 /* ARGLIST is the argument to target attribute. This function tokenizes
31652 the comma separated arguments, sorts them and returns a string which
31653 is a unique identifier for the comma separated arguments. It also
31654 replaces non-identifier characters "=,-" with "_". */
31658 {
31659 tree arg;
31668 {
31673 argnum++;
31676 argnum++;
31677 }
31682 {
31688 }
31690 /* Replace "=,-" with "_". */
31703 {
31705 i++;
31707 }
31714 {
31719 }
31724 }
31726 /* This function changes the assembler name for functions that are
31727 versions. If DECL is a function version and has a "target"
31728 attribute, it appends the attribute string to its assembler name. */
31730 static tree
31732 {
31733 tree version_attr;
31741 "Function versions cannot be marked as gnu_inline,"
31750 /* target attribute string cannot be NULL. */
31754 version_string
31765 /* Allow assembler name to be modified if already set. */
31773 }
31775 /* This function returns true if FN1 and FN2 are versions of the same function,
31776 that is, the target strings of the function decls are different. This assumes
31777 that FN1 and FN2 have the same signature. */
31779 static bool
31781 {
31793 /* At least one function decl should have the target attribute specified. */
31797 /* Diagnose missing target attribute if one of the decls is already
31798 multi-versioned. */
31800 {
31802 {
31804 {
31809 }
31812 fn2);
31815 /* Prevent diagnosing of the same error multiple times. */
31820 }
31822 }
31827 /* The sorted target strings must be different for fn1 and fn2
31828 to be versions. */
31831 else
31838 }
31840 static tree
31842 {
31843 /* For function version, add the target suffix to the assembler name. */
31847 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31849 #endif
31852 }
31854 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31855 is true, append the full path name of the source file. */
31859 {
31867 /* Get a unique name that can be used globally without any chances
31868 of collision at link time. */
31878 /* Use '.' to concatenate names as it is demangler friendly. */
31881 suffix);
31882 else
31886 }
31888 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
31890 /* Make a dispatcher declaration for the multi-versioned function DECL.
31891 Calls to DECL function will be replaced with calls to the dispatcher
31892 by the front-end. Return the decl created. */
31894 static tree
31896 {
31897 tree func_decl;
31917 /* Mark this func as external, the resolver will flip it again if
31918 it gets generated. */
31920 /* This will be of type IFUNCs have to be externally visible. */
31924 }
31926 #endif
31928 /* Returns true if decl is multi-versioned and DECL is the default function,
31929 that is it is not tagged with target specific optimization. */
31931 static bool
31933 {
31942 }
31944 /* Make a dispatcher declaration for the multi-versioned function DECL.
31945 Calls to DECL function will be replaced with calls to the dispatcher
31946 by the front-end. Returns the decl of the dispatcher function. */
31948 static tree
31950 {
31972 /* Find the default version and make it the first node. */
31974 /* Go to the beginning of the chain. */
31979 {
31984 }
31986 /* If there is no default node, just return NULL. */
31990 /* Make default info the first node. */
31992 {
31999 }
32003 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32005 {
32010 /* Right now, the dispatching is done via ifunc. */
32016 dispatcher_version_info
32021 /* Set the dispatcher for all the versions. */
32024 {
32027 }
32028 }
32029 else
32030 #endif
32031 {
32033 "multiversioning needs ifunc which is not supported "
32035 }
32038 }
32040 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32041 it to CHAIN. */
32043 static tree
32045 {
32046 tree attr_name;
32047 tree attr_arg_name;
32048 tree attr_args;
32049 tree attr;
32056 }
32058 /* Make the resolver function decl to dispatch the versions of
32059 a multi-versioned function, DEFAULT_DECL. Create an
32060 empty basic block in the resolver and store the pointer in
32061 EMPTY_BB. Return the decl of the resolver function. */
32063 static tree
32067 {
32072 /* IFUNC's have to be globally visible. So, if the default_decl is
32073 not, then the name of the IFUNC should be made unique. */
32077 /* Append the filename to the resolver function if the versions are
32078 not externally visible. This is because the resolver function has
32079 to be externally visible for the loader to find it. So, appending
32080 the filename will prevent conflicts with a resolver function from
32081 another module which is based on the same version name. */
32084 /* The resolver function should return a (void *). */
32095 /* IFUNC resolvers have to be externally visible. */
32099 /* Resolver is not external, body is generated. */
32109 {
32110 /* In this case, each translation unit with a call to this
32111 versioned function will put out a resolver. Ensure it
32112 is comdat to keep just one copy. */
32115 }
32116 /* Build result decl and add to function_decl. */
32132 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32136 /* Create the alias for dispatch to resolver here. */
32137 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32141 }
32143 /* Generate the dispatching code body to dispatch multi-versioned function
32144 DECL. The target hook is called to process the "target" attributes and
32145 provide the code to dispatch the right function at run-time. NODE points
32146 to the dispatcher decl whose body will be created. */
32148 static tree
32150 {
32151 tree resolver_decl;
32152 basic_block empty_bb;
32153 tree default_ver_decl;
32169 /* The first version in the chain corresponds to the default version. */
32172 /* node is going to be an alias, so remove the finalized bit. */
32186 {
32188 /* Check for virtual functions here again, as by this time it should
32189 have been determined if this function needs a vtable index or
32190 not. This happens for methods in derived classes that override
32191 virtual methods in base classes but are not explicitly marked as
32192 virtual. */
32197 }
32203 }
32204 /* This builds the processor_model struct type defined in
32205 libgcc/config/i386/cpuinfo.c */
32207 static tree
32209 {
32216 /* The first 3 fields are unsigned int. */
32218 {
32224 }
32226 /* The last field is an array of unsigned integers of size one. */
32237 }
32239 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32241 static tree
32243 {
32244 tree new_decl;
32247 VAR_DECL,
32249 type);
32262 }
32264 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32265 into an integer defined in libgcc/config/i386/cpuinfo.c */
32267 static tree
32269 {
32275 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32276 enum processor_features
32277 {
32279 F_MMX,
32280 F_POPCNT,
32281 F_SSE,
32282 F_SSE2,
32283 F_SSE3,
32284 F_SSSE3,
32285 F_SSE4_1,
32286 F_SSE4_2,
32287 F_AVX,
32288 F_AVX2,
32289 F_SSE4_A,
32290 F_FMA4,
32291 F_XOP,
32292 F_FMA,
32293 F_MAX
32294 };
32296 /* These are the values for vendor types and cpu types and subtypes
32297 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32298 the corresponding start value. */
32299 enum processor_model
32300 {
32302 M_AMD,
32303 M_CPU_TYPE_START,
32304 M_INTEL_BONNELL,
32305 M_INTEL_CORE2,
32306 M_INTEL_COREI7,
32307 M_AMDFAM10H,
32308 M_AMDFAM15H,
32309 M_INTEL_SILVERMONT,
32310 M_AMD_BTVER1,
32311 M_AMD_BTVER2,
32312 M_CPU_SUBTYPE_START,
32313 M_INTEL_COREI7_NEHALEM,
32314 M_INTEL_COREI7_WESTMERE,
32315 M_INTEL_COREI7_SANDYBRIDGE,
32316 M_AMDFAM10H_BARCELONA,
32317 M_AMDFAM10H_SHANGHAI,
32318 M_AMDFAM10H_ISTANBUL,
32319 M_AMDFAM15H_BDVER1,
32320 M_AMDFAM15H_BDVER2,
32321 M_AMDFAM15H_BDVER3,
32322 M_AMDFAM15H_BDVER4,
32323 M_INTEL_COREI7_IVYBRIDGE,
32324 M_INTEL_COREI7_HASWELL
32325 };
32327 static struct _arch_names_table
32328 {
32331 }
32333 {
32358 };
32360 static struct _isa_names_table
32361 {
32364 }
32366 {
32382 };
32396 {
32397 /* *args must be a expr that can contain other EXPRS leading to a
32398 STRING_CST. */
32400 {
32403 }
32405 }
32410 {
32411 tree ref;
32412 tree field;
32413 tree final;
32416 unsigned int NUM_ARCH_NAMES
32425 {
32429 }
32434 /* CPU types are stored in the next field. */
32437 {
32440 }
32442 /* CPU subtypes are stored in the next field. */
32444 {
32447 }
32449 /* Get the appropriate field in __cpu_model. */
32453 /* Check the value. */
32457 }
32459 {
32460 tree ref;
32461 tree array_elt;
32462 tree field;
32463 tree final;
32466 unsigned int NUM_ISA_NAMES
32475 {
32479 }
32482 /* Get the last field, which is __cpu_features. */
32486 /* Get the appropriate field: __cpu_model.__cpu_features */
32490 /* Access the 0th element of __cpu_features array. */
32495 /* Return __cpu_model.__cpu_features[0] & field_val */
32499 }
32501 }
32503 static tree
32506 {
32508 {
32513 {
32516 }
32517 }
32519 #ifdef SUBTARGET_FOLD_BUILTIN
32521 #endif
32524 }
32526 /* Make builtins to detect cpu type and features supported. NAME is
32527 the builtin name, CODE is the builtin code, and FTYPE is the function
32528 type of the builtin. */
32530 static void
32533 {
32534 tree decl;
32535 tree type;
32543 }
32545 /* Make builtins to get CPU type and features supported. The created
32546 builtins are :
32548 __builtin_cpu_init (), to detect cpu type and features,
32549 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32550 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32551 */
32553 static void
32555 {
32562 }
32564 /* Internal method for ix86_init_builtins. */
32566 static void
32568 {
32580 sysv_va_ref =
32583 fnvoid_va_end_ms =
32585 fnvoid_va_start_ms =
32587 fnvoid_va_end_sysv =
32589 fnvoid_va_start_sysv =
32591 NULL_TREE);
32592 fnvoid_va_copy_ms =
32594 NULL_TREE);
32595 fnvoid_va_copy_sysv =
32611 }
32613 static void
32615 {
32618 /* The __float80 type. */
32621 {
32622 /* The __float80 type. */
32627 }
32630 /* The __float128 type. */
32636 /* This macro is built by i386-builtin-types.awk. */
32637 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32638 }
32640 static void
32642 {
32643 tree t;
32647 /* Builtins to get CPU type and features. */
32650 /* TFmode support builtins. */
32656 /* We will expand them to normal call if SSE isn't available since
32657 they are used by libgcc. */
32676 #ifdef SUBTARGET_INIT_BUILTINS
32677 SUBTARGET_INIT_BUILTINS;
32678 #endif
32679 }
32681 /* Return the ix86 builtin for CODE. */
32683 static tree
32685 {
32690 }
32692 /* Errors in the source file can cause expand_expr to return const0_rtx
32693 where we expect a vector. To avoid crashing, use one of the vector
32694 clear instructions. */
32695 static rtx
32697 {
32701 }
32703 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32705 static rtx
32707 {
32708 rtx pat;
32728 {
32732 }
32746 }
32748 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32750 static rtx
32754 {
32755 rtx pat;
32763 rtx op;
32770 {
32850 }
32860 {
32867 {
32869 {
32872 {
32890 xop_rotl:
32892 {
32895 gcc_checking_assert
32897 }
32898 else
32899 {
32900 gcc_checking_assert
32911 }
32915 }
32916 }
32917 }
32918 else
32919 {
32920 non_constant:
32924 /* If we aren't optimizing, only allow one memory operand to be
32925 generated. */
32927 num_memory++;
32935 }
32939 }
32942 {
32953 else
32954 {
32960 }
32973 }
32980 }
32982 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
32983 insns with vec_merge. */
32985 static rtx
32987 rtx target)
32988 {
32989 rtx pat;
33016 }
33018 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33020 static rtx
33023 {
33024 rtx pat;
33029 rtx op2;
33040 /* Swap operands if we have a comparison that isn't available in
33041 hardware. */
33043 {
33048 }
33068 }
33070 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33072 static rtx
33074 rtx target)
33075 {
33076 rtx pat;
33090 /* Swap operands if we have a comparison that isn't available in
33091 hardware. */
33093 {
33097 }
33118 const0_rtx)));
33121 }
33123 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33125 static rtx
33127 rtx target)
33128 {
33129 rtx pat;
33154 }
33156 static rtx
33159 {
33160 rtx pat;
33165 rtx op2;
33192 }
33194 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33196 static rtx
33198 rtx target)
33199 {
33200 rtx pat;
33233 const0_rtx)));
33236 }
33238 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33240 static rtx
33243 {
33244 rtx pat;
33282 {
33285 }
33288 {
33297 }
33299 {
33308 }
33309 else
33310 {
33317 }
33325 {
33330 emit_insn
33334 FLAGS_REG),
33335 const0_rtx)));
33337 }
33338 else
33340 }
33343 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33345 static rtx
33348 {
33349 rtx pat;
33377 {
33380 }
33383 {
33392 }
33394 {
33403 }
33404 else
33405 {
33412 }
33420 {
33425 emit_insn
33429 FLAGS_REG),
33430 const0_rtx)));
33432 }
33433 else
33435 }
33437 /* Subroutine of ix86_expand_builtin to take care of insns with
33438 variable number of operands. */
33440 static rtx
33443 {
33449 struct
33450 {
33451 rtx op;
33463 {
33911 }
33916 {
33919 }
33922 {
33929 }
33930 else
33931 {
33934 }
33937 {
33944 {
33945 /* SIMD shift insns take either an 8-bit immediate or
33946 register as count. But builtin functions take int as
33947 count. If count doesn't match, we put it in register. */
33949 {
33953 }
33954 }
33957 {
33960 {
34036 {
34040 {
34043 }
34049 }
34051 }
34052 }
34053 else
34054 {
34058 /* If we aren't optimizing, only allow one memory operand to
34059 be generated. */
34061 num_memory++;
34064 {
34067 }
34068 else
34069 {
34072 }
34073 }
34077 }
34080 {
34105 }
34112 }
34114 /* Transform pattern of following layout:
34115 (parallel [
34116 set (A B)
34117 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34118 ])
34119 into:
34120 (set (A B))
34122 Or:
34123 (parallel [ A B
34124 ...
34125 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34126 ...
34127 ])
34128 into:
34129 (parallel [ A B ... ]) */
34131 static rtx
34133 {
34140 {
34149 }
34150 else
34151 {
34157 {
34162 }
34164 /* No more than 1 occurence was removed. */
34168 }
34169 }
34171 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34172 with rounding. */
34173 static rtx
34176 {
34193 /* See avxintrin.h for values. */
34195 {
34199 };
34201 {
34206 };
34209 {
34212 }
34214 {
34217 }
34220 {
34223 }
34246 ? CODE_FOR_sse_ucomi_round
34253 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34255 {
34261 }
34262 else
34263 {
34266 }
34272 set_dst,
34273 const0_rtx)));
34276 }
34278 static rtx
34281 {
34282 rtx pat;
34284 struct
34285 {
34286 rtx op;
34296 {
34373 }
34383 {
34390 {
34392 {
34394 {
34410 }
34411 }
34412 }
34414 {
34416 {
34419 }
34421 /* If there is no rounding use normal version of the pattern. */
34424 }
34425 else
34426 {
34431 {
34434 }
34435 else
34436 {
34439 }
34440 }
34444 }
34447 {
34472 }
34482 }
34484 /* Subroutine of ix86_expand_builtin to take care of special insns
34485 with variable number of operands. */
34487 static rtx
34490 {
34491 tree arg;
34495 struct
34496 {
34497 rtx op;
34507 {
34546 {
34554 }
34573 /* Reserve memory operand for target. */
34576 {
34577 /* These builtins and instructions require the memory
34578 to be properly aligned. */
34597 }
34622 {
34623 /* These builtins and instructions require the memory
34624 to be properly aligned. */
34633 }
34634 /* FALLTHRU */
34652 /* Reserve memory operand for target. */
34665 {
34666 /* These builtins and instructions require the memory
34667 to be properly aligned. */
34676 }
34689 }
34694 {
34699 {
34702 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34703 on it. Try to improve it using get_pointer_alignment,
34704 and if the special builtin is one that requires strict
34705 mode alignment, also from it's GET_MODE_ALIGNMENT.
34706 Failure to do so could lead to ix86_legitimate_combined_insn
34707 rejecting all changes to such insns. */
34713 }
34714 else
34717 }
34718 else
34719 {
34726 }
34729 {
34738 {
34740 {
34746 else
34749 }
34750 }
34751 else
34752 {
34754 {
34755 /* This must be the memory operand. */
34758 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34759 on it. Try to improve it using get_pointer_alignment,
34760 and if the special builtin is one that requires strict
34761 mode alignment, also from it's GET_MODE_ALIGNMENT.
34762 Failure to do so could lead to ix86_legitimate_combined_insn
34763 rejecting all changes to such insns. */
34769 }
34770 else
34771 {
34772 /* This must be register. */
34778 else
34779 {
34782 }
34783 }
34784 }
34788 }
34791 {
34806 }
34812 }
34814 /* Return the integer constant in ARG. Constrain it to be in the range
34815 of the subparts of VEC_TYPE; issue an error if not. */
34817 static int
34819 {
34824 {
34827 }
34830 }
34832 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34833 ix86_expand_vector_init. We DO have language-level syntax for this, in
34834 the form of (type){ init-list }. Except that since we can't place emms
34835 instructions from inside the compiler, we can't allow the use of MMX
34836 registers unless the user explicitly asks for it. So we do *not* define
34837 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34838 we have builtins invoked by mmintrin.h that gives us license to emit
34839 these sorts of instructions. */
34841 static rtx
34843 {
34853 {
34856 }
34863 }
34865 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34866 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34867 had a language-level syntax for referencing vector elements. */
34869 static rtx
34871 {
34875 rtx op0;
34895 }
34897 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34898 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
34899 a language-level syntax for referencing vector elements. */
34901 static rtx
34903 {
34927 /* OP0 is the source of these builtin functions and shouldn't be
34928 modified. Create a copy, use it and return it as target. */
34934 }
34936 /* Expand an expression EXP that calls a built-in function,
34937 with result going to TARGET if that's convenient
34938 (and in mode MODE if that's convenient).
34939 SUBTARGET may be used as the target for computing one of EXP's operands.
34940 IGNORE is nonzero if the value is to be ignored. */
34942 static rtx
34945 {
34955 /* For CPU builtins that can be folded, fold first and expand the fold. */
34957 {
34959 {
34960 /* Make it call __cpu_indicator_init in libgcc. */
34966 }
34969 {
34974 }
34975 }
34977 /* Determine whether the builtin function is available under the current ISA.
34978 Originally the builtin was not created if it wasn't applicable to the
34979 current ISA based on the command line switches. With function specific
34980 options, we need to check in the context of the function making the call
34981 whether it is supported. */
34984 {
34990 else
34991 {
34995 }
34997 }
35000 {
35004 ? CODE_FOR_mmx_maskmovq
35006 /* Note the arg order is different from the operand order. */
35107 {
35108 REAL_VALUE_TYPE inf;
35109 rtx tmp;
35121 }
35131 {
35137 insn = (TARGET_64BIT
35141 }
35143 {
35144 insn = (TARGET_64BIT
35148 }
35149 else
35150 {
35153 insn = (TARGET_64BIT
35161 {
35164 }
35166 }
35169 {
35170 /* mode is VOIDmode if __builtin_rd* has been called
35171 without lhs. */
35175 }
35178 {
35183 }
35197 {
35222 }
35228 {
35231 }
35251 {
35254 }
35260 {
35264 {
35285 }
35290 }
35291 else
35292 {
35294 {
35306 }
35308 }
35338 ? CODE_FOR_tbm_bextri_si
35341 {
35344 }
35345 else
35346 {
35355 }
35371 rdrand_step:
35378 {
35381 }
35387 /* Emit SImode conditional move. */
35389 {
35392 }
35395 else
35402 const0_rtx);
35421 rdseed_step:
35428 {
35431 }
35437 const0_rtx);
35455 addcarryx:
35463 /* Generate CF from input operand. */
35468 /* Gen ADCX instruction to compute X+Y+CF. */
35483 /* Store the result. */
35486 {
35489 }
35492 /* Return current CF value. */
35534 kortest:
35548 /* Emit kortest. */
35550 /* And use setcc to return result from flags. */
35701 gather_gen:
35702 rtx half;
35715 /* Note the arg order is different from the operand order. */
35726 else
35730 {
35752 else
35759 {
35764 }
35771 else
35778 {
35783 }
35787 }
35789 /* Force memory operand only with base register here. But we
35790 don't want to do it on memory operand for other builtin
35791 functions. */
35801 {
35804 }
35805 else
35806 {
35809 }
35811 {
35814 }
35816 /* Optimize. If mask is known to have all high bits set,
35817 replace op0 with pc_rtx to signal that the instruction
35818 overwrites the whole destination and doesn't use its
35819 previous contents. */
35821 {
35823 {
35826 }
35828 {
35831 {
35835 negative++;
35838 negative++;
35839 }
35842 }
35845 {
35846 /* Recognize also when mask is like:
35847 __v2df src = _mm_setzero_pd ();
35848 __v2df mask = _mm_cmpeq_pd (src, src);
35849 or
35850 __v8sf src = _mm256_setzero_ps ();
35851 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35852 as that is a cheaper way to load all ones into
35853 a register than having to load a constant from
35854 memory. */
35857 {
35862 {
35869 /* FALLTHRU */
35879 }
35880 }
35881 }
35882 }
35890 {
35914 }
35917 scatter_gen:
35933 /* Force memory operand only with base register here. But we
35934 don't want to do it on memory operand for other builtin
35935 functions. */
35942 {
35945 }
35946 else
35947 {
35950 }
35959 {
35962 }
35971 vec_prefetch_gen:
35989 {
35992 }
35994 {
35997 }
36002 /* Force memory operand only with base register here. But we
36003 don't want to do it on memory operand for other builtin
36004 functions. */
36011 {
36014 }
36017 {
36020 }
36036 {
36039 }
36045 }
36058 {
36062 /* Emit a normal call if SSE isn't available. */
36066 }
36095 }
36097 /* This returns the target-specific builtin with code CODE if
36098 current_function_decl has visibility on this builtin, which is checked
36099 using isa flags. Returns NULL_TREE otherwise. */
36102 {
36106 /* Determine the isa flags of current_function_decl. */
36118 else
36120 }
36122 /* Returns a function decl for a vectorized version of the builtin function
36123 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36124 if it is not available. */
36126 static tree
36128 tree type_in)
36129 {
36145 {
36148 {
36155 }
36160 {
36163 }
36168 {
36175 }
36181 /* The round insn does not trap on denormals. */
36186 {
36193 }
36199 /* The round insn does not trap on denormals. */
36204 {
36209 }
36215 /* The round insn does not trap on denormals. */
36220 {
36227 }
36233 /* The round insn does not trap on denormals. */
36238 {
36243 }
36250 {
36255 }
36262 {
36267 }
36273 /* The round insn does not trap on denormals. */
36278 {
36285 }
36291 /* The round insn does not trap on denormals. */
36296 {
36301 }
36306 {
36313 }
36318 {
36325 }
36329 /* The round insn does not trap on denormals. */
36334 {
36339 }
36343 /* The round insn does not trap on denormals. */
36348 {
36353 }
36357 /* The round insn does not trap on denormals. */
36362 {
36367 }
36371 /* The round insn does not trap on denormals. */
36376 {
36381 }
36385 /* The round insn does not trap on denormals. */
36390 {
36395 }
36399 /* The round insn does not trap on denormals. */
36404 {
36409 }
36413 /* The round insn does not trap on denormals. */
36418 {
36423 }
36427 /* The round insn does not trap on denormals. */
36432 {
36437 }
36441 /* The round insn does not trap on denormals. */
36446 {
36451 }
36455 /* The round insn does not trap on denormals. */
36460 {
36465 }
36470 {
36475 }
36480 {
36485 }
36490 }
36492 /* Dispatch to a handler for a vectorization library. */
36495 type_in);
36498 }
36500 /* Handler for an SVML-style interface to
36501 a library with vectorized intrinsics. */
36503 static tree
36505 {
36513 /* The SVML is suitable for unsafe math only. */
36526 {
36573 }
36582 {
36585 }
36586 else
36589 /* Convert to uppercase. */
36594 args;
36596 arity++;
36600 else
36603 /* Build a function declaration for the vectorized function. */
36612 }
36614 /* Handler for an ACML-style interface to
36615 a library with vectorized intrinsics. */
36617 static tree
36619 {
36627 /* The ACML is 64bits only and suitable for unsafe math only as
36628 it does not correctly support parts of IEEE with the required
36629 precision such as denormals. */
36643 {
36673 }
36680 args;
36682 arity++;
36686 else
36689 /* Build a function declaration for the vectorized function. */
36698 }
36700 /* Returns a decl of a function that implements gather load with
36701 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36702 Return NULL_TREE if it is not available. */
36704 static tree
36707 {
36723 /* v*gather* insn sign extends index to pointer mode. */
36735 {
36763 else
36769 else
36775 else
36781 else
36786 }
36789 }
36791 /* Returns a code for a target-specific builtin that implements
36792 reciprocal of the function, or NULL_TREE if not available. */
36794 static tree
36797 {
36804 /* Machine dependent builtins. */
36806 {
36807 /* Vectorized version of sqrt to rsqrt conversion. */
36816 }
36817 else
36818 /* Normal builtins. */
36820 {
36821 /* Sqrt to rsqrt conversion. */
36827 }
36828 }
36829 \f
36830 /* Helper for avx_vpermilps256_operand et al. This is also used by
36831 the expansion functions to turn the parallel back into a mask.
36832 The return value is 0 for no match and the imm8+1 for a match. */
36834 int
36836 {
36844 /* Validate that all of the elements are constants, and not totally
36845 out of range. Copy the data into an integral array to make the
36846 subsequent checks easier. */
36848 {
36858 }
36861 {
36863 /* In the 512-bit DFmode case, we can only move elements within
36864 a 128-bit lane. First fill the second part of the mask,
36865 then fallthru. */
36867 {
36871 }
36873 {
36877 }
36878 /* FALLTHRU */
36881 /* In the 256-bit DFmode case, we can only move elements within
36882 a 128-bit lane. */
36884 {
36888 }
36890 {
36894 }
36898 /* In 512 bit SFmode case, permutation in the upper 256 bits
36899 must mirror the permutation in the lower 256-bits. */
36903 /* FALLTHRU */
36906 /* In 256 bit SFmode case, we have full freedom of
36907 movement within the low 128-bit lane, but the high 128-bit
36908 lane must mirror the exact same pattern. */
36913 /* FALLTHRU */
36917 /* In the 128-bit case, we've full freedom in the placement of
36918 the elements from the source operand. */
36925 }
36927 /* Make sure success has a non-zero value by adding one. */
36929 }
36931 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
36932 the expansion functions to turn the parallel back into a mask.
36933 The return value is 0 for no match and the imm8+1 for a match. */
36935 int
36937 {
36945 /* Validate that all of the elements are constants, and not totally
36946 out of range. Copy the data into an integral array to make the
36947 subsequent checks easier. */
36949 {
36959 }
36961 /* Validate that the halves of the permute are halves. */
36969 /* Reconstruct the mask. */
36971 {
36977 }
36979 /* Make sure success has a non-zero value by adding one. */
36981 }
36982 \f
36983 /* Store OPERAND to the memory after reload is completed. This means
36984 that we can't easily use assign_stack_local. */
36985 rtx
36987 {
36988 rtx result;
36992 {
36995 stack_pointer_rtx,
36998 }
37000 {
37002 {
37006 /* FALLTHRU */
37012 stack_pointer_rtx)),
37013 operand));
37017 }
37019 }
37020 else
37021 {
37023 {
37025 {
37032 stack_pointer_rtx)),
37038 stack_pointer_rtx)),
37040 }
37043 /* Store HImodes as SImodes. */
37045 /* FALLTHRU */
37051 stack_pointer_rtx)),
37052 operand));
37056 }
37058 }
37060 }
37062 /* Free operand from the memory. */
37063 void
37065 {
37067 {
37072 else
37074 /* Use LEA to deallocate stack space. In peephole2 it will be converted
37075 to pop or add instruction if registers are available. */
37079 }
37080 }
37082 /* Return a register priority for hard reg REGNO. */
37083 static int
37085 {
37086 /* ebp and r13 as the base always wants a displacement, r12 as the
37087 base always wants an index. So discourage their usage in an
37088 address. */
37093 /* New x86-64 int registers result in bigger code size. Discourage
37094 them. */
37097 /* New x86-64 SSE registers result in bigger code size. Discourage
37098 them. */
37101 /* Usage of AX register results in smaller code. Prefer it. */
37105 }
37107 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37109 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37110 QImode must go into class Q_REGS.
37111 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37112 movdf to do mem-to-mem moves through integer regs. */
37114 static reg_class_t
37116 {
37119 /* We're only allowed to return a subclass of CLASS. Many of the
37120 following checks fail for NO_REGS, so eliminate that early. */
37124 /* All classes can load zeros. */
37128 /* Force constants into memory if we are loading a (nonzero) constant into
37129 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37130 instructions to load from a constant. */
37137 /* Prefer SSE regs only, if we can use them for math. */
37141 /* Floating-point constants need more complex checks. */
37143 {
37144 /* General regs can load everything. */
37148 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37149 zero above. We only want to wind up preferring 80387 registers if
37150 we plan on doing computation with them. */
37153 {
37154 /* Limit class to non-sse. */
37163 }
37166 }
37168 /* Generally when we see PLUS here, it's the function invariant
37169 (plus soft-fp const_int). Which can only be computed into general
37170 regs. */
37174 /* QImode constants are easy to load, but non-constant QImode data
37175 must go into Q_REGS. */
37177 {
37183 }
37186 }
37188 /* Discourage putting floating-point values in SSE registers unless
37189 SSE math is being used, and likewise for the 387 registers. */
37190 static reg_class_t
37192 {
37195 /* Restrict the output reload class to the register bank that we are doing
37196 math on. If we would like not to return a subset of CLASS, reject this
37197 alternative: if reload cannot do this, it will still use its choice. */
37203 {
37208 else
37210 }
37213 }
37215 static reg_class_t
37218 {
37219 /* Double-word spills from general registers to non-offsettable memory
37220 references (zero-extended addresses) require special handling. */
37226 {
37228 ? CODE_FOR_reload_noff_load
37230 /* Add the cost of moving address to a temporary. */
37234 }
37236 /* QImode spills from non-QI registers require
37237 intermediate register on 32bit targets. */
37243 {
37248 else
37254 /* Return Q_REGS if the operand is in memory. */
37257 }
37259 /* This condition handles corner case where an expression involving
37260 pointers gets vectorized. We're trying to use the address of a
37261 stack slot as a vector initializer.
37263 (set (reg:V2DI 74 [ vect_cst_.2 ])
37264 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37266 Eventually frame gets turned into sp+offset like this:
37268 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37269 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37270 (const_int 392 [0x188]))))
37272 That later gets turned into:
37274 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37275 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37276 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37278 We'll have the following reload recorded:
37280 Reload 0: reload_in (DI) =
37281 (plus:DI (reg/f:DI 7 sp)
37282 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37283 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37284 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37285 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37286 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37287 reload_reg_rtx: (reg:V2DI 22 xmm1)
37289 Which isn't going to work since SSE instructions can't handle scalar
37290 additions. Returning GENERAL_REGS forces the addition into integer
37291 register and reload can handle subsequent reloads without problems. */
37299 }
37301 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37303 static bool
37305 {
37307 {
37322 }
37325 }
37327 /* If we are copying between general and FP registers, we need a memory
37328 location. The same is true for SSE and MMX registers.
37330 To optimize register_move_cost performance, allow inline variant.
37332 The macro can't work reliably when one of the CLASSES is class containing
37333 registers from multiple units (SSE, MMX, integer). We avoid this by never
37334 combining those units in single alternative in the machine description.
37335 Ensure that this constraint holds to avoid unexpected surprises.
37337 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37338 enforce these sanity checks. */
37343 {
37352 {
37355 }
37360 /* ??? This is a lie. We do have moves between mmx/general, and for
37361 mmx/sse2. But by saying we need secondary memory we discourage the
37362 register allocator from using the mmx registers unless needed. */
37367 {
37368 /* SSE1 doesn't have any direct moves from other classes. */
37372 /* If the target says that inter-unit moves are more expensive
37373 than moving through memory, then don't generate them. */
37378 /* Between SSE and general, we have moves no larger than word size. */
37381 }
37384 }
37386 bool
37389 {
37391 }
37393 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37395 On the 80386, this is the size of MODE in words,
37396 except in the FP regs, where a single reg is always enough. */
37398 static unsigned char
37400 {
37402 {
37407 else
37409 }
37410 else
37411 {
37414 else
37416 }
37417 }
37419 /* Return true if the registers in CLASS cannot represent the change from
37420 modes FROM to TO. */
37422 bool
37425 {
37429 /* x87 registers can't do subreg at all, as all values are reformatted
37430 to extended precision. */
37435 {
37436 /* Vector registers do not support QI or HImode loads. If we don't
37437 disallow a change to these modes, reload will assume it's ok to
37438 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37439 the vec_dupv4hi pattern. */
37443 /* Vector registers do not support subreg with nonzero offsets, which
37444 are otherwise valid for integer registers. Since we can't see
37445 whether we have a nonzero offset from here, prohibit all
37446 nonparadoxical subregs changing size. */
37449 }
37452 }
37454 /* Return the cost of moving data of mode M between a
37455 register and memory. A value of 2 is the default; this cost is
37456 relative to those in `REGISTER_MOVE_COST'.
37458 This function is used extensively by register_move_cost that is used to
37459 build tables at startup. Make it inline in this case.
37460 When IN is 2, return maximum of in and out move cost.
37462 If moving between registers and memory is more expensive than
37463 between two registers, you should define this macro to express the
37464 relative cost.
37466 Model also increased moving costs of QImode registers in non
37467 Q_REGS classes.
37468 */
37472 {
37475 {
37478 {
37490 }
37494 }
37496 {
37499 {
37511 }
37515 }
37517 {
37520 {
37529 }
37533 }
37535 {
37538 {
37544 else
37549 }
37550 else
37551 {
37556 else
37558 }
37565 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37572 else
37576 }
37577 }
37579 static int
37582 {
37584 }
37587 /* Return the cost of moving data from a register in class CLASS1 to
37588 one in class CLASS2.
37590 It is not required that the cost always equal 2 when FROM is the same as TO;
37591 on some machines it is expensive to move between registers if they are not
37592 general registers. */
37594 static int
37596 reg_class_t class2_i)
37597 {
37601 /* In case we require secondary memory, compute cost of the store followed
37602 by load. In order to avoid bad register allocation choices, we need
37603 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37606 {
37612 /* In case of copying from general_purpose_register we may emit multiple
37613 stores followed by single load causing memory size mismatch stall.
37614 Count this as arbitrarily high cost of 20. */
37619 /* In the case of FP/MMX moves, the registers actually overlap, and we
37620 have to switch modes in order to treat them differently. */
37626 }
37628 /* Moves between SSE/MMX and integer unit are expensive. */
37632 /* ??? By keeping returned value relatively high, we limit the number
37633 of moves between integer and MMX/SSE registers for all targets.
37634 Additionally, high value prevents problem with x86_modes_tieable_p(),
37635 where integer modes in MMX/SSE registers are not tieable
37636 because of missing QImode and HImode moves to, from or between
37637 MMX/SSE registers. */
37647 }
37649 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37650 MODE. */
37652 bool
37654 {
37655 /* Flags and only flags can only hold CCmode values. */
37667 {
37668 /* We implement the move patterns for all vector modes into and
37669 out of SSE registers, even when no operation instructions
37670 are available. */
37672 /* For AVX-512 we allow, regardless of regno:
37673 - XI mode
37674 - any of 512-bit wide vector mode
37675 - any scalar mode. */
37682 /* xmm16-xmm31 are only available for AVX-512. */
37686 /* OImode and AVX modes are available only when AVX is enabled. */
37693 }
37695 {
37696 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37697 so if the register is available at all, then we can move data of
37698 the given mode into or out of it. */
37701 }
37704 {
37705 /* Take care for QImode values - they can be in non-QI regs,
37706 but then they do cause partial register stalls. */
37711 /* LRA checks if the hard register is OK for the given mode.
37712 QImode values can live in non-QI regs, so we allow all
37713 registers here. */
37717 }
37718 /* We handle both integer and floats in the general purpose registers. */
37725 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37726 on to use that value in smaller contexts, this can easily force a
37727 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37728 supporting DImode, allow it. */
37733 }
37735 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37736 tieable integer mode. */
37738 static bool
37740 {
37742 {
37755 }
37756 }
37758 /* Return true if MODE1 is accessible in a register that can hold MODE2
37759 without copying. That is, all register classes that can hold MODE2
37760 can also hold MODE1. */
37762 bool
37764 {
37772 /* MODE2 being XFmode implies fp stack or general regs, which means we
37773 can tie any smaller floating point modes to it. Note that we do not
37774 tie this with TFmode. */
37778 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37779 that we can tie it with SFmode. */
37783 /* If MODE2 is only appropriate for an SSE register, then tie with
37784 any other mode acceptable to SSE registers. */
37794 /* If MODE2 is appropriate for an MMX register, then tie
37795 with any other mode acceptable to MMX registers. */
37802 }
37804 /* Return the cost of moving between two registers of mode MODE. */
37806 static int
37808 {
37812 {
37844 }
37846 /* Return the cost of moving between two registers of mode MODE,
37847 assuming that the move will be in pieces of at most UNITS bytes. */
37849 }
37851 /* Compute a (partial) cost for rtx X. Return true if the complete
37852 cost has been computed, and false if subexpressions should be
37853 scanned. In either case, *TOTAL contains the cost result. */
37855 static bool
37858 {
37859 rtx mask;
37866 {
37870 {
37873 }
37885 && (!TARGET_64BIT
37890 else
37896 {
37899 }
37901 {
37911 }
37913 {
37916 {
37925 }
37926 }
37927 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37928 it'll probably end up. Add a penalty for size. */
37935 /* The zero extensions is often completely free on x86_64, so make
37936 it as cheap as possible. */
37942 else
37954 {
37957 {
37960 }
37963 {
37966 }
37967 }
37968 /* FALLTHRU */
37975 {
37976 /* ??? Should be SSE vector operation cost. */
37977 /* At least for published AMD latencies, this really is the same
37978 as the latency for a simple fpu operation like fabs. */
37979 /* V*QImode is emulated with 1-11 insns. */
37981 {
37984 {
37985 /* For XOP we use vpshab, which requires a broadcast of the
37986 value to the variable shift insn. For constants this
37987 means a V16Q const in mem; even when we can perform the
37988 shift with one insn set the cost to prefer paddb. */
37990 {
37995 }
37997 }
38001 }
38002 else
38004 }
38006 {
38008 {
38011 else
38013 }
38014 else
38015 {
38018 else
38020 }
38021 }
38022 else
38023 {
38028 {
38029 /* Return the cost after shift-and truncation. */
38032 }
38033 else
38035 }
38039 {
38040 rtx sub;
38045 /* ??? SSE scalar/vector cost should be used here. */
38046 /* ??? Bald assumption that fma has the same cost as fmul. */
38050 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38061 }
38065 {
38066 /* ??? SSE scalar cost should be used here. */
38069 }
38071 {
38074 }
38076 {
38077 /* ??? SSE vector cost should be used here. */
38080 }
38082 {
38083 /* V*QImode is emulated with 7-13 insns. */
38085 {
38092 }
38093 /* V*DImode is emulated with 5-8 insns. */
38095 {
38098 else
38100 }
38101 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38102 insns, including two PMULUDQ. */
38105 else
38108 }
38109 else
38110 {
38115 {
38118 nbits++;
38119 }
38120 else
38121 /* This is arbitrary. */
38124 /* Compute costs correctly for widening multiplication. */
38128 {
38135 {
38139 else
38141 }
38145 }
38153 }
38160 /* ??? SSE cost should be used here. */
38165 /* ??? SSE vector cost should be used here. */
38167 else
38174 {
38179 {
38182 {
38190 }
38191 }
38194 {
38197 {
38203 }
38204 }
38206 {
38214 }
38215 }
38216 /* FALLTHRU */
38220 {
38221 /* ??? SSE cost should be used here. */
38224 }
38226 {
38229 }
38231 {
38232 /* ??? SSE vector cost should be used here. */
38235 }
38236 /* FALLTHRU */
38243 {
38250 }
38251 /* FALLTHRU */
38255 {
38256 /* ??? SSE cost should be used here. */
38259 }
38261 {
38264 }
38266 {
38267 /* ??? SSE vector cost should be used here. */
38270 }
38271 /* FALLTHRU */
38275 {
38276 /* ??? Should be SSE vector operation cost. */
38277 /* At least for published AMD latencies, this really is the same
38278 as the latency for a simple fpu operation like fabs. */
38280 }
38283 else
38292 {
38293 /* This kind of construct is implemented using test[bwl].
38294 Treat it as if we had an AND. */
38299 }
38309 /* ??? SSE cost should be used here. */
38314 /* ??? SSE vector cost should be used here. */
38320 /* ??? SSE cost should be used here. */
38325 /* ??? SSE vector cost should be used here. */
38337 /* ??? Assume all of these vector manipulation patterns are
38338 recognizable. In which case they all pretty much have the
38339 same cost. */
38344 /* This is masked instruction, assume the same cost,
38345 as nonmasked variant. */
38348 else
38354 }
38355 }
38357 #if TARGET_MACHO
38361 /* Given a symbol name and its associated stub, write out the
38362 definition of the stub. */
38364 void
38366 {
38371 /* For 64-bit we shouldn't get here. */
38374 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38391 else
38398 {
38400 }
38402 {
38403 /* PIC stub. */
38404 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38410 }
38411 else
38414 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38415 it needs no stub-binding-helper. */
38422 {
38425 }
38426 else
38431 /* N.B. Keep the correspondence of these
38432 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38433 old-pic/new-pic/non-pic stubs; altering this will break
38434 compatibility with existing dylibs. */
38436 {
38437 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38439 }
38440 else
38441 /* 16-byte -mdynamic-no-pic stub. */
38447 }
38450 /* Order the registers for register allocator. */
38452 void
38454 {
38458 /* First allocate the local general purpose registers. */
38463 /* Global general purpose registers. */
38468 /* x87 registers come first in case we are doing FP math
38469 using them. */
38474 /* SSE registers. */
38480 /* Extended REX SSE registers. */
38484 /* Mask register. */
38488 /* x87 registers. */
38496 /* Initialize the rest of array as we do not allocate some registers
38497 at all. */
38500 }
38502 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38503 in struct attribute_spec handler. */
38504 static tree
38506 tree args,
38509 {
38514 {
38516 name);
38519 }
38521 {
38523 name);
38526 }
38528 {
38529 tree cst;
38533 {
38536 name);
38538 }
38541 {
38544 name);
38546 }
38549 }
38552 }
38554 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38555 struct attribute_spec.handler. */
38556 static tree
38558 tree args ATTRIBUTE_UNUSED,
38560 {
38565 {
38567 name);
38570 }
38572 /* Can combine regparm with all attributes but fastcall. */
38574 {
38576 {
38578 }
38581 }
38583 {
38585 {
38587 }
38590 }
38593 }
38595 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38596 struct attribute_spec.handler. */
38597 static tree
38599 tree args ATTRIBUTE_UNUSED,
38601 {
38604 {
38607 }
38608 else
38612 {
38614 name);
38616 }
38622 {
38624 name);
38626 }
38629 }
38631 static tree
38633 tree args ATTRIBUTE_UNUSED,
38635 {
38637 {
38639 name);
38641 }
38643 }
38645 static bool
38647 {
38651 }
38653 /* Returns an expression indicating where the this parameter is
38654 located on entry to the FUNCTION. */
38656 static rtx
38658 {
38664 {
38669 else
38672 }
38677 {
38684 {
38689 }
38690 else
38691 {
38694 {
38700 }
38701 }
38703 }
38707 }
38709 /* Determine whether x86_output_mi_thunk can succeed. */
38711 static bool
38713 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38715 {
38716 /* 64-bit can handle anything. */
38720 /* For 32-bit, everything's fine if we have one free register. */
38724 /* Need a free register for vcall_offset. */
38728 /* Need a free register for GOT references. */
38732 /* Otherwise ok. */
38734 }
38736 /* Output the assembler code for a thunk function. THUNK_DECL is the
38737 declaration for the thunk function itself, FUNCTION is the decl for
38738 the target function. DELTA is an immediate constant offset to be
38739 added to THIS. If VCALL_OFFSET is nonzero, the word at
38740 *(*this + vcall_offset) should be added to THIS. */
38742 static void
38746 {
38753 else
38754 {
38760 else
38762 }
38766 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38767 pull it in now and let DELTA benefit. */
38771 {
38772 /* Put the this parameter into %eax. */
38775 }
38776 else
38779 /* Adjust the this parameter by a fixed constant. */
38781 {
38786 {
38788 {
38792 }
38793 }
38796 }
38798 /* Adjust the this parameter by a value stored in the vtable. */
38800 {
38810 /* Adjust the this parameter. */
38814 {
38818 }
38825 vcall_mem));
38826 else
38828 }
38830 /* If necessary, drop THIS back to its stack slot. */
38836 {
38839 ;
38840 else
38841 {
38845 }
38846 }
38847 else
38848 {
38850 ;
38851 #if TARGET_MACHO
38853 {
38856 }
38858 else
38859 {
38866 }
38867 }
38869 /* Our sibling call patterns do not allow memories, because we have no
38870 predicate that can distinguish between frame and non-frame memory.
38871 For our purposes here, we can get away with (ab)using a jump pattern,
38872 because we're going to do no optimization. */
38875 else
38876 {
38882 {
38888 }
38894 }
38897 /* Emit just enough of rest_of_compilation to get the insns emitted.
38898 Note that use_thunk calls assemble_start_function et al. */
38904 }
38906 static void
38908 {
38912 #if TARGET_MACHO
38914 #endif
38921 }
38923 int
38925 {
38937 }
38939 /* Output assembler code to FILE to increment profiler label # LABELNO
38940 for profiling a function entry. */
38941 void
38943 {
38948 {
38949 #ifndef NO_PROFILE_COUNTERS
38951 #endif
38955 else
38957 }
38959 {
38960 #ifndef NO_PROFILE_COUNTERS
38963 #endif
38965 }
38966 else
38967 {
38968 #ifndef NO_PROFILE_COUNTERS
38971 #endif
38973 }
38974 }
38976 /* We don't have exact information about the insn sizes, but we may assume
38977 quite safely that we are informed about all 1 byte insns and memory
38978 address sizes. This is enough to eliminate unnecessary padding in
38979 99% of cases. */
38981 static int
38983 {
38989 /* Discard alignments we've emit and jump instructions. */
38994 /* Important case - calls are always 5 bytes.
38995 It is common to have many calls in the row. */
39004 /* For normal instructions we rely on get_attr_length being exact,
39005 with a few exceptions. */
39007 {
39011 {
39021 /* Otherwise trust get_attr_length. */
39023 }
39028 }
39031 else
39033 }
39035 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39037 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39038 window. */
39040 static void
39042 {
39047 /* Look for all minimal intervals of instructions containing 4 jumps.
39048 The intervals are bounded by START and INSN. NBYTES is the total
39049 size of instructions in the interval including INSN and not including
39050 START. When the NBYTES is smaller than 16 bytes, it is possible
39051 that the end of START and INSN ends up in the same 16byte page.
39053 The smallest offset in the page INSN can start is the case where START
39054 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39055 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39057 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39058 have to, control transfer to label(s) can be performed through other
39059 means, and also we estimate minimum length of all asm stmts as 0. */
39061 {
39065 {
39071 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39072 already in the current 16 byte page, because otherwise
39073 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39074 bytes to reach 16 byte boundary. */
39082 {
39084 {
39089 else
39092 }
39093 }
39095 }
39104 njumps++;
39105 else
39109 {
39114 else
39117 }
39124 {
39131 }
39132 }
39133 }
39134 #endif
39136 /* AMD Athlon works faster
39137 when RET is not destination of conditional jump or directly preceded
39138 by other jump instruction. We avoid the penalty by inserting NOP just
39139 before the RET instructions in such cases. */
39140 static void
39142 {
39143 edge e;
39144 edge_iterator ei;
39147 {
39150 rtx prev;
39160 {
39161 edge e;
39162 edge_iterator ei;
39167 {
39170 }
39171 }
39173 {
39179 /* Empty functions get branch mispredict even when
39180 the jump destination is not visible to us. */
39183 }
39185 {
39188 }
39189 }
39190 }
39192 /* Count the minimum number of instructions in BB. Return 4 if the
39193 number of instructions >= 4. */
39195 static int
39197 {
39198 rtx insn;
39201 /* Count number of instructions in this block. Return 4 if the number
39202 of instructions >= 4. */
39204 {
39205 /* Only happen in exit blocks. */
39213 {
39214 insn_count++;
39217 }
39218 }
39221 }
39224 /* Count the minimum number of instructions in code path in BB.
39225 Return 4 if the number of instructions >= 4. */
39227 static int
39229 {
39230 edge e;
39231 edge_iterator ei;
39234 /* Only bother counting instructions along paths with no
39235 more than 2 basic blocks between entry and exit. Given
39236 that BB has an edge to exit, determine if a predecessor
39237 of BB has an edge from entry. If so, compute the number
39238 of instructions in the predecessor block. If there
39239 happen to be multiple such blocks, compute the minimum. */
39242 {
39243 edge prev_e;
39244 edge_iterator prev_ei;
39247 {
39250 }
39252 {
39254 {
39259 }
39260 }
39261 }
39267 }
39269 /* Pad short function to 4 instructions. */
39271 static void
39273 {
39274 edge e;
39275 edge_iterator ei;
39278 {
39281 {
39284 /* Pad short function. */
39286 {
39289 /* Find epilogue. */
39298 /* Two NOPs count as one instruction. */
39301 }
39302 }
39303 }
39304 }
39306 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39307 the epilogue, the Windows system unwinder will apply epilogue logic and
39308 produce incorrect offsets. This can be avoided by adding a nop between
39309 the last insn that can throw and the first insn of the epilogue. */
39311 static void
39313 {
39314 edge e;
39315 edge_iterator ei;
39318 {
39321 /* Find the beginning of the epilogue. */
39328 /* We only care about preceding insns that can throw. */
39333 /* Do not separate calls from their debug information. */
39339 else
39343 }
39344 }
39346 /* Implement machine specific optimizations. We implement padding of returns
39347 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39348 static void
39350 {
39351 /* We are freeing block_for_insn in the toplev to keep compatibility
39352 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39359 {
39364 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39367 #endif
39368 }
39369 }
39371 /* Return nonzero when QImode register that must be represented via REX prefix
39372 is used. */
39373 bool
39375 {
39383 }
39385 /* Return nonzero when P points to register encoded via REX prefix.
39386 Called via for_each_rtx. */
39387 static int
39389 {
39395 }
39397 /* Return true when INSN mentions register that must be encoded using REX
39398 prefix. */
39399 bool
39401 {
39404 }
39406 /* If profitable, negate (without causing overflow) integer constant
39407 of mode MODE at location LOC. Return true in this case. */
39408 bool
39410 {
39411 HOST_WIDE_INT val;
39417 {
39419 /* DImode x86_64 constants must fit in 32 bits. */
39432 }
39434 /* Avoid overflows. */
39440 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39441 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39444 {
39447 }
39450 }
39452 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39453 optabs would emit if we didn't have TFmode patterns. */
39455 void
39457 {
39491 }
39492 \f
39493 /* AVX512F does support 64-byte integer vector operations,
39494 thus the longest vector we are faced with is V64QImode. */
39495 #define MAX_VECT_LEN 64
39497 struct expand_vec_perm_d
39498 {
39505 };
39511 /* Get a vector mode of the same size as the original but with elements
39512 twice as wide. This is only guaranteed to apply to integral vectors. */
39516 {
39517 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39522 }
39524 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39525 fill target with val via vec_duplicate. */
39527 static bool
39529 {
39533 /* First attempt to recognize VAL as-is. */
39537 {
39538 rtx seq;
39539 /* If that fails, force VAL into a register. */
39550 }
39552 }
39554 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39555 with all elements equal to VAR. Return true if successful. */
39557 static bool
39560 {
39564 {
39569 /* FALLTHRU */
39589 {
39590 rtx x;
39597 }
39607 {
39611 permute:
39619 /* Extend to SImode using a paradoxical SUBREG. */
39623 /* Insert the SImode value as low element of a V4SImode vector. */
39632 }
39640 widen:
39641 /* Replicate the value once into the next wider mode and recurse. */
39642 {
39644 rtx x;
39661 }
39665 {
39674 }
39679 }
39680 }
39682 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39683 whose ONE_VAR element is VAR, and other elements are zero. Return true
39684 if successful. */
39686 static bool
39689 {
39691 rtx new_target;
39696 {
39698 /* For SSE4.1, we normally use vector set. But if the second
39699 element is zero and inter-unit moves are OK, we use movq
39700 instead. */
39702 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39724 /* Use ix86_expand_vector_set in 64bit mode only. */
39729 }
39732 {
39737 }
39740 {
39745 /* FALLTHRU */
39760 else
39767 {
39768 /* We need to shuffle the value to the correct position, so
39769 create a new pseudo to store the intermediate result. */
39771 /* With SSE2, we can use the integer shuffle insns. */
39773 {
39775 const1_rtx,
39782 }
39784 /* Otherwise convert the intermediate result to V4SFmode and
39785 use the SSE1 shuffle instructions. */
39787 {
39790 }
39791 else
39795 const1_rtx,
39804 }
39819 widen:
39823 /* Zero extend the variable element to SImode and recurse. */
39836 }
39837 }
39839 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39840 consisting of the values in VALS. It is known that all elements
39841 except ONE_VAR are constants. Return true if successful. */
39843 static bool
39846 {
39856 {
39861 /* For the two element vectors, it's just as easy to use
39862 the general case. */
39866 /* Use ix86_expand_vector_set in 64bit mode only. */
39888 widen:
39889 /* There's no way to set one QImode entry easily. Combine
39890 the variable value with its adjacent constant value, and
39891 promote to an HImode set. */
39894 {
39899 }
39900 else
39901 {
39904 }
39918 }
39923 }
39925 /* A subroutine of ix86_expand_vector_init_general. Use vector
39926 concatenate to handle the most general case: all values variable,
39927 and none identical. */
39929 static void
39932 {
39935 rtvec v;
39939 {
39942 {
39987 }
40000 {
40015 }
40020 {
40039 }
40044 {
40057 }
40060 half:
40061 /* FIXME: We process inputs backward to help RA. PR 36222. */
40065 {
40070 }
40074 {
40078 {
40082 }
40085 {
40089 }
40092 }
40094 {
40097 {
40101 }
40104 }
40105 else
40111 }
40112 }
40114 /* A subroutine of ix86_expand_vector_init_general. Use vector
40115 interleave to handle the most general case: all values variable,
40116 and none identical. */
40118 static void
40121 {
40130 {
40151 }
40154 {
40155 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40159 /* Insert the SImode value as low element of V4SImode vector. */
40163 op0),
40165 const1_rtx);
40168 /* Cast the V4SImode vector back to a vector in orignal mode. */
40172 /* Load even elements into the second position. */
40176 const1_rtx));
40178 /* Cast vector to FIRST_IMODE vector. */
40181 }
40183 /* Interleave low FIRST_IMODE vectors. */
40185 {
40189 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40192 }
40194 /* Interleave low SECOND_IMODE vectors. */
40196 {
40199 {
40204 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40205 vector. */
40208 }
40211 /* FALLTHRU */
40218 /* Cast the SECOND_IMODE vector back to a vector on original
40219 mode. */
40226 }
40227 }
40229 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40230 all values variable, and none identical. */
40232 static void
40235 {
40241 {
40246 /* FALLTHRU */
40274 half:
40291 /* FALLTHRU */
40297 /* Don't use ix86_expand_vector_init_interleave if we can't
40298 move from GPR to SSE register directly. */
40314 }
40316 {
40328 {
40332 {
40338 else
40339 {
40344 }
40345 }
40348 }
40353 {
40359 }
40361 {
40367 }
40368 else
40370 }
40371 }
40373 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40374 instructions unless MMX_OK is true. */
40376 void
40378 {
40385 rtx x;
40388 {
40398 }
40400 /* Constants are best loaded from the constant pool. */
40402 {
40405 }
40407 /* If all values are identical, broadcast the value. */
40413 /* Values where only one field is non-constant are best loaded from
40414 the pool and overwritten via move later. */
40416 {
40420 one_var))
40425 }
40428 }
40430 void
40432 {
40437 rtx tmp;
40439 = {
40446 };
40448 = {
40455 };
40459 {
40463 {
40468 else
40472 }
40484 else
40490 {
40493 /* For the two element vectors, we implement a VEC_CONCAT with
40494 the extraction of the other element. */
40501 else
40506 }
40515 {
40521 /* tmp = target = A B C D */
40523 /* target = A A B B */
40525 /* target = X A B B */
40527 /* target = A X C D */
40534 /* tmp = target = A B C D */
40536 /* tmp = X B C D */
40538 /* target = A B X D */
40545 /* tmp = target = A B C D */
40547 /* tmp = X B C D */
40549 /* target = A B X D */
40557 }
40565 /* Element 0 handled by vec_merge below. */
40567 {
40570 }
40573 {
40574 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40575 store into element 0, then shuffle them back. */
40592 }
40593 else
40594 {
40595 /* For SSE1, we have to reuse the V4SF code. */
40599 }
40652 half:
40653 /* Compute offset. */
40659 /* Extract the half. */
40663 /* Put val in tmp at elt. */
40666 /* Put it back. */
40672 }
40675 {
40679 }
40680 else
40681 {
40690 }
40691 }
40693 void
40695 {
40699 rtx tmp;
40702 {
40707 /* FALLTHRU */
40720 {
40740 }
40752 {
40754 {
40774 }
40778 }
40779 else
40780 {
40781 /* For SSE1, we have to reuse the V4SF code. */
40785 }
40801 {
40805 else
40809 }
40814 {
40818 else
40822 }
40827 {
40831 else
40835 }
40840 {
40844 else
40848 }
40853 {
40857 else
40861 }
40866 {
40870 else
40874 }
40881 else
40890 else
40899 else
40908 else
40914 /* ??? Could extract the appropriate HImode element and shift. */
40917 }
40920 {
40924 /* Let the rtl optimizers know about the zero extension performed. */
40926 {
40929 }
40932 }
40933 else
40934 {
40941 }
40942 }
40944 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40945 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40946 The upper bits of DEST are undefined, though they shouldn't cause
40947 exceptions (some bits from src or all zeros are ok). */
40949 static void
40951 {
40954 {
40958 else
40976 else
40983 else
40991 {
40996 const1_rtx);
40997 }
40998 else
40999 {
41003 }
41023 else
41045 }
41049 }
41051 /* Expand a vector reduction. FN is the binary pattern to reduce;
41052 DEST is the destination; IN is the input vector. */
41054 void
41056 {
41061 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41065 {
41068 }
41073 {
41078 else
41082 }
41083 }
41084 \f
41085 /* Target hook for scalar_mode_supported_p. */
41086 static bool
41088 {
41093 else
41095 }
41097 /* Implements target hook vector_mode_supported_p. */
41098 static bool
41100 {
41114 }
41116 /* Target hook for c_mode_for_suffix. */
41117 static enum machine_mode
41119 {
41126 }
41128 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41130 We do this in the new i386 backend to maintain source compatibility
41131 with the old cc0-based compiler. */
41133 static tree
41135 tree inputs ATTRIBUTE_UNUSED,
41136 tree clobbers)
41137 {
41139 clobbers);
41141 clobbers);
41143 }
41145 /* Implements target vector targetm.asm.encode_section_info. */
41147 static void ATTRIBUTE_UNUSED
41149 {
41156 }
41158 /* Worker function for REVERSE_CONDITION. */
41160 enum rtx_code
41162 {
41166 }
41168 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41169 to OPERANDS[0]. */
41173 {
41175 {
41178 {
41182 }
41186 }
41188 {
41192 else
41193 {
41194 /* There is no non-popping store to memory for XFmode.
41195 So if we need one, follow the store with a load. */
41198 else
41200 }
41201 }
41202 else
41204 }
41206 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41207 FP status register is set. */
41209 void
41211 {
41213 rtx temp;
41218 {
41223 }
41224 else
41225 {
41230 }
41234 pc_rtx);
41239 }
41241 /* Output code to perform a log1p XFmode calculation. */
41244 {
41250 rtx test;
41256 XFmode));
41270 }
41272 /* Emit code for round calculation. */
41274 {
41281 rtx insn;
41286 {
41298 }
41301 {
41322 }
41330 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41332 /* scratch = fxam(op1) */
41335 UNSPEC_FXAM)));
41336 /* e1 = fabs(op1) */
41339 /* e2 = e1 + 0.5 */
41344 /* res = floor(e2) */
41346 {
41351 }
41352 else
41356 {
41359 {
41366 UNSPEC_TRUNC_NOOP)));
41367 }
41383 }
41385 /* flags = signbit(a) */
41388 /* if (flags) then res = -res */
41392 pc_rtx);
41403 }
41405 /* Output code to perform a Newton-Rhapson approximation of a single precision
41406 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41409 {
41417 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41421 /* x0 = rcp(b) estimate */
41425 UNSPEC_RCP14)));
41426 else
41429 UNSPEC_RCP)));
41431 /* e0 = x0 * b */
41435 /* e0 = x0 * e0 */
41439 /* e1 = x0 + x0 */
41443 /* x1 = e1 - e0 */
41447 /* res = a * x1 */
41450 }
41452 /* Output code to perform a Newton-Rhapson approximation of a
41453 single precision floating point [reciprocal] square root. */
41457 {
41459 REAL_VALUE_TYPE r;
41476 {
41479 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41482 }
41484 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41485 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41489 /* x0 = rsqrt(a) estimate */
41492 unspec)));
41494 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41496 {
41504 /* Handle masked compare. */
41506 {
41508 /* Imm value 0x4 corresponds to not-equal comparison. */
41511 }
41512 else
41513 {
41519 }
41520 }
41522 /* e0 = x0 * a */
41525 /* e1 = e0 * x0 */
41529 /* e2 = e1 - 3. */
41536 /* e3 = -.5 * x0 */
41539 else
41540 /* e3 = -.5 * e0 */
41543 /* ret = e2 * e3 */
41546 }
41548 #ifdef TARGET_SOLARIS
41549 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41551 static void
41553 tree decl)
41554 {
41555 /* With Binutils 2.15, the "@unwind" marker must be specified on
41556 every occurrence of the ".eh_frame" section, not just the first
41557 one. */
41560 {
41564 }
41566 #ifndef USE_GAS
41568 {
41571 }
41572 #endif
41575 }
41578 /* Return the mangling of TYPE if it is an extended fundamental type. */
41582 {
41590 {
41592 /* __float128 is "g". */
41595 /* "long double" or __float80 is "e". */
41599 }
41600 }
41602 /* For 32-bit code we can save PIC register setup by using
41603 __stack_chk_fail_local hidden function instead of calling
41604 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41605 register, so it is better to call __stack_chk_fail directly. */
41607 static tree ATTRIBUTE_UNUSED
41609 {
41610 return TARGET_64BIT
41613 }
41615 /* Select a format to encode pointers in exception handling data. CODE
41616 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41617 true if the symbol may be affected by dynamic relocations.
41619 ??? All x86 object file formats are capable of representing this.
41620 After all, the relocation needed is the same as for the call insn.
41621 Whether or not a particular assembler allows us to enter such, I
41622 guess we'll have to see. */
41623 int
41625 {
41627 {
41634 }
41639 }
41640 \f
41641 /* Expand copysign from SIGN to the positive value ABS_VALUE
41642 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41643 the sign-bit. */
41644 static void
41646 {
41650 {
41657 else
41662 {
41663 /* We need to generate a scalar mode mask in this case. */
41668 }
41669 }
41670 else
41676 }
41678 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41679 mask for masking out the sign-bit is stored in *SMASK, if that is
41680 non-null. */
41681 static rtx
41683 {
41692 else
41696 {
41697 /* We need to generate a scalar mode mask in this case. */
41702 }
41710 }
41712 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41713 swapping the operands if SWAP_OPERANDS is true. The expanded
41714 code is a forward jump to a newly created label in case the
41715 comparison is true. The generated label rtx is returned. */
41716 static rtx
41719 {
41724 {
41728 }
41741 }
41743 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41744 using comparison code CODE. Operands are swapped for the comparison if
41745 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41746 static rtx
41749 {
41755 {
41759 }
41766 }
41768 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41769 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41770 static rtx
41772 {
41773 REAL_VALUE_TYPE TWO52r;
41774 rtx TWO52;
41781 }
41783 /* Expand SSE sequence for computing lround from OP1 storing
41784 into OP0. */
41785 void
41787 {
41788 /* C code for the stuff we're doing below:
41789 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41790 return (long)tmp;
41791 */
41795 rtx adj;
41797 /* load nextafter (0.5, 0.0) */
41802 /* adj = copysign (0.5, op1) */
41806 /* adj = op1 + adj */
41809 /* op0 = (imode)adj */
41811 }
41813 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41814 into OPERAND0. */
41815 void
41817 {
41818 /* C code for the stuff we're doing below (for do_floor):
41819 xi = (long)op1;
41820 xi -= (double)xi > op1 ? 1 : 0;
41821 return xi;
41822 */
41827 /* reg = (long)op1 */
41831 /* freg = (double)reg */
41835 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41846 }
41848 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41849 result in OPERAND0. */
41850 void
41852 {
41853 /* C code for the stuff we're doing below:
41854 xa = fabs (operand1);
41855 if (!isless (xa, 2**52))
41856 return operand1;
41857 xa = xa + 2**52 - 2**52;
41858 return copysign (xa, operand1);
41859 */
41866 /* xa = abs (operand1) */
41869 /* if (!isless (xa, TWO52)) goto label; */
41882 }
41884 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41885 into OPERAND0. */
41886 void
41888 {
41889 /* C code for the stuff we expand below.
41890 double xa = fabs (x), x2;
41891 if (!isless (xa, TWO52))
41892 return x;
41893 xa = xa + TWO52 - TWO52;
41894 x2 = copysign (xa, x);
41895 Compensate. Floor:
41896 if (x2 > x)
41897 x2 -= 1;
41898 Compensate. Ceil:
41899 if (x2 < x)
41900 x2 -= -1;
41901 return x2;
41902 */
41908 /* Temporary for holding the result, initialized to the input
41909 operand to ease control flow. */
41913 /* xa = abs (operand1) */
41916 /* if (!isless (xa, TWO52)) goto label; */
41919 /* xa = xa + TWO52 - TWO52; */
41923 /* xa = copysign (xa, operand1) */
41926 /* generate 1.0 or -1.0 */
41931 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41935 /* We always need to subtract here to preserve signed zero. */
41944 }
41946 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41947 into OPERAND0. */
41948 void
41950 {
41951 /* C code for the stuff we expand below.
41952 double xa = fabs (x), x2;
41953 if (!isless (xa, TWO52))
41954 return x;
41955 x2 = (double)(long)x;
41956 Compensate. Floor:
41957 if (x2 > x)
41958 x2 -= 1;
41959 Compensate. Ceil:
41960 if (x2 < x)
41961 x2 += 1;
41962 if (HONOR_SIGNED_ZEROS (mode))
41963 return copysign (x2, x);
41964 return x2;
41965 */
41971 /* Temporary for holding the result, initialized to the input
41972 operand to ease control flow. */
41976 /* xa = abs (operand1) */
41979 /* if (!isless (xa, TWO52)) goto label; */
41982 /* xa = (double)(long)x */
41987 /* generate 1.0 */
41990 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42005 }
42007 /* Expand SSE sequence for computing round from OPERAND1 storing
42008 into OPERAND0. Sequence that works without relying on DImode truncation
42009 via cvttsd2siq that is only available on 64bit targets. */
42010 void
42012 {
42013 /* C code for the stuff we expand below.
42014 double xa = fabs (x), xa2, x2;
42015 if (!isless (xa, TWO52))
42016 return x;
42017 Using the absolute value and copying back sign makes
42018 -0.0 -> -0.0 correct.
42019 xa2 = xa + TWO52 - TWO52;
42020 Compensate.
42021 dxa = xa2 - xa;
42022 if (dxa <= -0.5)
42023 xa2 += 1;
42024 else if (dxa > 0.5)
42025 xa2 -= 1;
42026 x2 = copysign (xa2, x);
42027 return x2;
42028 */
42034 /* Temporary for holding the result, initialized to the input
42035 operand to ease control flow. */
42039 /* xa = abs (operand1) */
42042 /* if (!isless (xa, TWO52)) goto label; */
42045 /* xa2 = xa + TWO52 - TWO52; */
42049 /* dxa = xa2 - xa; */
42052 /* generate 0.5, 1.0 and -0.5 */
42058 /* Compensate. */
42060 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42065 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42071 /* res = copysign (xa2, operand1) */
42078 }
42080 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42081 into OPERAND0. */
42082 void
42084 {
42085 /* C code for SSE variant we expand below.
42086 double xa = fabs (x), x2;
42087 if (!isless (xa, TWO52))
42088 return x;
42089 x2 = (double)(long)x;
42090 if (HONOR_SIGNED_ZEROS (mode))
42091 return copysign (x2, x);
42092 return x2;
42093 */
42099 /* Temporary for holding the result, initialized to the input
42100 operand to ease control flow. */
42104 /* xa = abs (operand1) */
42107 /* if (!isless (xa, TWO52)) goto label; */
42110 /* x = (double)(long)x */
42122 }
42124 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42125 into OPERAND0. */
42126 void
42128 {
42132 /* C code for SSE variant we expand below.
42133 double xa = fabs (x), x2;
42134 if (!isless (xa, TWO52))
42135 return x;
42136 xa2 = xa + TWO52 - TWO52;
42137 Compensate:
42138 if (xa2 > xa)
42139 xa2 -= 1.0;
42140 x2 = copysign (xa2, x);
42141 return x2;
42142 */
42146 /* Temporary for holding the result, initialized to the input
42147 operand to ease control flow. */
42151 /* xa = abs (operand1) */
42154 /* if (!isless (xa, TWO52)) goto label; */
42157 /* res = xa + TWO52 - TWO52; */
42162 /* generate 1.0 */
42165 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42173 /* res = copysign (res, operand1) */
42180 }
42182 /* Expand SSE sequence for computing round from OPERAND1 storing
42183 into OPERAND0. */
42184 void
42186 {
42187 /* C code for the stuff we're doing below:
42188 double xa = fabs (x);
42189 if (!isless (xa, TWO52))
42190 return x;
42191 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42192 return copysign (xa, x);
42193 */
42199 /* Temporary for holding the result, initialized to the input
42200 operand to ease control flow. */
42208 /* load nextafter (0.5, 0.0) */
42213 /* xa = xa + 0.5 */
42217 /* xa = (double)(int64_t)xa */
42222 /* res = copysign (xa, operand1) */
42229 }
42231 /* Expand SSE sequence for computing round
42232 from OP1 storing into OP0 using sse4 round insn. */
42233 void
42235 {
42244 {
42255 }
42257 /* round (a) = trunc (a + copysign (0.5, a)) */
42259 /* load nextafter (0.5, 0.0) */
42265 /* e1 = copysign (0.5, op1) */
42269 /* e2 = op1 + e1 */
42272 /* res = trunc (e2) */
42277 }
42278 \f
42280 /* Table of valid machine attributes. */
42282 {
42283 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42284 affects_type_identity } */
42285 /* Stdcall attribute says callee is responsible for popping arguments
42286 if they are not variable. */
42289 /* Fastcall attribute says callee is responsible for popping arguments
42290 if they are not variable. */
42293 /* Thiscall attribute says callee is responsible for popping arguments
42294 if they are not variable. */
42297 /* Cdecl attribute says the callee is a normal C declaration */
42300 /* Regparm attribute specifies how many integer arguments are to be
42301 passed in registers. */
42304 /* Sseregparm attribute says we are using x86_64 calling conventions
42305 for FP arguments. */
42308 /* The transactional memory builtins are implicitly regparm or fastcall
42309 depending on the ABI. Override the generic do-nothing attribute that
42310 these builtins were declared with. */
42313 /* force_align_arg_pointer says this function realigns the stack at entry. */
42316 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42321 #endif
42326 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42327 SUBTARGET_ATTRIBUTE_TABLE,
42328 #endif
42329 /* ms_abi and sysv_abi calling convention function attributes. */
42336 /* End element. */
42338 };
42340 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42341 static int
42343 tree vectype,
42345 {
42349 {
42394 }
42395 }
42397 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42398 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42399 insn every time. */
42403 /* Initialize vselect_insn. */
42405 static void
42407 {
42409 rtx x;
42420 }
42422 /* Construct (set target (vec_select op0 (parallel perm))) and
42423 return true if that's a valid instruction in the active ISA. */
42425 static bool
42428 {
42454 }
42456 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42458 static bool
42462 {
42464 rtx x;
42479 }
42481 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42482 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42484 static bool
42486 {
42495 ;
42497 ;
42499 ;
42500 else
42503 /* This is a blend, not a permute. Elements must stay in their
42504 respective lanes. */
42506 {
42510 }
42515 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42516 decision should be extracted elsewhere, so that we only try that
42517 sequence once all budget==3 options have been tried. */
42524 {
42548 /* See if bytes move in pairs so we can use pblendw with
42549 an immediate argument, rather than pblendvb with a vector
42550 argument. */
42553 {
42554 use_pblendvb:
42558 finish_pblendvb:
42564 else
42569 }
42574 /* FALLTHRU */
42576 do_subreg:
42583 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42587 /* See if bytes move in quadruplets. If yes, vpblendd
42588 with immediate can be used. */
42593 {
42594 /* See if bytes move the same in both lanes. If yes,
42595 vpblendw with immediate can be used. */
42600 /* Use vpblendw. */
42605 }
42607 /* Use vpblendd. */
42614 /* See if words move in pairs. If yes, vpblendd can be used. */
42619 {
42620 /* See if words move the same in both lanes. If not,
42621 vpblendvb must be used. */
42624 {
42625 /* Use vpblendvb. */
42635 }
42637 /* Use vpblendw. */
42641 }
42643 /* Use vpblendd. */
42650 /* Use vpblendd. */
42658 }
42660 /* This matches five different patterns with the different modes. */
42668 }
42670 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42671 in terms of the variable form of vpermilps.
42673 Note that we will have already failed the immediate input vpermilps,
42674 which requires that the high and low part shuffle be identical; the
42675 variable form doesn't require that. */
42677 static bool
42679 {
42686 /* We can only permute within the 128-bit lane. */
42688 {
42692 }
42698 {
42701 /* Within each 128-bit lane, the elements of op0 are numbered
42702 from 0 and the elements of op1 are numbered from 4. */
42709 }
42716 }
42718 /* Return true if permutation D can be performed as VMODE permutation
42719 instead. */
42721 static bool
42723 {
42738 else
42744 }
42746 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42747 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42749 static bool
42751 {
42760 {
42762 {
42765 {
42769 /* Use vperm2i128 insn. The pattern uses
42770 V4DImode instead of V2TImode. */
42783 }
42785 }
42786 }
42787 else
42788 {
42790 {
42793 }
42795 {
42799 /* V4DImode should be already handled through
42800 expand_vselect by vpermq instruction. */
42807 {
42808 /* First see if vpermq can be used for
42809 V8SImode/V16HImode/V32QImode. */
42811 {
42819 {
42823 }
42825 }
42827 /* Next see if vpermd can be used. */
42830 }
42831 /* Or if vpermps can be used. */
42836 {
42837 /* vpshufb only works intra lanes, it is not
42838 possible to shuffle bytes in between the lanes. */
42842 }
42843 }
42844 else
42846 }
42854 else
42855 {
42861 else
42865 {
42869 }
42870 }
42881 {
42888 else
42890 }
42891 else
42892 {
42895 }
42900 }
42902 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42903 in a single instruction. */
42905 static bool
42907 {
42911 /* Check plain VEC_SELECT first, because AVX has instructions that could
42912 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42913 input where SEL+CONCAT may not. */
42915 {
42921 {
42927 }
42930 {
42934 }
42936 {
42937 /* Use vpbroadcast{b,w,d}. */
42940 {
42959 /* For other modes prefer other shuffles this function creates. */
42961 }
42963 {
42967 }
42968 }
42973 /* There are plenty of patterns in sse.md that are written for
42974 SEL+CONCAT and are not replicated for a single op. Perhaps
42975 that should be changed, to avoid the nastiness here. */
42977 /* Recognize interleave style patterns, which means incrementing
42978 every other permutation operand. */
42980 {
42983 }
42988 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
42990 {
42992 {
42997 }
43002 }
43003 }
43005 /* Finally, try the fully general two operand permute. */
43010 /* Recognize interleave style patterns with reversed operands. */
43012 {
43014 {
43018 else
43021 }
43026 }
43028 /* Try the SSE4.1 blend variable merge instructions. */
43032 /* Try one of the AVX vpermil variable permutations. */
43036 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43037 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43041 /* Try the AVX512F vpermi2 instructions. */
43055 }
43057 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43058 in terms of a pair of pshuflw + pshufhw instructions. */
43060 static bool
43062 {
43070 /* The two permutations only operate in 64-bit lanes. */
43081 /* Emit the pshuflw. */
43088 /* Emit the pshufhw. */
43096 }
43098 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43099 the permutation using the SSSE3 palignr instruction. This succeeds
43100 when all of the elements in PERM fit within one vector and we merely
43101 need to shift them down so that a single vector permutation has a
43102 chance to succeed. */
43104 static bool
43106 {
43113 /* Even with AVX, palignr only operates on 128-bit vectors. */
43119 {
43125 }
43129 /* Given that we have SSSE3, we know we'll be able to implement the
43130 single operand permutation after the palignr with pshufb. */
43145 {
43150 }
43152 /* Test for the degenerate case where the alignment by itself
43153 produces the desired permutation. */
43155 {
43158 }
43164 }
43168 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43169 a two vector permutation into a single vector permutation by using
43170 an interleave operation to merge the vectors. */
43172 static bool
43174 {
43179 rtx seq;
43183 {
43186 }
43188 {
43191 /* For 32-byte modes allow even d->one_operand_p.
43192 The lack of cross-lane shuffling in some instructions
43193 might prevent a single insn shuffle. */
43196 /* If expand_vec_perm_interleave3 can expand this into
43197 a 3 insn sequence, give up and let it be expanded as
43198 3 insn sequence. While that is one insn longer,
43199 it doesn't need a memory operand and in the common
43200 case that both interleave low and high permutations
43201 with the same operands are adjacent needs 4 insns
43202 for both after CSE. */
43205 }
43206 else
43209 /* Examine from whence the elements come. */
43218 {
43221 /* Split the two input vectors into 4 halves. */
43227 /* If the elements from the low halves use interleave low, and similarly
43228 for interleave high. If the elements are from mis-matched halves, we
43229 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43231 {
43232 /* punpckl* */
43234 {
43239 }
43242 }
43244 {
43245 /* punpckh* */
43247 {
43252 }
43255 }
43257 {
43258 /* shufps */
43260 {
43265 }
43267 {
43268 /* shufpd */
43273 }
43274 }
43276 {
43277 /* shufps */
43279 {
43284 }
43286 {
43287 /* shufpd */
43292 }
43293 }
43294 else
43296 }
43297 else
43298 {
43303 /* Split the two input vectors into 8 quarters. */
43309 {
43312 }
43315 {
43319 }
43321 {
43324 }
43327 {
43329 {
43330 /* Attempt to increase the likelihood that dfinal
43331 shuffle will be intra-lane. */
43335 }
43337 /* vperm2f128 or vperm2i128. */
43339 {
43344 }
43349 {
43353 {
43356 }
43357 }
43358 }
43363 {
43364 /* vpunpckl* */
43366 {
43375 }
43376 }
43379 {
43380 /* vpunpckh* */
43382 {
43391 }
43392 }
43393 else
43395 }
43397 /* Use the remapping array set up above to move the elements from their
43398 swizzled locations into their final destinations. */
43401 {
43404 /* If same_halves is true, both halves of the remapped vector are the
43405 same. Avoid cross-lane accesses if possible. */
43407 {
43410 }
43411 else
43413 }
43419 /* Test if the final remap can be done with a single insn. For V4SFmode or
43420 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43433 {
43436 }
43443 }
43445 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43446 a single vector cross-lane permutation into vpermq followed
43447 by any of the single insn permutations. */
43449 static bool
43451 {
43465 {
43468 }
43471 {
43476 }
43489 {
43496 }
43503 {
43508 ;
43511 else
43513 }
43522 }
43524 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43525 a vector permutation using two instructions, vperm2f128 resp.
43526 vperm2i128 followed by any single in-lane permutation. */
43528 static bool
43530 {
43544 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43545 immediate. For perm < 16 the second permutation uses
43546 d->op0 as first operand, for perm >= 16 it uses d->op1
43547 as first operand. The second operand is the result of
43548 vperm2[fi]128. */
43550 {
43551 /* Ignore permutations which do not move anything cross-lane. */
43553 {
43554 /* The second shuffle for e.g. V4DFmode has
43555 0123 and ABCD operands.
43556 Ignore AB23, as 23 is already in the second lane
43557 of the first operand. */
43559 /* And 01CD, as 01 is in the first lane of the first
43560 operand. */
43562 /* And 4567, as then the vperm2[fi]128 doesn't change
43563 anything on the original 4567 second operand. */
43565 }
43566 else
43567 {
43568 /* The second shuffle for e.g. V4DFmode has
43569 4567 and ABCD operands.
43570 Ignore AB67, as 67 is already in the second lane
43571 of the first operand. */
43573 /* And 45CD, as 45 is in the first lane of the first
43574 operand. */
43576 /* And 0123, as then the vperm2[fi]128 doesn't change
43577 anything on the original 0123 first operand. */
43579 }
43582 {
43588 else
43590 }
43593 {
43597 }
43598 else
43602 {
43606 /* Found a usable second shuffle. dfirst will be
43607 vperm2f128 on d->op0 and d->op1. */
43618 /* And dsecond is some single insn shuffle, taking
43619 d->op0 and result of vperm2f128 (if perm < 16) or
43620 d->op1 and result of vperm2f128 (otherwise). */
43629 }
43631 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43634 }
43637 }
43639 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43640 a two vector permutation using 2 intra-lane interleave insns
43641 and cross-lane shuffle for 32-byte vectors. */
43643 static bool
43645 {
43652 ;
43654 ;
43655 else
43670 {
43674 else
43680 else
43686 else
43692 else
43698 else
43704 else
43709 }
43713 }
43715 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43716 a single vector permutation using a single intra-lane vector
43717 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43718 the non-swapped and swapped vectors together. */
43720 static bool
43722 {
43725 rtx seq;
43730 || TARGET_AVX2
43739 {
43746 }
43781 }
43783 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43784 permutation using two vperm2f128, followed by a vshufpd insn blending
43785 the two vectors together. */
43787 static bool
43789 {
43832 }
43834 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43835 permutation with two pshufb insns and an ior. We should have already
43836 failed all two instruction sequences. */
43838 static bool
43840 {
43851 /* Generate two permutation masks. If the required element is within
43852 the given vector it is shuffled into the proper lane. If the required
43853 element is in the other vector, force a zero into the lane by setting
43854 bit 7 in the permutation mask. */
43857 {
43864 {
43867 }
43868 }
43892 }
43894 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
43895 with two vpshufb insns, vpermq and vpor. We should have already failed
43896 all two or three instruction sequences. */
43898 static bool
43900 {
43915 /* Generate two permutation masks. If the required element is within
43916 the same lane, it is shuffled in. If the required element from the
43917 other lane, force a zero by setting bit 7 in the permutation mask.
43918 In the other mask the mask has non-negative elements if element
43919 is requested from the other lane, but also moved to the other lane,
43920 so that the result of vpshufb can have the two V2TImode halves
43921 swapped. */
43924 {
43929 {
43932 }
43933 }
43942 /* Swap the 128-byte lanes of h into hp. */
43946 const1_rtx));
43963 }
43965 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
43966 and extract-odd permutations of two V32QImode and V16QImode operand
43967 with two vpshufb insns, vpor and vpermq. We should have already
43968 failed all two or three instruction sequences. */
43970 static bool
43972 {
43991 /* Generate two permutation masks. In the first permutation mask
43992 the first quarter will contain indexes for the first half
43993 of the op0, the second quarter will contain bit 7 set, third quarter
43994 will contain indexes for the second half of the op0 and the
43995 last quarter bit 7 set. In the second permutation mask
43996 the first quarter will contain bit 7 set, the second quarter
43997 indexes for the first half of the op1, the third quarter bit 7 set
43998 and last quarter indexes for the second half of the op1.
43999 I.e. the first mask e.g. for V32QImode extract even will be:
44000 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44001 (all values masked with 0xf except for -128) and second mask
44002 for extract even will be
44003 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44006 {
44012 {
44015 }
44016 }
44035 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44043 }
44045 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44046 and extract-odd permutations. */
44048 static bool
44050 {
44054 {
44059 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44063 /* Now an unpck[lh]pd will produce the result required. */
44066 else
44072 {
44079 /* Shuffle within the 128-bit lanes to produce:
44080 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44084 /* Shuffle the lanes around to produce:
44085 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44089 /* Shuffle within the 128-bit lanes to produce:
44090 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44093 /* Shuffle within the 128-bit lanes to produce:
44094 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44097 /* Shuffle the lanes around to produce:
44098 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44101 }
44108 /* These are always directly implementable by expand_vec_perm_1. */
44114 else
44115 {
44116 /* We need 2*log2(N)-1 operations to achieve odd/even
44117 with interleave. */
44126 else
44129 }
44135 else
44136 {
44148 else
44151 }
44160 {
44167 {
44172 }
44174 }
44179 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44183 /* Now an vpunpck[lh]qdq will produce the result required. */
44186 else
44193 {
44200 {
44205 }
44207 }
44215 /* Shuffle the lanes around into
44216 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44224 /* Swap the 2nd and 3rd position in each lane into
44225 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44231 /* Now an vpunpck[lh]qdq will produce
44232 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44236 else
44245 }
44248 }
44250 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44251 extract-even and extract-odd permutations. */
44253 static bool
44255 {
44267 }
44269 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44270 permutations. We assume that expand_vec_perm_1 has already failed. */
44272 static bool
44274 {
44282 {
44285 /* These are special-cased in sse.md so that we can optionally
44286 use the vbroadcast instruction. They expand to two insns
44287 if the input happens to be in a register. */
44294 /* These are always implementable using standard shuffle patterns. */
44299 /* These can be implemented via interleave. We save one insn by
44300 stopping once we have promoted to V4SImode and then use pshufd. */
44301 do
44302 {
44303 rtx dest;
44309 {
44313 }
44320 }
44335 /* For AVX2 broadcasts of the first element vpbroadcast* or
44336 vpermq should be used by expand_vec_perm_1. */
44342 }
44343 }
44345 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44346 broadcast permutations. */
44348 static bool
44350 {
44362 }
44364 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44365 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44366 all the shorter instruction sequences. */
44368 static bool
44370 {
44386 /* Generate 4 permutation masks. If the required element is within
44387 the same lane, it is shuffled in. If the required element from the
44388 other lane, force a zero by setting bit 7 in the permutation mask.
44389 In the other mask the mask has non-negative elements if element
44390 is requested from the other lane, but also moved to the other lane,
44391 so that the result of vpshufb can have the two V2TImode halves
44392 swapped. */
44395 {
44400 }
44406 {
44414 }
44417 {
44419 {
44422 }
44429 }
44431 /* Swap the 128-byte lanes of h[X]. */
44433 {
44439 const1_rtx));
44441 }
44444 {
44446 {
44449 }
44455 }
44458 {
44460 {
44464 }
44467 }
44477 }
44479 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44480 With all of the interface bits taken care of, perform the expansion
44481 in D and return true on success. */
44483 static bool
44485 {
44486 /* Try a single instruction expansion. */
44490 /* Try sequences of two instructions. */
44510 /* Try sequences of three instructions. */
44524 /* Try sequences of four instructions. */
44532 /* ??? Look for narrow permutations whose element orderings would
44533 allow the promotion to a wider mode. */
44535 /* ??? Look for sequences of interleave or a wider permute that place
44536 the data into the correct lanes for a half-vector shuffle like
44537 pshuf[lh]w or vpermilps. */
44539 /* ??? Look for sequences of interleave that produce the desired results.
44540 The combinatorics of punpck[lh] get pretty ugly... */
44545 /* Even longer sequences. */
44550 }
44552 /* If a permutation only uses one operand, make it clear. Returns true
44553 if the permutation references both operands. */
44555 static bool
44557 {
44565 {
44571 {
44574 }
44575 /* The elements of PERM do not suggest that only the first operand
44576 is used, but both operands are identical. Allow easier matching
44577 of the permutation by folding the permutation into the single
44578 input vector. */
44579 /* FALLTHRU */
44590 }
44593 }
44595 bool
44597 {
44602 rtx sel;
44619 {
44624 }
44631 /* If the selector says both arguments are needed, but the operands are the
44632 same, the above tried to expand with one_operand_p and flattened selector.
44633 If that didn't work, retry without one_operand_p; we succeeded with that
44634 during testing. */
44636 {
44640 }
44643 }
44645 /* Implement targetm.vectorize.vec_perm_const_ok. */
44647 static bool
44650 {
44659 /* Given sufficient ISA support we can just return true here
44660 for selected vector modes. */
44663 /* All implementable with a single vpermi2 insn. */
44666 {
44667 /* All implementable with a single vpperm insn. */
44670 /* All implementable with 2 pshufb + 1 ior. */
44673 /* All implementable with shufpd or unpck[lh]pd. */
44676 }
44678 /* Extract the values from the vector CST into the permutation
44679 array in D. */
44682 {
44686 }
44688 /* For all elements from second vector, fold the elements to first. */
44693 /* Check whether the mask can be applied to the vector type. */
44696 /* Implementable with shufps or pshufd. */
44700 /* Otherwise we have to go through the motions and see if we can
44701 figure out how to generate the requested permutation. */
44712 }
44714 void
44716 {
44731 /* We'll either be able to implement the permutation directly... */
44735 /* ... or we use the special-case patterns. */
44737 }
44739 static void
44741 {
44756 {
44759 }
44761 /* Note that for AVX this isn't one instruction. */
44764 }
44767 /* Expand a vector operation CODE for a V*QImode in terms of the
44768 same operation on V*HImode. */
44770 void
44772 {
44784 {
44797 }
44801 {
44803 /* Unpack data such that we've got a source byte in each low byte of
44804 each word. We don't care what goes into the high byte of each word.
44805 Rather than trying to get zero in there, most convenient is to let
44806 it be a copy of the low byte. */
44811 /* FALLTHRU */
44823 /* FALLTHRU */
44833 }
44835 /* Perform the operation. */
44842 /* Merge the data back into the right place. */
44852 {
44853 /* For SSE2, we used an full interleave, so the desired
44854 results are in the even elements. */
44857 }
44858 else
44859 {
44860 /* For AVX, the interleave used above was not cross-lane. So the
44861 extraction is evens but with the second and third quarter swapped.
44862 Happily, that is even one insn shorter than even extraction. */
44865 }
44872 }
44874 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
44875 if op is CONST_VECTOR with all odd elements equal to their
44876 preceding element. */
44878 static bool
44880 {
44890 }
44892 void
44895 {
44898 rtx x;
44906 /* We only play even/odd games with vectors of SImode. */
44909 /* If we're looking for the odd results, shift those members down to
44910 the even slots. For some cpus this is faster than a PSHUFD. */
44912 {
44913 /* For XOP use vpmacsdqh, but only for smult, as it is only
44914 signed. */
44916 {
44920 }
44931 }
44934 {
44937 else
44939 }
44941 {
44944 else
44946 }
44951 else
44952 {
44955 /* The easiest way to implement this without PMULDQ is to go through
44956 the motions as if we are performing a full 64-bit multiply. With
44957 the exception that we need to do less shuffling of the elements. */
44959 /* Compute the sign-extension, aka highparts, of the two operands. */
44965 /* Multiply LO(A) * HI(B), and vice-versa. */
44971 /* Multiply LO(A) * LO(B). */
44975 /* Combine and shift the highparts into place. */
44980 /* Combine high and low parts. */
44983 }
44985 }
44987 void
44990 {
44996 {
45001 {
45002 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45003 shuffle the elements once so that all elements are in the right
45004 place for immediate use: { A C B D }. */
45009 }
45010 else
45011 {
45012 /* Put the elements into place for the multiply. */
45016 }
45021 /* Shuffle the elements between the lanes. After this we
45022 have { A B E F | C D G H } for each operand. */
45032 /* Shuffle the elements within the lanes. After this we
45033 have { A A B B | C C D D } or { E E F F | G G H H }. */
45071 }
45072 }
45074 void
45076 {
45086 /* Move the results in element 2 down to element 1; we don't care
45087 what goes in elements 2 and 3. Then we can merge the parts
45088 back together with an interleave.
45090 Note that two other sequences were tried:
45091 (1) Use interleaves at the start instead of psrldq, which allows
45092 us to use a single shufps to merge things back at the end.
45093 (2) Use shufps here to combine the two vectors, then pshufd to
45094 put the elements in the correct order.
45095 In both cases the cost of the reformatting stall was too high
45096 and the overall sequence slower. */
45107 }
45109 void
45111 {
45116 {
45117 /* op1: A,B,C,D, op2: E,F,G,H */
45126 /* t1: B,A,D,C */
45133 /* t2: (B*E),(A*F),(D*G),(C*H) */
45136 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45139 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45142 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
45144 }
45145 else
45146 {
45151 {
45154 }
45156 {
45159 }
45161 {
45164 }
45165 else
45169 /* Multiply low parts. */
45173 /* Shift input vectors right 32 bits so we can multiply high parts. */
45178 /* Multiply high parts by low parts. */
45184 /* Combine and shift the highparts back. */
45188 /* Combine high and low parts. */
45190 }
45194 }
45196 /* Calculate integer abs() using only SSE2 instructions. */
45198 void
45200 {
45205 {
45206 /* For 32-bit signed integer X, the best way to calculate the absolute
45207 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45219 /* For 16-bit signed integer X, the best way to calculate the absolute
45220 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45228 /* For 8-bit signed integer X, the best way to calculate the absolute
45229 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45230 as SSE2 provides the PMINUB insn. */
45240 }
45244 }
45246 /* Expand an insert into a vector register through pinsr insn.
45247 Return true if successful. */
45249 bool
45251 {
45259 {
45262 }
45268 {
45273 {
45280 {
45312 }
45326 }
45330 }
45331 }
45332 \f
45333 /* This function returns the calling abi specific va_list type node.
45334 It returns the FNDECL specific va_list type. */
45336 static tree
45338 {
45345 else
45347 }
45349 /* Returns the canonical va_list type specified by TYPE. If there
45350 is no valid TYPE provided, it return NULL_TREE. */
45352 static tree
45354 {
45357 /* Resolve references and pointers to va_list type. */
45366 {
45371 {
45372 /* If va_list is an array type, the argument may have decayed
45373 to a pointer type, e.g. by being passed to another function.
45374 In that case, unwrap both types so that we can compare the
45375 underlying records. */
45378 {
45381 }
45382 }
45389 {
45390 /* If va_list is an array type, the argument may have decayed
45391 to a pointer type, e.g. by being passed to another function.
45392 In that case, unwrap both types so that we can compare the
45393 underlying records. */
45396 {
45399 }
45400 }
45407 {
45408 /* If va_list is an array type, the argument may have decayed
45409 to a pointer type, e.g. by being passed to another function.
45410 In that case, unwrap both types so that we can compare the
45411 underlying records. */
45414 {
45417 }
45418 }
45422 }
45424 }
45426 /* Iterate through the target-specific builtin types for va_list.
45427 IDX denotes the iterator, *PTREE is set to the result type of
45428 the va_list builtin, and *PNAME to its internal type.
45429 Returns zero if there is no element for this index, otherwise
45430 IDX should be increased upon the next call.
45431 Note, do not iterate a base builtin's name like __builtin_va_list.
45432 Used from c_common_nodes_and_builtins. */
45434 static int
45436 {
45438 {
45440 {
45453 }
45454 }
45457 }
45459 #undef TARGET_SCHED_DISPATCH
45460 #define TARGET_SCHED_DISPATCH has_dispatch
45461 #undef TARGET_SCHED_DISPATCH_DO
45462 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45463 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45464 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45465 #undef TARGET_SCHED_REORDER
45466 #define TARGET_SCHED_REORDER ix86_sched_reorder
45467 #undef TARGET_SCHED_ADJUST_PRIORITY
45468 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45469 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45470 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45471 ix86_dependencies_evaluation_hook
45473 /* The size of the dispatch window is the total number of bytes of
45474 object code allowed in a window. */
45475 #define DISPATCH_WINDOW_SIZE 16
45477 /* Number of dispatch windows considered for scheduling. */
45478 #define MAX_DISPATCH_WINDOWS 3
45480 /* Maximum number of instructions in a window. */
45481 #define MAX_INSN 4
45483 /* Maximum number of immediate operands in a window. */
45484 #define MAX_IMM 4
45486 /* Maximum number of immediate bits allowed in a window. */
45487 #define MAX_IMM_SIZE 128
45489 /* Maximum number of 32 bit immediates allowed in a window. */
45490 #define MAX_IMM_32 4
45492 /* Maximum number of 64 bit immediates allowed in a window. */
45493 #define MAX_IMM_64 2
45495 /* Maximum total of loads or prefetches allowed in a window. */
45496 #define MAX_LOAD 2
45498 /* Maximum total of stores allowed in a window. */
45499 #define MAX_STORE 1
45501 #undef BIG
45502 #define BIG 100
45505 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45508 disp_load,
45509 disp_store,
45510 disp_load_store,
45511 disp_prefetch,
45512 disp_imm,
45513 disp_imm_32,
45514 disp_imm_64,
45515 disp_branch,
45516 disp_cmp,
45517 disp_jcc,
45518 disp_last
45519 };
45521 /* Number of allowable groups in a dispatch window. It is an array
45522 indexed by dispatch_group enum. 100 is used as a big number,
45523 because the number of these kind of operations does not have any
45524 effect in dispatch window, but we need them for other reasons in
45525 the table. */
45528 };
45534 };
45536 /* Instruction path. */
45542 last_path
45543 };
45545 /* sched_insn_info defines a window to the instructions scheduled in
45546 the basic block. It contains a pointer to the insn_info table and
45547 the instruction scheduled.
45549 Windows are allocated for each basic block and are linked
45550 together. */
45552 rtx insn;
45559 /* Linked list of dispatch windows. This is a two way list of
45560 dispatch windows of a basic block. It contains information about
45561 the number of uops in the window and the total number of
45562 instructions and of bytes in the object code for this dispatch
45563 window. */
45581 /* Immediate valuse used in an insn. */
45583 {
45592 /* Get dispatch group of insn. */
45594 static enum dispatch_group
45596 {
45612 }
45614 /* Return true if insn is a compare instruction. */
45616 static bool
45618 {
45626 }
45628 /* Return true if a dispatch violation encountered. */
45630 static bool
45632 {
45636 }
45638 /* Return true if insn is a branch instruction. */
45640 static bool
45642 {
45644 }
45646 /* Return true if insn is a prefetch instruction. */
45648 static bool
45650 {
45652 }
45654 /* This function initializes a dispatch window and the list container holding a
45655 pointer to the window. */
45657 static void
45659 {
45665 else
45683 {
45689 }
45691 }
45693 /* This function allocates and initializes a dispatch window and the
45694 list container holding a pointer to the window. */
45698 {
45703 }
45705 /* This routine initializes the dispatch scheduling information. It
45706 initiates building dispatch scheduler tables and constructs the
45707 first dispatch window. */
45709 static void
45711 {
45712 /* Allocate a dispatch list and a window. */
45717 }
45719 /* This function returns true if a branch is detected. End of a basic block
45720 does not have to be a branch, but here we assume only branches end a
45721 window. */
45723 static bool
45725 {
45727 }
45729 /* This function is called when the end of a window processing is reached. */
45731 static void
45733 {
45736 {
45741 }
45743 }
45745 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45746 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45747 for 48 bytes of instructions. Note that these windows are not dispatch
45748 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45752 {
45754 {
45759 }
45765 }
45767 /* Increment the number of immediate operands of an instruction. */
45769 static int
45771 {
45776 {
45783 else
45794 {
45797 }
45802 }
45805 }
45807 /* Compute number of immediate operands of an instruction. */
45809 static void
45811 {
45814 }
45816 /* Return total size of immediate operands of an instruction along with number
45817 of corresponding immediate-operands. It initializes its parameters to zero
45818 befor calling FIND_CONSTANT.
45819 INSN is the input instruction. IMM is the total of immediates.
45820 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45821 bit immediates. */
45823 static int
45825 {
45833 }
45835 /* This function indicates if an operand of an instruction is an
45836 immediate. */
45838 static bool
45840 {
45849 }
45851 /* Return single or double path for instructions. */
45853 static enum insn_path
45855 {
45865 }
45867 /* Return insn dispatch group. */
45869 static enum dispatch_group
45871 {
45889 }
45891 /* Count number of GROUP restricted instructions in a dispatch
45892 window WINDOW_LIST. */
45894 static int
45896 {
45907 {
45926 }
45939 }
45941 /* This function returns true if insn satisfies dispatch rules on the
45942 last window scheduled. */
45944 static bool
45946 {
45954 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
45955 instructions should be given the lowest priority in the
45956 scheduling process in Haifa scheduler to make sure they will be
45957 scheduled in the same dispatch window as the reference to them. */
45961 /* Check nonrestricted. */
45965 /* Get last dispatch window. */
45970 {
45975 /* Window 1 is full. Go for next window. */
45977 }
45984 /* See if it fits in the first window. */
45986 {
45987 /* The first widow should have only single and double path
45988 uops. */
45994 }
45996 }
45998 /* Add an instruction INSN with NUM_UOPS micro-operations to the
45999 dispatch window WINDOW_LIST. */
46001 static void
46003 {
46021 /* Initialize window with new instruction. */
46042 {
46045 }
46046 }
46048 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46049 If the total bytes of instructions or the number of instructions in
46050 the window exceed allowable, it allocates a new window. */
46052 static void
46054 {
46077 /* Get the last dispatch window. */
46085 else
46088 /* If current window is full, get a new window.
46089 Window number zero is full, if MAX_INSN uops are scheduled in it.
46090 Window number one is full, if window zero's bytes plus window
46091 one's bytes is 32, or if the bytes of the new instruction added
46092 to the total makes it greater than 48, or it has already MAX_INSN
46093 instructions in it. */
46102 {
46105 }
46108 {
46112 {
46115 }
46116 }
46118 {
46123 {
46126 }
46129 }
46130 else
46134 {
46135 /* End of basic block is reached do end-basic-block process. */
46138 }
46139 }
46141 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46143 DEBUG_FUNCTION static void
46145 {
46151 else
46165 {
46168 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46174 }
46175 }
46177 /* Print to stdout a dispatch window. */
46179 DEBUG_FUNCTION void
46181 {
46183 }
46185 /* Print INSN dispatch information to FILE. */
46187 DEBUG_FUNCTION static void
46189 {
46212 }
46214 /* Print to STDERR the status of the ready list with respect to
46215 dispatch windows. */
46217 DEBUG_FUNCTION void
46219 {
46227 }
46229 /* This routine is the driver of the dispatch scheduler. */
46231 static void
46233 {
46238 }
46240 /* Return TRUE if Dispatch Scheduling is supported. */
46242 static bool
46244 {
46248 {
46264 }
46267 }
46269 /* Implementation of reassociation_width target hook used by
46270 reassoc phase to identify parallelism level in reassociated
46271 tree. Statements tree_code is passed in OPC. Arguments type
46272 is passed in MODE.
46274 Currently parallel reassociation is enabled for Atom
46275 processors only and we set reassociation width to be 2
46276 because Atom may issue up to 2 instructions per cycle.
46278 Return value should be fixed if parallel reassociation is
46279 enabled for other processors. */
46281 static int
46284 {
46293 }
46295 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46296 place emms and femms instructions. */
46298 static enum machine_mode
46300 {
46305 {
46322 else
46334 /* FALLTHRU */
46338 }
46339 }
46341 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46342 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46343 256bit and 128bit vectors. */
46345 static unsigned int
46347 {
46350 }
46352 \f
46354 /* Return class of registers which could be used for pseudo of MODE
46355 and of class RCLASS for spilling instead of memory. Return NO_REGS
46356 if it is not possible or non-profitable. */
46357 static reg_class_t
46359 {
46365 }
46367 /* Implement targetm.vectorize.init_cost. */
46371 {
46375 }
46377 /* Implement targetm.vectorize.add_stmt_cost. */
46379 static unsigned
46383 {
46390 /* Statements in an inner loop relative to the loop being
46391 vectorized are weighted more heavily. The value here is
46392 arbitrary and could potentially be improved with analysis. */
46400 }
46402 /* Implement targetm.vectorize.finish_cost. */
46404 static void
46407 {
46412 }
46414 /* Implement targetm.vectorize.destroy_cost_data. */
46416 static void
46418 {
46420 }
46422 /* Validate target specific memory model bits in VAL. */
46424 static unsigned HOST_WIDE_INT
46426 {
46433 {
46437 }
46440 {
46444 }
46446 {
46450 }
46452 }
46454 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46455 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46456 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46457 or number of vecsize_mangle variants that should be emitted. */
46459 static int
46463 {
46470 {
46474 }
46479 {
46486 /* case SCmode: */
46487 /* case DCmode: */
46493 }
46495 tree t;
46499 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46501 {
46508 /* case SCmode: */
46509 /* case DCmode: */
46515 }
46518 {
46519 /* Parse here processor clause. If not present, default to 'b'. */
46521 }
46523 {
46524 /* If the function isn't exported, we can pick up just one ISA
46525 for the clones. */
46530 else
46533 }
46534 else
46535 {
46538 }
46540 {
46553 }
46555 {
46558 else
46563 }
46565 }
46567 /* Add target attribute to SIMD clone NODE if needed. */
46569 static void
46571 {
46575 {
46590 }
46600 }
46602 /* If SIMD clone NODE can't be used in a vectorized loop
46603 in current function, return -1, otherwise return a badness of using it
46604 (0 if it is most desirable from vecsize_mangle point of view, 1
46605 slightly less desirable, etc.). */
46607 static int
46609 {
46611 {
46629 }
46630 }
46632 /* This function gives out the number of memory references.
46633 This value determines the unrolling factor for
46634 bdver3 and bdver4 architectures. */
46636 static int
46638 {
46640 {
46649 else
46651 }
46653 }
46655 /* This function adjusts the unroll factor based on
46656 the hardware capabilities. For ex, bdver3 has
46657 a loop buffer which makes unrolling of smaller
46658 loops less important. This function decides the
46659 unroll factor using number of memory references
46660 (value 32 is used) as a heuristic. */
46662 static unsigned
46664 {
46666 rtx insn;
46673 /* Count the number of memory references within the loop body. */
46676 {
46680 }
46687 }
46690 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46692 static bool
46694 {
46695 /* For x87 floating point with standard excess precision handling,
46696 there is no adddf3 pattern (since x87 floating point only has
46697 XFmode operations) so the default hook implementation gets this
46698 wrong. */
46700 }
46702 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46704 static void
46706 {
46711 {
46726 hold_fnclex);
46740 }
46742 {
46751 mxcsr_orig_var,
46761 ldmxcsr_hold_call);
46764 else
46769 ldmxcsr_clear_call);
46770 else
46774 stxmcsr_update_call);
46776 {
46782 exceptions_assign);
46783 }
46784 else
46789 ldmxcsr_update_call);
46790 }
46791 tree atomic_feraiseexcept
46796 atomic_feraiseexcept_call);
46797 }
46799 /* Initialize the GCC target structure. */
46800 #undef TARGET_RETURN_IN_MEMORY
46801 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46803 #undef TARGET_LEGITIMIZE_ADDRESS
46804 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46806 #undef TARGET_ATTRIBUTE_TABLE
46807 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46808 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46809 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46810 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46811 # undef TARGET_MERGE_DECL_ATTRIBUTES
46812 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46813 #endif
46815 #undef TARGET_COMP_TYPE_ATTRIBUTES
46816 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46818 #undef TARGET_INIT_BUILTINS
46819 #define TARGET_INIT_BUILTINS ix86_init_builtins
46820 #undef TARGET_BUILTIN_DECL
46821 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46822 #undef TARGET_EXPAND_BUILTIN
46823 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46825 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46826 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46827 ix86_builtin_vectorized_function
46829 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46830 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46832 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46833 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46835 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46836 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46838 #undef TARGET_BUILTIN_RECIPROCAL
46839 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46841 #undef TARGET_ASM_FUNCTION_EPILOGUE
46842 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
46844 #undef TARGET_ENCODE_SECTION_INFO
46845 #ifndef SUBTARGET_ENCODE_SECTION_INFO
46846 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
46847 #else
46848 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
46849 #endif
46851 #undef TARGET_ASM_OPEN_PAREN
46853 #undef TARGET_ASM_CLOSE_PAREN
46856 #undef TARGET_ASM_BYTE_OP
46857 #define TARGET_ASM_BYTE_OP ASM_BYTE
46859 #undef TARGET_ASM_ALIGNED_HI_OP
46860 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
46861 #undef TARGET_ASM_ALIGNED_SI_OP
46862 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
46863 #ifdef ASM_QUAD
46864 #undef TARGET_ASM_ALIGNED_DI_OP
46865 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
46866 #endif
46868 #undef TARGET_PROFILE_BEFORE_PROLOGUE
46869 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
46871 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
46872 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
46874 #undef TARGET_ASM_UNALIGNED_HI_OP
46875 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
46876 #undef TARGET_ASM_UNALIGNED_SI_OP
46877 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
46878 #undef TARGET_ASM_UNALIGNED_DI_OP
46879 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
46881 #undef TARGET_PRINT_OPERAND
46882 #define TARGET_PRINT_OPERAND ix86_print_operand
46883 #undef TARGET_PRINT_OPERAND_ADDRESS
46884 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
46885 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
46886 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
46887 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
46888 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
46890 #undef TARGET_SCHED_INIT_GLOBAL
46891 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
46892 #undef TARGET_SCHED_ADJUST_COST
46893 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
46894 #undef TARGET_SCHED_ISSUE_RATE
46895 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
46896 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
46897 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
46898 ia32_multipass_dfa_lookahead
46899 #undef TARGET_SCHED_MACRO_FUSION_P
46900 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
46901 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
46902 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
46904 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
46905 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
46907 #undef TARGET_MEMMODEL_CHECK
46908 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
46910 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
46911 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
46913 #ifdef HAVE_AS_TLS
46914 #undef TARGET_HAVE_TLS
46915 #define TARGET_HAVE_TLS true
46916 #endif
46917 #undef TARGET_CANNOT_FORCE_CONST_MEM
46918 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
46919 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
46920 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
46922 #undef TARGET_DELEGITIMIZE_ADDRESS
46923 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
46925 #undef TARGET_MS_BITFIELD_LAYOUT_P
46926 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
46928 #if TARGET_MACHO
46929 #undef TARGET_BINDS_LOCAL_P
46930 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
46931 #endif
46932 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46933 #undef TARGET_BINDS_LOCAL_P
46934 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
46935 #endif
46937 #undef TARGET_ASM_OUTPUT_MI_THUNK
46938 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
46939 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
46940 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
46942 #undef TARGET_ASM_FILE_START
46943 #define TARGET_ASM_FILE_START x86_file_start
46945 #undef TARGET_OPTION_OVERRIDE
46946 #define TARGET_OPTION_OVERRIDE ix86_option_override
46948 #undef TARGET_REGISTER_MOVE_COST
46949 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
46950 #undef TARGET_MEMORY_MOVE_COST
46951 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
46952 #undef TARGET_RTX_COSTS
46953 #define TARGET_RTX_COSTS ix86_rtx_costs
46954 #undef TARGET_ADDRESS_COST
46955 #define TARGET_ADDRESS_COST ix86_address_cost
46957 #undef TARGET_FIXED_CONDITION_CODE_REGS
46958 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
46959 #undef TARGET_CC_MODES_COMPATIBLE
46960 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
46962 #undef TARGET_MACHINE_DEPENDENT_REORG
46963 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
46965 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
46966 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
46968 #undef TARGET_BUILD_BUILTIN_VA_LIST
46969 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
46971 #undef TARGET_FOLD_BUILTIN
46972 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
46974 #undef TARGET_COMPARE_VERSION_PRIORITY
46975 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
46977 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
46978 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
46979 ix86_generate_version_dispatcher_body
46981 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
46982 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
46983 ix86_get_function_versions_dispatcher
46985 #undef TARGET_ENUM_VA_LIST_P
46986 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
46988 #undef TARGET_FN_ABI_VA_LIST
46989 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
46991 #undef TARGET_CANONICAL_VA_LIST_TYPE
46992 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
46994 #undef TARGET_EXPAND_BUILTIN_VA_START
46995 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
46997 #undef TARGET_MD_ASM_CLOBBERS
46998 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47000 #undef TARGET_PROMOTE_PROTOTYPES
47001 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47002 #undef TARGET_SETUP_INCOMING_VARARGS
47003 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47004 #undef TARGET_MUST_PASS_IN_STACK
47005 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47006 #undef TARGET_FUNCTION_ARG_ADVANCE
47007 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47008 #undef TARGET_FUNCTION_ARG
47009 #define TARGET_FUNCTION_ARG ix86_function_arg
47010 #undef TARGET_FUNCTION_ARG_BOUNDARY
47011 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47012 #undef TARGET_PASS_BY_REFERENCE
47013 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47014 #undef TARGET_INTERNAL_ARG_POINTER
47015 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47016 #undef TARGET_UPDATE_STACK_BOUNDARY
47017 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47018 #undef TARGET_GET_DRAP_RTX
47019 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47020 #undef TARGET_STRICT_ARGUMENT_NAMING
47021 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47022 #undef TARGET_STATIC_CHAIN
47023 #define TARGET_STATIC_CHAIN ix86_static_chain
47024 #undef TARGET_TRAMPOLINE_INIT
47025 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47026 #undef TARGET_RETURN_POPS_ARGS
47027 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47029 #undef TARGET_LEGITIMATE_COMBINED_INSN
47030 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47032 #undef TARGET_ASAN_SHADOW_OFFSET
47033 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47035 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47036 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47038 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47039 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47041 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47042 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47044 #undef TARGET_C_MODE_FOR_SUFFIX
47045 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47047 #ifdef HAVE_AS_TLS
47048 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47049 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47050 #endif
47052 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47053 #undef TARGET_INSERT_ATTRIBUTES
47054 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47055 #endif
47057 #undef TARGET_MANGLE_TYPE
47058 #define TARGET_MANGLE_TYPE ix86_mangle_type
47060 #if !TARGET_MACHO
47061 #undef TARGET_STACK_PROTECT_FAIL
47062 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47063 #endif
47065 #undef TARGET_FUNCTION_VALUE
47066 #define TARGET_FUNCTION_VALUE ix86_function_value
47068 #undef TARGET_FUNCTION_VALUE_REGNO_P
47069 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47071 #undef TARGET_PROMOTE_FUNCTION_MODE
47072 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47074 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47075 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47077 #undef TARGET_INSTANTIATE_DECLS
47078 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47080 #undef TARGET_SECONDARY_RELOAD
47081 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47083 #undef TARGET_CLASS_MAX_NREGS
47084 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47086 #undef TARGET_PREFERRED_RELOAD_CLASS
47087 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47088 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47089 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47090 #undef TARGET_CLASS_LIKELY_SPILLED_P
47091 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47093 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47094 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47095 ix86_builtin_vectorization_cost
47096 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47097 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47098 ix86_vectorize_vec_perm_const_ok
47099 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47100 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47101 ix86_preferred_simd_mode
47102 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47103 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47104 ix86_autovectorize_vector_sizes
47105 #undef TARGET_VECTORIZE_INIT_COST
47106 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47107 #undef TARGET_VECTORIZE_ADD_STMT_COST
47108 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47109 #undef TARGET_VECTORIZE_FINISH_COST
47110 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47111 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47112 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47114 #undef TARGET_SET_CURRENT_FUNCTION
47115 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47117 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47118 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47120 #undef TARGET_OPTION_SAVE
47121 #define TARGET_OPTION_SAVE ix86_function_specific_save
47123 #undef TARGET_OPTION_RESTORE
47124 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47126 #undef TARGET_OPTION_PRINT
47127 #define TARGET_OPTION_PRINT ix86_function_specific_print
47129 #undef TARGET_OPTION_FUNCTION_VERSIONS
47130 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47132 #undef TARGET_CAN_INLINE_P
47133 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47135 #undef TARGET_EXPAND_TO_RTL_HOOK
47136 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47138 #undef TARGET_LEGITIMATE_ADDRESS_P
47139 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47141 #undef TARGET_LRA_P
47142 #define TARGET_LRA_P hook_bool_void_true
47144 #undef TARGET_REGISTER_PRIORITY
47145 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47147 #undef TARGET_REGISTER_USAGE_LEVELING_P
47148 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47150 #undef TARGET_LEGITIMATE_CONSTANT_P
47151 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47153 #undef TARGET_FRAME_POINTER_REQUIRED
47154 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47156 #undef TARGET_CAN_ELIMINATE
47157 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47159 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47160 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47162 #undef TARGET_ASM_CODE_END
47163 #define TARGET_ASM_CODE_END ix86_code_end
47165 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47166 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47168 #if TARGET_MACHO
47169 #undef TARGET_INIT_LIBFUNCS
47170 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47171 #endif
47173 #undef TARGET_LOOP_UNROLL_ADJUST
47174 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47176 #undef TARGET_SPILL_CLASS
47177 #define TARGET_SPILL_CLASS ix86_spill_class
47179 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47180 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47181 ix86_simd_clone_compute_vecsize_and_simdlen
47183 #undef TARGET_SIMD_CLONE_ADJUST
47184 #define TARGET_SIMD_CLONE_ADJUST \
47185 ix86_simd_clone_adjust
47187 #undef TARGET_SIMD_CLONE_USABLE
47188 #define TARGET_SIMD_CLONE_USABLE \
47189 ix86_simd_clone_usable
47191 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47192 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47193 ix86_float_exceptions_rounding_supported_p
47196 \f