| blob | bbe3bd79ca105750af63d05058b61484ee653ccf |
1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2022 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
38 /* Include insn-config.h before expr.h so that HAVE_conditional_move
39 is properly defined. */
51 machine_mode *);
57 /* Debug facility for use in GDB. */
59 \f
60 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
61 the result of operation CODE applied to OP0 (and OP1 if it is a binary
62 operation). OP0_MODE is OP0's mode.
64 If the last insn does not set TARGET, don't do anything, but return 1.
66 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
67 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
68 try again, ensuring that TARGET is not one of the operands. */
70 static int
73 {
75 rtx set;
76 rtx note;
93 ;
95 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
96 a value changing in the insn, so the note would be invalid for CSE. */
99 {
103 {
104 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
105 over expanding it as temp = MEM op X, MEM = temp. If the target
106 supports MEM = MEM op X instructions, it is sometimes too hard
107 to reconstruct that form later, especially if X is also a memory,
108 and due to multiple occurrences of addresses the address might
109 be forced into register unnecessarily.
110 Note that not emitting the REG_EQUIV note might inhibit
111 CSE in some cases. */
120 }
122 }
129 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
136 {
145 {
151 else
155 }
156 /* FALLTHRU */
160 }
161 else
167 }
168 \f
169 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
170 for a widening operation would be. In most cases this would be OP0, but if
171 that's a constant it'll be VOIDmode, which isn't useful. */
173 static machine_mode
175 {
178 machine_mode result;
184 else
191 }
192 \f
193 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
194 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
195 not actually do a sign-extend or zero-extend, but can leave the
196 higher-order bits of the result rtx undefined, for example, in the case
197 of logical operations, but not right shifts. */
199 static rtx
202 {
203 rtx result;
204 scalar_int_mode int_mode;
206 /* If we don't have to extend and this is a constant, return it. */
210 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
211 extend since it will be more efficient to do so unless the signedness of
212 a promoted object differs from our extension. */
219 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
220 SUBREG. */
224 /* Otherwise, get an object of MODE, clobber it, and set the low-order
225 part to OP. */
231 }
232 \f
233 /* Expand vector widening operations.
235 There are two different classes of operations handled here:
236 1) Operations whose result is wider than all the arguments to the operation.
237 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
238 In this case OP0 and optionally OP1 would be initialized,
239 but WIDE_OP wouldn't (not relevant for this case).
240 2) Operations whose result is of the same size as the last argument to the
241 operation, but wider than all the other arguments to the operation.
242 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
243 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
245 E.g, when called to expand the following operations, this is how
246 the arguments will be initialized:
247 nops OP0 OP1 WIDE_OP
248 widening-sum 2 oprnd0 - oprnd1
249 widening-dot-product 3 oprnd0 oprnd1 oprnd2
250 widening-mult 2 oprnd0 oprnd1 -
251 type-promotion (vec-unpack) 1 oprnd0 - - */
253 rtx
256 {
260 optab widen_pattern_optab;
273 /* The sign is from the result type rather than operand's type
274 for these ops. */
275 widen_pattern_optab
283 {
284 /* For VEC_UNPACK_{LO,HI}_EXPR if the mode of op0 and result is
285 the same scalar mode for VECTOR_BOOLEAN_TYPE_P vectors, use
286 vec_unpacks_sbool_{lo,hi}_optab, so that we can pass in
287 the pattern number of elements in the wider vector. */
288 widen_pattern_optab
292 }
294 {
299 ;
301 {
303 /* Same as optab_vector_mixed_sign but flip the operands. */
305 }
308 else
311 widen_pattern_optab
313 }
314 else
315 widen_pattern_optab
321 tmode0);
322 else
329 {
333 }
335 /* The last operand is of a wider mode than the rest of the operands. */
339 {
343 }
354 }
356 /* Generate code to perform an operation specified by TERNARY_OPTAB
357 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
359 UNSIGNEDP is for the case where we have to widen the operands
360 to perform the operation. It says to use zero-extension.
362 If TARGET is nonzero, the value
363 is generated there, if it is convenient to do so.
364 In all cases an rtx is returned for the locus of the value;
365 this may or may not be TARGET. */
367 rtx
370 {
382 }
385 /* Like expand_binop, but return a constant rtx if the result can be
386 calculated at compile time. The arguments and return value are
387 otherwise the same as for expand_binop. */
389 rtx
393 {
395 {
400 }
403 }
405 /* Like simplify_expand_binop, but always put the result in TARGET.
406 Return true if the expansion succeeded. */
408 bool
412 {
420 }
422 /* Create a new vector value in VMODE with all elements set to OP. The
423 mode of OP must be the element mode of VMODE. If OP is a constant,
424 then the return value will be a constant. */
426 rtx
428 {
430 rtvec vec;
439 {
445 }
450 /* ??? If the target doesn't have a vec_init, then we have no easy way
451 of performing this operation. Most of this sort of generic support
452 is hidden away in the vector lowering support in gimple. */
465 }
467 /* This subroutine of expand_doubleword_shift handles the cases in which
468 the effective shift value is >= BITS_PER_WORD. The arguments and return
469 value are the same as for the parent routine, except that SUPERWORD_OP1
470 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
471 INTO_TARGET may be null if the caller has decided to calculate it. */
473 static bool
477 {
484 {
485 /* For a signed right shift, we must fill OUTOF_TARGET with copies
486 of the sign bit, otherwise we must fill it with zeros. */
489 else
495 }
497 }
499 /* This subroutine of expand_doubleword_shift handles the cases in which
500 the effective shift value is < BITS_PER_WORD. The arguments and return
501 value are the same as for the parent routine. */
503 static bool
509 {
516 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
517 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
518 the opposite direction to BINOPTAB. */
520 {
526 }
527 else
528 {
529 /* We must avoid shifting by BITS_PER_WORD bits since that is either
530 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
531 has unknown behavior. Do a single shift first, then shift by the
532 remainder. It's OK to use ~OP1 as the remainder if shift counts
533 are truncated to the mode size. */
537 {
538 tmp = immed_wide_int_const
542 }
543 else
544 {
549 }
550 }
558 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
559 so the result can go directly into INTO_TARGET if convenient. */
565 /* Now OR in the bits carried over from OUTOF_INPUT. */
570 /* Use a standard word_mode shift for the out-of half. */
577 }
580 /* Try implementing expand_doubleword_shift using conditional moves.
581 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
582 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
583 are the shift counts to use in the former and latter case. All other
584 arguments are the same as the parent routine. */
586 static bool
594 {
597 /* Put the superword version of the output into OUTOF_SUPERWORD and
598 INTO_SUPERWORD. */
601 {
602 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
603 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
608 }
609 else
610 {
616 }
618 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
625 /* Select between them. Do the INTO half first because INTO_SUPERWORD
626 might be the current value of OUTOF_TARGET. */
639 }
641 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
642 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
643 input operand; the shift moves bits in the direction OUTOF_INPUT->
644 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
645 of the target. OP1 is the shift count and OP1_MODE is its mode.
646 If OP1 is constant, it will have been truncated as appropriate
647 and is known to be nonzero.
649 If SHIFT_MASK is zero, the result of word shifts is undefined when the
650 shift count is outside the range [0, BITS_PER_WORD). This routine must
651 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
653 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
654 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
655 fill with zeros or sign bits as appropriate.
657 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
658 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
659 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
660 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
661 are undefined.
663 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
664 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
665 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
666 function wants to calculate it itself.
668 Return true if the shift could be successfully synthesized. */
670 static bool
676 {
680 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
681 fill the result with sign or zero bits as appropriate. If so, the value
682 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
683 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
684 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
686 This isn't worthwhile for constant shifts since the optimizers will
687 cope better with in-range shift counts. */
691 {
701 }
703 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
704 is true when the effective shift value is less than BITS_PER_WORD.
705 Set SUPERWORD_OP1 to the shift count that should be used to shift
706 OUTOF_INPUT into INTO_TARGET when the condition is false. */
709 {
710 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
711 is a subword shift count. */
717 }
718 else
719 {
720 /* Set CMP1 to OP1 - BITS_PER_WORD. */
726 }
730 /* If we can compute the condition at compile time, pick the
731 appropriate subroutine. */
734 {
739 else
744 }
746 /* Try using conditional moves to generate straight-line code. */
748 {
758 }
760 /* As a last resort, use branches to select the correct alternative. */
764 NO_DEFER_POP;
768 OK_DEFER_POP;
787 }
788 \f
789 /* Subroutine of expand_binop. Perform a double word multiplication of
790 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
791 as the target's word_mode. This function return NULL_RTX if anything
792 goes wrong, in which case it may have already emitted instructions
793 which need to be deleted.
795 If we want to multiply two two-word values and have normal and widening
796 multiplies of single-word values, we can do this with three smaller
797 multiplications.
799 The multiplication proceeds as follows:
800 _______________________
801 [__op0_high_|__op0_low__]
802 _______________________
803 * [__op1_high_|__op1_low__]
804 _______________________________________________
805 _______________________
806 (1) [__op0_low__*__op1_low__]
807 _______________________
808 (2a) [__op0_low__*__op1_high_]
809 _______________________
810 (2b) [__op0_high_*__op1_low__]
811 _______________________
812 (3) [__op0_high_*__op1_high_]
815 This gives a 4-word result. Since we are only interested in the
816 lower 2 words, partial result (3) and the upper words of (2a) and
817 (2b) don't need to be calculated. Hence (2a) and (2b) can be
818 calculated using non-widening multiplication.
820 (1), however, needs to be calculated with an unsigned widening
821 multiplication. If this operation is not directly supported we
822 try using a signed widening multiplication and adjust the result.
823 This adjustment works as follows:
825 If both operands are positive then no adjustment is needed.
827 If the operands have different signs, for example op0_low < 0 and
828 op1_low >= 0, the instruction treats the most significant bit of
829 op0_low as a sign bit instead of a bit with significance
830 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
831 with 2**BITS_PER_WORD - op0_low, and two's complements the
832 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
833 the result.
835 Similarly, if both operands are negative, we need to add
836 (op0_low + op1_low) * 2**BITS_PER_WORD.
838 We use a trick to adjust quickly. We logically shift op0_low right
839 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
840 op0_high (op1_high) before it is used to calculate 2b (2a). If no
841 logical shift exists, we do an arithmetic right shift and subtract
842 the 0 or -1. */
844 static rtx
847 {
859 /* If we're using an unsigned multiply to directly compute the product
860 of the low-order words of the operands and perform any required
861 adjustments of the operands, we begin by trying two more multiplications
862 and then computing the appropriate sum.
864 We have checked above that the required addition is provided.
865 Full-word addition will normally always succeed, especially if
866 it is provided at all, so we don't worry about its failure. The
867 multiplication may well fail, however, so we do handle that. */
870 {
871 /* ??? This could be done with emit_store_flag where available. */
877 else
878 {
885 }
889 }
896 /* OP0_HIGH should now be dead. */
899 {
900 /* ??? This could be done with emit_store_flag where available. */
906 else
907 {
914 }
918 }
925 /* OP1_HIGH should now be dead. */
933 /* *_widen_optab needs to determine operand mode, make sure at least
934 one operand has non-VOID mode. */
941 else
953 }
955 /* Subroutine of expand_binop. Optimize unsigned double-word OP0 % OP1 for
956 constant OP1. If for some bit in [BITS_PER_WORD / 2, BITS_PER_WORD] range
957 (prefer higher bits) ((1w << bit) % OP1) == 1, then the modulo can be
958 computed in word-mode as ((OP0 & (bit - 1)) + ((OP0 >> bit) & (bit - 1))
959 + (OP0 >> (2 * bit))) % OP1. Whether we need to sum 2, 3 or 4 values
960 depends on the bit value, if 2, then carry from the addition needs to be
961 added too, i.e. like:
962 sum += __builtin_add_overflow (low, high, &sum)
964 Optimize signed double-word OP0 % OP1 similarly, just apply some correction
965 factor to the sum before doing unsigned remainder, in the form of
966 sum += (((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & const);
967 then perform unsigned
968 remainder = sum % OP1;
969 and finally
970 remainder += ((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1); */
972 static rtx
974 {
980 {
986 {
987 /* For signed modulo we need to add correction to the sum
988 and that might again overflow. */
1011 OPTAB_DIRECT);
1014 }
1015 else
1016 {
1017 /* Code below uses GEN_INT, so we need the masks to be representable
1018 in HOST_WIDE_INTs. */
1021 /* If op0 is e.g. -1 or -2 unsigned, then the 2 additions might
1022 overflow. Consider 64-bit -1ULL for word size 32, if we add
1023 0x7fffffffU + 0x7fffffffU + 3U, it wraps around to 1. */
1031 {
1032 /* For signed modulo, compute it as unsigned modulo of
1033 sum with a correction added to it if OP0 is negative,
1034 such that the result can be computed as unsigned
1035 remainder + ((OP1 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1). */
1039 /* wmod2 == -wmod1. */
1042 {
1046 /* Now verify if the count sums can't overflow, and punt
1047 if they could. */
1058 mode);
1067 OPTAB_DIRECT);
1070 }
1071 }
1074 {
1088 OPTAB_DIRECT);
1093 else
1098 }
1100 {
1105 }
1106 }
1109 word_mode),
1115 {
1117 {
1119 mode);
1125 }
1128 word_mode),
1136 }
1139 /* Punt if we need any library calls. */
1142 else
1148 }
1150 }
1152 /* Similarly to the above function, but compute both quotient and remainder.
1153 Quotient can be computed from the remainder as:
1154 rem = op0 % op1; // Handled using expand_doubleword_mod
1155 quot = (op0 - rem) * inv; // inv is multiplicative inverse of op1 modulo
1156 // 2 * BITS_PER_WORD
1158 We can also handle cases where op1 is a multiple of power of two constant
1159 and constant handled by expand_doubleword_mod.
1160 op11 = 1 << __builtin_ctz (op1);
1161 op12 = op1 / op11;
1162 rem1 = op0 % op12; // Handled using expand_doubleword_mod
1163 quot1 = (op0 - rem1) * inv; // inv is multiplicative inverse of op12 modulo
1164 // 2 * BITS_PER_WORD
1165 rem = (quot1 % op11) * op12 + rem1;
1166 quot = quot1 / op11; */
1168 rtx
1171 {
1174 /* Negative dividend should have been optimized into positive,
1175 similarly modulo by 1 and modulo by power of two is optimized
1176 differently too. */
1183 {
1187 }
1211 {
1234 }
1236 /* Punt if we need any library calls. */
1239 else
1247 }
1248 \f
1249 /* Wrapper around expand_binop which takes an rtx code to specify
1250 the operation to perform, not an optab pointer. All other
1251 arguments are the same. */
1252 rtx
1256 {
1261 }
1263 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1264 binop. Order them according to commutative_operand_precedence and, if
1265 possible, try to put TARGET or a pseudo first. */
1266 static bool
1268 {
1278 /* With equal precedence, both orders are ok, but it is better if the
1279 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1282 else
1284 }
1286 /* Return true if BINOPTAB implements a shift operation. */
1288 static bool
1290 {
1292 {
1304 }
1305 }
1307 /* Return true if BINOPTAB implements a commutative binary operation. */
1309 static bool
1311 {
1317 }
1319 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1320 optimizing, and if the operand is a constant that costs more than
1321 1 instruction, force the constant into a register and return that
1322 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1324 static rtx
1327 {
1331 && optimize
1335 {
1337 {
1341 }
1342 else
1345 }
1347 }
1349 /* Helper function for expand_binop: handle the case where there
1350 is an insn ICODE that directly implements the indicated operation.
1351 Returns null if this is not possible. */
1352 static rtx
1357 {
1367 /* If it is a commutative operator and the modes would match
1368 if we would swap the operands, we can save the conversions. */
1375 /* If we are optimizing, force expensive constants into a register. */
1379 else
1380 /* Shifts and rotates often use a different mode for op1 from op0;
1381 for VOIDmode constants we don't know the mode, so force it
1382 to be canonicalized using convert_modes. */
1385 /* In case the insn wants input operands in modes different from
1386 those of the actual operands, convert the operands. It would
1387 seem that we don't need to convert CONST_INTs, but we do, so
1388 that they're properly zero-extended, sign-extended or truncated
1389 for their mode. */
1393 {
1396 }
1401 {
1404 }
1406 /* If operation is commutative,
1407 try to make the first operand a register.
1408 Even better, try to make it the same as the target.
1409 Also try to make the last operand a constant. */
1414 /* Now, if insn's predicates don't allow our operands, put them into
1415 pseudo regs. */
1424 {
1425 /* The mode of the result is different then the mode of the
1426 arguments. */
1430 {
1433 }
1434 }
1435 else
1443 {
1444 /* If PAT is composed of more than one insn, try to add an appropriate
1445 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1446 operand, call expand_binop again, this time without a target. */
1451 {
1455 }
1459 }
1462 }
1464 /* Generate code to perform an operation specified by BINOPTAB
1465 on operands OP0 and OP1, with result having machine-mode MODE.
1467 UNSIGNEDP is for the case where we have to widen the operands
1468 to perform the operation. It says to use zero-extension.
1470 If TARGET is nonzero, the value
1471 is generated there, if it is convenient to do so.
1472 In all cases an rtx is returned for the locus of the value;
1473 this may or may not be TARGET. */
1475 rtx
1478 {
1479 enum optab_methods next_methods
1484 machine_mode wider_mode;
1485 scalar_int_mode int_mode;
1486 rtx libfunc;
1487 rtx temp;
1493 /* If subtracting an integer constant, convert this into an addition of
1494 the negated constant. */
1497 {
1500 }
1501 /* For shifts, constant invalid op1 might be expanded from different
1502 mode than MODE. As those are invalid, force them to a register
1503 to avoid further problems during expansion. */
1507 {
1510 }
1512 /* Record where to delete back to if we backtrack. */
1515 /* If we can do it with a three-operand insn, do so. */
1518 {
1520 {
1523 }
1524 else
1527 {
1532 }
1533 }
1535 /* If we were trying to rotate, and that didn't work, try rotating
1536 the other direction before falling back to shifts and bitwise-or. */
1542 {
1544 rtx newop1;
1551 else
1560 }
1562 /* If this is a multiply, see if we can do a widening operation that
1563 takes operands of this mode and makes a wider mode. */
1568 ? umul_widen_optab
1571 {
1572 /* *_widen_optab needs to determine operand mode, make sure at least
1573 one operand has non-VOID mode. */
1581 {
1585 else
1587 }
1588 }
1590 /* If this is a vector shift by a scalar, see if we can do a vector
1591 shift by a vector. If so, broadcast the scalar into a vector. */
1593 {
1609 {
1610 /* The scalar may have been extended to be too wide. Truncate
1611 it back to the proper size to fit in the broadcast vector. */
1621 {
1626 }
1627 }
1628 }
1630 /* Look for a wider mode of the same class for which we think we
1631 can open-code the operation. Check for a widening multiply at the
1632 wider mode as well. */
1637 {
1638 machine_mode next_mode;
1643 ? umul_widen_optab
1647 {
1651 /* For certain integer operations, we need not actually extend
1652 the narrow operands, as long as we will truncate
1653 the results to the same narrowness. */
1660 {
1667 }
1671 /* The second operand of a shift must always be extended. */
1678 {
1681 {
1686 }
1687 else
1689 }
1690 else
1692 }
1693 }
1695 /* If operation is commutative,
1696 try to make the first operand a register.
1697 Even better, try to make it the same as the target.
1698 Also try to make the last operand a constant. */
1703 /* These can be done a word at a time. */
1708 {
1712 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1713 won't be accurate, so use a new target. */
1724 /* Do the actual arithmetic. */
1732 {
1744 }
1750 {
1753 }
1754 }
1756 /* Synthesize double word shifts from single word shifts. */
1766 {
1768 scalar_int_mode op1_mode;
1776 /* Apply the truncation to constant shifts. */
1783 /* Make sure that this is a combination that expand_doubleword_shift
1784 can handle. See the comments there for details. */
1788 {
1794 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1795 won't be accurate, so use a new target. */
1806 /* OUTOF_* is the word we are shifting bits away from, and
1807 INTO_* is the word that we are shifting bits towards, thus
1808 they differ depending on the direction of the shift and
1809 WORDS_BIG_ENDIAN. */
1824 {
1830 }
1832 }
1833 }
1835 /* Synthesize double word rotates from single word shifts. */
1842 {
1846 rtx inter;
1849 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1850 won't be accurate, so use a new target. Do this also if target is not
1851 a REG, first because having a register instead may open optimization
1852 opportunities, and second because if target and op0 happen to be MEMs
1853 designating the same location, we would risk clobbering it too early
1854 in the code sequence we generate below. */
1868 /* OUTOF_* is the word we are shifting bits away from, and
1869 INTO_* is the word that we are shifting bits towards, thus
1870 they differ depending on the direction of the shift and
1871 WORDS_BIG_ENDIAN. */
1883 {
1884 /* This is just a word swap. */
1888 }
1889 else
1890 {
1902 {
1905 }
1906 else
1907 {
1910 }
1911 rtx first_shift_count_rtx
1913 rtx second_shift_count_rtx
1926 else
1946 }
1952 {
1955 }
1956 }
1958 /* These can be done a word at a time by propagating carries. */
1963 {
1970 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1971 value is one of those, use it. Otherwise, use 1 since it is the
1972 one easiest to get. */
1973 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1975 #else
1977 #endif
1979 /* Prepare the operands. */
1988 /* Indicate for flow that the entire target reg is being set. */
1992 /* Do the actual arithmetic. */
1994 {
1999 rtx x;
2001 /* Main add/subtract of the input operands. */
2009 {
2010 /* Store carry from main add/subtract. */
2017 }
2020 {
2021 rtx newx;
2023 /* Add/subtract previous carry to main result. */
2030 {
2031 /* Get out carry from adding/subtracting carry in. */
2039 /* Logical-ior the two poss. carry together. */
2045 }
2047 }
2048 else
2049 {
2052 }
2055 }
2058 {
2061 {
2068 target);
2069 }
2070 else
2074 }
2076 else
2078 }
2080 /* Attempt to synthesize double word multiplies using a sequence of word
2081 mode multiplications. We first attempt to generate a sequence using a
2082 more efficient unsigned widening multiply, and if that fails we then
2083 try using a signed widening multiply. */
2090 {
2094 {
2099 }
2104 {
2109 }
2112 {
2114 {
2116 product);
2118 REG_EQUAL,
2123 }
2125 }
2126 }
2128 /* Attempt to synthetize double word modulo by constant divisor. */
2133 && optimize
2139 int_mode) == CODE_FOR_nothing
2143 {
2149 else
2150 {
2152 binoptab == umod_optab
2158 }
2160 {
2162 {
2164 res);
2169 }
2171 }
2172 else
2174 }
2176 /* It can't be open-coded in this mode.
2177 Use a library call if one is available and caller says that's ok. */
2182 {
2186 rtx value;
2191 {
2193 /* Specify unsigned here,
2194 since negative shift counts are meaningless. */
2196 }
2202 /* Pass 1 for NO_QUEUE so we don't lose any increments
2203 if the libcall is cse'd or moved. */
2214 trapv ? NULL_RTX
2219 }
2223 /* It can't be done in this mode. Can we do it in a wider mode? */
2227 {
2228 /* Caller says, don't even try. */
2231 }
2233 /* Compute the value of METHODS to pass to recursive calls.
2234 Don't allow widening to be tried recursively. */
2238 /* Look for a wider mode of the same class for which it appears we can do
2239 the operation. */
2242 {
2243 /* This code doesn't make sense for conversion optabs, since we
2244 wouldn't then want to extend the operands to be the same size
2245 as the result. */
2248 {
2252 {
2256 /* For certain integer operations, we need not actually extend
2257 the narrow operands, as long as we will truncate
2258 the results to the same narrowness. */
2270 /* The second operand of a shift must always be extended. */
2277 {
2280 {
2285 }
2286 else
2288 }
2289 else
2291 }
2292 }
2293 }
2297 }
2298 \f
2299 /* Expand a binary operator which has both signed and unsigned forms.
2300 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2301 signed operations.
2303 If we widen unsigned operands, we may use a signed wider operation instead
2304 of an unsigned wider operation, since the result would be the same. */
2306 rtx
2310 {
2311 rtx temp;
2315 /* Do it without widening, if possible. */
2321 /* Try widening to a signed int. Disable any direct use of any
2322 signed insn in the current mode. */
2328 /* For unsigned operands, try widening to an unsigned int. */
2335 /* Use the right width libcall if that exists. */
2341 /* Must widen and use a libcall, use either signed or unsigned. */
2348 egress:
2349 /* Undo the fiddling above. */
2353 }
2354 \f
2355 /* Generate code to perform an operation specified by UNOPPTAB
2356 on operand OP0, with two results to TARG0 and TARG1.
2357 We assume that the order of the operands for the instruction
2358 is TARG0, TARG1, OP0.
2360 Either TARG0 or TARG1 may be zero, but what that means is that
2361 the result is not actually wanted. We will generate it into
2362 a dummy pseudo-reg and discard it. They may not both be zero.
2364 Returns 1 if this operation can be performed; 0 if not. */
2366 int
2369 {
2372 machine_mode wider_mode;
2383 /* Record where to go back to if we fail. */
2387 {
2396 }
2398 /* It can't be done in this mode. Can we do it in a wider mode? */
2401 {
2403 {
2405 {
2411 {
2415 }
2416 else
2418 }
2419 }
2420 }
2424 }
2425 \f
2426 /* Generate code to perform an operation specified by BINOPTAB
2427 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2428 We assume that the order of the operands for the instruction
2429 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2430 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2432 Either TARG0 or TARG1 may be zero, but what that means is that
2433 the result is not actually wanted. We will generate it into
2434 a dummy pseudo-reg and discard it. They may not both be zero.
2436 Returns 1 if this operation can be performed; 0 if not. */
2438 int
2441 {
2444 machine_mode wider_mode;
2455 /* Record where to go back to if we fail. */
2459 {
2466 /* If we are optimizing, force expensive constants into a register. */
2477 }
2479 /* It can't be done in this mode. Can we do it in a wider mode? */
2482 {
2484 {
2486 {
2494 {
2498 }
2499 else
2501 }
2502 }
2503 }
2507 }
2509 /* Expand the two-valued library call indicated by BINOPTAB, but
2510 preserve only one of the values. If TARG0 is non-NULL, the first
2511 value is placed into TARG0; otherwise the second value is placed
2512 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2513 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2514 This routine assumes that the value returned by the library call is
2515 as if the return value was of an integral mode twice as wide as the
2516 mode of OP0. Returns 1 if the call was successful. */
2518 bool
2521 {
2522 machine_mode mode;
2523 machine_mode libval_mode;
2524 rtx libval;
2526 rtx libfunc;
2528 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2536 /* The value returned by the library function will have twice as
2537 many bits as the nominal MODE. */
2541 libval_mode,
2544 /* Get the part of VAL containing the value that we want. */
2549 /* Move the into the desired location. */
2554 }
2556 \f
2557 /* Wrapper around expand_unop which takes an rtx code to specify
2558 the operation to perform, not an optab pointer. All other
2559 arguments are the same. */
2560 rtx
2563 {
2568 }
2570 /* Try calculating
2571 (clz:narrow x)
2572 as
2573 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2575 A similar operation can be used for clrsb. UNOPTAB says which operation
2576 we are trying to expand. */
2577 static rtx
2579 {
2580 opt_scalar_int_mode wider_mode_iter;
2582 {
2585 {
2598 temp = expand_binop
2602 wider_mode),
2608 }
2609 }
2611 }
2613 /* Attempt to emit (clrsb:mode op0) as
2614 (plus:mode (clz:mode (xor:mode op0 (ashr:mode op0 (const_int prec-1))))
2615 (const_int -1))
2616 if CLZ_DEFINED_VALUE_AT_ZERO (mode, val) is 2 and val is prec,
2617 or as
2618 (clz:mode (ior:mode (xor:mode (ashl:mode op0 (const_int 1))
2619 (ashr:mode op0 (const_int prec-1)))
2620 (const_int 1)))
2621 otherwise. */
2623 static rtx
2625 {
2635 else
2640 {
2644 {
2645 fail:
2648 }
2649 }
2658 OPTAB_DIRECT);
2663 {
2668 }
2674 {
2679 }
2687 }
2689 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2690 quantities, choosing which based on whether the high word is nonzero. */
2691 static rtx
2693 {
2702 /* If we were not given a target, use a word_mode register, not a
2703 'mode' register. The result will fit, and nobody is expecting
2704 anything bigger (the return type of __builtin_clz* is int). */
2708 /* In any case, write to a word_mode scratch in both branches of the
2709 conditional, so we can ensure there is a single move insn setting
2710 'target' to tag a REG_EQUAL note on. */
2715 /* If the high word is not equal to zero,
2716 then clz of the full value is clz of the high word. */
2730 /* Else clz of the full value is clz of the low word plus the number
2731 of bits in the high word. */
2755 fail:
2758 }
2760 /* Try calculating popcount of a double-word quantity as two popcount's of
2761 word-sized quantities and summing up the results. */
2762 static rtx
2764 {
2777 {
2780 }
2782 /* If we were not given a target, use a word_mode register, not a
2783 'mode' register. The result will fit, and nobody is expecting
2784 anything bigger (the return type of __builtin_popcount* is int). */
2796 }
2798 /* Try calculating
2799 (parity:wide x)
2800 as
2801 (parity:narrow (low (x) ^ high (x))) */
2802 static rtx
2804 {
2810 }
2812 /* Try calculating
2813 (bswap:narrow x)
2814 as
2815 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2816 static rtx
2818 {
2819 rtx x;
2821 opt_scalar_int_mode wider_mode_iter;
2846 {
2850 }
2851 else
2855 }
2857 /* Try calculating bswap as two bswaps of two word-sized operands. */
2859 static rtx
2861 {
2877 }
2879 /* Try calculating (parity x) as (and (popcount x) 1), where
2880 popcount can also be done in a wider mode. */
2881 static rtx
2883 {
2885 opt_scalar_int_mode wider_mode_iter;
2887 {
2890 {
2907 {
2911 else
2913 }
2914 else
2916 }
2917 }
2919 }
2921 /* Try calculating ctz(x) as K - clz(x & -x) ,
2922 where K is GET_MODE_PRECISION(mode) - 1.
2924 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2925 don't have to worry about what the hardware does in that case. (If
2926 the clz instruction produces the usual value at 0, which is K, the
2927 result of this code sequence will be -1; expand_ffs, below, relies
2928 on this. It might be nice to have it be K instead, for consistency
2929 with the (very few) processors that provide a ctz with a defined
2930 value, but that would take one more instruction, and it would be
2931 less convenient for expand_ffs anyway. */
2933 static rtx
2935 {
2937 rtx temp;
2956 {
2959 }
2967 }
2970 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2971 else with the sequence used by expand_clz.
2973 The ffs builtin promises to return zero for a zero value and ctz/clz
2974 may have an undefined value in that case. If they do not give us a
2975 convenient value, we have to generate a test and branch. */
2976 static rtx
2978 {
2981 rtx temp;
2985 {
2993 }
2995 {
3002 {
3005 }
3006 }
3007 else
3012 else
3013 {
3014 /* We don't try to do anything clever with the situation found
3015 on some processors (eg Alpha) where ctz(0:mode) ==
3016 bitsize(mode). If someone can think of a way to send N to -1
3017 and leave alone all values in the range 0..N-1 (where N is a
3018 power of two), cheaper than this test-and-branch, please add it.
3020 The test-and-branch is done after the operation itself, in case
3021 the operation sets condition codes that can be recycled for this.
3022 (This is true on i386, for instance.) */
3030 }
3032 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
3033 to produce a value in the range 0..bitsize. */
3046 fail:
3049 }
3051 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
3052 conditions, VAL may already be a SUBREG against which we cannot generate
3053 a further SUBREG. In this case, we expect forcing the value into a
3054 register will work around the situation. */
3056 static rtx
3058 machine_mode imode)
3059 {
3060 rtx ret;
3063 {
3067 }
3069 }
3071 /* Expand a floating point absolute value or negation operation via a
3072 logical operation on the sign bit. */
3074 static rtx
3077 {
3080 scalar_int_mode imode;
3081 rtx temp;
3084 /* The format has to have a simple sign bit. */
3093 /* Don't create negative zeros if the format doesn't support them. */
3098 {
3103 }
3104 else
3105 {
3110 else
3114 }
3127 {
3131 {
3136 {
3138 op0_piece,
3143 }
3144 else
3146 }
3152 }
3153 else
3154 {
3163 target);
3164 }
3167 }
3169 /* As expand_unop, but will fail rather than attempt the operation in a
3170 different mode or with a libcall. */
3171 static rtx
3174 {
3176 {
3186 {
3191 {
3194 }
3199 }
3200 }
3202 }
3204 /* Generate code to perform an operation specified by UNOPTAB
3205 on operand OP0, with result having machine-mode MODE.
3207 UNSIGNEDP is for the case where we have to widen the operands
3208 to perform the operation. It says to use zero-extension.
3210 If TARGET is nonzero, the value
3211 is generated there, if it is convenient to do so.
3212 In all cases an rtx is returned for the locus of the value;
3213 this may or may not be TARGET. */
3215 rtx
3218 {
3220 machine_mode wider_mode;
3221 scalar_int_mode int_mode;
3222 scalar_float_mode float_mode;
3223 rtx temp;
3224 rtx libfunc;
3230 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3232 /* Widening (or narrowing) clz needs special treatment. */
3234 {
3236 {
3243 {
3247 }
3248 }
3251 }
3254 {
3256 {
3263 }
3265 }
3272 {
3276 }
3284 {
3288 }
3290 /* Widening (or narrowing) bswap needs special treatment. */
3292 {
3293 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3294 or ROTATERT. First try these directly; if this fails, then try the
3295 obvious pair of shifts with allowed widening, as this will probably
3296 be always more efficient than the other fallback methods. */
3298 {
3303 {
3309 }
3312 {
3318 }
3329 {
3334 }
3337 }
3340 {
3345 /* We do not provide a 128-bit bswap in libgcc so force the use of
3346 a double bswap for 64-bit targets. */
3350 {
3354 }
3355 }
3358 }
3362 {
3364 {
3368 /* For certain operations, we need not actually extend
3369 the narrow operand, as long as we will truncate the
3370 results to the same narrowness. */
3378 unsignedp);
3381 {
3384 {
3389 }
3390 else
3392 }
3393 else
3395 }
3396 }
3398 /* These can be done a word at a time. */
3403 {
3415 /* Do the actual arithmetic. */
3417 {
3425 }
3432 }
3434 /* Emit ~op0 as op0 ^ -1. */
3438 {
3443 }
3446 {
3447 /* Try negating floating point values by flipping the sign bit. */
3449 {
3453 }
3455 /* If there is no negation pattern, and we have no negative zero,
3456 try subtracting from zero. */
3458 {
3465 }
3466 }
3468 /* Try calculating parity (x) as popcount (x) % 2. */
3470 {
3474 }
3476 /* Try implementing ffs (x) in terms of clz (x). */
3478 {
3482 }
3484 /* Try implementing ctz (x) in terms of clz (x). */
3486 {
3490 }
3492 try_libcall:
3493 /* Now try a library call in this mode. */
3496 {
3498 rtx value;
3499 rtx eq_value;
3502 /* All of these functions return small values. Thus we choose to
3503 have them return something that isn't a double-word. */
3507 outmode
3513 /* Pass 1 for NO_QUEUE so we don't lose any increments
3514 if the libcall is cse'd or moved. */
3524 else
3525 {
3532 }
3536 }
3538 /* It can't be done in this mode. Can we do it in a wider mode? */
3541 {
3543 {
3546 {
3550 /* For certain operations, we need not actually extend
3551 the narrow operand, as long as we will truncate the
3552 results to the same narrowness. */
3560 unsignedp);
3562 /* If we are generating clz using wider mode, adjust the
3563 result. Similarly for clrsb. */
3566 {
3567 scalar_int_mode wider_int_mode
3570 temp = expand_binop
3574 wider_int_mode),
3576 }
3578 /* Likewise for bswap. */
3580 {
3581 scalar_int_mode wider_int_mode
3593 }
3596 {
3598 {
3603 }
3604 else
3606 }
3607 else
3609 }
3610 }
3611 }
3613 /* One final attempt at implementing negation via subtraction,
3614 this time allowing widening of the operand. */
3616 {
3617 rtx temp;
3624 }
3627 }
3628 \f
3629 /* Emit code to compute the absolute value of OP0, with result to
3630 TARGET if convenient. (TARGET may be 0.) The return value says
3631 where the result actually is to be found.
3633 MODE is the mode of the operand; the mode of the result is
3634 different but can be deduced from MODE.
3636 */
3638 rtx
3641 {
3642 rtx temp;
3648 /* First try to do it with a special abs instruction. */
3654 /* For floating point modes, try clearing the sign bit. */
3655 scalar_float_mode float_mode;
3657 {
3661 }
3663 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3666 {
3673 OPTAB_WIDEN);
3679 }
3681 /* If this machine has expensive jumps, we can do integer absolute
3682 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3683 where W is the width of MODE. */
3685 scalar_int_mode int_mode;
3689 {
3695 OPTAB_LIB_WIDEN);
3703 }
3706 }
3708 rtx
3711 {
3712 rtx temp;
3723 /* If that does not win, use conditional jump and negate. */
3725 /* It is safe to use the target if it is the same
3726 as the source if this is also a pseudo register */
3740 NO_DEFER_POP;
3751 OK_DEFER_POP;
3753 }
3755 /* Emit code to compute the one's complement absolute value of OP0
3756 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3757 (TARGET may be NULL_RTX.) The return value says where the result
3758 actually is to be found.
3760 MODE is the mode of the operand; the mode of the result is
3761 different but can be deduced from MODE. */
3763 rtx
3765 {
3766 rtx temp;
3768 /* Not applicable for floating point modes. */
3772 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3774 {
3780 OPTAB_WIDEN);
3786 }
3788 /* If this machine has expensive jumps, we can do one's complement
3789 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3791 scalar_int_mode int_mode;
3795 {
3801 OPTAB_LIB_WIDEN);
3805 }
3808 }
3810 /* A subroutine of expand_copysign, perform the copysign operation using the
3811 abs and neg primitives advertised to exist on the target. The assumption
3812 is that we have a split register file, and leaving op0 in fp registers,
3813 and not playing with subregs so much, will help the register allocator. */
3815 static rtx
3818 {
3819 scalar_int_mode imode;
3821 rtx sign;
3827 /* Check if the back end provides an insn that handles signbit for the
3828 argument's mode. */
3831 {
3835 }
3836 else
3837 {
3839 {
3843 }
3844 else
3845 {
3851 else
3855 }
3861 }
3864 {
3869 }
3870 else
3871 {
3874 else
3876 }
3883 else
3891 }
3894 /* A subroutine of expand_copysign, perform the entire copysign operation
3895 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3896 is true if op0 is known to have its sign bit clear. */
3898 static rtx
3901 {
3902 scalar_int_mode imode;
3904 rtx temp;
3908 {
3913 }
3914 else
3915 {
3920 else
3924 }
3937 {
3941 {
3946 {
3948 op0_piece
3961 }
3962 else
3964 }
3970 }
3971 else
3972 {
3986 }
3989 }
3991 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3992 scalar floating point mode. Return NULL if we do not know how to
3993 expand the operation inline. */
3995 rtx
3997 {
3998 scalar_float_mode mode;
4001 rtx temp;
4006 /* First try to do it with a special instruction. */
4018 {
4022 }
4028 {
4033 }
4039 }
4040 \f
4041 /* Generate an instruction whose insn-code is INSN_CODE,
4042 with two operands: an output TARGET and an input OP0.
4043 TARGET *must* be nonzero, and the output is always stored there.
4044 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4045 the value that is stored into TARGET.
4047 Return false if expansion failed. */
4049 bool
4052 {
4072 }
4073 /* Generate an instruction whose insn-code is INSN_CODE,
4074 with two operands: an output TARGET and an input OP0.
4075 TARGET *must* be nonzero, and the output is always stored there.
4076 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4077 the value that is stored into TARGET. */
4079 void
4081 {
4084 }
4085 \f
4086 struct no_conflict_data
4087 {
4088 rtx target;
4091 };
4093 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
4094 the currently examined clobber / store has to stay in the list of
4095 insns that constitute the actual libcall block. */
4096 static void
4098 {
4101 /* If this inns directly contributes to setting the target, it must stay. */
4104 /* If we haven't committed to keeping any other insns in the list yet,
4105 there is nothing more to check. */
4108 /* If this insn sets / clobbers a register that feeds one of the insns
4109 already in the list, this insn has to stay too. */
4113 /* Likewise if this insn depends on a register set by a previous
4114 insn in the list, or if it sets a result (presumably a hard
4115 register) that is set or clobbered by a previous insn.
4116 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
4117 SET_DEST perform the former check on the address, and the latter
4118 check on the MEM. */
4125 }
4127 \f
4128 /* Emit code to make a call to a constant function or a library call.
4130 INSNS is a list containing all insns emitted in the call.
4131 These insns leave the result in RESULT. Our block is to copy RESULT
4132 to TARGET, which is logically equivalent to EQUIV.
4134 We first emit any insns that set a pseudo on the assumption that these are
4135 loading constants into registers; doing so allows them to be safely cse'ed
4136 between blocks. Then we emit all the other insns in the block, followed by
4137 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
4138 note with an operand of EQUIV. */
4140 static void
4143 {
4147 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
4148 into a MEM later. Protect the libcall block from this change. */
4152 /* If we're using non-call exceptions, a libcall corresponding to an
4153 operation that may trap may also trap. */
4154 /* ??? See the comment in front of make_reg_eh_region_note. */
4157 {
4160 {
4163 {
4167 }
4168 }
4169 }
4170 else
4171 {
4172 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
4173 reg note to indicate that this call cannot throw or execute a nonlocal
4174 goto (unless there is already a REG_EH_REGION note, in which case
4175 we update it). */
4179 }
4181 /* First emit all insns that set pseudos. Remove them from the list as
4182 we go. Avoid insns that set pseudos which were referenced in previous
4183 insns. These can be generated by move_by_pieces, for example,
4184 to update an address. Similarly, avoid insns that reference things
4185 set in previous insns. */
4188 {
4195 {
4204 {
4207 else
4214 }
4215 }
4217 /* Some ports use a loop to copy large arguments onto the stack.
4218 Don't move anything outside such a loop. */
4221 }
4223 /* Write the remaining insns followed by the final copy. */
4225 {
4229 }
4237 }
4239 void
4241 {
4243 }
4244 \f
4245 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4246 PURPOSE describes how this comparison will be used. CODE is the rtx
4247 comparison code we will be using.
4249 ??? Actually, CODE is slightly weaker than that. A target is still
4250 required to implement all of the normal bcc operations, but not
4251 required to implement all (or any) of the unordered bcc operations. */
4253 int
4256 {
4257 rtx test;
4259 do
4260 {
4277 }
4281 }
4283 /* Return whether RTL code CODE corresponds to an unsigned optab. */
4285 static bool
4287 {
4289 }
4291 /* Return whether the backend-emitted comparison for code CODE, comparing
4292 operands of mode VALUE_MODE and producing a result with MASK_MODE, matches
4293 operand OPNO of pattern ICODE. */
4295 static bool
4298 machine_mode value_mode)
4299 {
4304 }
4306 /* Return whether the backend can emit a vector comparison (vec_cmp/vec_cmpu)
4307 for code CODE, comparing operands of mode VALUE_MODE and producing a result
4308 with MASK_MODE. */
4310 bool
4312 machine_mode mask_mode)
4313 {
4314 enum insn_code icode
4320 }
4322 /* Return whether the backend can emit a vector comparison (vcond/vcondu) for
4323 code CODE, comparing operands of mode CMP_OP_MODE and producing a result
4324 with VALUE_MODE. */
4326 bool
4328 machine_mode cmp_op_mode)
4329 {
4330 enum insn_code icode
4336 }
4338 /* Return whether the backend can emit vector set instructions for inserting
4339 element into vector at variable index position. */
4341 bool
4343 {
4362 }
4364 /* This function is called when we are going to emit a compare instruction that
4365 compares the values found in X and Y, using the rtl operator COMPARISON.
4367 If they have mode BLKmode, then SIZE specifies the size of both operands.
4369 UNSIGNEDP nonzero says that the operands are unsigned;
4370 this matters if they need to be widened (as given by METHODS).
4372 *PTEST is where the resulting comparison RTX is returned or NULL_RTX
4373 if we failed to produce one.
4375 *PMODE is the mode of the inputs (in case they are const_int).
4377 This function performs all the setup necessary so that the caller only has
4378 to emit a single comparison insn. This setup can involve doing a BLKmode
4379 comparison or emitting a library call to perform the comparison if no insn
4380 is available to handle it.
4381 The values which are passed in through pointers can be modified; the caller
4382 should perform the comparison on the modified values. Constant
4383 comparisons must have already been folded. */
4385 static void
4389 {
4392 machine_mode cmp_mode;
4394 /* The other methods are not needed. */
4401 /* If we are optimizing, force expensive constants into a register. */
4414 /* Don't let both operands fail to indicate the mode. */
4420 /* Handle all BLKmode compares. */
4423 {
4424 machine_mode result_mode;
4426 rtx result;
4427 rtx opalign
4432 /* Try to use a memory block compare insn - either cmpstr
4433 or cmpmem will do. */
4434 opt_scalar_int_mode cmp_mode_iter;
4436 {
4446 /* Must make sure the size fits the insn's mode. */
4461 }
4466 /* Otherwise call a library function. */
4474 }
4476 /* Don't allow operands to the compare to trap, as that can put the
4477 compare and branch in different basic blocks. */
4479 {
4486 }
4489 {
4496 }
4500 {
4505 {
4512 {
4518 }
4520 }
4524 }
4530 {
4531 /* Small trick if UNORDERED isn't implemented by the hardware. */
4533 {
4538 }
4541 }
4542 else
4543 {
4544 rtx result;
4545 machine_mode ret_mode;
4547 /* Handle a libcall just for the mode we are using. */
4551 /* If we want unsigned, and this mode has a distinct unsigned
4552 comparison routine, use that. */
4554 {
4558 }
4564 /* There are two kinds of comparison routines. Biased routines
4565 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4566 of gcc expect that the comparison operation is equivalent
4567 to the modified comparison. For signed comparisons compare the
4568 result against 1 in the biased case, and zero in the unbiased
4569 case. For unsigned comparisons always compare against 1 after
4570 biasing the unbiased result by adding 1. This gives us a way to
4571 represent LTU.
4572 The comparisons in the fixed-point helper library are always
4573 biased. */
4578 {
4581 else
4583 }
4588 }
4592 fail:
4594 }
4596 /* Before emitting an insn with code ICODE, make sure that X, which is going
4597 to be used for operand OPNUM of the insn, is converted from mode MODE to
4598 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4599 that it is accepted by the operand predicate. Return the new value. */
4601 rtx
4604 {
4609 {
4616 }
4619 }
4621 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4622 we can do the branch. */
4624 static void
4626 profile_probability prob)
4627 {
4628 machine_mode optab_mode;
4643 && insn
4648 }
4650 /* Generate code to compare X with Y so that the condition codes are
4651 set and to jump to LABEL if the condition is true. If X is a
4652 constant and Y is not a constant, then the comparison is swapped to
4653 ensure that the comparison RTL has the canonical form.
4655 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4656 need to be widened. UNSIGNEDP is also used to select the proper
4657 branch condition code.
4659 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4661 MODE is the mode of the inputs (in case they are const_int).
4663 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4664 It will be potentially converted into an unsigned variant based on
4665 UNSIGNEDP to select a proper jump instruction.
4667 PROB is the probability of jumping to LABEL. */
4669 void
4672 profile_probability prob)
4673 {
4675 rtx test;
4677 /* Swap operands and condition to ensure canonical RTL. */
4680 {
4683 }
4685 /* If OP0 is still a constant, then both X and Y must be constants
4686 or the opposite comparison is not supported. Force X into a register
4687 to create canonical RTL. */
4697 }
4699 \f
4700 /* Emit a library call comparison between floating point X and Y.
4701 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4703 static void
4706 {
4710 machine_mode mode;
4719 {
4726 {
4730 }
4734 {
4738 }
4739 }
4744 {
4747 }
4749 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4750 the RTL. The allows the RTL optimizers to delete the libcall if the
4751 condition can be determined at compile-time. */
4754 {
4757 }
4758 else
4759 {
4761 {
4794 }
4795 }
4798 {
4803 }
4804 else
4805 {
4810 }
4825 else
4829 }
4830 \f
4831 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4833 void
4835 {
4838 else
4839 {
4844 }
4845 }
4846 \f
4848 /* Emit a conditional move instruction if the machine supports one for that
4849 condition and machine mode.
4851 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4852 the mode to use should they be constants. If it is VOIDmode, they cannot
4853 both be constants.
4855 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4856 should be stored there. MODE is the mode to use should they be constants.
4857 If it is VOIDmode, they cannot both be constants.
4859 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4860 is not supported. */
4862 rtx
4866 {
4867 rtx comparison;
4872 /* If the two source operands are identical, that's just a move. */
4875 {
4881 }
4883 /* If one operand is constant, make it the second one. Only do this
4884 if the other operand is not constant as well. */
4887 {
4890 }
4892 /* get_condition will prefer to generate LT and GT even if the old
4893 comparison was against zero, so undo that canonicalization here since
4894 comparisons against zero are cheaper. */
4910 {
4914 }
4928 {
4930 comparison =
4934 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4935 punt and let the caller figure out how best to deal with this
4936 situation. */
4938 {
4939 saved_pending_stack_adjust save;
4948 {
4953 }
4956 }
4961 /* If the preferred op2/op3 order is not usable, retry with other
4962 operand order, perhaps it will expand successfully. */
4967 NULL))
4970 else
4973 }
4974 }
4976 /* Helper function that, in addition to COMPARISON, also tries
4977 the reversed REV_COMPARISON with swapped OP2 and OP3. As opposed
4978 to when we pass the specific constituents of a comparison, no
4979 additional insns are emitted for it. It might still be necessary
4980 to emit more than one insn for the final conditional move, though. */
4982 rtx
4985 {
4992 }
4994 /* Helper for emitting a conditional move. */
4996 static rtx
4999 {
5005 /* If the two source operands are identical, that's just a move.
5006 As the comparison comes in non-canonicalized, we must make
5007 sure not to discard any possible side effects. If there are
5008 side effects, just let the target handle it. */
5010 {
5016 }
5037 {
5041 }
5044 }
5047 /* Emit a conditional negate or bitwise complement using the
5048 negcc or notcc optabs if available. Return NULL_RTX if such operations
5049 are not available. Otherwise return the RTX holding the result.
5050 TARGET is the desired destination of the result. COMP is the comparison
5051 on which to negate. If COND is true move into TARGET the negation
5052 or bitwise complement of OP1. Otherwise move OP2 into TARGET.
5053 CODE is either NEG or NOT. MODE is the machine mode in which the
5054 operation is performed. */
5056 rtx
5059 rtx op2)
5060 {
5066 else
5086 {
5091 }
5094 }
5096 /* Emit a conditional addition instruction if the machine supports one for that
5097 condition and machine mode.
5099 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
5100 the mode to use should they be constants. If it is VOIDmode, they cannot
5101 both be constants.
5103 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
5104 should be stored there. MODE is the mode to use should they be constants.
5105 If it is VOIDmode, they cannot both be constants.
5107 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
5108 is not supported. */
5110 rtx
5114 {
5115 rtx comparison;
5119 /* If one operand is constant, make it the second one. Only do this
5120 if the other operand is not constant as well. */
5123 {
5126 }
5128 /* get_condition will prefer to generate LT and GT even if the old
5129 comparison was against zero, so undo that canonicalization here since
5130 comparisons against zero are cheaper. */
5153 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
5154 return NULL and let the caller figure out how best to deal with this
5155 situation. */
5165 {
5173 {
5177 }
5178 }
5181 }
5182 \f
5183 /* These functions attempt to generate an insn body, rather than
5184 emitting the insn, but if the gen function already emits them, we
5185 make no attempt to turn them back into naked patterns. */
5187 /* Generate and return an insn body to add Y to X. */
5189 rtx_insn *
5191 {
5199 }
5201 /* Generate and return an insn body to add r1 and c,
5202 storing the result in r0. */
5204 rtx_insn *
5206 {
5216 }
5218 int
5220 {
5236 }
5238 /* Generate and return an insn body to add Y to X. */
5240 rtx_insn *
5242 {
5250 }
5252 /* Return true if the target implements an addptr pattern and X, Y,
5253 and Z are valid for the pattern predicates. */
5255 int
5257 {
5273 }
5275 /* Generate and return an insn body to subtract Y from X. */
5277 rtx_insn *
5279 {
5287 }
5289 /* Generate and return an insn body to subtract r1 and c,
5290 storing the result in r0. */
5292 rtx_insn *
5294 {
5304 }
5306 int
5308 {
5324 }
5325 \f
5326 /* Generate the body of an insn to extend Y (with mode MFROM)
5327 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
5329 rtx_insn *
5332 {
5335 }
5336 \f
5337 /* Generate code to convert FROM to floating point
5338 and store in TO. FROM must be fixed point and not VOIDmode.
5339 UNSIGNEDP nonzero means regard FROM as unsigned.
5340 Normally this is done by correcting the final value
5341 if it is negative. */
5343 void
5345 {
5352 /* Crash now, because we won't be able to decide which mode to use. */
5355 /* Look for an insn to do the conversion. Do it in the specified
5356 modes if possible; otherwise convert either input, output or both to
5357 wider mode. If the integer mode is wider than the mode of FROM,
5358 we can do the conversion signed even if the input is unsigned. */
5362 {
5372 {
5378 }
5381 {
5394 }
5395 }
5397 /* Unsigned integer, and no way to convert directly. Convert as signed,
5398 then unconditionally adjust the result. */
5400 && can_do_signed
5403 {
5404 opt_scalar_mode fmode_iter;
5406 rtx temp;
5407 REAL_VALUE_TYPE offset;
5409 /* Look for a usable floating mode FMODE wider than the source and at
5410 least as wide as the target. Using FMODE will avoid rounding woes
5411 with unsigned values greater than the signed maximum value. */
5414 {
5419 }
5422 {
5423 /* There is no such mode. Pretend the target is wide enough. */
5426 /* Avoid double-rounding when TO is narrower than FROM. */
5429 {
5430 rtx temp1;
5433 /* Don't use TARGET if it isn't a register, is a hard register,
5434 or is the wrong mode. */
5443 /* Test whether the sign bit is set. */
5447 /* The sign bit is not set. Convert as signed. */
5452 /* The sign bit is set.
5453 Convert to a usable (positive signed) value by shifting right
5454 one bit, while remembering if a nonzero bit was shifted
5455 out; i.e., compute (from & 1) | (from >> 1). */
5462 OPTAB_LIB_WIDEN);
5465 /* Multiply by 2 to undo the shift above. */
5474 }
5475 }
5477 /* If we are about to do some arithmetic to correct for an
5478 unsigned operand, do it in a pseudo-register. */
5484 /* Convert as signed integer to floating. */
5487 /* If FROM is negative (and therefore TO is negative),
5488 correct its value by 2**bitwidth. */
5505 }
5507 /* No hardware instruction available; call a library routine. */
5508 {
5509 rtx libfunc;
5511 rtx value;
5530 }
5532 done:
5534 /* Copy result to requested destination
5535 if we have been computing in a temp location. */
5538 {
5541 else
5543 }
5544 }
5545 \f
5546 /* Generate code to convert FROM to fixed point and store in TO. FROM
5547 must be floating point. */
5549 void
5551 {
5555 opt_scalar_mode fmode_iter;
5558 /* We first try to find a pair of modes, one real and one integer, at
5559 least as wide as FROM and TO, respectively, in which we can open-code
5560 this conversion. If the integer mode is wider than the mode of TO,
5561 we can do the conversion either signed or unsigned. */
5565 {
5573 {
5580 {
5584 }
5591 {
5595 }
5597 }
5598 }
5600 /* For an unsigned conversion, there is one more way to do it.
5601 If we have a signed conversion, we generate code that compares
5602 the real value to the largest representable positive number. If if
5603 is smaller, the conversion is done normally. Otherwise, subtract
5604 one plus the highest signed number, convert, and add it back.
5606 We only need to check all real modes, since we know we didn't find
5607 anything with a wider integer mode.
5609 This code used to extend FP value into mode wider than the destination.
5610 This is needed for decimal float modes which cannot accurately
5611 represent one plus the highest signed number of the same size, but
5612 not for binary modes. Consider, for instance conversion from SFmode
5613 into DImode.
5615 The hot path through the code is dealing with inputs smaller than 2^63
5616 and doing just the conversion, so there is no bits to lose.
5618 In the other path we know the value is positive in the range 2^63..2^64-1
5619 inclusive. (as for other input overflow happens and result is undefined)
5620 So we know that the most important bit set in mantissa corresponds to
5621 2^63. The subtraction of 2^63 should not generate any rounding as it
5622 simply clears out that bit. The rest is trivial. */
5624 scalar_int_mode to_mode;
5629 {
5635 {
5637 REAL_VALUE_TYPE offset;
5638 rtx limit;
5651 /* See if we need to do the subtraction. */
5656 /* If not, do the signed "fix" and branch around fixup code. */
5661 /* Otherwise, subtract 2**(N-1), convert to signed number,
5662 then add 2**(N-1). Do the addition using XOR since this
5663 will often generate better code. */
5669 gen_int_mode
5671 to_mode),
5680 {
5681 /* Make a place for a REG_NOTE and add it. */
5686 to);
5687 }
5690 }
5691 }
5693 /* We can't do it with an insn, so use a library call. But first ensure
5694 that the mode of TO is at least as wide as SImode, since those are the
5695 only library calls we know about. */
5698 {
5702 }
5703 else
5704 {
5706 rtx value;
5707 rtx libfunc;
5723 }
5726 {
5729 else
5731 }
5732 }
5735 /* Promote integer arguments for a libcall if necessary.
5736 emit_library_call_value cannot do the promotion because it does not
5737 know if it should do a signed or unsigned promotion. This is because
5738 there are no tree types defined for libcalls. */
5740 static rtx
5742 {
5743 scalar_int_mode mode;
5744 machine_mode arg_mode;
5746 {
5747 /* If we need to promote the integer function argument we need to do
5748 it here instead of inside emit_library_call_value because in
5749 emit_library_call_value we don't know if we should do a signed or
5750 unsigned promotion. */
5757 }
5759 }
5761 /* Generate code to convert FROM or TO a fixed-point.
5762 If UINTP is true, either TO or FROM is an unsigned integer.
5763 If SATP is true, we need to saturate the result. */
5765 void
5767 {
5770 convert_optab tab;
5774 rtx value;
5775 rtx libfunc;
5778 {
5781 }
5784 {
5787 }
5788 else
5789 {
5792 }
5795 {
5798 }
5814 }
5816 /* Generate code to convert FROM to fixed point and store in TO. FROM
5817 must be floating point, TO must be signed. Use the conversion optab
5818 TAB to do the conversion. */
5820 bool
5822 {
5827 /* We first try to find a pair of modes, one real and one integer, at
5828 least as wide as FROM and TO, respectively, in which we can open-code
5829 this conversion. If the integer mode is wider than the mode of TO,
5830 we can do the conversion either signed or unsigned. */
5834 {
5838 {
5847 {
5850 }
5854 }
5855 }
5858 }
5859 \f
5860 /* Report whether we have an instruction to perform the operation
5861 specified by CODE on operands of mode MODE. */
5862 int
5864 {
5868 }
5870 /* Print information about the current contents of the optabs on
5871 STDERR. */
5873 DEBUG_FUNCTION void
5875 {
5878 /* Dump the arithmetic optabs. */
5881 {
5884 {
5890 }
5891 }
5893 /* Dump the conversion optabs. */
5897 {
5901 {
5908 }
5909 }
5910 }
5912 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5913 CODE. Return 0 on failure. */
5915 rtx_insn *
5917 {
5921 rtx trap_rtx;
5930 /* Some targets only accept a zero trap code. */
5940 else
5942 tcode);
5944 /* If that failed, then give up. */
5946 {
5949 }
5955 }
5957 /* Return rtx code for TCODE or UNKNOWN. Use UNSIGNEDP to select signed
5958 or unsigned operation code. */
5960 enum rtx_code
5962 {
5965 {
6021 }
6023 }
6025 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6026 or unsigned operation code. */
6028 enum rtx_code
6030 {
6034 }
6036 /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to
6037 select signed or unsigned operators. OPNO holds the index of the
6038 first comparison operand for insn ICODE. Do not generate the
6039 compare instruction itself. */
6041 rtx
6045 {
6053 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
6054 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
6055 cases, use the original mode. */
6057 EXPAND_STACK_PARM);
6063 EXPAND_STACK_PARM);
6073 }
6075 /* Check if vec_perm mask SEL is a constant equivalent to a shift of
6076 the first vec_perm operand, assuming the second operand (for left shift
6077 first operand) is a constant vector of zeros. Return the shift distance
6078 in bits if so, or NULL_RTX if the vec_perm is not a shift. MODE is the
6079 mode of the value being shifted. SHIFT_OPTAB is vec_shr_optab for right
6080 shift or vec_shl_optab for left shift. */
6081 static rtx
6083 optab shift_optab)
6084 {
6091 {
6097 {
6099 {
6103 }
6108 }
6113 }
6115 {
6120 {
6122 /* Indices into the second vector are all equivalent. */
6127 }
6128 }
6131 }
6133 /* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */
6135 static rtx
6138 {
6148 /* Make an effort to preserve v0 == v1. The target expander is able to
6149 rely on this to determine if we're permuting a single input operand. */
6151 {
6159 }
6160 else
6161 {
6164 }
6169 }
6171 /* Implement a permutation of vectors v0 and v1 using the permutation
6172 vector in SEL and return the result. Use TARGET to hold the result
6173 if nonnull and convenient.
6175 MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE
6176 is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known
6177 to have a particular mode. */
6179 rtx
6182 rtx target)
6183 {
6187 /* Set QIMODE to a different vector mode with byte elements.
6188 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6189 machine_mode qimode;
6196 /* Always specify two input vectors here and leave the target to handle
6197 cases in which the inputs are equal. Not all backends can cope with
6198 the single-input representation when testing for a double-input
6199 target instruction. */
6202 /* See if this can be handled with a vec_shr or vec_shl. We only do this
6203 if the second (for vec_shr) or first (for vec_shl) vector is all
6204 zeroes. */
6212 {
6215 }
6217 {
6222 }
6224 {
6227 {
6232 {
6238 }
6240 {
6247 }
6248 }
6249 }
6252 {
6259 indices))
6261 }
6263 /* Fall back to a constant byte-based permutation. */
6264 vec_perm_indices qimode_indices;
6267 {
6276 }
6283 /* Otherwise expand as a fully variable permuation. */
6285 /* The optabs are only defined for selectors with the same width
6286 as the values being permuted. */
6287 machine_mode required_sel_mode;
6289 {
6292 }
6294 /* We know that it is semantically valid to treat SEL as having SEL_MODE.
6295 If that isn't the mode we want then we need to prove that using
6296 REQUIRED_SEL_MODE is OK. */
6298 {
6300 {
6303 }
6305 }
6309 {
6314 }
6318 {
6321 {
6326 }
6327 }
6331 }
6333 /* Implement a permutation of vectors v0 and v1 using the permutation
6334 vector in SEL and return the result. Use TARGET to hold the result
6335 if nonnull and convenient.
6337 MODE is the mode of the vectors being permuted (V0 and V1).
6338 SEL must have the integer equivalent of MODE and is known to be
6339 unsuitable for permutes with a constant permutation vector. */
6341 rtx
6343 {
6355 {
6359 }
6361 /* As a special case to aid several targets, lower the element-based
6362 permutation to a byte-based permutation and try again. */
6363 machine_mode qimode;
6371 /* Multiply each element by its byte size. */
6376 else
6382 /* Broadcast the low byte each element into each of its bytes.
6383 The encoding has U interleaved stepped patterns, one for each
6384 byte of an element. */
6394 /* Add the byte offset to each byte element. */
6395 /* Note that the definition of the indicies here is memory ordering,
6396 so there should be no difference between big and little endian. */
6411 }
6413 /* Generate VEC_SERIES_EXPR <OP0, OP1>, returning a value of mode VMODE.
6414 Use TARGET for the result if nonnull and convenient. */
6416 rtx
6418 {
6432 }
6434 /* Generate insns for a vector comparison into a mask. */
6436 rtx
6438 {
6441 rtx comparison;
6443 machine_mode vmode;
6457 {
6462 }
6472 }
6474 /* Expand a highpart multiply. */
6476 rtx
6479 {
6483 machine_mode wmode;
6489 {
6495 OPTAB_LIB_WIDEN);
6508 }
6528 vec_perm_builder sel;
6530 {
6531 /* The encoding has 2 interleaved stepped patterns. */
6536 }
6537 else
6538 {
6539 /* The encoding has a single interleaved stepped pattern. */
6543 }
6546 }
6547 \f
6548 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6549 pattern. */
6551 static void
6553 {
6556 {
6560 }
6561 }
6563 /* This is a helper function for the other atomic operations. This function
6564 emits a loop that contains SEQ that iterates until a compare-and-swap
6565 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6566 a set of instructions that takes a value from OLD_REG as an input and
6567 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6568 set to the current contents of MEM. After SEQ, a compare-and-swap will
6569 attempt to update MEM with NEW_REG. The function returns true when the
6570 loop was generated successfully. */
6572 static bool
6574 {
6579 /* The loop we want to generate looks like
6581 cmp_reg = mem;
6582 label:
6583 old_reg = cmp_reg;
6584 seq;
6585 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6586 if (success)
6587 goto label;
6589 Note that we only do the plain load from memory once. Subsequent
6590 iterations use the value loaded by the compare-and-swap pattern. */
6605 MEMMODEL_RELAXED))
6611 /* Mark this jump predicted not taken. */
6616 }
6619 /* This function tries to emit an atomic_exchange intruction. VAL is written
6620 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6621 using TARGET if possible. */
6623 static rtx
6625 {
6629 /* If the target supports the exchange directly, great. */
6632 {
6641 }
6644 }
6646 /* This function tries to implement an atomic exchange operation using
6647 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6648 The previous contents of *MEM are returned, using TARGET if possible.
6649 Since this instructionn is an acquire barrier only, stronger memory
6650 models may require additional barriers to be emitted. */
6652 static rtx
6655 {
6662 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6663 exists, and the memory model is stronger than acquire, add a release
6664 barrier before the instruction. */
6670 {
6677 }
6679 /* If an external test-and-set libcall is provided, use that instead of
6680 any external compare-and-swap that we might get from the compare-and-
6681 swap-loop expansion later. */
6683 {
6686 {
6687 rtx addr;
6693 }
6694 }
6696 /* If the test_and_set can't be emitted, eliminate any barrier that might
6697 have been emitted. */
6700 }
6702 /* This function tries to implement an atomic exchange operation using a
6703 compare_and_swap loop. VAL is written to *MEM. The previous contents of
6704 *MEM are returned, using TARGET if possible. No memory model is required
6705 since a compare_and_swap loop is seq-cst. */
6707 static rtx
6709 {
6713 {
6718 }
6721 }
6723 /* This function tries to implement an atomic test-and-set operation
6724 using the atomic_test_and_set instruction pattern. A boolean value
6725 is returned from the operation, using TARGET if possible. */
6727 static rtx
6729 {
6730 machine_mode pat_bool_mode;
6736 /* While we always get QImode from __atomic_test_and_set, we get
6737 other memory modes from __sync_lock_test_and_set. Note that we
6738 use no endian adjustment here. This matches the 4.6 behavior
6739 in the Sparc backend. */
6753 }
6755 /* This function expands the legacy _sync_lock test_and_set operation which is
6756 generally an atomic exchange. Some limited targets only allow the
6757 constant 1 to be stored. This is an ACQUIRE operation.
6759 TARGET is an optional place to stick the return value.
6760 MEM is where VAL is stored. */
6762 rtx
6764 {
6765 rtx ret;
6767 /* Try an atomic_exchange first. */
6773 MEMMODEL_SYNC_ACQUIRE);
6781 /* If there are no other options, try atomic_test_and_set if the value
6782 being stored is 1. */
6787 }
6789 /* This function expands the atomic test_and_set operation:
6790 atomically store a boolean TRUE into MEM and return the previous value.
6792 MEMMODEL is the memory model variant to use.
6793 TARGET is an optional place to stick the return value. */
6795 rtx
6797 {
6805 /* Be binary compatible with non-default settings of trueval, and different
6806 cpu revisions. E.g. one revision may have atomic-test-and-set, but
6807 another only has atomic-exchange. */
6809 {
6812 }
6813 else
6814 {
6817 }
6819 /* Try the atomic-exchange optab... */
6822 /* ... then an atomic-compare-and-swap loop ... */
6826 /* ... before trying the vaguely defined legacy lock_test_and_set. */
6830 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
6831 things with the value 1. Thus we try again without trueval. */
6835 /* Failing all else, assume a single threaded environment and simply
6836 perform the operation. */
6838 {
6839 /* If the result is ignored skip the move to target. */
6845 }
6847 /* Recall that have to return a boolean value; rectify if trueval
6848 is not exactly one. */
6853 }
6855 /* This function expands the atomic exchange operation:
6856 atomically store VAL in MEM and return the previous value in MEM.
6858 MEMMODEL is the memory model variant to use.
6859 TARGET is an optional place to stick the return value. */
6861 rtx
6863 {
6865 rtx ret;
6867 /* If loads are not atomic for the required size and we are not called to
6868 provide a __sync builtin, do not do anything so that we stay consistent
6869 with atomic loads of the same size. */
6875 /* Next try a compare-and-swap loop for the exchange. */
6880 }
6882 /* This function expands the atomic compare exchange operation:
6884 *PTARGET_BOOL is an optional place to store the boolean success/failure.
6885 *PTARGET_OVAL is an optional place to store the old value from memory.
6886 Both target parameters may be NULL or const0_rtx to indicate that we do
6887 not care about that return value. Both target parameters are updated on
6888 success to the actual location of the corresponding result.
6890 MEMMODEL is the memory model variant to use.
6892 The return value of the function is true for success. */
6894 bool
6899 {
6904 rtx libfunc;
6906 /* If loads are not atomic for the required size and we are not called to
6907 provide a __sync builtin, do not do anything so that we stay consistent
6908 with atomic loads of the same size. */
6912 /* Load expected into a register for the compare and swap. */
6916 /* Make sure we always have some place to put the return oldval.
6917 Further, make sure that place is distinct from the input expected,
6918 just in case we need that path down below. */
6929 {
6935 /* Make sure we always have a place for the bool operand. */
6941 /* Emit the compare_and_swap. */
6951 {
6952 /* Return success/failure. */
6956 }
6957 }
6959 /* Otherwise fall back to the original __sync_val_compare_and_swap
6960 which is always seq-cst. */
6963 {
6964 rtx cc_reg;
6975 /* If the caller isn't interested in the boolean return value,
6976 skip the computation of it. */
6980 /* Otherwise, work out if the compare-and-swap succeeded. */
6985 {
6989 }
6991 }
6993 /* Also check for library support for __sync_val_compare_and_swap. */
6996 {
7003 /* Compute the boolean return value only if requested. */
7006 else
7008 }
7010 /* Failure. */
7013 success_bool_from_val:
7016 success:
7017 /* Make sure that the oval output winds up where the caller asked. */
7023 }
7025 /* Generate asm volatile("" : : : "memory") as the memory blockage. */
7027 static void
7029 {
7042 }
7044 /* Do not propagate memory accesses across this point. */
7046 static void
7048 {
7051 else
7053 }
7055 /* Generate asm volatile("" : : : "memory") as a memory blockage, at the
7056 same time clobbering the register set specified by REGS. */
7058 void
7060 {
7066 num_of_regs++;
7083 {
7087 {
7089 j++;
7090 }
7092 }
7095 }
7097 /* This routine will either emit the mem_thread_fence pattern or issue a
7098 sync_synchronize to generate a fence for memory model MEMMODEL. */
7100 void
7102 {
7106 {
7109 }
7114 else
7116 }
7118 /* Emit a signal fence with given memory model. */
7120 void
7122 {
7123 /* No machine barrier is required to implement a signal fence, but
7124 a compiler memory barrier must be issued, except for relaxed MM. */
7127 }
7129 /* This function expands the atomic load operation:
7130 return the atomically loaded value in MEM.
7132 MEMMODEL is the memory model variant to use.
7133 TARGET is an option place to stick the return value. */
7135 rtx
7137 {
7141 /* If the target supports the load directly, great. */
7144 {
7154 {
7158 }
7160 }
7162 /* If the size of the object is greater than word size on this target,
7163 then we assume that a load will not be atomic. We could try to
7164 emulate a load with a compare-and-swap operation, but the store that
7165 doing this could result in would be incorrect if this is a volatile
7166 atomic load or targetting read-only-mapped memory. */
7168 /* If there is no atomic load, leave the library call. */
7171 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7175 /* For SEQ_CST, emit a barrier before the load. */
7181 /* Emit the appropriate barrier after the load. */
7185 }
7187 /* This function expands the atomic store operation:
7188 Atomically store VAL in MEM.
7189 MEMMODEL is the memory model variant to use.
7190 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7191 function returns const0_rtx if a pattern was emitted. */
7193 rtx
7195 {
7200 /* If the target supports the store directly, great. */
7203 {
7211 {
7215 }
7217 }
7219 /* If using __sync_lock_release is a viable alternative, try it.
7220 Note that this will not be set to true if we are expanding a generic
7221 __atomic_store_n. */
7223 {
7226 {
7230 {
7231 /* lock_release is only a release barrier. */
7235 }
7236 }
7237 }
7239 /* If the size of the object is greater than word size on this target,
7240 a default store will not be atomic. */
7242 {
7243 /* If loads are atomic or we are called to provide a __sync builtin,
7244 we can try a atomic_exchange and throw away the result. Otherwise,
7245 don't do anything so that we do not create an inconsistency between
7246 loads and stores. */
7248 {
7252 val);
7255 }
7257 }
7259 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7264 /* For SEQ_CST, also emit a barrier after the store. */
7269 }
7272 /* Structure containing the pointers and values required to process the
7273 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7275 struct atomic_op_functions
7276 {
7277 direct_optab mem_fetch_before;
7278 direct_optab mem_fetch_after;
7279 direct_optab mem_no_result;
7280 optab fetch_before;
7281 optab fetch_after;
7282 direct_optab no_result;
7284 };
7287 /* Fill in structure pointed to by OP with the various optab entries for an
7288 operation of type CODE. */
7290 static void
7292 {
7295 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7296 in the source code during compilation, and the optab entries are not
7297 computable until runtime. Fill in the values at runtime. */
7299 {
7356 }
7357 }
7359 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7360 using memory order MODEL. If AFTER is true the operation needs to return
7361 the value of *MEM after the operation, otherwise the previous value.
7362 TARGET is an optional place to place the result. The result is unused if
7363 it is const0_rtx.
7364 Return the result if there is a better sequence, otherwise NULL_RTX. */
7366 static rtx
7369 {
7370 /* If the value is prefetched, or not used, it may be possible to replace
7371 the sequence with a native exchange operation. */
7373 {
7374 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7376 {
7380 }
7382 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7384 {
7388 }
7389 }
7392 }
7394 /* Try to emit an instruction for a specific operation varaition.
7395 OPTAB contains the OP functions.
7396 TARGET is an optional place to return the result. const0_rtx means unused.
7397 MEM is the memory location to operate on.
7398 VAL is the value to use in the operation.
7399 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7400 MODEL is the memory model, if used.
7401 AFTER is true if the returned result is the value after the operation. */
7403 static rtx
7406 {
7413 /* Check to see if there is a result returned. */
7415 {
7417 {
7421 }
7422 else
7423 {
7426 }
7427 }
7428 /* Otherwise, we need to generate a result. */
7429 else
7430 {
7432 {
7437 }
7438 else
7439 {
7443 }
7445 }
7450 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7457 }
7460 /* This function expands an atomic fetch_OP or OP_fetch operation:
7461 TARGET is an option place to stick the return value. const0_rtx indicates
7462 the result is unused.
7463 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7464 CODE is the operation being performed (OP)
7465 MEMMODEL is the memory model variant to use.
7466 AFTER is true to return the result of the operation (OP_fetch).
7467 AFTER is false to return the value before the operation (fetch_OP).
7469 This function will *only* generate instructions if there is a direct
7470 optab. No compare and swap loops or libcalls will be generated. */
7472 static rtx
7476 {
7479 rtx result;
7484 /* Check to see if there are any better instructions. */
7489 /* Check for the case where the result isn't used and try those patterns. */
7491 {
7492 /* Try the memory model variant first. */
7497 /* Next try the old style withuot a memory model. */
7502 /* There is no no-result pattern, so try patterns with a result. */
7504 }
7506 /* Try the __atomic version. */
7511 /* Try the older __sync version. */
7516 /* If the fetch value can be calculated from the other variation of fetch,
7517 try that operation. */
7519 {
7520 /* Try the __atomic version, then the older __sync version. */
7526 {
7527 /* If the result isn't used, no need to do compensation code. */
7531 /* Issue compensation code. Fetch_after == fetch_before OP val.
7532 Fetch_before == after REVERSE_OP val. */
7536 {
7540 }
7541 else
7545 }
7546 }
7548 /* No direct opcode can be generated. */
7550 }
7554 /* This function expands an atomic fetch_OP or OP_fetch operation:
7555 TARGET is an option place to stick the return value. const0_rtx indicates
7556 the result is unused.
7557 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7558 CODE is the operation being performed (OP)
7559 MEMMODEL is the memory model variant to use.
7560 AFTER is true to return the result of the operation (OP_fetch).
7561 AFTER is false to return the value before the operation (fetch_OP). */
7562 rtx
7565 {
7567 rtx result;
7570 /* If loads are not atomic for the required size and we are not called to
7571 provide a __sync builtin, do not do anything so that we stay consistent
7572 with atomic loads of the same size. */
7577 after);
7582 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7584 {
7585 rtx tmp;
7593 {
7594 /* PLUS worked so emit the insns and return. */
7599 }
7601 /* PLUS did not work, so throw away the negation code and continue. */
7603 }
7605 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7607 {
7608 rtx libfunc;
7618 {
7624 }
7626 {
7635 }
7637 /* We need the original code for any further attempts. */
7639 }
7641 /* If nothing else has succeeded, default to a compare and swap loop. */
7643 {
7649 /* If the result is used, get a register for it. */
7651 {
7654 /* If fetch_before, copy the value now. */
7657 }
7658 else
7663 {
7667 }
7668 else
7670 OPTAB_LIB_WIDEN);
7672 /* For after, copy the value now. */
7680 }
7683 }
7684 \f
7685 /* Return true if OPERAND is suitable for operand number OPNO of
7686 instruction ICODE. */
7688 bool
7690 {
7694 }
7695 \f
7696 /* TARGET is a target of a multiword operation that we are going to
7697 implement as a series of word-mode operations. Return true if
7698 TARGET is suitable for this purpose. */
7700 bool
7702 {
7703 machine_mode mode;
7713 }
7715 /* Make OP describe an input operand that has value INTVAL and that has
7716 no inherent mode. This function should only be used for operands that
7717 are always expand-time constants. The backend may request that INTVAL
7718 be copied into a different kind of rtx, but it must specify the mode
7719 of that rtx if so. */
7721 void
7723 {
7727 }
7729 /* Like maybe_legitimize_operand, but do not change the code of the
7730 current rtx value. */
7732 static bool
7735 {
7736 /* See if the operand matches in its current form. */
7740 /* If the operand is a memory whose address has no side effects,
7741 try forcing the address into a non-virtual pseudo register.
7742 The check for side effects is important because copy_to_mode_reg
7743 cannot handle things like auto-modified addresses. */
7745 {
7752 {
7754 machine_mode mode;
7760 {
7763 }
7765 }
7766 }
7769 }
7771 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7772 on success, storing the new operand value back in OP. */
7774 static bool
7777 {
7782 {
7784 {
7787 }
7802 input:
7820 else
7821 /* The caller must tell us what mode this value has. */
7828 {
7831 }
7833 {
7837 }
7850 {
7853 }
7855 }
7857 }
7859 /* Make OP describe an input operand that should have the same value
7860 as VALUE, after any mode conversion that the target might request.
7861 TYPE is the type of VALUE. */
7863 void
7866 {
7869 }
7871 /* Return true if the requirements on operands OP1 and OP2 of instruction
7872 ICODE are similar enough for the result of legitimizing OP1 to be
7873 reusable for OP2. OPNO1 and OPNO2 are the operand numbers associated
7874 with OP1 and OP2 respectively. */
7881 {
7882 /* Check requirements that are common to all types. */
7889 /* Check the requirements for specific types. */
7891 {
7893 /* Outputs must remain distinct. */
7905 }
7907 }
7909 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
7910 of instruction ICODE. Return true on success, leaving the new operand
7911 values in the OPS themselves. Emit no code on failure. */
7913 bool
7916 {
7920 {
7923 /* First try reusing the result of an earlier legitimization.
7924 This avoids duplicate rtl and ensures that tied operands
7925 remain tied.
7927 This search is linear, but NOPS is bounded at compile time
7928 to a small number (current a single digit). */
7935 {
7938 }
7940 /* Otherwise try legitimizing the operand on its own. */
7942 {
7945 }
7946 }
7948 }
7950 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
7951 as its operands. Return the instruction pattern on success,
7952 and emit any necessary set-up code. Return null and emit no
7953 code on failure. */
7955 rtx_insn *
7958 {
7964 {
7994 }
7996 }
7998 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
7999 as its operands. Return true on success and emit no code on failure. */
8001 bool
8004 {
8007 {
8010 }
8012 }
8014 /* Like maybe_expand_insn, but for jumps. */
8016 bool
8019 {
8022 {
8025 }
8027 }
8029 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8030 as its operands. */
8032 void
8035 {
8038 }
8040 /* Like expand_insn, but for jumps. */
8042 void
8045 {
8048 }