1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
53 #include "sched-int.h"
55 #include "tree-flow.h"
58 #include "tm-constrs.h"
60 #include "tree-vectorizer.h"
63 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66 #include "gstab.h" /* for N_SLINE */
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
73 #define min(A,B) ((A) < (B) ? (A) : (B))
74 #define max(A,B) ((A) > (B) ? (A) : (B))
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack
{
78 int reload_completed
; /* stack info won't change from here on */
79 int first_gp_reg_save
; /* first callee saved GP register used */
80 int first_fp_reg_save
; /* first callee saved FP register used */
81 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
82 int lr_save_p
; /* true if the link reg needs to be saved */
83 int cr_save_p
; /* true if the CR reg needs to be saved */
84 unsigned int vrsave_mask
; /* mask of vec registers to save */
85 int push_p
; /* true if we need to allocate stack space */
86 int calls_p
; /* true if the function makes any calls */
87 int world_save_p
; /* true if we're saving *everything*:
88 r13-r31, cr, f14-f31, vrsave, v20-v31 */
89 enum rs6000_abi abi
; /* which ABI to use */
90 int gp_save_offset
; /* offset to save GP regs from initial SP */
91 int fp_save_offset
; /* offset to save FP regs from initial SP */
92 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
93 int lr_save_offset
; /* offset to save LR from initial SP */
94 int cr_save_offset
; /* offset to save CR from initial SP */
95 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
96 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
97 int varargs_save_offset
; /* offset to save the varargs registers */
98 int ehrd_offset
; /* offset to EH return data */
99 int reg_size
; /* register size (4 or 8) */
100 HOST_WIDE_INT vars_size
; /* variable save area size */
101 int parm_size
; /* outgoing parameter size */
102 int save_size
; /* save area size */
103 int fixed_size
; /* fixed size of stack frame */
104 int gp_size
; /* size of saved GP registers */
105 int fp_size
; /* size of saved FP registers */
106 int altivec_size
; /* size of saved AltiVec registers */
107 int cr_size
; /* size to hold CR if not in save_size */
108 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size
; /* size of altivec alignment padding if
111 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size
;
113 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
114 int spe_64bit_regs_used
;
118 /* A C structure for machine-specific, per-function data.
119 This is added to the cfun structure. */
120 typedef struct GTY(()) machine_function
122 /* Some local-dynamic symbol. */
123 const char *some_ld_name
;
124 /* Whether the instruction chain has been scanned already. */
125 int insn_chain_scanned_p
;
126 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
127 int ra_needs_full_frame
;
128 /* Flags if __builtin_return_address (0) was used. */
130 /* Cache lr_save_p after expansion of builtin_eh_return. */
132 /* Whether we need to save the TOC to the reserved stack location in the
133 function prologue. */
134 bool save_toc_in_prologue
;
135 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
136 varargs save area. */
137 HOST_WIDE_INT varargs_save_offset
;
138 /* Temporary stack slot to use for SDmode copies. This slot is
139 64-bits wide and is allocated early enough so that the offset
140 does not overflow the 16-bit load/store offset field. */
141 rtx sdmode_stack_slot
;
144 /* Support targetm.vectorize.builtin_mask_for_load. */
145 static GTY(()) tree altivec_builtin_mask_for_load
;
147 /* Set to nonzero once AIX common-mode calls have been defined. */
148 static GTY(()) int common_mode_defined
;
150 /* Label number of label created for -mrelocatable, to call to so we can
151 get the address of the GOT section */
152 static int rs6000_pic_labelno
;
155 /* Counter for labels which are to be placed in .fixup. */
156 int fixuplabelno
= 0;
159 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
162 /* Specify the machine mode that pointers have. After generation of rtl, the
163 compiler makes no further distinction between pointers and any other objects
164 of this machine mode. The type is unsigned since not all things that
165 include rs6000.h also include machmode.h. */
166 unsigned rs6000_pmode
;
168 /* Width in bits of a pointer. */
169 unsigned rs6000_pointer_size
;
171 #ifdef HAVE_AS_GNU_ATTRIBUTE
172 /* Flag whether floating point values have been passed/returned. */
173 static bool rs6000_passes_float
;
174 /* Flag whether vector values have been passed/returned. */
175 static bool rs6000_passes_vector
;
176 /* Flag whether small (<= 8 byte) structures have been returned. */
177 static bool rs6000_returns_struct
;
180 /* Value is TRUE if register/mode pair is acceptable. */
181 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
183 /* Maximum number of registers needed for a given register class and mode. */
184 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
186 /* How many registers are needed for a given register and mode. */
187 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
189 /* Map register number to register class. */
190 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
192 /* Reload functions based on the type and the vector unit. */
193 static enum insn_code rs6000_vector_reload
[NUM_MACHINE_MODES
][2];
195 static int dbg_cost_ctrl
;
197 /* Built in types. */
198 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
199 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
201 /* Flag to say the TOC is initialized */
203 char toc_label_name
[10];
205 /* Cached value of rs6000_variable_issue. This is cached in
206 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
207 static short cached_can_issue_more
;
209 static GTY(()) section
*read_only_data_section
;
210 static GTY(()) section
*private_data_section
;
211 static GTY(()) section
*tls_data_section
;
212 static GTY(()) section
*tls_private_data_section
;
213 static GTY(()) section
*read_only_private_data_section
;
214 static GTY(()) section
*sdata2_section
;
215 static GTY(()) section
*toc_section
;
217 struct builtin_description
219 const HOST_WIDE_INT mask
;
220 const enum insn_code icode
;
221 const char *const name
;
222 const enum rs6000_builtins code
;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
227 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align
[NUM_MACHINE_MODES
];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask
{
246 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
247 RECIP_DF_DIV
= 0x002,
248 RECIP_V4SF_DIV
= 0x004,
249 RECIP_V2DF_DIV
= 0x008,
251 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT
= 0x020,
253 RECIP_V4SF_RSQRT
= 0x040,
254 RECIP_V2DF_RSQRT
= 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
262 RECIP_HIGH_PRECISION
= RECIP_ALL
,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
269 /* -mrecip options. */
272 const char *string
; /* option name */
273 unsigned int mask
; /* mask bits to set */
274 } recip_options
[] = {
275 { "all", RECIP_ALL
},
276 { "none", RECIP_NONE
},
277 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
280 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
281 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT
) },
283 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
284 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t
) (rtx
, rtx
, rtx
);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
296 /* Target cpu costs. */
298 struct processor_costs
{
299 const int mulsi
; /* cost of SImode multiplication. */
300 const int mulsi_const
; /* cost of SImode multiplication by constant. */
301 const int mulsi_const9
; /* cost of SImode mult by short constant. */
302 const int muldi
; /* cost of DImode multiplication. */
303 const int divsi
; /* cost of SImode division. */
304 const int divdi
; /* cost of DImode division. */
305 const int fp
; /* cost of simple SFmode and DFmode insns. */
306 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
307 const int sdiv
; /* cost of SFmode division (fdivs). */
308 const int ddiv
; /* cost of DFmode division (fdiv). */
309 const int cache_line_size
; /* cache line size in bytes. */
310 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
311 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
312 const int simultaneous_prefetches
; /* number of parallel prefetch
316 const struct processor_costs
*rs6000_cost
;
318 /* Processor costs (relative to an add) */
320 /* Instruction size costs on 32bit processors. */
322 struct processor_costs size32_cost
= {
323 COSTS_N_INSNS (1), /* mulsi */
324 COSTS_N_INSNS (1), /* mulsi_const */
325 COSTS_N_INSNS (1), /* mulsi_const9 */
326 COSTS_N_INSNS (1), /* muldi */
327 COSTS_N_INSNS (1), /* divsi */
328 COSTS_N_INSNS (1), /* divdi */
329 COSTS_N_INSNS (1), /* fp */
330 COSTS_N_INSNS (1), /* dmul */
331 COSTS_N_INSNS (1), /* sdiv */
332 COSTS_N_INSNS (1), /* ddiv */
339 /* Instruction size costs on 64bit processors. */
341 struct processor_costs size64_cost
= {
342 COSTS_N_INSNS (1), /* mulsi */
343 COSTS_N_INSNS (1), /* mulsi_const */
344 COSTS_N_INSNS (1), /* mulsi_const9 */
345 COSTS_N_INSNS (1), /* muldi */
346 COSTS_N_INSNS (1), /* divsi */
347 COSTS_N_INSNS (1), /* divdi */
348 COSTS_N_INSNS (1), /* fp */
349 COSTS_N_INSNS (1), /* dmul */
350 COSTS_N_INSNS (1), /* sdiv */
351 COSTS_N_INSNS (1), /* ddiv */
358 /* Instruction costs on RS64A processors. */
360 struct processor_costs rs64a_cost
= {
361 COSTS_N_INSNS (20), /* mulsi */
362 COSTS_N_INSNS (12), /* mulsi_const */
363 COSTS_N_INSNS (8), /* mulsi_const9 */
364 COSTS_N_INSNS (34), /* muldi */
365 COSTS_N_INSNS (65), /* divsi */
366 COSTS_N_INSNS (67), /* divdi */
367 COSTS_N_INSNS (4), /* fp */
368 COSTS_N_INSNS (4), /* dmul */
369 COSTS_N_INSNS (31), /* sdiv */
370 COSTS_N_INSNS (31), /* ddiv */
371 128, /* cache line size */
377 /* Instruction costs on MPCCORE processors. */
379 struct processor_costs mpccore_cost
= {
380 COSTS_N_INSNS (2), /* mulsi */
381 COSTS_N_INSNS (2), /* mulsi_const */
382 COSTS_N_INSNS (2), /* mulsi_const9 */
383 COSTS_N_INSNS (2), /* muldi */
384 COSTS_N_INSNS (6), /* divsi */
385 COSTS_N_INSNS (6), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (5), /* dmul */
388 COSTS_N_INSNS (10), /* sdiv */
389 COSTS_N_INSNS (17), /* ddiv */
390 32, /* cache line size */
396 /* Instruction costs on PPC403 processors. */
398 struct processor_costs ppc403_cost
= {
399 COSTS_N_INSNS (4), /* mulsi */
400 COSTS_N_INSNS (4), /* mulsi_const */
401 COSTS_N_INSNS (4), /* mulsi_const9 */
402 COSTS_N_INSNS (4), /* muldi */
403 COSTS_N_INSNS (33), /* divsi */
404 COSTS_N_INSNS (33), /* divdi */
405 COSTS_N_INSNS (11), /* fp */
406 COSTS_N_INSNS (11), /* dmul */
407 COSTS_N_INSNS (11), /* sdiv */
408 COSTS_N_INSNS (11), /* ddiv */
409 32, /* cache line size */
415 /* Instruction costs on PPC405 processors. */
417 struct processor_costs ppc405_cost
= {
418 COSTS_N_INSNS (5), /* mulsi */
419 COSTS_N_INSNS (4), /* mulsi_const */
420 COSTS_N_INSNS (3), /* mulsi_const9 */
421 COSTS_N_INSNS (5), /* muldi */
422 COSTS_N_INSNS (35), /* divsi */
423 COSTS_N_INSNS (35), /* divdi */
424 COSTS_N_INSNS (11), /* fp */
425 COSTS_N_INSNS (11), /* dmul */
426 COSTS_N_INSNS (11), /* sdiv */
427 COSTS_N_INSNS (11), /* ddiv */
428 32, /* cache line size */
434 /* Instruction costs on PPC440 processors. */
436 struct processor_costs ppc440_cost
= {
437 COSTS_N_INSNS (3), /* mulsi */
438 COSTS_N_INSNS (2), /* mulsi_const */
439 COSTS_N_INSNS (2), /* mulsi_const9 */
440 COSTS_N_INSNS (3), /* muldi */
441 COSTS_N_INSNS (34), /* divsi */
442 COSTS_N_INSNS (34), /* divdi */
443 COSTS_N_INSNS (5), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (19), /* sdiv */
446 COSTS_N_INSNS (33), /* ddiv */
447 32, /* cache line size */
453 /* Instruction costs on PPC476 processors. */
455 struct processor_costs ppc476_cost
= {
456 COSTS_N_INSNS (4), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (4), /* mulsi_const9 */
459 COSTS_N_INSNS (4), /* muldi */
460 COSTS_N_INSNS (11), /* divsi */
461 COSTS_N_INSNS (11), /* divdi */
462 COSTS_N_INSNS (6), /* fp */
463 COSTS_N_INSNS (6), /* dmul */
464 COSTS_N_INSNS (19), /* sdiv */
465 COSTS_N_INSNS (33), /* ddiv */
466 32, /* l1 cache line size */
472 /* Instruction costs on PPC601 processors. */
474 struct processor_costs ppc601_cost
= {
475 COSTS_N_INSNS (5), /* mulsi */
476 COSTS_N_INSNS (5), /* mulsi_const */
477 COSTS_N_INSNS (5), /* mulsi_const9 */
478 COSTS_N_INSNS (5), /* muldi */
479 COSTS_N_INSNS (36), /* divsi */
480 COSTS_N_INSNS (36), /* divdi */
481 COSTS_N_INSNS (4), /* fp */
482 COSTS_N_INSNS (5), /* dmul */
483 COSTS_N_INSNS (17), /* sdiv */
484 COSTS_N_INSNS (31), /* ddiv */
485 32, /* cache line size */
491 /* Instruction costs on PPC603 processors. */
493 struct processor_costs ppc603_cost
= {
494 COSTS_N_INSNS (5), /* mulsi */
495 COSTS_N_INSNS (3), /* mulsi_const */
496 COSTS_N_INSNS (2), /* mulsi_const9 */
497 COSTS_N_INSNS (5), /* muldi */
498 COSTS_N_INSNS (37), /* divsi */
499 COSTS_N_INSNS (37), /* divdi */
500 COSTS_N_INSNS (3), /* fp */
501 COSTS_N_INSNS (4), /* dmul */
502 COSTS_N_INSNS (18), /* sdiv */
503 COSTS_N_INSNS (33), /* ddiv */
504 32, /* cache line size */
510 /* Instruction costs on PPC604 processors. */
512 struct processor_costs ppc604_cost
= {
513 COSTS_N_INSNS (4), /* mulsi */
514 COSTS_N_INSNS (4), /* mulsi_const */
515 COSTS_N_INSNS (4), /* mulsi_const9 */
516 COSTS_N_INSNS (4), /* muldi */
517 COSTS_N_INSNS (20), /* divsi */
518 COSTS_N_INSNS (20), /* divdi */
519 COSTS_N_INSNS (3), /* fp */
520 COSTS_N_INSNS (3), /* dmul */
521 COSTS_N_INSNS (18), /* sdiv */
522 COSTS_N_INSNS (32), /* ddiv */
523 32, /* cache line size */
529 /* Instruction costs on PPC604e processors. */
531 struct processor_costs ppc604e_cost
= {
532 COSTS_N_INSNS (2), /* mulsi */
533 COSTS_N_INSNS (2), /* mulsi_const */
534 COSTS_N_INSNS (2), /* mulsi_const9 */
535 COSTS_N_INSNS (2), /* muldi */
536 COSTS_N_INSNS (20), /* divsi */
537 COSTS_N_INSNS (20), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (18), /* sdiv */
541 COSTS_N_INSNS (32), /* ddiv */
542 32, /* cache line size */
548 /* Instruction costs on PPC620 processors. */
550 struct processor_costs ppc620_cost
= {
551 COSTS_N_INSNS (5), /* mulsi */
552 COSTS_N_INSNS (4), /* mulsi_const */
553 COSTS_N_INSNS (3), /* mulsi_const9 */
554 COSTS_N_INSNS (7), /* muldi */
555 COSTS_N_INSNS (21), /* divsi */
556 COSTS_N_INSNS (37), /* divdi */
557 COSTS_N_INSNS (3), /* fp */
558 COSTS_N_INSNS (3), /* dmul */
559 COSTS_N_INSNS (18), /* sdiv */
560 COSTS_N_INSNS (32), /* ddiv */
561 128, /* cache line size */
567 /* Instruction costs on PPC630 processors. */
569 struct processor_costs ppc630_cost
= {
570 COSTS_N_INSNS (5), /* mulsi */
571 COSTS_N_INSNS (4), /* mulsi_const */
572 COSTS_N_INSNS (3), /* mulsi_const9 */
573 COSTS_N_INSNS (7), /* muldi */
574 COSTS_N_INSNS (21), /* divsi */
575 COSTS_N_INSNS (37), /* divdi */
576 COSTS_N_INSNS (3), /* fp */
577 COSTS_N_INSNS (3), /* dmul */
578 COSTS_N_INSNS (17), /* sdiv */
579 COSTS_N_INSNS (21), /* ddiv */
580 128, /* cache line size */
586 /* Instruction costs on Cell processor. */
587 /* COSTS_N_INSNS (1) ~ one add. */
589 struct processor_costs ppccell_cost
= {
590 COSTS_N_INSNS (9/2)+2, /* mulsi */
591 COSTS_N_INSNS (6/2), /* mulsi_const */
592 COSTS_N_INSNS (6/2), /* mulsi_const9 */
593 COSTS_N_INSNS (15/2)+2, /* muldi */
594 COSTS_N_INSNS (38/2), /* divsi */
595 COSTS_N_INSNS (70/2), /* divdi */
596 COSTS_N_INSNS (10/2), /* fp */
597 COSTS_N_INSNS (10/2), /* dmul */
598 COSTS_N_INSNS (74/2), /* sdiv */
599 COSTS_N_INSNS (74/2), /* ddiv */
600 128, /* cache line size */
606 /* Instruction costs on PPC750 and PPC7400 processors. */
608 struct processor_costs ppc750_cost
= {
609 COSTS_N_INSNS (5), /* mulsi */
610 COSTS_N_INSNS (3), /* mulsi_const */
611 COSTS_N_INSNS (2), /* mulsi_const9 */
612 COSTS_N_INSNS (5), /* muldi */
613 COSTS_N_INSNS (17), /* divsi */
614 COSTS_N_INSNS (17), /* divdi */
615 COSTS_N_INSNS (3), /* fp */
616 COSTS_N_INSNS (3), /* dmul */
617 COSTS_N_INSNS (17), /* sdiv */
618 COSTS_N_INSNS (31), /* ddiv */
619 32, /* cache line size */
625 /* Instruction costs on PPC7450 processors. */
627 struct processor_costs ppc7450_cost
= {
628 COSTS_N_INSNS (4), /* mulsi */
629 COSTS_N_INSNS (3), /* mulsi_const */
630 COSTS_N_INSNS (3), /* mulsi_const9 */
631 COSTS_N_INSNS (4), /* muldi */
632 COSTS_N_INSNS (23), /* divsi */
633 COSTS_N_INSNS (23), /* divdi */
634 COSTS_N_INSNS (5), /* fp */
635 COSTS_N_INSNS (5), /* dmul */
636 COSTS_N_INSNS (21), /* sdiv */
637 COSTS_N_INSNS (35), /* ddiv */
638 32, /* cache line size */
644 /* Instruction costs on PPC8540 processors. */
646 struct processor_costs ppc8540_cost
= {
647 COSTS_N_INSNS (4), /* mulsi */
648 COSTS_N_INSNS (4), /* mulsi_const */
649 COSTS_N_INSNS (4), /* mulsi_const9 */
650 COSTS_N_INSNS (4), /* muldi */
651 COSTS_N_INSNS (19), /* divsi */
652 COSTS_N_INSNS (19), /* divdi */
653 COSTS_N_INSNS (4), /* fp */
654 COSTS_N_INSNS (4), /* dmul */
655 COSTS_N_INSNS (29), /* sdiv */
656 COSTS_N_INSNS (29), /* ddiv */
657 32, /* cache line size */
660 1, /* prefetch streams /*/
663 /* Instruction costs on E300C2 and E300C3 cores. */
665 struct processor_costs ppce300c2c3_cost
= {
666 COSTS_N_INSNS (4), /* mulsi */
667 COSTS_N_INSNS (4), /* mulsi_const */
668 COSTS_N_INSNS (4), /* mulsi_const9 */
669 COSTS_N_INSNS (4), /* muldi */
670 COSTS_N_INSNS (19), /* divsi */
671 COSTS_N_INSNS (19), /* divdi */
672 COSTS_N_INSNS (3), /* fp */
673 COSTS_N_INSNS (4), /* dmul */
674 COSTS_N_INSNS (18), /* sdiv */
675 COSTS_N_INSNS (33), /* ddiv */
679 1, /* prefetch streams /*/
682 /* Instruction costs on PPCE500MC processors. */
684 struct processor_costs ppce500mc_cost
= {
685 COSTS_N_INSNS (4), /* mulsi */
686 COSTS_N_INSNS (4), /* mulsi_const */
687 COSTS_N_INSNS (4), /* mulsi_const9 */
688 COSTS_N_INSNS (4), /* muldi */
689 COSTS_N_INSNS (14), /* divsi */
690 COSTS_N_INSNS (14), /* divdi */
691 COSTS_N_INSNS (8), /* fp */
692 COSTS_N_INSNS (10), /* dmul */
693 COSTS_N_INSNS (36), /* sdiv */
694 COSTS_N_INSNS (66), /* ddiv */
695 64, /* cache line size */
698 1, /* prefetch streams /*/
701 /* Instruction costs on PPCE500MC64 processors. */
703 struct processor_costs ppce500mc64_cost
= {
704 COSTS_N_INSNS (4), /* mulsi */
705 COSTS_N_INSNS (4), /* mulsi_const */
706 COSTS_N_INSNS (4), /* mulsi_const9 */
707 COSTS_N_INSNS (4), /* muldi */
708 COSTS_N_INSNS (14), /* divsi */
709 COSTS_N_INSNS (14), /* divdi */
710 COSTS_N_INSNS (4), /* fp */
711 COSTS_N_INSNS (10), /* dmul */
712 COSTS_N_INSNS (36), /* sdiv */
713 COSTS_N_INSNS (66), /* ddiv */
714 64, /* cache line size */
717 1, /* prefetch streams /*/
720 /* Instruction costs on PPCE5500 processors. */
722 struct processor_costs ppce5500_cost
= {
723 COSTS_N_INSNS (5), /* mulsi */
724 COSTS_N_INSNS (5), /* mulsi_const */
725 COSTS_N_INSNS (4), /* mulsi_const9 */
726 COSTS_N_INSNS (5), /* muldi */
727 COSTS_N_INSNS (14), /* divsi */
728 COSTS_N_INSNS (14), /* divdi */
729 COSTS_N_INSNS (7), /* fp */
730 COSTS_N_INSNS (10), /* dmul */
731 COSTS_N_INSNS (36), /* sdiv */
732 COSTS_N_INSNS (66), /* ddiv */
733 64, /* cache line size */
736 1, /* prefetch streams /*/
739 /* Instruction costs on PPCE6500 processors. */
741 struct processor_costs ppce6500_cost
= {
742 COSTS_N_INSNS (5), /* mulsi */
743 COSTS_N_INSNS (5), /* mulsi_const */
744 COSTS_N_INSNS (4), /* mulsi_const9 */
745 COSTS_N_INSNS (5), /* muldi */
746 COSTS_N_INSNS (14), /* divsi */
747 COSTS_N_INSNS (14), /* divdi */
748 COSTS_N_INSNS (7), /* fp */
749 COSTS_N_INSNS (10), /* dmul */
750 COSTS_N_INSNS (36), /* sdiv */
751 COSTS_N_INSNS (66), /* ddiv */
752 64, /* cache line size */
755 1, /* prefetch streams /*/
758 /* Instruction costs on AppliedMicro Titan processors. */
760 struct processor_costs titan_cost
= {
761 COSTS_N_INSNS (5), /* mulsi */
762 COSTS_N_INSNS (5), /* mulsi_const */
763 COSTS_N_INSNS (5), /* mulsi_const9 */
764 COSTS_N_INSNS (5), /* muldi */
765 COSTS_N_INSNS (18), /* divsi */
766 COSTS_N_INSNS (18), /* divdi */
767 COSTS_N_INSNS (10), /* fp */
768 COSTS_N_INSNS (10), /* dmul */
769 COSTS_N_INSNS (46), /* sdiv */
770 COSTS_N_INSNS (72), /* ddiv */
771 32, /* cache line size */
774 1, /* prefetch streams /*/
777 /* Instruction costs on POWER4 and POWER5 processors. */
779 struct processor_costs power4_cost
= {
780 COSTS_N_INSNS (3), /* mulsi */
781 COSTS_N_INSNS (2), /* mulsi_const */
782 COSTS_N_INSNS (2), /* mulsi_const9 */
783 COSTS_N_INSNS (4), /* muldi */
784 COSTS_N_INSNS (18), /* divsi */
785 COSTS_N_INSNS (34), /* divdi */
786 COSTS_N_INSNS (3), /* fp */
787 COSTS_N_INSNS (3), /* dmul */
788 COSTS_N_INSNS (17), /* sdiv */
789 COSTS_N_INSNS (17), /* ddiv */
790 128, /* cache line size */
793 8, /* prefetch streams /*/
796 /* Instruction costs on POWER6 processors. */
798 struct processor_costs power6_cost
= {
799 COSTS_N_INSNS (8), /* mulsi */
800 COSTS_N_INSNS (8), /* mulsi_const */
801 COSTS_N_INSNS (8), /* mulsi_const9 */
802 COSTS_N_INSNS (8), /* muldi */
803 COSTS_N_INSNS (22), /* divsi */
804 COSTS_N_INSNS (28), /* divdi */
805 COSTS_N_INSNS (3), /* fp */
806 COSTS_N_INSNS (3), /* dmul */
807 COSTS_N_INSNS (13), /* sdiv */
808 COSTS_N_INSNS (16), /* ddiv */
809 128, /* cache line size */
812 16, /* prefetch streams */
815 /* Instruction costs on POWER7 processors. */
817 struct processor_costs power7_cost
= {
818 COSTS_N_INSNS (2), /* mulsi */
819 COSTS_N_INSNS (2), /* mulsi_const */
820 COSTS_N_INSNS (2), /* mulsi_const9 */
821 COSTS_N_INSNS (2), /* muldi */
822 COSTS_N_INSNS (18), /* divsi */
823 COSTS_N_INSNS (34), /* divdi */
824 COSTS_N_INSNS (3), /* fp */
825 COSTS_N_INSNS (3), /* dmul */
826 COSTS_N_INSNS (13), /* sdiv */
827 COSTS_N_INSNS (16), /* ddiv */
828 128, /* cache line size */
831 12, /* prefetch streams */
834 /* Instruction costs on POWER A2 processors. */
836 struct processor_costs ppca2_cost
= {
837 COSTS_N_INSNS (16), /* mulsi */
838 COSTS_N_INSNS (16), /* mulsi_const */
839 COSTS_N_INSNS (16), /* mulsi_const9 */
840 COSTS_N_INSNS (16), /* muldi */
841 COSTS_N_INSNS (22), /* divsi */
842 COSTS_N_INSNS (28), /* divdi */
843 COSTS_N_INSNS (3), /* fp */
844 COSTS_N_INSNS (3), /* dmul */
845 COSTS_N_INSNS (59), /* sdiv */
846 COSTS_N_INSNS (72), /* ddiv */
850 16, /* prefetch streams */
854 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
855 #undef RS6000_BUILTIN_1
856 #undef RS6000_BUILTIN_2
857 #undef RS6000_BUILTIN_3
858 #undef RS6000_BUILTIN_A
859 #undef RS6000_BUILTIN_D
860 #undef RS6000_BUILTIN_E
861 #undef RS6000_BUILTIN_P
862 #undef RS6000_BUILTIN_Q
863 #undef RS6000_BUILTIN_S
864 #undef RS6000_BUILTIN_X
866 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
867 { NAME, ICODE, MASK, ATTR },
869 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
870 { NAME, ICODE, MASK, ATTR },
872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
873 { NAME, ICODE, MASK, ATTR },
875 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
876 { NAME, ICODE, MASK, ATTR },
878 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
879 { NAME, ICODE, MASK, ATTR },
881 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
882 { NAME, ICODE, MASK, ATTR },
884 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
885 { NAME, ICODE, MASK, ATTR },
887 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
888 { NAME, ICODE, MASK, ATTR },
890 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
891 { NAME, ICODE, MASK, ATTR },
893 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
894 { NAME, ICODE, MASK, ATTR },
896 struct rs6000_builtin_info_type
{
898 const enum insn_code icode
;
899 const HOST_WIDE_INT mask
;
903 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
905 #include "rs6000-builtin.def"
908 #undef RS6000_BUILTIN_1
909 #undef RS6000_BUILTIN_2
910 #undef RS6000_BUILTIN_3
911 #undef RS6000_BUILTIN_A
912 #undef RS6000_BUILTIN_D
913 #undef RS6000_BUILTIN_E
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
919 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
920 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
923 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
924 static bool spe_func_has_64bit_regs_p (void);
925 static struct machine_function
* rs6000_init_machine_status (void);
926 static int rs6000_ra_ever_killed (void);
927 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
928 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
929 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
930 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
931 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
932 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
933 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
934 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
936 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
937 static bool is_microcoded_insn (rtx
);
938 static bool is_nonpipeline_insn (rtx
);
939 static bool is_cracked_insn (rtx
);
940 static bool is_load_insn (rtx
, rtx
*);
941 static bool is_store_insn (rtx
, rtx
*);
942 static bool set_to_load_agen (rtx
,rtx
);
943 static bool insn_terminates_group_p (rtx
, enum group_termination
);
944 static bool insn_must_be_first_in_group (rtx
);
945 static bool insn_must_be_last_in_group (rtx
);
946 static void altivec_init_builtins (void);
947 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
948 enum machine_mode
, enum machine_mode
,
949 enum rs6000_builtins
, const char *name
);
950 static void rs6000_common_init_builtins (void);
951 static void paired_init_builtins (void);
952 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
953 static void spe_init_builtins (void);
954 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
955 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
956 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
957 static rs6000_stack_t
*rs6000_stack_info (void);
958 static void is_altivec_return_reg (rtx
, void *);
959 int easy_vector_constant (rtx
, enum machine_mode
);
960 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
961 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
962 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
963 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
964 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
967 static void macho_branch_islands (void);
969 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
971 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
973 static bool rs6000_mode_dependent_address (const_rtx
);
974 static bool rs6000_debug_mode_dependent_address (const_rtx
);
975 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
976 enum machine_mode
, rtx
);
977 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
980 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
981 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
983 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
985 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
988 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
991 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
994 static bool rs6000_save_toc_in_prologue_p (void);
996 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
998 = rs6000_legitimize_reload_address
;
1000 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1001 = rs6000_mode_dependent_address
;
1003 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1004 enum machine_mode
, rtx
)
1005 = rs6000_secondary_reload_class
;
1007 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1008 = rs6000_preferred_reload_class
;
1010 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1012 = rs6000_secondary_memory_needed
;
1014 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1017 = rs6000_cannot_change_mode_class
;
1019 const int INSN_NOT_AVAILABLE
= -1;
1021 static void rs6000_print_isa_options (FILE *, int, const char *,
1023 static void rs6000_print_builtin_options (FILE *, int, const char *,
1026 /* Hash table stuff for keeping track of TOC entries. */
1028 struct GTY(()) toc_hash_struct
1030 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1031 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1033 enum machine_mode key_mode
;
1037 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1039 /* Hash table to keep track of the argument types for builtin functions. */
1041 struct GTY(()) builtin_hash_struct
1044 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1045 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1048 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1051 /* Default register names. */
1052 char rs6000_reg_names
[][8] =
1054 "0", "1", "2", "3", "4", "5", "6", "7",
1055 "8", "9", "10", "11", "12", "13", "14", "15",
1056 "16", "17", "18", "19", "20", "21", "22", "23",
1057 "24", "25", "26", "27", "28", "29", "30", "31",
1058 "0", "1", "2", "3", "4", "5", "6", "7",
1059 "8", "9", "10", "11", "12", "13", "14", "15",
1060 "16", "17", "18", "19", "20", "21", "22", "23",
1061 "24", "25", "26", "27", "28", "29", "30", "31",
1062 "mq", "lr", "ctr","ap",
1063 "0", "1", "2", "3", "4", "5", "6", "7",
1065 /* AltiVec registers. */
1066 "0", "1", "2", "3", "4", "5", "6", "7",
1067 "8", "9", "10", "11", "12", "13", "14", "15",
1068 "16", "17", "18", "19", "20", "21", "22", "23",
1069 "24", "25", "26", "27", "28", "29", "30", "31",
1071 /* SPE registers. */
1072 "spe_acc", "spefscr",
1073 /* Soft frame pointer. */
1077 #ifdef TARGET_REGNAMES
1078 static const char alt_reg_names
[][8] =
1080 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1081 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1082 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1083 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1084 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1085 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1086 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1087 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1088 "mq", "lr", "ctr", "ap",
1089 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1091 /* AltiVec registers. */
1092 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1093 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1094 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1095 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1097 /* SPE registers. */
1098 "spe_acc", "spefscr",
1099 /* Soft frame pointer. */
1104 /* Table of valid machine attributes. */
1106 static const struct attribute_spec rs6000_attribute_table
[] =
1108 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1109 affects_type_identity } */
1110 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1112 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1114 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1116 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1118 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1120 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1121 SUBTARGET_ATTRIBUTE_TABLE
,
1123 { NULL
, 0, 0, false, false, false, NULL
, false }
1126 #ifndef TARGET_PROFILE_KERNEL
1127 #define TARGET_PROFILE_KERNEL 0
1130 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1131 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1133 /* Initialize the GCC target structure. */
1134 #undef TARGET_ATTRIBUTE_TABLE
1135 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1136 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1137 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1138 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1139 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1141 #undef TARGET_ASM_ALIGNED_DI_OP
1142 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1144 /* Default unaligned ops are only provided for ELF. Find the ops needed
1145 for non-ELF systems. */
1146 #ifndef OBJECT_FORMAT_ELF
1148 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1150 #undef TARGET_ASM_UNALIGNED_HI_OP
1151 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1152 #undef TARGET_ASM_UNALIGNED_SI_OP
1153 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1154 #undef TARGET_ASM_UNALIGNED_DI_OP
1155 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1158 #undef TARGET_ASM_UNALIGNED_HI_OP
1159 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1160 #undef TARGET_ASM_UNALIGNED_SI_OP
1161 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1162 #undef TARGET_ASM_UNALIGNED_DI_OP
1163 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1164 #undef TARGET_ASM_ALIGNED_DI_OP
1165 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1169 /* This hook deals with fixups for relocatable code and DI-mode objects
1171 #undef TARGET_ASM_INTEGER
1172 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1174 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1175 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1176 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1179 #undef TARGET_SET_UP_BY_PROLOGUE
1180 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1182 #undef TARGET_HAVE_TLS
1183 #define TARGET_HAVE_TLS HAVE_AS_TLS
1185 #undef TARGET_CANNOT_FORCE_CONST_MEM
1186 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1188 #undef TARGET_DELEGITIMIZE_ADDRESS
1189 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1191 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1192 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1194 #undef TARGET_ASM_FUNCTION_PROLOGUE
1195 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1196 #undef TARGET_ASM_FUNCTION_EPILOGUE
1197 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1199 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1200 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1202 #undef TARGET_LEGITIMIZE_ADDRESS
1203 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1205 #undef TARGET_SCHED_VARIABLE_ISSUE
1206 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1208 #undef TARGET_SCHED_ISSUE_RATE
1209 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1210 #undef TARGET_SCHED_ADJUST_COST
1211 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1212 #undef TARGET_SCHED_ADJUST_PRIORITY
1213 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1214 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1215 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1216 #undef TARGET_SCHED_INIT
1217 #define TARGET_SCHED_INIT rs6000_sched_init
1218 #undef TARGET_SCHED_FINISH
1219 #define TARGET_SCHED_FINISH rs6000_sched_finish
1220 #undef TARGET_SCHED_REORDER
1221 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1222 #undef TARGET_SCHED_REORDER2
1223 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1225 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1226 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1228 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1229 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1231 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1232 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1233 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1234 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1235 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1236 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1237 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1238 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1240 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1241 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1242 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1243 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1244 rs6000_builtin_support_vector_misalignment
1245 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1246 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1247 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1248 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1249 rs6000_builtin_vectorization_cost
1250 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1251 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1252 rs6000_preferred_simd_mode
1253 #undef TARGET_VECTORIZE_INIT_COST
1254 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1255 #undef TARGET_VECTORIZE_ADD_STMT_COST
1256 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1257 #undef TARGET_VECTORIZE_FINISH_COST
1258 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1259 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1260 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1262 #undef TARGET_INIT_BUILTINS
1263 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1264 #undef TARGET_BUILTIN_DECL
1265 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1267 #undef TARGET_EXPAND_BUILTIN
1268 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1270 #undef TARGET_MANGLE_TYPE
1271 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1273 #undef TARGET_INIT_LIBFUNCS
1274 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1277 #undef TARGET_BINDS_LOCAL_P
1278 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1281 #undef TARGET_MS_BITFIELD_LAYOUT_P
1282 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1284 #undef TARGET_ASM_OUTPUT_MI_THUNK
1285 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1287 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1288 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1290 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1291 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1293 #undef TARGET_INVALID_WITHIN_DOLOOP
1294 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1296 #undef TARGET_REGISTER_MOVE_COST
1297 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1298 #undef TARGET_MEMORY_MOVE_COST
1299 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1300 #undef TARGET_RTX_COSTS
1301 #define TARGET_RTX_COSTS rs6000_rtx_costs
1302 #undef TARGET_ADDRESS_COST
1303 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1305 #undef TARGET_DWARF_REGISTER_SPAN
1306 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1308 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1309 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1311 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1312 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1314 /* On rs6000, function arguments are promoted, as are function return
1316 #undef TARGET_PROMOTE_FUNCTION_MODE
1317 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1319 #undef TARGET_RETURN_IN_MEMORY
1320 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1322 #undef TARGET_SETUP_INCOMING_VARARGS
1323 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1325 /* Always strict argument naming on rs6000. */
1326 #undef TARGET_STRICT_ARGUMENT_NAMING
1327 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1328 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1329 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1330 #undef TARGET_SPLIT_COMPLEX_ARG
1331 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1332 #undef TARGET_MUST_PASS_IN_STACK
1333 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1334 #undef TARGET_PASS_BY_REFERENCE
1335 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1336 #undef TARGET_ARG_PARTIAL_BYTES
1337 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1338 #undef TARGET_FUNCTION_ARG_ADVANCE
1339 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1340 #undef TARGET_FUNCTION_ARG
1341 #define TARGET_FUNCTION_ARG rs6000_function_arg
1342 #undef TARGET_FUNCTION_ARG_BOUNDARY
1343 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1345 #undef TARGET_BUILD_BUILTIN_VA_LIST
1346 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1348 #undef TARGET_EXPAND_BUILTIN_VA_START
1349 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1351 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1352 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1354 #undef TARGET_EH_RETURN_FILTER_MODE
1355 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1357 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1358 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1360 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1361 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1363 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1364 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1366 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1367 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1369 #undef TARGET_OPTION_OVERRIDE
1370 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1372 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1373 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1374 rs6000_builtin_vectorized_function
1377 #undef TARGET_STACK_PROTECT_FAIL
1378 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1381 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1382 The PowerPC architecture requires only weak consistency among
1383 processors--that is, memory accesses between processors need not be
1384 sequentially consistent and memory accesses among processors can occur
1385 in any order. The ability to order memory accesses weakly provides
1386 opportunities for more efficient use of the system bus. Unless a
1387 dependency exists, the 604e allows read operations to precede store
1389 #undef TARGET_RELAXED_ORDERING
1390 #define TARGET_RELAXED_ORDERING true
1393 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1394 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1397 /* Use a 32-bit anchor range. This leads to sequences like:
1399 addis tmp,anchor,high
1402 where tmp itself acts as an anchor, and can be shared between
1403 accesses to the same 64k page. */
1404 #undef TARGET_MIN_ANCHOR_OFFSET
1405 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1406 #undef TARGET_MAX_ANCHOR_OFFSET
1407 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1408 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1409 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1410 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1411 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1413 #undef TARGET_BUILTIN_RECIPROCAL
1414 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1416 #undef TARGET_EXPAND_TO_RTL_HOOK
1417 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1419 #undef TARGET_INSTANTIATE_DECLS
1420 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1422 #undef TARGET_SECONDARY_RELOAD
1423 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1425 #undef TARGET_LEGITIMATE_ADDRESS_P
1426 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1428 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1429 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1431 #undef TARGET_CAN_ELIMINATE
1432 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1434 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1435 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1437 #undef TARGET_TRAMPOLINE_INIT
1438 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1440 #undef TARGET_FUNCTION_VALUE
1441 #define TARGET_FUNCTION_VALUE rs6000_function_value
1443 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1444 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1446 #undef TARGET_OPTION_SAVE
1447 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1449 #undef TARGET_OPTION_RESTORE
1450 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1452 #undef TARGET_OPTION_PRINT
1453 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1455 #undef TARGET_CAN_INLINE_P
1456 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1458 #undef TARGET_SET_CURRENT_FUNCTION
1459 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1461 #undef TARGET_LEGITIMATE_CONSTANT_P
1462 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1464 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1465 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1468 /* Processor table. */
1471 const char *const name
; /* Canonical processor name. */
1472 const enum processor_type processor
; /* Processor type enum value. */
1473 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1476 static struct rs6000_ptt
const processor_target_table
[] =
1478 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1479 #include "rs6000-cpus.def"
1483 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1487 rs6000_cpu_name_lookup (const char *name
)
1493 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1494 if (! strcmp (name
, processor_target_table
[i
].name
))
1502 /* Return number of consecutive hard regs needed starting at reg REGNO
1503 to hold something of mode MODE.
1504 This is ordinarily the length in words of a value of mode MODE
1505 but can be less for certain modes in special long registers.
1507 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1508 scalar instructions. The upper 32 bits are only available to the
1511 POWER and PowerPC GPRs hold 32 bits worth;
1512 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1515 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1517 unsigned HOST_WIDE_INT reg_size
;
1519 if (FP_REGNO_P (regno
))
1520 reg_size
= (VECTOR_MEM_VSX_P (mode
)
1521 ? UNITS_PER_VSX_WORD
1522 : UNITS_PER_FP_WORD
);
1524 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1525 reg_size
= UNITS_PER_SPE_WORD
;
1527 else if (ALTIVEC_REGNO_P (regno
))
1528 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1530 /* The value returned for SCmode in the E500 double case is 2 for
1531 ABI compatibility; storing an SCmode value in a single register
1532 would require function_arg and rs6000_spe_function_arg to handle
1533 SCmode so as to pass the value correctly in a pair of
1535 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1536 && !DECIMAL_FLOAT_MODE_P (mode
))
1537 reg_size
= UNITS_PER_FP_WORD
;
1540 reg_size
= UNITS_PER_WORD
;
1542 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1545 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1548 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1550 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1552 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1553 implementations. Don't allow an item to be split between a FP register
1554 and an Altivec register. */
1555 if (VECTOR_MEM_VSX_P (mode
))
1557 if (FP_REGNO_P (regno
))
1558 return FP_REGNO_P (last_regno
);
1560 if (ALTIVEC_REGNO_P (regno
))
1561 return ALTIVEC_REGNO_P (last_regno
);
1564 /* The GPRs can hold any mode, but values bigger than one register
1565 cannot go past R31. */
1566 if (INT_REGNO_P (regno
))
1567 return INT_REGNO_P (last_regno
);
1569 /* The float registers (except for VSX vector modes) can only hold floating
1570 modes and DImode. This excludes the 32-bit decimal float mode for
1572 if (FP_REGNO_P (regno
))
1574 if (SCALAR_FLOAT_MODE_P (mode
)
1575 && (mode
!= TDmode
|| (regno
% 2) == 0)
1576 && FP_REGNO_P (last_regno
))
1579 if (GET_MODE_CLASS (mode
) == MODE_INT
1580 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1583 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1584 && PAIRED_VECTOR_MODE (mode
))
1590 /* The CR register can only hold CC modes. */
1591 if (CR_REGNO_P (regno
))
1592 return GET_MODE_CLASS (mode
) == MODE_CC
;
1594 if (CA_REGNO_P (regno
))
1595 return mode
== BImode
;
1597 /* AltiVec only in AldyVec registers. */
1598 if (ALTIVEC_REGNO_P (regno
))
1599 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1601 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1602 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1605 /* We cannot put TImode anywhere except general register and it must be able
1606 to fit within the register set. In the future, allow TImode in the
1607 Altivec or VSX registers. */
1609 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1612 /* Print interesting facts about registers. */
1614 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1618 for (r
= first_regno
; r
<= last_regno
; ++r
)
1620 const char *comma
= "";
1623 if (first_regno
== last_regno
)
1624 fprintf (stderr
, "%s:\t", reg_name
);
1626 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1629 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1630 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1634 fprintf (stderr
, ",\n\t");
1639 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1640 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1641 rs6000_hard_regno_nregs
[m
][r
]);
1643 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1648 if (call_used_regs
[r
])
1652 fprintf (stderr
, ",\n\t");
1657 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1665 fprintf (stderr
, ",\n\t");
1670 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1676 fprintf (stderr
, ",\n\t");
1680 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1684 #define DEBUG_FMT_ID "%-32s= "
1685 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1686 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1687 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1689 /* Print various interesting information with -mdebug=reg. */
1691 rs6000_debug_reg_global (void)
1693 static const char *const tf
[2] = { "false", "true" };
1694 const char *nl
= (const char *)0;
1696 char costly_num
[20];
1698 char flags_buffer
[40];
1699 const char *costly_str
;
1700 const char *nop_str
;
1701 const char *trace_str
;
1702 const char *abi_str
;
1703 const char *cmodel_str
;
1704 struct cl_target_option cl_opts
;
1706 /* Map enum rs6000_vector to string. */
1707 static const char *rs6000_debug_vector_unit
[] = {
1716 fprintf (stderr
, "Register information: (last virtual reg = %d)\n",
1717 LAST_VIRTUAL_REGISTER
);
1718 rs6000_debug_reg_print (0, 31, "gr");
1719 rs6000_debug_reg_print (32, 63, "fp");
1720 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
1723 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
1724 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
1725 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
1726 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
1727 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
1728 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
1729 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
1730 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
1734 "d reg_class = %s\n"
1735 "f reg_class = %s\n"
1736 "v reg_class = %s\n"
1737 "wa reg_class = %s\n"
1738 "wd reg_class = %s\n"
1739 "wf reg_class = %s\n"
1740 "ws reg_class = %s\n\n",
1741 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
1742 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
1743 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
1744 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
1745 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
1746 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
1747 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]]);
1749 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1750 if (rs6000_vector_unit
[m
] || rs6000_vector_mem
[m
])
1753 fprintf (stderr
, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1755 rs6000_debug_vector_unit
[ rs6000_vector_unit
[m
] ],
1756 rs6000_debug_vector_unit
[ rs6000_vector_mem
[m
] ]);
1762 if (rs6000_recip_control
)
1764 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
1766 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1767 if (rs6000_recip_bits
[m
])
1770 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1772 (RS6000_RECIP_AUTO_RE_P (m
)
1774 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
1775 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
1777 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
1780 fputs ("\n", stderr
);
1783 if (rs6000_cpu_index
>= 0)
1785 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
1787 = processor_target_table
[rs6000_cpu_index
].target_enable
;
1789 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
1790 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1793 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
1795 if (rs6000_tune_index
>= 0)
1797 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
1799 = processor_target_table
[rs6000_tune_index
].target_enable
;
1801 sprintf (flags_buffer
, "-mtune=%s flags", name
);
1802 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1805 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
1807 cl_target_option_save (&cl_opts
, &global_options
);
1808 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
1811 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
1812 rs6000_isa_flags_explicit
);
1814 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
1815 rs6000_builtin_mask
);
1817 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
1819 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
1820 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
1822 switch (rs6000_sched_costly_dep
)
1824 case max_dep_latency
:
1825 costly_str
= "max_dep_latency";
1829 costly_str
= "no_dep_costly";
1832 case all_deps_costly
:
1833 costly_str
= "all_deps_costly";
1836 case true_store_to_load_dep_costly
:
1837 costly_str
= "true_store_to_load_dep_costly";
1840 case store_to_load_dep_costly
:
1841 costly_str
= "store_to_load_dep_costly";
1845 costly_str
= costly_num
;
1846 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
1850 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
1852 switch (rs6000_sched_insert_nops
)
1854 case sched_finish_regroup_exact
:
1855 nop_str
= "sched_finish_regroup_exact";
1858 case sched_finish_pad_groups
:
1859 nop_str
= "sched_finish_pad_groups";
1862 case sched_finish_none
:
1863 nop_str
= "sched_finish_none";
1868 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
1872 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
1874 switch (rs6000_sdata
)
1881 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
1885 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
1889 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
1894 switch (rs6000_traceback
)
1896 case traceback_default
: trace_str
= "default"; break;
1897 case traceback_none
: trace_str
= "none"; break;
1898 case traceback_part
: trace_str
= "part"; break;
1899 case traceback_full
: trace_str
= "full"; break;
1900 default: trace_str
= "unknown"; break;
1903 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
1905 switch (rs6000_current_cmodel
)
1907 case CMODEL_SMALL
: cmodel_str
= "small"; break;
1908 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
1909 case CMODEL_LARGE
: cmodel_str
= "large"; break;
1910 default: cmodel_str
= "unknown"; break;
1913 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
1915 switch (rs6000_current_abi
)
1917 case ABI_NONE
: abi_str
= "none"; break;
1918 case ABI_AIX
: abi_str
= "aix"; break;
1919 case ABI_V4
: abi_str
= "V4"; break;
1920 case ABI_DARWIN
: abi_str
= "darwin"; break;
1921 default: abi_str
= "unknown"; break;
1924 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
1926 if (rs6000_altivec_abi
)
1927 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
1930 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
1932 if (rs6000_darwin64_abi
)
1933 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
1935 if (rs6000_float_gprs
)
1936 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
1938 if (TARGET_LINK_STACK
)
1939 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
1941 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
1942 TARGET_SECURE_PLT
? "secure" : "bss");
1943 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
1944 aix_struct_return
? "aix" : "sysv");
1945 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
1946 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
1947 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
1948 tf
[!!rs6000_align_branch_targets
]);
1949 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
1950 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
1951 rs6000_long_double_type_size
);
1952 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
1953 (int)rs6000_sched_restricted_insns_priority
);
1954 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
1956 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
1957 (int)RS6000_BUILTIN_COUNT
);
1960 /* Initialize the various global tables that are based on register size. */
1962 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
1968 /* Precalculate REGNO_REG_CLASS. */
1969 rs6000_regno_regclass
[0] = GENERAL_REGS
;
1970 for (r
= 1; r
< 32; ++r
)
1971 rs6000_regno_regclass
[r
] = BASE_REGS
;
1973 for (r
= 32; r
< 64; ++r
)
1974 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
1976 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1977 rs6000_regno_regclass
[r
] = NO_REGS
;
1979 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
1980 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
1982 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
1983 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
1984 rs6000_regno_regclass
[r
] = CR_REGS
;
1986 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
1987 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
1988 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
1989 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
1990 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
1991 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
1992 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
1993 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
1994 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
1996 /* Precalculate vector information, this must be set up before the
1997 rs6000_hard_regno_nregs_internal below. */
1998 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2000 rs6000_vector_unit
[m
] = rs6000_vector_mem
[m
] = VECTOR_NONE
;
2001 rs6000_vector_reload
[m
][0] = CODE_FOR_nothing
;
2002 rs6000_vector_reload
[m
][1] = CODE_FOR_nothing
;
2005 for (c
= 0; c
< (int)(int)RS6000_CONSTRAINT_MAX
; c
++)
2006 rs6000_constraints
[c
] = NO_REGS
;
2008 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2009 believes it can use native alignment or still uses 128-bit alignment. */
2010 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2021 /* V2DF mode, VSX only. */
2024 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2025 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2026 rs6000_vector_align
[V2DFmode
] = align64
;
2029 /* V4SF mode, either VSX or Altivec. */
2032 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2033 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2034 rs6000_vector_align
[V4SFmode
] = align32
;
2036 else if (TARGET_ALTIVEC
)
2038 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2039 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2040 rs6000_vector_align
[V4SFmode
] = align32
;
2043 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2047 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2048 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2049 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2050 rs6000_vector_align
[V4SImode
] = align32
;
2051 rs6000_vector_align
[V8HImode
] = align32
;
2052 rs6000_vector_align
[V16QImode
] = align32
;
2056 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2057 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2058 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2062 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2063 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2064 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2068 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2069 Altivec doesn't have 64-bit support. */
2072 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2073 rs6000_vector_unit
[V2DImode
] = VECTOR_NONE
;
2074 rs6000_vector_align
[V2DImode
] = align64
;
2077 /* DFmode, see if we want to use the VSX unit. */
2078 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2080 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2081 rs6000_vector_mem
[DFmode
]
2082 = (TARGET_VSX_SCALAR_MEMORY
? VECTOR_VSX
: VECTOR_NONE
);
2083 rs6000_vector_align
[DFmode
] = align64
;
2086 /* TODO add SPE and paired floating point vector support. */
2088 /* Register class constraints for the constraints that depend on compile
2090 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2091 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2093 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2094 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2098 /* At present, we just use VSX_REGS, but we have different constraints
2099 based on the use, in case we want to fine tune the default register
2100 class used. wa = any VSX register, wf = register class to use for
2101 V4SF, wd = register class to use for V2DF, and ws = register classs to
2102 use for DF scalars. */
2103 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2104 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2105 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2106 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = (TARGET_VSX_SCALAR_MEMORY
2112 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2114 /* Set up the reload helper functions. */
2115 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2119 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_di_store
;
2120 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_di_load
;
2121 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_di_store
;
2122 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_di_load
;
2123 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_di_store
;
2124 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_di_load
;
2125 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_di_store
;
2126 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_di_load
;
2127 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_di_store
;
2128 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_di_load
;
2129 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_di_store
;
2130 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_di_load
;
2131 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2133 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_di_store
;
2134 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_di_load
;
2139 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_si_store
;
2140 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_si_load
;
2141 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_si_store
;
2142 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_si_load
;
2143 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_si_store
;
2144 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_si_load
;
2145 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_si_store
;
2146 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_si_load
;
2147 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_si_store
;
2148 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_si_load
;
2149 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_si_store
;
2150 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_si_load
;
2151 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2153 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_si_store
;
2154 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_si_load
;
2159 /* Precalculate HARD_REGNO_NREGS. */
2160 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2161 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2162 rs6000_hard_regno_nregs
[m
][r
]
2163 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2165 /* Precalculate HARD_REGNO_MODE_OK. */
2166 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2167 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2168 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2169 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2171 /* Precalculate CLASS_MAX_NREGS sizes. */
2172 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2176 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2177 reg_size
= UNITS_PER_VSX_WORD
;
2179 else if (c
== ALTIVEC_REGS
)
2180 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2182 else if (c
== FLOAT_REGS
)
2183 reg_size
= UNITS_PER_FP_WORD
;
2186 reg_size
= UNITS_PER_WORD
;
2188 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2189 rs6000_class_max_nregs
[m
][c
]
2190 = (GET_MODE_SIZE (m
) + reg_size
- 1) / reg_size
;
2193 if (TARGET_E500_DOUBLE
)
2194 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2196 /* Calculate which modes to automatically generate code to use a the
2197 reciprocal divide and square root instructions. In the future, possibly
2198 automatically generate the instructions even if the user did not specify
2199 -mrecip. The older machines double precision reciprocal sqrt estimate is
2200 not accurate enough. */
2201 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2203 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2205 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2206 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2207 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2208 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2209 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2211 if (TARGET_FRSQRTES
)
2212 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2214 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2215 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2216 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2217 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2218 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2220 if (rs6000_recip_control
)
2222 if (!flag_finite_math_only
)
2223 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2224 if (flag_trapping_math
)
2225 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2226 if (!flag_reciprocal_math
)
2227 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2228 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2230 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2231 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2232 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2234 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2235 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2236 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2238 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2239 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2240 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2242 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2243 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2244 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2246 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2247 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2248 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2250 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2251 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2252 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2254 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2255 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2256 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2258 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2259 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2260 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2264 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2266 if (TARGET_DEBUG_REG
)
2267 rs6000_debug_reg_global ();
2269 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2271 "SImode variable mult cost = %d\n"
2272 "SImode constant mult cost = %d\n"
2273 "SImode short constant mult cost = %d\n"
2274 "DImode multipliciation cost = %d\n"
2275 "SImode division cost = %d\n"
2276 "DImode division cost = %d\n"
2277 "Simple fp operation cost = %d\n"
2278 "DFmode multiplication cost = %d\n"
2279 "SFmode division cost = %d\n"
2280 "DFmode division cost = %d\n"
2281 "cache line size = %d\n"
2282 "l1 cache size = %d\n"
2283 "l2 cache size = %d\n"
2284 "simultaneous prefetches = %d\n"
2287 rs6000_cost
->mulsi_const
,
2288 rs6000_cost
->mulsi_const9
,
2296 rs6000_cost
->cache_line_size
,
2297 rs6000_cost
->l1_cache_size
,
2298 rs6000_cost
->l2_cache_size
,
2299 rs6000_cost
->simultaneous_prefetches
);
2304 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2307 darwin_rs6000_override_options (void)
2309 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2311 rs6000_altivec_abi
= 1;
2312 TARGET_ALTIVEC_VRSAVE
= 1;
2313 rs6000_current_abi
= ABI_DARWIN
;
2315 if (DEFAULT_ABI
== ABI_DARWIN
2317 darwin_one_byte_bool
= 1;
2319 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2321 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2322 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2326 rs6000_default_long_calls
= 1;
2327 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2330 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2332 if (!flag_mkernel
&& !flag_apple_kext
2334 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2335 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2337 /* Unless the user (not the configurer) has explicitly overridden
2338 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2339 G4 unless targeting the kernel. */
2342 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2343 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2344 && ! global_options_set
.x_rs6000_cpu_index
)
2346 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2351 /* If not otherwise specified by a target, make 'long double' equivalent to
2354 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2355 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2358 /* Return the builtin mask of the various options used that could affect which
2359 builtins were used. In the past we used target_flags, but we've run out of
2360 bits, and some options like SPE and PAIRED are no longer in
2364 rs6000_builtin_mask_calculate (void)
2366 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2367 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2368 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2369 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2370 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2371 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2372 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2373 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2374 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2375 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0));
2378 /* Override command line options. Mostly we process the processor type and
2379 sometimes adjust other TARGET_ options. */
2382 rs6000_option_override_internal (bool global_init_p
)
2385 bool have_cpu
= false;
2387 /* The default cpu requested at configure time, if any. */
2388 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
2390 HOST_WIDE_INT set_masks
;
2393 struct cl_target_option
*main_target_opt
2394 = ((global_init_p
|| target_option_default_node
== NULL
)
2395 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
2397 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2398 library functions, so warn about it. The flag may be useful for
2399 performance studies from time to time though, so don't disable it
2401 if (global_options_set
.x_rs6000_alignment_flags
2402 && rs6000_alignment_flags
== MASK_ALIGN_POWER
2403 && DEFAULT_ABI
== ABI_DARWIN
2405 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2406 " it is incompatible with the installed C and C++ libraries");
2408 /* Numerous experiment shows that IRA based loop pressure
2409 calculation works better for RTL loop invariant motion on targets
2410 with enough (>= 32) registers. It is an expensive optimization.
2411 So it is on only for peak performance. */
2412 if (optimize
>= 3 && global_init_p
)
2413 flag_ira_loop_pressure
= 1;
2415 /* Set the pointer size. */
2418 rs6000_pmode
= (int)DImode
;
2419 rs6000_pointer_size
= 64;
2423 rs6000_pmode
= (int)SImode
;
2424 rs6000_pointer_size
= 32;
2427 /* Some OSs don't support saving the high part of 64-bit registers on context
2428 switch. Other OSs don't support saving Altivec registers. On those OSs,
2429 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
2430 if the user wants either, the user must explicitly specify them and we
2431 won't interfere with the user's specification. */
2433 set_masks
= POWERPC_MASKS
;
2434 #ifdef OS_MISSING_POWERPC64
2435 if (OS_MISSING_POWERPC64
)
2436 set_masks
&= ~OPTION_MASK_POWERPC64
;
2438 #ifdef OS_MISSING_ALTIVEC
2439 if (OS_MISSING_ALTIVEC
)
2440 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
2443 /* Don't override by the processor default if given explicitly. */
2444 set_masks
&= ~rs6000_isa_flags_explicit
;
2446 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2447 the cpu in a target attribute or pragma, but did not specify a tuning
2448 option, use the cpu for the tuning option rather than the option specified
2449 with -mtune on the command line. Process a '--with-cpu' configuration
2450 request as an implicit --cpu. */
2451 if (rs6000_cpu_index
>= 0)
2453 cpu_index
= rs6000_cpu_index
;
2456 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
2458 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
2461 else if (implicit_cpu
)
2463 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
2468 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
2469 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
2473 gcc_assert (cpu_index
>= 0);
2475 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
2476 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
2477 with those from the cpu, except for options that were explicitly set. If
2478 we don't have a cpu, do not override the target bits set in
2482 rs6000_isa_flags
&= ~set_masks
;
2483 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2487 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2488 & ~rs6000_isa_flags_explicit
);
2490 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
2491 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
2492 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
2493 to using rs6000_isa_flags, we need to do the initialization here. */
2495 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
2497 if (rs6000_tune_index
>= 0)
2498 tune_index
= rs6000_tune_index
;
2500 rs6000_tune_index
= tune_index
= cpu_index
;
2504 enum processor_type tune_proc
2505 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
2508 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2509 if (processor_target_table
[i
].processor
== tune_proc
)
2511 rs6000_tune_index
= tune_index
= i
;
2516 gcc_assert (tune_index
>= 0);
2517 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
2519 /* Pick defaults for SPE related control flags. Do this early to make sure
2520 that the TARGET_ macros are representative ASAP. */
2522 int spe_capable_cpu
=
2523 (rs6000_cpu
== PROCESSOR_PPC8540
2524 || rs6000_cpu
== PROCESSOR_PPC8548
);
2526 if (!global_options_set
.x_rs6000_spe_abi
)
2527 rs6000_spe_abi
= spe_capable_cpu
;
2529 if (!global_options_set
.x_rs6000_spe
)
2530 rs6000_spe
= spe_capable_cpu
;
2532 if (!global_options_set
.x_rs6000_float_gprs
)
2534 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
2535 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
2539 if (global_options_set
.x_rs6000_spe_abi
2542 error ("not configured for SPE ABI");
2544 if (global_options_set
.x_rs6000_spe
2547 error ("not configured for SPE instruction set");
2549 if (main_target_opt
!= NULL
2550 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
2551 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
2552 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
2553 error ("target attribute or pragma changes SPE ABI");
2555 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
2556 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
2557 || rs6000_cpu
== PROCESSOR_PPCE5500
)
2560 error ("AltiVec not supported in this target");
2562 error ("SPE not supported in this target");
2564 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
2567 error ("SPE not supported in this target");
2570 /* Disable Cell microcode if we are optimizing for the Cell
2571 and not optimizing for size. */
2572 if (rs6000_gen_cell_microcode
== -1)
2573 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
2576 /* If we are optimizing big endian systems for space and it's OK to
2577 use instructions that would be microcoded on the Cell, use the
2578 load/store multiple and string instructions. */
2579 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
2580 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
2581 | OPTION_MASK_STRING
);
2583 /* Don't allow -mmultiple or -mstring on little endian systems
2584 unless the cpu is a 750, because the hardware doesn't support the
2585 instructions used in little endian mode, and causes an alignment
2586 trap. The 750 does not cause an alignment trap (except when the
2587 target is unaligned). */
2589 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
2591 if (TARGET_MULTIPLE
)
2593 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
2594 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
2595 warning (0, "-mmultiple is not supported on little endian systems");
2600 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
2601 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
2602 warning (0, "-mstring is not supported on little endian systems");
2606 /* Add some warnings for VSX. */
2609 const char *msg
= NULL
;
2610 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
2611 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
2613 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2614 msg
= N_("-mvsx requires hardware floating point");
2616 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2618 else if (TARGET_PAIRED_FLOAT
)
2619 msg
= N_("-mvsx and -mpaired are incompatible");
2620 /* The hardware will allow VSX and little endian, but until we make sure
2621 things like vector select, etc. work don't allow VSX on little endian
2622 systems at this point. */
2623 else if (!BYTES_BIG_ENDIAN
)
2624 msg
= N_("-mvsx used with little endian code");
2625 else if (TARGET_AVOID_XFORM
> 0)
2626 msg
= N_("-mvsx needs indexed addressing");
2627 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
2628 & OPTION_MASK_ALTIVEC
))
2630 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2631 msg
= N_("-mvsx and -mno-altivec are incompatible");
2633 msg
= N_("-mno-altivec disables vsx");
2639 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2640 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
2644 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2645 unless the user explicitly used the -mno-<option> to disable the code. */
2647 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
2648 else if (TARGET_POPCNTD
)
2649 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
2650 else if (TARGET_DFP
)
2651 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
2652 else if (TARGET_CMPB
)
2653 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
2654 else if (TARGET_FPRND
)
2655 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
2656 else if (TARGET_POPCNTB
)
2657 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
2658 else if (TARGET_ALTIVEC
)
2659 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
2661 /* E500mc does "better" if we inline more aggressively. Respect the
2662 user's opinion, though. */
2663 if (rs6000_block_move_inline_limit
== 0
2664 && (rs6000_cpu
== PROCESSOR_PPCE500MC
2665 || rs6000_cpu
== PROCESSOR_PPCE500MC64
2666 || rs6000_cpu
== PROCESSOR_PPCE5500
2667 || rs6000_cpu
== PROCESSOR_PPCE6500
))
2668 rs6000_block_move_inline_limit
= 128;
2670 /* store_one_arg depends on expand_block_move to handle at least the
2671 size of reg_parm_stack_space. */
2672 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
2673 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
2677 /* If the appropriate debug option is enabled, replace the target hooks
2678 with debug versions that call the real version and then prints
2679 debugging information. */
2680 if (TARGET_DEBUG_COST
)
2682 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
2683 targetm
.address_cost
= rs6000_debug_address_cost
;
2684 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
2687 if (TARGET_DEBUG_ADDR
)
2689 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
2690 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
2691 rs6000_secondary_reload_class_ptr
2692 = rs6000_debug_secondary_reload_class
;
2693 rs6000_secondary_memory_needed_ptr
2694 = rs6000_debug_secondary_memory_needed
;
2695 rs6000_cannot_change_mode_class_ptr
2696 = rs6000_debug_cannot_change_mode_class
;
2697 rs6000_preferred_reload_class_ptr
2698 = rs6000_debug_preferred_reload_class
;
2699 rs6000_legitimize_reload_address_ptr
2700 = rs6000_debug_legitimize_reload_address
;
2701 rs6000_mode_dependent_address_ptr
2702 = rs6000_debug_mode_dependent_address
;
2705 if (rs6000_veclibabi_name
)
2707 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
2708 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
2711 error ("unknown vectorization library ABI type (%s) for "
2712 "-mveclibabi= switch", rs6000_veclibabi_name
);
2718 if (!global_options_set
.x_rs6000_long_double_type_size
)
2720 if (main_target_opt
!= NULL
2721 && (main_target_opt
->x_rs6000_long_double_type_size
2722 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
2723 error ("target attribute or pragma changes long double size");
2725 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2728 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2729 if (!global_options_set
.x_rs6000_ieeequad
)
2730 rs6000_ieeequad
= 1;
2733 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2734 target attribute or pragma which automatically enables both options,
2735 unless the altivec ABI was set. This is set by default for 64-bit, but
2737 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
2738 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
2739 & ~rs6000_isa_flags_explicit
);
2741 /* Enable Altivec ABI for AIX -maltivec. */
2742 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
2744 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
2745 error ("target attribute or pragma changes AltiVec ABI");
2747 rs6000_altivec_abi
= 1;
2750 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2751 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2752 be explicitly overridden in either case. */
2755 if (!global_options_set
.x_rs6000_altivec_abi
2756 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
2758 if (main_target_opt
!= NULL
&&
2759 !main_target_opt
->x_rs6000_altivec_abi
)
2760 error ("target attribute or pragma changes AltiVec ABI");
2762 rs6000_altivec_abi
= 1;
2766 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2767 So far, the only darwin64 targets are also MACH-O. */
2769 && DEFAULT_ABI
== ABI_DARWIN
2772 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
2773 error ("target attribute or pragma changes darwin64 ABI");
2776 rs6000_darwin64_abi
= 1;
2777 /* Default to natural alignment, for better performance. */
2778 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2782 /* Place FP constants in the constant pool instead of TOC
2783 if section anchors enabled. */
2784 if (flag_section_anchors
)
2785 TARGET_NO_FP_IN_TOC
= 1;
2787 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2788 SUBTARGET_OVERRIDE_OPTIONS
;
2790 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2791 SUBSUBTARGET_OVERRIDE_OPTIONS
;
2793 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2794 SUB3TARGET_OVERRIDE_OPTIONS
;
2797 /* For the E500 family of cores, reset the single/double FP flags to let us
2798 check that they remain constant across attributes or pragmas. Also,
2799 clear a possible request for string instructions, not supported and which
2800 we might have silently queried above for -Os.
2802 For other families, clear ISEL in case it was set implicitly.
2807 case PROCESSOR_PPC8540
:
2808 case PROCESSOR_PPC8548
:
2809 case PROCESSOR_PPCE500MC
:
2810 case PROCESSOR_PPCE500MC64
:
2811 case PROCESSOR_PPCE5500
:
2812 case PROCESSOR_PPCE6500
:
2814 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
2815 rs6000_double_float
= TARGET_E500_DOUBLE
;
2817 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
2823 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
2824 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
2829 if (main_target_opt
)
2831 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
2832 error ("target attribute or pragma changes single precision floating "
2834 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
2835 error ("target attribute or pragma changes double precision floating "
2839 /* Detect invalid option combinations with E500. */
2842 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
2843 && rs6000_cpu
!= PROCESSOR_POWER5
2844 && rs6000_cpu
!= PROCESSOR_POWER6
2845 && rs6000_cpu
!= PROCESSOR_POWER7
2846 && rs6000_cpu
!= PROCESSOR_PPCA2
2847 && rs6000_cpu
!= PROCESSOR_CELL
2848 && rs6000_cpu
!= PROCESSOR_PPC476
);
2849 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
2850 || rs6000_cpu
== PROCESSOR_POWER5
2851 || rs6000_cpu
== PROCESSOR_POWER7
);
2852 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
2853 || rs6000_cpu
== PROCESSOR_POWER5
2854 || rs6000_cpu
== PROCESSOR_POWER6
2855 || rs6000_cpu
== PROCESSOR_POWER7
2856 || rs6000_cpu
== PROCESSOR_PPCE500MC
2857 || rs6000_cpu
== PROCESSOR_PPCE500MC64
2858 || rs6000_cpu
== PROCESSOR_PPCE5500
2859 || rs6000_cpu
== PROCESSOR_PPCE6500
);
2861 /* Allow debug switches to override the above settings. These are set to -1
2862 in rs6000.opt to indicate the user hasn't directly set the switch. */
2863 if (TARGET_ALWAYS_HINT
>= 0)
2864 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
2866 if (TARGET_SCHED_GROUPS
>= 0)
2867 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
2869 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
2870 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
2872 rs6000_sched_restricted_insns_priority
2873 = (rs6000_sched_groups
? 1 : 0);
2875 /* Handle -msched-costly-dep option. */
2876 rs6000_sched_costly_dep
2877 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
2879 if (rs6000_sched_costly_dep_str
)
2881 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
2882 rs6000_sched_costly_dep
= no_dep_costly
;
2883 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
2884 rs6000_sched_costly_dep
= all_deps_costly
;
2885 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
2886 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
2887 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
2888 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
2890 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
2891 atoi (rs6000_sched_costly_dep_str
));
2894 /* Handle -minsert-sched-nops option. */
2895 rs6000_sched_insert_nops
2896 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
2898 if (rs6000_sched_insert_nops_str
)
2900 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
2901 rs6000_sched_insert_nops
= sched_finish_none
;
2902 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
2903 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
2904 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
2905 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
2907 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
2908 atoi (rs6000_sched_insert_nops_str
));
2913 #ifdef TARGET_REGNAMES
2914 /* If the user desires alternate register names, copy in the
2915 alternate names now. */
2916 if (TARGET_REGNAMES
)
2917 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
2920 /* Set aix_struct_return last, after the ABI is determined.
2921 If -maix-struct-return or -msvr4-struct-return was explicitly
2922 used, don't override with the ABI default. */
2923 if (!global_options_set
.x_aix_struct_return
)
2924 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
2927 /* IBM XL compiler defaults to unsigned bitfields. */
2928 if (TARGET_XL_COMPAT
)
2929 flag_signed_bitfields
= 0;
2932 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
2933 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
2936 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
2938 /* We can only guarantee the availability of DI pseudo-ops when
2939 assembling for 64-bit targets. */
2942 targetm
.asm_out
.aligned_op
.di
= NULL
;
2943 targetm
.asm_out
.unaligned_op
.di
= NULL
;
2947 /* Set branch target alignment, if not optimizing for size. */
2950 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
2951 aligned 8byte to avoid misprediction by the branch predictor. */
2952 if (rs6000_cpu
== PROCESSOR_TITAN
2953 || rs6000_cpu
== PROCESSOR_CELL
)
2955 if (align_functions
<= 0)
2956 align_functions
= 8;
2957 if (align_jumps
<= 0)
2959 if (align_loops
<= 0)
2962 if (rs6000_align_branch_targets
)
2964 if (align_functions
<= 0)
2965 align_functions
= 16;
2966 if (align_jumps
<= 0)
2968 if (align_loops
<= 0)
2970 can_override_loop_align
= 1;
2974 if (align_jumps_max_skip
<= 0)
2975 align_jumps_max_skip
= 15;
2976 if (align_loops_max_skip
<= 0)
2977 align_loops_max_skip
= 15;
2980 /* Arrange to save and restore machine status around nested functions. */
2981 init_machine_status
= rs6000_init_machine_status
;
2983 /* We should always be splitting complex arguments, but we can't break
2984 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
2985 if (DEFAULT_ABI
!= ABI_AIX
)
2986 targetm
.calls
.split_complex_arg
= NULL
;
2989 /* Initialize rs6000_cost with the appropriate target costs. */
2991 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
2995 case PROCESSOR_RS64A
:
2996 rs6000_cost
= &rs64a_cost
;
2999 case PROCESSOR_MPCCORE
:
3000 rs6000_cost
= &mpccore_cost
;
3003 case PROCESSOR_PPC403
:
3004 rs6000_cost
= &ppc403_cost
;
3007 case PROCESSOR_PPC405
:
3008 rs6000_cost
= &ppc405_cost
;
3011 case PROCESSOR_PPC440
:
3012 rs6000_cost
= &ppc440_cost
;
3015 case PROCESSOR_PPC476
:
3016 rs6000_cost
= &ppc476_cost
;
3019 case PROCESSOR_PPC601
:
3020 rs6000_cost
= &ppc601_cost
;
3023 case PROCESSOR_PPC603
:
3024 rs6000_cost
= &ppc603_cost
;
3027 case PROCESSOR_PPC604
:
3028 rs6000_cost
= &ppc604_cost
;
3031 case PROCESSOR_PPC604e
:
3032 rs6000_cost
= &ppc604e_cost
;
3035 case PROCESSOR_PPC620
:
3036 rs6000_cost
= &ppc620_cost
;
3039 case PROCESSOR_PPC630
:
3040 rs6000_cost
= &ppc630_cost
;
3043 case PROCESSOR_CELL
:
3044 rs6000_cost
= &ppccell_cost
;
3047 case PROCESSOR_PPC750
:
3048 case PROCESSOR_PPC7400
:
3049 rs6000_cost
= &ppc750_cost
;
3052 case PROCESSOR_PPC7450
:
3053 rs6000_cost
= &ppc7450_cost
;
3056 case PROCESSOR_PPC8540
:
3057 case PROCESSOR_PPC8548
:
3058 rs6000_cost
= &ppc8540_cost
;
3061 case PROCESSOR_PPCE300C2
:
3062 case PROCESSOR_PPCE300C3
:
3063 rs6000_cost
= &ppce300c2c3_cost
;
3066 case PROCESSOR_PPCE500MC
:
3067 rs6000_cost
= &ppce500mc_cost
;
3070 case PROCESSOR_PPCE500MC64
:
3071 rs6000_cost
= &ppce500mc64_cost
;
3074 case PROCESSOR_PPCE5500
:
3075 rs6000_cost
= &ppce5500_cost
;
3078 case PROCESSOR_PPCE6500
:
3079 rs6000_cost
= &ppce6500_cost
;
3082 case PROCESSOR_TITAN
:
3083 rs6000_cost
= &titan_cost
;
3086 case PROCESSOR_POWER4
:
3087 case PROCESSOR_POWER5
:
3088 rs6000_cost
= &power4_cost
;
3091 case PROCESSOR_POWER6
:
3092 rs6000_cost
= &power6_cost
;
3095 case PROCESSOR_POWER7
:
3096 rs6000_cost
= &power7_cost
;
3099 case PROCESSOR_PPCA2
:
3100 rs6000_cost
= &ppca2_cost
;
3109 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3110 rs6000_cost
->simultaneous_prefetches
,
3111 global_options
.x_param_values
,
3112 global_options_set
.x_param_values
);
3113 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3114 global_options
.x_param_values
,
3115 global_options_set
.x_param_values
);
3116 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3117 rs6000_cost
->cache_line_size
,
3118 global_options
.x_param_values
,
3119 global_options_set
.x_param_values
);
3120 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3121 global_options
.x_param_values
,
3122 global_options_set
.x_param_values
);
3124 /* Increase loop peeling limits based on performance analysis. */
3125 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3126 global_options
.x_param_values
,
3127 global_options_set
.x_param_values
);
3128 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3129 global_options
.x_param_values
,
3130 global_options_set
.x_param_values
);
3132 /* If using typedef char *va_list, signal that
3133 __builtin_va_start (&ap, 0) can be optimized to
3134 ap = __builtin_next_arg (0). */
3135 if (DEFAULT_ABI
!= ABI_V4
)
3136 targetm
.expand_builtin_va_start
= NULL
;
3139 /* Set up single/double float flags.
3140 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3141 then set both flags. */
3142 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3143 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3144 rs6000_single_float
= rs6000_double_float
= 1;
3146 /* If not explicitly specified via option, decide whether to generate indexed
3147 load/store instructions. */
3148 if (TARGET_AVOID_XFORM
== -1)
3149 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3150 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3151 need indexed accesses and the type used is the scalar type of the element
3152 being loaded or stored. */
3153 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3154 && !TARGET_ALTIVEC
);
3156 /* Set the -mrecip options. */
3157 if (rs6000_recip_name
)
3159 char *p
= ASTRDUP (rs6000_recip_name
);
3161 unsigned int mask
, i
;
3164 while ((q
= strtok (p
, ",")) != NULL
)
3175 if (!strcmp (q
, "default"))
3176 mask
= ((TARGET_RECIP_PRECISION
)
3177 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3180 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3181 if (!strcmp (q
, recip_options
[i
].string
))
3183 mask
= recip_options
[i
].mask
;
3187 if (i
== ARRAY_SIZE (recip_options
))
3189 error ("unknown option for -mrecip=%s", q
);
3197 rs6000_recip_control
&= ~mask
;
3199 rs6000_recip_control
|= mask
;
3203 /* Set the builtin mask of the various options used that could affect which
3204 builtins were used. In the past we used target_flags, but we've run out
3205 of bits, and some options like SPE and PAIRED are no longer in
3207 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3208 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3211 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3212 rs6000_builtin_mask
);
3213 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3216 /* Initialize all of the registers. */
3217 rs6000_init_hard_regno_mode_ok (global_init_p
);
3219 /* Save the initial options in case the user does function specific options */
3221 target_option_default_node
= target_option_current_node
3222 = build_target_option_node ();
3224 /* If not explicitly specified via option, decide whether to generate the
3225 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3226 if (TARGET_LINK_STACK
== -1)
3227 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3232 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3233 define the target cpu type. */
3236 rs6000_option_override (void)
3238 (void) rs6000_option_override_internal (true);
3242 /* Implement targetm.vectorize.builtin_mask_for_load. */
3244 rs6000_builtin_mask_for_load (void)
3246 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3247 return altivec_builtin_mask_for_load
;
3252 /* Implement LOOP_ALIGN. */
3254 rs6000_loop_align (rtx label
)
3259 /* Don't override loop alignment if -falign-loops was specified. */
3260 if (!can_override_loop_align
)
3261 return align_loops_log
;
3263 bb
= BLOCK_FOR_INSN (label
);
3264 ninsns
= num_loop_insns(bb
->loop_father
);
3266 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3267 if (ninsns
> 4 && ninsns
<= 8
3268 && (rs6000_cpu
== PROCESSOR_POWER4
3269 || rs6000_cpu
== PROCESSOR_POWER5
3270 || rs6000_cpu
== PROCESSOR_POWER6
3271 || rs6000_cpu
== PROCESSOR_POWER7
))
3274 return align_loops_log
;
3277 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3279 rs6000_loop_align_max_skip (rtx label
)
3281 return (1 << rs6000_loop_align (label
)) - 1;
3284 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3285 after applying N number of iterations. This routine does not determine
3286 how may iterations are required to reach desired alignment. */
3289 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
3296 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
3299 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
3309 /* Assuming that all other types are naturally aligned. CHECKME! */
3314 /* Return true if the vector misalignment factor is supported by the
3317 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
3324 /* Return if movmisalign pattern is not supported for this mode. */
3325 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
3328 if (misalignment
== -1)
3330 /* Misalignment factor is unknown at compile time but we know
3331 it's word aligned. */
3332 if (rs6000_vector_alignment_reachable (type
, is_packed
))
3334 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
3336 if (element_size
== 64 || element_size
== 32)
3343 /* VSX supports word-aligned vector. */
3344 if (misalignment
% 4 == 0)
3350 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3352 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3353 tree vectype
, int misalign
)
3358 switch (type_of_cost
)
3368 case cond_branch_not_taken
:
3377 case vec_promote_demote
:
3383 case cond_branch_taken
:
3386 case unaligned_load
:
3387 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3389 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3391 /* Double word aligned. */
3399 /* Double word aligned. */
3403 /* Unknown misalignment. */
3416 /* Misaligned loads are not supported. */
3421 case unaligned_store
:
3422 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3424 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3426 /* Double word aligned. */
3434 /* Double word aligned. */
3438 /* Unknown misalignment. */
3451 /* Misaligned stores are not supported. */
3457 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3458 elem_type
= TREE_TYPE (vectype
);
3459 /* 32-bit vectors loaded into registers are stored as double
3460 precision, so we need n/2 converts in addition to the usual
3461 n/2 merges to construct a vector of short floats from them. */
3462 if (SCALAR_FLOAT_TYPE_P (elem_type
)
3463 && TYPE_PRECISION (elem_type
) == 32)
3464 return elements
+ 1;
3466 return elements
/ 2 + 1;
3473 /* Implement targetm.vectorize.preferred_simd_mode. */
3475 static enum machine_mode
3476 rs6000_preferred_simd_mode (enum machine_mode mode
)
3485 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3509 if (TARGET_PAIRED_FLOAT
3515 typedef struct _rs6000_cost_data
3517 struct loop
*loop_info
;
3521 /* Test for likely overcommitment of vector hardware resources. If a
3522 loop iteration is relatively large, and too large a percentage of
3523 instructions in the loop are vectorized, the cost model may not
3524 adequately reflect delays from unavailable vector resources.
3525 Penalize the loop body cost for this case. */
3528 rs6000_density_test (rs6000_cost_data
*data
)
3530 const int DENSITY_PCT_THRESHOLD
= 85;
3531 const int DENSITY_SIZE_THRESHOLD
= 70;
3532 const int DENSITY_PENALTY
= 10;
3533 struct loop
*loop
= data
->loop_info
;
3534 basic_block
*bbs
= get_loop_body (loop
);
3535 int nbbs
= loop
->num_nodes
;
3536 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
3539 for (i
= 0; i
< nbbs
; i
++)
3541 basic_block bb
= bbs
[i
];
3542 gimple_stmt_iterator gsi
;
3544 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
3546 gimple stmt
= gsi_stmt (gsi
);
3547 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
3549 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
3550 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
3556 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
3558 if (density_pct
> DENSITY_PCT_THRESHOLD
3559 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
3561 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
3562 if (dump_enabled_p ())
3563 dump_printf_loc (MSG_NOTE
, vect_location
,
3564 "density %d%%, cost %d exceeds threshold, penalizing "
3565 "loop body cost by %d%%", density_pct
,
3566 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
3570 /* Implement targetm.vectorize.init_cost. */
3573 rs6000_init_cost (struct loop
*loop_info
)
3575 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
3576 data
->loop_info
= loop_info
;
3577 data
->cost
[vect_prologue
] = 0;
3578 data
->cost
[vect_body
] = 0;
3579 data
->cost
[vect_epilogue
] = 0;
3583 /* Implement targetm.vectorize.add_stmt_cost. */
3586 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
3587 struct _stmt_vec_info
*stmt_info
, int misalign
,
3588 enum vect_cost_model_location where
)
3590 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
3591 unsigned retval
= 0;
3593 if (flag_vect_cost_model
)
3595 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
3596 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
3598 /* Statements in an inner loop relative to the loop being
3599 vectorized are weighted more heavily. The value here is
3600 arbitrary and could potentially be improved with analysis. */
3601 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
3602 count
*= 50; /* FIXME. */
3604 retval
= (unsigned) (count
* stmt_cost
);
3605 cost_data
->cost
[where
] += retval
;
3611 /* Implement targetm.vectorize.finish_cost. */
3614 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
3615 unsigned *body_cost
, unsigned *epilogue_cost
)
3617 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
3619 if (cost_data
->loop_info
)
3620 rs6000_density_test (cost_data
);
3622 *prologue_cost
= cost_data
->cost
[vect_prologue
];
3623 *body_cost
= cost_data
->cost
[vect_body
];
3624 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
3627 /* Implement targetm.vectorize.destroy_cost_data. */
3630 rs6000_destroy_cost_data (void *data
)
3635 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3636 library with vectorized intrinsics. */
3639 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
3642 const char *suffix
= NULL
;
3643 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
3646 enum machine_mode el_mode
, in_mode
;
3649 /* Libmass is suitable for unsafe math only as it does not correctly support
3650 parts of IEEE with the required precision such as denormals. Only support
3651 it if we have VSX to use the simd d2 or f4 functions.
3652 XXX: Add variable length support. */
3653 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
3656 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
3657 n
= TYPE_VECTOR_SUBPARTS (type_out
);
3658 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
3659 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
3660 if (el_mode
!= in_mode
3664 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
3666 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
3669 case BUILT_IN_ATAN2
:
3670 case BUILT_IN_HYPOT
:
3676 case BUILT_IN_ACOSH
:
3678 case BUILT_IN_ASINH
:
3680 case BUILT_IN_ATANH
:
3688 case BUILT_IN_EXPM1
:
3689 case BUILT_IN_LGAMMA
:
3690 case BUILT_IN_LOG10
:
3691 case BUILT_IN_LOG1P
:
3699 bdecl
= builtin_decl_implicit (fn
);
3700 suffix
= "d2"; /* pow -> powd2 */
3701 if (el_mode
!= DFmode
3706 case BUILT_IN_ATAN2F
:
3707 case BUILT_IN_HYPOTF
:
3712 case BUILT_IN_ACOSF
:
3713 case BUILT_IN_ACOSHF
:
3714 case BUILT_IN_ASINF
:
3715 case BUILT_IN_ASINHF
:
3716 case BUILT_IN_ATANF
:
3717 case BUILT_IN_ATANHF
:
3718 case BUILT_IN_CBRTF
:
3720 case BUILT_IN_COSHF
:
3722 case BUILT_IN_ERFCF
:
3723 case BUILT_IN_EXP2F
:
3725 case BUILT_IN_EXPM1F
:
3726 case BUILT_IN_LGAMMAF
:
3727 case BUILT_IN_LOG10F
:
3728 case BUILT_IN_LOG1PF
:
3729 case BUILT_IN_LOG2F
:
3732 case BUILT_IN_SINHF
:
3733 case BUILT_IN_SQRTF
:
3735 case BUILT_IN_TANHF
:
3736 bdecl
= builtin_decl_implicit (fn
);
3737 suffix
= "4"; /* powf -> powf4 */
3738 if (el_mode
!= SFmode
3750 gcc_assert (suffix
!= NULL
);
3751 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
3752 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
3753 strcat (name
, suffix
);
3756 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
3757 else if (n_args
== 2)
3758 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
3762 /* Build a function declaration for the vectorized function. */
3763 new_fndecl
= build_decl (BUILTINS_LOCATION
,
3764 FUNCTION_DECL
, get_identifier (name
), fntype
);
3765 TREE_PUBLIC (new_fndecl
) = 1;
3766 DECL_EXTERNAL (new_fndecl
) = 1;
3767 DECL_IS_NOVOPS (new_fndecl
) = 1;
3768 TREE_READONLY (new_fndecl
) = 1;
3773 /* Returns a function decl for a vectorized version of the builtin function
3774 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3775 if it is not available. */
3778 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
3781 enum machine_mode in_mode
, out_mode
;
3784 if (TARGET_DEBUG_BUILTIN
)
3785 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3786 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
3787 GET_MODE_NAME (TYPE_MODE (type_out
)),
3788 GET_MODE_NAME (TYPE_MODE (type_in
)));
3790 if (TREE_CODE (type_out
) != VECTOR_TYPE
3791 || TREE_CODE (type_in
) != VECTOR_TYPE
3792 || !TARGET_VECTORIZE_BUILTINS
)
3795 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
3796 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
3797 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
3798 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
3800 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
3802 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
3805 case BUILT_IN_COPYSIGN
:
3806 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3807 && out_mode
== DFmode
&& out_n
== 2
3808 && in_mode
== DFmode
&& in_n
== 2)
3809 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
3811 case BUILT_IN_COPYSIGNF
:
3812 if (out_mode
!= SFmode
|| out_n
!= 4
3813 || in_mode
!= SFmode
|| in_n
!= 4)
3815 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3816 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
3817 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3818 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
3821 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3822 && out_mode
== DFmode
&& out_n
== 2
3823 && in_mode
== DFmode
&& in_n
== 2)
3824 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
3826 case BUILT_IN_SQRTF
:
3827 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3828 && out_mode
== SFmode
&& out_n
== 4
3829 && in_mode
== SFmode
&& in_n
== 4)
3830 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
3833 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3834 && out_mode
== DFmode
&& out_n
== 2
3835 && in_mode
== DFmode
&& in_n
== 2)
3836 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
3838 case BUILT_IN_CEILF
:
3839 if (out_mode
!= SFmode
|| out_n
!= 4
3840 || in_mode
!= SFmode
|| in_n
!= 4)
3842 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3843 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
3844 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3845 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
3847 case BUILT_IN_FLOOR
:
3848 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3849 && out_mode
== DFmode
&& out_n
== 2
3850 && in_mode
== DFmode
&& in_n
== 2)
3851 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
3853 case BUILT_IN_FLOORF
:
3854 if (out_mode
!= SFmode
|| out_n
!= 4
3855 || in_mode
!= SFmode
|| in_n
!= 4)
3857 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3858 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
3859 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3860 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
3863 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3864 && out_mode
== DFmode
&& out_n
== 2
3865 && in_mode
== DFmode
&& in_n
== 2)
3866 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
3869 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3870 && out_mode
== SFmode
&& out_n
== 4
3871 && in_mode
== SFmode
&& in_n
== 4)
3872 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
3873 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
3874 && out_mode
== SFmode
&& out_n
== 4
3875 && in_mode
== SFmode
&& in_n
== 4)
3876 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
3878 case BUILT_IN_TRUNC
:
3879 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3880 && out_mode
== DFmode
&& out_n
== 2
3881 && in_mode
== DFmode
&& in_n
== 2)
3882 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
3884 case BUILT_IN_TRUNCF
:
3885 if (out_mode
!= SFmode
|| out_n
!= 4
3886 || in_mode
!= SFmode
|| in_n
!= 4)
3888 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3889 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
3890 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3891 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
3893 case BUILT_IN_NEARBYINT
:
3894 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3895 && flag_unsafe_math_optimizations
3896 && out_mode
== DFmode
&& out_n
== 2
3897 && in_mode
== DFmode
&& in_n
== 2)
3898 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
3900 case BUILT_IN_NEARBYINTF
:
3901 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3902 && flag_unsafe_math_optimizations
3903 && out_mode
== SFmode
&& out_n
== 4
3904 && in_mode
== SFmode
&& in_n
== 4)
3905 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
3908 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3909 && !flag_trapping_math
3910 && out_mode
== DFmode
&& out_n
== 2
3911 && in_mode
== DFmode
&& in_n
== 2)
3912 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
3914 case BUILT_IN_RINTF
:
3915 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3916 && !flag_trapping_math
3917 && out_mode
== SFmode
&& out_n
== 4
3918 && in_mode
== SFmode
&& in_n
== 4)
3919 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
3926 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
3928 enum rs6000_builtins fn
3929 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
3932 case RS6000_BUILTIN_RSQRTF
:
3933 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
3934 && out_mode
== SFmode
&& out_n
== 4
3935 && in_mode
== SFmode
&& in_n
== 4)
3936 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
3938 case RS6000_BUILTIN_RSQRT
:
3939 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3940 && out_mode
== DFmode
&& out_n
== 2
3941 && in_mode
== DFmode
&& in_n
== 2)
3942 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
3944 case RS6000_BUILTIN_RECIPF
:
3945 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
3946 && out_mode
== SFmode
&& out_n
== 4
3947 && in_mode
== SFmode
&& in_n
== 4)
3948 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
3950 case RS6000_BUILTIN_RECIP
:
3951 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3952 && out_mode
== DFmode
&& out_n
== 2
3953 && in_mode
== DFmode
&& in_n
== 2)
3954 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
3961 /* Generate calls to libmass if appropriate. */
3962 if (rs6000_veclib_handler
)
3963 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
3968 /* Default CPU string for rs6000*_file_start functions. */
3969 static const char *rs6000_default_cpu
;
3971 /* Do anything needed at the start of the asm file. */
3974 rs6000_file_start (void)
3977 const char *start
= buffer
;
3978 FILE *file
= asm_out_file
;
3980 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
3982 default_file_start ();
3984 if (flag_verbose_asm
)
3986 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
3988 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
3990 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
3994 if (global_options_set
.x_rs6000_cpu_index
)
3996 fprintf (file
, "%s -mcpu=%s", start
,
3997 processor_target_table
[rs6000_cpu_index
].name
);
4001 if (global_options_set
.x_rs6000_tune_index
)
4003 fprintf (file
, "%s -mtune=%s", start
,
4004 processor_target_table
[rs6000_tune_index
].name
);
4008 if (PPC405_ERRATUM77
)
4010 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4014 #ifdef USING_ELFOS_H
4015 switch (rs6000_sdata
)
4017 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4018 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4019 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4020 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4023 if (rs6000_sdata
&& g_switch_value
)
4025 fprintf (file
, "%s -G %d", start
,
4035 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
4037 switch_to_section (toc_section
);
4038 switch_to_section (text_section
);
4043 /* Return nonzero if this function is known to have a null epilogue. */
4046 direct_return (void)
4048 if (reload_completed
)
4050 rs6000_stack_t
*info
= rs6000_stack_info ();
4052 if (info
->first_gp_reg_save
== 32
4053 && info
->first_fp_reg_save
== 64
4054 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4055 && ! info
->lr_save_p
4056 && ! info
->cr_save_p
4057 && info
->vrsave_mask
== 0
4065 /* Return the number of instructions it takes to form a constant in an
4066 integer register. */
4069 num_insns_constant_wide (HOST_WIDE_INT value
)
4071 /* signed constant loadable with addi */
4072 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4075 /* constant loadable with addis */
4076 else if ((value
& 0xffff) == 0
4077 && (value
>> 31 == -1 || value
>> 31 == 0))
4080 #if HOST_BITS_PER_WIDE_INT == 64
4081 else if (TARGET_POWERPC64
)
4083 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4084 HOST_WIDE_INT high
= value
>> 31;
4086 if (high
== 0 || high
== -1)
4092 return num_insns_constant_wide (high
) + 1;
4094 return num_insns_constant_wide (low
) + 1;
4096 return (num_insns_constant_wide (high
)
4097 + num_insns_constant_wide (low
) + 1);
4106 num_insns_constant (rtx op
, enum machine_mode mode
)
4108 HOST_WIDE_INT low
, high
;
4110 switch (GET_CODE (op
))
4113 #if HOST_BITS_PER_WIDE_INT == 64
4114 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4115 && mask64_operand (op
, mode
))
4119 return num_insns_constant_wide (INTVAL (op
));
4122 if (mode
== SFmode
|| mode
== SDmode
)
4127 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4128 if (DECIMAL_FLOAT_MODE_P (mode
))
4129 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4131 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4132 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4135 if (mode
== VOIDmode
|| mode
== DImode
)
4137 high
= CONST_DOUBLE_HIGH (op
);
4138 low
= CONST_DOUBLE_LOW (op
);
4145 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4146 if (DECIMAL_FLOAT_MODE_P (mode
))
4147 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4149 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4150 high
= l
[WORDS_BIG_ENDIAN
== 0];
4151 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4155 return (num_insns_constant_wide (low
)
4156 + num_insns_constant_wide (high
));
4159 if ((high
== 0 && low
>= 0)
4160 || (high
== -1 && low
< 0))
4161 return num_insns_constant_wide (low
);
4163 else if (mask64_operand (op
, mode
))
4167 return num_insns_constant_wide (high
) + 1;
4170 return (num_insns_constant_wide (high
)
4171 + num_insns_constant_wide (low
) + 1);
4179 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4180 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4181 corresponding element of the vector, but for V4SFmode and V2SFmode,
4182 the corresponding "float" is interpreted as an SImode integer. */
4185 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4189 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4190 gcc_assert (GET_MODE (op
) != V2DImode
4191 && GET_MODE (op
) != V2DFmode
);
4193 tmp
= CONST_VECTOR_ELT (op
, elt
);
4194 if (GET_MODE (op
) == V4SFmode
4195 || GET_MODE (op
) == V2SFmode
)
4196 tmp
= gen_lowpart (SImode
, tmp
);
4197 return INTVAL (tmp
);
4200 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4201 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4202 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4203 all items are set to the same value and contain COPIES replicas of the
4204 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4205 operand and the others are set to the value of the operand's msb. */
4208 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4210 enum machine_mode mode
= GET_MODE (op
);
4211 enum machine_mode inner
= GET_MODE_INNER (mode
);
4219 HOST_WIDE_INT splat_val
;
4220 HOST_WIDE_INT msb_val
;
4222 if (mode
== V2DImode
|| mode
== V2DFmode
)
4225 nunits
= GET_MODE_NUNITS (mode
);
4226 bitsize
= GET_MODE_BITSIZE (inner
);
4227 mask
= GET_MODE_MASK (inner
);
4229 val
= const_vector_elt_as_int (op
, nunits
- 1);
4231 msb_val
= val
> 0 ? 0 : -1;
4233 /* Construct the value to be splatted, if possible. If not, return 0. */
4234 for (i
= 2; i
<= copies
; i
*= 2)
4236 HOST_WIDE_INT small_val
;
4238 small_val
= splat_val
>> bitsize
;
4240 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4242 splat_val
= small_val
;
4245 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4246 if (EASY_VECTOR_15 (splat_val
))
4249 /* Also check if we can splat, and then add the result to itself. Do so if
4250 the value is positive, of if the splat instruction is using OP's mode;
4251 for splat_val < 0, the splat and the add should use the same mode. */
4252 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4253 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4256 /* Also check if are loading up the most significant bit which can be done by
4257 loading up -1 and shifting the value left by -1. */
4258 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4264 /* Check if VAL is present in every STEP-th element, and the
4265 other elements are filled with its most significant bit. */
4266 for (i
= 0; i
< nunits
- 1; ++i
)
4268 HOST_WIDE_INT desired_val
;
4269 if (((i
+ 1) & (step
- 1)) == 0)
4272 desired_val
= msb_val
;
4274 if (desired_val
!= const_vector_elt_as_int (op
, i
))
4282 /* Return true if OP is of the given MODE and can be synthesized
4283 with a vspltisb, vspltish or vspltisw. */
4286 easy_altivec_constant (rtx op
, enum machine_mode mode
)
4288 unsigned step
, copies
;
4290 if (mode
== VOIDmode
)
4291 mode
= GET_MODE (op
);
4292 else if (mode
!= GET_MODE (op
))
4295 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4297 if (mode
== V2DFmode
)
4298 return zero_constant (op
, mode
);
4300 if (mode
== V2DImode
)
4302 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4304 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
4305 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
4308 if (zero_constant (op
, mode
))
4311 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
4312 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
4318 /* Start with a vspltisw. */
4319 step
= GET_MODE_NUNITS (mode
) / 4;
4322 if (vspltis_constant (op
, step
, copies
))
4325 /* Then try with a vspltish. */
4331 if (vspltis_constant (op
, step
, copies
))
4334 /* And finally a vspltisb. */
4340 if (vspltis_constant (op
, step
, copies
))
4346 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4347 result is OP. Abort if it is not possible. */
4350 gen_easy_altivec_constant (rtx op
)
4352 enum machine_mode mode
= GET_MODE (op
);
4353 int nunits
= GET_MODE_NUNITS (mode
);
4354 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
4355 unsigned step
= nunits
/ 4;
4356 unsigned copies
= 1;
4358 /* Start with a vspltisw. */
4359 if (vspltis_constant (op
, step
, copies
))
4360 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
4362 /* Then try with a vspltish. */
4368 if (vspltis_constant (op
, step
, copies
))
4369 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
4371 /* And finally a vspltisb. */
4377 if (vspltis_constant (op
, step
, copies
))
4378 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
4384 output_vec_const_move (rtx
*operands
)
4387 enum machine_mode mode
;
4392 mode
= GET_MODE (dest
);
4396 if (zero_constant (vec
, mode
))
4397 return "xxlxor %x0,%x0,%x0";
4399 if (mode
== V2DImode
4400 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
4401 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
4402 return "vspltisw %0,-1";
4408 if (zero_constant (vec
, mode
))
4409 return "vxor %0,%0,%0";
4411 splat_vec
= gen_easy_altivec_constant (vec
);
4412 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
4413 operands
[1] = XEXP (splat_vec
, 0);
4414 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
4417 switch (GET_MODE (splat_vec
))
4420 return "vspltisw %0,%1";
4423 return "vspltish %0,%1";
4426 return "vspltisb %0,%1";
4433 gcc_assert (TARGET_SPE
);
4435 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4436 pattern of V1DI, V4HI, and V2SF.
4438 FIXME: We should probably return # and add post reload
4439 splitters for these, but this way is so easy ;-). */
4440 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
4441 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
4442 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
4443 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
4445 return "li %0,%1\n\tevmergelo %0,%0,%0";
4447 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4450 /* Initialize TARGET of vector PAIRED to VALS. */
4453 paired_expand_vector_init (rtx target
, rtx vals
)
4455 enum machine_mode mode
= GET_MODE (target
);
4456 int n_elts
= GET_MODE_NUNITS (mode
);
4458 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
4461 for (i
= 0; i
< n_elts
; ++i
)
4463 x
= XVECEXP (vals
, 0, i
);
4464 if (!(CONST_INT_P (x
)
4465 || GET_CODE (x
) == CONST_DOUBLE
4466 || GET_CODE (x
) == CONST_FIXED
))
4471 /* Load from constant pool. */
4472 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
4478 /* The vector is initialized only with non-constants. */
4479 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
4480 XVECEXP (vals
, 0, 1));
4482 emit_move_insn (target
, new_rtx
);
4486 /* One field is non-constant and the other one is a constant. Load the
4487 constant from the constant pool and use ps_merge instruction to
4488 construct the whole vector. */
4489 op1
= XVECEXP (vals
, 0, 0);
4490 op2
= XVECEXP (vals
, 0, 1);
4492 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
4494 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
4495 emit_move_insn (tmp
, constant_op
);
4497 if (CONSTANT_P (op1
))
4498 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
4500 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
4502 emit_move_insn (target
, new_rtx
);
4506 paired_expand_vector_move (rtx operands
[])
4508 rtx op0
= operands
[0], op1
= operands
[1];
4510 emit_move_insn (op0
, op1
);
4513 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4514 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4515 operands for the relation operation COND. This is a recursive
4519 paired_emit_vector_compare (enum rtx_code rcode
,
4520 rtx dest
, rtx op0
, rtx op1
,
4521 rtx cc_op0
, rtx cc_op1
)
4523 rtx tmp
= gen_reg_rtx (V2SFmode
);
4526 gcc_assert (TARGET_PAIRED_FLOAT
);
4527 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
4533 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4537 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4538 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
4542 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
4545 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4548 tmp1
= gen_reg_rtx (V2SFmode
);
4549 max
= gen_reg_rtx (V2SFmode
);
4550 min
= gen_reg_rtx (V2SFmode
);
4551 gen_reg_rtx (V2SFmode
);
4553 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4554 emit_insn (gen_selv2sf4
4555 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4556 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
4557 emit_insn (gen_selv2sf4
4558 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4559 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
4560 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
4563 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4566 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4569 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4572 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4575 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4584 /* Emit vector conditional expression.
4585 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4586 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4589 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
4590 rtx cond
, rtx cc_op0
, rtx cc_op1
)
4592 enum rtx_code rcode
= GET_CODE (cond
);
4594 if (!TARGET_PAIRED_FLOAT
)
4597 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
4602 /* Initialize vector TARGET to VALS. */
4605 rs6000_expand_vector_init (rtx target
, rtx vals
)
4607 enum machine_mode mode
= GET_MODE (target
);
4608 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4609 int n_elts
= GET_MODE_NUNITS (mode
);
4610 int n_var
= 0, one_var
= -1;
4611 bool all_same
= true, all_const_zero
= true;
4615 for (i
= 0; i
< n_elts
; ++i
)
4617 x
= XVECEXP (vals
, 0, i
);
4618 if (!(CONST_INT_P (x
)
4619 || GET_CODE (x
) == CONST_DOUBLE
4620 || GET_CODE (x
) == CONST_FIXED
))
4621 ++n_var
, one_var
= i
;
4622 else if (x
!= CONST0_RTX (inner_mode
))
4623 all_const_zero
= false;
4625 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
4631 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
4632 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
4633 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
4635 /* Zero register. */
4636 emit_insn (gen_rtx_SET (VOIDmode
, target
,
4637 gen_rtx_XOR (mode
, target
, target
)));
4640 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
4642 /* Splat immediate. */
4643 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
4648 /* Load from constant pool. */
4649 emit_move_insn (target
, const_vec
);
4654 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4655 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
4657 rtx op0
= XVECEXP (vals
, 0, 0);
4658 rtx op1
= XVECEXP (vals
, 0, 1);
4661 if (!MEM_P (op0
) && !REG_P (op0
))
4662 op0
= force_reg (inner_mode
, op0
);
4663 if (mode
== V2DFmode
)
4664 emit_insn (gen_vsx_splat_v2df (target
, op0
));
4666 emit_insn (gen_vsx_splat_v2di (target
, op0
));
4670 op0
= force_reg (inner_mode
, op0
);
4671 op1
= force_reg (inner_mode
, op1
);
4672 if (mode
== V2DFmode
)
4673 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
4675 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
4680 /* With single precision floating point on VSX, know that internally single
4681 precision is actually represented as a double, and either make 2 V2DF
4682 vectors, and convert these vectors to single precision, or do one
4683 conversion, and splat the result to the other elements. */
4684 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
4688 rtx freg
= gen_reg_rtx (V4SFmode
);
4689 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
4691 emit_insn (gen_vsx_xscvdpsp_scalar (freg
, sreg
));
4692 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
4696 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
4697 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
4698 rtx flt_even
= gen_reg_rtx (V4SFmode
);
4699 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
4700 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
4701 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
4702 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
4703 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
4705 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
4706 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
4707 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
4708 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
4709 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
4714 /* Store value to stack temp. Load vector element. Splat. However, splat
4715 of 64-bit items is not supported on Altivec. */
4716 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
4718 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
4719 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
4720 XVECEXP (vals
, 0, 0));
4721 x
= gen_rtx_UNSPEC (VOIDmode
,
4722 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
4723 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4725 gen_rtx_SET (VOIDmode
,
4728 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
4729 gen_rtx_PARALLEL (VOIDmode
,
4730 gen_rtvec (1, const0_rtx
)));
4731 emit_insn (gen_rtx_SET (VOIDmode
, target
,
4732 gen_rtx_VEC_DUPLICATE (mode
, x
)));
4736 /* One field is non-constant. Load constant then overwrite
4740 rtx copy
= copy_rtx (vals
);
4742 /* Load constant part of vector, substitute neighboring value for
4744 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
4745 rs6000_expand_vector_init (target
, copy
);
4747 /* Insert variable. */
4748 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
4752 /* Construct the vector in memory one field at a time
4753 and load the whole vector. */
4754 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
4755 for (i
= 0; i
< n_elts
; i
++)
4756 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
4757 i
* GET_MODE_SIZE (inner_mode
)),
4758 XVECEXP (vals
, 0, i
));
4759 emit_move_insn (target
, mem
);
4762 /* Set field ELT of TARGET to VAL. */
4765 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
4767 enum machine_mode mode
= GET_MODE (target
);
4768 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4769 rtx reg
= gen_reg_rtx (mode
);
4771 int width
= GET_MODE_SIZE (inner_mode
);
4774 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
4776 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
4777 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
4778 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
4782 /* Load single variable value. */
4783 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
4784 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
4785 x
= gen_rtx_UNSPEC (VOIDmode
,
4786 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
4787 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4789 gen_rtx_SET (VOIDmode
,
4793 /* Linear sequence. */
4794 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
4795 for (i
= 0; i
< 16; ++i
)
4796 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
4798 /* Set permute mask to insert element into target. */
4799 for (i
= 0; i
< width
; ++i
)
4800 XVECEXP (mask
, 0, elt
*width
+ i
)
4801 = GEN_INT (i
+ 0x10);
4802 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
4803 x
= gen_rtx_UNSPEC (mode
,
4804 gen_rtvec (3, target
, reg
,
4805 force_reg (V16QImode
, x
)),
4807 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
4810 /* Extract field ELT from VEC into TARGET. */
4813 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
4815 enum machine_mode mode
= GET_MODE (vec
);
4816 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4819 if (VECTOR_MEM_VSX_P (mode
))
4826 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
4829 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
4832 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
4837 /* Allocate mode-sized buffer. */
4838 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
4840 emit_move_insn (mem
, vec
);
4842 /* Add offset to field within buffer matching vector element. */
4843 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
4845 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
4848 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4849 implement ANDing by the mask IN. */
4851 build_mask64_2_operands (rtx in
, rtx
*out
)
4853 #if HOST_BITS_PER_WIDE_INT >= 64
4854 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
4857 gcc_assert (GET_CODE (in
) == CONST_INT
);
4862 /* Assume c initially something like 0x00fff000000fffff. The idea
4863 is to rotate the word so that the middle ^^^^^^ group of zeros
4864 is at the MS end and can be cleared with an rldicl mask. We then
4865 rotate back and clear off the MS ^^ group of zeros with a
4867 c
= ~c
; /* c == 0xff000ffffff00000 */
4868 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
4869 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
4870 c
= ~c
; /* c == 0x00fff000000fffff */
4871 c
&= -lsb
; /* c == 0x00fff00000000000 */
4872 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
4873 c
= ~c
; /* c == 0xff000fffffffffff */
4874 c
&= -lsb
; /* c == 0xff00000000000000 */
4876 while ((lsb
>>= 1) != 0)
4877 shift
++; /* shift == 44 on exit from loop */
4878 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
4879 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
4880 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
4884 /* Assume c initially something like 0xff000f0000000000. The idea
4885 is to rotate the word so that the ^^^ middle group of zeros
4886 is at the LS end and can be cleared with an rldicr mask. We then
4887 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4889 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
4890 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
4891 c
= ~c
; /* c == 0x00fff0ffffffffff */
4892 c
&= -lsb
; /* c == 0x00fff00000000000 */
4893 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
4894 c
= ~c
; /* c == 0xff000fffffffffff */
4895 c
&= -lsb
; /* c == 0xff00000000000000 */
4897 while ((lsb
>>= 1) != 0)
4898 shift
++; /* shift == 44 on exit from loop */
4899 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
4900 m1
>>= shift
; /* m1 == 0x0000000000000fff */
4901 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
4904 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4905 masks will be all 1's. We are guaranteed more than one transition. */
4906 out
[0] = GEN_INT (64 - shift
);
4907 out
[1] = GEN_INT (m1
);
4908 out
[2] = GEN_INT (shift
);
4909 out
[3] = GEN_INT (m2
);
4917 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4920 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
4922 if (TARGET_E500_DOUBLE
)
4924 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4925 subreg:TI and reg:TF. Decimal float modes are like integer
4926 modes (only low part of each register used) for this
4928 if (GET_CODE (op
) == SUBREG
4929 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
4930 || mode
== DDmode
|| mode
== TDmode
)
4931 && REG_P (SUBREG_REG (op
))
4932 && (GET_MODE (SUBREG_REG (op
)) == DFmode
4933 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
4936 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4938 if (GET_CODE (op
) == SUBREG
4939 && (mode
== DFmode
|| mode
== TFmode
)
4940 && REG_P (SUBREG_REG (op
))
4941 && (GET_MODE (SUBREG_REG (op
)) == DImode
4942 || GET_MODE (SUBREG_REG (op
)) == TImode
4943 || GET_MODE (SUBREG_REG (op
)) == DDmode
4944 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
4949 && GET_CODE (op
) == SUBREG
4951 && REG_P (SUBREG_REG (op
))
4952 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
4958 /* AIX increases natural record alignment to doubleword if the first
4959 field is an FP double while the FP fields remain word aligned. */
4962 rs6000_special_round_type_align (tree type
, unsigned int computed
,
4963 unsigned int specified
)
4965 unsigned int align
= MAX (computed
, specified
);
4966 tree field
= TYPE_FIELDS (type
);
4968 /* Skip all non field decls */
4969 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
4970 field
= DECL_CHAIN (field
);
4972 if (field
!= NULL
&& field
!= type
)
4974 type
= TREE_TYPE (field
);
4975 while (TREE_CODE (type
) == ARRAY_TYPE
)
4976 type
= TREE_TYPE (type
);
4978 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
4979 align
= MAX (align
, 64);
4985 /* Darwin increases record alignment to the natural alignment of
4989 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
4990 unsigned int specified
)
4992 unsigned int align
= MAX (computed
, specified
);
4994 if (TYPE_PACKED (type
))
4997 /* Find the first field, looking down into aggregates. */
4999 tree field
= TYPE_FIELDS (type
);
5000 /* Skip all non field decls */
5001 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5002 field
= DECL_CHAIN (field
);
5005 /* A packed field does not contribute any extra alignment. */
5006 if (DECL_PACKED (field
))
5008 type
= TREE_TYPE (field
);
5009 while (TREE_CODE (type
) == ARRAY_TYPE
)
5010 type
= TREE_TYPE (type
);
5011 } while (AGGREGATE_TYPE_P (type
));
5013 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5014 align
= MAX (align
, TYPE_ALIGN (type
));
5019 /* Return 1 for an operand in small memory on V.4/eabi. */
5022 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5023 enum machine_mode mode ATTRIBUTE_UNUSED
)
5028 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5031 if (DEFAULT_ABI
!= ABI_V4
)
5034 /* Vector and float memory instructions have a limited offset on the
5035 SPE, so using a vector or float variable directly as an operand is
5038 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5041 if (GET_CODE (op
) == SYMBOL_REF
)
5044 else if (GET_CODE (op
) != CONST
5045 || GET_CODE (XEXP (op
, 0)) != PLUS
5046 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5047 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5052 rtx sum
= XEXP (op
, 0);
5053 HOST_WIDE_INT summand
;
5055 /* We have to be careful here, because it is the referenced address
5056 that must be 32k from _SDA_BASE_, not just the symbol. */
5057 summand
= INTVAL (XEXP (sum
, 1));
5058 if (summand
< 0 || summand
> g_switch_value
)
5061 sym_ref
= XEXP (sum
, 0);
5064 return SYMBOL_REF_SMALL_P (sym_ref
);
5070 /* Return true if either operand is a general purpose register. */
5073 gpr_or_gpr_p (rtx op0
, rtx op1
)
5075 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5076 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5079 /* Given an address, return a constant offset term if one exists. */
5082 address_offset (rtx op
)
5084 if (GET_CODE (op
) == PRE_INC
5085 || GET_CODE (op
) == PRE_DEC
)
5087 else if (GET_CODE (op
) == PRE_MODIFY
5088 || GET_CODE (op
) == LO_SUM
)
5091 if (GET_CODE (op
) == CONST
)
5094 if (GET_CODE (op
) == PLUS
)
5097 if (CONST_INT_P (op
))
5103 /* Return true if the MEM operand is a memory operand suitable for use
5104 with a (full width, possibly multiple) gpr load/store. On
5105 powerpc64 this means the offset must be divisible by 4.
5106 Implements 'Y' constraint.
5108 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5109 a constraint function we know the operand has satisfied a suitable
5110 memory predicate. Also accept some odd rtl generated by reload
5111 (see rs6000_legitimize_reload_address for various forms). It is
5112 important that reload rtl be accepted by appropriate constraints
5113 but not by the operand predicate.
5115 Offsetting a lo_sum should not be allowed, except where we know by
5116 alignment that a 32k boundary is not crossed, but see the ???
5117 comment in rs6000_legitimize_reload_address. Note that by
5118 "offsetting" here we mean a further offset to access parts of the
5119 MEM. It's fine to have a lo_sum where the inner address is offset
5120 from a sym, since the same sym+offset will appear in the high part
5121 of the address calculation. */
5124 mem_operand_gpr (rtx op
, enum machine_mode mode
)
5126 unsigned HOST_WIDE_INT offset
;
5128 rtx addr
= XEXP (op
, 0);
5130 op
= address_offset (addr
);
5134 offset
= INTVAL (op
);
5135 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
5138 if (GET_CODE (addr
) == LO_SUM
)
5139 /* We know by alignment that ABI_AIX medium/large model toc refs
5140 will not cross a 32k boundary, since all entries in the
5141 constant pool are naturally aligned and we check alignment for
5142 other medium model toc-relative addresses. For ABI_V4 and
5143 ABI_DARWIN lo_sum addresses, we just check that 64-bit
5144 offsets are 4-byte aligned. */
5147 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
5148 gcc_assert (extra
>= 0);
5149 return offset
+ 0x8000 < 0x10000u
- extra
;
5152 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5155 reg_offset_addressing_ok_p (enum machine_mode mode
)
5165 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5166 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
5174 /* Paired vector modes. Only reg+reg addressing is valid. */
5175 if (TARGET_PAIRED_FLOAT
)
5187 virtual_stack_registers_memory_p (rtx op
)
5191 if (GET_CODE (op
) == REG
)
5192 regnum
= REGNO (op
);
5194 else if (GET_CODE (op
) == PLUS
5195 && GET_CODE (XEXP (op
, 0)) == REG
5196 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5197 regnum
= REGNO (XEXP (op
, 0));
5202 return (regnum
>= FIRST_VIRTUAL_REGISTER
5203 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
5206 /* Return true if memory accesses to OP are known to never straddle
5210 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
5211 enum machine_mode mode
)
5214 unsigned HOST_WIDE_INT dsize
, dalign
;
5216 if (GET_CODE (op
) != SYMBOL_REF
)
5219 decl
= SYMBOL_REF_DECL (op
);
5222 if (GET_MODE_SIZE (mode
) == 0)
5225 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5226 replacing memory addresses with an anchor plus offset. We
5227 could find the decl by rummaging around in the block->objects
5228 VEC for the given offset but that seems like too much work. */
5230 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
5231 && SYMBOL_REF_ANCHOR_P (op
)
5232 && SYMBOL_REF_BLOCK (op
) != NULL
)
5234 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
5235 HOST_WIDE_INT lsb
, mask
;
5237 /* Given the alignment of the block.. */
5238 dalign
= block
->alignment
;
5239 mask
= dalign
/ BITS_PER_UNIT
- 1;
5241 /* ..and the combined offset of the anchor and any offset
5242 to this block object.. */
5243 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
5244 lsb
= offset
& -offset
;
5246 /* ..find how many bits of the alignment we know for the
5251 return dalign
>= GET_MODE_SIZE (mode
);
5256 if (TREE_CODE (decl
) == FUNCTION_DECL
)
5259 if (!DECL_SIZE_UNIT (decl
))
5262 if (!host_integerp (DECL_SIZE_UNIT (decl
), 1))
5265 dsize
= tree_low_cst (DECL_SIZE_UNIT (decl
), 1);
5269 dalign
= DECL_ALIGN_UNIT (decl
);
5270 return dalign
>= dsize
;
5273 type
= TREE_TYPE (decl
);
5275 if (TREE_CODE (decl
) == STRING_CST
)
5276 dsize
= TREE_STRING_LENGTH (decl
);
5277 else if (TYPE_SIZE_UNIT (type
)
5278 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5279 dsize
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
5285 dalign
= TYPE_ALIGN (type
);
5286 if (CONSTANT_CLASS_P (decl
))
5287 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
5289 dalign
= DATA_ALIGNMENT (decl
, dalign
);
5290 dalign
/= BITS_PER_UNIT
;
5291 return dalign
>= dsize
;
5295 constant_pool_expr_p (rtx op
)
5299 split_const (op
, &base
, &offset
);
5300 return (GET_CODE (base
) == SYMBOL_REF
5301 && CONSTANT_POOL_ADDRESS_P (base
)
5302 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
5305 static const_rtx tocrel_base
, tocrel_offset
;
5307 /* Return true if OP is a toc pointer relative address (the output
5308 of create_TOC_reference). If STRICT, do not match high part or
5309 non-split -mcmodel=large/medium toc pointer relative addresses. */
5312 toc_relative_expr_p (const_rtx op
, bool strict
)
5317 if (TARGET_CMODEL
!= CMODEL_SMALL
)
5319 /* Only match the low part. */
5320 if (GET_CODE (op
) == LO_SUM
5321 && REG_P (XEXP (op
, 0))
5322 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
5329 tocrel_offset
= const0_rtx
;
5330 if (GET_CODE (op
) == PLUS
&& CONST_INT_P (XEXP (op
, 1)))
5332 tocrel_base
= XEXP (op
, 0);
5333 tocrel_offset
= XEXP (op
, 1);
5336 return (GET_CODE (tocrel_base
) == UNSPEC
5337 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
5340 /* Return true if X is a constant pool address, and also for cmodel=medium
5341 if X is a toc-relative address known to be offsettable within MODE. */
5344 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
5347 return (toc_relative_expr_p (x
, strict
)
5348 && (TARGET_CMODEL
!= CMODEL_MEDIUM
5349 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
5351 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
5352 INTVAL (tocrel_offset
), mode
)));
5356 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
5358 return (DEFAULT_ABI
== ABI_V4
5359 && !flag_pic
&& !TARGET_TOC
5360 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
5361 && small_data_operand (x
, mode
));
5364 /* SPE offset addressing is limited to 5-bits worth of double words. */
5365 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5368 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
5369 bool strict
, bool worst_case
)
5371 unsigned HOST_WIDE_INT offset
;
5374 if (GET_CODE (x
) != PLUS
)
5376 if (!REG_P (XEXP (x
, 0)))
5378 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5380 if (!reg_offset_addressing_ok_p (mode
))
5381 return virtual_stack_registers_memory_p (x
);
5382 if (legitimate_constant_pool_address_p (x
, mode
, strict
))
5384 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5387 offset
= INTVAL (XEXP (x
, 1));
5395 /* SPE vector modes. */
5396 return SPE_CONST_OFFSET_OK (offset
);
5401 /* On e500v2, we may have:
5403 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5405 Which gets addressed with evldd instructions. */
5406 if (TARGET_E500_DOUBLE
)
5407 return SPE_CONST_OFFSET_OK (offset
);
5409 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5411 if (mode
== DFmode
&& VECTOR_MEM_VSX_P (DFmode
))
5416 if (!TARGET_POWERPC64
)
5418 else if (offset
& 3)
5425 if (TARGET_E500_DOUBLE
)
5426 return (SPE_CONST_OFFSET_OK (offset
)
5427 && SPE_CONST_OFFSET_OK (offset
+ 8));
5432 if (!TARGET_POWERPC64
)
5434 else if (offset
& 3)
5443 return offset
< 0x10000 - extra
;
5447 legitimate_indexed_address_p (rtx x
, int strict
)
5451 if (GET_CODE (x
) != PLUS
)
5457 /* Recognize the rtl generated by reload which we know will later be
5458 replaced with proper base and index regs. */
5460 && reload_in_progress
5461 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
5465 return (REG_P (op0
) && REG_P (op1
)
5466 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
5467 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
5468 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
5469 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
5473 avoiding_indexed_address_p (enum machine_mode mode
)
5475 /* Avoid indexed addressing for modes that have non-indexed
5476 load/store instruction forms. */
5477 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
5481 legitimate_indirect_address_p (rtx x
, int strict
)
5483 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
5487 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
5489 if (!TARGET_MACHO
|| !flag_pic
5490 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
5494 if (GET_CODE (x
) != LO_SUM
)
5496 if (GET_CODE (XEXP (x
, 0)) != REG
)
5498 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
5502 return CONSTANT_P (x
);
5506 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
5508 if (GET_CODE (x
) != LO_SUM
)
5510 if (GET_CODE (XEXP (x
, 0)) != REG
)
5512 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5514 /* Restrict addressing for DI because of our SUBREG hackery. */
5515 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
5519 if (TARGET_ELF
|| TARGET_MACHO
)
5521 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
5525 if (GET_MODE_NUNITS (mode
) != 1)
5527 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
5528 && !(/* ??? Assume floating point reg based on mode? */
5529 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
5530 && (mode
== DFmode
|| mode
== DDmode
)))
5533 return CONSTANT_P (x
);
5540 /* Try machine-dependent ways of modifying an illegitimate address
5541 to be legitimate. If we find one, return the new, valid address.
5542 This is used from only one place: `memory_address' in explow.c.
5544 OLDX is the address as it was before break_out_memory_refs was
5545 called. In some cases it is useful to look at this to decide what
5548 It is always safe for this function to do nothing. It exists to
5549 recognize opportunities to optimize the output.
5551 On RS/6000, first check for the sum of a register with a constant
5552 integer that is out of range. If so, generate code to add the
5553 constant with the low-order 16 bits masked to the register and force
5554 this result into another register (this can be done with `cau').
5555 Then generate an address of REG+(CONST&0xffff), allowing for the
5556 possibility of bit 16 being a one.
5558 Then check for the sum of a register and something not constant, try to
5559 load the other things into a register and return the sum. */
5562 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
5563 enum machine_mode mode
)
5567 if (!reg_offset_addressing_ok_p (mode
))
5569 if (virtual_stack_registers_memory_p (x
))
5572 /* In theory we should not be seeing addresses of the form reg+0,
5573 but just in case it is generated, optimize it away. */
5574 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
5575 return force_reg (Pmode
, XEXP (x
, 0));
5577 /* Make sure both operands are registers. */
5578 else if (GET_CODE (x
) == PLUS
)
5579 return gen_rtx_PLUS (Pmode
,
5580 force_reg (Pmode
, XEXP (x
, 0)),
5581 force_reg (Pmode
, XEXP (x
, 1)));
5583 return force_reg (Pmode
, x
);
5585 if (GET_CODE (x
) == SYMBOL_REF
)
5587 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
5589 return rs6000_legitimize_tls_address (x
, model
);
5598 /* As in legitimate_offset_address_p we do not assume
5599 worst-case. The mode here is just a hint as to the registers
5600 used. A TImode is usually in gprs, but may actually be in
5601 fprs. Leave worst-case scenario for reload to handle via
5602 insn constraints. */
5609 if (GET_CODE (x
) == PLUS
5610 && GET_CODE (XEXP (x
, 0)) == REG
5611 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5612 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
5614 && !(SPE_VECTOR_MODE (mode
)
5615 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
5617 HOST_WIDE_INT high_int
, low_int
;
5619 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5620 if (low_int
>= 0x8000 - extra
)
5622 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
5623 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5624 GEN_INT (high_int
)), 0);
5625 return plus_constant (Pmode
, sum
, low_int
);
5627 else if (GET_CODE (x
) == PLUS
5628 && GET_CODE (XEXP (x
, 0)) == REG
5629 && GET_CODE (XEXP (x
, 1)) != CONST_INT
5630 && GET_MODE_NUNITS (mode
) == 1
5631 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
5632 || (/* ??? Assume floating point reg based on mode? */
5633 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5634 && (mode
== DFmode
|| mode
== DDmode
)))
5635 && !avoiding_indexed_address_p (mode
))
5637 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5638 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
5640 else if (SPE_VECTOR_MODE (mode
)
5641 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
5645 /* We accept [reg + reg] and [reg + OFFSET]. */
5647 if (GET_CODE (x
) == PLUS
)
5649 rtx op1
= XEXP (x
, 0);
5650 rtx op2
= XEXP (x
, 1);
5653 op1
= force_reg (Pmode
, op1
);
5655 if (GET_CODE (op2
) != REG
5656 && (GET_CODE (op2
) != CONST_INT
5657 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
5658 || (GET_MODE_SIZE (mode
) > 8
5659 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
5660 op2
= force_reg (Pmode
, op2
);
5662 /* We can't always do [reg + reg] for these, because [reg +
5663 reg + offset] is not a legitimate addressing mode. */
5664 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
5666 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
5667 return force_reg (Pmode
, y
);
5672 return force_reg (Pmode
, x
);
5674 else if ((TARGET_ELF
5676 || !MACHO_DYNAMIC_NO_PIC_P
5682 && GET_CODE (x
) != CONST_INT
5683 && GET_CODE (x
) != CONST_DOUBLE
5685 && GET_MODE_NUNITS (mode
) == 1
5686 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
5687 || (/* ??? Assume floating point reg based on mode? */
5688 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5689 && (mode
== DFmode
|| mode
== DDmode
))))
5691 rtx reg
= gen_reg_rtx (Pmode
);
5693 emit_insn (gen_elf_high (reg
, x
));
5695 emit_insn (gen_macho_high (reg
, x
));
5696 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
5699 && GET_CODE (x
) == SYMBOL_REF
5700 && constant_pool_expr_p (x
)
5701 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
5702 return create_TOC_reference (x
, NULL_RTX
);
5707 /* Debug version of rs6000_legitimize_address. */
5709 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
5715 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
5716 insns
= get_insns ();
5722 "\nrs6000_legitimize_address: mode %s, old code %s, "
5723 "new code %s, modified\n",
5724 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
5725 GET_RTX_NAME (GET_CODE (ret
)));
5727 fprintf (stderr
, "Original address:\n");
5730 fprintf (stderr
, "oldx:\n");
5733 fprintf (stderr
, "New address:\n");
5738 fprintf (stderr
, "Insns added:\n");
5739 debug_rtx_list (insns
, 20);
5745 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5746 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
5757 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5758 We need to emit DTP-relative relocations. */
5760 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
5762 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5767 fputs ("\t.long\t", file
);
5770 fputs (DOUBLE_INT_ASM_OP
, file
);
5775 output_addr_const (file
, x
);
5776 fputs ("@dtprel+0x8000", file
);
5779 /* In the name of slightly smaller debug output, and to cater to
5780 general assembler lossage, recognize various UNSPEC sequences
5781 and turn them back into a direct symbol reference. */
5784 rs6000_delegitimize_address (rtx orig_x
)
5788 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5794 if (TARGET_CMODEL
!= CMODEL_SMALL
5795 && GET_CODE (y
) == LO_SUM
)
5799 if (GET_CODE (y
) == PLUS
5800 && GET_MODE (y
) == Pmode
5801 && CONST_INT_P (XEXP (y
, 1)))
5803 offset
= XEXP (y
, 1);
5807 if (GET_CODE (y
) == UNSPEC
5808 && XINT (y
, 1) == UNSPEC_TOCREL
)
5810 #ifdef ENABLE_CHECKING
5811 if (REG_P (XVECEXP (y
, 0, 1))
5812 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
5816 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
5818 /* Weirdness alert. df_note_compute can replace r2 with a
5819 debug_expr when this unspec is in a debug_insn.
5820 Seen in gcc.dg/pr51957-1.c */
5828 y
= XVECEXP (y
, 0, 0);
5831 /* Do not associate thread-local symbols with the original
5832 constant pool symbol. */
5834 && GET_CODE (y
) == SYMBOL_REF
5835 && CONSTANT_POOL_ADDRESS_P (y
)
5836 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
5840 if (offset
!= NULL_RTX
)
5841 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
5842 if (!MEM_P (orig_x
))
5845 return replace_equiv_address_nv (orig_x
, y
);
5849 && GET_CODE (orig_x
) == LO_SUM
5850 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
5852 y
= XEXP (XEXP (orig_x
, 1), 0);
5853 if (GET_CODE (y
) == UNSPEC
5854 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
5855 return XVECEXP (y
, 0, 0);
5861 /* Return true if X shouldn't be emitted into the debug info.
5862 The linker doesn't like .toc section references from
5863 .debug_* sections, so reject .toc section symbols. */
5866 rs6000_const_not_ok_for_debug_p (rtx x
)
5868 if (GET_CODE (x
) == SYMBOL_REF
5869 && CONSTANT_POOL_ADDRESS_P (x
))
5871 rtx c
= get_pool_constant (x
);
5872 enum machine_mode cmode
= get_pool_mode (x
);
5873 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
5880 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5882 static GTY(()) rtx rs6000_tls_symbol
;
5884 rs6000_tls_get_addr (void)
5886 if (!rs6000_tls_symbol
)
5887 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
5889 return rs6000_tls_symbol
;
5892 /* Construct the SYMBOL_REF for TLS GOT references. */
5894 static GTY(()) rtx rs6000_got_symbol
;
5896 rs6000_got_sym (void)
5898 if (!rs6000_got_symbol
)
5900 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
5901 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
5902 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
5905 return rs6000_got_symbol
;
5908 /* AIX Thread-Local Address support. */
5911 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
5913 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
5917 name
= XSTR (addr
, 0);
5918 /* Append TLS CSECT qualifier, unless the symbol already is qualified
5919 or the symbol will be in TLS private data section. */
5920 if (name
[strlen (name
) - 1] != ']'
5921 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
5922 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
5924 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
5925 strcpy (tlsname
, name
);
5927 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
5928 tlsaddr
= copy_rtx (addr
);
5929 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
5934 /* Place addr into TOC constant pool. */
5935 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
5937 /* Output the TOC entry and create the MEM referencing the value. */
5938 if (constant_pool_expr_p (XEXP (sym
, 0))
5939 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
5941 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
5942 mem
= gen_const_mem (Pmode
, tocref
);
5943 set_mem_alias_set (mem
, get_TOC_alias_set ());
5948 /* Use global-dynamic for local-dynamic. */
5949 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
5950 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
5952 /* Create new TOC reference for @m symbol. */
5953 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
5954 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
5955 strcpy (tlsname
, "*LCM");
5956 strcat (tlsname
, name
+ 3);
5957 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
5958 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
5959 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
5960 rtx modmem
= gen_const_mem (Pmode
, tocref
);
5961 set_mem_alias_set (modmem
, get_TOC_alias_set ());
5963 rtx modreg
= gen_reg_rtx (Pmode
);
5964 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
5966 tmpreg
= gen_reg_rtx (Pmode
);
5967 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
5969 dest
= gen_reg_rtx (Pmode
);
5971 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
5973 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
5976 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
5977 else if (TARGET_32BIT
)
5979 tlsreg
= gen_reg_rtx (SImode
);
5980 emit_insn (gen_tls_get_tpointer (tlsreg
));
5983 tlsreg
= gen_rtx_REG (DImode
, 13);
5985 /* Load the TOC value into temporary register. */
5986 tmpreg
= gen_reg_rtx (Pmode
);
5987 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
5988 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
5989 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
5991 /* Add TOC symbol value to TLS pointer. */
5992 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
5997 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5998 this (thread-local) address. */
6001 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6006 return rs6000_legitimize_tls_address_aix (addr
, model
);
6008 dest
= gen_reg_rtx (Pmode
);
6009 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6015 tlsreg
= gen_rtx_REG (Pmode
, 13);
6016 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6020 tlsreg
= gen_rtx_REG (Pmode
, 2);
6021 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6025 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6029 tmp
= gen_reg_rtx (Pmode
);
6032 tlsreg
= gen_rtx_REG (Pmode
, 13);
6033 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6037 tlsreg
= gen_rtx_REG (Pmode
, 2);
6038 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6042 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6044 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6049 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6051 /* We currently use relocations like @got@tlsgd for tls, which
6052 means the linker will handle allocation of tls entries, placing
6053 them in the .got section. So use a pointer to the .got section,
6054 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6055 or to secondary GOT sections used by 32-bit -fPIC. */
6057 got
= gen_rtx_REG (Pmode
, 2);
6061 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6064 rtx gsym
= rs6000_got_sym ();
6065 got
= gen_reg_rtx (Pmode
);
6067 rs6000_emit_move (got
, gsym
, Pmode
);
6072 tmp1
= gen_reg_rtx (Pmode
);
6073 tmp2
= gen_reg_rtx (Pmode
);
6074 mem
= gen_const_mem (Pmode
, tmp1
);
6075 lab
= gen_label_rtx ();
6076 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6077 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6078 if (TARGET_LINK_STACK
)
6079 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6080 emit_move_insn (tmp2
, mem
);
6081 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6082 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
6087 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
6089 tga
= rs6000_tls_get_addr ();
6090 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
6091 1, const0_rtx
, Pmode
);
6093 r3
= gen_rtx_REG (Pmode
, 3);
6094 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6095 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
6096 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6097 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
6098 else if (DEFAULT_ABI
== ABI_V4
)
6099 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
6102 call_insn
= last_call_insn ();
6103 PATTERN (call_insn
) = insn
;
6104 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6105 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6106 pic_offset_table_rtx
);
6108 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
6110 tga
= rs6000_tls_get_addr ();
6111 tmp1
= gen_reg_rtx (Pmode
);
6112 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
6113 1, const0_rtx
, Pmode
);
6115 r3
= gen_rtx_REG (Pmode
, 3);
6116 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6117 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
6118 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6119 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
6120 else if (DEFAULT_ABI
== ABI_V4
)
6121 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
6124 call_insn
= last_call_insn ();
6125 PATTERN (call_insn
) = insn
;
6126 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6127 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6128 pic_offset_table_rtx
);
6130 if (rs6000_tls_size
== 16)
6133 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
6135 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
6137 else if (rs6000_tls_size
== 32)
6139 tmp2
= gen_reg_rtx (Pmode
);
6141 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
6143 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
6146 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
6148 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
6152 tmp2
= gen_reg_rtx (Pmode
);
6154 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
6156 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
6158 insn
= gen_rtx_SET (Pmode
, dest
,
6159 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
6165 /* IE, or 64-bit offset LE. */
6166 tmp2
= gen_reg_rtx (Pmode
);
6168 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
6170 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
6173 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
6175 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
6183 /* Return 1 if X contains a thread-local symbol. */
6186 rs6000_tls_referenced_p (rtx x
)
6188 if (! TARGET_HAVE_TLS
)
6191 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
6194 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6197 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6199 if (GET_CODE (x
) == HIGH
6200 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6203 /* A TLS symbol in the TOC cannot contain a sum. */
6204 if (GET_CODE (x
) == CONST
6205 && GET_CODE (XEXP (x
, 0)) == PLUS
6206 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
6207 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
6210 /* Do not place an ELF TLS symbol in the constant pool. */
6211 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
6214 /* Return 1 if *X is a thread-local symbol. This is the same as
6215 rs6000_tls_symbol_ref except for the type of the unused argument. */
6218 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6220 return RS6000_SYMBOL_REF_TLS_P (*x
);
6223 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
6224 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
6225 can be addressed relative to the toc pointer. */
6228 use_toc_relative_ref (rtx sym
)
6230 return ((constant_pool_expr_p (sym
)
6231 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
6232 get_pool_mode (sym
)))
6233 || (TARGET_CMODEL
== CMODEL_MEDIUM
6234 && !CONSTANT_POOL_ADDRESS_P (sym
)
6235 && SYMBOL_REF_LOCAL_P (sym
)));
6238 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6239 replace the input X, or the original X if no replacement is called for.
6240 The output parameter *WIN is 1 if the calling macro should goto WIN,
6243 For RS/6000, we wish to handle large displacements off a base
6244 register by splitting the addend across an addiu/addis and the mem insn.
6245 This cuts number of extra insns needed from 3 to 1.
6247 On Darwin, we use this to generate code for floating point constants.
6248 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6249 The Darwin code is inside #if TARGET_MACHO because only then are the
6250 machopic_* functions defined. */
6252 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6253 int opnum
, int type
,
6254 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
6256 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6258 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6259 DFmode/DImode MEM. */
6262 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
6263 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
6264 reg_offset_p
= false;
6266 /* We must recognize output that we have already generated ourselves. */
6267 if (GET_CODE (x
) == PLUS
6268 && GET_CODE (XEXP (x
, 0)) == PLUS
6269 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6270 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6271 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6273 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6274 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6275 opnum
, (enum reload_type
) type
);
6280 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6281 if (GET_CODE (x
) == LO_SUM
6282 && GET_CODE (XEXP (x
, 0)) == HIGH
)
6284 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6285 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6286 opnum
, (enum reload_type
) type
);
6292 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
6293 && GET_CODE (x
) == LO_SUM
6294 && GET_CODE (XEXP (x
, 0)) == PLUS
6295 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
6296 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
6297 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
6298 && machopic_operand_p (XEXP (x
, 1)))
6300 /* Result of previous invocation of this function on Darwin
6301 floating point constant. */
6302 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6303 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6304 opnum
, (enum reload_type
) type
);
6310 if (TARGET_CMODEL
!= CMODEL_SMALL
6312 && small_toc_ref (x
, VOIDmode
))
6314 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
6315 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
6316 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6317 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6318 opnum
, (enum reload_type
) type
);
6323 if (GET_CODE (x
) == PLUS
6324 && GET_CODE (XEXP (x
, 0)) == REG
6325 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
6326 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
6327 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6329 && !SPE_VECTOR_MODE (mode
)
6330 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
6331 || mode
== DDmode
|| mode
== TDmode
6333 && VECTOR_MEM_NONE_P (mode
))
6335 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
6336 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
6338 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6340 /* Check for 32-bit overflow. */
6341 if (high
+ low
!= val
)
6347 /* Reload the high part into a base reg; leave the low part
6348 in the mem directly. */
6350 x
= gen_rtx_PLUS (GET_MODE (x
),
6351 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
6355 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6356 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6357 opnum
, (enum reload_type
) type
);
6362 if (GET_CODE (x
) == SYMBOL_REF
6364 && VECTOR_MEM_NONE_P (mode
)
6365 && !SPE_VECTOR_MODE (mode
)
6367 && DEFAULT_ABI
== ABI_DARWIN
6368 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
6369 && machopic_symbol_defined_p (x
)
6371 && DEFAULT_ABI
== ABI_V4
6374 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6375 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6377 ??? Assume floating point reg based on mode? This assumption is
6378 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
6379 where reload ends up doing a DFmode load of a constant from
6380 mem using two gprs. Unfortunately, at this point reload
6381 hasn't yet selected regs so poking around in reload data
6382 won't help and even if we could figure out the regs reliably,
6383 we'd still want to allow this transformation when the mem is
6384 naturally aligned. Since we say the address is good here, we
6385 can't disable offsets from LO_SUMs in mem_operand_gpr.
6386 FIXME: Allow offset from lo_sum for other modes too, when
6387 mem is sufficiently aligned. */
6390 && (mode
!= DImode
|| TARGET_POWERPC64
)
6391 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
6392 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
6397 rtx offset
= machopic_gen_offset (x
);
6398 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6399 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
6400 gen_rtx_HIGH (Pmode
, offset
)), offset
);
6404 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6405 gen_rtx_HIGH (Pmode
, x
), x
);
6407 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6408 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6409 opnum
, (enum reload_type
) type
);
6414 /* Reload an offset address wrapped by an AND that represents the
6415 masking of the lower bits. Strip the outer AND and let reload
6416 convert the offset address into an indirect address. For VSX,
6417 force reload to create the address with an AND in a separate
6418 register, because we can't guarantee an altivec register will
6420 if (VECTOR_MEM_ALTIVEC_P (mode
)
6421 && GET_CODE (x
) == AND
6422 && GET_CODE (XEXP (x
, 0)) == PLUS
6423 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6424 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6425 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6426 && INTVAL (XEXP (x
, 1)) == -16)
6435 && GET_CODE (x
) == SYMBOL_REF
6436 && use_toc_relative_ref (x
))
6438 x
= create_TOC_reference (x
, NULL_RTX
);
6439 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6440 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6441 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6442 opnum
, (enum reload_type
) type
);
6450 /* Debug version of rs6000_legitimize_reload_address. */
6452 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6453 int opnum
, int type
,
6454 int ind_levels
, int *win
)
6456 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
6459 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6460 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6461 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
6465 fprintf (stderr
, "Same address returned\n");
6467 fprintf (stderr
, "NULL returned\n");
6470 fprintf (stderr
, "New address:\n");
6477 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6478 that is a valid memory address for an instruction.
6479 The MODE argument is the machine mode for the MEM expression
6480 that wants to use this address.
6482 On the RS/6000, there are four valid address: a SYMBOL_REF that
6483 refers to a constant pool entry of an address (or the sum of it
6484 plus a constant), a short (16-bit signed) constant plus a register,
6485 the sum of two registers, or a register indirect, possibly with an
6486 auto-increment. For DFmode, DDmode and DImode with a constant plus
6487 register, we must ensure that both words are addressable or PowerPC64
6488 with offset word aligned.
6490 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6491 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6492 because adjacent memory cells are accessed by adding word-sized offsets
6493 during assembly output. */
6495 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
6497 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6499 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6500 if (VECTOR_MEM_ALTIVEC_P (mode
)
6501 && GET_CODE (x
) == AND
6502 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6503 && INTVAL (XEXP (x
, 1)) == -16)
6506 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
6508 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
6510 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
6511 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
6512 && !SPE_VECTOR_MODE (mode
)
6515 /* Restrict addressing for DI because of our SUBREG hackery. */
6516 && !(TARGET_E500_DOUBLE
6517 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
6519 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
6521 if (virtual_stack_registers_memory_p (x
))
6523 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
6526 && legitimate_constant_pool_address_p (x
, mode
, reg_ok_strict
))
6528 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6531 && GET_CODE (x
) == PLUS
6532 && GET_CODE (XEXP (x
, 0)) == REG
6533 && (XEXP (x
, 0) == virtual_stack_vars_rtx
6534 || XEXP (x
, 0) == arg_pointer_rtx
)
6535 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6537 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
6542 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6544 || (mode
!= DFmode
&& mode
!= DDmode
)
6545 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
6546 && (TARGET_POWERPC64
|| mode
!= DImode
)
6547 && !avoiding_indexed_address_p (mode
)
6548 && legitimate_indexed_address_p (x
, reg_ok_strict
))
6550 if (GET_CODE (x
) == PRE_MODIFY
6554 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6556 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
6557 && (TARGET_POWERPC64
|| mode
!= DImode
)
6558 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
6559 && !SPE_VECTOR_MODE (mode
)
6560 /* Restrict addressing for DI because of our SUBREG hackery. */
6561 && !(TARGET_E500_DOUBLE
6562 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
6564 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
6565 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
6566 reg_ok_strict
, false)
6567 || (!avoiding_indexed_address_p (mode
)
6568 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
6569 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6571 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
6576 /* Debug version of rs6000_legitimate_address_p. */
6578 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
6581 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
6583 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6584 "strict = %d, code = %s\n",
6585 ret
? "true" : "false",
6586 GET_MODE_NAME (mode
),
6588 GET_RTX_NAME (GET_CODE (x
)));
6594 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6597 rs6000_mode_dependent_address_p (const_rtx addr
,
6598 addr_space_t as ATTRIBUTE_UNUSED
)
6600 return rs6000_mode_dependent_address_ptr (addr
);
6603 /* Go to LABEL if ADDR (a legitimate address expression)
6604 has an effect that depends on the machine mode it is used for.
6606 On the RS/6000 this is true of all integral offsets (since AltiVec
6607 and VSX modes don't allow them) or is a pre-increment or decrement.
6609 ??? Except that due to conceptual problems in offsettable_address_p
6610 we can't really report the problems of integral offsets. So leave
6611 this assuming that the adjustable offset must be valid for the
6612 sub-words of a TFmode operand, which is what we had before. */
6615 rs6000_mode_dependent_address (const_rtx addr
)
6617 switch (GET_CODE (addr
))
6620 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6621 is considered a legitimate address before reload, so there
6622 are no offset restrictions in that case. Note that this
6623 condition is safe in strict mode because any address involving
6624 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6625 been rejected as illegitimate. */
6626 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
6627 && XEXP (addr
, 0) != arg_pointer_rtx
6628 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6630 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
6631 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
6636 /* Anything in the constant pool is sufficiently aligned that
6637 all bytes have the same high part address. */
6638 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
6640 /* Auto-increment cases are now treated generically in recog.c. */
6642 return TARGET_UPDATE
;
6644 /* AND is only allowed in Altivec loads. */
6655 /* Debug version of rs6000_mode_dependent_address. */
6657 rs6000_debug_mode_dependent_address (const_rtx addr
)
6659 bool ret
= rs6000_mode_dependent_address (addr
);
6661 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
6662 ret
? "true" : "false");
6668 /* Implement FIND_BASE_TERM. */
6671 rs6000_find_base_term (rtx op
)
6676 if (GET_CODE (base
) == CONST
)
6677 base
= XEXP (base
, 0);
6678 if (GET_CODE (base
) == PLUS
)
6679 base
= XEXP (base
, 0);
6680 if (GET_CODE (base
) == UNSPEC
)
6681 switch (XINT (base
, 1))
6684 case UNSPEC_MACHOPIC_OFFSET
:
6685 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6686 for aliasing purposes. */
6687 return XVECEXP (base
, 0, 0);
6693 /* More elaborate version of recog's offsettable_memref_p predicate
6694 that works around the ??? note of rs6000_mode_dependent_address.
6695 In particular it accepts
6697 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6699 in 32-bit mode, that the recog predicate rejects. */
6702 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
6709 /* First mimic offsettable_memref_p. */
6710 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
6713 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6714 the latter predicate knows nothing about the mode of the memory
6715 reference and, therefore, assumes that it is the largest supported
6716 mode (TFmode). As a consequence, legitimate offsettable memory
6717 references are rejected. rs6000_legitimate_offset_address_p contains
6718 the correct logic for the PLUS case of rs6000_mode_dependent_address,
6719 at least with a little bit of help here given that we know the
6720 actual registers used. */
6721 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
6722 || GET_MODE_SIZE (reg_mode
) == 4);
6723 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
6727 /* Change register usage conditional on target flags. */
6729 rs6000_conditional_register_usage (void)
6733 if (TARGET_DEBUG_TARGET
)
6734 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
6736 /* Set MQ register fixed (already call_used) so that it will not be
6740 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6742 fixed_regs
[13] = call_used_regs
[13]
6743 = call_really_used_regs
[13] = 1;
6745 /* Conditionally disable FPRs. */
6746 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
6747 for (i
= 32; i
< 64; i
++)
6748 fixed_regs
[i
] = call_used_regs
[i
]
6749 = call_really_used_regs
[i
] = 1;
6751 /* The TOC register is not killed across calls in a way that is
6752 visible to the compiler. */
6753 if (DEFAULT_ABI
== ABI_AIX
)
6754 call_really_used_regs
[2] = 0;
6756 if (DEFAULT_ABI
== ABI_V4
6757 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
6759 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6761 if (DEFAULT_ABI
== ABI_V4
6762 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
6764 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6765 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6766 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6768 if (DEFAULT_ABI
== ABI_DARWIN
6769 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
6770 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6771 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6772 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6774 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
6775 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6776 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6780 global_regs
[SPEFSCR_REGNO
] = 1;
6781 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6782 registers in prologues and epilogues. We no longer use r14
6783 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6784 pool for link-compatibility with older versions of GCC. Once
6785 "old" code has died out, we can return r14 to the allocation
6788 = call_used_regs
[14]
6789 = call_really_used_regs
[14] = 1;
6792 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
6794 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
6795 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6796 call_really_used_regs
[VRSAVE_REGNO
] = 1;
6799 if (TARGET_ALTIVEC
|| TARGET_VSX
)
6800 global_regs
[VSCR_REGNO
] = 1;
6802 if (TARGET_ALTIVEC_ABI
)
6804 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
6805 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6807 /* AIX reserves VR20:31 in non-extended ABI mode. */
6809 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
6810 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6814 /* Try to output insns to set TARGET equal to the constant C if it can
6815 be done in less than N insns. Do all computations in MODE.
6816 Returns the place where the output has been placed if it can be
6817 done and the insns have been emitted. If it would take more than N
6818 insns, zero is returned and no insns and emitted. */
6821 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
6822 rtx source
, int n ATTRIBUTE_UNUSED
)
6824 rtx result
, insn
, set
;
6825 HOST_WIDE_INT c0
, c1
;
6832 dest
= gen_reg_rtx (mode
);
6833 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
6837 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
6839 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
6840 GEN_INT (INTVAL (source
)
6841 & (~ (HOST_WIDE_INT
) 0xffff))));
6842 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
6843 gen_rtx_IOR (SImode
, copy_rtx (result
),
6844 GEN_INT (INTVAL (source
) & 0xffff))));
6849 switch (GET_CODE (source
))
6852 c0
= INTVAL (source
);
6857 #if HOST_BITS_PER_WIDE_INT >= 64
6858 c0
= CONST_DOUBLE_LOW (source
);
6861 c0
= CONST_DOUBLE_LOW (source
);
6862 c1
= CONST_DOUBLE_HIGH (source
);
6870 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
6877 insn
= get_last_insn ();
6878 set
= single_set (insn
);
6879 if (! CONSTANT_P (SET_SRC (set
)))
6880 set_unique_reg_note (insn
, REG_EQUAL
, source
);
6885 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6886 fall back to a straight forward decomposition. We do this to avoid
6887 exponential run times encountered when looking for longer sequences
6888 with rs6000_emit_set_const. */
6890 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
6892 if (!TARGET_POWERPC64
)
6894 rtx operand1
, operand2
;
6896 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
6898 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
6900 emit_move_insn (operand1
, GEN_INT (c1
));
6901 emit_move_insn (operand2
, GEN_INT (c2
));
6905 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
6908 ud2
= (c1
& 0xffff0000) >> 16;
6909 #if HOST_BITS_PER_WIDE_INT >= 64
6913 ud4
= (c2
& 0xffff0000) >> 16;
6915 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
6916 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
6919 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
6921 emit_move_insn (dest
, GEN_INT (ud1
));
6924 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
6925 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
6928 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
6931 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
6933 emit_move_insn (copy_rtx (dest
),
6934 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6937 else if (ud3
== 0 && ud4
== 0)
6939 gcc_assert (ud2
& 0x8000);
6940 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
6943 emit_move_insn (copy_rtx (dest
),
6944 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6946 emit_move_insn (copy_rtx (dest
),
6947 gen_rtx_ZERO_EXTEND (DImode
,
6948 gen_lowpart (SImode
,
6951 else if ((ud4
== 0xffff && (ud3
& 0x8000))
6952 || (ud4
== 0 && ! (ud3
& 0x8000)))
6955 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
6958 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
6961 emit_move_insn (copy_rtx (dest
),
6962 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6964 emit_move_insn (copy_rtx (dest
),
6965 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
6968 emit_move_insn (copy_rtx (dest
),
6969 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6975 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
6978 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
6981 emit_move_insn (copy_rtx (dest
),
6982 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6985 emit_move_insn (copy_rtx (dest
),
6986 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
6989 emit_move_insn (copy_rtx (dest
),
6990 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6991 GEN_INT (ud2
<< 16)));
6993 emit_move_insn (copy_rtx (dest
),
6994 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
7000 /* Helper for the following. Get rid of [r+r] memory refs
7001 in cases where it won't work (TImode, TFmode, TDmode). */
7004 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7006 if (reload_in_progress
)
7009 if (GET_CODE (operands
[0]) == MEM
7010 && GET_CODE (XEXP (operands
[0], 0)) != REG
7011 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7012 GET_MODE (operands
[0]), false))
7014 = replace_equiv_address (operands
[0],
7015 copy_addr_to_reg (XEXP (operands
[0], 0)));
7017 if (GET_CODE (operands
[1]) == MEM
7018 && GET_CODE (XEXP (operands
[1], 0)) != REG
7019 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7020 GET_MODE (operands
[1]), false))
7022 = replace_equiv_address (operands
[1],
7023 copy_addr_to_reg (XEXP (operands
[1], 0)));
7026 /* Emit a move from SOURCE to DEST in mode MODE. */
7028 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
7032 operands
[1] = source
;
7034 if (TARGET_DEBUG_ADDR
)
7037 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
7038 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
7039 GET_MODE_NAME (mode
),
7042 can_create_pseudo_p ());
7044 fprintf (stderr
, "source:\n");
7048 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
7049 if (GET_CODE (operands
[1]) == CONST_DOUBLE
7050 && ! FLOAT_MODE_P (mode
)
7051 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
7053 /* FIXME. This should never happen. */
7054 /* Since it seems that it does, do the safe thing and convert
7056 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
7058 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
7059 || FLOAT_MODE_P (mode
)
7060 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
7061 || CONST_DOUBLE_LOW (operands
[1]) < 0)
7062 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
7063 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
7065 /* Check if GCC is setting up a block move that will end up using FP
7066 registers as temporaries. We must make sure this is acceptable. */
7067 if (GET_CODE (operands
[0]) == MEM
7068 && GET_CODE (operands
[1]) == MEM
7070 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
7071 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
7072 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
7073 ? 32 : MEM_ALIGN (operands
[0])))
7074 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
7076 : MEM_ALIGN (operands
[1]))))
7077 && ! MEM_VOLATILE_P (operands
[0])
7078 && ! MEM_VOLATILE_P (operands
[1]))
7080 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
7081 adjust_address (operands
[1], SImode
, 0));
7082 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
7083 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
7087 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
7088 && !gpc_reg_operand (operands
[1], mode
))
7089 operands
[1] = force_reg (mode
, operands
[1]);
7091 /* Recognize the case where operand[1] is a reference to thread-local
7092 data and load its address to a register. */
7093 if (rs6000_tls_referenced_p (operands
[1]))
7095 enum tls_model model
;
7096 rtx tmp
= operands
[1];
7099 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
7101 addend
= XEXP (XEXP (tmp
, 0), 1);
7102 tmp
= XEXP (XEXP (tmp
, 0), 0);
7105 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
7106 model
= SYMBOL_REF_TLS_MODEL (tmp
);
7107 gcc_assert (model
!= 0);
7109 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
7112 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
7113 tmp
= force_operand (tmp
, operands
[0]);
7118 /* Handle the case where reload calls us with an invalid address. */
7119 if (reload_in_progress
&& mode
== Pmode
7120 && (! general_operand (operands
[1], mode
)
7121 || ! nonimmediate_operand (operands
[0], mode
)))
7124 /* 128-bit constant floating-point values on Darwin should really be
7125 loaded as two parts. */
7126 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
7127 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
7129 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
7130 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
7132 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
7133 GET_MODE_SIZE (DFmode
)),
7134 simplify_gen_subreg (DFmode
, operands
[1], mode
,
7135 GET_MODE_SIZE (DFmode
)),
7140 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
7141 cfun
->machine
->sdmode_stack_slot
=
7142 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
7144 if (reload_in_progress
7146 && MEM_P (operands
[0])
7147 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
7148 && REG_P (operands
[1]))
7150 if (FP_REGNO_P (REGNO (operands
[1])))
7152 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
7153 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7154 emit_insn (gen_movsd_store (mem
, operands
[1]));
7156 else if (INT_REGNO_P (REGNO (operands
[1])))
7158 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
7159 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7160 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
7166 if (reload_in_progress
7168 && REG_P (operands
[0])
7169 && MEM_P (operands
[1])
7170 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
7172 if (FP_REGNO_P (REGNO (operands
[0])))
7174 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
7175 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7176 emit_insn (gen_movsd_load (operands
[0], mem
));
7178 else if (INT_REGNO_P (REGNO (operands
[0])))
7180 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
7181 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7182 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
7189 /* FIXME: In the long term, this switch statement should go away
7190 and be replaced by a sequence of tests based on things like
7196 if (CONSTANT_P (operands
[1])
7197 && GET_CODE (operands
[1]) != CONST_INT
)
7198 operands
[1] = force_const_mem (mode
, operands
[1]);
7203 rs6000_eliminate_indexed_memrefs (operands
);
7210 if (CONSTANT_P (operands
[1])
7211 && ! easy_fp_constant (operands
[1], mode
))
7212 operands
[1] = force_const_mem (mode
, operands
[1]);
7225 if (CONSTANT_P (operands
[1])
7226 && !easy_vector_constant (operands
[1], mode
))
7227 operands
[1] = force_const_mem (mode
, operands
[1]);
7232 /* Use default pattern for address of ELF small data */
7235 && DEFAULT_ABI
== ABI_V4
7236 && (GET_CODE (operands
[1]) == SYMBOL_REF
7237 || GET_CODE (operands
[1]) == CONST
)
7238 && small_data_operand (operands
[1], mode
))
7240 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7244 if (DEFAULT_ABI
== ABI_V4
7245 && mode
== Pmode
&& mode
== SImode
7246 && flag_pic
== 1 && got_operand (operands
[1], mode
))
7248 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
7252 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
7256 && CONSTANT_P (operands
[1])
7257 && GET_CODE (operands
[1]) != HIGH
7258 && GET_CODE (operands
[1]) != CONST_INT
)
7260 rtx target
= (!can_create_pseudo_p ()
7262 : gen_reg_rtx (mode
));
7264 /* If this is a function address on -mcall-aixdesc,
7265 convert it to the address of the descriptor. */
7266 if (DEFAULT_ABI
== ABI_AIX
7267 && GET_CODE (operands
[1]) == SYMBOL_REF
7268 && XSTR (operands
[1], 0)[0] == '.')
7270 const char *name
= XSTR (operands
[1], 0);
7272 while (*name
== '.')
7274 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
7275 CONSTANT_POOL_ADDRESS_P (new_ref
)
7276 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
7277 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
7278 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
7279 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
7280 operands
[1] = new_ref
;
7283 if (DEFAULT_ABI
== ABI_DARWIN
)
7286 if (MACHO_DYNAMIC_NO_PIC_P
)
7288 /* Take care of any required data indirection. */
7289 operands
[1] = rs6000_machopic_legitimize_pic_address (
7290 operands
[1], mode
, operands
[0]);
7291 if (operands
[0] != operands
[1])
7292 emit_insn (gen_rtx_SET (VOIDmode
,
7293 operands
[0], operands
[1]));
7297 emit_insn (gen_macho_high (target
, operands
[1]));
7298 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
7302 emit_insn (gen_elf_high (target
, operands
[1]));
7303 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
7307 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7308 and we have put it in the TOC, we just need to make a TOC-relative
7311 && GET_CODE (operands
[1]) == SYMBOL_REF
7312 && use_toc_relative_ref (operands
[1]))
7313 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
7314 else if (mode
== Pmode
7315 && CONSTANT_P (operands
[1])
7316 && GET_CODE (operands
[1]) != HIGH
7317 && ((GET_CODE (operands
[1]) != CONST_INT
7318 && ! easy_fp_constant (operands
[1], mode
))
7319 || (GET_CODE (operands
[1]) == CONST_INT
7320 && (num_insns_constant (operands
[1], mode
)
7321 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
7322 || (GET_CODE (operands
[0]) == REG
7323 && FP_REGNO_P (REGNO (operands
[0]))))
7324 && !toc_relative_expr_p (operands
[1], false)
7325 && (TARGET_CMODEL
== CMODEL_SMALL
7326 || can_create_pseudo_p ()
7327 || (REG_P (operands
[0])
7328 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
7332 /* Darwin uses a special PIC legitimizer. */
7333 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
7336 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
7338 if (operands
[0] != operands
[1])
7339 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7344 /* If we are to limit the number of things we put in the TOC and
7345 this is a symbol plus a constant we can add in one insn,
7346 just put the symbol in the TOC and add the constant. Don't do
7347 this if reload is in progress. */
7348 if (GET_CODE (operands
[1]) == CONST
7349 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
7350 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
7351 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
7352 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
7353 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
7354 && ! side_effects_p (operands
[0]))
7357 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
7358 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
7360 sym
= force_reg (mode
, sym
);
7361 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
7365 operands
[1] = force_const_mem (mode
, operands
[1]);
7368 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
7369 && constant_pool_expr_p (XEXP (operands
[1], 0))
7370 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7371 get_pool_constant (XEXP (operands
[1], 0)),
7372 get_pool_mode (XEXP (operands
[1], 0))))
7374 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
7376 operands
[1] = gen_const_mem (mode
, tocref
);
7377 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
7383 rs6000_eliminate_indexed_memrefs (operands
);
7387 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
7390 /* Above, we may have called force_const_mem which may have returned
7391 an invalid address. If we can, fix this up; otherwise, reload will
7392 have to deal with it. */
7393 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
7394 operands
[1] = validize_mem (operands
[1]);
7397 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7400 /* Return true if a structure, union or array containing FIELD should be
7401 accessed using `BLKMODE'.
7403 For the SPE, simd types are V2SI, and gcc can be tempted to put the
7404 entire thing in a DI and use subregs to access the internals.
7405 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
7406 back-end. Because a single GPR can hold a V2SI, but not a DI, the
7407 best thing to do is set structs to BLKmode and avoid Severe Tire
7410 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
7411 fit into 1, whereas DI still needs two. */
7414 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
7416 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
7417 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
7420 /* Nonzero if we can use a floating-point register to pass this arg. */
7421 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7422 (SCALAR_FLOAT_MODE_P (MODE) \
7423 && (CUM)->fregno <= FP_ARG_MAX_REG \
7424 && TARGET_HARD_FLOAT && TARGET_FPRS)
7426 /* Nonzero if we can use an AltiVec register to pass this arg. */
7427 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7428 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7429 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7430 && TARGET_ALTIVEC_ABI \
7433 /* Return a nonzero value to say to return the function value in
7434 memory, just as large structures are always returned. TYPE will be
7435 the data type of the value, and FNTYPE will be the type of the
7436 function doing the returning, or @code{NULL} for libcalls.
7438 The AIX ABI for the RS/6000 specifies that all structures are
7439 returned in memory. The Darwin ABI does the same.
7441 For the Darwin 64 Bit ABI, a function result can be returned in
7442 registers or in memory, depending on the size of the return data
7443 type. If it is returned in registers, the value occupies the same
7444 registers as it would if it were the first and only function
7445 argument. Otherwise, the function places its result in memory at
7446 the location pointed to by GPR3.
7448 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7449 but a draft put them in memory, and GCC used to implement the draft
7450 instead of the final standard. Therefore, aix_struct_return
7451 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7452 compatibility can change DRAFT_V4_STRUCT_RET to override the
7453 default, and -m switches get the final word. See
7454 rs6000_option_override_internal for more details.
7456 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7457 long double support is enabled. These values are returned in memory.
7459 int_size_in_bytes returns -1 for variable size objects, which go in
7460 memory always. The cast to unsigned makes -1 > 8. */
7463 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7465 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7467 && rs6000_darwin64_abi
7468 && TREE_CODE (type
) == RECORD_TYPE
7469 && int_size_in_bytes (type
) > 0)
7471 CUMULATIVE_ARGS valcum
;
7475 valcum
.fregno
= FP_ARG_MIN_REG
;
7476 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
7477 /* Do a trial code generation as if this were going to be passed
7478 as an argument; if any part goes in memory, we return NULL. */
7479 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
7482 /* Otherwise fall through to more conventional ABI rules. */
7485 if (AGGREGATE_TYPE_P (type
)
7486 && (aix_struct_return
7487 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
7490 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7491 modes only exist for GCC vector types if -maltivec. */
7492 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
7493 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
7496 /* Return synthetic vectors in memory. */
7497 if (TREE_CODE (type
) == VECTOR_TYPE
7498 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
7500 static bool warned_for_return_big_vectors
= false;
7501 if (!warned_for_return_big_vectors
)
7503 warning (0, "GCC vector returned by reference: "
7504 "non-standard ABI extension with no compatibility guarantee");
7505 warned_for_return_big_vectors
= true;
7510 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
7516 #ifdef HAVE_AS_GNU_ATTRIBUTE
7517 /* Return TRUE if a call to function FNDECL may be one that
7518 potentially affects the function calling ABI of the object file. */
7521 call_ABI_of_interest (tree fndecl
)
7523 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
7525 struct cgraph_node
*c_node
;
7527 /* Libcalls are always interesting. */
7528 if (fndecl
== NULL_TREE
)
7531 /* Any call to an external function is interesting. */
7532 if (DECL_EXTERNAL (fndecl
))
7535 /* Interesting functions that we are emitting in this object file. */
7536 c_node
= cgraph_get_node (fndecl
);
7537 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
7538 return !cgraph_only_called_directly_p (c_node
);
7544 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7545 for a call to a function whose data type is FNTYPE.
7546 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7548 For incoming args we set the number of arguments in the prototype large
7549 so we never return a PARALLEL. */
7552 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
7553 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
7554 int libcall
, int n_named_args
,
7555 tree fndecl ATTRIBUTE_UNUSED
,
7556 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
7558 static CUMULATIVE_ARGS zero_cumulative
;
7560 *cum
= zero_cumulative
;
7562 cum
->fregno
= FP_ARG_MIN_REG
;
7563 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
7564 cum
->prototype
= (fntype
&& prototype_p (fntype
));
7565 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
7566 ? CALL_LIBCALL
: CALL_NORMAL
);
7567 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
7568 cum
->stdarg
= stdarg_p (fntype
);
7570 cum
->nargs_prototype
= 0;
7571 if (incoming
|| cum
->prototype
)
7572 cum
->nargs_prototype
= n_named_args
;
7574 /* Check for a longcall attribute. */
7575 if ((!fntype
&& rs6000_default_long_calls
)
7577 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
7578 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
7579 cum
->call_cookie
|= CALL_LONG
;
7581 if (TARGET_DEBUG_ARG
)
7583 fprintf (stderr
, "\ninit_cumulative_args:");
7586 tree ret_type
= TREE_TYPE (fntype
);
7587 fprintf (stderr
, " ret code = %s,",
7588 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
7591 if (cum
->call_cookie
& CALL_LONG
)
7592 fprintf (stderr
, " longcall,");
7594 fprintf (stderr
, " proto = %d, nargs = %d\n",
7595 cum
->prototype
, cum
->nargs_prototype
);
7598 #ifdef HAVE_AS_GNU_ATTRIBUTE
7599 if (DEFAULT_ABI
== ABI_V4
)
7601 cum
->escapes
= call_ABI_of_interest (fndecl
);
7608 return_type
= TREE_TYPE (fntype
);
7609 return_mode
= TYPE_MODE (return_type
);
7612 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
7614 if (return_type
!= NULL
)
7616 if (TREE_CODE (return_type
) == RECORD_TYPE
7617 && TYPE_TRANSPARENT_AGGR (return_type
))
7619 return_type
= TREE_TYPE (first_field (return_type
));
7620 return_mode
= TYPE_MODE (return_type
);
7622 if (AGGREGATE_TYPE_P (return_type
)
7623 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
7625 rs6000_returns_struct
= true;
7627 if (SCALAR_FLOAT_MODE_P (return_mode
))
7628 rs6000_passes_float
= true;
7629 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
7630 || SPE_VECTOR_MODE (return_mode
))
7631 rs6000_passes_vector
= true;
7638 && TARGET_ALTIVEC_ABI
7639 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
7641 error ("cannot return value in vector register because"
7642 " altivec instructions are disabled, use -maltivec"
7647 /* Return true if TYPE must be passed on the stack and not in registers. */
7650 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
7652 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
7653 return must_pass_in_stack_var_size (mode
, type
);
7655 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7658 /* If defined, a C expression which determines whether, and in which
7659 direction, to pad out an argument with extra space. The value
7660 should be of type `enum direction': either `upward' to pad above
7661 the argument, `downward' to pad below, or `none' to inhibit
7664 For the AIX ABI structs are always stored left shifted in their
7668 function_arg_padding (enum machine_mode mode
, const_tree type
)
7670 #ifndef AGGREGATE_PADDING_FIXED
7671 #define AGGREGATE_PADDING_FIXED 0
7673 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7674 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7677 if (!AGGREGATE_PADDING_FIXED
)
7679 /* GCC used to pass structures of the same size as integer types as
7680 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7681 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7682 passed padded downward, except that -mstrict-align further
7683 muddied the water in that multi-component structures of 2 and 4
7684 bytes in size were passed padded upward.
7686 The following arranges for best compatibility with previous
7687 versions of gcc, but removes the -mstrict-align dependency. */
7688 if (BYTES_BIG_ENDIAN
)
7690 HOST_WIDE_INT size
= 0;
7692 if (mode
== BLKmode
)
7694 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
7695 size
= int_size_in_bytes (type
);
7698 size
= GET_MODE_SIZE (mode
);
7700 if (size
== 1 || size
== 2 || size
== 4)
7706 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
7708 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
7712 /* Fall back to the default. */
7713 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7716 /* If defined, a C expression that gives the alignment boundary, in bits,
7717 of an argument with the specified mode and type. If it is not defined,
7718 PARM_BOUNDARY is used for all arguments.
7720 V.4 wants long longs and doubles to be double word aligned. Just
7721 testing the mode size is a boneheaded way to do this as it means
7722 that other types such as complex int are also double word aligned.
7723 However, we're stuck with this because changing the ABI might break
7724 existing library interfaces.
7726 Doubleword align SPE vectors.
7727 Quadword align Altivec/VSX vectors.
7728 Quadword align large synthetic vector types. */
7731 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
7733 if (DEFAULT_ABI
== ABI_V4
7734 && (GET_MODE_SIZE (mode
) == 8
7735 || (TARGET_HARD_FLOAT
7737 && (mode
== TFmode
|| mode
== TDmode
))))
7739 else if (SPE_VECTOR_MODE (mode
)
7740 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7741 && int_size_in_bytes (type
) >= 8
7742 && int_size_in_bytes (type
) < 16))
7744 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7745 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7746 && int_size_in_bytes (type
) >= 16))
7748 else if (TARGET_MACHO
7749 && rs6000_darwin64_abi
7751 && type
&& TYPE_ALIGN (type
) > 64)
7754 return PARM_BOUNDARY
;
7757 /* For a function parm of MODE and TYPE, return the starting word in
7758 the parameter area. NWORDS of the parameter area are already used. */
7761 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
7762 unsigned int nwords
)
7765 unsigned int parm_offset
;
7767 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
7768 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
7769 return nwords
+ (-(parm_offset
+ nwords
) & align
);
7772 /* Compute the size (in words) of a function argument. */
7774 static unsigned long
7775 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
7779 if (mode
!= BLKmode
)
7780 size
= GET_MODE_SIZE (mode
);
7782 size
= int_size_in_bytes (type
);
7785 return (size
+ 3) >> 2;
7787 return (size
+ 7) >> 3;
7790 /* Use this to flush pending int fields. */
7793 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
7794 HOST_WIDE_INT bitpos
, int final
)
7796 unsigned int startbit
, endbit
;
7797 int intregs
, intoffset
;
7798 enum machine_mode mode
;
7800 /* Handle the situations where a float is taking up the first half
7801 of the GPR, and the other half is empty (typically due to
7802 alignment restrictions). We can detect this by a 8-byte-aligned
7803 int field, or by seeing that this is the final flush for this
7804 argument. Count the word and continue on. */
7805 if (cum
->floats_in_gpr
== 1
7806 && (cum
->intoffset
% 64 == 0
7807 || (cum
->intoffset
== -1 && final
)))
7810 cum
->floats_in_gpr
= 0;
7813 if (cum
->intoffset
== -1)
7816 intoffset
= cum
->intoffset
;
7817 cum
->intoffset
= -1;
7818 cum
->floats_in_gpr
= 0;
7820 if (intoffset
% BITS_PER_WORD
!= 0)
7822 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
7824 if (mode
== BLKmode
)
7826 /* We couldn't find an appropriate mode, which happens,
7827 e.g., in packed structs when there are 3 bytes to load.
7828 Back intoffset back to the beginning of the word in this
7830 intoffset
= intoffset
& -BITS_PER_WORD
;
7834 startbit
= intoffset
& -BITS_PER_WORD
;
7835 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
7836 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
7837 cum
->words
+= intregs
;
7838 /* words should be unsigned. */
7839 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
7841 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
7846 /* The darwin64 ABI calls for us to recurse down through structs,
7847 looking for elements passed in registers. Unfortunately, we have
7848 to track int register count here also because of misalignments
7849 in powerpc alignment mode. */
7852 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
7854 HOST_WIDE_INT startbitpos
)
7858 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
7859 if (TREE_CODE (f
) == FIELD_DECL
)
7861 HOST_WIDE_INT bitpos
= startbitpos
;
7862 tree ftype
= TREE_TYPE (f
);
7863 enum machine_mode mode
;
7864 if (ftype
== error_mark_node
)
7866 mode
= TYPE_MODE (ftype
);
7868 if (DECL_SIZE (f
) != 0
7869 && host_integerp (bit_position (f
), 1))
7870 bitpos
+= int_bit_position (f
);
7872 /* ??? FIXME: else assume zero offset. */
7874 if (TREE_CODE (ftype
) == RECORD_TYPE
)
7875 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
7876 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
7878 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
7879 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
7880 cum
->fregno
+= n_fpregs
;
7881 /* Single-precision floats present a special problem for
7882 us, because they are smaller than an 8-byte GPR, and so
7883 the structure-packing rules combined with the standard
7884 varargs behavior mean that we want to pack float/float
7885 and float/int combinations into a single register's
7886 space. This is complicated by the arg advance flushing,
7887 which works on arbitrarily large groups of int-type
7891 if (cum
->floats_in_gpr
== 1)
7893 /* Two floats in a word; count the word and reset
7896 cum
->floats_in_gpr
= 0;
7898 else if (bitpos
% 64 == 0)
7900 /* A float at the beginning of an 8-byte word;
7901 count it and put off adjusting cum->words until
7902 we see if a arg advance flush is going to do it
7904 cum
->floats_in_gpr
++;
7908 /* The float is at the end of a word, preceded
7909 by integer fields, so the arg advance flush
7910 just above has already set cum->words and
7911 everything is taken care of. */
7915 cum
->words
+= n_fpregs
;
7917 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
7919 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
7923 else if (cum
->intoffset
== -1)
7924 cum
->intoffset
= bitpos
;
7928 /* Check for an item that needs to be considered specially under the darwin 64
7929 bit ABI. These are record types where the mode is BLK or the structure is
7932 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
7934 return rs6000_darwin64_abi
7935 && ((mode
== BLKmode
7936 && TREE_CODE (type
) == RECORD_TYPE
7937 && int_size_in_bytes (type
) > 0)
7938 || (type
&& TREE_CODE (type
) == RECORD_TYPE
7939 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
7942 /* Update the data in CUM to advance over an argument
7943 of mode MODE and data type TYPE.
7944 (TYPE is null for libcalls where that information may not be available.)
7946 Note that for args passed by reference, function_arg will be called
7947 with MODE and TYPE set to that of the pointer to the arg, not the arg
7951 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
7952 const_tree type
, bool named
, int depth
)
7954 /* Only tick off an argument if we're not recursing. */
7956 cum
->nargs_prototype
--;
7958 #ifdef HAVE_AS_GNU_ATTRIBUTE
7959 if (DEFAULT_ABI
== ABI_V4
7962 if (SCALAR_FLOAT_MODE_P (mode
))
7963 rs6000_passes_float
= true;
7964 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
7965 rs6000_passes_vector
= true;
7966 else if (SPE_VECTOR_MODE (mode
)
7968 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
7969 rs6000_passes_vector
= true;
7973 if (TARGET_ALTIVEC_ABI
7974 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7975 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7976 && int_size_in_bytes (type
) == 16)))
7980 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
7983 if (!TARGET_ALTIVEC
)
7984 error ("cannot pass argument in vector register because"
7985 " altivec instructions are disabled, use -maltivec"
7988 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7989 even if it is going to be passed in a vector register.
7990 Darwin does the same for variable-argument functions. */
7991 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
7992 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
8002 /* Vector parameters must be 16-byte aligned. This places
8003 them at 2 mod 4 in terms of words in 32-bit mode, since
8004 the parameter save area starts at offset 24 from the
8005 stack. In 64-bit mode, they just have to start on an
8006 even word, since the parameter save area is 16-byte
8007 aligned. Space for GPRs is reserved even if the argument
8008 will be passed in memory. */
8010 align
= (2 - cum
->words
) & 3;
8012 align
= cum
->words
& 1;
8013 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
8015 if (TARGET_DEBUG_ARG
)
8017 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
8019 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
8020 cum
->nargs_prototype
, cum
->prototype
,
8021 GET_MODE_NAME (mode
));
8025 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
8027 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
8030 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8032 int size
= int_size_in_bytes (type
);
8033 /* Variable sized types have size == -1 and are
8034 treated as if consisting entirely of ints.
8035 Pad to 16 byte boundary if needed. */
8036 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8037 && (cum
->words
% 2) != 0)
8039 /* For varargs, we can just go up by the size of the struct. */
8041 cum
->words
+= (size
+ 7) / 8;
8044 /* It is tempting to say int register count just goes up by
8045 sizeof(type)/8, but this is wrong in a case such as
8046 { int; double; int; } [powerpc alignment]. We have to
8047 grovel through the fields for these too. */
8049 cum
->floats_in_gpr
= 0;
8050 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
8051 rs6000_darwin64_record_arg_advance_flush (cum
,
8052 size
* BITS_PER_UNIT
, 1);
8054 if (TARGET_DEBUG_ARG
)
8056 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
8057 cum
->words
, TYPE_ALIGN (type
), size
);
8059 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
8060 cum
->nargs_prototype
, cum
->prototype
,
8061 GET_MODE_NAME (mode
));
8064 else if (DEFAULT_ABI
== ABI_V4
)
8066 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8067 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8068 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8069 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8070 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8072 /* _Decimal128 must use an even/odd register pair. This assumes
8073 that the register number is odd when fregno is odd. */
8074 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8077 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8078 <= FP_ARG_V4_MAX_REG
)
8079 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8082 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
8083 if (mode
== DFmode
|| mode
== TFmode
8084 || mode
== DDmode
|| mode
== TDmode
)
8085 cum
->words
+= cum
->words
& 1;
8086 cum
->words
+= rs6000_arg_size (mode
, type
);
8091 int n_words
= rs6000_arg_size (mode
, type
);
8092 int gregno
= cum
->sysv_gregno
;
8094 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8095 (r7,r8) or (r9,r10). As does any other 2 word item such
8096 as complex int due to a historical mistake. */
8098 gregno
+= (1 - gregno
) & 1;
8100 /* Multi-reg args are not split between registers and stack. */
8101 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8103 /* Long long and SPE vectors are aligned on the stack.
8104 So are other 2 word items such as complex int due to
8105 a historical mistake. */
8107 cum
->words
+= cum
->words
& 1;
8108 cum
->words
+= n_words
;
8111 /* Note: continuing to accumulate gregno past when we've started
8112 spilling to the stack indicates the fact that we've started
8113 spilling to the stack to expand_builtin_saveregs. */
8114 cum
->sysv_gregno
= gregno
+ n_words
;
8117 if (TARGET_DEBUG_ARG
)
8119 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8120 cum
->words
, cum
->fregno
);
8121 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
8122 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
8123 fprintf (stderr
, "mode = %4s, named = %d\n",
8124 GET_MODE_NAME (mode
), named
);
8129 int n_words
= rs6000_arg_size (mode
, type
);
8130 int start_words
= cum
->words
;
8131 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
8133 cum
->words
= align_words
+ n_words
;
8135 if (SCALAR_FLOAT_MODE_P (mode
)
8136 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8138 /* _Decimal128 must be passed in an even/odd float register pair.
8139 This assumes that the register number is odd when fregno is
8141 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8143 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8146 if (TARGET_DEBUG_ARG
)
8148 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8149 cum
->words
, cum
->fregno
);
8150 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
8151 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
8152 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
8153 named
, align_words
- start_words
, depth
);
8159 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
8160 const_tree type
, bool named
)
8162 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
8167 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
8174 r1
= gen_rtx_REG (DImode
, gregno
);
8175 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8176 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
8180 r1
= gen_rtx_REG (DImode
, gregno
);
8181 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8182 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8183 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8184 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
8187 r1
= gen_rtx_REG (DImode
, gregno
);
8188 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8189 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8190 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8191 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
8192 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
8193 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
8194 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
8195 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
8202 /* Determine where to put a SIMD argument on the SPE. */
8204 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8207 int gregno
= cum
->sysv_gregno
;
8209 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8210 are passed and returned in a pair of GPRs for ABI compatibility. */
8211 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
8212 || mode
== DCmode
|| mode
== TCmode
))
8214 int n_words
= rs6000_arg_size (mode
, type
);
8216 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8218 gregno
+= (1 - gregno
) & 1;
8220 /* Multi-reg args are not split between registers and stack. */
8221 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8224 return spe_build_register_parallel (mode
, gregno
);
8228 int n_words
= rs6000_arg_size (mode
, type
);
8230 /* SPE vectors are put in odd registers. */
8231 if (n_words
== 2 && (gregno
& 1) == 0)
8234 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
8237 enum machine_mode m
= SImode
;
8239 r1
= gen_rtx_REG (m
, gregno
);
8240 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
8241 r2
= gen_rtx_REG (m
, gregno
+ 1);
8242 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
8243 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
8250 if (gregno
<= GP_ARG_MAX_REG
)
8251 return gen_rtx_REG (mode
, gregno
);
8257 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8258 structure between cum->intoffset and bitpos to integer registers. */
8261 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
8262 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
8264 enum machine_mode mode
;
8266 unsigned int startbit
, endbit
;
8267 int this_regno
, intregs
, intoffset
;
8270 if (cum
->intoffset
== -1)
8273 intoffset
= cum
->intoffset
;
8274 cum
->intoffset
= -1;
8276 /* If this is the trailing part of a word, try to only load that
8277 much into the register. Otherwise load the whole register. Note
8278 that in the latter case we may pick up unwanted bits. It's not a
8279 problem at the moment but may wish to revisit. */
8281 if (intoffset
% BITS_PER_WORD
!= 0)
8283 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8285 if (mode
== BLKmode
)
8287 /* We couldn't find an appropriate mode, which happens,
8288 e.g., in packed structs when there are 3 bytes to load.
8289 Back intoffset back to the beginning of the word in this
8291 intoffset
= intoffset
& -BITS_PER_WORD
;
8298 startbit
= intoffset
& -BITS_PER_WORD
;
8299 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8300 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8301 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
8303 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
8306 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
8310 intoffset
/= BITS_PER_UNIT
;
8313 regno
= GP_ARG_MIN_REG
+ this_regno
;
8314 reg
= gen_rtx_REG (mode
, regno
);
8316 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
8319 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
8323 while (intregs
> 0);
8326 /* Recursive workhorse for the following. */
8329 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
8330 HOST_WIDE_INT startbitpos
, rtx rvec
[],
8335 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8336 if (TREE_CODE (f
) == FIELD_DECL
)
8338 HOST_WIDE_INT bitpos
= startbitpos
;
8339 tree ftype
= TREE_TYPE (f
);
8340 enum machine_mode mode
;
8341 if (ftype
== error_mark_node
)
8343 mode
= TYPE_MODE (ftype
);
8345 if (DECL_SIZE (f
) != 0
8346 && host_integerp (bit_position (f
), 1))
8347 bitpos
+= int_bit_position (f
);
8349 /* ??? FIXME: else assume zero offset. */
8351 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8352 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
8353 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8355 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8359 case SCmode
: mode
= SFmode
; break;
8360 case DCmode
: mode
= DFmode
; break;
8361 case TCmode
: mode
= TFmode
; break;
8365 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8366 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8368 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8369 && (mode
== TFmode
|| mode
== TDmode
));
8370 /* Long double or _Decimal128 split over regs and memory. */
8371 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
8375 = gen_rtx_EXPR_LIST (VOIDmode
,
8376 gen_rtx_REG (mode
, cum
->fregno
++),
8377 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8378 if (mode
== TFmode
|| mode
== TDmode
)
8381 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
8383 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8385 = gen_rtx_EXPR_LIST (VOIDmode
,
8386 gen_rtx_REG (mode
, cum
->vregno
++),
8387 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8389 else if (cum
->intoffset
== -1)
8390 cum
->intoffset
= bitpos
;
8394 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8395 the register(s) to be used for each field and subfield of a struct
8396 being passed by value, along with the offset of where the
8397 register's value may be found in the block. FP fields go in FP
8398 register, vector fields go in vector registers, and everything
8399 else goes in int registers, packed as in memory.
8401 This code is also used for function return values. RETVAL indicates
8402 whether this is the case.
8404 Much of this is taken from the SPARC V9 port, which has a similar
8405 calling convention. */
8408 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
8409 bool named
, bool retval
)
8411 rtx rvec
[FIRST_PSEUDO_REGISTER
];
8412 int k
= 1, kbase
= 1;
8413 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
8414 /* This is a copy; modifications are not visible to our caller. */
8415 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
8416 CUMULATIVE_ARGS
*cum
= ©_cum
;
8418 /* Pad to 16 byte boundary if needed. */
8419 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8420 && (cum
->words
% 2) != 0)
8427 /* Put entries into rvec[] for individual FP and vector fields, and
8428 for the chunks of memory that go in int regs. Note we start at
8429 element 1; 0 is reserved for an indication of using memory, and
8430 may or may not be filled in below. */
8431 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
8432 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
8434 /* If any part of the struct went on the stack put all of it there.
8435 This hack is because the generic code for
8436 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8437 parts of the struct are not at the beginning. */
8441 return NULL_RTX
; /* doesn't go in registers at all */
8443 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8445 if (k
> 1 || cum
->use_stack
)
8446 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
8451 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8454 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
8459 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8461 if (align_words
>= GP_ARG_NUM_REG
)
8464 n_units
= rs6000_arg_size (mode
, type
);
8466 /* Optimize the simple case where the arg fits in one gpr, except in
8467 the case of BLKmode due to assign_parms assuming that registers are
8468 BITS_PER_WORD wide. */
8470 || (n_units
== 1 && mode
!= BLKmode
))
8471 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8474 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
8475 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8476 using a magic NULL_RTX component.
8477 This is not strictly correct. Only some of the arg belongs in
8478 memory, not all of it. However, the normal scheme using
8479 function_arg_partial_nregs can result in unusual subregs, eg.
8480 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8481 store the whole arg to memory is often more efficient than code
8482 to store pieces, and we know that space is available in the right
8483 place for the whole arg. */
8484 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8489 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
8490 rtx off
= GEN_INT (i
++ * 4);
8491 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
8493 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
8495 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
8498 /* Determine where to put an argument to a function.
8499 Value is zero to push the argument on the stack,
8500 or a hard register in which to store the argument.
8502 MODE is the argument's machine mode.
8503 TYPE is the data type of the argument (as a tree).
8504 This is null for libcalls where that information may
8506 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8507 the preceding args and about the function being called. It is
8508 not modified in this routine.
8509 NAMED is nonzero if this argument is a named parameter
8510 (otherwise it is an extra parameter matching an ellipsis).
8512 On RS/6000 the first eight words of non-FP are normally in registers
8513 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8514 Under V.4, the first 8 FP args are in registers.
8516 If this is floating-point and no prototype is specified, we use
8517 both an FP and integer register (or possibly FP reg and stack). Library
8518 functions (when CALL_LIBCALL is set) always have the proper types for args,
8519 so we can pass the FP value just in one register. emit_library_function
8520 doesn't support PARALLEL anyway.
8522 Note that for args passed by reference, function_arg will be called
8523 with MODE and TYPE set to that of the pointer to the arg, not the arg
8527 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
8528 const_tree type
, bool named
)
8530 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8531 enum rs6000_abi abi
= DEFAULT_ABI
;
8533 /* Return a marker to indicate whether CR1 needs to set or clear the
8534 bit that V.4 uses to say fp args were passed in registers.
8535 Assume that we don't need the marker for software floating point,
8536 or compiler generated library calls. */
8537 if (mode
== VOIDmode
)
8540 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
8542 || (cum
->nargs_prototype
< 0
8543 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
8545 /* For the SPE, we need to crxor CR6 always. */
8547 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
8548 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8549 return GEN_INT (cum
->call_cookie
8550 | ((cum
->fregno
== FP_ARG_MIN_REG
)
8551 ? CALL_V4_SET_FP_ARGS
8552 : CALL_V4_CLEAR_FP_ARGS
));
8555 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
8558 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8560 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
8561 if (rslt
!= NULL_RTX
)
8563 /* Else fall through to usual handling. */
8566 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
8567 if (TARGET_64BIT
&& ! cum
->prototype
)
8569 /* Vector parameters get passed in vector register
8570 and also in GPRs or memory, in absence of prototype. */
8573 align_words
= (cum
->words
+ 1) & ~1;
8575 if (align_words
>= GP_ARG_NUM_REG
)
8581 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8583 return gen_rtx_PARALLEL (mode
,
8585 gen_rtx_EXPR_LIST (VOIDmode
,
8587 gen_rtx_EXPR_LIST (VOIDmode
,
8588 gen_rtx_REG (mode
, cum
->vregno
),
8592 return gen_rtx_REG (mode
, cum
->vregno
);
8593 else if (TARGET_ALTIVEC_ABI
8594 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8595 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8596 && int_size_in_bytes (type
) == 16)))
8598 if (named
|| abi
== ABI_V4
)
8602 /* Vector parameters to varargs functions under AIX or Darwin
8603 get passed in memory and possibly also in GPRs. */
8604 int align
, align_words
, n_words
;
8605 enum machine_mode part_mode
;
8607 /* Vector parameters must be 16-byte aligned. This places them at
8608 2 mod 4 in terms of words in 32-bit mode, since the parameter
8609 save area starts at offset 24 from the stack. In 64-bit mode,
8610 they just have to start on an even word, since the parameter
8611 save area is 16-byte aligned. */
8613 align
= (2 - cum
->words
) & 3;
8615 align
= cum
->words
& 1;
8616 align_words
= cum
->words
+ align
;
8618 /* Out of registers? Memory, then. */
8619 if (align_words
>= GP_ARG_NUM_REG
)
8622 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8623 return rs6000_mixed_function_arg (mode
, type
, align_words
);
8625 /* The vector value goes in GPRs. Only the part of the
8626 value in GPRs is reported here. */
8628 n_words
= rs6000_arg_size (mode
, type
);
8629 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
8630 /* Fortunately, there are only two possibilities, the value
8631 is either wholly in GPRs or half in GPRs and half not. */
8634 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
8637 else if (TARGET_SPE_ABI
&& TARGET_SPE
8638 && (SPE_VECTOR_MODE (mode
)
8639 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
8642 || mode
== TCmode
))))
8643 return rs6000_spe_function_arg (cum
, mode
, type
);
8645 else if (abi
== ABI_V4
)
8647 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8648 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8649 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8650 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8651 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8653 /* _Decimal128 must use an even/odd register pair. This assumes
8654 that the register number is odd when fregno is odd. */
8655 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8658 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8659 <= FP_ARG_V4_MAX_REG
)
8660 return gen_rtx_REG (mode
, cum
->fregno
);
8666 int n_words
= rs6000_arg_size (mode
, type
);
8667 int gregno
= cum
->sysv_gregno
;
8669 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8670 (r7,r8) or (r9,r10). As does any other 2 word item such
8671 as complex int due to a historical mistake. */
8673 gregno
+= (1 - gregno
) & 1;
8675 /* Multi-reg args are not split between registers and stack. */
8676 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8679 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8680 return rs6000_mixed_function_arg (mode
, type
,
8681 gregno
- GP_ARG_MIN_REG
);
8682 return gen_rtx_REG (mode
, gregno
);
8687 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
8689 /* _Decimal128 must be passed in an even/odd float register pair.
8690 This assumes that the register number is odd when fregno is odd. */
8691 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8694 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
8696 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8700 enum machine_mode fmode
= mode
;
8701 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8703 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8705 /* Currently, we only ever need one reg here because complex
8706 doubles are split. */
8707 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8708 && (fmode
== TFmode
|| fmode
== TDmode
));
8710 /* Long double or _Decimal128 split over regs and memory. */
8711 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
8714 /* Do we also need to pass this arg in the parameter save
8717 && (cum
->nargs_prototype
<= 0
8718 || (DEFAULT_ABI
== ABI_AIX
8720 && align_words
>= GP_ARG_NUM_REG
)));
8722 if (!needs_psave
&& mode
== fmode
)
8723 return gen_rtx_REG (fmode
, cum
->fregno
);
8728 /* Describe the part that goes in gprs or the stack.
8729 This piece must come first, before the fprs. */
8730 if (align_words
< GP_ARG_NUM_REG
)
8732 unsigned long n_words
= rs6000_arg_size (mode
, type
);
8734 if (align_words
+ n_words
> GP_ARG_NUM_REG
8735 || (TARGET_32BIT
&& TARGET_POWERPC64
))
8737 /* If this is partially on the stack, then we only
8738 include the portion actually in registers here. */
8739 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
8742 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
8743 /* Not all of the arg fits in gprs. Say that it
8744 goes in memory too, using a magic NULL_RTX
8745 component. Also see comment in
8746 rs6000_mixed_function_arg for why the normal
8747 function_arg_partial_nregs scheme doesn't work
8749 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
8753 r
= gen_rtx_REG (rmode
,
8754 GP_ARG_MIN_REG
+ align_words
);
8755 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
8756 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
8758 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
8762 /* The whole arg fits in gprs. */
8763 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8764 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
8768 /* It's entirely in memory. */
8769 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8772 /* Describe where this piece goes in the fprs. */
8773 r
= gen_rtx_REG (fmode
, cum
->fregno
);
8774 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
8776 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
8778 else if (align_words
< GP_ARG_NUM_REG
)
8780 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8781 return rs6000_mixed_function_arg (mode
, type
, align_words
);
8783 if (mode
== BLKmode
)
8786 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8793 /* For an arg passed partly in registers and partly in memory, this is
8794 the number of bytes passed in registers. For args passed entirely in
8795 registers or entirely in memory, zero. When an arg is described by a
8796 PARALLEL, perhaps using more than one register type, this function
8797 returns the number of bytes used by the first element of the PARALLEL. */
8800 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
8801 tree type
, bool named
)
8803 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8807 if (DEFAULT_ABI
== ABI_V4
)
8810 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
8811 && cum
->nargs_prototype
>= 0)
8814 /* In this complicated case we just disable the partial_nregs code. */
8815 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8818 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
8820 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
8822 /* If we are passing this arg in the fixed parameter save area
8823 (gprs or memory) as well as fprs, then this function should
8824 return the number of partial bytes passed in the parameter
8825 save area rather than partial bytes passed in fprs. */
8827 && (cum
->nargs_prototype
<= 0
8828 || (DEFAULT_ABI
== ABI_AIX
8830 && align_words
>= GP_ARG_NUM_REG
)))
8832 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
8833 > FP_ARG_MAX_REG
+ 1)
8834 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
8835 else if (cum
->nargs_prototype
>= 0)
8839 if (align_words
< GP_ARG_NUM_REG
8840 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
8841 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
8843 if (ret
!= 0 && TARGET_DEBUG_ARG
)
8844 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
8849 /* A C expression that indicates when an argument must be passed by
8850 reference. If nonzero for an argument, a copy of that argument is
8851 made in memory and a pointer to the argument is passed instead of
8852 the argument itself. The pointer is passed in whatever way is
8853 appropriate for passing a pointer to that type.
8855 Under V.4, aggregates and long double are passed by reference.
8857 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8858 reference unless the AltiVec vector extension ABI is in force.
8860 As an extension to all ABIs, variable sized types are passed by
8864 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
8865 enum machine_mode mode
, const_tree type
,
8866 bool named ATTRIBUTE_UNUSED
)
8868 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
8870 if (TARGET_DEBUG_ARG
)
8871 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
8878 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
8880 if (TARGET_DEBUG_ARG
)
8881 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
8885 if (int_size_in_bytes (type
) < 0)
8887 if (TARGET_DEBUG_ARG
)
8888 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
8892 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8893 modes only exist for GCC vector types if -maltivec. */
8894 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
8896 if (TARGET_DEBUG_ARG
)
8897 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
8901 /* Pass synthetic vectors in memory. */
8902 if (TREE_CODE (type
) == VECTOR_TYPE
8903 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8905 static bool warned_for_pass_big_vectors
= false;
8906 if (TARGET_DEBUG_ARG
)
8907 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
8908 if (!warned_for_pass_big_vectors
)
8910 warning (0, "GCC vector passed by reference: "
8911 "non-standard ABI extension with no compatibility guarantee");
8912 warned_for_pass_big_vectors
= true;
8921 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
8924 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
8929 for (i
= 0; i
< nregs
; i
++)
8931 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
8932 if (reload_completed
)
8934 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
8937 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
8938 i
* GET_MODE_SIZE (reg_mode
));
8941 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
8945 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
8949 /* Perform any needed actions needed for a function that is receiving a
8950 variable number of arguments.
8954 MODE and TYPE are the mode and type of the current parameter.
8956 PRETEND_SIZE is a variable that should be set to the amount of stack
8957 that must be pushed by the prolog to pretend that our caller pushed
8960 Normally, this macro will push all remaining incoming registers on the
8961 stack and set PRETEND_SIZE to the length of the registers pushed. */
8964 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
8965 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
8968 CUMULATIVE_ARGS next_cum
;
8969 int reg_size
= TARGET_32BIT
? 4 : 8;
8970 rtx save_area
= NULL_RTX
, mem
;
8971 int first_reg_offset
;
8974 /* Skip the last named argument. */
8975 next_cum
= *get_cumulative_args (cum
);
8976 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
8978 if (DEFAULT_ABI
== ABI_V4
)
8980 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
8984 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
8985 HOST_WIDE_INT offset
= 0;
8987 /* Try to optimize the size of the varargs save area.
8988 The ABI requires that ap.reg_save_area is doubleword
8989 aligned, but we don't need to allocate space for all
8990 the bytes, only those to which we actually will save
8992 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
8993 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
8994 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8995 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
8996 && cfun
->va_list_fpr_size
)
8999 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
9000 * UNITS_PER_FP_WORD
;
9001 if (cfun
->va_list_fpr_size
9002 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
9003 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
9005 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
9006 * UNITS_PER_FP_WORD
;
9010 offset
= -((first_reg_offset
* reg_size
) & ~7);
9011 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
9013 gpr_reg_num
= cfun
->va_list_gpr_size
;
9014 if (reg_size
== 4 && (first_reg_offset
& 1))
9017 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
9020 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
9022 - (int) (GP_ARG_NUM_REG
* reg_size
);
9024 if (gpr_size
+ fpr_size
)
9027 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
9028 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
9029 reg_save_area
= XEXP (reg_save_area
, 0);
9030 if (GET_CODE (reg_save_area
) == PLUS
)
9032 gcc_assert (XEXP (reg_save_area
, 0)
9033 == virtual_stack_vars_rtx
);
9034 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
9035 offset
+= INTVAL (XEXP (reg_save_area
, 1));
9038 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
9041 cfun
->machine
->varargs_save_offset
= offset
;
9042 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
9047 first_reg_offset
= next_cum
.words
;
9048 save_area
= virtual_incoming_args_rtx
;
9050 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
9051 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
9054 set
= get_varargs_alias_set ();
9055 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
9056 && cfun
->va_list_gpr_size
)
9058 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
9060 if (va_list_gpr_counter_field
)
9062 /* V4 va_list_gpr_size counts number of registers needed. */
9063 if (nregs
> cfun
->va_list_gpr_size
)
9064 nregs
= cfun
->va_list_gpr_size
;
9068 /* char * va_list instead counts number of bytes needed. */
9069 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
9070 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
9073 mem
= gen_rtx_MEM (BLKmode
,
9074 plus_constant (Pmode
, save_area
,
9075 first_reg_offset
* reg_size
));
9076 MEM_NOTRAP_P (mem
) = 1;
9077 set_mem_alias_set (mem
, set
);
9078 set_mem_align (mem
, BITS_PER_WORD
);
9080 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
9084 /* Save FP registers if needed. */
9085 if (DEFAULT_ABI
== ABI_V4
9086 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9088 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9089 && cfun
->va_list_fpr_size
)
9091 int fregno
= next_cum
.fregno
, nregs
;
9092 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
9093 rtx lab
= gen_label_rtx ();
9094 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
9095 * UNITS_PER_FP_WORD
);
9098 (gen_rtx_SET (VOIDmode
,
9100 gen_rtx_IF_THEN_ELSE (VOIDmode
,
9101 gen_rtx_NE (VOIDmode
, cr1
,
9103 gen_rtx_LABEL_REF (VOIDmode
, lab
),
9107 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
9108 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
9110 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9112 plus_constant (Pmode
, save_area
, off
));
9113 MEM_NOTRAP_P (mem
) = 1;
9114 set_mem_alias_set (mem
, set
);
9115 set_mem_align (mem
, GET_MODE_ALIGNMENT (
9116 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9117 ? DFmode
: SFmode
));
9118 emit_move_insn (mem
, gen_rtx_REG (
9119 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9120 ? DFmode
: SFmode
, fregno
));
9127 /* Create the va_list data type. */
9130 rs6000_build_builtin_va_list (void)
9132 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
9134 /* For AIX, prefer 'char *' because that's what the system
9135 header files like. */
9136 if (DEFAULT_ABI
!= ABI_V4
)
9137 return build_pointer_type (char_type_node
);
9139 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
9140 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
9141 get_identifier ("__va_list_tag"), record
);
9143 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
9144 unsigned_char_type_node
);
9145 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
9146 unsigned_char_type_node
);
9147 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9149 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9150 get_identifier ("reserved"), short_unsigned_type_node
);
9151 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9152 get_identifier ("overflow_arg_area"),
9154 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9155 get_identifier ("reg_save_area"),
9158 va_list_gpr_counter_field
= f_gpr
;
9159 va_list_fpr_counter_field
= f_fpr
;
9161 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9162 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9163 DECL_FIELD_CONTEXT (f_res
) = record
;
9164 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9165 DECL_FIELD_CONTEXT (f_sav
) = record
;
9167 TYPE_STUB_DECL (record
) = type_decl
;
9168 TYPE_NAME (record
) = type_decl
;
9169 TYPE_FIELDS (record
) = f_gpr
;
9170 DECL_CHAIN (f_gpr
) = f_fpr
;
9171 DECL_CHAIN (f_fpr
) = f_res
;
9172 DECL_CHAIN (f_res
) = f_ovf
;
9173 DECL_CHAIN (f_ovf
) = f_sav
;
9175 layout_type (record
);
9177 /* The correct type is an array type of one element. */
9178 return build_array_type (record
, build_index_type (size_zero_node
));
9181 /* Implement va_start. */
9184 rs6000_va_start (tree valist
, rtx nextarg
)
9186 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
9187 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9188 tree gpr
, fpr
, ovf
, sav
, t
;
9190 /* Only SVR4 needs something special. */
9191 if (DEFAULT_ABI
!= ABI_V4
)
9193 std_expand_builtin_va_start (valist
, nextarg
);
9197 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9198 f_fpr
= DECL_CHAIN (f_gpr
);
9199 f_res
= DECL_CHAIN (f_fpr
);
9200 f_ovf
= DECL_CHAIN (f_res
);
9201 f_sav
= DECL_CHAIN (f_ovf
);
9203 valist
= build_simple_mem_ref (valist
);
9204 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9205 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9207 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9209 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9212 /* Count number of gp and fp argument registers used. */
9213 words
= crtl
->args
.info
.words
;
9214 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
9216 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
9219 if (TARGET_DEBUG_ARG
)
9220 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
9221 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
9222 words
, n_gpr
, n_fpr
);
9224 if (cfun
->va_list_gpr_size
)
9226 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9227 build_int_cst (NULL_TREE
, n_gpr
));
9228 TREE_SIDE_EFFECTS (t
) = 1;
9229 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9232 if (cfun
->va_list_fpr_size
)
9234 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9235 build_int_cst (NULL_TREE
, n_fpr
));
9236 TREE_SIDE_EFFECTS (t
) = 1;
9237 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9239 #ifdef HAVE_AS_GNU_ATTRIBUTE
9240 if (call_ABI_of_interest (cfun
->decl
))
9241 rs6000_passes_float
= true;
9245 /* Find the overflow area. */
9246 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9248 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
9249 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9250 TREE_SIDE_EFFECTS (t
) = 1;
9251 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9253 /* If there were no va_arg invocations, don't set up the register
9255 if (!cfun
->va_list_gpr_size
9256 && !cfun
->va_list_fpr_size
9257 && n_gpr
< GP_ARG_NUM_REG
9258 && n_fpr
< FP_ARG_V4_MAX_REG
)
9261 /* Find the register save area. */
9262 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
9263 if (cfun
->machine
->varargs_save_offset
)
9264 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
9265 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9266 TREE_SIDE_EFFECTS (t
) = 1;
9267 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9270 /* Implement va_arg. */
9273 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9276 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9277 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9278 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
9279 tree lab_false
, lab_over
, addr
;
9281 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9285 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9287 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
9288 return build_va_arg_indirect_ref (t
);
9291 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9292 earlier version of gcc, with the property that it always applied alignment
9293 adjustments to the va-args (even for zero-sized types). The cheapest way
9294 to deal with this is to replicate the effect of the part of
9295 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9297 We don't need to check for pass-by-reference because of the test above.
9298 We can return a simplifed answer, since we know there's no offset to add. */
9301 && rs6000_darwin64_abi
9302 && integer_zerop (TYPE_SIZE (type
)))
9304 unsigned HOST_WIDE_INT align
, boundary
;
9305 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
9306 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
9307 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
9308 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
9309 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
9310 boundary
/= BITS_PER_UNIT
;
9311 if (boundary
> align
)
9314 /* This updates arg ptr by the amount that would be necessary
9315 to align the zero-sized (but not zero-alignment) item. */
9316 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9317 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
9318 gimplify_and_add (t
, pre_p
);
9320 t
= fold_convert (sizetype
, valist_tmp
);
9321 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9322 fold_convert (TREE_TYPE (valist
),
9323 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
9324 size_int (-boundary
))));
9325 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
9326 gimplify_and_add (t
, pre_p
);
9328 /* Since it is zero-sized there's no increment for the item itself. */
9329 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
9330 return build_va_arg_indirect_ref (valist_tmp
);
9333 if (DEFAULT_ABI
!= ABI_V4
)
9335 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
9337 tree elem_type
= TREE_TYPE (type
);
9338 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
9339 int elem_size
= GET_MODE_SIZE (elem_mode
);
9341 if (elem_size
< UNITS_PER_WORD
)
9343 tree real_part
, imag_part
;
9344 gimple_seq post
= NULL
;
9346 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9348 /* Copy the value into a temporary, lest the formal temporary
9349 be reused out from under us. */
9350 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
9351 gimple_seq_add_seq (pre_p
, post
);
9353 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9356 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
9360 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
9363 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9364 f_fpr
= DECL_CHAIN (f_gpr
);
9365 f_res
= DECL_CHAIN (f_fpr
);
9366 f_ovf
= DECL_CHAIN (f_res
);
9367 f_sav
= DECL_CHAIN (f_ovf
);
9369 valist
= build_va_arg_indirect_ref (valist
);
9370 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9371 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9373 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9375 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9378 size
= int_size_in_bytes (type
);
9379 rsize
= (size
+ 3) / 4;
9382 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9383 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
9384 || (TARGET_DOUBLE_FLOAT
9385 && (TYPE_MODE (type
) == DFmode
9386 || TYPE_MODE (type
) == TFmode
9387 || TYPE_MODE (type
) == SDmode
9388 || TYPE_MODE (type
) == DDmode
9389 || TYPE_MODE (type
) == TDmode
))))
9391 /* FP args go in FP registers, if present. */
9393 n_reg
= (size
+ 7) / 8;
9394 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
9395 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
9396 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
9401 /* Otherwise into GP registers. */
9410 /* Pull the value out of the saved registers.... */
9413 addr
= create_tmp_var (ptr_type_node
, "addr");
9415 /* AltiVec vectors never go in registers when -mabi=altivec. */
9416 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9420 lab_false
= create_artificial_label (input_location
);
9421 lab_over
= create_artificial_label (input_location
);
9423 /* Long long and SPE vectors are aligned in the registers.
9424 As are any other 2 gpr item such as complex int due to a
9425 historical mistake. */
9427 if (n_reg
== 2 && reg
== gpr
)
9430 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9431 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
9432 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
9433 unshare_expr (reg
), u
);
9435 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9436 reg number is 0 for f1, so we want to make it odd. */
9437 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
9439 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9440 build_int_cst (TREE_TYPE (reg
), 1));
9441 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
9444 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
9445 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
9446 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9447 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9448 gimplify_and_add (t
, pre_p
);
9452 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9454 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9455 build_int_cst (TREE_TYPE (reg
), n_reg
));
9456 u
= fold_convert (sizetype
, u
);
9457 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
9458 t
= fold_build_pointer_plus (t
, u
);
9460 /* _Decimal32 varargs are located in the second word of the 64-bit
9461 FP register for 32-bit binaries. */
9462 if (!TARGET_POWERPC64
9463 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9464 && TYPE_MODE (type
) == SDmode
)
9465 t
= fold_build_pointer_plus_hwi (t
, size
);
9467 gimplify_assign (addr
, t
, pre_p
);
9469 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9471 stmt
= gimple_build_label (lab_false
);
9472 gimple_seq_add_stmt (pre_p
, stmt
);
9474 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
9476 /* Ensure that we don't find any more args in regs.
9477 Alignment has taken care of for special cases. */
9478 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
9482 /* ... otherwise out of the overflow area. */
9484 /* Care for on-stack alignment if needed. */
9488 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
9489 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
9490 build_int_cst (TREE_TYPE (t
), -align
));
9492 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9494 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
9496 t
= fold_build_pointer_plus_hwi (t
, size
);
9497 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
9501 stmt
= gimple_build_label (lab_over
);
9502 gimple_seq_add_stmt (pre_p
, stmt
);
9505 if (STRICT_ALIGNMENT
9506 && (TYPE_ALIGN (type
)
9507 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
9509 /* The value (of type complex double, for example) may not be
9510 aligned in memory in the saved registers, so copy via a
9511 temporary. (This is the same code as used for SPARC.) */
9512 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
9513 tree dest_addr
= build_fold_addr_expr (tmp
);
9515 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
9516 3, dest_addr
, addr
, size_int (rsize
* 4));
9518 gimplify_and_add (copy
, pre_p
);
9522 addr
= fold_convert (ptrtype
, addr
);
9523 return build_va_arg_indirect_ref (addr
);
9529 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
9532 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
9533 const char *attr_string
= "";
9535 gcc_assert (name
!= NULL
);
9536 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
9538 if (rs6000_builtin_decls
[(int)code
])
9539 fatal_error ("internal error: builtin function %s already processed", name
);
9541 rs6000_builtin_decls
[(int)code
] = t
=
9542 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
9544 /* Set any special attributes. */
9545 if ((classify
& RS6000_BTC_CONST
) != 0)
9547 /* const function, function only depends on the inputs. */
9548 TREE_READONLY (t
) = 1;
9549 TREE_NOTHROW (t
) = 1;
9550 attr_string
= ", pure";
9552 else if ((classify
& RS6000_BTC_PURE
) != 0)
9554 /* pure function, function can read global memory, but does not set any
9556 DECL_PURE_P (t
) = 1;
9557 TREE_NOTHROW (t
) = 1;
9558 attr_string
= ", const";
9560 else if ((classify
& RS6000_BTC_FP
) != 0)
9562 /* Function is a math function. If rounding mode is on, then treat the
9563 function as not reading global memory, but it can have arbitrary side
9564 effects. If it is off, then assume the function is a const function.
9565 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9566 builtin-attribute.def that is used for the math functions. */
9567 TREE_NOTHROW (t
) = 1;
9568 if (flag_rounding_math
)
9570 DECL_PURE_P (t
) = 1;
9571 DECL_IS_NOVOPS (t
) = 1;
9572 attr_string
= ", fp, pure";
9576 TREE_READONLY (t
) = 1;
9577 attr_string
= ", fp, const";
9580 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
9583 if (TARGET_DEBUG_BUILTIN
)
9584 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
9585 (int)code
, name
, attr_string
);
9588 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9590 #undef RS6000_BUILTIN_1
9591 #undef RS6000_BUILTIN_2
9592 #undef RS6000_BUILTIN_3
9593 #undef RS6000_BUILTIN_A
9594 #undef RS6000_BUILTIN_D
9595 #undef RS6000_BUILTIN_E
9596 #undef RS6000_BUILTIN_P
9597 #undef RS6000_BUILTIN_Q
9598 #undef RS6000_BUILTIN_S
9599 #undef RS6000_BUILTIN_X
9601 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9602 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9603 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9604 { MASK, ICODE, NAME, ENUM },
9606 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9607 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9608 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9609 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9610 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9611 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9612 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9614 static const struct builtin_description bdesc_3arg
[] =
9616 #include "rs6000-builtin.def"
9619 /* DST operations: void foo (void *, const int, const char). */
9621 #undef RS6000_BUILTIN_1
9622 #undef RS6000_BUILTIN_2
9623 #undef RS6000_BUILTIN_3
9624 #undef RS6000_BUILTIN_A
9625 #undef RS6000_BUILTIN_D
9626 #undef RS6000_BUILTIN_E
9627 #undef RS6000_BUILTIN_P
9628 #undef RS6000_BUILTIN_Q
9629 #undef RS6000_BUILTIN_S
9630 #undef RS6000_BUILTIN_X
9632 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9633 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9634 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9635 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9636 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9637 { MASK, ICODE, NAME, ENUM },
9639 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9640 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9641 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9642 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9643 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9645 static const struct builtin_description bdesc_dst
[] =
9647 #include "rs6000-builtin.def"
9650 /* Simple binary operations: VECc = foo (VECa, VECb). */
9652 #undef RS6000_BUILTIN_1
9653 #undef RS6000_BUILTIN_2
9654 #undef RS6000_BUILTIN_3
9655 #undef RS6000_BUILTIN_A
9656 #undef RS6000_BUILTIN_D
9657 #undef RS6000_BUILTIN_E
9658 #undef RS6000_BUILTIN_P
9659 #undef RS6000_BUILTIN_Q
9660 #undef RS6000_BUILTIN_S
9661 #undef RS6000_BUILTIN_X
9663 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9664 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9665 { MASK, ICODE, NAME, ENUM },
9667 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9668 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9669 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9670 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9671 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9672 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9673 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9674 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9676 static const struct builtin_description bdesc_2arg
[] =
9678 #include "rs6000-builtin.def"
9681 #undef RS6000_BUILTIN_1
9682 #undef RS6000_BUILTIN_2
9683 #undef RS6000_BUILTIN_3
9684 #undef RS6000_BUILTIN_A
9685 #undef RS6000_BUILTIN_D
9686 #undef RS6000_BUILTIN_E
9687 #undef RS6000_BUILTIN_P
9688 #undef RS6000_BUILTIN_Q
9689 #undef RS6000_BUILTIN_S
9690 #undef RS6000_BUILTIN_X
9692 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9693 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9694 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9695 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9696 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9697 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9698 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9699 { MASK, ICODE, NAME, ENUM },
9701 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9702 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9703 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9705 /* AltiVec predicates. */
9707 static const struct builtin_description bdesc_altivec_preds
[] =
9709 #include "rs6000-builtin.def"
9712 /* SPE predicates. */
9713 #undef RS6000_BUILTIN_1
9714 #undef RS6000_BUILTIN_2
9715 #undef RS6000_BUILTIN_3
9716 #undef RS6000_BUILTIN_A
9717 #undef RS6000_BUILTIN_D
9718 #undef RS6000_BUILTIN_E
9719 #undef RS6000_BUILTIN_P
9720 #undef RS6000_BUILTIN_Q
9721 #undef RS6000_BUILTIN_S
9722 #undef RS6000_BUILTIN_X
9724 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9725 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9726 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9727 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9728 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9729 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9730 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9731 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9732 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9733 { MASK, ICODE, NAME, ENUM },
9735 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9737 static const struct builtin_description bdesc_spe_predicates
[] =
9739 #include "rs6000-builtin.def"
9742 /* SPE evsel predicates. */
9743 #undef RS6000_BUILTIN_1
9744 #undef RS6000_BUILTIN_2
9745 #undef RS6000_BUILTIN_3
9746 #undef RS6000_BUILTIN_A
9747 #undef RS6000_BUILTIN_D
9748 #undef RS6000_BUILTIN_E
9749 #undef RS6000_BUILTIN_P
9750 #undef RS6000_BUILTIN_Q
9751 #undef RS6000_BUILTIN_S
9752 #undef RS6000_BUILTIN_X
9754 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9755 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9756 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9757 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9758 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9759 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9760 { MASK, ICODE, NAME, ENUM },
9762 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9763 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9764 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9765 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9767 static const struct builtin_description bdesc_spe_evsel
[] =
9769 #include "rs6000-builtin.def"
9772 /* PAIRED predicates. */
9773 #undef RS6000_BUILTIN_1
9774 #undef RS6000_BUILTIN_2
9775 #undef RS6000_BUILTIN_3
9776 #undef RS6000_BUILTIN_A
9777 #undef RS6000_BUILTIN_D
9778 #undef RS6000_BUILTIN_E
9779 #undef RS6000_BUILTIN_P
9780 #undef RS6000_BUILTIN_Q
9781 #undef RS6000_BUILTIN_S
9782 #undef RS6000_BUILTIN_X
9784 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9785 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9786 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9787 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9788 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9789 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9790 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9791 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9792 { MASK, ICODE, NAME, ENUM },
9794 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9795 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9797 static const struct builtin_description bdesc_paired_preds
[] =
9799 #include "rs6000-builtin.def"
9802 /* ABS* operations. */
9804 #undef RS6000_BUILTIN_1
9805 #undef RS6000_BUILTIN_2
9806 #undef RS6000_BUILTIN_3
9807 #undef RS6000_BUILTIN_A
9808 #undef RS6000_BUILTIN_D
9809 #undef RS6000_BUILTIN_E
9810 #undef RS6000_BUILTIN_P
9811 #undef RS6000_BUILTIN_Q
9812 #undef RS6000_BUILTIN_S
9813 #undef RS6000_BUILTIN_X
9815 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9816 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9817 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9818 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9819 { MASK, ICODE, NAME, ENUM },
9821 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9822 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9823 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9824 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9825 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9826 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9828 static const struct builtin_description bdesc_abs
[] =
9830 #include "rs6000-builtin.def"
9833 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9836 #undef RS6000_BUILTIN_1
9837 #undef RS6000_BUILTIN_2
9838 #undef RS6000_BUILTIN_3
9839 #undef RS6000_BUILTIN_A
9840 #undef RS6000_BUILTIN_E
9841 #undef RS6000_BUILTIN_D
9842 #undef RS6000_BUILTIN_P
9843 #undef RS6000_BUILTIN_Q
9844 #undef RS6000_BUILTIN_S
9845 #undef RS6000_BUILTIN_X
9847 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9848 { MASK, ICODE, NAME, ENUM },
9850 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9851 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9852 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9853 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9854 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9855 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9856 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9857 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9858 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9860 static const struct builtin_description bdesc_1arg
[] =
9862 #include "rs6000-builtin.def"
9865 #undef RS6000_BUILTIN_1
9866 #undef RS6000_BUILTIN_2
9867 #undef RS6000_BUILTIN_3
9868 #undef RS6000_BUILTIN_A
9869 #undef RS6000_BUILTIN_D
9870 #undef RS6000_BUILTIN_E
9871 #undef RS6000_BUILTIN_P
9872 #undef RS6000_BUILTIN_Q
9873 #undef RS6000_BUILTIN_S
9874 #undef RS6000_BUILTIN_X
9876 /* Return true if a builtin function is overloaded. */
9878 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
9880 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
9883 /* Expand an expression EXP that calls a builtin without arguments. */
9885 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
9888 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9890 if (icode
== CODE_FOR_nothing
)
9891 /* Builtin not supported on this processor. */
9895 || GET_MODE (target
) != tmode
9896 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9897 target
= gen_reg_rtx (tmode
);
9899 pat
= GEN_FCN (icode
) (target
);
9909 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
9912 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9913 rtx op0
= expand_normal (arg0
);
9914 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9915 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9917 if (icode
== CODE_FOR_nothing
)
9918 /* Builtin not supported on this processor. */
9921 /* If we got invalid arguments bail out before generating bad rtl. */
9922 if (arg0
== error_mark_node
)
9925 if (icode
== CODE_FOR_altivec_vspltisb
9926 || icode
== CODE_FOR_altivec_vspltish
9927 || icode
== CODE_FOR_altivec_vspltisw
9928 || icode
== CODE_FOR_spe_evsplatfi
9929 || icode
== CODE_FOR_spe_evsplati
)
9931 /* Only allow 5-bit *signed* literals. */
9932 if (GET_CODE (op0
) != CONST_INT
9933 || INTVAL (op0
) > 15
9934 || INTVAL (op0
) < -16)
9936 error ("argument 1 must be a 5-bit signed literal");
9942 || GET_MODE (target
) != tmode
9943 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9944 target
= gen_reg_rtx (tmode
);
9946 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9947 op0
= copy_to_mode_reg (mode0
, op0
);
9949 pat
= GEN_FCN (icode
) (target
, op0
);
9958 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
9960 rtx pat
, scratch1
, scratch2
;
9961 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9962 rtx op0
= expand_normal (arg0
);
9963 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9964 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9966 /* If we have invalid arguments, bail out before generating bad rtl. */
9967 if (arg0
== error_mark_node
)
9971 || GET_MODE (target
) != tmode
9972 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9973 target
= gen_reg_rtx (tmode
);
9975 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9976 op0
= copy_to_mode_reg (mode0
, op0
);
9978 scratch1
= gen_reg_rtx (mode0
);
9979 scratch2
= gen_reg_rtx (mode0
);
9981 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
9990 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
9993 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9994 tree arg1
= CALL_EXPR_ARG (exp
, 1);
9995 rtx op0
= expand_normal (arg0
);
9996 rtx op1
= expand_normal (arg1
);
9997 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9998 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9999 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10001 if (icode
== CODE_FOR_nothing
)
10002 /* Builtin not supported on this processor. */
10005 /* If we got invalid arguments bail out before generating bad rtl. */
10006 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10009 if (icode
== CODE_FOR_altivec_vcfux
10010 || icode
== CODE_FOR_altivec_vcfsx
10011 || icode
== CODE_FOR_altivec_vctsxs
10012 || icode
== CODE_FOR_altivec_vctuxs
10013 || icode
== CODE_FOR_altivec_vspltb
10014 || icode
== CODE_FOR_altivec_vsplth
10015 || icode
== CODE_FOR_altivec_vspltw
10016 || icode
== CODE_FOR_spe_evaddiw
10017 || icode
== CODE_FOR_spe_evldd
10018 || icode
== CODE_FOR_spe_evldh
10019 || icode
== CODE_FOR_spe_evldw
10020 || icode
== CODE_FOR_spe_evlhhesplat
10021 || icode
== CODE_FOR_spe_evlhhossplat
10022 || icode
== CODE_FOR_spe_evlhhousplat
10023 || icode
== CODE_FOR_spe_evlwhe
10024 || icode
== CODE_FOR_spe_evlwhos
10025 || icode
== CODE_FOR_spe_evlwhou
10026 || icode
== CODE_FOR_spe_evlwhsplat
10027 || icode
== CODE_FOR_spe_evlwwsplat
10028 || icode
== CODE_FOR_spe_evrlwi
10029 || icode
== CODE_FOR_spe_evslwi
10030 || icode
== CODE_FOR_spe_evsrwis
10031 || icode
== CODE_FOR_spe_evsubifw
10032 || icode
== CODE_FOR_spe_evsrwiu
)
10034 /* Only allow 5-bit unsigned literals. */
10036 if (TREE_CODE (arg1
) != INTEGER_CST
10037 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
10039 error ("argument 2 must be a 5-bit unsigned literal");
10045 || GET_MODE (target
) != tmode
10046 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10047 target
= gen_reg_rtx (tmode
);
10049 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10050 op0
= copy_to_mode_reg (mode0
, op0
);
10051 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10052 op1
= copy_to_mode_reg (mode1
, op1
);
10054 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
10063 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
10066 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
10067 tree arg0
= CALL_EXPR_ARG (exp
, 1);
10068 tree arg1
= CALL_EXPR_ARG (exp
, 2);
10069 rtx op0
= expand_normal (arg0
);
10070 rtx op1
= expand_normal (arg1
);
10071 enum machine_mode tmode
= SImode
;
10072 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10073 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10076 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
10078 error ("argument 1 of __builtin_altivec_predicate must be a constant");
10082 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
10084 gcc_assert (mode0
== mode1
);
10086 /* If we have invalid arguments, bail out before generating bad rtl. */
10087 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10091 || GET_MODE (target
) != tmode
10092 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10093 target
= gen_reg_rtx (tmode
);
10095 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10096 op0
= copy_to_mode_reg (mode0
, op0
);
10097 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10098 op1
= copy_to_mode_reg (mode1
, op1
);
10100 scratch
= gen_reg_rtx (mode0
);
10102 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
10107 /* The vec_any* and vec_all* predicates use the same opcodes for two
10108 different operations, but the bits in CR6 will be different
10109 depending on what information we want. So we have to play tricks
10110 with CR6 to get the right bits out.
10112 If you think this is disgusting, look at the specs for the
10113 AltiVec predicates. */
10115 switch (cr6_form_int
)
10118 emit_insn (gen_cr6_test_for_zero (target
));
10121 emit_insn (gen_cr6_test_for_zero_reverse (target
));
10124 emit_insn (gen_cr6_test_for_lt (target
));
10127 emit_insn (gen_cr6_test_for_lt_reverse (target
));
10130 error ("argument 1 of __builtin_altivec_predicate is out of range");
10138 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
10141 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10142 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10143 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10144 enum machine_mode mode0
= Pmode
;
10145 enum machine_mode mode1
= Pmode
;
10146 rtx op0
= expand_normal (arg0
);
10147 rtx op1
= expand_normal (arg1
);
10149 if (icode
== CODE_FOR_nothing
)
10150 /* Builtin not supported on this processor. */
10153 /* If we got invalid arguments bail out before generating bad rtl. */
10154 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10158 || GET_MODE (target
) != tmode
10159 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10160 target
= gen_reg_rtx (tmode
);
10162 op1
= copy_to_mode_reg (mode1
, op1
);
10164 if (op0
== const0_rtx
)
10166 addr
= gen_rtx_MEM (tmode
, op1
);
10170 op0
= copy_to_mode_reg (mode0
, op0
);
10171 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10174 pat
= GEN_FCN (icode
) (target
, addr
);
10184 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
10187 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10188 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10189 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10190 enum machine_mode mode0
= Pmode
;
10191 enum machine_mode mode1
= Pmode
;
10192 rtx op0
= expand_normal (arg0
);
10193 rtx op1
= expand_normal (arg1
);
10195 if (icode
== CODE_FOR_nothing
)
10196 /* Builtin not supported on this processor. */
10199 /* If we got invalid arguments bail out before generating bad rtl. */
10200 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10204 || GET_MODE (target
) != tmode
10205 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10206 target
= gen_reg_rtx (tmode
);
10208 op1
= copy_to_mode_reg (mode1
, op1
);
10210 if (op0
== const0_rtx
)
10212 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
10216 op0
= copy_to_mode_reg (mode0
, op0
);
10217 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10220 pat
= GEN_FCN (icode
) (target
, addr
);
10230 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
10232 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10233 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10234 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10235 rtx op0
= expand_normal (arg0
);
10236 rtx op1
= expand_normal (arg1
);
10237 rtx op2
= expand_normal (arg2
);
10239 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
10240 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
10241 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
10243 /* Invalid arguments. Bail before doing anything stoopid! */
10244 if (arg0
== error_mark_node
10245 || arg1
== error_mark_node
10246 || arg2
== error_mark_node
)
10249 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
10250 op0
= copy_to_mode_reg (mode2
, op0
);
10251 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
10252 op1
= copy_to_mode_reg (mode0
, op1
);
10253 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
10254 op2
= copy_to_mode_reg (mode1
, op2
);
10256 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
10263 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
10265 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10266 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10267 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10268 rtx op0
= expand_normal (arg0
);
10269 rtx op1
= expand_normal (arg1
);
10270 rtx op2
= expand_normal (arg2
);
10272 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10273 enum machine_mode mode1
= Pmode
;
10274 enum machine_mode mode2
= Pmode
;
10276 /* Invalid arguments. Bail before doing anything stoopid! */
10277 if (arg0
== error_mark_node
10278 || arg1
== error_mark_node
10279 || arg2
== error_mark_node
)
10282 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
10283 op0
= copy_to_mode_reg (tmode
, op0
);
10285 op2
= copy_to_mode_reg (mode2
, op2
);
10287 if (op1
== const0_rtx
)
10289 addr
= gen_rtx_MEM (tmode
, op2
);
10293 op1
= copy_to_mode_reg (mode1
, op1
);
10294 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10297 pat
= GEN_FCN (icode
) (addr
, op0
);
10304 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
10306 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10307 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10308 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10309 rtx op0
= expand_normal (arg0
);
10310 rtx op1
= expand_normal (arg1
);
10311 rtx op2
= expand_normal (arg2
);
10313 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10314 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
10315 enum machine_mode mode1
= Pmode
;
10316 enum machine_mode mode2
= Pmode
;
10318 /* Invalid arguments. Bail before doing anything stoopid! */
10319 if (arg0
== error_mark_node
10320 || arg1
== error_mark_node
10321 || arg2
== error_mark_node
)
10324 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
10325 op0
= copy_to_mode_reg (smode
, op0
);
10327 op2
= copy_to_mode_reg (mode2
, op2
);
10329 if (op1
== const0_rtx
)
10331 addr
= gen_rtx_MEM (tmode
, op2
);
10335 op1
= copy_to_mode_reg (mode1
, op1
);
10336 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10339 pat
= GEN_FCN (icode
) (addr
, op0
);
10346 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10349 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10350 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10351 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10352 rtx op0
= expand_normal (arg0
);
10353 rtx op1
= expand_normal (arg1
);
10354 rtx op2
= expand_normal (arg2
);
10355 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10356 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10357 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10358 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
10360 if (icode
== CODE_FOR_nothing
)
10361 /* Builtin not supported on this processor. */
10364 /* If we got invalid arguments bail out before generating bad rtl. */
10365 if (arg0
== error_mark_node
10366 || arg1
== error_mark_node
10367 || arg2
== error_mark_node
)
10370 /* Check and prepare argument depending on the instruction code.
10372 Note that a switch statement instead of the sequence of tests
10373 would be incorrect as many of the CODE_FOR values could be
10374 CODE_FOR_nothing and that would yield multiple alternatives
10375 with identical values. We'd never reach here at runtime in
10377 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
10378 || icode
== CODE_FOR_altivec_vsldoi_v4si
10379 || icode
== CODE_FOR_altivec_vsldoi_v8hi
10380 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
10382 /* Only allow 4-bit unsigned literals. */
10384 if (TREE_CODE (arg2
) != INTEGER_CST
10385 || TREE_INT_CST_LOW (arg2
) & ~0xf)
10387 error ("argument 3 must be a 4-bit unsigned literal");
10391 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
10392 || icode
== CODE_FOR_vsx_xxpermdi_v2di
10393 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
10394 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
10395 || icode
== CODE_FOR_vsx_xxsldwi_v4si
10396 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
10397 || icode
== CODE_FOR_vsx_xxsldwi_v2di
10398 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
10400 /* Only allow 2-bit unsigned literals. */
10402 if (TREE_CODE (arg2
) != INTEGER_CST
10403 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10405 error ("argument 3 must be a 2-bit unsigned literal");
10409 else if (icode
== CODE_FOR_vsx_set_v2df
10410 || icode
== CODE_FOR_vsx_set_v2di
)
10412 /* Only allow 1-bit unsigned literals. */
10414 if (TREE_CODE (arg2
) != INTEGER_CST
10415 || TREE_INT_CST_LOW (arg2
) & ~0x1)
10417 error ("argument 3 must be a 1-bit unsigned literal");
10423 || GET_MODE (target
) != tmode
10424 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10425 target
= gen_reg_rtx (tmode
);
10427 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10428 op0
= copy_to_mode_reg (mode0
, op0
);
10429 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10430 op1
= copy_to_mode_reg (mode1
, op1
);
10431 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
10432 op2
= copy_to_mode_reg (mode2
, op2
);
10434 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
10435 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
10437 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
10445 /* Expand the lvx builtins. */
10447 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
10449 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10450 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10452 enum machine_mode tmode
, mode0
;
10454 enum insn_code icode
;
10458 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
10459 icode
= CODE_FOR_vector_altivec_load_v16qi
;
10461 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
10462 icode
= CODE_FOR_vector_altivec_load_v8hi
;
10464 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
10465 icode
= CODE_FOR_vector_altivec_load_v4si
;
10467 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
10468 icode
= CODE_FOR_vector_altivec_load_v4sf
;
10470 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
10471 icode
= CODE_FOR_vector_altivec_load_v2df
;
10473 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
10474 icode
= CODE_FOR_vector_altivec_load_v2di
;
10477 *expandedp
= false;
10483 arg0
= CALL_EXPR_ARG (exp
, 0);
10484 op0
= expand_normal (arg0
);
10485 tmode
= insn_data
[icode
].operand
[0].mode
;
10486 mode0
= insn_data
[icode
].operand
[1].mode
;
10489 || GET_MODE (target
) != tmode
10490 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10491 target
= gen_reg_rtx (tmode
);
10493 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10494 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10496 pat
= GEN_FCN (icode
) (target
, op0
);
10503 /* Expand the stvx builtins. */
10505 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
10508 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10509 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10511 enum machine_mode mode0
, mode1
;
10513 enum insn_code icode
;
10517 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
10518 icode
= CODE_FOR_vector_altivec_store_v16qi
;
10520 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
10521 icode
= CODE_FOR_vector_altivec_store_v8hi
;
10523 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
10524 icode
= CODE_FOR_vector_altivec_store_v4si
;
10526 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
10527 icode
= CODE_FOR_vector_altivec_store_v4sf
;
10529 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
10530 icode
= CODE_FOR_vector_altivec_store_v2df
;
10532 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
10533 icode
= CODE_FOR_vector_altivec_store_v2di
;
10536 *expandedp
= false;
10540 arg0
= CALL_EXPR_ARG (exp
, 0);
10541 arg1
= CALL_EXPR_ARG (exp
, 1);
10542 op0
= expand_normal (arg0
);
10543 op1
= expand_normal (arg1
);
10544 mode0
= insn_data
[icode
].operand
[0].mode
;
10545 mode1
= insn_data
[icode
].operand
[1].mode
;
10547 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10548 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10549 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
10550 op1
= copy_to_mode_reg (mode1
, op1
);
10552 pat
= GEN_FCN (icode
) (op0
, op1
);
10560 /* Expand the dst builtins. */
10562 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
10565 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10566 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10567 tree arg0
, arg1
, arg2
;
10568 enum machine_mode mode0
, mode1
;
10569 rtx pat
, op0
, op1
, op2
;
10570 const struct builtin_description
*d
;
10573 *expandedp
= false;
10575 /* Handle DST variants. */
10577 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
10578 if (d
->code
== fcode
)
10580 arg0
= CALL_EXPR_ARG (exp
, 0);
10581 arg1
= CALL_EXPR_ARG (exp
, 1);
10582 arg2
= CALL_EXPR_ARG (exp
, 2);
10583 op0
= expand_normal (arg0
);
10584 op1
= expand_normal (arg1
);
10585 op2
= expand_normal (arg2
);
10586 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10587 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10589 /* Invalid arguments, bail out before generating bad rtl. */
10590 if (arg0
== error_mark_node
10591 || arg1
== error_mark_node
10592 || arg2
== error_mark_node
)
10597 if (TREE_CODE (arg2
) != INTEGER_CST
10598 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10600 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
10604 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
10605 op0
= copy_to_mode_reg (Pmode
, op0
);
10606 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
10607 op1
= copy_to_mode_reg (mode1
, op1
);
10609 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
10619 /* Expand vec_init builtin. */
10621 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
10623 enum machine_mode tmode
= TYPE_MODE (type
);
10624 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
10625 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
10626 rtvec v
= rtvec_alloc (n_elt
);
10628 gcc_assert (VECTOR_MODE_P (tmode
));
10629 gcc_assert (n_elt
== call_expr_nargs (exp
));
10631 for (i
= 0; i
< n_elt
; ++i
)
10633 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
10634 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
10637 if (!target
|| !register_operand (target
, tmode
))
10638 target
= gen_reg_rtx (tmode
);
10640 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
10644 /* Return the integer constant in ARG. Constrain it to be in the range
10645 of the subparts of VEC_TYPE; issue an error if not. */
10648 get_element_number (tree vec_type
, tree arg
)
10650 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
10652 if (!host_integerp (arg
, 1)
10653 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
10655 error ("selector must be an integer constant in the range 0..%wi", max
);
10662 /* Expand vec_set builtin. */
10664 altivec_expand_vec_set_builtin (tree exp
)
10666 enum machine_mode tmode
, mode1
;
10667 tree arg0
, arg1
, arg2
;
10671 arg0
= CALL_EXPR_ARG (exp
, 0);
10672 arg1
= CALL_EXPR_ARG (exp
, 1);
10673 arg2
= CALL_EXPR_ARG (exp
, 2);
10675 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
10676 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
10677 gcc_assert (VECTOR_MODE_P (tmode
));
10679 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
10680 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
10681 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
10683 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
10684 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
10686 op0
= force_reg (tmode
, op0
);
10687 op1
= force_reg (mode1
, op1
);
10689 rs6000_expand_vector_set (op0
, op1
, elt
);
10694 /* Expand vec_ext builtin. */
10696 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
10698 enum machine_mode tmode
, mode0
;
10703 arg0
= CALL_EXPR_ARG (exp
, 0);
10704 arg1
= CALL_EXPR_ARG (exp
, 1);
10706 op0
= expand_normal (arg0
);
10707 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
10709 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
10710 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
10711 gcc_assert (VECTOR_MODE_P (mode0
));
10713 op0
= force_reg (mode0
, op0
);
10715 if (optimize
|| !target
|| !register_operand (target
, tmode
))
10716 target
= gen_reg_rtx (tmode
);
10718 rs6000_expand_vector_extract (target
, op0
, elt
);
10723 /* Expand the builtin in EXP and store the result in TARGET. Store
10724 true in *EXPANDEDP if we found a builtin to expand. */
10726 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
10728 const struct builtin_description
*d
;
10730 enum insn_code icode
;
10731 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10734 enum machine_mode tmode
, mode0
;
10735 enum rs6000_builtins fcode
10736 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10738 if (rs6000_overloaded_builtin_p (fcode
))
10741 error ("unresolved overload for Altivec builtin %qF", fndecl
);
10743 /* Given it is invalid, just generate a normal call. */
10744 return expand_call (exp
, target
, false);
10747 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
10751 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
10755 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
10763 case ALTIVEC_BUILTIN_STVX
:
10764 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
10765 case ALTIVEC_BUILTIN_STVEBX
:
10766 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
10767 case ALTIVEC_BUILTIN_STVEHX
:
10768 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
10769 case ALTIVEC_BUILTIN_STVEWX
:
10770 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
10771 case ALTIVEC_BUILTIN_STVXL
:
10772 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
10774 case ALTIVEC_BUILTIN_STVLX
:
10775 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
10776 case ALTIVEC_BUILTIN_STVLXL
:
10777 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
10778 case ALTIVEC_BUILTIN_STVRX
:
10779 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
10780 case ALTIVEC_BUILTIN_STVRXL
:
10781 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
10783 case VSX_BUILTIN_STXVD2X_V2DF
:
10784 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
10785 case VSX_BUILTIN_STXVD2X_V2DI
:
10786 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
10787 case VSX_BUILTIN_STXVW4X_V4SF
:
10788 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
10789 case VSX_BUILTIN_STXVW4X_V4SI
:
10790 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
10791 case VSX_BUILTIN_STXVW4X_V8HI
:
10792 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
10793 case VSX_BUILTIN_STXVW4X_V16QI
:
10794 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
10796 case ALTIVEC_BUILTIN_MFVSCR
:
10797 icode
= CODE_FOR_altivec_mfvscr
;
10798 tmode
= insn_data
[icode
].operand
[0].mode
;
10801 || GET_MODE (target
) != tmode
10802 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10803 target
= gen_reg_rtx (tmode
);
10805 pat
= GEN_FCN (icode
) (target
);
10811 case ALTIVEC_BUILTIN_MTVSCR
:
10812 icode
= CODE_FOR_altivec_mtvscr
;
10813 arg0
= CALL_EXPR_ARG (exp
, 0);
10814 op0
= expand_normal (arg0
);
10815 mode0
= insn_data
[icode
].operand
[0].mode
;
10817 /* If we got invalid arguments bail out before generating bad rtl. */
10818 if (arg0
== error_mark_node
)
10821 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10822 op0
= copy_to_mode_reg (mode0
, op0
);
10824 pat
= GEN_FCN (icode
) (op0
);
10829 case ALTIVEC_BUILTIN_DSSALL
:
10830 emit_insn (gen_altivec_dssall ());
10833 case ALTIVEC_BUILTIN_DSS
:
10834 icode
= CODE_FOR_altivec_dss
;
10835 arg0
= CALL_EXPR_ARG (exp
, 0);
10837 op0
= expand_normal (arg0
);
10838 mode0
= insn_data
[icode
].operand
[0].mode
;
10840 /* If we got invalid arguments bail out before generating bad rtl. */
10841 if (arg0
== error_mark_node
)
10844 if (TREE_CODE (arg0
) != INTEGER_CST
10845 || TREE_INT_CST_LOW (arg0
) & ~0x3)
10847 error ("argument to dss must be a 2-bit unsigned literal");
10851 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10852 op0
= copy_to_mode_reg (mode0
, op0
);
10854 emit_insn (gen_altivec_dss (op0
));
10857 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
10858 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
10859 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
10860 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
10861 case VSX_BUILTIN_VEC_INIT_V2DF
:
10862 case VSX_BUILTIN_VEC_INIT_V2DI
:
10863 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
10865 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
10866 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
10867 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
10868 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
10869 case VSX_BUILTIN_VEC_SET_V2DF
:
10870 case VSX_BUILTIN_VEC_SET_V2DI
:
10871 return altivec_expand_vec_set_builtin (exp
);
10873 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
10874 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
10875 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
10876 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
10877 case VSX_BUILTIN_VEC_EXT_V2DF
:
10878 case VSX_BUILTIN_VEC_EXT_V2DI
:
10879 return altivec_expand_vec_ext_builtin (exp
, target
);
10883 /* Fall through. */
10886 /* Expand abs* operations. */
10888 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
10889 if (d
->code
== fcode
)
10890 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
10892 /* Expand the AltiVec predicates. */
10893 d
= bdesc_altivec_preds
;
10894 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
10895 if (d
->code
== fcode
)
10896 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
10898 /* LV* are funky. We initialized them differently. */
10901 case ALTIVEC_BUILTIN_LVSL
:
10902 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
10903 exp
, target
, false);
10904 case ALTIVEC_BUILTIN_LVSR
:
10905 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
10906 exp
, target
, false);
10907 case ALTIVEC_BUILTIN_LVEBX
:
10908 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
10909 exp
, target
, false);
10910 case ALTIVEC_BUILTIN_LVEHX
:
10911 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
10912 exp
, target
, false);
10913 case ALTIVEC_BUILTIN_LVEWX
:
10914 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
10915 exp
, target
, false);
10916 case ALTIVEC_BUILTIN_LVXL
:
10917 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
10918 exp
, target
, false);
10919 case ALTIVEC_BUILTIN_LVX
:
10920 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
10921 exp
, target
, false);
10922 case ALTIVEC_BUILTIN_LVLX
:
10923 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
10924 exp
, target
, true);
10925 case ALTIVEC_BUILTIN_LVLXL
:
10926 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
10927 exp
, target
, true);
10928 case ALTIVEC_BUILTIN_LVRX
:
10929 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
10930 exp
, target
, true);
10931 case ALTIVEC_BUILTIN_LVRXL
:
10932 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
10933 exp
, target
, true);
10934 case VSX_BUILTIN_LXVD2X_V2DF
:
10935 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
10936 exp
, target
, false);
10937 case VSX_BUILTIN_LXVD2X_V2DI
:
10938 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
10939 exp
, target
, false);
10940 case VSX_BUILTIN_LXVW4X_V4SF
:
10941 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
10942 exp
, target
, false);
10943 case VSX_BUILTIN_LXVW4X_V4SI
:
10944 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
10945 exp
, target
, false);
10946 case VSX_BUILTIN_LXVW4X_V8HI
:
10947 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
10948 exp
, target
, false);
10949 case VSX_BUILTIN_LXVW4X_V16QI
:
10950 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
10951 exp
, target
, false);
10955 /* Fall through. */
10958 *expandedp
= false;
10962 /* Expand the builtin in EXP and store the result in TARGET. Store
10963 true in *EXPANDEDP if we found a builtin to expand. */
10965 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
10967 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10968 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10969 const struct builtin_description
*d
;
10976 case PAIRED_BUILTIN_STX
:
10977 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
10978 case PAIRED_BUILTIN_LX
:
10979 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
10982 /* Fall through. */
10985 /* Expand the paired predicates. */
10986 d
= bdesc_paired_preds
;
10987 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
10988 if (d
->code
== fcode
)
10989 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
10991 *expandedp
= false;
10995 /* Binops that need to be initialized manually, but can be expanded
10996 automagically by rs6000_expand_binop_builtin. */
10997 static const struct builtin_description bdesc_2arg_spe
[] =
10999 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
11000 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
11001 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
11002 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
11003 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
11004 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
11005 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
11006 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
11007 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
11008 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
11009 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
11010 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
11011 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
11012 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
11013 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
11014 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
11015 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
11016 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
11017 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
11018 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
11019 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
11020 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
11023 /* Expand the builtin in EXP and store the result in TARGET. Store
11024 true in *EXPANDEDP if we found a builtin to expand.
11026 This expands the SPE builtins that are not simple unary and binary
11029 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
11031 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11033 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11034 enum insn_code icode
;
11035 enum machine_mode tmode
, mode0
;
11037 const struct builtin_description
*d
;
11042 /* Syntax check for a 5-bit unsigned immediate. */
11045 case SPE_BUILTIN_EVSTDD
:
11046 case SPE_BUILTIN_EVSTDH
:
11047 case SPE_BUILTIN_EVSTDW
:
11048 case SPE_BUILTIN_EVSTWHE
:
11049 case SPE_BUILTIN_EVSTWHO
:
11050 case SPE_BUILTIN_EVSTWWE
:
11051 case SPE_BUILTIN_EVSTWWO
:
11052 arg1
= CALL_EXPR_ARG (exp
, 2);
11053 if (TREE_CODE (arg1
) != INTEGER_CST
11054 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11056 error ("argument 2 must be a 5-bit unsigned literal");
11064 /* The evsplat*i instructions are not quite generic. */
11067 case SPE_BUILTIN_EVSPLATFI
:
11068 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
11070 case SPE_BUILTIN_EVSPLATI
:
11071 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
11077 d
= bdesc_2arg_spe
;
11078 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
11079 if (d
->code
== fcode
)
11080 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11082 d
= bdesc_spe_predicates
;
11083 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
11084 if (d
->code
== fcode
)
11085 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
11087 d
= bdesc_spe_evsel
;
11088 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
11089 if (d
->code
== fcode
)
11090 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
11094 case SPE_BUILTIN_EVSTDDX
:
11095 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
11096 case SPE_BUILTIN_EVSTDHX
:
11097 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
11098 case SPE_BUILTIN_EVSTDWX
:
11099 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
11100 case SPE_BUILTIN_EVSTWHEX
:
11101 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
11102 case SPE_BUILTIN_EVSTWHOX
:
11103 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
11104 case SPE_BUILTIN_EVSTWWEX
:
11105 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
11106 case SPE_BUILTIN_EVSTWWOX
:
11107 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
11108 case SPE_BUILTIN_EVSTDD
:
11109 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
11110 case SPE_BUILTIN_EVSTDH
:
11111 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
11112 case SPE_BUILTIN_EVSTDW
:
11113 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
11114 case SPE_BUILTIN_EVSTWHE
:
11115 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
11116 case SPE_BUILTIN_EVSTWHO
:
11117 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
11118 case SPE_BUILTIN_EVSTWWE
:
11119 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
11120 case SPE_BUILTIN_EVSTWWO
:
11121 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
11122 case SPE_BUILTIN_MFSPEFSCR
:
11123 icode
= CODE_FOR_spe_mfspefscr
;
11124 tmode
= insn_data
[icode
].operand
[0].mode
;
11127 || GET_MODE (target
) != tmode
11128 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11129 target
= gen_reg_rtx (tmode
);
11131 pat
= GEN_FCN (icode
) (target
);
11136 case SPE_BUILTIN_MTSPEFSCR
:
11137 icode
= CODE_FOR_spe_mtspefscr
;
11138 arg0
= CALL_EXPR_ARG (exp
, 0);
11139 op0
= expand_normal (arg0
);
11140 mode0
= insn_data
[icode
].operand
[0].mode
;
11142 if (arg0
== error_mark_node
)
11145 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11146 op0
= copy_to_mode_reg (mode0
, op0
);
11148 pat
= GEN_FCN (icode
) (op0
);
11156 *expandedp
= false;
11161 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11163 rtx pat
, scratch
, tmp
;
11164 tree form
= CALL_EXPR_ARG (exp
, 0);
11165 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11166 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11167 rtx op0
= expand_normal (arg0
);
11168 rtx op1
= expand_normal (arg1
);
11169 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11170 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11172 enum rtx_code code
;
11174 if (TREE_CODE (form
) != INTEGER_CST
)
11176 error ("argument 1 of __builtin_paired_predicate must be a constant");
11180 form_int
= TREE_INT_CST_LOW (form
);
11182 gcc_assert (mode0
== mode1
);
11184 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11188 || GET_MODE (target
) != SImode
11189 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11190 target
= gen_reg_rtx (SImode
);
11191 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11192 op0
= copy_to_mode_reg (mode0
, op0
);
11193 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11194 op1
= copy_to_mode_reg (mode1
, op1
);
11196 scratch
= gen_reg_rtx (CCFPmode
);
11198 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11220 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11223 error ("argument 1 of __builtin_paired_predicate is out of range");
11227 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11228 emit_move_insn (target
, tmp
);
11233 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11235 rtx pat
, scratch
, tmp
;
11236 tree form
= CALL_EXPR_ARG (exp
, 0);
11237 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11238 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11239 rtx op0
= expand_normal (arg0
);
11240 rtx op1
= expand_normal (arg1
);
11241 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11242 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11244 enum rtx_code code
;
11246 if (TREE_CODE (form
) != INTEGER_CST
)
11248 error ("argument 1 of __builtin_spe_predicate must be a constant");
11252 form_int
= TREE_INT_CST_LOW (form
);
11254 gcc_assert (mode0
== mode1
);
11256 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11260 || GET_MODE (target
) != SImode
11261 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11262 target
= gen_reg_rtx (SImode
);
11264 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11265 op0
= copy_to_mode_reg (mode0
, op0
);
11266 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11267 op1
= copy_to_mode_reg (mode1
, op1
);
11269 scratch
= gen_reg_rtx (CCmode
);
11271 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11276 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11277 _lower_. We use one compare, but look in different bits of the
11278 CR for each variant.
11280 There are 2 elements in each SPE simd type (upper/lower). The CR
11281 bits are set as follows:
11283 BIT0 | BIT 1 | BIT 2 | BIT 3
11284 U | L | (U | L) | (U & L)
11286 So, for an "all" relationship, BIT 3 would be set.
11287 For an "any" relationship, BIT 2 would be set. Etc.
11289 Following traditional nomenclature, these bits map to:
11291 BIT0 | BIT 1 | BIT 2 | BIT 3
11294 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11299 /* All variant. OV bit. */
11301 /* We need to get to the OV bit, which is the ORDERED bit. We
11302 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11303 that's ugly and will make validate_condition_mode die.
11304 So let's just use another pattern. */
11305 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11307 /* Any variant. EQ bit. */
11311 /* Upper variant. LT bit. */
11315 /* Lower variant. GT bit. */
11320 error ("argument 1 of __builtin_spe_predicate is out of range");
11324 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11325 emit_move_insn (target
, tmp
);
11330 /* The evsel builtins look like this:
11332 e = __builtin_spe_evsel_OP (a, b, c, d);
11334 and work like this:
11336 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11337 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11341 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
11344 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11345 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11346 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11347 tree arg3
= CALL_EXPR_ARG (exp
, 3);
11348 rtx op0
= expand_normal (arg0
);
11349 rtx op1
= expand_normal (arg1
);
11350 rtx op2
= expand_normal (arg2
);
11351 rtx op3
= expand_normal (arg3
);
11352 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11353 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11355 gcc_assert (mode0
== mode1
);
11357 if (arg0
== error_mark_node
|| arg1
== error_mark_node
11358 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
11362 || GET_MODE (target
) != mode0
11363 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
11364 target
= gen_reg_rtx (mode0
);
11366 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11367 op0
= copy_to_mode_reg (mode0
, op0
);
11368 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11369 op1
= copy_to_mode_reg (mode0
, op1
);
11370 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11371 op2
= copy_to_mode_reg (mode0
, op2
);
11372 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
11373 op3
= copy_to_mode_reg (mode0
, op3
);
11375 /* Generate the compare. */
11376 scratch
= gen_reg_rtx (CCmode
);
11377 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11382 if (mode0
== V2SImode
)
11383 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
11385 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
11390 /* Raise an error message for a builtin function that is called without the
11391 appropriate target options being set. */
11394 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
11396 size_t uns_fncode
= (size_t)fncode
;
11397 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
11398 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
11400 gcc_assert (name
!= NULL
);
11401 if ((fnmask
& RS6000_BTM_CELL
) != 0)
11402 error ("Builtin function %s is only valid for the cell processor", name
);
11403 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
11404 error ("Builtin function %s requires the -mvsx option", name
);
11405 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
11406 error ("Builtin function %s requires the -maltivec option", name
);
11407 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
11408 error ("Builtin function %s requires the -mpaired option", name
);
11409 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
11410 error ("Builtin function %s requires the -mspe option", name
);
11412 error ("Builtin function %s is not supported with the current options",
11416 /* Expand an expression EXP that calls a built-in function,
11417 with result going to TARGET if that's convenient
11418 (and in mode MODE if that's convenient).
11419 SUBTARGET may be used as the target for computing one of EXP's operands.
11420 IGNORE is nonzero if the value is to be ignored. */
11423 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
11424 enum machine_mode mode ATTRIBUTE_UNUSED
,
11425 int ignore ATTRIBUTE_UNUSED
)
11427 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11428 enum rs6000_builtins fcode
11429 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
11430 size_t uns_fcode
= (size_t)fcode
;
11431 const struct builtin_description
*d
;
11435 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
11436 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
11438 if (TARGET_DEBUG_BUILTIN
)
11440 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
11441 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
11442 const char *name2
= ((icode
!= CODE_FOR_nothing
)
11443 ? get_insn_name ((int)icode
)
11447 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
11449 default: name3
= "unknown"; break;
11450 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
11451 case RS6000_BTC_UNARY
: name3
= "unary"; break;
11452 case RS6000_BTC_BINARY
: name3
= "binary"; break;
11453 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
11454 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
11455 case RS6000_BTC_ABS
: name3
= "abs"; break;
11456 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
11457 case RS6000_BTC_DST
: name3
= "dst"; break;
11462 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11463 (name1
) ? name1
: "---", fcode
,
11464 (name2
) ? name2
: "---", (int)icode
,
11466 func_valid_p
? "" : ", not valid");
11471 rs6000_invalid_builtin (fcode
);
11473 /* Given it is invalid, just generate a normal call. */
11474 return expand_call (exp
, target
, ignore
);
11479 case RS6000_BUILTIN_RECIP
:
11480 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
11482 case RS6000_BUILTIN_RECIPF
:
11483 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
11485 case RS6000_BUILTIN_RSQRTF
:
11486 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
11488 case RS6000_BUILTIN_RSQRT
:
11489 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
11491 case POWER7_BUILTIN_BPERMD
:
11492 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
11493 ? CODE_FOR_bpermd_di
11494 : CODE_FOR_bpermd_si
), exp
, target
);
11496 case RS6000_BUILTIN_GET_TB
:
11497 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
11500 case RS6000_BUILTIN_MFTB
:
11501 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
11502 ? CODE_FOR_rs6000_mftb_di
11503 : CODE_FOR_rs6000_mftb_si
),
11506 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
11507 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
11509 int icode
= (int) CODE_FOR_altivec_lvsr
;
11510 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11511 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
11515 gcc_assert (TARGET_ALTIVEC
);
11517 arg
= CALL_EXPR_ARG (exp
, 0);
11518 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
11519 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
11520 addr
= memory_address (mode
, op
);
11521 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
11525 /* For the load case need to negate the address. */
11526 op
= gen_reg_rtx (GET_MODE (addr
));
11527 emit_insn (gen_rtx_SET (VOIDmode
, op
,
11528 gen_rtx_NEG (GET_MODE (addr
), addr
)));
11530 op
= gen_rtx_MEM (mode
, op
);
11533 || GET_MODE (target
) != tmode
11534 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11535 target
= gen_reg_rtx (tmode
);
11537 /*pat = gen_altivec_lvsr (target, op);*/
11538 pat
= GEN_FCN (icode
) (target
, op
);
11546 case ALTIVEC_BUILTIN_VCFUX
:
11547 case ALTIVEC_BUILTIN_VCFSX
:
11548 case ALTIVEC_BUILTIN_VCTUXS
:
11549 case ALTIVEC_BUILTIN_VCTSXS
:
11550 /* FIXME: There's got to be a nicer way to handle this case than
11551 constructing a new CALL_EXPR. */
11552 if (call_expr_nargs (exp
) == 1)
11554 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
11555 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
11563 if (TARGET_ALTIVEC
)
11565 ret
= altivec_expand_builtin (exp
, target
, &success
);
11572 ret
= spe_expand_builtin (exp
, target
, &success
);
11577 if (TARGET_PAIRED_FLOAT
)
11579 ret
= paired_expand_builtin (exp
, target
, &success
);
11585 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
11587 /* Handle simple unary operations. */
11589 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
11590 if (d
->code
== fcode
)
11591 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
11593 /* Handle simple binary operations. */
11595 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11596 if (d
->code
== fcode
)
11597 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11599 /* Handle simple ternary operations. */
11601 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
11602 if (d
->code
== fcode
)
11603 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
11605 gcc_unreachable ();
11609 rs6000_init_builtins (void)
11613 enum machine_mode mode
;
11615 if (TARGET_DEBUG_BUILTIN
)
11616 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
11617 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
11618 (TARGET_SPE
) ? ", spe" : "",
11619 (TARGET_ALTIVEC
) ? ", altivec" : "",
11620 (TARGET_VSX
) ? ", vsx" : "");
11622 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
11623 V2SF_type_node
= build_vector_type (float_type_node
, 2);
11624 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
11625 V2DF_type_node
= build_vector_type (double_type_node
, 2);
11626 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
11627 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
11628 V4SF_type_node
= build_vector_type (float_type_node
, 4);
11629 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
11630 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
11632 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
11633 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
11634 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
11635 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
11637 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
11638 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
11639 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
11640 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
11642 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11643 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11644 'vector unsigned short'. */
11646 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
11647 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
11648 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
11649 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
11650 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
11652 long_integer_type_internal_node
= long_integer_type_node
;
11653 long_unsigned_type_internal_node
= long_unsigned_type_node
;
11654 long_long_integer_type_internal_node
= long_long_integer_type_node
;
11655 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
11656 intQI_type_internal_node
= intQI_type_node
;
11657 uintQI_type_internal_node
= unsigned_intQI_type_node
;
11658 intHI_type_internal_node
= intHI_type_node
;
11659 uintHI_type_internal_node
= unsigned_intHI_type_node
;
11660 intSI_type_internal_node
= intSI_type_node
;
11661 uintSI_type_internal_node
= unsigned_intSI_type_node
;
11662 intDI_type_internal_node
= intDI_type_node
;
11663 uintDI_type_internal_node
= unsigned_intDI_type_node
;
11664 float_type_internal_node
= float_type_node
;
11665 double_type_internal_node
= double_type_node
;
11666 void_type_internal_node
= void_type_node
;
11668 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11670 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
11671 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
11672 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
11673 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
11674 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
11675 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
11676 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
11677 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
11678 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
11679 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
11680 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
11681 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
11682 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
11683 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
11684 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
11685 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
11686 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
11687 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
11688 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
11689 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
11690 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
11692 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
11693 TYPE_NAME (bool_char_type_node
) = tdecl
;
11695 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
11696 TYPE_NAME (bool_short_type_node
) = tdecl
;
11698 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
11699 TYPE_NAME (bool_int_type_node
) = tdecl
;
11701 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
11702 TYPE_NAME (pixel_type_node
) = tdecl
;
11704 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
11705 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
11706 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
11707 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
11708 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
11710 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
11711 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
11713 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
11714 TYPE_NAME (V16QI_type_node
) = tdecl
;
11716 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
11717 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
11719 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
11720 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
11722 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
11723 TYPE_NAME (V8HI_type_node
) = tdecl
;
11725 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
11726 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
11728 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
11729 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
11731 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
11732 TYPE_NAME (V4SI_type_node
) = tdecl
;
11734 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
11735 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
11737 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
11738 TYPE_NAME (V4SF_type_node
) = tdecl
;
11740 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
11741 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
11743 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
11744 TYPE_NAME (V2DF_type_node
) = tdecl
;
11746 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
11747 TYPE_NAME (V2DI_type_node
) = tdecl
;
11749 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
11750 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
11752 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
11753 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
11755 /* Paired and SPE builtins are only available if you build a compiler with
11756 the appropriate options, so only create those builtins with the
11757 appropriate compiler option. Create Altivec and VSX builtins on machines
11758 with at least the general purpose extensions (970 and newer) to allow the
11759 use of the target attribute. */
11760 if (TARGET_PAIRED_FLOAT
)
11761 paired_init_builtins ();
11763 spe_init_builtins ();
11764 if (TARGET_EXTRA_BUILTINS
)
11765 altivec_init_builtins ();
11766 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
11767 rs6000_common_init_builtins ();
11769 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
11770 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
11771 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
11773 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
11774 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
11775 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
11777 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
11778 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
11779 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
11781 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
11782 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
11783 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
11785 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
11786 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
11787 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
11788 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
11790 ftype
= build_function_type_list (unsigned_intDI_type_node
,
11792 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
11795 ftype
= build_function_type_list (unsigned_intDI_type_node
,
11798 ftype
= build_function_type_list (unsigned_intSI_type_node
,
11800 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
11803 /* AIX libm provides clog as __clog. */
11804 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
11805 set_user_assembler_name (tdecl
, "__clog");
11808 #ifdef SUBTARGET_INIT_BUILTINS
11809 SUBTARGET_INIT_BUILTINS
;
11813 /* Returns the rs6000 builtin decl for CODE. */
11816 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11818 HOST_WIDE_INT fnmask
;
11820 if (code
>= RS6000_BUILTIN_COUNT
)
11821 return error_mark_node
;
11823 fnmask
= rs6000_builtin_info
[code
].mask
;
11824 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
11826 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
11827 return error_mark_node
;
11830 return rs6000_builtin_decls
[code
];
11834 spe_init_builtins (void)
11836 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
11837 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
11838 const struct builtin_description
*d
;
11841 tree v2si_ftype_4_v2si
11842 = build_function_type_list (opaque_V2SI_type_node
,
11843 opaque_V2SI_type_node
,
11844 opaque_V2SI_type_node
,
11845 opaque_V2SI_type_node
,
11846 opaque_V2SI_type_node
,
11849 tree v2sf_ftype_4_v2sf
11850 = build_function_type_list (opaque_V2SF_type_node
,
11851 opaque_V2SF_type_node
,
11852 opaque_V2SF_type_node
,
11853 opaque_V2SF_type_node
,
11854 opaque_V2SF_type_node
,
11857 tree int_ftype_int_v2si_v2si
11858 = build_function_type_list (integer_type_node
,
11860 opaque_V2SI_type_node
,
11861 opaque_V2SI_type_node
,
11864 tree int_ftype_int_v2sf_v2sf
11865 = build_function_type_list (integer_type_node
,
11867 opaque_V2SF_type_node
,
11868 opaque_V2SF_type_node
,
11871 tree void_ftype_v2si_puint_int
11872 = build_function_type_list (void_type_node
,
11873 opaque_V2SI_type_node
,
11878 tree void_ftype_v2si_puint_char
11879 = build_function_type_list (void_type_node
,
11880 opaque_V2SI_type_node
,
11885 tree void_ftype_v2si_pv2si_int
11886 = build_function_type_list (void_type_node
,
11887 opaque_V2SI_type_node
,
11888 opaque_p_V2SI_type_node
,
11892 tree void_ftype_v2si_pv2si_char
11893 = build_function_type_list (void_type_node
,
11894 opaque_V2SI_type_node
,
11895 opaque_p_V2SI_type_node
,
11899 tree void_ftype_int
11900 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
11902 tree int_ftype_void
11903 = build_function_type_list (integer_type_node
, NULL_TREE
);
11905 tree v2si_ftype_pv2si_int
11906 = build_function_type_list (opaque_V2SI_type_node
,
11907 opaque_p_V2SI_type_node
,
11911 tree v2si_ftype_puint_int
11912 = build_function_type_list (opaque_V2SI_type_node
,
11917 tree v2si_ftype_pushort_int
11918 = build_function_type_list (opaque_V2SI_type_node
,
11923 tree v2si_ftype_signed_char
11924 = build_function_type_list (opaque_V2SI_type_node
,
11925 signed_char_type_node
,
11928 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
11930 /* Initialize irregular SPE builtins. */
11932 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
11933 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
11934 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
11935 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
11936 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
11937 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
11938 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
11939 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
11940 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
11941 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
11942 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
11943 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
11944 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
11945 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
11946 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
11947 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
11948 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
11949 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
11952 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
11953 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
11954 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
11955 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
11956 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
11957 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
11958 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
11959 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
11960 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
11961 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
11962 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
11963 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
11964 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
11965 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
11966 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
11967 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
11968 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
11969 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
11970 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
11971 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
11972 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
11973 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
11976 d
= bdesc_spe_predicates
;
11977 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
11981 switch (insn_data
[d
->icode
].operand
[1].mode
)
11984 type
= int_ftype_int_v2si_v2si
;
11987 type
= int_ftype_int_v2sf_v2sf
;
11990 gcc_unreachable ();
11993 def_builtin (d
->name
, type
, d
->code
);
11996 /* Evsel predicates. */
11997 d
= bdesc_spe_evsel
;
11998 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
12002 switch (insn_data
[d
->icode
].operand
[1].mode
)
12005 type
= v2si_ftype_4_v2si
;
12008 type
= v2sf_ftype_4_v2sf
;
12011 gcc_unreachable ();
12014 def_builtin (d
->name
, type
, d
->code
);
12019 paired_init_builtins (void)
12021 const struct builtin_description
*d
;
12024 tree int_ftype_int_v2sf_v2sf
12025 = build_function_type_list (integer_type_node
,
12030 tree pcfloat_type_node
=
12031 build_pointer_type (build_qualified_type
12032 (float_type_node
, TYPE_QUAL_CONST
));
12034 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
12035 long_integer_type_node
,
12038 tree void_ftype_v2sf_long_pcfloat
=
12039 build_function_type_list (void_type_node
,
12041 long_integer_type_node
,
12046 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
12047 PAIRED_BUILTIN_LX
);
12050 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
12051 PAIRED_BUILTIN_STX
);
12054 d
= bdesc_paired_preds
;
12055 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
12059 if (TARGET_DEBUG_BUILTIN
)
12060 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
12061 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
12062 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
12064 switch (insn_data
[d
->icode
].operand
[1].mode
)
12067 type
= int_ftype_int_v2sf_v2sf
;
12070 gcc_unreachable ();
12073 def_builtin (d
->name
, type
, d
->code
);
12078 altivec_init_builtins (void)
12080 const struct builtin_description
*d
;
12085 tree pvoid_type_node
= build_pointer_type (void_type_node
);
12087 tree pcvoid_type_node
12088 = build_pointer_type (build_qualified_type (void_type_node
,
12091 tree int_ftype_opaque
12092 = build_function_type_list (integer_type_node
,
12093 opaque_V4SI_type_node
, NULL_TREE
);
12094 tree opaque_ftype_opaque
12095 = build_function_type_list (integer_type_node
, NULL_TREE
);
12096 tree opaque_ftype_opaque_int
12097 = build_function_type_list (opaque_V4SI_type_node
,
12098 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
12099 tree opaque_ftype_opaque_opaque_int
12100 = build_function_type_list (opaque_V4SI_type_node
,
12101 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
12102 integer_type_node
, NULL_TREE
);
12103 tree int_ftype_int_opaque_opaque
12104 = build_function_type_list (integer_type_node
,
12105 integer_type_node
, opaque_V4SI_type_node
,
12106 opaque_V4SI_type_node
, NULL_TREE
);
12107 tree int_ftype_int_v4si_v4si
12108 = build_function_type_list (integer_type_node
,
12109 integer_type_node
, V4SI_type_node
,
12110 V4SI_type_node
, NULL_TREE
);
12111 tree void_ftype_v4si
12112 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
12113 tree v8hi_ftype_void
12114 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
12115 tree void_ftype_void
12116 = build_function_type_list (void_type_node
, NULL_TREE
);
12117 tree void_ftype_int
12118 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
12120 tree opaque_ftype_long_pcvoid
12121 = build_function_type_list (opaque_V4SI_type_node
,
12122 long_integer_type_node
, pcvoid_type_node
,
12124 tree v16qi_ftype_long_pcvoid
12125 = build_function_type_list (V16QI_type_node
,
12126 long_integer_type_node
, pcvoid_type_node
,
12128 tree v8hi_ftype_long_pcvoid
12129 = build_function_type_list (V8HI_type_node
,
12130 long_integer_type_node
, pcvoid_type_node
,
12132 tree v4si_ftype_long_pcvoid
12133 = build_function_type_list (V4SI_type_node
,
12134 long_integer_type_node
, pcvoid_type_node
,
12136 tree v4sf_ftype_long_pcvoid
12137 = build_function_type_list (V4SF_type_node
,
12138 long_integer_type_node
, pcvoid_type_node
,
12140 tree v2df_ftype_long_pcvoid
12141 = build_function_type_list (V2DF_type_node
,
12142 long_integer_type_node
, pcvoid_type_node
,
12144 tree v2di_ftype_long_pcvoid
12145 = build_function_type_list (V2DI_type_node
,
12146 long_integer_type_node
, pcvoid_type_node
,
12149 tree void_ftype_opaque_long_pvoid
12150 = build_function_type_list (void_type_node
,
12151 opaque_V4SI_type_node
, long_integer_type_node
,
12152 pvoid_type_node
, NULL_TREE
);
12153 tree void_ftype_v4si_long_pvoid
12154 = build_function_type_list (void_type_node
,
12155 V4SI_type_node
, long_integer_type_node
,
12156 pvoid_type_node
, NULL_TREE
);
12157 tree void_ftype_v16qi_long_pvoid
12158 = build_function_type_list (void_type_node
,
12159 V16QI_type_node
, long_integer_type_node
,
12160 pvoid_type_node
, NULL_TREE
);
12161 tree void_ftype_v8hi_long_pvoid
12162 = build_function_type_list (void_type_node
,
12163 V8HI_type_node
, long_integer_type_node
,
12164 pvoid_type_node
, NULL_TREE
);
12165 tree void_ftype_v4sf_long_pvoid
12166 = build_function_type_list (void_type_node
,
12167 V4SF_type_node
, long_integer_type_node
,
12168 pvoid_type_node
, NULL_TREE
);
12169 tree void_ftype_v2df_long_pvoid
12170 = build_function_type_list (void_type_node
,
12171 V2DF_type_node
, long_integer_type_node
,
12172 pvoid_type_node
, NULL_TREE
);
12173 tree void_ftype_v2di_long_pvoid
12174 = build_function_type_list (void_type_node
,
12175 V2DI_type_node
, long_integer_type_node
,
12176 pvoid_type_node
, NULL_TREE
);
12177 tree int_ftype_int_v8hi_v8hi
12178 = build_function_type_list (integer_type_node
,
12179 integer_type_node
, V8HI_type_node
,
12180 V8HI_type_node
, NULL_TREE
);
12181 tree int_ftype_int_v16qi_v16qi
12182 = build_function_type_list (integer_type_node
,
12183 integer_type_node
, V16QI_type_node
,
12184 V16QI_type_node
, NULL_TREE
);
12185 tree int_ftype_int_v4sf_v4sf
12186 = build_function_type_list (integer_type_node
,
12187 integer_type_node
, V4SF_type_node
,
12188 V4SF_type_node
, NULL_TREE
);
12189 tree int_ftype_int_v2df_v2df
12190 = build_function_type_list (integer_type_node
,
12191 integer_type_node
, V2DF_type_node
,
12192 V2DF_type_node
, NULL_TREE
);
12193 tree v4si_ftype_v4si
12194 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12195 tree v8hi_ftype_v8hi
12196 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12197 tree v16qi_ftype_v16qi
12198 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12199 tree v4sf_ftype_v4sf
12200 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12201 tree v2df_ftype_v2df
12202 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12203 tree void_ftype_pcvoid_int_int
12204 = build_function_type_list (void_type_node
,
12205 pcvoid_type_node
, integer_type_node
,
12206 integer_type_node
, NULL_TREE
);
12208 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
12209 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
12210 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
12211 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
12212 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
12213 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
12214 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
12215 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
12216 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
12217 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
12218 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
12219 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
12220 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
12221 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
12222 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
12223 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
12224 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
12225 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
12226 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
12227 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
12228 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
12229 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
12230 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
12231 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
12232 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
12233 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
12234 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
12235 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
12236 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
12237 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
12239 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
12240 VSX_BUILTIN_LXVD2X_V2DF
);
12241 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
12242 VSX_BUILTIN_LXVD2X_V2DI
);
12243 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
12244 VSX_BUILTIN_LXVW4X_V4SF
);
12245 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
12246 VSX_BUILTIN_LXVW4X_V4SI
);
12247 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
12248 VSX_BUILTIN_LXVW4X_V8HI
);
12249 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
12250 VSX_BUILTIN_LXVW4X_V16QI
);
12251 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
12252 VSX_BUILTIN_STXVD2X_V2DF
);
12253 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
12254 VSX_BUILTIN_STXVD2X_V2DI
);
12255 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
12256 VSX_BUILTIN_STXVW4X_V4SF
);
12257 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
12258 VSX_BUILTIN_STXVW4X_V4SI
);
12259 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
12260 VSX_BUILTIN_STXVW4X_V8HI
);
12261 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
12262 VSX_BUILTIN_STXVW4X_V16QI
);
12263 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
12264 VSX_BUILTIN_VEC_LD
);
12265 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
12266 VSX_BUILTIN_VEC_ST
);
12268 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
12269 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
12270 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
12272 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
12273 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
12274 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
12275 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
12276 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
12277 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
12278 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
12279 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
12280 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
12281 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
12282 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
12283 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
12285 /* Cell builtins. */
12286 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
12287 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
12288 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
12289 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
12291 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
12292 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
12293 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
12294 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
12296 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
12297 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
12298 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
12299 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
12301 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
12302 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
12303 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
12304 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
12306 /* Add the DST variants. */
12308 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12309 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
12311 /* Initialize the predicates. */
12312 d
= bdesc_altivec_preds
;
12313 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12315 enum machine_mode mode1
;
12318 if (rs6000_overloaded_builtin_p (d
->code
))
12321 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12326 type
= int_ftype_int_opaque_opaque
;
12329 type
= int_ftype_int_v4si_v4si
;
12332 type
= int_ftype_int_v8hi_v8hi
;
12335 type
= int_ftype_int_v16qi_v16qi
;
12338 type
= int_ftype_int_v4sf_v4sf
;
12341 type
= int_ftype_int_v2df_v2df
;
12344 gcc_unreachable ();
12347 def_builtin (d
->name
, type
, d
->code
);
12350 /* Initialize the abs* operators. */
12352 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12354 enum machine_mode mode0
;
12357 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12362 type
= v4si_ftype_v4si
;
12365 type
= v8hi_ftype_v8hi
;
12368 type
= v16qi_ftype_v16qi
;
12371 type
= v4sf_ftype_v4sf
;
12374 type
= v2df_ftype_v2df
;
12377 gcc_unreachable ();
12380 def_builtin (d
->name
, type
, d
->code
);
12383 /* Initialize target builtin that implements
12384 targetm.vectorize.builtin_mask_for_load. */
12386 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
12387 v16qi_ftype_long_pcvoid
,
12388 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
12389 BUILT_IN_MD
, NULL
, NULL_TREE
);
12390 TREE_READONLY (decl
) = 1;
12391 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12392 altivec_builtin_mask_for_load
= decl
;
12394 /* Access to the vec_init patterns. */
12395 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
12396 integer_type_node
, integer_type_node
,
12397 integer_type_node
, NULL_TREE
);
12398 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
12400 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
12401 short_integer_type_node
,
12402 short_integer_type_node
,
12403 short_integer_type_node
,
12404 short_integer_type_node
,
12405 short_integer_type_node
,
12406 short_integer_type_node
,
12407 short_integer_type_node
, NULL_TREE
);
12408 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
12410 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
12411 char_type_node
, char_type_node
,
12412 char_type_node
, char_type_node
,
12413 char_type_node
, char_type_node
,
12414 char_type_node
, char_type_node
,
12415 char_type_node
, char_type_node
,
12416 char_type_node
, char_type_node
,
12417 char_type_node
, char_type_node
,
12418 char_type_node
, NULL_TREE
);
12419 def_builtin ("__builtin_vec_init_v16qi", ftype
,
12420 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
12422 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
12423 float_type_node
, float_type_node
,
12424 float_type_node
, NULL_TREE
);
12425 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
12427 /* VSX builtins. */
12428 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
12429 double_type_node
, NULL_TREE
);
12430 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
12432 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
12433 intDI_type_node
, NULL_TREE
);
12434 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
12436 /* Access to the vec_set patterns. */
12437 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
12439 integer_type_node
, NULL_TREE
);
12440 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
12442 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
12444 integer_type_node
, NULL_TREE
);
12445 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
12447 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
12449 integer_type_node
, NULL_TREE
);
12450 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
12452 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
12454 integer_type_node
, NULL_TREE
);
12455 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
12457 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
12459 integer_type_node
, NULL_TREE
);
12460 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
12462 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
12464 integer_type_node
, NULL_TREE
);
12465 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
12467 /* Access to the vec_extract patterns. */
12468 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
12469 integer_type_node
, NULL_TREE
);
12470 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
12472 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
12473 integer_type_node
, NULL_TREE
);
12474 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
12476 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
12477 integer_type_node
, NULL_TREE
);
12478 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
12480 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
12481 integer_type_node
, NULL_TREE
);
12482 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
12484 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
12485 integer_type_node
, NULL_TREE
);
12486 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
12488 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
12489 integer_type_node
, NULL_TREE
);
12490 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
12493 /* Hash function for builtin functions with up to 3 arguments and a return
12496 builtin_hash_function (const void *hash_entry
)
12500 const struct builtin_hash_struct
*bh
=
12501 (const struct builtin_hash_struct
*) hash_entry
;
12503 for (i
= 0; i
< 4; i
++)
12505 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
12506 ret
= (ret
* 2) + bh
->uns_p
[i
];
12512 /* Compare builtin hash entries H1 and H2 for equivalence. */
12514 builtin_hash_eq (const void *h1
, const void *h2
)
12516 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
12517 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
12519 return ((p1
->mode
[0] == p2
->mode
[0])
12520 && (p1
->mode
[1] == p2
->mode
[1])
12521 && (p1
->mode
[2] == p2
->mode
[2])
12522 && (p1
->mode
[3] == p2
->mode
[3])
12523 && (p1
->uns_p
[0] == p2
->uns_p
[0])
12524 && (p1
->uns_p
[1] == p2
->uns_p
[1])
12525 && (p1
->uns_p
[2] == p2
->uns_p
[2])
12526 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
12529 /* Map types for builtin functions with an explicit return type and up to 3
12530 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12531 of the argument. */
12533 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
12534 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
12535 enum rs6000_builtins builtin
, const char *name
)
12537 struct builtin_hash_struct h
;
12538 struct builtin_hash_struct
*h2
;
12542 tree ret_type
= NULL_TREE
;
12543 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
12545 /* Create builtin_hash_table. */
12546 if (builtin_hash_table
== NULL
)
12547 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
12548 builtin_hash_eq
, NULL
);
12550 h
.type
= NULL_TREE
;
12551 h
.mode
[0] = mode_ret
;
12552 h
.mode
[1] = mode_arg0
;
12553 h
.mode
[2] = mode_arg1
;
12554 h
.mode
[3] = mode_arg2
;
12560 /* If the builtin is a type that produces unsigned results or takes unsigned
12561 arguments, and it is returned as a decl for the vectorizer (such as
12562 widening multiplies, permute), make sure the arguments and return value
12563 are type correct. */
12566 /* unsigned 2 argument functions. */
12567 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
12568 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
12569 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
12570 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
12576 /* unsigned 3 argument functions. */
12577 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
12578 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
12579 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
12580 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
12581 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
12582 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
12583 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
12584 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
12585 case VSX_BUILTIN_VPERM_16QI_UNS
:
12586 case VSX_BUILTIN_VPERM_8HI_UNS
:
12587 case VSX_BUILTIN_VPERM_4SI_UNS
:
12588 case VSX_BUILTIN_VPERM_2DI_UNS
:
12589 case VSX_BUILTIN_XXSEL_16QI_UNS
:
12590 case VSX_BUILTIN_XXSEL_8HI_UNS
:
12591 case VSX_BUILTIN_XXSEL_4SI_UNS
:
12592 case VSX_BUILTIN_XXSEL_2DI_UNS
:
12599 /* signed permute functions with unsigned char mask. */
12600 case ALTIVEC_BUILTIN_VPERM_16QI
:
12601 case ALTIVEC_BUILTIN_VPERM_8HI
:
12602 case ALTIVEC_BUILTIN_VPERM_4SI
:
12603 case ALTIVEC_BUILTIN_VPERM_4SF
:
12604 case ALTIVEC_BUILTIN_VPERM_2DI
:
12605 case ALTIVEC_BUILTIN_VPERM_2DF
:
12606 case VSX_BUILTIN_VPERM_16QI
:
12607 case VSX_BUILTIN_VPERM_8HI
:
12608 case VSX_BUILTIN_VPERM_4SI
:
12609 case VSX_BUILTIN_VPERM_4SF
:
12610 case VSX_BUILTIN_VPERM_2DI
:
12611 case VSX_BUILTIN_VPERM_2DF
:
12615 /* unsigned args, signed return. */
12616 case VSX_BUILTIN_XVCVUXDDP_UNS
:
12617 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
12621 /* signed args, unsigned return. */
12622 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
12623 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
12631 /* Figure out how many args are present. */
12632 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
12636 fatal_error ("internal error: builtin function %s had no type", name
);
12638 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
12639 if (!ret_type
&& h
.uns_p
[0])
12640 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
12643 fatal_error ("internal error: builtin function %s had an unexpected "
12644 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
12646 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
12647 arg_type
[i
] = NULL_TREE
;
12649 for (i
= 0; i
< num_args
; i
++)
12651 int m
= (int) h
.mode
[i
+1];
12652 int uns_p
= h
.uns_p
[i
+1];
12654 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
12655 if (!arg_type
[i
] && uns_p
)
12656 arg_type
[i
] = builtin_mode_to_type
[m
][0];
12659 fatal_error ("internal error: builtin function %s, argument %d "
12660 "had unexpected argument type %s", name
, i
,
12661 GET_MODE_NAME (m
));
12664 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
12665 if (*found
== NULL
)
12667 h2
= ggc_alloc_builtin_hash_struct ();
12669 *found
= (void *)h2
;
12671 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
12672 arg_type
[2], NULL_TREE
);
12675 return ((struct builtin_hash_struct
*)(*found
))->type
;
12679 rs6000_common_init_builtins (void)
12681 const struct builtin_description
*d
;
12684 tree opaque_ftype_opaque
= NULL_TREE
;
12685 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
12686 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
12687 tree v2si_ftype_qi
= NULL_TREE
;
12688 tree v2si_ftype_v2si_qi
= NULL_TREE
;
12689 tree v2si_ftype_int_qi
= NULL_TREE
;
12690 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
12692 if (!TARGET_PAIRED_FLOAT
)
12694 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
12695 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
12698 /* Paired and SPE builtins are only available if you build a compiler with
12699 the appropriate options, so only create those builtins with the
12700 appropriate compiler option. Create Altivec and VSX builtins on machines
12701 with at least the general purpose extensions (970 and newer) to allow the
12702 use of the target attribute.. */
12704 if (TARGET_EXTRA_BUILTINS
)
12705 builtin_mask
|= RS6000_BTM_COMMON
;
12707 /* Add the ternary operators. */
12709 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
12712 HOST_WIDE_INT mask
= d
->mask
;
12714 if ((mask
& builtin_mask
) != mask
)
12716 if (TARGET_DEBUG_BUILTIN
)
12717 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
12721 if (rs6000_overloaded_builtin_p (d
->code
))
12723 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
12724 type
= opaque_ftype_opaque_opaque_opaque
12725 = build_function_type_list (opaque_V4SI_type_node
,
12726 opaque_V4SI_type_node
,
12727 opaque_V4SI_type_node
,
12728 opaque_V4SI_type_node
,
12733 enum insn_code icode
= d
->icode
;
12734 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12737 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
12738 insn_data
[icode
].operand
[1].mode
,
12739 insn_data
[icode
].operand
[2].mode
,
12740 insn_data
[icode
].operand
[3].mode
,
12744 def_builtin (d
->name
, type
, d
->code
);
12747 /* Add the binary operators. */
12749 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12751 enum machine_mode mode0
, mode1
, mode2
;
12753 HOST_WIDE_INT mask
= d
->mask
;
12755 if ((mask
& builtin_mask
) != mask
)
12757 if (TARGET_DEBUG_BUILTIN
)
12758 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
12762 if (rs6000_overloaded_builtin_p (d
->code
))
12764 if (! (type
= opaque_ftype_opaque_opaque
))
12765 type
= opaque_ftype_opaque_opaque
12766 = build_function_type_list (opaque_V4SI_type_node
,
12767 opaque_V4SI_type_node
,
12768 opaque_V4SI_type_node
,
12773 enum insn_code icode
= d
->icode
;
12774 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12777 mode0
= insn_data
[icode
].operand
[0].mode
;
12778 mode1
= insn_data
[icode
].operand
[1].mode
;
12779 mode2
= insn_data
[icode
].operand
[2].mode
;
12781 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
12783 if (! (type
= v2si_ftype_v2si_qi
))
12784 type
= v2si_ftype_v2si_qi
12785 = build_function_type_list (opaque_V2SI_type_node
,
12786 opaque_V2SI_type_node
,
12791 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
12792 && mode2
== QImode
)
12794 if (! (type
= v2si_ftype_int_qi
))
12795 type
= v2si_ftype_int_qi
12796 = build_function_type_list (opaque_V2SI_type_node
,
12803 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
12807 def_builtin (d
->name
, type
, d
->code
);
12810 /* Add the simple unary operators. */
12812 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12814 enum machine_mode mode0
, mode1
;
12816 HOST_WIDE_INT mask
= d
->mask
;
12818 if ((mask
& builtin_mask
) != mask
)
12820 if (TARGET_DEBUG_BUILTIN
)
12821 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
12825 if (rs6000_overloaded_builtin_p (d
->code
))
12827 if (! (type
= opaque_ftype_opaque
))
12828 type
= opaque_ftype_opaque
12829 = build_function_type_list (opaque_V4SI_type_node
,
12830 opaque_V4SI_type_node
,
12835 enum insn_code icode
= d
->icode
;
12836 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12839 mode0
= insn_data
[icode
].operand
[0].mode
;
12840 mode1
= insn_data
[icode
].operand
[1].mode
;
12842 if (mode0
== V2SImode
&& mode1
== QImode
)
12844 if (! (type
= v2si_ftype_qi
))
12845 type
= v2si_ftype_qi
12846 = build_function_type_list (opaque_V2SI_type_node
,
12852 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
12856 def_builtin (d
->name
, type
, d
->code
);
12861 rs6000_init_libfuncs (void)
12863 if (!TARGET_IEEEQUAD
)
12864 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12865 if (!TARGET_XL_COMPAT
)
12867 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
12868 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
12869 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
12870 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
12872 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
12874 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
12875 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
12876 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
12877 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
12878 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
12879 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
12880 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
12882 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
12883 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
12884 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
12885 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
12886 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
12887 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
12888 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
12889 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
12892 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
12893 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
12897 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
12898 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
12899 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
12900 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
12904 /* 32-bit SVR4 quad floating point routines. */
12906 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
12907 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
12908 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
12909 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
12910 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
12911 if (TARGET_PPC_GPOPT
)
12912 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
12914 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
12915 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
12916 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
12917 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
12918 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
12919 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
12921 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
12922 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
12923 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
12924 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
12925 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
12926 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
12927 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
12928 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
12933 /* Expand a block clear operation, and return 1 if successful. Return 0
12934 if we should let the compiler generate normal code.
12936 operands[0] is the destination
12937 operands[1] is the length
12938 operands[3] is the alignment */
12941 expand_block_clear (rtx operands
[])
12943 rtx orig_dest
= operands
[0];
12944 rtx bytes_rtx
= operands
[1];
12945 rtx align_rtx
= operands
[3];
12946 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
12947 HOST_WIDE_INT align
;
12948 HOST_WIDE_INT bytes
;
12953 /* If this is not a fixed size move, just call memcpy */
12957 /* This must be a fixed size alignment */
12958 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
12959 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
12961 /* Anything to clear? */
12962 bytes
= INTVAL (bytes_rtx
);
12966 /* Use the builtin memset after a point, to avoid huge code bloat.
12967 When optimize_size, avoid any significant code bloat; calling
12968 memset is about 4 instructions, so allow for one instruction to
12969 load zero and three to do clearing. */
12970 if (TARGET_ALTIVEC
&& align
>= 128)
12972 else if (TARGET_POWERPC64
&& align
>= 32)
12974 else if (TARGET_SPE
&& align
>= 64)
12979 if (optimize_size
&& bytes
> 3 * clear_step
)
12981 if (! optimize_size
&& bytes
> 8 * clear_step
)
12984 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
12986 enum machine_mode mode
= BLKmode
;
12989 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
12994 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
12999 else if (bytes
>= 8 && TARGET_POWERPC64
13000 /* 64-bit loads and stores require word-aligned
13002 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
13007 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
13008 { /* move 4 bytes */
13012 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
13013 { /* move 2 bytes */
13017 else /* move 1 byte at a time */
13023 dest
= adjust_address (orig_dest
, mode
, offset
);
13025 emit_move_insn (dest
, CONST0_RTX (mode
));
13032 /* Expand a block move operation, and return 1 if successful. Return 0
13033 if we should let the compiler generate normal code.
13035 operands[0] is the destination
13036 operands[1] is the source
13037 operands[2] is the length
13038 operands[3] is the alignment */
13040 #define MAX_MOVE_REG 4
13043 expand_block_move (rtx operands
[])
13045 rtx orig_dest
= operands
[0];
13046 rtx orig_src
= operands
[1];
13047 rtx bytes_rtx
= operands
[2];
13048 rtx align_rtx
= operands
[3];
13049 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
13054 rtx stores
[MAX_MOVE_REG
];
13057 /* If this is not a fixed size move, just call memcpy */
13061 /* This must be a fixed size alignment */
13062 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
13063 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
13065 /* Anything to move? */
13066 bytes
= INTVAL (bytes_rtx
);
13070 if (bytes
> rs6000_block_move_inline_limit
)
13073 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
13076 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
13077 rtx (*mov
) (rtx
, rtx
);
13079 enum machine_mode mode
= BLKmode
;
13082 /* Altivec first, since it will be faster than a string move
13083 when it applies, and usually not significantly larger. */
13084 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
13088 gen_func
.mov
= gen_movv4si
;
13090 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
13094 gen_func
.mov
= gen_movv2si
;
13096 else if (TARGET_STRING
13097 && bytes
> 24 /* move up to 32 bytes at a time */
13103 && ! fixed_regs
[10]
13104 && ! fixed_regs
[11]
13105 && ! fixed_regs
[12])
13107 move_bytes
= (bytes
> 32) ? 32 : bytes
;
13108 gen_func
.movmemsi
= gen_movmemsi_8reg
;
13110 else if (TARGET_STRING
13111 && bytes
> 16 /* move up to 24 bytes at a time */
13117 && ! fixed_regs
[10])
13119 move_bytes
= (bytes
> 24) ? 24 : bytes
;
13120 gen_func
.movmemsi
= gen_movmemsi_6reg
;
13122 else if (TARGET_STRING
13123 && bytes
> 8 /* move up to 16 bytes at a time */
13127 && ! fixed_regs
[8])
13129 move_bytes
= (bytes
> 16) ? 16 : bytes
;
13130 gen_func
.movmemsi
= gen_movmemsi_4reg
;
13132 else if (bytes
>= 8 && TARGET_POWERPC64
13133 /* 64-bit loads and stores require word-aligned
13135 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
13139 gen_func
.mov
= gen_movdi
;
13141 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
13142 { /* move up to 8 bytes at a time */
13143 move_bytes
= (bytes
> 8) ? 8 : bytes
;
13144 gen_func
.movmemsi
= gen_movmemsi_2reg
;
13146 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
13147 { /* move 4 bytes */
13150 gen_func
.mov
= gen_movsi
;
13152 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
13153 { /* move 2 bytes */
13156 gen_func
.mov
= gen_movhi
;
13158 else if (TARGET_STRING
&& bytes
> 1)
13159 { /* move up to 4 bytes at a time */
13160 move_bytes
= (bytes
> 4) ? 4 : bytes
;
13161 gen_func
.movmemsi
= gen_movmemsi_1reg
;
13163 else /* move 1 byte at a time */
13167 gen_func
.mov
= gen_movqi
;
13170 src
= adjust_address (orig_src
, mode
, offset
);
13171 dest
= adjust_address (orig_dest
, mode
, offset
);
13173 if (mode
!= BLKmode
)
13175 rtx tmp_reg
= gen_reg_rtx (mode
);
13177 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
13178 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
13181 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
13184 for (i
= 0; i
< num_reg
; i
++)
13185 emit_insn (stores
[i
]);
13189 if (mode
== BLKmode
)
13191 /* Move the address into scratch registers. The movmemsi
13192 patterns require zero offset. */
13193 if (!REG_P (XEXP (src
, 0)))
13195 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
13196 src
= replace_equiv_address (src
, src_reg
);
13198 set_mem_size (src
, move_bytes
);
13200 if (!REG_P (XEXP (dest
, 0)))
13202 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
13203 dest
= replace_equiv_address (dest
, dest_reg
);
13205 set_mem_size (dest
, move_bytes
);
13207 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
13208 GEN_INT (move_bytes
& 31),
13217 /* Return a string to perform a load_multiple operation.
13218 operands[0] is the vector.
13219 operands[1] is the source address.
13220 operands[2] is the first destination register. */
13223 rs6000_output_load_multiple (rtx operands
[3])
13225 /* We have to handle the case where the pseudo used to contain the address
13226 is assigned to one of the output registers. */
13228 int words
= XVECLEN (operands
[0], 0);
13231 if (XVECLEN (operands
[0], 0) == 1)
13232 return "lwz %2,0(%1)";
13234 for (i
= 0; i
< words
; i
++)
13235 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
13236 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
13240 xop
[0] = GEN_INT (4 * (words
-1));
13241 xop
[1] = operands
[1];
13242 xop
[2] = operands
[2];
13243 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
13248 xop
[0] = GEN_INT (4 * (words
-1));
13249 xop
[1] = operands
[1];
13250 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
13251 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
13256 for (j
= 0; j
< words
; j
++)
13259 xop
[0] = GEN_INT (j
* 4);
13260 xop
[1] = operands
[1];
13261 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
13262 output_asm_insn ("lwz %2,%0(%1)", xop
);
13264 xop
[0] = GEN_INT (i
* 4);
13265 xop
[1] = operands
[1];
13266 output_asm_insn ("lwz %1,%0(%1)", xop
);
13271 return "lswi %2,%1,%N0";
13275 /* A validation routine: say whether CODE, a condition code, and MODE
13276 match. The other alternatives either don't make sense or should
13277 never be generated. */
13280 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
13282 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
13283 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
13284 && GET_MODE_CLASS (mode
) == MODE_CC
);
13286 /* These don't make sense. */
13287 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
13288 || mode
!= CCUNSmode
);
13290 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
13291 || mode
== CCUNSmode
);
13293 gcc_assert (mode
== CCFPmode
13294 || (code
!= ORDERED
&& code
!= UNORDERED
13295 && code
!= UNEQ
&& code
!= LTGT
13296 && code
!= UNGT
&& code
!= UNLT
13297 && code
!= UNGE
&& code
!= UNLE
));
13299 /* These should never be generated except for
13300 flag_finite_math_only. */
13301 gcc_assert (mode
!= CCFPmode
13302 || flag_finite_math_only
13303 || (code
!= LE
&& code
!= GE
13304 && code
!= UNEQ
&& code
!= LTGT
13305 && code
!= UNGT
&& code
!= UNLT
));
13307 /* These are invalid; the information is not there. */
13308 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
13312 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13313 mask required to convert the result of a rotate insn into a shift
13314 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13317 includes_lshift_p (rtx shiftop
, rtx andop
)
13319 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13321 shift_mask
<<= INTVAL (shiftop
);
13323 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13326 /* Similar, but for right shift. */
13329 includes_rshift_p (rtx shiftop
, rtx andop
)
13331 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13333 shift_mask
>>= INTVAL (shiftop
);
13335 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13338 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13339 to perform a left shift. It must have exactly SHIFTOP least
13340 significant 0's, then one or more 1's, then zero or more 0's. */
13343 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
13345 if (GET_CODE (andop
) == CONST_INT
)
13347 HOST_WIDE_INT c
, lsb
, shift_mask
;
13349 c
= INTVAL (andop
);
13350 if (c
== 0 || c
== ~0)
13354 shift_mask
<<= INTVAL (shiftop
);
13356 /* Find the least significant one bit. */
13359 /* It must coincide with the LSB of the shift mask. */
13360 if (-lsb
!= shift_mask
)
13363 /* Invert to look for the next transition (if any). */
13366 /* Remove the low group of ones (originally low group of zeros). */
13369 /* Again find the lsb, and check we have all 1's above. */
13373 else if (GET_CODE (andop
) == CONST_DOUBLE
13374 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
13376 HOST_WIDE_INT low
, high
, lsb
;
13377 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
13379 low
= CONST_DOUBLE_LOW (andop
);
13380 if (HOST_BITS_PER_WIDE_INT
< 64)
13381 high
= CONST_DOUBLE_HIGH (andop
);
13383 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
13384 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
13387 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
13389 shift_mask_high
= ~0;
13390 if (INTVAL (shiftop
) > 32)
13391 shift_mask_high
<<= INTVAL (shiftop
) - 32;
13393 lsb
= high
& -high
;
13395 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
13401 lsb
= high
& -high
;
13402 return high
== -lsb
;
13405 shift_mask_low
= ~0;
13406 shift_mask_low
<<= INTVAL (shiftop
);
13410 if (-lsb
!= shift_mask_low
)
13413 if (HOST_BITS_PER_WIDE_INT
< 64)
13418 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
13420 lsb
= high
& -high
;
13421 return high
== -lsb
;
13425 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
13431 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13432 to perform a left shift. It must have SHIFTOP or more least
13433 significant 0's, with the remainder of the word 1's. */
13436 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
13438 if (GET_CODE (andop
) == CONST_INT
)
13440 HOST_WIDE_INT c
, lsb
, shift_mask
;
13443 shift_mask
<<= INTVAL (shiftop
);
13444 c
= INTVAL (andop
);
13446 /* Find the least significant one bit. */
13449 /* It must be covered by the shift mask.
13450 This test also rejects c == 0. */
13451 if ((lsb
& shift_mask
) == 0)
13454 /* Check we have all 1's above the transition, and reject all 1's. */
13455 return c
== -lsb
&& lsb
!= 1;
13457 else if (GET_CODE (andop
) == CONST_DOUBLE
13458 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
13460 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
13462 low
= CONST_DOUBLE_LOW (andop
);
13464 if (HOST_BITS_PER_WIDE_INT
< 64)
13466 HOST_WIDE_INT high
, shift_mask_high
;
13468 high
= CONST_DOUBLE_HIGH (andop
);
13472 shift_mask_high
= ~0;
13473 if (INTVAL (shiftop
) > 32)
13474 shift_mask_high
<<= INTVAL (shiftop
) - 32;
13476 lsb
= high
& -high
;
13478 if ((lsb
& shift_mask_high
) == 0)
13481 return high
== -lsb
;
13487 shift_mask_low
= ~0;
13488 shift_mask_low
<<= INTVAL (shiftop
);
13492 if ((lsb
& shift_mask_low
) == 0)
13495 return low
== -lsb
&& lsb
!= 1;
13501 /* Return 1 if operands will generate a valid arguments to rlwimi
13502 instruction for insert with right shift in 64-bit mode. The mask may
13503 not start on the first bit or stop on the last bit because wrap-around
13504 effects of instruction do not correspond to semantics of RTL insn. */
13507 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
13509 if (INTVAL (startop
) > 32
13510 && INTVAL (startop
) < 64
13511 && INTVAL (sizeop
) > 1
13512 && INTVAL (sizeop
) + INTVAL (startop
) < 64
13513 && INTVAL (shiftop
) > 0
13514 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
13515 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
13521 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13522 for lfq and stfq insns iff the registers are hard registers. */
13525 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
13527 /* We might have been passed a SUBREG. */
13528 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
13531 /* We might have been passed non floating point registers. */
13532 if (!FP_REGNO_P (REGNO (reg1
))
13533 || !FP_REGNO_P (REGNO (reg2
)))
13536 return (REGNO (reg1
) == REGNO (reg2
) - 1);
13539 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13540 addr1 and addr2 must be in consecutive memory locations
13541 (addr2 == addr1 + 8). */
13544 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
13547 unsigned int reg1
, reg2
;
13548 int offset1
, offset2
;
13550 /* The mems cannot be volatile. */
13551 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
13554 addr1
= XEXP (mem1
, 0);
13555 addr2
= XEXP (mem2
, 0);
13557 /* Extract an offset (if used) from the first addr. */
13558 if (GET_CODE (addr1
) == PLUS
)
13560 /* If not a REG, return zero. */
13561 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
13565 reg1
= REGNO (XEXP (addr1
, 0));
13566 /* The offset must be constant! */
13567 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
13569 offset1
= INTVAL (XEXP (addr1
, 1));
13572 else if (GET_CODE (addr1
) != REG
)
13576 reg1
= REGNO (addr1
);
13577 /* This was a simple (mem (reg)) expression. Offset is 0. */
13581 /* And now for the second addr. */
13582 if (GET_CODE (addr2
) == PLUS
)
13584 /* If not a REG, return zero. */
13585 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
13589 reg2
= REGNO (XEXP (addr2
, 0));
13590 /* The offset must be constant. */
13591 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
13593 offset2
= INTVAL (XEXP (addr2
, 1));
13596 else if (GET_CODE (addr2
) != REG
)
13600 reg2
= REGNO (addr2
);
13601 /* This was a simple (mem (reg)) expression. Offset is 0. */
13605 /* Both of these must have the same base register. */
13609 /* The offset for the second addr must be 8 more than the first addr. */
13610 if (offset2
!= offset1
+ 8)
13613 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13620 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
13622 static bool eliminated
= false;
13625 if (mode
!= SDmode
)
13626 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
13629 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
13630 gcc_assert (mem
!= NULL_RTX
);
13634 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
13635 cfun
->machine
->sdmode_stack_slot
= mem
;
13641 if (TARGET_DEBUG_ADDR
)
13643 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13644 GET_MODE_NAME (mode
));
13646 fprintf (stderr
, "\tNULL_RTX\n");
13655 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
13657 /* Don't walk into types. */
13658 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
13660 *walk_subtrees
= 0;
13664 switch (TREE_CODE (*tp
))
13673 case VIEW_CONVERT_EXPR
:
13674 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
13684 enum reload_reg_type
{
13686 VECTOR_REGISTER_TYPE
,
13687 OTHER_REGISTER_TYPE
13690 static enum reload_reg_type
13691 rs6000_reload_register_type (enum reg_class rclass
)
13697 return GPR_REGISTER_TYPE
;
13702 return VECTOR_REGISTER_TYPE
;
13705 return OTHER_REGISTER_TYPE
;
13709 /* Inform reload about cases where moving X with a mode MODE to a register in
13710 RCLASS requires an extra scratch or immediate register. Return the class
13711 needed for the immediate register.
13713 For VSX and Altivec, we may need a register to convert sp+offset into
13716 For misaligned 64-bit gpr loads and stores we need a register to
13717 convert an offset address to indirect. */
13720 rs6000_secondary_reload (bool in_p
,
13722 reg_class_t rclass_i
,
13723 enum machine_mode mode
,
13724 secondary_reload_info
*sri
)
13726 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13727 reg_class_t ret
= ALL_REGS
;
13728 enum insn_code icode
;
13729 bool default_p
= false;
13731 sri
->icode
= CODE_FOR_nothing
;
13733 /* Convert vector loads and stores into gprs to use an additional base
13735 icode
= rs6000_vector_reload
[mode
][in_p
!= false];
13736 if (icode
!= CODE_FOR_nothing
)
13739 sri
->icode
= CODE_FOR_nothing
;
13740 sri
->extra_cost
= 0;
13742 if (GET_CODE (x
) == MEM
)
13744 rtx addr
= XEXP (x
, 0);
13746 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13747 an extra register in that case, but it would need an extra
13748 register if the addressing is reg+reg or (reg+reg)&(-16). */
13749 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
13751 if (!legitimate_indirect_address_p (addr
, false)
13752 && !rs6000_legitimate_offset_address_p (TImode
, addr
,
13755 sri
->icode
= icode
;
13756 /* account for splitting the loads, and converting the
13757 address from reg+reg to reg. */
13758 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
13759 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
13762 /* Loads to and stores from vector registers can only do reg+reg
13763 addressing. Altivec registers can also do (reg+reg)&(-16). */
13764 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
13765 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
13767 if (!VECTOR_MEM_ALTIVEC_P (mode
)
13768 && GET_CODE (addr
) == AND
13769 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
13770 && INTVAL (XEXP (addr
, 1)) == -16
13771 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
13772 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
13774 sri
->icode
= icode
;
13775 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
13778 else if (!legitimate_indirect_address_p (addr
, false)
13779 && (rclass
== NO_REGS
13780 || !legitimate_indexed_address_p (addr
, false)))
13782 sri
->icode
= icode
;
13783 sri
->extra_cost
= 1;
13786 icode
= CODE_FOR_nothing
;
13788 /* Any other loads, including to pseudo registers which haven't been
13789 assigned to a register yet, default to require a scratch
13793 sri
->icode
= icode
;
13794 sri
->extra_cost
= 2;
13797 else if (REG_P (x
))
13799 int regno
= true_regnum (x
);
13801 icode
= CODE_FOR_nothing
;
13802 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
13806 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
13807 enum reload_reg_type rtype1
= rs6000_reload_register_type (rclass
);
13808 enum reload_reg_type rtype2
= rs6000_reload_register_type (xclass
);
13810 /* If memory is needed, use default_secondary_reload to create the
13812 if (rtype1
!= rtype2
|| rtype1
== OTHER_REGISTER_TYPE
)
13821 else if (TARGET_POWERPC64
13822 && rs6000_reload_register_type (rclass
) == GPR_REGISTER_TYPE
13824 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
13826 rtx off
= address_offset (XEXP (x
, 0));
13827 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
13829 if (off
!= NULL_RTX
13830 && (INTVAL (off
) & 3) != 0
13831 && (unsigned HOST_WIDE_INT
) INTVAL (off
) + 0x8000 < 0x10000 - extra
)
13834 sri
->icode
= CODE_FOR_reload_di_load
;
13836 sri
->icode
= CODE_FOR_reload_di_store
;
13837 sri
->extra_cost
= 2;
13843 else if (!TARGET_POWERPC64
13844 && rs6000_reload_register_type (rclass
) == GPR_REGISTER_TYPE
13846 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
13848 rtx off
= address_offset (XEXP (x
, 0));
13849 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
13851 /* We need a secondary reload only when our legitimate_address_p
13852 says the address is good (as otherwise the entire address
13853 will be reloaded). So for mode sizes of 8 and 16 this will
13854 be when the offset is in the ranges [0x7ffc,0x7fff] and
13855 [0x7ff4,0x7ff7] respectively. Note that the address we see
13856 here may have been manipulated by legitimize_reload_address. */
13857 if (off
!= NULL_RTX
13858 && ((unsigned HOST_WIDE_INT
) INTVAL (off
) - (0x8000 - extra
)
13862 sri
->icode
= CODE_FOR_reload_si_load
;
13864 sri
->icode
= CODE_FOR_reload_si_store
;
13865 sri
->extra_cost
= 2;
13875 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
13877 gcc_assert (ret
!= ALL_REGS
);
13879 if (TARGET_DEBUG_ADDR
)
13882 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13884 reg_class_names
[ret
],
13885 in_p
? "true" : "false",
13886 reg_class_names
[rclass
],
13887 GET_MODE_NAME (mode
));
13890 fprintf (stderr
, ", default secondary reload");
13892 if (sri
->icode
!= CODE_FOR_nothing
)
13893 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
13894 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
13896 fprintf (stderr
, "\n");
13904 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13905 to SP+reg addressing. */
13908 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
13910 int regno
= true_regnum (reg
);
13911 enum machine_mode mode
= GET_MODE (reg
);
13912 enum reg_class rclass
;
13914 rtx and_op2
= NULL_RTX
;
13917 rtx scratch_or_premodify
= scratch
;
13921 if (TARGET_DEBUG_ADDR
)
13923 fprintf (stderr
, "\nrs6000_secondary_reload_inner, type = %s\n",
13924 store_p
? "store" : "load");
13925 fprintf (stderr
, "reg:\n");
13927 fprintf (stderr
, "mem:\n");
13929 fprintf (stderr
, "scratch:\n");
13930 debug_rtx (scratch
);
13933 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
13934 gcc_assert (GET_CODE (mem
) == MEM
);
13935 rclass
= REGNO_REG_CLASS (regno
);
13936 addr
= XEXP (mem
, 0);
13940 /* GPRs can handle reg + small constant, all other addresses need to use
13941 the scratch register. */
13944 if (GET_CODE (addr
) == AND
)
13946 and_op2
= XEXP (addr
, 1);
13947 addr
= XEXP (addr
, 0);
13950 if (GET_CODE (addr
) == PRE_MODIFY
)
13952 scratch_or_premodify
= XEXP (addr
, 0);
13953 gcc_assert (REG_P (scratch_or_premodify
));
13954 gcc_assert (GET_CODE (XEXP (addr
, 1)) == PLUS
);
13955 addr
= XEXP (addr
, 1);
13958 if (GET_CODE (addr
) == PLUS
13959 && (and_op2
!= NULL_RTX
13960 || !rs6000_legitimate_offset_address_p (TImode
, addr
,
13963 addr_op1
= XEXP (addr
, 0);
13964 addr_op2
= XEXP (addr
, 1);
13965 gcc_assert (legitimate_indirect_address_p (addr_op1
, false));
13967 if (!REG_P (addr_op2
)
13968 && (GET_CODE (addr_op2
) != CONST_INT
13969 || !satisfies_constraint_I (addr_op2
)))
13971 if (TARGET_DEBUG_ADDR
)
13974 "\nMove plus addr to register %s, mode = %s: ",
13975 rs6000_reg_names
[REGNO (scratch
)],
13976 GET_MODE_NAME (mode
));
13977 debug_rtx (addr_op2
);
13979 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
13980 addr_op2
= scratch
;
13983 emit_insn (gen_rtx_SET (VOIDmode
,
13984 scratch_or_premodify
,
13985 gen_rtx_PLUS (Pmode
,
13989 addr
= scratch_or_premodify
;
13990 scratch_or_premodify
= scratch
;
13992 else if (!legitimate_indirect_address_p (addr
, false)
13993 && !rs6000_legitimate_offset_address_p (TImode
, addr
,
13996 if (TARGET_DEBUG_ADDR
)
13998 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
13999 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
14000 GET_MODE_NAME (mode
));
14003 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14004 addr
= scratch_or_premodify
;
14005 scratch_or_premodify
= scratch
;
14009 /* Float/Altivec registers can only handle reg+reg addressing. Move
14010 other addresses into a scratch register. */
14015 /* With float regs, we need to handle the AND ourselves, since we can't
14016 use the Altivec instruction with an implicit AND -16. Allow scalar
14017 loads to float registers to use reg+offset even if VSX. */
14018 if (GET_CODE (addr
) == AND
14019 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
14020 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
14021 || INTVAL (XEXP (addr
, 1)) != -16
14022 || !VECTOR_MEM_ALTIVEC_P (mode
)))
14024 and_op2
= XEXP (addr
, 1);
14025 addr
= XEXP (addr
, 0);
14028 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
14029 as the address later. */
14030 if (GET_CODE (addr
) == PRE_MODIFY
14031 && (!VECTOR_MEM_VSX_P (mode
)
14032 || and_op2
!= NULL_RTX
14033 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
14035 scratch_or_premodify
= XEXP (addr
, 0);
14036 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify
,
14038 gcc_assert (GET_CODE (XEXP (addr
, 1)) == PLUS
);
14039 addr
= XEXP (addr
, 1);
14042 if (legitimate_indirect_address_p (addr
, false) /* reg */
14043 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
14044 || GET_CODE (addr
) == PRE_MODIFY
/* VSX pre-modify */
14045 || (GET_CODE (addr
) == AND
/* Altivec memory */
14046 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
14047 && INTVAL (XEXP (addr
, 1)) == -16
14048 && VECTOR_MEM_ALTIVEC_P (mode
))
14049 || (rclass
== FLOAT_REGS
/* legacy float mem */
14050 && GET_MODE_SIZE (mode
) == 8
14051 && and_op2
== NULL_RTX
14052 && scratch_or_premodify
== scratch
14053 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
14056 else if (GET_CODE (addr
) == PLUS
)
14058 addr_op1
= XEXP (addr
, 0);
14059 addr_op2
= XEXP (addr
, 1);
14060 gcc_assert (REG_P (addr_op1
));
14062 if (TARGET_DEBUG_ADDR
)
14064 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
14065 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
14066 debug_rtx (addr_op2
);
14068 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
14069 emit_insn (gen_rtx_SET (VOIDmode
,
14070 scratch_or_premodify
,
14071 gen_rtx_PLUS (Pmode
,
14074 addr
= scratch_or_premodify
;
14075 scratch_or_premodify
= scratch
;
14078 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
14079 || GET_CODE (addr
) == CONST_INT
|| REG_P (addr
))
14081 if (TARGET_DEBUG_ADDR
)
14083 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
14084 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
14085 GET_MODE_NAME (mode
));
14089 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14090 addr
= scratch_or_premodify
;
14091 scratch_or_premodify
= scratch
;
14095 gcc_unreachable ();
14100 gcc_unreachable ();
14103 /* If the original address involved a pre-modify that we couldn't use the VSX
14104 memory instruction with update, and we haven't taken care of already,
14105 store the address in the pre-modify register and use that as the
14107 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
14109 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
14110 addr
= scratch_or_premodify
;
14113 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
14114 memory instruction, recreate the AND now, including the clobber which is
14115 generated by the general ANDSI3/ANDDI3 patterns for the
14116 andi. instruction. */
14117 if (and_op2
!= NULL_RTX
)
14119 if (! legitimate_indirect_address_p (addr
, false))
14121 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
14125 if (TARGET_DEBUG_ADDR
)
14127 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
14128 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
14129 debug_rtx (and_op2
);
14132 and_rtx
= gen_rtx_SET (VOIDmode
,
14134 gen_rtx_AND (Pmode
,
14138 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
14139 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
14140 gen_rtvec (2, and_rtx
, cc_clobber
)));
14144 /* Adjust the address if it changed. */
14145 if (addr
!= XEXP (mem
, 0))
14147 mem
= change_address (mem
, mode
, addr
);
14148 if (TARGET_DEBUG_ADDR
)
14149 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14152 /* Now create the move. */
14154 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14156 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14161 /* Convert reloads involving 64-bit gprs and misaligned offset
14162 addressing, or multiple 32-bit gprs and offsets that are too large,
14163 to use indirect addressing. */
14166 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
14168 int regno
= true_regnum (reg
);
14169 enum reg_class rclass
;
14171 rtx scratch_or_premodify
= scratch
;
14173 if (TARGET_DEBUG_ADDR
)
14175 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
14176 store_p
? "store" : "load");
14177 fprintf (stderr
, "reg:\n");
14179 fprintf (stderr
, "mem:\n");
14181 fprintf (stderr
, "scratch:\n");
14182 debug_rtx (scratch
);
14185 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
14186 gcc_assert (GET_CODE (mem
) == MEM
);
14187 rclass
= REGNO_REG_CLASS (regno
);
14188 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
14189 addr
= XEXP (mem
, 0);
14191 if (GET_CODE (addr
) == PRE_MODIFY
)
14193 scratch_or_premodify
= XEXP (addr
, 0);
14194 gcc_assert (REG_P (scratch_or_premodify
));
14195 addr
= XEXP (addr
, 1);
14197 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
14199 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14201 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
14203 /* Now create the move. */
14205 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14207 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14212 /* Allocate a 64-bit stack slot to be used for copying SDmode
14213 values through if this function has any SDmode references. */
14216 rs6000_alloc_sdmode_stack_slot (void)
14220 gimple_stmt_iterator gsi
;
14222 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
14225 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
14227 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
14230 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
14231 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
14237 /* Check for any SDmode parameters of the function. */
14238 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
14240 if (TREE_TYPE (t
) == error_mark_node
)
14243 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
14244 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
14246 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
14247 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
14255 rs6000_instantiate_decls (void)
14257 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
14258 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
14261 /* Given an rtx X being reloaded into a reg required to be
14262 in class CLASS, return the class of reg to actually use.
14263 In general this is just CLASS; but on some machines
14264 in some cases it is preferable to use a more restrictive class.
14266 On the RS/6000, we have to return NO_REGS when we want to reload a
14267 floating-point CONST_DOUBLE to force it to be copied to memory.
14269 We also don't want to reload integer values into floating-point
14270 registers if we can at all help it. In fact, this can
14271 cause reload to die, if it tries to generate a reload of CTR
14272 into a FP register and discovers it doesn't have the memory location
14275 ??? Would it be a good idea to have reload do the converse, that is
14276 try to reload floating modes into FP registers if possible?
14279 static enum reg_class
14280 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
14282 enum machine_mode mode
= GET_MODE (x
);
14284 if (VECTOR_UNIT_VSX_P (mode
)
14285 && x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
14288 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
14289 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
14290 && easy_vector_constant (x
, mode
))
14291 return ALTIVEC_REGS
;
14293 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
14296 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
14297 return GENERAL_REGS
;
14299 /* For VSX, prefer the traditional registers for 64-bit values because we can
14300 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14301 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14302 prefer Altivec loads.. */
14303 if (rclass
== VSX_REGS
)
14305 if (GET_MODE_SIZE (mode
) <= 8)
14308 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
14309 return ALTIVEC_REGS
;
14317 /* Debug version of rs6000_preferred_reload_class. */
14318 static enum reg_class
14319 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
14321 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
14324 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14326 reg_class_names
[ret
], reg_class_names
[rclass
],
14327 GET_MODE_NAME (GET_MODE (x
)));
14333 /* If we are copying between FP or AltiVec registers and anything else, we need
14334 a memory location. The exception is when we are targeting ppc64 and the
14335 move to/from fpr to gpr instructions are available. Also, under VSX, you
14336 can copy vector registers from the FP register set to the Altivec register
14337 set and vice versa. */
14340 rs6000_secondary_memory_needed (enum reg_class class1
,
14341 enum reg_class class2
,
14342 enum machine_mode mode
)
14344 if (class1
== class2
)
14347 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14348 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14349 between these classes. But we need memory for other things that can go in
14350 FLOAT_REGS like SFmode. */
14352 && (VECTOR_MEM_VSX_P (mode
) || VECTOR_UNIT_VSX_P (mode
))
14353 && (class1
== VSX_REGS
|| class1
== ALTIVEC_REGS
14354 || class1
== FLOAT_REGS
))
14355 return (class2
!= VSX_REGS
&& class2
!= ALTIVEC_REGS
14356 && class2
!= FLOAT_REGS
);
14358 if (class1
== VSX_REGS
|| class2
== VSX_REGS
)
14361 if (class1
== FLOAT_REGS
14362 && (!TARGET_MFPGPR
|| !TARGET_POWERPC64
14363 || ((mode
!= DFmode
)
14364 && (mode
!= DDmode
)
14365 && (mode
!= DImode
))))
14368 if (class2
== FLOAT_REGS
14369 && (!TARGET_MFPGPR
|| !TARGET_POWERPC64
14370 || ((mode
!= DFmode
)
14371 && (mode
!= DDmode
)
14372 && (mode
!= DImode
))))
14375 if (class1
== ALTIVEC_REGS
|| class2
== ALTIVEC_REGS
)
14381 /* Debug version of rs6000_secondary_memory_needed. */
14383 rs6000_debug_secondary_memory_needed (enum reg_class class1
,
14384 enum reg_class class2
,
14385 enum machine_mode mode
)
14387 bool ret
= rs6000_secondary_memory_needed (class1
, class2
, mode
);
14390 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14391 "class2 = %s, mode = %s\n",
14392 ret
? "true" : "false", reg_class_names
[class1
],
14393 reg_class_names
[class2
], GET_MODE_NAME (mode
));
14398 /* Return the register class of a scratch register needed to copy IN into
14399 or out of a register in RCLASS in MODE. If it can be done directly,
14400 NO_REGS is returned. */
14402 static enum reg_class
14403 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
14408 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
14410 && MACHOPIC_INDIRECT
14414 /* We cannot copy a symbolic operand directly into anything
14415 other than BASE_REGS for TARGET_ELF. So indicate that a
14416 register from BASE_REGS is needed as an intermediate
14419 On Darwin, pic addresses require a load from memory, which
14420 needs a base register. */
14421 if (rclass
!= BASE_REGS
14422 && (GET_CODE (in
) == SYMBOL_REF
14423 || GET_CODE (in
) == HIGH
14424 || GET_CODE (in
) == LABEL_REF
14425 || GET_CODE (in
) == CONST
))
14429 if (GET_CODE (in
) == REG
)
14431 regno
= REGNO (in
);
14432 if (regno
>= FIRST_PSEUDO_REGISTER
)
14434 regno
= true_regnum (in
);
14435 if (regno
>= FIRST_PSEUDO_REGISTER
)
14439 else if (GET_CODE (in
) == SUBREG
)
14441 regno
= true_regnum (in
);
14442 if (regno
>= FIRST_PSEUDO_REGISTER
)
14448 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14450 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
14451 || (regno
>= 0 && INT_REGNO_P (regno
)))
14454 /* Constants, memory, and FP registers can go into FP registers. */
14455 if ((regno
== -1 || FP_REGNO_P (regno
))
14456 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
14457 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
14459 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14462 && (regno
== -1 || VSX_REGNO_P (regno
))
14463 && VSX_REG_CLASS_P (rclass
))
14466 /* Memory, and AltiVec registers can go into AltiVec registers. */
14467 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
14468 && rclass
== ALTIVEC_REGS
)
14471 /* We can copy among the CR registers. */
14472 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
14473 && regno
>= 0 && CR_REGNO_P (regno
))
14476 /* Otherwise, we need GENERAL_REGS. */
14477 return GENERAL_REGS
;
14480 /* Debug version of rs6000_secondary_reload_class. */
14481 static enum reg_class
14482 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
14483 enum machine_mode mode
, rtx in
)
14485 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
14487 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14488 "mode = %s, input rtx:\n",
14489 reg_class_names
[ret
], reg_class_names
[rclass
],
14490 GET_MODE_NAME (mode
));
14496 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14499 rs6000_cannot_change_mode_class (enum machine_mode from
,
14500 enum machine_mode to
,
14501 enum reg_class rclass
)
14503 unsigned from_size
= GET_MODE_SIZE (from
);
14504 unsigned to_size
= GET_MODE_SIZE (to
);
14506 if (from_size
!= to_size
)
14508 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
14509 return ((from_size
< 8 || to_size
< 8 || TARGET_IEEEQUAD
)
14510 && reg_classes_intersect_p (xclass
, rclass
));
14513 if (TARGET_E500_DOUBLE
14514 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
14515 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
14516 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
14517 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
14518 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
14521 /* Since the VSX register set includes traditional floating point registers
14522 and altivec registers, just check for the size being different instead of
14523 trying to check whether the modes are vector modes. Otherwise it won't
14524 allow say DF and DI to change classes. */
14525 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
14526 return (from_size
!= 8 && from_size
!= 16);
14528 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
14529 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
14532 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
14533 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
14539 /* Debug version of rs6000_cannot_change_mode_class. */
14541 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
14542 enum machine_mode to
,
14543 enum reg_class rclass
)
14545 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
14548 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14549 "to = %s, rclass = %s\n",
14550 ret
? "true" : "false",
14551 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
14552 reg_class_names
[rclass
]);
14557 /* Given a comparison operation, return the bit number in CCR to test. We
14558 know this is a valid comparison.
14560 SCC_P is 1 if this is for an scc. That means that %D will have been
14561 used instead of %C, so the bits will be in different places.
14563 Return -1 if OP isn't a valid comparison for some reason. */
14566 ccr_bit (rtx op
, int scc_p
)
14568 enum rtx_code code
= GET_CODE (op
);
14569 enum machine_mode cc_mode
;
14574 if (!COMPARISON_P (op
))
14577 reg
= XEXP (op
, 0);
14579 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
14581 cc_mode
= GET_MODE (reg
);
14582 cc_regnum
= REGNO (reg
);
14583 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
14585 validate_condition_mode (code
, cc_mode
);
14587 /* When generating a sCOND operation, only positive conditions are
14590 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
14591 || code
== GTU
|| code
== LTU
);
14596 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
14598 return base_bit
+ 2;
14599 case GT
: case GTU
: case UNLE
:
14600 return base_bit
+ 1;
14601 case LT
: case LTU
: case UNGE
:
14603 case ORDERED
: case UNORDERED
:
14604 return base_bit
+ 3;
14607 /* If scc, we will have done a cror to put the bit in the
14608 unordered position. So test that bit. For integer, this is ! LT
14609 unless this is an scc insn. */
14610 return scc_p
? base_bit
+ 3 : base_bit
;
14613 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
14616 gcc_unreachable ();
14620 /* Return the GOT register. */
14623 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
14625 /* The second flow pass currently (June 1999) can't update
14626 regs_ever_live without disturbing other parts of the compiler, so
14627 update it here to make the prolog/epilogue code happy. */
14628 if (!can_create_pseudo_p ()
14629 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
14630 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
14632 crtl
->uses_pic_offset_table
= 1;
14634 return pic_offset_table_rtx
;
14637 static rs6000_stack_t stack_info
;
14639 /* Function to init struct machine_function.
14640 This will be called, via a pointer variable,
14641 from push_function_context. */
14643 static struct machine_function
*
14644 rs6000_init_machine_status (void)
14646 stack_info
.reload_completed
= 0;
14647 return ggc_alloc_cleared_machine_function ();
14650 /* These macros test for integers and extract the low-order bits. */
14652 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14653 && GET_MODE (X) == VOIDmode)
14655 #define INT_LOWPART(X) \
14656 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14659 extract_MB (rtx op
)
14662 unsigned long val
= INT_LOWPART (op
);
14664 /* If the high bit is zero, the value is the first 1 bit we find
14666 if ((val
& 0x80000000) == 0)
14668 gcc_assert (val
& 0xffffffff);
14671 while (((val
<<= 1) & 0x80000000) == 0)
14676 /* If the high bit is set and the low bit is not, or the mask is all
14677 1's, the value is zero. */
14678 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
14681 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14684 while (((val
>>= 1) & 1) != 0)
14691 extract_ME (rtx op
)
14694 unsigned long val
= INT_LOWPART (op
);
14696 /* If the low bit is zero, the value is the first 1 bit we find from
14698 if ((val
& 1) == 0)
14700 gcc_assert (val
& 0xffffffff);
14703 while (((val
>>= 1) & 1) == 0)
14709 /* If the low bit is set and the high bit is not, or the mask is all
14710 1's, the value is 31. */
14711 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
14714 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14717 while (((val
<<= 1) & 0x80000000) != 0)
14723 /* Locate some local-dynamic symbol still in use by this function
14724 so that we can print its name in some tls_ld pattern. */
14726 static const char *
14727 rs6000_get_some_local_dynamic_name (void)
14731 if (cfun
->machine
->some_ld_name
)
14732 return cfun
->machine
->some_ld_name
;
14734 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14736 && for_each_rtx (&PATTERN (insn
),
14737 rs6000_get_some_local_dynamic_name_1
, 0))
14738 return cfun
->machine
->some_ld_name
;
14740 gcc_unreachable ();
14743 /* Helper function for rs6000_get_some_local_dynamic_name. */
14746 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
14750 if (GET_CODE (x
) == SYMBOL_REF
)
14752 const char *str
= XSTR (x
, 0);
14753 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
14755 cfun
->machine
->some_ld_name
= str
;
14763 /* Write out a function code label. */
14766 rs6000_output_function_entry (FILE *file
, const char *fname
)
14768 if (fname
[0] != '.')
14770 switch (DEFAULT_ABI
)
14773 gcc_unreachable ();
14779 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
14788 RS6000_OUTPUT_BASENAME (file
, fname
);
14791 /* Print an operand. Recognize special options, documented below. */
14794 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14795 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14797 #define SMALL_DATA_RELOC "sda21"
14798 #define SMALL_DATA_REG 0
14802 print_operand (FILE *file
, rtx x
, int code
)
14805 unsigned HOST_WIDE_INT uval
;
14809 /* %a is output_address. */
14812 /* If constant, low-order 16 bits of constant, unsigned.
14813 Otherwise, write normally. */
14815 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
14817 print_operand (file
, x
, 0);
14821 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14822 for 64-bit mask direction. */
14823 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
14826 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14830 /* Like 'J' but get to the GT bit only. */
14831 gcc_assert (REG_P (x
));
14833 /* Bit 1 is GT bit. */
14834 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
14836 /* Add one for shift count in rlinm for scc. */
14837 fprintf (file
, "%d", i
+ 1);
14841 /* X is a CR register. Print the number of the EQ bit of the CR */
14842 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14843 output_operand_lossage ("invalid %%E value");
14845 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
14849 /* X is a CR register. Print the shift count needed to move it
14850 to the high-order four bits. */
14851 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14852 output_operand_lossage ("invalid %%f value");
14854 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
14858 /* Similar, but print the count for the rotate in the opposite
14860 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14861 output_operand_lossage ("invalid %%F value");
14863 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
14867 /* X is a constant integer. If it is negative, print "m",
14868 otherwise print "z". This is to make an aze or ame insn. */
14869 if (GET_CODE (x
) != CONST_INT
)
14870 output_operand_lossage ("invalid %%G value");
14871 else if (INTVAL (x
) >= 0)
14878 /* If constant, output low-order five bits. Otherwise, write
14881 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
14883 print_operand (file
, x
, 0);
14887 /* If constant, output low-order six bits. Otherwise, write
14890 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
14892 print_operand (file
, x
, 0);
14896 /* Print `i' if this is a constant, else nothing. */
14902 /* Write the bit number in CCR for jump. */
14903 i
= ccr_bit (x
, 0);
14905 output_operand_lossage ("invalid %%j code");
14907 fprintf (file
, "%d", i
);
14911 /* Similar, but add one for shift count in rlinm for scc and pass
14912 scc flag to `ccr_bit'. */
14913 i
= ccr_bit (x
, 1);
14915 output_operand_lossage ("invalid %%J code");
14917 /* If we want bit 31, write a shift count of zero, not 32. */
14918 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
14922 /* X must be a constant. Write the 1's complement of the
14925 output_operand_lossage ("invalid %%k value");
14927 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
14931 /* X must be a symbolic constant on ELF. Write an
14932 expression suitable for an 'addi' that adds in the low 16
14933 bits of the MEM. */
14934 if (GET_CODE (x
) == CONST
)
14936 if (GET_CODE (XEXP (x
, 0)) != PLUS
14937 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
14938 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
14939 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
14940 output_operand_lossage ("invalid %%K value");
14942 print_operand_address (file
, x
);
14943 fputs ("@l", file
);
14946 /* %l is output_asm_label. */
14949 /* Write second word of DImode or DFmode reference. Works on register
14950 or non-indexed memory only. */
14952 fputs (reg_names
[REGNO (x
) + 1], file
);
14953 else if (MEM_P (x
))
14955 /* Handle possible auto-increment. Since it is pre-increment and
14956 we have already done it, we can just use an offset of word. */
14957 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
14958 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
14959 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
14961 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
14962 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
14965 output_address (XEXP (adjust_address_nv (x
, SImode
,
14969 if (small_data_operand (x
, GET_MODE (x
)))
14970 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
14971 reg_names
[SMALL_DATA_REG
]);
14976 /* MB value for a mask operand. */
14977 if (! mask_operand (x
, SImode
))
14978 output_operand_lossage ("invalid %%m value");
14980 fprintf (file
, "%d", extract_MB (x
));
14984 /* ME value for a mask operand. */
14985 if (! mask_operand (x
, SImode
))
14986 output_operand_lossage ("invalid %%M value");
14988 fprintf (file
, "%d", extract_ME (x
));
14991 /* %n outputs the negative of its operand. */
14994 /* Write the number of elements in the vector times 4. */
14995 if (GET_CODE (x
) != PARALLEL
)
14996 output_operand_lossage ("invalid %%N value");
14998 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
15002 /* Similar, but subtract 1 first. */
15003 if (GET_CODE (x
) != PARALLEL
)
15004 output_operand_lossage ("invalid %%O value");
15006 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
15010 /* X is a CONST_INT that is a power of two. Output the logarithm. */
15012 || INT_LOWPART (x
) < 0
15013 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
15014 output_operand_lossage ("invalid %%p value");
15016 fprintf (file
, "%d", i
);
15020 /* The operand must be an indirect memory reference. The result
15021 is the register name. */
15022 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
15023 || REGNO (XEXP (x
, 0)) >= 32)
15024 output_operand_lossage ("invalid %%P value");
15026 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
15030 /* This outputs the logical code corresponding to a boolean
15031 expression. The expression may have one or both operands
15032 negated (if one, only the first one). For condition register
15033 logical operations, it will also treat the negated
15034 CR codes as NOTs, but not handle NOTs of them. */
15036 const char *const *t
= 0;
15038 enum rtx_code code
= GET_CODE (x
);
15039 static const char * const tbl
[3][3] = {
15040 { "and", "andc", "nor" },
15041 { "or", "orc", "nand" },
15042 { "xor", "eqv", "xor" } };
15046 else if (code
== IOR
)
15048 else if (code
== XOR
)
15051 output_operand_lossage ("invalid %%q value");
15053 if (GET_CODE (XEXP (x
, 0)) != NOT
)
15057 if (GET_CODE (XEXP (x
, 1)) == NOT
)
15068 if (! TARGET_MFCRF
)
15074 /* X is a CR register. Print the mask for `mtcrf'. */
15075 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
15076 output_operand_lossage ("invalid %%R value");
15078 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
15082 /* Low 5 bits of 32 - value */
15084 output_operand_lossage ("invalid %%s value");
15086 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
15090 /* PowerPC64 mask position. All 0's is excluded.
15091 CONST_INT 32-bit mask is considered sign-extended so any
15092 transition must occur within the CONST_INT, not on the boundary. */
15093 if (! mask64_operand (x
, DImode
))
15094 output_operand_lossage ("invalid %%S value");
15096 uval
= INT_LOWPART (x
);
15098 if (uval
& 1) /* Clear Left */
15100 #if HOST_BITS_PER_WIDE_INT > 64
15101 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
15105 else /* Clear Right */
15108 #if HOST_BITS_PER_WIDE_INT > 64
15109 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
15115 gcc_assert (i
>= 0);
15116 fprintf (file
, "%d", i
);
15120 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15121 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
15123 /* Bit 3 is OV bit. */
15124 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
15126 /* If we want bit 31, write a shift count of zero, not 32. */
15127 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
15131 /* Print the symbolic name of a branch target register. */
15132 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
15133 && REGNO (x
) != CTR_REGNO
))
15134 output_operand_lossage ("invalid %%T value");
15135 else if (REGNO (x
) == LR_REGNO
)
15136 fputs ("lr", file
);
15138 fputs ("ctr", file
);
15142 /* High-order 16 bits of constant for use in unsigned operand. */
15144 output_operand_lossage ("invalid %%u value");
15146 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
15147 (INT_LOWPART (x
) >> 16) & 0xffff);
15151 /* High-order 16 bits of constant for use in signed operand. */
15153 output_operand_lossage ("invalid %%v value");
15155 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
15156 (INT_LOWPART (x
) >> 16) & 0xffff);
15160 /* Print `u' if this has an auto-increment or auto-decrement. */
15162 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
15163 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
15164 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
15169 /* Print the trap code for this operand. */
15170 switch (GET_CODE (x
))
15173 fputs ("eq", file
); /* 4 */
15176 fputs ("ne", file
); /* 24 */
15179 fputs ("lt", file
); /* 16 */
15182 fputs ("le", file
); /* 20 */
15185 fputs ("gt", file
); /* 8 */
15188 fputs ("ge", file
); /* 12 */
15191 fputs ("llt", file
); /* 2 */
15194 fputs ("lle", file
); /* 6 */
15197 fputs ("lgt", file
); /* 1 */
15200 fputs ("lge", file
); /* 5 */
15203 gcc_unreachable ();
15208 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15211 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
15212 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
15214 print_operand (file
, x
, 0);
15218 /* MB value for a PowerPC64 rldic operand. */
15219 i
= clz_hwi (GET_CODE (x
) == CONST_INT
15220 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
15222 #if HOST_BITS_PER_WIDE_INT == 32
15223 if (GET_CODE (x
) == CONST_INT
&& i
> 0)
15224 i
+= 32; /* zero-extend high-part was all 0's */
15225 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
15226 i
= clz_hwi (CONST_DOUBLE_LOW (x
)) + 32;
15229 fprintf (file
, "%d", i
);
15233 /* X is a FPR or Altivec register used in a VSX context. */
15234 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
15235 output_operand_lossage ("invalid %%x value");
15238 int reg
= REGNO (x
);
15239 int vsx_reg
= (FP_REGNO_P (reg
)
15241 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
15243 #ifdef TARGET_REGNAMES
15244 if (TARGET_REGNAMES
)
15245 fprintf (file
, "%%vs%d", vsx_reg
);
15248 fprintf (file
, "%d", vsx_reg
);
15254 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
15255 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
15256 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
15261 /* Like 'L', for third word of TImode */
15263 fputs (reg_names
[REGNO (x
) + 2], file
);
15264 else if (MEM_P (x
))
15266 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15267 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15268 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
15269 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15270 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
15272 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
15273 if (small_data_operand (x
, GET_MODE (x
)))
15274 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15275 reg_names
[SMALL_DATA_REG
]);
15280 /* X is a SYMBOL_REF. Write out the name preceded by a
15281 period and without any trailing data in brackets. Used for function
15282 names. If we are configured for System V (or the embedded ABI) on
15283 the PowerPC, do not emit the period, since those systems do not use
15284 TOCs and the like. */
15285 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
15287 /* Mark the decl as referenced so that cgraph will output the
15289 if (SYMBOL_REF_DECL (x
))
15290 mark_decl_referenced (SYMBOL_REF_DECL (x
));
15292 /* For macho, check to see if we need a stub. */
15295 const char *name
= XSTR (x
, 0);
15297 if (darwin_emit_branch_islands
15298 && MACHOPIC_INDIRECT
15299 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
15300 name
= machopic_indirection_name (x
, /*stub_p=*/true);
15302 assemble_name (file
, name
);
15304 else if (!DOT_SYMBOLS
)
15305 assemble_name (file
, XSTR (x
, 0));
15307 rs6000_output_function_entry (file
, XSTR (x
, 0));
15311 /* Like 'L', for last word of TImode. */
15313 fputs (reg_names
[REGNO (x
) + 3], file
);
15314 else if (MEM_P (x
))
15316 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15317 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15318 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
15319 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15320 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
15322 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
15323 if (small_data_operand (x
, GET_MODE (x
)))
15324 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15325 reg_names
[SMALL_DATA_REG
]);
15329 /* Print AltiVec or SPE memory operand. */
15334 gcc_assert (MEM_P (x
));
15338 /* Ugly hack because %y is overloaded. */
15339 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
15340 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
15341 || GET_MODE (x
) == TFmode
15342 || GET_MODE (x
) == TImode
))
15344 /* Handle [reg]. */
15347 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
15350 /* Handle [reg+UIMM]. */
15351 else if (GET_CODE (tmp
) == PLUS
&&
15352 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
15356 gcc_assert (REG_P (XEXP (tmp
, 0)));
15358 x
= INTVAL (XEXP (tmp
, 1));
15359 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
15363 /* Fall through. Must be [reg+reg]. */
15365 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
15366 && GET_CODE (tmp
) == AND
15367 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
15368 && INTVAL (XEXP (tmp
, 1)) == -16)
15369 tmp
= XEXP (tmp
, 0);
15370 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
15371 && GET_CODE (tmp
) == PRE_MODIFY
)
15372 tmp
= XEXP (tmp
, 1);
15374 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
15377 if (!GET_CODE (tmp
) == PLUS
15378 || !REG_P (XEXP (tmp
, 0))
15379 || !REG_P (XEXP (tmp
, 1)))
15381 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15385 if (REGNO (XEXP (tmp
, 0)) == 0)
15386 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
15387 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
15389 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
15390 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
15397 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
15398 else if (MEM_P (x
))
15400 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15401 know the width from the mode. */
15402 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
15403 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
15404 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
15405 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15406 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
15407 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
15408 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15409 output_address (XEXP (XEXP (x
, 0), 1));
15411 output_address (XEXP (x
, 0));
15415 if (toc_relative_expr_p (x
, false))
15416 /* This hack along with a corresponding hack in
15417 rs6000_output_addr_const_extra arranges to output addends
15418 where the assembler expects to find them. eg.
15419 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
15420 without this hack would be output as "x@toc+4". We
15422 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
15424 output_addr_const (file
, x
);
15429 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
15433 output_operand_lossage ("invalid %%xn code");
15437 /* Print the address of an operand. */
15440 print_operand_address (FILE *file
, rtx x
)
15443 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
15444 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
15445 || GET_CODE (x
) == LABEL_REF
)
15447 output_addr_const (file
, x
);
15448 if (small_data_operand (x
, GET_MODE (x
)))
15449 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15450 reg_names
[SMALL_DATA_REG
]);
15452 gcc_assert (!TARGET_TOC
);
15454 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
15455 && REG_P (XEXP (x
, 1)))
15457 if (REGNO (XEXP (x
, 0)) == 0)
15458 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
15459 reg_names
[ REGNO (XEXP (x
, 0)) ]);
15461 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
15462 reg_names
[ REGNO (XEXP (x
, 1)) ]);
15464 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
15465 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
15466 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
15467 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
15469 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
15470 && CONSTANT_P (XEXP (x
, 1)))
15472 fprintf (file
, "lo16(");
15473 output_addr_const (file
, XEXP (x
, 1));
15474 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15478 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
15479 && CONSTANT_P (XEXP (x
, 1)))
15481 output_addr_const (file
, XEXP (x
, 1));
15482 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15485 else if (toc_relative_expr_p (x
, false))
15487 /* This hack along with a corresponding hack in
15488 rs6000_output_addr_const_extra arranges to output addends
15489 where the assembler expects to find them. eg.
15491 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
15492 without this hack would be output as "x@toc+8@l(9)". We
15493 want "x+8@toc@l(9)". */
15494 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
15495 if (GET_CODE (x
) == LO_SUM
)
15496 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
15498 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
15501 gcc_unreachable ();
15504 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15507 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
15509 if (GET_CODE (x
) == UNSPEC
)
15510 switch (XINT (x
, 1))
15512 case UNSPEC_TOCREL
:
15513 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
15514 && REG_P (XVECEXP (x
, 0, 1))
15515 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
15516 output_addr_const (file
, XVECEXP (x
, 0, 0));
15517 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
15519 if (INTVAL (tocrel_offset
) >= 0)
15520 fprintf (file
, "+");
15521 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
15523 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
15526 assemble_name (file
, toc_label_name
);
15528 else if (TARGET_ELF
)
15529 fputs ("@toc", file
);
15533 case UNSPEC_MACHOPIC_OFFSET
:
15534 output_addr_const (file
, XVECEXP (x
, 0, 0));
15536 machopic_output_function_base_name (file
);
15543 /* Target hook for assembling integer objects. The PowerPC version has
15544 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15545 is defined. It also needs to handle DI-mode objects on 64-bit
15549 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
15551 #ifdef RELOCATABLE_NEEDS_FIXUP
15552 /* Special handling for SI values. */
15553 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
15555 static int recurse
= 0;
15557 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15558 the .fixup section. Since the TOC section is already relocated, we
15559 don't need to mark it here. We used to skip the text section, but it
15560 should never be valid for relocated addresses to be placed in the text
15562 if (TARGET_RELOCATABLE
15563 && in_section
!= toc_section
15565 && GET_CODE (x
) != CONST_INT
15566 && GET_CODE (x
) != CONST_DOUBLE
15572 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
15574 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
15575 fprintf (asm_out_file
, "\t.long\t(");
15576 output_addr_const (asm_out_file
, x
);
15577 fprintf (asm_out_file
, ")@fixup\n");
15578 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
15579 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
15580 fprintf (asm_out_file
, "\t.long\t");
15581 assemble_name (asm_out_file
, buf
);
15582 fprintf (asm_out_file
, "\n\t.previous\n");
15586 /* Remove initial .'s to turn a -mcall-aixdesc function
15587 address into the address of the descriptor, not the function
15589 else if (GET_CODE (x
) == SYMBOL_REF
15590 && XSTR (x
, 0)[0] == '.'
15591 && DEFAULT_ABI
== ABI_AIX
)
15593 const char *name
= XSTR (x
, 0);
15594 while (*name
== '.')
15597 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
15601 #endif /* RELOCATABLE_NEEDS_FIXUP */
15602 return default_assemble_integer (x
, size
, aligned_p
);
15605 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15606 /* Emit an assembler directive to set symbol visibility for DECL to
15607 VISIBILITY_TYPE. */
15610 rs6000_assemble_visibility (tree decl
, int vis
)
15615 /* Functions need to have their entry point symbol visibility set as
15616 well as their descriptor symbol visibility. */
15617 if (DEFAULT_ABI
== ABI_AIX
15619 && TREE_CODE (decl
) == FUNCTION_DECL
)
15621 static const char * const visibility_types
[] = {
15622 NULL
, "internal", "hidden", "protected"
15625 const char *name
, *type
;
15627 name
= ((* targetm
.strip_name_encoding
)
15628 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
15629 type
= visibility_types
[vis
];
15631 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
15632 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
15635 default_assemble_visibility (decl
, vis
);
15640 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
15642 /* Reversal of FP compares takes care -- an ordered compare
15643 becomes an unordered compare and vice versa. */
15644 if (mode
== CCFPmode
15645 && (!flag_finite_math_only
15646 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
15647 || code
== UNEQ
|| code
== LTGT
))
15648 return reverse_condition_maybe_unordered (code
);
15650 return reverse_condition (code
);
15653 /* Generate a compare for CODE. Return a brand-new rtx that
15654 represents the result of the compare. */
15657 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
15659 enum machine_mode comp_mode
;
15660 rtx compare_result
;
15661 enum rtx_code code
= GET_CODE (cmp
);
15662 rtx op0
= XEXP (cmp
, 0);
15663 rtx op1
= XEXP (cmp
, 1);
15665 if (FLOAT_MODE_P (mode
))
15666 comp_mode
= CCFPmode
;
15667 else if (code
== GTU
|| code
== LTU
15668 || code
== GEU
|| code
== LEU
)
15669 comp_mode
= CCUNSmode
;
15670 else if ((code
== EQ
|| code
== NE
)
15671 && unsigned_reg_p (op0
)
15672 && (unsigned_reg_p (op1
)
15673 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
15674 /* These are unsigned values, perhaps there will be a later
15675 ordering compare that can be shared with this one. */
15676 comp_mode
= CCUNSmode
;
15678 comp_mode
= CCmode
;
15680 /* If we have an unsigned compare, make sure we don't have a signed value as
15682 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
15683 && INTVAL (op1
) < 0)
15685 op0
= copy_rtx_if_shared (op0
);
15686 op1
= force_reg (GET_MODE (op0
), op1
);
15687 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
15690 /* First, the compare. */
15691 compare_result
= gen_reg_rtx (comp_mode
);
15693 /* E500 FP compare instructions on the GPRs. Yuck! */
15694 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
15695 && FLOAT_MODE_P (mode
))
15697 rtx cmp
, or_result
, compare_result2
;
15698 enum machine_mode op_mode
= GET_MODE (op0
);
15700 if (op_mode
== VOIDmode
)
15701 op_mode
= GET_MODE (op1
);
15703 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15704 This explains the following mess. */
15708 case EQ
: case UNEQ
: case NE
: case LTGT
:
15712 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15713 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
15714 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
15718 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15719 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
15720 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
15724 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15725 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
15726 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
15730 gcc_unreachable ();
15734 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
15738 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15739 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
15740 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
15744 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15745 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
15746 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
15750 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15751 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
15752 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
15756 gcc_unreachable ();
15760 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
15764 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15765 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
15766 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
15770 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15771 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
15772 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
15776 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15777 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
15778 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
15782 gcc_unreachable ();
15786 gcc_unreachable ();
15789 /* Synthesize LE and GE from LT/GT || EQ. */
15790 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
15796 case LE
: code
= LT
; break;
15797 case GE
: code
= GT
; break;
15798 case LEU
: code
= LT
; break;
15799 case GEU
: code
= GT
; break;
15800 default: gcc_unreachable ();
15803 compare_result2
= gen_reg_rtx (CCFPmode
);
15809 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15810 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
15811 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
15815 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15816 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
15817 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
15821 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15822 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
15823 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
15827 gcc_unreachable ();
15831 /* OR them together. */
15832 or_result
= gen_reg_rtx (CCFPmode
);
15833 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
15835 compare_result
= or_result
;
15840 if (code
== NE
|| code
== LTGT
)
15850 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15851 CLOBBERs to match cmptf_internal2 pattern. */
15852 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
15853 && GET_MODE (op0
) == TFmode
15854 && !TARGET_IEEEQUAD
15855 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
15856 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
15858 gen_rtx_SET (VOIDmode
,
15860 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
15861 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15862 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15863 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15864 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15865 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15866 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15867 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15868 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15869 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
15870 else if (GET_CODE (op1
) == UNSPEC
15871 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
15873 rtx op1b
= XVECEXP (op1
, 0, 0);
15874 comp_mode
= CCEQmode
;
15875 compare_result
= gen_reg_rtx (CCEQmode
);
15877 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
15879 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
15882 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
15883 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
15886 /* Some kinds of FP comparisons need an OR operation;
15887 under flag_finite_math_only we don't bother. */
15888 if (FLOAT_MODE_P (mode
)
15889 && !flag_finite_math_only
15890 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
15891 && (code
== LE
|| code
== GE
15892 || code
== UNEQ
|| code
== LTGT
15893 || code
== UNGT
|| code
== UNLT
))
15895 enum rtx_code or1
, or2
;
15896 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
15897 rtx or_result
= gen_reg_rtx (CCEQmode
);
15901 case LE
: or1
= LT
; or2
= EQ
; break;
15902 case GE
: or1
= GT
; or2
= EQ
; break;
15903 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
15904 case LTGT
: or1
= LT
; or2
= GT
; break;
15905 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
15906 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
15907 default: gcc_unreachable ();
15909 validate_condition_mode (or1
, comp_mode
);
15910 validate_condition_mode (or2
, comp_mode
);
15911 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
15912 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
15913 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
15914 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
15916 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
15918 compare_result
= or_result
;
15922 validate_condition_mode (code
, GET_MODE (compare_result
));
15924 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
15928 /* Emit the RTL for an sISEL pattern. */
15931 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
15933 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
15937 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
15940 enum machine_mode op_mode
;
15941 enum rtx_code cond_code
;
15942 rtx result
= operands
[0];
15944 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
15946 rs6000_emit_sISEL (mode
, operands
);
15950 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
15951 cond_code
= GET_CODE (condition_rtx
);
15953 if (FLOAT_MODE_P (mode
)
15954 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
15958 PUT_MODE (condition_rtx
, SImode
);
15959 t
= XEXP (condition_rtx
, 0);
15961 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
15963 if (cond_code
== NE
)
15964 emit_insn (gen_e500_flip_gt_bit (t
, t
));
15966 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
15970 if (cond_code
== NE
15971 || cond_code
== GE
|| cond_code
== LE
15972 || cond_code
== GEU
|| cond_code
== LEU
15973 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
15975 rtx not_result
= gen_reg_rtx (CCEQmode
);
15976 rtx not_op
, rev_cond_rtx
;
15977 enum machine_mode cc_mode
;
15979 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
15981 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
15982 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
15983 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
15984 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
15985 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
15988 op_mode
= GET_MODE (XEXP (operands
[1], 0));
15989 if (op_mode
== VOIDmode
)
15990 op_mode
= GET_MODE (XEXP (operands
[1], 1));
15992 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
15994 PUT_MODE (condition_rtx
, DImode
);
15995 convert_move (result
, condition_rtx
, 0);
15999 PUT_MODE (condition_rtx
, SImode
);
16000 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
16004 /* Emit a branch of kind CODE to location LOC. */
16007 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
16009 rtx condition_rtx
, loc_ref
;
16011 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
16012 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
16013 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
16014 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
16015 loc_ref
, pc_rtx
)));
16018 /* Return the string to output a conditional branch to LABEL, which is
16019 the operand template of the label, or NULL if the branch is really a
16020 conditional return.
16022 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
16023 condition code register and its mode specifies what kind of
16024 comparison we made.
16026 REVERSED is nonzero if we should reverse the sense of the comparison.
16028 INSN is the insn. */
16031 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
16033 static char string
[64];
16034 enum rtx_code code
= GET_CODE (op
);
16035 rtx cc_reg
= XEXP (op
, 0);
16036 enum machine_mode mode
= GET_MODE (cc_reg
);
16037 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
16038 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
16039 int really_reversed
= reversed
^ need_longbranch
;
16045 validate_condition_mode (code
, mode
);
16047 /* Work out which way this really branches. We could use
16048 reverse_condition_maybe_unordered here always but this
16049 makes the resulting assembler clearer. */
16050 if (really_reversed
)
16052 /* Reversal of FP compares takes care -- an ordered compare
16053 becomes an unordered compare and vice versa. */
16054 if (mode
== CCFPmode
)
16055 code
= reverse_condition_maybe_unordered (code
);
16057 code
= reverse_condition (code
);
16060 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
16062 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
16067 /* Opposite of GT. */
16076 gcc_unreachable ();
16082 /* Not all of these are actually distinct opcodes, but
16083 we distinguish them for clarity of the resulting assembler. */
16084 case NE
: case LTGT
:
16085 ccode
= "ne"; break;
16086 case EQ
: case UNEQ
:
16087 ccode
= "eq"; break;
16089 ccode
= "ge"; break;
16090 case GT
: case GTU
: case UNGT
:
16091 ccode
= "gt"; break;
16093 ccode
= "le"; break;
16094 case LT
: case LTU
: case UNLT
:
16095 ccode
= "lt"; break;
16096 case UNORDERED
: ccode
= "un"; break;
16097 case ORDERED
: ccode
= "nu"; break;
16098 case UNGE
: ccode
= "nl"; break;
16099 case UNLE
: ccode
= "ng"; break;
16101 gcc_unreachable ();
16104 /* Maybe we have a guess as to how likely the branch is. */
16106 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
16107 if (note
!= NULL_RTX
)
16109 /* PROB is the difference from 50%. */
16110 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
16112 /* Only hint for highly probable/improbable branches on newer
16113 cpus as static prediction overrides processor dynamic
16114 prediction. For older cpus we may as well always hint, but
16115 assume not taken for branches that are very close to 50% as a
16116 mispredicted taken branch is more expensive than a
16117 mispredicted not-taken branch. */
16118 if (rs6000_always_hint
16119 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
16120 && br_prob_note_reliable_p (note
)))
16122 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
16123 && ((prob
> 0) ^ need_longbranch
))
16131 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
16133 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
16135 /* We need to escape any '%' characters in the reg_names string.
16136 Assume they'd only be the first character.... */
16137 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
16139 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
16143 /* If the branch distance was too far, we may have to use an
16144 unconditional branch to go the distance. */
16145 if (need_longbranch
)
16146 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
16148 s
+= sprintf (s
, ",%s", label
);
16154 /* Return the string to flip the GT bit on a CR. */
16156 output_e500_flip_gt_bit (rtx dst
, rtx src
)
16158 static char string
[64];
16161 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
16162 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
16165 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
16166 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
16168 sprintf (string
, "crnot %d,%d", a
, b
);
16172 /* Return insn for VSX or Altivec comparisons. */
16175 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
16178 enum machine_mode mode
= GET_MODE (op0
);
16186 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
16196 mask
= gen_reg_rtx (mode
);
16197 emit_insn (gen_rtx_SET (VOIDmode
,
16199 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
16206 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16207 DMODE is expected destination mode. This is a recursive function. */
16210 rs6000_emit_vector_compare (enum rtx_code rcode
,
16212 enum machine_mode dmode
)
16215 bool swap_operands
= false;
16216 bool try_again
= false;
16218 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
16219 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
16221 /* See if the comparison works as is. */
16222 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
16230 swap_operands
= true;
16235 swap_operands
= true;
16243 /* Invert condition and try again.
16244 e.g., A != B becomes ~(A==B). */
16246 enum rtx_code rev_code
;
16247 enum insn_code nor_code
;
16250 rev_code
= reverse_condition_maybe_unordered (rcode
);
16251 if (rev_code
== UNKNOWN
)
16254 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
16255 if (nor_code
== CODE_FOR_nothing
)
16258 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
16262 mask
= gen_reg_rtx (dmode
);
16263 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
16271 /* Try GT/GTU/LT/LTU OR EQ */
16274 enum insn_code ior_code
;
16275 enum rtx_code new_code
;
16296 gcc_unreachable ();
16299 ior_code
= optab_handler (ior_optab
, dmode
);
16300 if (ior_code
== CODE_FOR_nothing
)
16303 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
16307 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
16311 mask
= gen_reg_rtx (dmode
);
16312 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
16330 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
16335 /* You only get two chances. */
16339 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16340 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16341 operands for the relation operation COND. */
16344 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
16345 rtx cond
, rtx cc_op0
, rtx cc_op1
)
16347 enum machine_mode dest_mode
= GET_MODE (dest
);
16348 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
16349 enum rtx_code rcode
= GET_CODE (cond
);
16350 enum machine_mode cc_mode
= CCmode
;
16354 bool invert_move
= false;
16356 if (VECTOR_UNIT_NONE_P (dest_mode
))
16359 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
16360 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
16364 /* Swap operands if we can, and fall back to doing the operation as
16365 specified, and doing a NOR to invert the test. */
16371 /* Invert condition and try again.
16372 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16373 invert_move
= true;
16374 rcode
= reverse_condition_maybe_unordered (rcode
);
16375 if (rcode
== UNKNOWN
)
16379 /* Mark unsigned tests with CCUNSmode. */
16384 cc_mode
= CCUNSmode
;
16391 /* Get the vector mask for the given relational operations. */
16392 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
16400 op_true
= op_false
;
16404 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
16405 CONST0_RTX (dest_mode
));
16406 emit_insn (gen_rtx_SET (VOIDmode
,
16408 gen_rtx_IF_THEN_ELSE (dest_mode
,
16415 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16416 operands of the last comparison is nonzero/true, FALSE_COND if it
16417 is zero/false. Return 0 if the hardware has no such operation. */
16420 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
16422 enum rtx_code code
= GET_CODE (op
);
16423 rtx op0
= XEXP (op
, 0);
16424 rtx op1
= XEXP (op
, 1);
16425 REAL_VALUE_TYPE c1
;
16426 enum machine_mode compare_mode
= GET_MODE (op0
);
16427 enum machine_mode result_mode
= GET_MODE (dest
);
16429 bool is_against_zero
;
16431 /* These modes should always match. */
16432 if (GET_MODE (op1
) != compare_mode
16433 /* In the isel case however, we can use a compare immediate, so
16434 op1 may be a small constant. */
16435 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
16437 if (GET_MODE (true_cond
) != result_mode
)
16439 if (GET_MODE (false_cond
) != result_mode
)
16442 /* Don't allow using floating point comparisons for integer results for
16444 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
16447 /* First, work out if the hardware can do this at all, or
16448 if it's too slow.... */
16449 if (!FLOAT_MODE_P (compare_mode
))
16452 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
16455 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
16456 && SCALAR_FLOAT_MODE_P (compare_mode
))
16459 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
16461 /* A floating-point subtract might overflow, underflow, or produce
16462 an inexact result, thus changing the floating-point flags, so it
16463 can't be generated if we care about that. It's safe if one side
16464 of the construct is zero, since then no subtract will be
16466 if (SCALAR_FLOAT_MODE_P (compare_mode
)
16467 && flag_trapping_math
&& ! is_against_zero
)
16470 /* Eliminate half of the comparisons by switching operands, this
16471 makes the remaining code simpler. */
16472 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
16473 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
16475 code
= reverse_condition_maybe_unordered (code
);
16477 true_cond
= false_cond
;
16481 /* UNEQ and LTGT take four instructions for a comparison with zero,
16482 it'll probably be faster to use a branch here too. */
16483 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
16486 if (GET_CODE (op1
) == CONST_DOUBLE
)
16487 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
16489 /* We're going to try to implement comparisons by performing
16490 a subtract, then comparing against zero. Unfortunately,
16491 Inf - Inf is NaN which is not zero, and so if we don't
16492 know that the operand is finite and the comparison
16493 would treat EQ different to UNORDERED, we can't do it. */
16494 if (HONOR_INFINITIES (compare_mode
)
16495 && code
!= GT
&& code
!= UNGE
16496 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
16497 /* Constructs of the form (a OP b ? a : b) are safe. */
16498 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
16499 || (! rtx_equal_p (op0
, true_cond
)
16500 && ! rtx_equal_p (op1
, true_cond
))))
16503 /* At this point we know we can use fsel. */
16505 /* Reduce the comparison to a comparison against zero. */
16506 if (! is_against_zero
)
16508 temp
= gen_reg_rtx (compare_mode
);
16509 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16510 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
16512 op1
= CONST0_RTX (compare_mode
);
16515 /* If we don't care about NaNs we can reduce some of the comparisons
16516 down to faster ones. */
16517 if (! HONOR_NANS (compare_mode
))
16523 true_cond
= false_cond
;
16536 /* Now, reduce everything down to a GE. */
16543 temp
= gen_reg_rtx (compare_mode
);
16544 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16549 temp
= gen_reg_rtx (compare_mode
);
16550 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
16555 temp
= gen_reg_rtx (compare_mode
);
16556 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16557 gen_rtx_NEG (compare_mode
,
16558 gen_rtx_ABS (compare_mode
, op0
))));
16563 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16564 temp
= gen_reg_rtx (result_mode
);
16565 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16566 gen_rtx_IF_THEN_ELSE (result_mode
,
16567 gen_rtx_GE (VOIDmode
,
16569 true_cond
, false_cond
)));
16570 false_cond
= true_cond
;
16573 temp
= gen_reg_rtx (compare_mode
);
16574 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16579 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16580 temp
= gen_reg_rtx (result_mode
);
16581 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16582 gen_rtx_IF_THEN_ELSE (result_mode
,
16583 gen_rtx_GE (VOIDmode
,
16585 true_cond
, false_cond
)));
16586 true_cond
= false_cond
;
16589 temp
= gen_reg_rtx (compare_mode
);
16590 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16595 gcc_unreachable ();
16598 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16599 gen_rtx_IF_THEN_ELSE (result_mode
,
16600 gen_rtx_GE (VOIDmode
,
16602 true_cond
, false_cond
)));
16606 /* Same as above, but for ints (isel). */
16609 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
16611 rtx condition_rtx
, cr
;
16612 enum machine_mode mode
= GET_MODE (dest
);
16613 enum rtx_code cond_code
;
16614 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
16617 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
16620 /* We still have to do the compare, because isel doesn't do a
16621 compare, it just looks at the CRx bits set by a previous compare
16623 condition_rtx
= rs6000_generate_compare (op
, mode
);
16624 cond_code
= GET_CODE (condition_rtx
);
16625 cr
= XEXP (condition_rtx
, 0);
16626 signedp
= GET_MODE (cr
) == CCmode
;
16628 isel_func
= (mode
== SImode
16629 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
16630 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
16634 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
16635 /* isel handles these directly. */
16639 /* We need to swap the sense of the comparison. */
16642 true_cond
= false_cond
;
16644 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
16649 false_cond
= force_reg (mode
, false_cond
);
16650 if (true_cond
!= const0_rtx
)
16651 true_cond
= force_reg (mode
, true_cond
);
16653 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
16659 output_isel (rtx
*operands
)
16661 enum rtx_code code
;
16663 code
= GET_CODE (operands
[1]);
16665 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
16667 gcc_assert (GET_CODE (operands
[2]) == REG
16668 && GET_CODE (operands
[3]) == REG
);
16669 PUT_CODE (operands
[1], reverse_condition (code
));
16670 return "isel %0,%3,%2,%j1";
16673 return "isel %0,%2,%3,%j1";
16677 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
16679 enum machine_mode mode
= GET_MODE (op0
);
16683 /* VSX/altivec have direct min/max insns. */
16684 if ((code
== SMAX
|| code
== SMIN
)
16685 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16686 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
16688 emit_insn (gen_rtx_SET (VOIDmode
,
16690 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
16694 if (code
== SMAX
|| code
== SMIN
)
16699 if (code
== SMAX
|| code
== UMAX
)
16700 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
16701 op0
, op1
, mode
, 0);
16703 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
16704 op1
, op0
, mode
, 0);
16705 gcc_assert (target
);
16706 if (target
!= dest
)
16707 emit_move_insn (dest
, target
);
16710 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16711 COND is true. Mark the jump as unlikely to be taken. */
16714 emit_unlikely_jump (rtx cond
, rtx label
)
16716 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
16719 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
16720 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
16721 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
16724 /* A subroutine of the atomic operation splitters. Emit a load-locked
16725 instruction in MODE. */
16728 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
16730 rtx (*fn
) (rtx
, rtx
) = NULL
;
16735 fn
= gen_load_lockedsi
;
16738 fn
= gen_load_lockeddi
;
16741 gcc_unreachable ();
16743 emit_insn (fn (reg
, mem
));
16746 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16747 instruction in MODE. */
16750 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
16752 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
16757 fn
= gen_store_conditionalsi
;
16760 fn
= gen_store_conditionaldi
;
16763 gcc_unreachable ();
16766 /* Emit sync before stwcx. to address PPC405 Erratum. */
16767 if (PPC405_ERRATUM77
)
16768 emit_insn (gen_hwsync ());
16770 emit_insn (fn (res
, mem
, val
));
16773 /* Expand barriers before and after a load_locked/store_cond sequence. */
16776 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
16778 rtx addr
= XEXP (mem
, 0);
16779 int strict_p
= (reload_in_progress
|| reload_completed
);
16781 if (!legitimate_indirect_address_p (addr
, strict_p
)
16782 && !legitimate_indexed_address_p (addr
, strict_p
))
16784 addr
= force_reg (Pmode
, addr
);
16785 mem
= replace_equiv_address_nv (mem
, addr
);
16790 case MEMMODEL_RELAXED
:
16791 case MEMMODEL_CONSUME
:
16792 case MEMMODEL_ACQUIRE
:
16794 case MEMMODEL_RELEASE
:
16795 case MEMMODEL_ACQ_REL
:
16796 emit_insn (gen_lwsync ());
16798 case MEMMODEL_SEQ_CST
:
16799 emit_insn (gen_hwsync ());
16802 gcc_unreachable ();
16808 rs6000_post_atomic_barrier (enum memmodel model
)
16812 case MEMMODEL_RELAXED
:
16813 case MEMMODEL_CONSUME
:
16814 case MEMMODEL_RELEASE
:
16816 case MEMMODEL_ACQUIRE
:
16817 case MEMMODEL_ACQ_REL
:
16818 case MEMMODEL_SEQ_CST
:
16819 emit_insn (gen_isync ());
16822 gcc_unreachable ();
16826 /* A subroutine of the various atomic expanders. For sub-word operations,
16827 we must adjust things to operate on SImode. Given the original MEM,
16828 return a new aligned memory. Also build and return the quantities by
16829 which to shift and mask. */
16832 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
16834 rtx addr
, align
, shift
, mask
, mem
;
16835 HOST_WIDE_INT shift_mask
;
16836 enum machine_mode mode
= GET_MODE (orig_mem
);
16838 /* For smaller modes, we have to implement this via SImode. */
16839 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
16841 addr
= XEXP (orig_mem
, 0);
16842 addr
= force_reg (GET_MODE (addr
), addr
);
16844 /* Aligned memory containing subword. Generate a new memory. We
16845 do not want any of the existing MEM_ATTR data, as we're now
16846 accessing memory outside the original object. */
16847 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
16848 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16849 mem
= gen_rtx_MEM (SImode
, align
);
16850 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
16851 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
16852 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
16854 /* Shift amount for subword relative to aligned word. */
16855 shift
= gen_reg_rtx (SImode
);
16856 addr
= gen_lowpart (SImode
, addr
);
16857 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
16858 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
16859 shift
, 1, OPTAB_LIB_WIDEN
);
16862 /* Mask for insertion. */
16863 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
16864 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16870 /* A subroutine of the various atomic expanders. For sub-word operands,
16871 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16874 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
16878 x
= gen_reg_rtx (SImode
);
16879 emit_insn (gen_rtx_SET (VOIDmode
, x
,
16880 gen_rtx_AND (SImode
,
16881 gen_rtx_NOT (SImode
, mask
),
16884 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
16889 /* A subroutine of the various atomic expanders. For sub-word operands,
16890 extract WIDE to NARROW via SHIFT. */
16893 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
16895 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
16896 wide
, 1, OPTAB_LIB_WIDEN
);
16897 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
16900 /* Expand an atomic compare and swap operation. */
16903 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
16905 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
16906 rtx label1
, label2
, x
, mask
, shift
;
16907 enum machine_mode mode
;
16908 enum memmodel mod_s
, mod_f
;
16911 boolval
= operands
[0];
16912 retval
= operands
[1];
16914 oldval
= operands
[3];
16915 newval
= operands
[4];
16916 is_weak
= (INTVAL (operands
[5]) != 0);
16917 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
16918 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
16919 mode
= GET_MODE (mem
);
16921 mask
= shift
= NULL_RTX
;
16922 if (mode
== QImode
|| mode
== HImode
)
16924 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
16926 /* Shift and mask OLDVAL into position with the word. */
16927 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
16928 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
16929 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16931 /* Shift and mask NEWVAL into position within the word. */
16932 newval
= convert_modes (SImode
, mode
, newval
, 1);
16933 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
16934 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16936 /* Prepare to adjust the return value. */
16937 retval
= gen_reg_rtx (SImode
);
16940 else if (reg_overlap_mentioned_p (retval
, oldval
))
16941 oldval
= copy_to_reg (oldval
);
16943 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
16948 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16949 emit_label (XEXP (label1
, 0));
16951 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16953 emit_load_locked (mode
, retval
, mem
);
16958 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
16959 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16962 cond
= gen_reg_rtx (CCmode
);
16963 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
16964 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
16966 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16967 emit_unlikely_jump (x
, label2
);
16971 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
16973 emit_store_conditional (mode
, cond
, mem
, x
);
16977 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16978 emit_unlikely_jump (x
, label1
);
16981 if (mod_f
!= MEMMODEL_RELAXED
)
16982 emit_label (XEXP (label2
, 0));
16984 rs6000_post_atomic_barrier (mod_s
);
16986 if (mod_f
== MEMMODEL_RELAXED
)
16987 emit_label (XEXP (label2
, 0));
16990 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
16992 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16993 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
16994 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
16997 /* Expand an atomic exchange operation. */
17000 rs6000_expand_atomic_exchange (rtx operands
[])
17002 rtx retval
, mem
, val
, cond
;
17003 enum machine_mode mode
;
17004 enum memmodel model
;
17005 rtx label
, x
, mask
, shift
;
17007 retval
= operands
[0];
17010 model
= (enum memmodel
) INTVAL (operands
[3]);
17011 mode
= GET_MODE (mem
);
17013 mask
= shift
= NULL_RTX
;
17014 if (mode
== QImode
|| mode
== HImode
)
17016 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
17018 /* Shift and mask VAL into position with the word. */
17019 val
= convert_modes (SImode
, mode
, val
, 1);
17020 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
17021 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17023 /* Prepare to adjust the return value. */
17024 retval
= gen_reg_rtx (SImode
);
17028 mem
= rs6000_pre_atomic_barrier (mem
, model
);
17030 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
17031 emit_label (XEXP (label
, 0));
17033 emit_load_locked (mode
, retval
, mem
);
17037 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
17039 cond
= gen_reg_rtx (CCmode
);
17040 emit_store_conditional (mode
, cond
, mem
, x
);
17042 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
17043 emit_unlikely_jump (x
, label
);
17045 rs6000_post_atomic_barrier (model
);
17048 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
17051 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
17052 to perform. MEM is the memory on which to operate. VAL is the second
17053 operand of the binary operator. BEFORE and AFTER are optional locations to
17054 return the value of MEM either before of after the operation. MODEL_RTX
17055 is a CONST_INT containing the memory model to use. */
17058 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
17059 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
17061 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
17062 enum machine_mode mode
= GET_MODE (mem
);
17063 rtx label
, x
, cond
, mask
, shift
;
17064 rtx before
= orig_before
, after
= orig_after
;
17066 mask
= shift
= NULL_RTX
;
17067 if (mode
== QImode
|| mode
== HImode
)
17069 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
17071 /* Shift and mask VAL into position with the word. */
17072 val
= convert_modes (SImode
, mode
, val
, 1);
17073 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
17074 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17080 /* We've already zero-extended VAL. That is sufficient to
17081 make certain that it does not affect other bits. */
17086 /* If we make certain that all of the other bits in VAL are
17087 set, that will be sufficient to not affect other bits. */
17088 x
= gen_rtx_NOT (SImode
, mask
);
17089 x
= gen_rtx_IOR (SImode
, x
, val
);
17090 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
17097 /* These will all affect bits outside the field and need
17098 adjustment via MASK within the loop. */
17102 gcc_unreachable ();
17105 /* Prepare to adjust the return value. */
17106 before
= gen_reg_rtx (SImode
);
17108 after
= gen_reg_rtx (SImode
);
17112 mem
= rs6000_pre_atomic_barrier (mem
, model
);
17114 label
= gen_label_rtx ();
17115 emit_label (label
);
17116 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
17118 if (before
== NULL_RTX
)
17119 before
= gen_reg_rtx (mode
);
17121 emit_load_locked (mode
, before
, mem
);
17125 x
= expand_simple_binop (mode
, AND
, before
, val
,
17126 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17127 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
17131 after
= expand_simple_binop (mode
, code
, before
, val
,
17132 after
, 1, OPTAB_LIB_WIDEN
);
17138 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
17139 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17140 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
17143 cond
= gen_reg_rtx (CCmode
);
17144 emit_store_conditional (mode
, cond
, mem
, x
);
17146 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
17147 emit_unlikely_jump (x
, label
);
17149 rs6000_post_atomic_barrier (model
);
17154 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
17156 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
17158 else if (orig_after
&& after
!= orig_after
)
17159 emit_move_insn (orig_after
, after
);
17162 /* Emit instructions to move SRC to DST. Called by splitters for
17163 multi-register moves. It will emit at most one instruction for
17164 each register that is accessed; that is, it won't emit li/lis pairs
17165 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17169 rs6000_split_multireg_move (rtx dst
, rtx src
)
17171 /* The register number of the first register being moved. */
17173 /* The mode that is to be moved. */
17174 enum machine_mode mode
;
17175 /* The mode that the move is being done in, and its size. */
17176 enum machine_mode reg_mode
;
17178 /* The number of registers that will be moved. */
17181 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
17182 mode
= GET_MODE (dst
);
17183 nregs
= hard_regno_nregs
[reg
][mode
];
17184 if (FP_REGNO_P (reg
))
17185 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
17186 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
17187 else if (ALTIVEC_REGNO_P (reg
))
17188 reg_mode
= V16QImode
;
17189 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
17192 reg_mode
= word_mode
;
17193 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
17195 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
17197 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
17199 /* Move register range backwards, if we might have destructive
17202 for (i
= nregs
- 1; i
>= 0; i
--)
17203 emit_insn (gen_rtx_SET (VOIDmode
,
17204 simplify_gen_subreg (reg_mode
, dst
, mode
,
17205 i
* reg_mode_size
),
17206 simplify_gen_subreg (reg_mode
, src
, mode
,
17207 i
* reg_mode_size
)));
17213 bool used_update
= false;
17214 rtx restore_basereg
= NULL_RTX
;
17216 if (MEM_P (src
) && INT_REGNO_P (reg
))
17220 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
17221 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
17224 breg
= XEXP (XEXP (src
, 0), 0);
17225 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
17226 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
17227 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
17228 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
17229 src
= replace_equiv_address (src
, breg
);
17231 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
17233 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
17235 rtx basereg
= XEXP (XEXP (src
, 0), 0);
17238 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
17239 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
17240 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
17241 used_update
= true;
17244 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
17245 XEXP (XEXP (src
, 0), 1)));
17246 src
= replace_equiv_address (src
, basereg
);
17250 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
17251 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
17252 src
= replace_equiv_address (src
, basereg
);
17256 breg
= XEXP (src
, 0);
17257 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
17258 breg
= XEXP (breg
, 0);
17260 /* If the base register we are using to address memory is
17261 also a destination reg, then change that register last. */
17263 && REGNO (breg
) >= REGNO (dst
)
17264 && REGNO (breg
) < REGNO (dst
) + nregs
)
17265 j
= REGNO (breg
) - REGNO (dst
);
17267 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
17271 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
17272 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
17275 breg
= XEXP (XEXP (dst
, 0), 0);
17276 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
17277 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
17278 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
17280 /* We have to update the breg before doing the store.
17281 Use store with update, if available. */
17285 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
17286 emit_insn (TARGET_32BIT
17287 ? (TARGET_POWERPC64
17288 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
17289 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
17290 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
17291 used_update
= true;
17294 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
17295 dst
= replace_equiv_address (dst
, breg
);
17297 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
17298 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
17300 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
17302 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
17305 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
17306 emit_insn (gen_rtx_SET (VOIDmode
,
17307 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
17308 used_update
= true;
17311 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
17312 XEXP (XEXP (dst
, 0), 1)));
17313 dst
= replace_equiv_address (dst
, basereg
);
17317 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
17318 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
17319 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
17321 && REG_P (offsetreg
)
17322 && REGNO (basereg
) != REGNO (offsetreg
));
17323 if (REGNO (basereg
) == 0)
17325 rtx tmp
= offsetreg
;
17326 offsetreg
= basereg
;
17329 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
17330 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
17331 dst
= replace_equiv_address (dst
, basereg
);
17334 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
17335 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
17338 for (i
= 0; i
< nregs
; i
++)
17340 /* Calculate index to next subword. */
17345 /* If compiler already emitted move of first word by
17346 store with update, no need to do anything. */
17347 if (j
== 0 && used_update
)
17350 emit_insn (gen_rtx_SET (VOIDmode
,
17351 simplify_gen_subreg (reg_mode
, dst
, mode
,
17352 j
* reg_mode_size
),
17353 simplify_gen_subreg (reg_mode
, src
, mode
,
17354 j
* reg_mode_size
)));
17356 if (restore_basereg
!= NULL_RTX
)
17357 emit_insn (restore_basereg
);
17362 /* This page contains routines that are used to determine what the
17363 function prologue and epilogue code will do and write them out. */
17368 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
17371 /* Return the first fixed-point register that is required to be
17372 saved. 32 if none. */
17375 first_reg_to_save (void)
17379 /* Find lowest numbered live register. */
17380 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
17381 if (save_reg_p (first_reg
))
17384 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
17385 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
17386 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
17387 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
17388 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
17389 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
17393 && crtl
->uses_pic_offset_table
17394 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
17395 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
17401 /* Similar, for FP regs. */
17404 first_fp_reg_to_save (void)
17408 /* Find lowest numbered live register. */
17409 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
17410 if (save_reg_p (first_reg
))
17416 /* Similar, for AltiVec regs. */
17419 first_altivec_reg_to_save (void)
17423 /* Stack frame remains as is unless we are in AltiVec ABI. */
17424 if (! TARGET_ALTIVEC_ABI
)
17425 return LAST_ALTIVEC_REGNO
+ 1;
17427 /* On Darwin, the unwind routines are compiled without
17428 TARGET_ALTIVEC, and use save_world to save/restore the
17429 altivec registers when necessary. */
17430 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
17431 && ! TARGET_ALTIVEC
)
17432 return FIRST_ALTIVEC_REGNO
+ 20;
17434 /* Find lowest numbered live register. */
17435 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17436 if (save_reg_p (i
))
17442 /* Return a 32-bit mask of the AltiVec registers we need to set in
17443 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17444 the 32-bit word is 0. */
17446 static unsigned int
17447 compute_vrsave_mask (void)
17449 unsigned int i
, mask
= 0;
17451 /* On Darwin, the unwind routines are compiled without
17452 TARGET_ALTIVEC, and use save_world to save/restore the
17453 call-saved altivec registers when necessary. */
17454 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
17455 && ! TARGET_ALTIVEC
)
17458 /* First, find out if we use _any_ altivec registers. */
17459 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17460 if (df_regs_ever_live_p (i
))
17461 mask
|= ALTIVEC_REG_BIT (i
);
17466 /* Next, remove the argument registers from the set. These must
17467 be in the VRSAVE mask set by the caller, so we don't need to add
17468 them in again. More importantly, the mask we compute here is
17469 used to generate CLOBBERs in the set_vrsave insn, and we do not
17470 wish the argument registers to die. */
17471 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
17472 mask
&= ~ALTIVEC_REG_BIT (i
);
17474 /* Similarly, remove the return value from the set. */
17477 diddle_return_value (is_altivec_return_reg
, &yes
);
17479 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
17485 /* For a very restricted set of circumstances, we can cut down the
17486 size of prologues/epilogues by calling our own save/restore-the-world
17490 compute_save_world_info (rs6000_stack_t
*info_ptr
)
17492 info_ptr
->world_save_p
= 1;
17493 info_ptr
->world_save_p
17494 = (WORLD_SAVE_P (info_ptr
)
17495 && DEFAULT_ABI
== ABI_DARWIN
17496 && !cfun
->has_nonlocal_label
17497 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
17498 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
17499 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
17500 && info_ptr
->cr_save_p
);
17502 /* This will not work in conjunction with sibcalls. Make sure there
17503 are none. (This check is expensive, but seldom executed.) */
17504 if (WORLD_SAVE_P (info_ptr
))
17507 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
17508 if ( GET_CODE (insn
) == CALL_INSN
17509 && SIBLING_CALL_P (insn
))
17511 info_ptr
->world_save_p
= 0;
17516 if (WORLD_SAVE_P (info_ptr
))
17518 /* Even if we're not touching VRsave, make sure there's room on the
17519 stack for it, if it looks like we're calling SAVE_WORLD, which
17520 will attempt to save it. */
17521 info_ptr
->vrsave_size
= 4;
17523 /* If we are going to save the world, we need to save the link register too. */
17524 info_ptr
->lr_save_p
= 1;
17526 /* "Save" the VRsave register too if we're saving the world. */
17527 if (info_ptr
->vrsave_mask
== 0)
17528 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
17530 /* Because the Darwin register save/restore routines only handle
17531 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17533 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
17534 && (info_ptr
->first_altivec_reg_save
17535 >= FIRST_SAVED_ALTIVEC_REGNO
));
17542 is_altivec_return_reg (rtx reg
, void *xyes
)
17544 bool *yes
= (bool *) xyes
;
17545 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
17550 /* Look for user-defined global regs in the range FIRST to LAST-1.
17551 We should not restore these, and so cannot use lmw or out-of-line
17552 restore functions if there are any. We also can't save them
17553 (well, emit frame notes for them), because frame unwinding during
17554 exception handling will restore saved registers. */
17557 global_regs_p (unsigned first
, unsigned last
)
17559 while (first
< last
)
17560 if (global_regs
[first
++])
17565 /* Determine the strategy for savings/restoring registers. */
17568 SAVRES_MULTIPLE
= 0x1,
17569 SAVE_INLINE_FPRS
= 0x2,
17570 SAVE_INLINE_GPRS
= 0x4,
17571 REST_INLINE_FPRS
= 0x8,
17572 REST_INLINE_GPRS
= 0x10,
17573 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
17574 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
17575 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
17576 SAVE_INLINE_VRS
= 0x100,
17577 REST_INLINE_VRS
= 0x200
17581 rs6000_savres_strategy (rs6000_stack_t
*info
,
17582 bool using_static_chain_p
)
17587 if (TARGET_MULTIPLE
17588 && !TARGET_POWERPC64
17589 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
17590 && info
->first_gp_reg_save
< 31
17591 && !global_regs_p (info
->first_gp_reg_save
, 32))
17592 strategy
|= SAVRES_MULTIPLE
;
17594 if (crtl
->calls_eh_return
17595 || cfun
->machine
->ra_need_lr
)
17596 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
17597 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
17598 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
17600 if (info
->first_fp_reg_save
== 64
17601 /* The out-of-line FP routines use double-precision stores;
17602 we can't use those routines if we don't have such stores. */
17603 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
17604 || global_regs_p (info
->first_fp_reg_save
, 64))
17605 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17607 if (info
->first_gp_reg_save
== 32
17608 || (!(strategy
& SAVRES_MULTIPLE
)
17609 && global_regs_p (info
->first_gp_reg_save
, 32)))
17610 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17612 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
17613 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
17614 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17616 /* Define cutoff for using out-of-line functions to save registers. */
17617 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
17619 if (!optimize_size
)
17621 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17622 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17623 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17627 /* Prefer out-of-line restore if it will exit. */
17628 if (info
->first_fp_reg_save
> 61)
17629 strategy
|= SAVE_INLINE_FPRS
;
17630 if (info
->first_gp_reg_save
> 29)
17632 if (info
->first_fp_reg_save
== 64)
17633 strategy
|= SAVE_INLINE_GPRS
;
17635 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17637 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
17638 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17641 else if (DEFAULT_ABI
== ABI_DARWIN
)
17643 if (info
->first_fp_reg_save
> 60)
17644 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17645 if (info
->first_gp_reg_save
> 29)
17646 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17647 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17651 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
);
17652 if (info
->first_fp_reg_save
> 61)
17653 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17654 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17655 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
17658 /* Don't bother to try to save things out-of-line if r11 is occupied
17659 by the static chain. It would require too much fiddling and the
17660 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17661 pointer on Darwin, and AIX uses r1 or r12. */
17662 if (using_static_chain_p
&& DEFAULT_ABI
!= ABI_AIX
)
17663 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
17665 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
17667 /* We can only use the out-of-line routines to restore if we've
17668 saved all the registers from first_fp_reg_save in the prologue.
17669 Otherwise, we risk loading garbage. */
17670 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
17674 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
17675 if (!save_reg_p (i
))
17677 strategy
|= REST_INLINE_FPRS
;
17682 /* If we are going to use store multiple, then don't even bother
17683 with the out-of-line routines, since the store-multiple
17684 instruction will always be smaller. */
17685 if ((strategy
& SAVRES_MULTIPLE
))
17686 strategy
|= SAVE_INLINE_GPRS
;
17688 /* info->lr_save_p isn't yet set if the only reason lr needs to be
17689 saved is an out-of-line save or restore. Set up the value for
17690 the next test (excluding out-of-line gpr restore). */
17691 lr_save_p
= (info
->lr_save_p
17692 || !(strategy
& SAVE_INLINE_GPRS
)
17693 || !(strategy
& SAVE_INLINE_FPRS
)
17694 || !(strategy
& SAVE_INLINE_VRS
)
17695 || !(strategy
& REST_INLINE_FPRS
)
17696 || !(strategy
& REST_INLINE_VRS
));
17698 /* The situation is more complicated with load multiple. We'd
17699 prefer to use the out-of-line routines for restores, since the
17700 "exit" out-of-line routines can handle the restore of LR and the
17701 frame teardown. However if doesn't make sense to use the
17702 out-of-line routine if that is the only reason we'd need to save
17703 LR, and we can't use the "exit" out-of-line gpr restore if we
17704 have saved some fprs; In those cases it is advantageous to use
17705 load multiple when available. */
17706 if ((strategy
& SAVRES_MULTIPLE
)
17708 || info
->first_fp_reg_save
!= 64))
17709 strategy
|= REST_INLINE_GPRS
;
17711 /* Saving CR interferes with the exit routines used on the SPE, so
17714 && info
->spe_64bit_regs_used
17715 && info
->cr_save_p
)
17716 strategy
|= REST_INLINE_GPRS
;
17718 /* We can only use load multiple or the out-of-line routines to
17719 restore if we've used store multiple or out-of-line routines
17720 in the prologue, i.e. if we've saved all the registers from
17721 first_gp_reg_save. Otherwise, we risk loading garbage. */
17722 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
17723 == SAVE_INLINE_GPRS
)
17727 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
17728 if (!save_reg_p (i
))
17730 strategy
|= REST_INLINE_GPRS
;
17735 if (TARGET_ELF
&& TARGET_64BIT
)
17737 if (!(strategy
& SAVE_INLINE_FPRS
))
17738 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
17739 else if (!(strategy
& SAVE_INLINE_GPRS
)
17740 && info
->first_fp_reg_save
== 64)
17741 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
17743 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
17744 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
17746 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
17747 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
17752 /* Calculate the stack information for the current function. This is
17753 complicated by having two separate calling sequences, the AIX calling
17754 sequence and the V.4 calling sequence.
17756 AIX (and Darwin/Mac OS X) stack frames look like:
17758 SP----> +---------------------------------------+
17759 | back chain to caller | 0 0
17760 +---------------------------------------+
17761 | saved CR | 4 8 (8-11)
17762 +---------------------------------------+
17764 +---------------------------------------+
17765 | reserved for compilers | 12 24
17766 +---------------------------------------+
17767 | reserved for binders | 16 32
17768 +---------------------------------------+
17769 | saved TOC pointer | 20 40
17770 +---------------------------------------+
17771 | Parameter save area (P) | 24 48
17772 +---------------------------------------+
17773 | Alloca space (A) | 24+P etc.
17774 +---------------------------------------+
17775 | Local variable space (L) | 24+P+A
17776 +---------------------------------------+
17777 | Float/int conversion temporary (X) | 24+P+A+L
17778 +---------------------------------------+
17779 | Save area for AltiVec registers (W) | 24+P+A+L+X
17780 +---------------------------------------+
17781 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17782 +---------------------------------------+
17783 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17784 +---------------------------------------+
17785 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17786 +---------------------------------------+
17787 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17788 +---------------------------------------+
17789 old SP->| back chain to caller's caller |
17790 +---------------------------------------+
17792 The required alignment for AIX configurations is two words (i.e., 8
17796 V.4 stack frames look like:
17798 SP----> +---------------------------------------+
17799 | back chain to caller | 0
17800 +---------------------------------------+
17801 | caller's saved LR | 4
17802 +---------------------------------------+
17803 | Parameter save area (P) | 8
17804 +---------------------------------------+
17805 | Alloca space (A) | 8+P
17806 +---------------------------------------+
17807 | Varargs save area (V) | 8+P+A
17808 +---------------------------------------+
17809 | Local variable space (L) | 8+P+A+V
17810 +---------------------------------------+
17811 | Float/int conversion temporary (X) | 8+P+A+V+L
17812 +---------------------------------------+
17813 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17814 +---------------------------------------+
17815 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17816 +---------------------------------------+
17817 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17818 +---------------------------------------+
17819 | SPE: area for 64-bit GP registers |
17820 +---------------------------------------+
17821 | SPE alignment padding |
17822 +---------------------------------------+
17823 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17824 +---------------------------------------+
17825 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17826 +---------------------------------------+
17827 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17828 +---------------------------------------+
17829 old SP->| back chain to caller's caller |
17830 +---------------------------------------+
17832 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17833 given. (But note below and in sysv4.h that we require only 8 and
17834 may round up the size of our stack frame anyways. The historical
17835 reason is early versions of powerpc-linux which didn't properly
17836 align the stack at program startup. A happy side-effect is that
17837 -mno-eabi libraries can be used with -meabi programs.)
17839 The EABI configuration defaults to the V.4 layout. However,
17840 the stack alignment requirements may differ. If -mno-eabi is not
17841 given, the required stack alignment is 8 bytes; if -mno-eabi is
17842 given, the required alignment is 16 bytes. (But see V.4 comment
17845 #ifndef ABI_STACK_BOUNDARY
17846 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17849 static rs6000_stack_t
*
17850 rs6000_stack_info (void)
17852 rs6000_stack_t
*info_ptr
= &stack_info
;
17853 int reg_size
= TARGET_32BIT
? 4 : 8;
17857 HOST_WIDE_INT non_fixed_size
;
17858 bool using_static_chain_p
;
17860 if (reload_completed
&& info_ptr
->reload_completed
)
17863 memset (info_ptr
, 0, sizeof (*info_ptr
));
17864 info_ptr
->reload_completed
= reload_completed
;
17868 /* Cache value so we don't rescan instruction chain over and over. */
17869 if (cfun
->machine
->insn_chain_scanned_p
== 0)
17870 cfun
->machine
->insn_chain_scanned_p
17871 = spe_func_has_64bit_regs_p () + 1;
17872 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
17875 /* Select which calling sequence. */
17876 info_ptr
->abi
= DEFAULT_ABI
;
17878 /* Calculate which registers need to be saved & save area size. */
17879 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
17880 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17881 even if it currently looks like we won't. Reload may need it to
17882 get at a constant; if so, it will have already created a constant
17883 pool entry for it. */
17884 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
17885 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
17886 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
17887 && crtl
->uses_const_pool
17888 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
17889 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
17891 first_gp
= info_ptr
->first_gp_reg_save
;
17893 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
17895 /* For the SPE, we have an additional upper 32-bits on each GPR.
17896 Ideally we should save the entire 64-bits only when the upper
17897 half is used in SIMD instructions. Since we only record
17898 registers live (not the size they are used in), this proves
17899 difficult because we'd have to traverse the instruction chain at
17900 the right time, taking reload into account. This is a real pain,
17901 so we opt to save the GPRs in 64-bits always if but one register
17902 gets used in 64-bits. Otherwise, all the registers in the frame
17903 get saved in 32-bits.
17905 So... since when we save all GPRs (except the SP) in 64-bits, the
17906 traditional GP save area will be empty. */
17907 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17908 info_ptr
->gp_size
= 0;
17910 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
17911 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
17913 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
17914 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
17915 - info_ptr
->first_altivec_reg_save
);
17917 /* Does this function call anything? */
17918 info_ptr
->calls_p
= (! crtl
->is_leaf
17919 || cfun
->machine
->ra_needs_full_frame
);
17921 /* Determine if we need to save the condition code registers. */
17922 if (df_regs_ever_live_p (CR2_REGNO
)
17923 || df_regs_ever_live_p (CR3_REGNO
)
17924 || df_regs_ever_live_p (CR4_REGNO
))
17926 info_ptr
->cr_save_p
= 1;
17927 if (DEFAULT_ABI
== ABI_V4
)
17928 info_ptr
->cr_size
= reg_size
;
17931 /* If the current function calls __builtin_eh_return, then we need
17932 to allocate stack space for registers that will hold data for
17933 the exception handler. */
17934 if (crtl
->calls_eh_return
)
17937 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
17940 /* SPE saves EH registers in 64-bits. */
17941 ehrd_size
= i
* (TARGET_SPE_ABI
17942 && info_ptr
->spe_64bit_regs_used
!= 0
17943 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
17948 /* Determine various sizes. */
17949 info_ptr
->reg_size
= reg_size
;
17950 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
17951 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
17952 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
17953 TARGET_ALTIVEC
? 16 : 8);
17954 if (FRAME_GROWS_DOWNWARD
)
17955 info_ptr
->vars_size
17956 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
17957 + info_ptr
->parm_size
,
17958 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
17959 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
17960 + info_ptr
->parm_size
);
17962 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17963 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
17965 info_ptr
->spe_gp_size
= 0;
17967 if (TARGET_ALTIVEC_ABI
)
17968 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
17970 info_ptr
->vrsave_mask
= 0;
17972 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
17973 info_ptr
->vrsave_size
= 4;
17975 info_ptr
->vrsave_size
= 0;
17977 compute_save_world_info (info_ptr
);
17979 /* Calculate the offsets. */
17980 switch (DEFAULT_ABI
)
17984 gcc_unreachable ();
17988 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
17989 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
17991 if (TARGET_ALTIVEC_ABI
)
17993 info_ptr
->vrsave_save_offset
17994 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
17996 /* Align stack so vector save area is on a quadword boundary.
17997 The padding goes above the vectors. */
17998 if (info_ptr
->altivec_size
!= 0)
17999 info_ptr
->altivec_padding_size
18000 = info_ptr
->vrsave_save_offset
& 0xF;
18002 info_ptr
->altivec_padding_size
= 0;
18004 info_ptr
->altivec_save_offset
18005 = info_ptr
->vrsave_save_offset
18006 - info_ptr
->altivec_padding_size
18007 - info_ptr
->altivec_size
;
18008 gcc_assert (info_ptr
->altivec_size
== 0
18009 || info_ptr
->altivec_save_offset
% 16 == 0);
18011 /* Adjust for AltiVec case. */
18012 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
18015 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
18016 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
18017 info_ptr
->lr_save_offset
= 2*reg_size
;
18021 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
18022 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
18023 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
18025 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
18027 /* Align stack so SPE GPR save area is aligned on a
18028 double-word boundary. */
18029 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
18030 info_ptr
->spe_padding_size
18031 = 8 - (-info_ptr
->cr_save_offset
% 8);
18033 info_ptr
->spe_padding_size
= 0;
18035 info_ptr
->spe_gp_save_offset
18036 = info_ptr
->cr_save_offset
18037 - info_ptr
->spe_padding_size
18038 - info_ptr
->spe_gp_size
;
18040 /* Adjust for SPE case. */
18041 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
18043 else if (TARGET_ALTIVEC_ABI
)
18045 info_ptr
->vrsave_save_offset
18046 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
18048 /* Align stack so vector save area is on a quadword boundary. */
18049 if (info_ptr
->altivec_size
!= 0)
18050 info_ptr
->altivec_padding_size
18051 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
18053 info_ptr
->altivec_padding_size
= 0;
18055 info_ptr
->altivec_save_offset
18056 = info_ptr
->vrsave_save_offset
18057 - info_ptr
->altivec_padding_size
18058 - info_ptr
->altivec_size
;
18060 /* Adjust for AltiVec case. */
18061 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
18064 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
18065 info_ptr
->ehrd_offset
-= ehrd_size
;
18066 info_ptr
->lr_save_offset
= reg_size
;
18070 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
18071 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
18072 + info_ptr
->gp_size
18073 + info_ptr
->altivec_size
18074 + info_ptr
->altivec_padding_size
18075 + info_ptr
->spe_gp_size
18076 + info_ptr
->spe_padding_size
18078 + info_ptr
->cr_size
18079 + info_ptr
->vrsave_size
,
18082 non_fixed_size
= (info_ptr
->vars_size
18083 + info_ptr
->parm_size
18084 + info_ptr
->save_size
);
18086 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
18087 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
18089 /* Determine if we need to save the link register. */
18090 if (info_ptr
->calls_p
18091 || (DEFAULT_ABI
== ABI_AIX
18093 && !TARGET_PROFILE_KERNEL
)
18094 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
18095 #ifdef TARGET_RELOCATABLE
18096 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
18098 || rs6000_ra_ever_killed ())
18099 info_ptr
->lr_save_p
= 1;
18101 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
18102 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
18103 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
18104 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
18105 using_static_chain_p
);
18107 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
18108 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
18109 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
18110 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
18111 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
18112 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
18113 info_ptr
->lr_save_p
= 1;
18115 if (info_ptr
->lr_save_p
)
18116 df_set_regs_ever_live (LR_REGNO
, true);
18118 /* Determine if we need to allocate any stack frame:
18120 For AIX we need to push the stack if a frame pointer is needed
18121 (because the stack might be dynamically adjusted), if we are
18122 debugging, if we make calls, or if the sum of fp_save, gp_save,
18123 and local variables are more than the space needed to save all
18124 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
18125 + 18*8 = 288 (GPR13 reserved).
18127 For V.4 we don't have the stack cushion that AIX uses, but assume
18128 that the debugger can handle stackless frames. */
18130 if (info_ptr
->calls_p
)
18131 info_ptr
->push_p
= 1;
18133 else if (DEFAULT_ABI
== ABI_V4
)
18134 info_ptr
->push_p
= non_fixed_size
!= 0;
18136 else if (frame_pointer_needed
)
18137 info_ptr
->push_p
= 1;
18139 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
18140 info_ptr
->push_p
= 1;
18143 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
18145 /* Zero offsets if we're not saving those registers. */
18146 if (info_ptr
->fp_size
== 0)
18147 info_ptr
->fp_save_offset
= 0;
18149 if (info_ptr
->gp_size
== 0)
18150 info_ptr
->gp_save_offset
= 0;
18152 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
18153 info_ptr
->altivec_save_offset
= 0;
18155 /* Zero VRSAVE offset if not saved and restored. */
18156 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
18157 info_ptr
->vrsave_save_offset
= 0;
18159 if (! TARGET_SPE_ABI
18160 || info_ptr
->spe_64bit_regs_used
== 0
18161 || info_ptr
->spe_gp_size
== 0)
18162 info_ptr
->spe_gp_save_offset
= 0;
18164 if (! info_ptr
->lr_save_p
)
18165 info_ptr
->lr_save_offset
= 0;
18167 if (! info_ptr
->cr_save_p
)
18168 info_ptr
->cr_save_offset
= 0;
18173 /* Return true if the current function uses any GPRs in 64-bit SIMD
18177 spe_func_has_64bit_regs_p (void)
18181 /* Functions that save and restore all the call-saved registers will
18182 need to save/restore the registers in 64-bits. */
18183 if (crtl
->calls_eh_return
18184 || cfun
->calls_setjmp
18185 || crtl
->has_nonlocal_goto
)
18188 insns
= get_insns ();
18190 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
18196 /* FIXME: This should be implemented with attributes...
18198 (set_attr "spe64" "true")....then,
18199 if (get_spe64(insn)) return true;
18201 It's the only reliable way to do the stuff below. */
18203 i
= PATTERN (insn
);
18204 if (GET_CODE (i
) == SET
)
18206 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
18208 if (SPE_VECTOR_MODE (mode
))
18210 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
18220 debug_stack_info (rs6000_stack_t
*info
)
18222 const char *abi_string
;
18225 info
= rs6000_stack_info ();
18227 fprintf (stderr
, "\nStack information for function %s:\n",
18228 ((current_function_decl
&& DECL_NAME (current_function_decl
))
18229 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
18234 default: abi_string
= "Unknown"; break;
18235 case ABI_NONE
: abi_string
= "NONE"; break;
18236 case ABI_AIX
: abi_string
= "AIX"; break;
18237 case ABI_DARWIN
: abi_string
= "Darwin"; break;
18238 case ABI_V4
: abi_string
= "V.4"; break;
18241 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
18243 if (TARGET_ALTIVEC_ABI
)
18244 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
18246 if (TARGET_SPE_ABI
)
18247 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
18249 if (info
->first_gp_reg_save
!= 32)
18250 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
18252 if (info
->first_fp_reg_save
!= 64)
18253 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
18255 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
18256 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
18257 info
->first_altivec_reg_save
);
18259 if (info
->lr_save_p
)
18260 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
18262 if (info
->cr_save_p
)
18263 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
18265 if (info
->vrsave_mask
)
18266 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
18269 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
18272 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
18274 if (info
->gp_save_offset
)
18275 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
18277 if (info
->fp_save_offset
)
18278 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
18280 if (info
->altivec_save_offset
)
18281 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
18282 info
->altivec_save_offset
);
18284 if (info
->spe_gp_save_offset
)
18285 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
18286 info
->spe_gp_save_offset
);
18288 if (info
->vrsave_save_offset
)
18289 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
18290 info
->vrsave_save_offset
);
18292 if (info
->lr_save_offset
)
18293 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
18295 if (info
->cr_save_offset
)
18296 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
18298 if (info
->varargs_save_offset
)
18299 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
18301 if (info
->total_size
)
18302 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
18305 if (info
->vars_size
)
18306 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
18309 if (info
->parm_size
)
18310 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
18312 if (info
->fixed_size
)
18313 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
18316 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
18318 if (info
->spe_gp_size
)
18319 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
18322 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
18324 if (info
->altivec_size
)
18325 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
18327 if (info
->vrsave_size
)
18328 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
18330 if (info
->altivec_padding_size
)
18331 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
18332 info
->altivec_padding_size
);
18334 if (info
->spe_padding_size
)
18335 fprintf (stderr
, "\tspe_padding_size = %5d\n",
18336 info
->spe_padding_size
);
18339 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
18341 if (info
->save_size
)
18342 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
18344 if (info
->reg_size
!= 4)
18345 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
18347 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
18349 fprintf (stderr
, "\n");
18353 rs6000_return_addr (int count
, rtx frame
)
18355 /* Currently we don't optimize very well between prolog and body
18356 code and for PIC code the code can be actually quite bad, so
18357 don't try to be too clever here. */
18358 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
18360 cfun
->machine
->ra_needs_full_frame
= 1;
18367 plus_constant (Pmode
,
18369 (gen_rtx_MEM (Pmode
,
18370 memory_address (Pmode
, frame
))),
18371 RETURN_ADDRESS_OFFSET
)));
18374 cfun
->machine
->ra_need_lr
= 1;
18375 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
18378 /* Say whether a function is a candidate for sibcall handling or not. */
18381 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
18386 fntype
= TREE_TYPE (decl
);
18388 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
18390 /* We can't do it if the called function has more vector parameters
18391 than the current function; there's nowhere to put the VRsave code. */
18392 if (TARGET_ALTIVEC_ABI
18393 && TARGET_ALTIVEC_VRSAVE
18394 && !(decl
&& decl
== current_function_decl
))
18396 function_args_iterator args_iter
;
18400 /* Functions with vector parameters are required to have a
18401 prototype, so the argument type info must be available
18403 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
18404 if (TREE_CODE (type
) == VECTOR_TYPE
18405 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
18408 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
18409 if (TREE_CODE (type
) == VECTOR_TYPE
18410 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
18417 /* Under the AIX ABI we can't allow calls to non-local functions,
18418 because the callee may have a different TOC pointer to the
18419 caller and there's no way to ensure we restore the TOC when we
18420 return. With the secure-plt SYSV ABI we can't make non-local
18421 calls when -fpic/PIC because the plt call stubs use r30. */
18422 if (DEFAULT_ABI
== ABI_DARWIN
18423 || (DEFAULT_ABI
== ABI_AIX
18425 && !DECL_EXTERNAL (decl
)
18426 && (*targetm
.binds_local_p
) (decl
))
18427 || (DEFAULT_ABI
== ABI_V4
18428 && (!TARGET_SECURE_PLT
18431 && (*targetm
.binds_local_p
) (decl
)))))
18433 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
18435 if (!lookup_attribute ("longcall", attr_list
)
18436 || lookup_attribute ("shortcall", attr_list
))
18443 /* NULL if INSN insn is valid within a low-overhead loop.
18444 Otherwise return why doloop cannot be applied.
18445 PowerPC uses the COUNT register for branch on table instructions. */
18447 static const char *
18448 rs6000_invalid_within_doloop (const_rtx insn
)
18451 return "Function call in the loop.";
18454 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
18455 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
18456 return "Computed branch in the loop.";
18462 rs6000_ra_ever_killed (void)
18468 if (cfun
->is_thunk
)
18471 if (cfun
->machine
->lr_save_state
)
18472 return cfun
->machine
->lr_save_state
- 1;
18474 /* regs_ever_live has LR marked as used if any sibcalls are present,
18475 but this should not force saving and restoring in the
18476 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18477 clobbers LR, so that is inappropriate. */
18479 /* Also, the prologue can generate a store into LR that
18480 doesn't really count, like this:
18483 bcl to set PIC register
18487 When we're called from the epilogue, we need to avoid counting
18488 this as a store. */
18490 push_topmost_sequence ();
18491 top
= get_insns ();
18492 pop_topmost_sequence ();
18493 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
18495 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
18501 if (!SIBLING_CALL_P (insn
))
18504 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
18506 else if (set_of (reg
, insn
) != NULL_RTX
18507 && !prologue_epilogue_contains (insn
))
18514 /* Emit instructions needed to load the TOC register.
18515 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18516 a constant pool; or for SVR4 -fpic. */
18519 rs6000_emit_load_toc_table (int fromprolog
)
18522 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
18524 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
18527 rtx lab
, tmp1
, tmp2
, got
;
18529 lab
= gen_label_rtx ();
18530 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
18531 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18533 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
18535 got
= rs6000_got_sym ();
18536 tmp1
= tmp2
= dest
;
18539 tmp1
= gen_reg_rtx (Pmode
);
18540 tmp2
= gen_reg_rtx (Pmode
);
18542 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
18543 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
18544 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
18545 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
18547 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
18549 emit_insn (gen_load_toc_v4_pic_si ());
18550 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18552 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
18555 rtx temp0
= (fromprolog
18556 ? gen_rtx_REG (Pmode
, 0)
18557 : gen_reg_rtx (Pmode
));
18563 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
18564 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18566 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
18567 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18569 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
18570 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18571 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
18577 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
18578 lab
= gen_label_rtx ();
18579 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
18580 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18581 if (TARGET_LINK_STACK
)
18582 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
18583 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
18585 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
18587 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
18589 /* This is for AIX code running in non-PIC ELF32. */
18592 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
18593 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18595 emit_insn (gen_elf_high (dest
, realsym
));
18596 emit_insn (gen_elf_low (dest
, dest
, realsym
));
18600 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
18603 emit_insn (gen_load_toc_aix_si (dest
));
18605 emit_insn (gen_load_toc_aix_di (dest
));
18609 /* Emit instructions to restore the link register after determining where
18610 its value has been stored. */
18613 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
18615 rs6000_stack_t
*info
= rs6000_stack_info ();
18618 operands
[0] = source
;
18619 operands
[1] = scratch
;
18621 if (info
->lr_save_p
)
18623 rtx frame_rtx
= stack_pointer_rtx
;
18624 HOST_WIDE_INT sp_offset
= 0;
18627 if (frame_pointer_needed
18628 || cfun
->calls_alloca
18629 || info
->total_size
> 32767)
18631 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
18632 emit_move_insn (operands
[1], tmp
);
18633 frame_rtx
= operands
[1];
18635 else if (info
->push_p
)
18636 sp_offset
= info
->total_size
;
18638 tmp
= plus_constant (Pmode
, frame_rtx
,
18639 info
->lr_save_offset
+ sp_offset
);
18640 tmp
= gen_frame_mem (Pmode
, tmp
);
18641 emit_move_insn (tmp
, operands
[0]);
18644 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
18646 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18647 state of lr_save_p so any change from here on would be a bug. In
18648 particular, stop rs6000_ra_ever_killed from considering the SET
18649 of lr we may have added just above. */
18650 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
18653 static GTY(()) alias_set_type set
= -1;
18656 get_TOC_alias_set (void)
18659 set
= new_alias_set ();
18663 /* This returns nonzero if the current function uses the TOC. This is
18664 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18665 is generated by the ABI_V4 load_toc_* patterns. */
18672 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
18675 rtx pat
= PATTERN (insn
);
18678 if (GET_CODE (pat
) == PARALLEL
)
18679 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18681 rtx sub
= XVECEXP (pat
, 0, i
);
18682 if (GET_CODE (sub
) == USE
)
18684 sub
= XEXP (sub
, 0);
18685 if (GET_CODE (sub
) == UNSPEC
18686 && XINT (sub
, 1) == UNSPEC_TOC
)
18696 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
18698 rtx tocrel
, tocreg
, hi
;
18700 if (TARGET_DEBUG_ADDR
)
18702 if (GET_CODE (symbol
) == SYMBOL_REF
)
18703 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18707 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
18708 GET_RTX_NAME (GET_CODE (symbol
)));
18709 debug_rtx (symbol
);
18713 if (!can_create_pseudo_p ())
18714 df_set_regs_ever_live (TOC_REGISTER
, true);
18716 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
18717 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
18718 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
18721 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
18722 if (largetoc_reg
!= NULL
)
18724 emit_move_insn (largetoc_reg
, hi
);
18727 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
18730 /* Issue assembly directives that create a reference to the given DWARF
18731 FRAME_TABLE_LABEL from the current function section. */
18733 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
18735 fprintf (asm_out_file
, "\t.ref %s\n",
18736 (* targetm
.strip_name_encoding
) (frame_table_label
));
18739 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18740 and the change to the stack pointer. */
18743 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
18750 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
18751 if (hard_frame_needed
)
18752 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
18753 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
18754 || (hard_frame_needed
18755 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
18758 p
= rtvec_alloc (i
);
18761 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
18762 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
18765 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
18768 /* Emit the correct code for allocating stack space, as insns.
18769 If COPY_REG, make sure a copy of the old frame is left there.
18770 The generated code may use hard register 0 as a temporary. */
18773 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
18776 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
18777 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
18778 rtx todec
= gen_int_mode (-size
, Pmode
);
18781 if (INTVAL (todec
) != -size
)
18783 warning (0, "stack frame too large");
18784 emit_insn (gen_trap ());
18788 if (crtl
->limit_stack
)
18790 if (REG_P (stack_limit_rtx
)
18791 && REGNO (stack_limit_rtx
) > 1
18792 && REGNO (stack_limit_rtx
) <= 31)
18794 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
18795 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
18798 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
18800 && DEFAULT_ABI
== ABI_V4
)
18802 rtx toload
= gen_rtx_CONST (VOIDmode
,
18803 gen_rtx_PLUS (Pmode
,
18807 emit_insn (gen_elf_high (tmp_reg
, toload
));
18808 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
18809 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
18813 warning (0, "stack limit expression is not supported");
18819 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
18821 emit_move_insn (copy_reg
, stack_reg
);
18826 /* Need a note here so that try_split doesn't get confused. */
18827 if (get_last_insn () == NULL_RTX
)
18828 emit_note (NOTE_INSN_DELETED
);
18829 insn
= emit_move_insn (tmp_reg
, todec
);
18830 try_split (PATTERN (insn
), insn
, 0);
18834 insn
= emit_insn (TARGET_32BIT
18835 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
18837 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
18838 todec
, stack_reg
));
18839 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18840 it now and set the alias set/attributes. The above gen_*_update
18841 calls will generate a PARALLEL with the MEM set being the first
18843 par
= PATTERN (insn
);
18844 gcc_assert (GET_CODE (par
) == PARALLEL
);
18845 set
= XVECEXP (par
, 0, 0);
18846 gcc_assert (GET_CODE (set
) == SET
);
18847 mem
= SET_DEST (set
);
18848 gcc_assert (MEM_P (mem
));
18849 MEM_NOTRAP_P (mem
) = 1;
18850 set_mem_alias_set (mem
, get_frame_alias_set ());
18852 RTX_FRAME_RELATED_P (insn
) = 1;
18853 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
18854 gen_rtx_SET (VOIDmode
, stack_reg
,
18855 gen_rtx_PLUS (Pmode
, stack_reg
,
18856 GEN_INT (-size
))));
18859 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18861 #if PROBE_INTERVAL > 32768
18862 #error Cannot use indexed addressing mode for stack probing
18865 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18866 inclusive. These are offsets from the current stack pointer. */
18869 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
18871 /* See if we have a constant small number of probes to generate. If so,
18872 that's the easy case. */
18873 if (first
+ size
<= 32768)
18877 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18878 it exceeds SIZE. If only one probe is needed, this will not
18879 generate any code. Then probe at FIRST + SIZE. */
18880 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
18881 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
18884 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
18888 /* Otherwise, do the same as above, but in a loop. Note that we must be
18889 extra careful with variables wrapping around because we might be at
18890 the very top (or the very bottom) of the address space and we have
18891 to be able to handle this case properly; in particular, we use an
18892 equality test for the loop condition. */
18895 HOST_WIDE_INT rounded_size
;
18896 rtx r12
= gen_rtx_REG (Pmode
, 12);
18897 rtx r0
= gen_rtx_REG (Pmode
, 0);
18899 /* Sanity check for the addressing mode we're going to use. */
18900 gcc_assert (first
<= 32768);
18902 /* Step 1: round SIZE to the previous multiple of the interval. */
18904 rounded_size
= size
& -PROBE_INTERVAL
;
18907 /* Step 2: compute initial and final value of the loop counter. */
18909 /* TEST_ADDR = SP + FIRST. */
18910 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
18911 plus_constant (Pmode
, stack_pointer_rtx
,
18914 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18915 if (rounded_size
> 32768)
18917 emit_move_insn (r0
, GEN_INT (-rounded_size
));
18918 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
18919 gen_rtx_PLUS (Pmode
, r12
, r0
)));
18922 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
18923 plus_constant (Pmode
, r12
, -rounded_size
)));
18926 /* Step 3: the loop
18928 while (TEST_ADDR != LAST_ADDR)
18930 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18934 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18935 until it is equal to ROUNDED_SIZE. */
18938 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
18940 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
18943 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18944 that SIZE is equal to ROUNDED_SIZE. */
18946 if (size
!= rounded_size
)
18947 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
18951 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18952 absolute addresses. */
18955 output_probe_stack_range (rtx reg1
, rtx reg2
)
18957 static int labelno
= 0;
18958 char loop_lab
[32], end_lab
[32];
18961 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
18962 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
18964 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
18966 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18970 output_asm_insn ("cmpd 0,%0,%1", xops
);
18972 output_asm_insn ("cmpw 0,%0,%1", xops
);
18974 fputs ("\tbeq 0,", asm_out_file
);
18975 assemble_name_raw (asm_out_file
, end_lab
);
18976 fputc ('\n', asm_out_file
);
18978 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18979 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
18980 output_asm_insn ("addi %0,%0,%1", xops
);
18982 /* Probe at TEST_ADDR and branch. */
18983 xops
[1] = gen_rtx_REG (Pmode
, 0);
18984 output_asm_insn ("stw %1,0(%0)", xops
);
18985 fprintf (asm_out_file
, "\tb ");
18986 assemble_name_raw (asm_out_file
, loop_lab
);
18987 fputc ('\n', asm_out_file
);
18989 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
18994 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18995 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18996 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18997 deduce these equivalences by itself so it wasn't necessary to hold
18998 its hand so much. Don't be tempted to always supply d2_f_d_e with
18999 the actual cfa register, ie. r31 when we are using a hard frame
19000 pointer. That fails when saving regs off r1, and sched moves the
19001 r31 setup past the reg saves. */
19004 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
19005 rtx reg2
, rtx rreg
)
19009 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
19011 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
19014 gcc_checking_assert (val
== 0);
19015 real
= PATTERN (insn
);
19016 if (GET_CODE (real
) == PARALLEL
)
19017 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
19018 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
19020 rtx set
= XVECEXP (real
, 0, i
);
19022 RTX_FRAME_RELATED_P (set
) = 1;
19024 RTX_FRAME_RELATED_P (insn
) = 1;
19028 /* copy_rtx will not make unique copies of registers, so we need to
19029 ensure we don't have unwanted sharing here. */
19031 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
19034 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
19036 real
= copy_rtx (PATTERN (insn
));
19038 if (reg2
!= NULL_RTX
)
19039 real
= replace_rtx (real
, reg2
, rreg
);
19041 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
19042 gcc_checking_assert (val
== 0);
19044 real
= replace_rtx (real
, reg
,
19045 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
19046 STACK_POINTER_REGNUM
),
19049 /* We expect that 'real' is either a SET or a PARALLEL containing
19050 SETs (and possibly other stuff). In a PARALLEL, all the SETs
19051 are important so they all have to be marked RTX_FRAME_RELATED_P. */
19053 if (GET_CODE (real
) == SET
)
19057 temp
= simplify_rtx (SET_SRC (set
));
19059 SET_SRC (set
) = temp
;
19060 temp
= simplify_rtx (SET_DEST (set
));
19062 SET_DEST (set
) = temp
;
19063 if (GET_CODE (SET_DEST (set
)) == MEM
)
19065 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
19067 XEXP (SET_DEST (set
), 0) = temp
;
19074 gcc_assert (GET_CODE (real
) == PARALLEL
);
19075 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
19076 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
19078 rtx set
= XVECEXP (real
, 0, i
);
19080 temp
= simplify_rtx (SET_SRC (set
));
19082 SET_SRC (set
) = temp
;
19083 temp
= simplify_rtx (SET_DEST (set
));
19085 SET_DEST (set
) = temp
;
19086 if (GET_CODE (SET_DEST (set
)) == MEM
)
19088 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
19090 XEXP (SET_DEST (set
), 0) = temp
;
19092 RTX_FRAME_RELATED_P (set
) = 1;
19096 RTX_FRAME_RELATED_P (insn
) = 1;
19097 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
19102 /* Returns an insn that has a vrsave set operation with the
19103 appropriate CLOBBERs. */
19106 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
19109 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
19110 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
19113 = gen_rtx_SET (VOIDmode
,
19115 gen_rtx_UNSPEC_VOLATILE (SImode
,
19116 gen_rtvec (2, reg
, vrsave
),
19117 UNSPECV_SET_VRSAVE
));
19121 /* We need to clobber the registers in the mask so the scheduler
19122 does not move sets to VRSAVE before sets of AltiVec registers.
19124 However, if the function receives nonlocal gotos, reload will set
19125 all call saved registers live. We will end up with:
19127 (set (reg 999) (mem))
19128 (parallel [ (set (reg vrsave) (unspec blah))
19129 (clobber (reg 999))])
19131 The clobber will cause the store into reg 999 to be dead, and
19132 flow will attempt to delete an epilogue insn. In this case, we
19133 need an unspec use/set of the register. */
19135 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19136 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
19138 if (!epiloguep
|| call_used_regs
[i
])
19139 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
19140 gen_rtx_REG (V4SImode
, i
));
19143 rtx reg
= gen_rtx_REG (V4SImode
, i
);
19146 = gen_rtx_SET (VOIDmode
,
19148 gen_rtx_UNSPEC (V4SImode
,
19149 gen_rtvec (1, reg
), 27));
19153 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
19155 for (i
= 0; i
< nclobs
; ++i
)
19156 XVECEXP (insn
, 0, i
) = clobs
[i
];
19162 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
19166 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
19167 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
19168 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
19172 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
19174 return gen_frame_set (reg
, frame_reg
, offset
, false);
19178 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
19180 return gen_frame_set (reg
, frame_reg
, offset
, true);
19183 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
19184 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
19187 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
19188 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
19192 /* Some cases that need register indexed addressing. */
19193 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
19194 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
19195 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
19197 && SPE_VECTOR_MODE (mode
)
19198 && !SPE_CONST_OFFSET_OK (offset
))));
19200 reg
= gen_rtx_REG (mode
, regno
);
19201 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
19202 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
19203 NULL_RTX
, NULL_RTX
);
19206 /* Emit an offset memory reference suitable for a frame store, while
19207 converting to a valid addressing mode. */
19210 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
19212 rtx int_rtx
, offset_rtx
;
19214 int_rtx
= GEN_INT (offset
);
19216 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
19217 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
19219 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
19220 emit_move_insn (offset_rtx
, int_rtx
);
19223 offset_rtx
= int_rtx
;
19225 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
19228 #ifndef TARGET_FIX_AND_CONTINUE
19229 #define TARGET_FIX_AND_CONTINUE 0
19232 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
19233 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
19234 #define LAST_SAVRES_REGISTER 31
19235 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
19246 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
19248 /* Temporary holding space for an out-of-line register save/restore
19250 static char savres_routine_name
[30];
19252 /* Return the name for an out-of-line register save/restore routine.
19253 We are saving/restoring GPRs if GPR is true. */
19256 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
19258 const char *prefix
= "";
19259 const char *suffix
= "";
19261 /* Different targets are supposed to define
19262 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
19263 routine name could be defined with:
19265 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
19267 This is a nice idea in practice, but in reality, things are
19268 complicated in several ways:
19270 - ELF targets have save/restore routines for GPRs.
19272 - SPE targets use different prefixes for 32/64-bit registers, and
19273 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
19275 - PPC64 ELF targets have routines for save/restore of GPRs that
19276 differ in what they do with the link register, so having a set
19277 prefix doesn't work. (We only use one of the save routines at
19278 the moment, though.)
19280 - PPC32 elf targets have "exit" versions of the restore routines
19281 that restore the link register and can save some extra space.
19282 These require an extra suffix. (There are also "tail" versions
19283 of the restore routines and "GOT" versions of the save routines,
19284 but we don't generate those at present. Same problems apply,
19287 We deal with all this by synthesizing our own prefix/suffix and
19288 using that for the simple sprintf call shown above. */
19291 /* No floating point saves on the SPE. */
19292 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
19294 if ((sel
& SAVRES_SAVE
))
19295 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
19297 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
19299 if ((sel
& SAVRES_LR
))
19302 else if (DEFAULT_ABI
== ABI_V4
)
19307 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
19308 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
19309 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
19310 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
19311 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19312 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
19316 if ((sel
& SAVRES_LR
))
19319 else if (DEFAULT_ABI
== ABI_AIX
)
19321 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
19322 /* No out-of-line save/restore routines for GPRs on AIX. */
19323 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
19327 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
19328 prefix
= ((sel
& SAVRES_SAVE
)
19329 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
19330 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
19331 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
19333 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
19334 if ((sel
& SAVRES_LR
))
19335 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
19339 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
19340 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
19343 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19344 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
19349 if (DEFAULT_ABI
== ABI_DARWIN
)
19351 /* The Darwin approach is (slightly) different, in order to be
19352 compatible with code generated by the system toolchain. There is a
19353 single symbol for the start of save sequence, and the code here
19354 embeds an offset into that code on the basis of the first register
19356 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
19357 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
19358 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
19359 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
19360 (regno
- 13) * 4, prefix
, regno
);
19361 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
19362 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
19363 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
19364 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19365 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
19366 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
19371 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
19373 return savres_routine_name
;
19376 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19377 We are saving/restoring GPRs if GPR is true. */
19380 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
19382 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
19383 ? info
->first_gp_reg_save
19384 : (sel
& SAVRES_REG
) == SAVRES_FPR
19385 ? info
->first_fp_reg_save
- 32
19386 : (sel
& SAVRES_REG
) == SAVRES_VR
19387 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
19392 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
19393 versions of the gpr routines. */
19394 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
19395 && info
->spe_64bit_regs_used
)
19396 select
^= SAVRES_FPR
^ SAVRES_GPR
;
19398 /* Don't generate bogus routine names. */
19399 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
19400 && regno
<= LAST_SAVRES_REGISTER
19401 && select
>= 0 && select
<= 12);
19403 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
19409 name
= rs6000_savres_routine_name (info
, regno
, sel
);
19411 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
19412 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
19413 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
19419 /* Emit a sequence of insns, including a stack tie if needed, for
19420 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
19421 reset the stack pointer, but move the base of the frame into
19422 reg UPDT_REGNO for use by out-of-line register restore routines. */
19425 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
19426 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
19427 unsigned updt_regno
)
19431 /* This blockage is needed so that sched doesn't decide to move
19432 the sp change before the register restores. */
19433 if (DEFAULT_ABI
== ABI_V4
19435 && info
->spe_64bit_regs_used
!= 0
19436 && info
->first_gp_reg_save
!= 32))
19437 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
19439 /* If we are restoring registers out-of-line, we will be using the
19440 "exit" variants of the restore routines, which will reset the
19441 stack for us. But we do need to point updt_reg into the
19442 right place for those routines. */
19443 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
19445 if (frame_off
!= 0)
19446 return emit_insn (gen_add3_insn (updt_reg_rtx
,
19447 frame_reg_rtx
, GEN_INT (frame_off
)));
19448 else if (REGNO (frame_reg_rtx
) != updt_regno
)
19449 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
19454 /* Return the register number used as a pointer by out-of-line
19455 save/restore functions. */
19457 static inline unsigned
19458 ptr_regno_for_savres (int sel
)
19460 if (DEFAULT_ABI
== ABI_AIX
)
19461 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
19462 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
19465 /* Construct a parallel rtx describing the effect of a call to an
19466 out-of-line register save/restore routine, and emit the insn
19467 or jump_insn as appropriate. */
19470 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
19471 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
19472 enum machine_mode reg_mode
, int sel
)
19475 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
19476 int reg_size
= GET_MODE_SIZE (reg_mode
);
19482 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
19483 ? info
->first_gp_reg_save
19484 : (sel
& SAVRES_REG
) == SAVRES_FPR
19485 ? info
->first_fp_reg_save
19486 : (sel
& SAVRES_REG
) == SAVRES_VR
19487 ? info
->first_altivec_reg_save
19489 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
19491 : (sel
& SAVRES_REG
) == SAVRES_FPR
19493 : (sel
& SAVRES_REG
) == SAVRES_VR
19494 ? LAST_ALTIVEC_REGNO
+ 1
19496 n_regs
= end_reg
- start_reg
;
19497 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
19498 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
19501 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
19502 RTVEC_ELT (p
, offset
++) = ret_rtx
;
19504 RTVEC_ELT (p
, offset
++)
19505 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
19507 sym
= rs6000_savres_routine_sym (info
, sel
);
19508 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
19510 use_reg
= ptr_regno_for_savres (sel
);
19511 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
19513 /* Vector regs are saved/restored using [reg+reg] addressing. */
19514 RTVEC_ELT (p
, offset
++)
19515 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
19516 RTVEC_ELT (p
, offset
++)
19517 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
19520 RTVEC_ELT (p
, offset
++)
19521 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
19523 for (i
= 0; i
< end_reg
- start_reg
; i
++)
19524 RTVEC_ELT (p
, i
+ offset
)
19525 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
19526 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
19527 (sel
& SAVRES_SAVE
) != 0);
19529 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
19530 RTVEC_ELT (p
, i
+ offset
)
19531 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
19533 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
19535 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
19537 insn
= emit_jump_insn (par
);
19538 JUMP_LABEL (insn
) = ret_rtx
;
19541 insn
= emit_insn (par
);
19545 /* Determine whether the gp REG is really used. */
19548 rs6000_reg_live_or_pic_offset_p (int reg
)
19550 /* If the function calls eh_return, claim used all the registers that would
19551 be checked for liveness otherwise. This is required for the PIC offset
19552 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19553 register allocation purposes in this case. */
19555 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
19556 && (!call_used_regs
[reg
]
19557 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
19558 && !TARGET_SINGLE_PIC_BASE
19559 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
19560 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
19561 && !TARGET_SINGLE_PIC_BASE
19562 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19563 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
19566 /* Emit function prologue as insns. */
19569 rs6000_emit_prologue (void)
19571 rs6000_stack_t
*info
= rs6000_stack_info ();
19572 enum machine_mode reg_mode
= Pmode
;
19573 int reg_size
= TARGET_32BIT
? 4 : 8;
19574 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
19575 rtx frame_reg_rtx
= sp_reg_rtx
;
19576 unsigned int cr_save_regno
;
19577 rtx cr_save_rtx
= NULL_RTX
;
19580 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
19581 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
19582 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
19583 /* Offset to top of frame for frame_reg and sp respectively. */
19584 HOST_WIDE_INT frame_off
= 0;
19585 HOST_WIDE_INT sp_off
= 0;
19587 #ifdef ENABLE_CHECKING
19588 /* Track and check usage of r0, r11, r12. */
19589 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
19590 #define START_USE(R) do \
19592 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19593 reg_inuse |= 1 << (R); \
19595 #define END_USE(R) do \
19597 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
19598 reg_inuse &= ~(1 << (R)); \
19600 #define NOT_INUSE(R) do \
19602 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19605 #define START_USE(R) do {} while (0)
19606 #define END_USE(R) do {} while (0)
19607 #define NOT_INUSE(R) do {} while (0)
19610 if (flag_stack_usage_info
)
19611 current_function_static_stack_size
= info
->total_size
;
19613 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& info
->total_size
)
19614 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, info
->total_size
);
19616 if (TARGET_FIX_AND_CONTINUE
)
19618 /* gdb on darwin arranges to forward a function from the old
19619 address by modifying the first 5 instructions of the function
19620 to branch to the overriding function. This is necessary to
19621 permit function pointers that point to the old function to
19622 actually forward to the new function. */
19623 emit_insn (gen_nop ());
19624 emit_insn (gen_nop ());
19625 emit_insn (gen_nop ());
19626 emit_insn (gen_nop ());
19627 emit_insn (gen_nop ());
19630 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
19632 reg_mode
= V2SImode
;
19636 /* Handle world saves specially here. */
19637 if (WORLD_SAVE_P (info
))
19644 /* save_world expects lr in r0. */
19645 reg0
= gen_rtx_REG (Pmode
, 0);
19646 if (info
->lr_save_p
)
19648 insn
= emit_move_insn (reg0
,
19649 gen_rtx_REG (Pmode
, LR_REGNO
));
19650 RTX_FRAME_RELATED_P (insn
) = 1;
19653 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19654 assumptions about the offsets of various bits of the stack
19656 gcc_assert (info
->gp_save_offset
== -220
19657 && info
->fp_save_offset
== -144
19658 && info
->lr_save_offset
== 8
19659 && info
->cr_save_offset
== 4
19662 && (!crtl
->calls_eh_return
19663 || info
->ehrd_offset
== -432)
19664 && info
->vrsave_save_offset
== -224
19665 && info
->altivec_save_offset
== -416);
19667 treg
= gen_rtx_REG (SImode
, 11);
19668 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
19670 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19671 in R11. It also clobbers R12, so beware! */
19673 /* Preserve CR2 for save_world prologues */
19675 sz
+= 32 - info
->first_gp_reg_save
;
19676 sz
+= 64 - info
->first_fp_reg_save
;
19677 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
19678 p
= rtvec_alloc (sz
);
19680 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
19681 gen_rtx_REG (SImode
,
19683 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
19684 gen_rtx_SYMBOL_REF (Pmode
,
19686 /* We do floats first so that the instruction pattern matches
19688 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
19690 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
19692 info
->first_fp_reg_save
+ i
),
19694 info
->fp_save_offset
+ frame_off
+ 8 * i
);
19695 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
19697 = gen_frame_store (gen_rtx_REG (V4SImode
,
19698 info
->first_altivec_reg_save
+ i
),
19700 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
19701 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19703 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
19705 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
19707 /* CR register traditionally saved as CR2. */
19709 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
19710 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
19711 /* Explain about use of R0. */
19712 if (info
->lr_save_p
)
19714 = gen_frame_store (reg0
,
19715 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
19716 /* Explain what happens to the stack pointer. */
19718 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
19719 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
19722 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
19723 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
19724 treg
, GEN_INT (-info
->total_size
));
19725 sp_off
= frame_off
= info
->total_size
;
19728 strategy
= info
->savres_strategy
;
19730 /* For V.4, update stack before we do any saving and set back pointer. */
19731 if (! WORLD_SAVE_P (info
)
19733 && (DEFAULT_ABI
== ABI_V4
19734 || crtl
->calls_eh_return
))
19736 bool need_r11
= (TARGET_SPE
19737 ? (!(strategy
& SAVE_INLINE_GPRS
)
19738 && info
->spe_64bit_regs_used
== 0)
19739 : (!(strategy
& SAVE_INLINE_FPRS
)
19740 || !(strategy
& SAVE_INLINE_GPRS
)
19741 || !(strategy
& SAVE_INLINE_VRS
)));
19742 int ptr_regno
= -1;
19743 rtx ptr_reg
= NULL_RTX
;
19746 if (info
->total_size
< 32767)
19747 frame_off
= info
->total_size
;
19750 else if (info
->cr_save_p
19752 || info
->first_fp_reg_save
< 64
19753 || info
->first_gp_reg_save
< 32
19754 || info
->altivec_size
!= 0
19755 || info
->vrsave_mask
!= 0
19756 || crtl
->calls_eh_return
)
19760 /* The prologue won't be saving any regs so there is no need
19761 to set up a frame register to access any frame save area.
19762 We also won't be using frame_off anywhere below, but set
19763 the correct value anyway to protect against future
19764 changes to this function. */
19765 frame_off
= info
->total_size
;
19767 if (ptr_regno
!= -1)
19769 /* Set up the frame offset to that needed by the first
19770 out-of-line save function. */
19771 START_USE (ptr_regno
);
19772 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
19773 frame_reg_rtx
= ptr_reg
;
19774 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
19775 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
19776 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
19777 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
19778 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
19779 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
19780 frame_off
= -ptr_off
;
19782 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
19783 sp_off
= info
->total_size
;
19784 if (frame_reg_rtx
!= sp_reg_rtx
)
19785 rs6000_emit_stack_tie (frame_reg_rtx
, false);
19788 /* If we use the link register, get it into r0. */
19789 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
19791 rtx addr
, reg
, mem
;
19793 reg
= gen_rtx_REG (Pmode
, 0);
19795 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
19796 RTX_FRAME_RELATED_P (insn
) = 1;
19798 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
19799 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
19801 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19802 GEN_INT (info
->lr_save_offset
+ frame_off
));
19803 mem
= gen_rtx_MEM (Pmode
, addr
);
19804 /* This should not be of rs6000_sr_alias_set, because of
19805 __builtin_return_address. */
19807 insn
= emit_move_insn (mem
, reg
);
19808 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
19809 NULL_RTX
, NULL_RTX
);
19814 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
19815 r12 will be needed by out-of-line gpr restore. */
19816 cr_save_regno
= (DEFAULT_ABI
== ABI_AIX
19817 && !(strategy
& (SAVE_INLINE_GPRS
19818 | SAVE_NOINLINE_GPRS_SAVES_LR
))
19820 if (!WORLD_SAVE_P (info
)
19822 && REGNO (frame_reg_rtx
) != cr_save_regno
19823 && !(using_static_chain_p
&& cr_save_regno
== 11))
19827 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
19828 START_USE (cr_save_regno
);
19829 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
19830 RTX_FRAME_RELATED_P (insn
) = 1;
19831 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19832 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19833 But that's OK. All we have to do is specify that _one_ condition
19834 code register is saved in this stack slot. The thrower's epilogue
19835 will then restore all the call-saved registers.
19836 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19837 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
19838 gen_rtx_REG (SImode
, CR2_REGNO
));
19839 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
19842 /* Do any required saving of fpr's. If only one or two to save, do
19843 it ourselves. Otherwise, call function. */
19844 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
19847 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
19848 if (save_reg_p (info
->first_fp_reg_save
+ i
))
19849 emit_frame_save (frame_reg_rtx
,
19850 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
19851 ? DFmode
: SFmode
),
19852 info
->first_fp_reg_save
+ i
,
19853 info
->fp_save_offset
+ frame_off
+ 8 * i
,
19854 sp_off
- frame_off
);
19856 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
19858 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
19859 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
19860 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
19861 rtx ptr_reg
= frame_reg_rtx
;
19863 if (REGNO (frame_reg_rtx
) == ptr_regno
)
19864 gcc_checking_assert (frame_off
== 0);
19867 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
19868 NOT_INUSE (ptr_regno
);
19869 emit_insn (gen_add3_insn (ptr_reg
,
19870 frame_reg_rtx
, GEN_INT (frame_off
)));
19872 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
19873 info
->fp_save_offset
,
19874 info
->lr_save_offset
,
19876 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
19877 NULL_RTX
, NULL_RTX
);
19882 /* Save GPRs. This is done as a PARALLEL if we are using
19883 the store-multiple instructions. */
19884 if (!WORLD_SAVE_P (info
)
19886 && info
->spe_64bit_regs_used
!= 0
19887 && info
->first_gp_reg_save
!= 32)
19890 rtx spe_save_area_ptr
;
19891 HOST_WIDE_INT save_off
;
19892 int ool_adjust
= 0;
19894 /* Determine whether we can address all of the registers that need
19895 to be saved with an offset from frame_reg_rtx that fits in
19896 the small const field for SPE memory instructions. */
19897 int spe_regs_addressable
19898 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
19899 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
19900 && (strategy
& SAVE_INLINE_GPRS
));
19902 if (spe_regs_addressable
)
19904 spe_save_area_ptr
= frame_reg_rtx
;
19905 save_off
= frame_off
;
19909 /* Make r11 point to the start of the SPE save area. We need
19910 to be careful here if r11 is holding the static chain. If
19911 it is, then temporarily save it in r0. */
19912 HOST_WIDE_INT offset
;
19914 if (!(strategy
& SAVE_INLINE_GPRS
))
19915 ool_adjust
= 8 * (info
->first_gp_reg_save
19916 - (FIRST_SAVRES_REGISTER
+ 1));
19917 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
19918 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
19919 save_off
= frame_off
- offset
;
19921 if (using_static_chain_p
)
19923 rtx r0
= gen_rtx_REG (Pmode
, 0);
19926 gcc_assert (info
->first_gp_reg_save
> 11);
19928 emit_move_insn (r0
, spe_save_area_ptr
);
19930 else if (REGNO (frame_reg_rtx
) != 11)
19933 emit_insn (gen_addsi3 (spe_save_area_ptr
,
19934 frame_reg_rtx
, GEN_INT (offset
)));
19935 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
19936 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
19939 if ((strategy
& SAVE_INLINE_GPRS
))
19941 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19942 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
19943 emit_frame_save (spe_save_area_ptr
, reg_mode
,
19944 info
->first_gp_reg_save
+ i
,
19945 (info
->spe_gp_save_offset
+ save_off
19947 sp_off
- save_off
);
19951 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
19952 info
->spe_gp_save_offset
+ save_off
,
19954 SAVRES_SAVE
| SAVRES_GPR
);
19956 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
19957 NULL_RTX
, NULL_RTX
);
19960 /* Move the static chain pointer back. */
19961 if (!spe_regs_addressable
)
19963 if (using_static_chain_p
)
19965 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
19968 else if (REGNO (frame_reg_rtx
) != 11)
19972 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
19974 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
19975 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
19976 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
19977 rtx ptr_reg
= frame_reg_rtx
;
19978 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
19979 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
19983 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
19985 /* Need to adjust r11 (r12) if we saved any FPRs. */
19986 if (end_save
+ frame_off
!= 0)
19988 rtx offset
= GEN_INT (end_save
+ frame_off
);
19991 frame_off
= -end_save
;
19993 NOT_INUSE (ptr_regno
);
19994 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
19996 else if (!ptr_set_up
)
19998 NOT_INUSE (ptr_regno
);
19999 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20001 ptr_off
= -end_save
;
20002 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
20003 info
->gp_save_offset
+ ptr_off
,
20004 info
->lr_save_offset
+ ptr_off
,
20006 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
20007 NULL_RTX
, NULL_RTX
);
20011 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
20015 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
20016 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20018 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
20020 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
20021 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20022 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20023 NULL_RTX
, NULL_RTX
);
20025 else if (!WORLD_SAVE_P (info
))
20028 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20029 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
20030 emit_frame_save (frame_reg_rtx
, reg_mode
,
20031 info
->first_gp_reg_save
+ i
,
20032 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
20033 sp_off
- frame_off
);
20036 if (crtl
->calls_eh_return
)
20043 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
20044 if (regno
== INVALID_REGNUM
)
20048 p
= rtvec_alloc (i
);
20052 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
20053 if (regno
== INVALID_REGNUM
)
20057 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
20059 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
20060 RTVEC_ELT (p
, i
) = insn
;
20061 RTX_FRAME_RELATED_P (insn
) = 1;
20064 insn
= emit_insn (gen_blockage ());
20065 RTX_FRAME_RELATED_P (insn
) = 1;
20066 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
20069 /* In AIX ABI we need to make sure r2 is really saved. */
20070 if (TARGET_AIX
&& crtl
->calls_eh_return
)
20072 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
20073 rtx save_insn
, join_insn
, note
;
20074 long toc_restore_insn
;
20076 tmp_reg
= gen_rtx_REG (Pmode
, 11);
20077 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
20078 if (using_static_chain_p
)
20081 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
20085 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
20086 /* Peek at instruction to which this function returns. If it's
20087 restoring r2, then we know we've already saved r2. We can't
20088 unconditionally save r2 because the value we have will already
20089 be updated if we arrived at this function via a plt call or
20090 toc adjusting stub. */
20091 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
20092 toc_restore_insn
= TARGET_32BIT
? 0x80410014 : 0xE8410028;
20093 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
20094 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
20095 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
20096 validate_condition_mode (EQ
, CCUNSmode
);
20097 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
20098 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
20099 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
20100 toc_save_done
= gen_label_rtx ();
20101 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
20102 gen_rtx_EQ (VOIDmode
, compare_result
,
20104 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
20106 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
20107 JUMP_LABEL (jump
) = toc_save_done
;
20108 LABEL_NUSES (toc_save_done
) += 1;
20110 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
20111 TOC_REGNUM
, frame_off
+ 5 * reg_size
,
20112 sp_off
- frame_off
);
20114 emit_label (toc_save_done
);
20116 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
20117 have a CFG that has different saves along different paths.
20118 Move the note to a dummy blockage insn, which describes that
20119 R2 is unconditionally saved after the label. */
20120 /* ??? An alternate representation might be a special insn pattern
20121 containing both the branch and the store. That might let the
20122 code that minimizes the number of DW_CFA_advance opcodes better
20123 freedom in placing the annotations. */
20124 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
20126 remove_note (save_insn
, note
);
20128 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
20129 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
20130 RTX_FRAME_RELATED_P (save_insn
) = 0;
20132 join_insn
= emit_insn (gen_blockage ());
20133 REG_NOTES (join_insn
) = note
;
20134 RTX_FRAME_RELATED_P (join_insn
) = 1;
20136 if (using_static_chain_p
)
20138 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
20145 /* Save CR if we use any that must be preserved. */
20146 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
20148 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20149 GEN_INT (info
->cr_save_offset
+ frame_off
));
20150 rtx mem
= gen_frame_mem (SImode
, addr
);
20151 /* See the large comment above about why CR2_REGNO is used. */
20152 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
20154 /* If we didn't copy cr before, do so now using r0. */
20155 if (cr_save_rtx
== NULL_RTX
)
20160 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
20161 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
20162 RTX_FRAME_RELATED_P (insn
) = 1;
20163 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
20164 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
20166 insn
= emit_move_insn (mem
, cr_save_rtx
);
20167 END_USE (REGNO (cr_save_rtx
));
20169 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20170 NULL_RTX
, NULL_RTX
);
20173 /* Update stack and set back pointer unless this is V.4,
20174 for which it was done previously. */
20175 if (!WORLD_SAVE_P (info
) && info
->push_p
20176 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
20178 rtx ptr_reg
= NULL
;
20181 /* If saving altivec regs we need to be able to address all save
20182 locations using a 16-bit offset. */
20183 if ((strategy
& SAVE_INLINE_VRS
) == 0
20184 || (info
->altivec_size
!= 0
20185 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
20186 + info
->total_size
- frame_off
) > 32767)
20187 || (info
->vrsave_size
!= 0
20188 && (info
->vrsave_save_offset
20189 + info
->total_size
- frame_off
) > 32767))
20191 int sel
= SAVRES_SAVE
| SAVRES_VR
;
20192 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
20194 if (using_static_chain_p
20195 && ptr_regno
== STATIC_CHAIN_REGNUM
)
20197 if (REGNO (frame_reg_rtx
) != ptr_regno
)
20198 START_USE (ptr_regno
);
20199 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
20200 frame_reg_rtx
= ptr_reg
;
20201 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
20202 frame_off
= -ptr_off
;
20204 else if (REGNO (frame_reg_rtx
) == 1)
20205 frame_off
= info
->total_size
;
20206 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
20207 sp_off
= info
->total_size
;
20208 if (frame_reg_rtx
!= sp_reg_rtx
)
20209 rs6000_emit_stack_tie (frame_reg_rtx
, false);
20212 /* Set frame pointer, if needed. */
20213 if (frame_pointer_needed
)
20215 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
20217 RTX_FRAME_RELATED_P (insn
) = 1;
20220 /* Save AltiVec registers if needed. Save here because the red zone does
20221 not always include AltiVec registers. */
20222 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
20223 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
20225 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
20227 /* Oddly, the vector save/restore functions point r0 at the end
20228 of the save area, then use r11 or r12 to load offsets for
20229 [reg+reg] addressing. */
20230 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
20231 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
20232 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
20234 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
20236 if (end_save
+ frame_off
!= 0)
20238 rtx offset
= GEN_INT (end_save
+ frame_off
);
20240 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
20243 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20245 ptr_off
= -end_save
;
20246 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
20247 info
->altivec_save_offset
+ ptr_off
,
20248 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
20249 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
20250 NULL_RTX
, NULL_RTX
);
20251 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
20253 /* The oddity mentioned above clobbered our frame reg. */
20254 emit_move_insn (frame_reg_rtx
, ptr_reg
);
20255 frame_off
= ptr_off
;
20258 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
20259 && info
->altivec_size
!= 0)
20263 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20264 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20266 rtx areg
, savereg
, mem
;
20269 offset
= (info
->altivec_save_offset
+ frame_off
20270 + 16 * (i
- info
->first_altivec_reg_save
));
20272 savereg
= gen_rtx_REG (V4SImode
, i
);
20275 areg
= gen_rtx_REG (Pmode
, 0);
20276 emit_move_insn (areg
, GEN_INT (offset
));
20278 /* AltiVec addressing mode is [reg+reg]. */
20279 mem
= gen_frame_mem (V4SImode
,
20280 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
20282 insn
= emit_move_insn (mem
, savereg
);
20284 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20285 areg
, GEN_INT (offset
));
20289 /* VRSAVE is a bit vector representing which AltiVec registers
20290 are used. The OS uses this to determine which vector
20291 registers to save on a context switch. We need to save
20292 VRSAVE on the stack frame, add whatever AltiVec registers we
20293 used in this function, and do the corresponding magic in the
20296 if (!WORLD_SAVE_P (info
)
20298 && TARGET_ALTIVEC_VRSAVE
20299 && info
->vrsave_mask
!= 0)
20305 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
20306 be using r12 as frame_reg_rtx and r11 as the static chain
20307 pointer for nested functions. */
20309 if (DEFAULT_ABI
== ABI_AIX
&& !using_static_chain_p
)
20311 else if (REGNO (frame_reg_rtx
) == 12)
20314 if (using_static_chain_p
)
20318 NOT_INUSE (save_regno
);
20319 reg
= gen_rtx_REG (SImode
, save_regno
);
20320 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
20322 emit_insn (gen_get_vrsave_internal (reg
));
20324 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
20327 offset
= info
->vrsave_save_offset
+ frame_off
;
20328 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
20330 /* Include the registers in the mask. */
20331 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
20333 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
20336 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
20337 if (!TARGET_SINGLE_PIC_BASE
20338 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
20339 || (DEFAULT_ABI
== ABI_V4
20340 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
20341 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
20343 /* If emit_load_toc_table will use the link register, we need to save
20344 it. We use R12 for this purpose because emit_load_toc_table
20345 can use register 0. This allows us to use a plain 'blr' to return
20346 from the procedure more often. */
20347 int save_LR_around_toc_setup
= (TARGET_ELF
20348 && DEFAULT_ABI
!= ABI_AIX
20350 && ! info
->lr_save_p
20351 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
20352 if (save_LR_around_toc_setup
)
20354 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
20355 rtx tmp
= gen_rtx_REG (Pmode
, 12);
20357 insn
= emit_move_insn (tmp
, lr
);
20358 RTX_FRAME_RELATED_P (insn
) = 1;
20360 rs6000_emit_load_toc_table (TRUE
);
20362 insn
= emit_move_insn (lr
, tmp
);
20363 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
20364 RTX_FRAME_RELATED_P (insn
) = 1;
20367 rs6000_emit_load_toc_table (TRUE
);
20371 if (!TARGET_SINGLE_PIC_BASE
20372 && DEFAULT_ABI
== ABI_DARWIN
20373 && flag_pic
&& crtl
->uses_pic_offset_table
)
20375 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
20376 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
20378 /* Save and restore LR locally around this call (in R0). */
20379 if (!info
->lr_save_p
)
20380 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
20382 emit_insn (gen_load_macho_picbase (src
));
20384 emit_move_insn (gen_rtx_REG (Pmode
,
20385 RS6000_PIC_OFFSET_TABLE_REGNUM
),
20388 if (!info
->lr_save_p
)
20389 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
20393 /* If we need to, save the TOC register after doing the stack setup.
20394 Do not emit eh frame info for this save. The unwinder wants info,
20395 conceptually attached to instructions in this function, about
20396 register values in the caller of this function. This R2 may have
20397 already been changed from the value in the caller.
20398 We don't attempt to write accurate DWARF EH frame info for R2
20399 because code emitted by gcc for a (non-pointer) function call
20400 doesn't save and restore R2. Instead, R2 is managed out-of-line
20401 by a linker generated plt call stub when the function resides in
20402 a shared library. This behaviour is costly to describe in DWARF,
20403 both in terms of the size of DWARF info and the time taken in the
20404 unwinder to interpret it. R2 changes, apart from the
20405 calls_eh_return case earlier in this function, are handled by
20406 linux-unwind.h frob_update_context. */
20407 if (rs6000_save_toc_in_prologue_p ())
20409 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
20410 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, 5 * reg_size
));
20414 /* Write function prologue. */
20417 rs6000_output_function_prologue (FILE *file
,
20418 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
20420 rs6000_stack_t
*info
= rs6000_stack_info ();
20422 if (TARGET_DEBUG_STACK
)
20423 debug_stack_info (info
);
20425 /* Write .extern for any function we will call to save and restore
20427 if (info
->first_fp_reg_save
< 64
20432 int regno
= info
->first_fp_reg_save
- 32;
20434 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
20436 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
20437 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20438 name
= rs6000_savres_routine_name (info
, regno
, sel
);
20439 fprintf (file
, "\t.extern %s\n", name
);
20441 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
20443 bool lr
= (info
->savres_strategy
20444 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
20445 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20446 name
= rs6000_savres_routine_name (info
, regno
, sel
);
20447 fprintf (file
, "\t.extern %s\n", name
);
20451 rs6000_pic_labelno
++;
20454 /* Non-zero if vmx regs are restored before the frame pop, zero if
20455 we restore after the pop when possible. */
20456 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20458 /* Restoring cr is a two step process: loading a reg from the frame
20459 save, then moving the reg to cr. For ABI_V4 we must let the
20460 unwinder know that the stack location is no longer valid at or
20461 before the stack deallocation, but we can't emit a cfa_restore for
20462 cr at the stack deallocation like we do for other registers.
20463 The trouble is that it is possible for the move to cr to be
20464 scheduled after the stack deallocation. So say exactly where cr
20465 is located on each of the two insns. */
20468 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
20470 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
20471 rtx reg
= gen_rtx_REG (SImode
, regno
);
20472 rtx insn
= emit_move_insn (reg
, mem
);
20474 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
20476 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
20477 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
20479 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
20480 RTX_FRAME_RELATED_P (insn
) = 1;
20485 /* Reload CR from REG. */
20488 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
20493 if (using_mfcr_multiple
)
20495 for (i
= 0; i
< 8; i
++)
20496 if (save_reg_p (CR0_REGNO
+ i
))
20498 gcc_assert (count
);
20501 if (using_mfcr_multiple
&& count
> 1)
20506 p
= rtvec_alloc (count
);
20509 for (i
= 0; i
< 8; i
++)
20510 if (save_reg_p (CR0_REGNO
+ i
))
20512 rtvec r
= rtvec_alloc (2);
20513 RTVEC_ELT (r
, 0) = reg
;
20514 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
20515 RTVEC_ELT (p
, ndx
) =
20516 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
20517 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
20520 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20521 gcc_assert (ndx
== count
);
20524 for (i
= 0; i
< 8; i
++)
20525 if (save_reg_p (CR0_REGNO
+ i
))
20526 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
20529 if (!exit_func
&& (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
20531 rtx insn
= get_last_insn ();
20532 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
20534 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
20535 RTX_FRAME_RELATED_P (insn
) = 1;
20539 /* Like cr, the move to lr instruction can be scheduled after the
20540 stack deallocation, but unlike cr, its stack frame save is still
20541 valid. So we only need to emit the cfa_restore on the correct
20545 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
20547 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
20548 rtx reg
= gen_rtx_REG (Pmode
, regno
);
20550 emit_move_insn (reg
, mem
);
20554 restore_saved_lr (int regno
, bool exit_func
)
20556 rtx reg
= gen_rtx_REG (Pmode
, regno
);
20557 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
20558 rtx insn
= emit_move_insn (lr
, reg
);
20560 if (!exit_func
&& flag_shrink_wrap
)
20562 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
20563 RTX_FRAME_RELATED_P (insn
) = 1;
20568 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
20570 if (info
->cr_save_p
)
20571 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20572 gen_rtx_REG (SImode
, CR2_REGNO
),
20574 if (info
->lr_save_p
)
20575 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20576 gen_rtx_REG (Pmode
, LR_REGNO
),
20578 return cfa_restores
;
20581 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20582 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20583 below stack pointer not cloberred by signals. */
20586 offset_below_red_zone_p (HOST_WIDE_INT offset
)
20588 return offset
< (DEFAULT_ABI
== ABI_V4
20590 : TARGET_32BIT
? -220 : -288);
20593 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20596 emit_cfa_restores (rtx cfa_restores
)
20598 rtx insn
= get_last_insn ();
20599 rtx
*loc
= ®_NOTES (insn
);
20602 loc
= &XEXP (*loc
, 1);
20603 *loc
= cfa_restores
;
20604 RTX_FRAME_RELATED_P (insn
) = 1;
20607 /* Emit function epilogue as insns. */
20610 rs6000_emit_epilogue (int sibcall
)
20612 rs6000_stack_t
*info
;
20613 int restoring_GPRs_inline
;
20614 int restoring_FPRs_inline
;
20615 int using_load_multiple
;
20616 int using_mtcr_multiple
;
20617 int use_backchain_to_restore_sp
;
20620 HOST_WIDE_INT frame_off
= 0;
20621 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
20622 rtx frame_reg_rtx
= sp_reg_rtx
;
20623 rtx cfa_restores
= NULL_RTX
;
20625 rtx cr_save_reg
= NULL_RTX
;
20626 enum machine_mode reg_mode
= Pmode
;
20627 int reg_size
= TARGET_32BIT
? 4 : 8;
20630 unsigned ptr_regno
;
20632 info
= rs6000_stack_info ();
20634 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
20636 reg_mode
= V2SImode
;
20640 strategy
= info
->savres_strategy
;
20641 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
20642 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
20643 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
20644 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
20645 || rs6000_cpu
== PROCESSOR_PPC603
20646 || rs6000_cpu
== PROCESSOR_PPC750
20648 /* Restore via the backchain when we have a large frame, since this
20649 is more efficient than an addis, addi pair. The second condition
20650 here will not trigger at the moment; We don't actually need a
20651 frame pointer for alloca, but the generic parts of the compiler
20652 give us one anyway. */
20653 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
20654 || (cfun
->calls_alloca
20655 && !frame_pointer_needed
));
20656 restore_lr
= (info
->lr_save_p
20657 && (restoring_FPRs_inline
20658 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
20659 && (restoring_GPRs_inline
20660 || info
->first_fp_reg_save
< 64));
20662 if (WORLD_SAVE_P (info
))
20666 const char *alloc_rname
;
20669 /* eh_rest_world_r10 will return to the location saved in the LR
20670 stack slot (which is not likely to be our caller.)
20671 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20672 rest_world is similar, except any R10 parameter is ignored.
20673 The exception-handling stuff that was here in 2.95 is no
20674 longer necessary. */
20678 + 32 - info
->first_gp_reg_save
20679 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
20680 + 63 + 1 - info
->first_fp_reg_save
);
20682 strcpy (rname
, ((crtl
->calls_eh_return
) ?
20683 "*eh_rest_world_r10" : "*rest_world"));
20684 alloc_rname
= ggc_strdup (rname
);
20687 RTVEC_ELT (p
, j
++) = ret_rtx
;
20688 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
20689 gen_rtx_REG (Pmode
,
20692 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
20693 /* The instruction pattern requires a clobber here;
20694 it is shared with the restVEC helper. */
20696 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
20699 /* CR register traditionally saved as CR2. */
20700 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
20702 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
20703 if (flag_shrink_wrap
)
20705 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20706 gen_rtx_REG (Pmode
, LR_REGNO
),
20708 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20712 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20714 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
20716 = gen_frame_load (reg
,
20717 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
20718 if (flag_shrink_wrap
)
20719 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20721 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
20723 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
20725 = gen_frame_load (reg
,
20726 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
20727 if (flag_shrink_wrap
)
20728 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20730 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
20732 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
20733 ? DFmode
: SFmode
),
20734 info
->first_fp_reg_save
+ i
);
20736 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
20737 if (flag_shrink_wrap
)
20738 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20741 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
20743 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
20745 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
20747 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
20749 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
20750 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20752 if (flag_shrink_wrap
)
20754 REG_NOTES (insn
) = cfa_restores
;
20755 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20756 RTX_FRAME_RELATED_P (insn
) = 1;
20761 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
20763 frame_off
= info
->total_size
;
20765 /* Restore AltiVec registers if we must do so before adjusting the
20767 if (TARGET_ALTIVEC_ABI
20768 && info
->altivec_size
!= 0
20769 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20770 || (DEFAULT_ABI
!= ABI_V4
20771 && offset_below_red_zone_p (info
->altivec_save_offset
))))
20774 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
20776 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
20777 if (use_backchain_to_restore_sp
)
20779 int frame_regno
= 11;
20781 if ((strategy
& REST_INLINE_VRS
) == 0)
20783 /* Of r11 and r12, select the one not clobbered by an
20784 out-of-line restore function for the frame register. */
20785 frame_regno
= 11 + 12 - scratch_regno
;
20787 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
20788 emit_move_insn (frame_reg_rtx
,
20789 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20792 else if (frame_pointer_needed
)
20793 frame_reg_rtx
= hard_frame_pointer_rtx
;
20795 if ((strategy
& REST_INLINE_VRS
) == 0)
20797 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
20799 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
20800 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
20802 if (end_save
+ frame_off
!= 0)
20804 rtx offset
= GEN_INT (end_save
+ frame_off
);
20806 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
20809 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20811 ptr_off
= -end_save
;
20812 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
20813 info
->altivec_save_offset
+ ptr_off
,
20814 0, V4SImode
, SAVRES_VR
);
20818 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20819 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20821 rtx addr
, areg
, mem
, reg
;
20823 areg
= gen_rtx_REG (Pmode
, 0);
20825 (areg
, GEN_INT (info
->altivec_save_offset
20827 + 16 * (i
- info
->first_altivec_reg_save
)));
20829 /* AltiVec addressing mode is [reg+reg]. */
20830 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
20831 mem
= gen_frame_mem (V4SImode
, addr
);
20833 reg
= gen_rtx_REG (V4SImode
, i
);
20834 emit_move_insn (reg
, mem
);
20838 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20839 if (((strategy
& REST_INLINE_VRS
) == 0
20840 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
20841 && (flag_shrink_wrap
20842 || (offset_below_red_zone_p
20843 (info
->altivec_save_offset
20844 + 16 * (i
- info
->first_altivec_reg_save
)))))
20846 rtx reg
= gen_rtx_REG (V4SImode
, i
);
20847 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20851 /* Restore VRSAVE if we must do so before adjusting the stack. */
20853 && TARGET_ALTIVEC_VRSAVE
20854 && info
->vrsave_mask
!= 0
20855 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20856 || (DEFAULT_ABI
!= ABI_V4
20857 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
20861 if (frame_reg_rtx
== sp_reg_rtx
)
20863 if (use_backchain_to_restore_sp
)
20865 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20866 emit_move_insn (frame_reg_rtx
,
20867 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20870 else if (frame_pointer_needed
)
20871 frame_reg_rtx
= hard_frame_pointer_rtx
;
20874 reg
= gen_rtx_REG (SImode
, 12);
20875 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
20876 info
->vrsave_save_offset
+ frame_off
));
20878 emit_insn (generate_set_vrsave (reg
, info
, 1));
20882 /* If we have a large stack frame, restore the old stack pointer
20883 using the backchain. */
20884 if (use_backchain_to_restore_sp
)
20886 if (frame_reg_rtx
== sp_reg_rtx
)
20888 /* Under V.4, don't reset the stack pointer until after we're done
20889 loading the saved registers. */
20890 if (DEFAULT_ABI
== ABI_V4
)
20891 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20893 insn
= emit_move_insn (frame_reg_rtx
,
20894 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20897 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20898 && DEFAULT_ABI
== ABI_V4
)
20899 /* frame_reg_rtx has been set up by the altivec restore. */
20903 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
20904 frame_reg_rtx
= sp_reg_rtx
;
20907 /* If we have a frame pointer, we can restore the old stack pointer
20909 else if (frame_pointer_needed
)
20911 frame_reg_rtx
= sp_reg_rtx
;
20912 if (DEFAULT_ABI
== ABI_V4
)
20913 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20914 /* Prevent reordering memory accesses against stack pointer restore. */
20915 else if (cfun
->calls_alloca
20916 || offset_below_red_zone_p (-info
->total_size
))
20917 rs6000_emit_stack_tie (frame_reg_rtx
, true);
20919 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
20920 GEN_INT (info
->total_size
)));
20923 else if (info
->push_p
20924 && DEFAULT_ABI
!= ABI_V4
20925 && !crtl
->calls_eh_return
)
20927 /* Prevent reordering memory accesses against stack pointer restore. */
20928 if (cfun
->calls_alloca
20929 || offset_below_red_zone_p (-info
->total_size
))
20930 rs6000_emit_stack_tie (frame_reg_rtx
, false);
20931 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
20932 GEN_INT (info
->total_size
)));
20935 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
20939 REG_NOTES (insn
) = cfa_restores
;
20940 cfa_restores
= NULL_RTX
;
20942 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20943 RTX_FRAME_RELATED_P (insn
) = 1;
20946 /* Restore AltiVec registers if we have not done so already. */
20947 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20948 && TARGET_ALTIVEC_ABI
20949 && info
->altivec_size
!= 0
20950 && (DEFAULT_ABI
== ABI_V4
20951 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
20955 if ((strategy
& REST_INLINE_VRS
) == 0)
20957 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
20959 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
20960 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
20961 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
20963 if (end_save
+ frame_off
!= 0)
20965 rtx offset
= GEN_INT (end_save
+ frame_off
);
20967 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
20970 emit_move_insn (ptr_reg
, frame_reg_rtx
);
20972 ptr_off
= -end_save
;
20973 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
20974 info
->altivec_save_offset
+ ptr_off
,
20975 0, V4SImode
, SAVRES_VR
);
20976 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
20978 /* Frame reg was clobbered by out-of-line save. Restore it
20979 from ptr_reg, and if we are calling out-of-line gpr or
20980 fpr restore set up the correct pointer and offset. */
20981 unsigned newptr_regno
= 1;
20982 if (!restoring_GPRs_inline
)
20984 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
20985 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
20986 newptr_regno
= ptr_regno_for_savres (sel
);
20987 end_save
= info
->gp_save_offset
+ info
->gp_size
;
20989 else if (!restoring_FPRs_inline
)
20991 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
20992 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20993 newptr_regno
= ptr_regno_for_savres (sel
);
20994 end_save
= info
->gp_save_offset
+ info
->gp_size
;
20997 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
20998 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
21000 if (end_save
+ ptr_off
!= 0)
21002 rtx offset
= GEN_INT (end_save
+ ptr_off
);
21004 frame_off
= -end_save
;
21005 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
21009 frame_off
= ptr_off
;
21010 emit_move_insn (frame_reg_rtx
, ptr_reg
);
21016 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21017 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21019 rtx addr
, areg
, mem
, reg
;
21021 areg
= gen_rtx_REG (Pmode
, 0);
21023 (areg
, GEN_INT (info
->altivec_save_offset
21025 + 16 * (i
- info
->first_altivec_reg_save
)));
21027 /* AltiVec addressing mode is [reg+reg]. */
21028 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
21029 mem
= gen_frame_mem (V4SImode
, addr
);
21031 reg
= gen_rtx_REG (V4SImode
, i
);
21032 emit_move_insn (reg
, mem
);
21036 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21037 if (((strategy
& REST_INLINE_VRS
) == 0
21038 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
21039 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
21041 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21042 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21046 /* Restore VRSAVE if we have not done so already. */
21047 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21049 && TARGET_ALTIVEC_VRSAVE
21050 && info
->vrsave_mask
!= 0
21051 && (DEFAULT_ABI
== ABI_V4
21052 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
21056 reg
= gen_rtx_REG (SImode
, 12);
21057 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21058 info
->vrsave_save_offset
+ frame_off
));
21060 emit_insn (generate_set_vrsave (reg
, info
, 1));
21063 /* If we exit by an out-of-line restore function on ABI_V4 then that
21064 function will deallocate the stack, so we don't need to worry
21065 about the unwinder restoring cr from an invalid stack frame
21067 exit_func
= (!restoring_FPRs_inline
21068 || (!restoring_GPRs_inline
21069 && info
->first_fp_reg_save
== 64));
21071 /* Get the old lr if we saved it. If we are restoring registers
21072 out-of-line, then the out-of-line routines can do this for us. */
21073 if (restore_lr
&& restoring_GPRs_inline
)
21074 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
21076 /* Get the old cr if we saved it. */
21077 if (info
->cr_save_p
)
21079 unsigned cr_save_regno
= 12;
21081 if (!restoring_GPRs_inline
)
21083 /* Ensure we don't use the register used by the out-of-line
21084 gpr register restore below. */
21085 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
21086 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
21087 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
21089 if (gpr_ptr_regno
== 12)
21090 cr_save_regno
= 11;
21091 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
21093 else if (REGNO (frame_reg_rtx
) == 12)
21094 cr_save_regno
= 11;
21096 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
21097 info
->cr_save_offset
+ frame_off
,
21101 /* Set LR here to try to overlap restores below. */
21102 if (restore_lr
&& restoring_GPRs_inline
)
21103 restore_saved_lr (0, exit_func
);
21105 /* Load exception handler data registers, if needed. */
21106 if (crtl
->calls_eh_return
)
21108 unsigned int i
, regno
;
21112 rtx reg
= gen_rtx_REG (reg_mode
, 2);
21113 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21114 frame_off
+ 5 * reg_size
));
21121 regno
= EH_RETURN_DATA_REGNO (i
);
21122 if (regno
== INVALID_REGNUM
)
21125 /* Note: possible use of r0 here to address SPE regs. */
21126 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
21127 info
->ehrd_offset
+ frame_off
21128 + reg_size
* (int) i
);
21130 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
21134 /* Restore GPRs. This is done as a PARALLEL if we are using
21135 the load-multiple instructions. */
21137 && info
->spe_64bit_regs_used
21138 && info
->first_gp_reg_save
!= 32)
21140 /* Determine whether we can address all of the registers that need
21141 to be saved with an offset from frame_reg_rtx that fits in
21142 the small const field for SPE memory instructions. */
21143 int spe_regs_addressable
21144 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
21145 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
21146 && restoring_GPRs_inline
);
21148 if (!spe_regs_addressable
)
21150 int ool_adjust
= 0;
21151 rtx old_frame_reg_rtx
= frame_reg_rtx
;
21152 /* Make r11 point to the start of the SPE save area. We worried about
21153 not clobbering it when we were saving registers in the prologue.
21154 There's no need to worry here because the static chain is passed
21155 anew to every function. */
21157 if (!restoring_GPRs_inline
)
21158 ool_adjust
= 8 * (info
->first_gp_reg_save
21159 - (FIRST_SAVRES_REGISTER
+ 1));
21160 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
21161 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
21162 GEN_INT (info
->spe_gp_save_offset
21165 /* Keep the invariant that frame_reg_rtx + frame_off points
21166 at the top of the stack frame. */
21167 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
21170 if (restoring_GPRs_inline
)
21172 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
21174 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21175 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21177 rtx offset
, addr
, mem
, reg
;
21179 /* We're doing all this to ensure that the immediate offset
21180 fits into the immediate field of 'evldd'. */
21181 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
21183 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
21184 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
21185 mem
= gen_rtx_MEM (V2SImode
, addr
);
21186 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
21188 emit_move_insn (reg
, mem
);
21192 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
21193 info
->spe_gp_save_offset
+ frame_off
,
21194 info
->lr_save_offset
+ frame_off
,
21196 SAVRES_GPR
| SAVRES_LR
);
21198 else if (!restoring_GPRs_inline
)
21200 /* We are jumping to an out-of-line function. */
21202 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
21203 bool can_use_exit
= end_save
== 0;
21204 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
21207 /* Emit stack reset code if we need it. */
21208 ptr_regno
= ptr_regno_for_savres (sel
);
21209 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21211 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
21212 else if (end_save
+ frame_off
!= 0)
21213 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
21214 GEN_INT (end_save
+ frame_off
)));
21215 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
21216 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21217 if (REGNO (frame_reg_rtx
) == ptr_regno
)
21218 frame_off
= -end_save
;
21220 if (can_use_exit
&& info
->cr_save_p
)
21221 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
21223 ptr_off
= -end_save
;
21224 rs6000_emit_savres_rtx (info
, ptr_reg
,
21225 info
->gp_save_offset
+ ptr_off
,
21226 info
->lr_save_offset
+ ptr_off
,
21229 else if (using_load_multiple
)
21232 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
21233 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21235 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21237 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21238 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21242 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21243 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21244 emit_insn (gen_frame_load
21245 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21247 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
21250 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
21252 /* If the frame pointer was used then we can't delay emitting
21253 a REG_CFA_DEF_CFA note. This must happen on the insn that
21254 restores the frame pointer, r31. We may have already emitted
21255 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
21256 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
21257 be harmless if emitted. */
21258 if (frame_pointer_needed
)
21260 insn
= get_last_insn ();
21261 add_reg_note (insn
, REG_CFA_DEF_CFA
,
21262 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
21263 RTX_FRAME_RELATED_P (insn
) = 1;
21266 /* Set up cfa_restores. We always need these when
21267 shrink-wrapping. If not shrink-wrapping then we only need
21268 the cfa_restore when the stack location is no longer valid.
21269 The cfa_restores must be emitted on or before the insn that
21270 invalidates the stack, and of course must not be emitted
21271 before the insn that actually does the restore. The latter
21272 is why it is a bad idea to emit the cfa_restores as a group
21273 on the last instruction here that actually does a restore:
21274 That insn may be reordered with respect to others doing
21276 if (flag_shrink_wrap
21277 && !restoring_GPRs_inline
21278 && info
->first_fp_reg_save
== 64)
21279 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
21281 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
21282 if (!restoring_GPRs_inline
21283 || using_load_multiple
21284 || rs6000_reg_live_or_pic_offset_p (i
))
21286 rtx reg
= gen_rtx_REG (reg_mode
, i
);
21288 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21292 if (!restoring_GPRs_inline
21293 && info
->first_fp_reg_save
== 64)
21295 /* We are jumping to an out-of-line function. */
21297 emit_cfa_restores (cfa_restores
);
21301 if (restore_lr
&& !restoring_GPRs_inline
)
21303 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
21304 restore_saved_lr (0, exit_func
);
21307 /* Restore fpr's if we need to do it without calling a function. */
21308 if (restoring_FPRs_inline
)
21309 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21310 if (save_reg_p (info
->first_fp_reg_save
+ i
))
21312 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21313 ? DFmode
: SFmode
),
21314 info
->first_fp_reg_save
+ i
);
21315 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21316 info
->fp_save_offset
+ frame_off
+ 8 * i
));
21317 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
21318 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21321 /* If we saved cr, restore it here. Just those that were used. */
21322 if (info
->cr_save_p
)
21323 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
21325 /* If this is V.4, unwind the stack pointer after all of the loads
21326 have been done, or set up r11 if we are restoring fp out of line. */
21328 if (!restoring_FPRs_inline
)
21330 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
21331 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21332 ptr_regno
= ptr_regno_for_savres (sel
);
21335 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
21336 if (REGNO (frame_reg_rtx
) == ptr_regno
)
21339 if (insn
&& restoring_FPRs_inline
)
21343 REG_NOTES (insn
) = cfa_restores
;
21344 cfa_restores
= NULL_RTX
;
21346 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
21347 RTX_FRAME_RELATED_P (insn
) = 1;
21350 if (crtl
->calls_eh_return
)
21352 rtx sa
= EH_RETURN_STACKADJ_RTX
;
21353 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
21359 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
21360 if (! restoring_FPRs_inline
)
21362 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
21363 RTVEC_ELT (p
, 0) = ret_rtx
;
21369 /* We can't hang the cfa_restores off a simple return,
21370 since the shrink-wrap code sometimes uses an existing
21371 return. This means there might be a path from
21372 pre-prologue code to this return, and dwarf2cfi code
21373 wants the eh_frame unwinder state to be the same on
21374 all paths to any point. So we need to emit the
21375 cfa_restores before the return. For -m64 we really
21376 don't need epilogue cfa_restores at all, except for
21377 this irritating dwarf2cfi with shrink-wrap
21378 requirement; The stack red-zone means eh_frame info
21379 from the prologue telling the unwinder to restore
21380 from the stack is perfectly good right to the end of
21382 emit_insn (gen_blockage ());
21383 emit_cfa_restores (cfa_restores
);
21384 cfa_restores
= NULL_RTX
;
21386 p
= rtvec_alloc (2);
21387 RTVEC_ELT (p
, 0) = simple_return_rtx
;
21390 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
21391 ? gen_rtx_USE (VOIDmode
,
21392 gen_rtx_REG (Pmode
, LR_REGNO
))
21393 : gen_rtx_CLOBBER (VOIDmode
,
21394 gen_rtx_REG (Pmode
, LR_REGNO
)));
21396 /* If we have to restore more than two FP registers, branch to the
21397 restore function. It will return to our caller. */
21398 if (! restoring_FPRs_inline
)
21403 if (flag_shrink_wrap
)
21404 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
21406 sym
= rs6000_savres_routine_sym (info
,
21407 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
21408 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
21409 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
21410 gen_rtx_REG (Pmode
,
21411 DEFAULT_ABI
== ABI_AIX
21413 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21415 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
21417 RTVEC_ELT (p
, i
+ 4)
21418 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
21419 if (flag_shrink_wrap
)
21420 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
21425 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21431 /* Ensure the cfa_restores are hung off an insn that won't
21432 be reordered above other restores. */
21433 emit_insn (gen_blockage ());
21435 emit_cfa_restores (cfa_restores
);
21439 /* Write function epilogue. */
21442 rs6000_output_function_epilogue (FILE *file
,
21443 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
21446 macho_branch_islands ();
21447 /* Mach-O doesn't support labels at the end of objects, so if
21448 it looks like we might want one, insert a NOP. */
21450 rtx insn
= get_last_insn ();
21451 rtx deleted_debug_label
= NULL_RTX
;
21454 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
21456 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
21457 notes only, instead set their CODE_LABEL_NUMBER to -1,
21458 otherwise there would be code generation differences
21459 in between -g and -g0. */
21460 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
21461 deleted_debug_label
= insn
;
21462 insn
= PREV_INSN (insn
);
21467 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
21468 fputs ("\tnop\n", file
);
21469 else if (deleted_debug_label
)
21470 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
21471 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
21472 CODE_LABEL_NUMBER (insn
) = -1;
21476 /* Output a traceback table here. See /usr/include/sys/debug.h for info
21479 We don't output a traceback table if -finhibit-size-directive was
21480 used. The documentation for -finhibit-size-directive reads
21481 ``don't output a @code{.size} assembler directive, or anything
21482 else that would cause trouble if the function is split in the
21483 middle, and the two halves are placed at locations far apart in
21484 memory.'' The traceback table has this property, since it
21485 includes the offset from the start of the function to the
21486 traceback table itself.
21488 System V.4 Powerpc's (and the embedded ABI derived from it) use a
21489 different traceback table. */
21490 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
21491 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
21493 const char *fname
= NULL
;
21494 const char *language_string
= lang_hooks
.name
;
21495 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
21497 int optional_tbtab
;
21498 rs6000_stack_t
*info
= rs6000_stack_info ();
21500 if (rs6000_traceback
== traceback_full
)
21501 optional_tbtab
= 1;
21502 else if (rs6000_traceback
== traceback_part
)
21503 optional_tbtab
= 0;
21505 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
21507 if (optional_tbtab
)
21509 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
21510 while (*fname
== '.') /* V.4 encodes . in the name */
21513 /* Need label immediately before tbtab, so we can compute
21514 its offset from the function start. */
21515 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
21516 ASM_OUTPUT_LABEL (file
, fname
);
21519 /* The .tbtab pseudo-op can only be used for the first eight
21520 expressions, since it can't handle the possibly variable
21521 length fields that follow. However, if you omit the optional
21522 fields, the assembler outputs zeros for all optional fields
21523 anyways, giving each variable length field is minimum length
21524 (as defined in sys/debug.h). Thus we can not use the .tbtab
21525 pseudo-op at all. */
21527 /* An all-zero word flags the start of the tbtab, for debuggers
21528 that have to find it by searching forward from the entry
21529 point or from the current pc. */
21530 fputs ("\t.long 0\n", file
);
21532 /* Tbtab format type. Use format type 0. */
21533 fputs ("\t.byte 0,", file
);
21535 /* Language type. Unfortunately, there does not seem to be any
21536 official way to discover the language being compiled, so we
21537 use language_string.
21538 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21539 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21540 a number, so for now use 9. LTO and Go aren't assigned numbers
21541 either, so for now use 0. */
21542 if (! strcmp (language_string
, "GNU C")
21543 || ! strcmp (language_string
, "GNU GIMPLE")
21544 || ! strcmp (language_string
, "GNU Go"))
21546 else if (! strcmp (language_string
, "GNU F77")
21547 || ! strcmp (language_string
, "GNU Fortran"))
21549 else if (! strcmp (language_string
, "GNU Pascal"))
21551 else if (! strcmp (language_string
, "GNU Ada"))
21553 else if (! strcmp (language_string
, "GNU C++")
21554 || ! strcmp (language_string
, "GNU Objective-C++"))
21556 else if (! strcmp (language_string
, "GNU Java"))
21558 else if (! strcmp (language_string
, "GNU Objective-C"))
21561 gcc_unreachable ();
21562 fprintf (file
, "%d,", i
);
21564 /* 8 single bit fields: global linkage (not set for C extern linkage,
21565 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21566 from start of procedure stored in tbtab, internal function, function
21567 has controlled storage, function has no toc, function uses fp,
21568 function logs/aborts fp operations. */
21569 /* Assume that fp operations are used if any fp reg must be saved. */
21570 fprintf (file
, "%d,",
21571 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
21573 /* 6 bitfields: function is interrupt handler, name present in
21574 proc table, function calls alloca, on condition directives
21575 (controls stack walks, 3 bits), saves condition reg, saves
21577 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21578 set up as a frame pointer, even when there is no alloca call. */
21579 fprintf (file
, "%d,",
21580 ((optional_tbtab
<< 6)
21581 | ((optional_tbtab
& frame_pointer_needed
) << 5)
21582 | (info
->cr_save_p
<< 1)
21583 | (info
->lr_save_p
)));
21585 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21587 fprintf (file
, "%d,",
21588 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
21590 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21591 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
21593 if (optional_tbtab
)
21595 /* Compute the parameter info from the function decl argument
21598 int next_parm_info_bit
= 31;
21600 for (decl
= DECL_ARGUMENTS (current_function_decl
);
21601 decl
; decl
= DECL_CHAIN (decl
))
21603 rtx parameter
= DECL_INCOMING_RTL (decl
);
21604 enum machine_mode mode
= GET_MODE (parameter
);
21606 if (GET_CODE (parameter
) == REG
)
21608 if (SCALAR_FLOAT_MODE_P (mode
))
21629 gcc_unreachable ();
21632 /* If only one bit will fit, don't or in this entry. */
21633 if (next_parm_info_bit
> 0)
21634 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
21635 next_parm_info_bit
-= 2;
21639 fixed_parms
+= ((GET_MODE_SIZE (mode
)
21640 + (UNITS_PER_WORD
- 1))
21642 next_parm_info_bit
-= 1;
21648 /* Number of fixed point parameters. */
21649 /* This is actually the number of words of fixed point parameters; thus
21650 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21651 fprintf (file
, "%d,", fixed_parms
);
21653 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21655 /* This is actually the number of fp registers that hold parameters;
21656 and thus the maximum value is 13. */
21657 /* Set parameters on stack bit if parameters are not in their original
21658 registers, regardless of whether they are on the stack? Xlc
21659 seems to set the bit when not optimizing. */
21660 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
21662 if (! optional_tbtab
)
21665 /* Optional fields follow. Some are variable length. */
21667 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21668 11 double float. */
21669 /* There is an entry for each parameter in a register, in the order that
21670 they occur in the parameter list. Any intervening arguments on the
21671 stack are ignored. If the list overflows a long (max possible length
21672 34 bits) then completely leave off all elements that don't fit. */
21673 /* Only emit this long if there was at least one parameter. */
21674 if (fixed_parms
|| float_parms
)
21675 fprintf (file
, "\t.long %d\n", parm_info
);
21677 /* Offset from start of code to tb table. */
21678 fputs ("\t.long ", file
);
21679 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
21680 RS6000_OUTPUT_BASENAME (file
, fname
);
21682 rs6000_output_function_entry (file
, fname
);
21685 /* Interrupt handler mask. */
21686 /* Omit this long, since we never set the interrupt handler bit
21689 /* Number of CTL (controlled storage) anchors. */
21690 /* Omit this long, since the has_ctl bit is never set above. */
21692 /* Displacement into stack of each CTL anchor. */
21693 /* Omit this list of longs, because there are no CTL anchors. */
21695 /* Length of function name. */
21698 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
21700 /* Function name. */
21701 assemble_string (fname
, strlen (fname
));
21703 /* Register for alloca automatic storage; this is always reg 31.
21704 Only emit this if the alloca bit was set above. */
21705 if (frame_pointer_needed
)
21706 fputs ("\t.byte 31\n", file
);
21708 fputs ("\t.align 2\n", file
);
21712 /* A C compound statement that outputs the assembler code for a thunk
21713 function, used to implement C++ virtual function calls with
21714 multiple inheritance. The thunk acts as a wrapper around a virtual
21715 function, adjusting the implicit object parameter before handing
21716 control off to the real function.
21718 First, emit code to add the integer DELTA to the location that
21719 contains the incoming first argument. Assume that this argument
21720 contains a pointer, and is the one used to pass the `this' pointer
21721 in C++. This is the incoming argument *before* the function
21722 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21723 values of all other incoming arguments.
21725 After the addition, emit code to jump to FUNCTION, which is a
21726 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21727 not touch the return address. Hence returning from FUNCTION will
21728 return to whoever called the current `thunk'.
21730 The effect must be as if FUNCTION had been called directly with the
21731 adjusted first argument. This macro is responsible for emitting
21732 all of the code for a thunk function; output_function_prologue()
21733 and output_function_epilogue() are not invoked.
21735 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21736 been extracted from it.) It might possibly be useful on some
21737 targets, but probably not.
21739 If you do not define this macro, the target-independent code in the
21740 C++ frontend will generate a less efficient heavyweight thunk that
21741 calls FUNCTION instead of jumping to it. The generic approach does
21742 not support varargs. */
21745 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
21746 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
21749 rtx this_rtx
, insn
, funexp
;
21751 reload_completed
= 1;
21752 epilogue_completed
= 1;
21754 /* Mark the end of the (empty) prologue. */
21755 emit_note (NOTE_INSN_PROLOGUE_END
);
21757 /* Find the "this" pointer. If the function returns a structure,
21758 the structure return pointer is in r3. */
21759 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
21760 this_rtx
= gen_rtx_REG (Pmode
, 4);
21762 this_rtx
= gen_rtx_REG (Pmode
, 3);
21764 /* Apply the constant offset, if required. */
21766 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
21768 /* Apply the offset from the vtable, if required. */
21771 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
21772 rtx tmp
= gen_rtx_REG (Pmode
, 12);
21774 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
21775 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
21777 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
21778 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
21782 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
21784 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
21786 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
21789 /* Generate a tail call to the target function. */
21790 if (!TREE_USED (function
))
21792 assemble_external (function
);
21793 TREE_USED (function
) = 1;
21795 funexp
= XEXP (DECL_RTL (function
), 0);
21796 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
21799 if (MACHOPIC_INDIRECT
)
21800 funexp
= machopic_indirect_call_target (funexp
);
21803 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21804 generate sibcall RTL explicitly. */
21805 insn
= emit_call_insn (
21806 gen_rtx_PARALLEL (VOIDmode
,
21808 gen_rtx_CALL (VOIDmode
,
21809 funexp
, const0_rtx
),
21810 gen_rtx_USE (VOIDmode
, const0_rtx
),
21811 gen_rtx_USE (VOIDmode
,
21812 gen_rtx_REG (SImode
,
21814 simple_return_rtx
)));
21815 SIBLING_CALL_P (insn
) = 1;
21818 /* Run just enough of rest_of_compilation to get the insns emitted.
21819 There's not really enough bulk here to make other passes such as
21820 instruction scheduling worth while. Note that use_thunk calls
21821 assemble_start_function and assemble_end_function. */
21822 insn
= get_insns ();
21823 shorten_branches (insn
);
21824 final_start_function (insn
, file
, 1);
21825 final (insn
, file
, 1);
21826 final_end_function ();
21828 reload_completed
= 0;
21829 epilogue_completed
= 0;
21832 /* A quick summary of the various types of 'constant-pool tables'
21835 Target Flags Name One table per
21836 AIX (none) AIX TOC object file
21837 AIX -mfull-toc AIX TOC object file
21838 AIX -mminimal-toc AIX minimal TOC translation unit
21839 SVR4/EABI (none) SVR4 SDATA object file
21840 SVR4/EABI -fpic SVR4 pic object file
21841 SVR4/EABI -fPIC SVR4 PIC translation unit
21842 SVR4/EABI -mrelocatable EABI TOC function
21843 SVR4/EABI -maix AIX TOC object file
21844 SVR4/EABI -maix -mminimal-toc
21845 AIX minimal TOC translation unit
21847 Name Reg. Set by entries contains:
21848 made by addrs? fp? sum?
21850 AIX TOC 2 crt0 as Y option option
21851 AIX minimal TOC 30 prolog gcc Y Y option
21852 SVR4 SDATA 13 crt0 gcc N Y N
21853 SVR4 pic 30 prolog ld Y not yet N
21854 SVR4 PIC 30 prolog gcc Y option option
21855 EABI TOC 30 prolog gcc Y option option
21859 /* Hash functions for the hash table. */
21862 rs6000_hash_constant (rtx k
)
21864 enum rtx_code code
= GET_CODE (k
);
21865 enum machine_mode mode
= GET_MODE (k
);
21866 unsigned result
= (code
<< 3) ^ mode
;
21867 const char *format
;
21870 format
= GET_RTX_FORMAT (code
);
21871 flen
= strlen (format
);
21877 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
21880 if (mode
!= VOIDmode
)
21881 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
21893 for (; fidx
< flen
; fidx
++)
21894 switch (format
[fidx
])
21899 const char *str
= XSTR (k
, fidx
);
21900 len
= strlen (str
);
21901 result
= result
* 613 + len
;
21902 for (i
= 0; i
< len
; i
++)
21903 result
= result
* 613 + (unsigned) str
[i
];
21908 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
21912 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
21915 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
21916 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
21920 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
21921 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
21928 gcc_unreachable ();
21935 toc_hash_function (const void *hash_entry
)
21937 const struct toc_hash_struct
*thc
=
21938 (const struct toc_hash_struct
*) hash_entry
;
21939 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
21942 /* Compare H1 and H2 for equivalence. */
21945 toc_hash_eq (const void *h1
, const void *h2
)
21947 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
21948 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
21950 if (((const struct toc_hash_struct
*) h1
)->key_mode
21951 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
21954 return rtx_equal_p (r1
, r2
);
21957 /* These are the names given by the C++ front-end to vtables, and
21958 vtable-like objects. Ideally, this logic should not be here;
21959 instead, there should be some programmatic way of inquiring as
21960 to whether or not an object is a vtable. */
21962 #define VTABLE_NAME_P(NAME) \
21963 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21964 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21965 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21966 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21967 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21969 #ifdef NO_DOLLAR_IN_LABEL
21970 /* Return a GGC-allocated character string translating dollar signs in
21971 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21974 rs6000_xcoff_strip_dollar (const char *name
)
21980 q
= (const char *) strchr (name
, '$');
21982 if (q
== 0 || q
== name
)
21985 len
= strlen (name
);
21986 strip
= XALLOCAVEC (char, len
+ 1);
21987 strcpy (strip
, name
);
21988 p
= strip
+ (q
- name
);
21992 p
= strchr (p
+ 1, '$');
21995 return ggc_alloc_string (strip
, len
);
22000 rs6000_output_symbol_ref (FILE *file
, rtx x
)
22002 /* Currently C++ toc references to vtables can be emitted before it
22003 is decided whether the vtable is public or private. If this is
22004 the case, then the linker will eventually complain that there is
22005 a reference to an unknown section. Thus, for vtables only,
22006 we emit the TOC reference to reference the symbol and not the
22008 const char *name
= XSTR (x
, 0);
22010 if (VTABLE_NAME_P (name
))
22012 RS6000_OUTPUT_BASENAME (file
, name
);
22015 assemble_name (file
, name
);
22018 /* Output a TOC entry. We derive the entry name from what is being
22022 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
22025 const char *name
= buf
;
22027 HOST_WIDE_INT offset
= 0;
22029 gcc_assert (!TARGET_NO_TOC
);
22031 /* When the linker won't eliminate them, don't output duplicate
22032 TOC entries (this happens on AIX if there is any kind of TOC,
22033 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
22035 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
22037 struct toc_hash_struct
*h
;
22040 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
22041 time because GGC is not initialized at that point. */
22042 if (toc_hash_table
== NULL
)
22043 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
22044 toc_hash_eq
, NULL
);
22046 h
= ggc_alloc_toc_hash_struct ();
22048 h
->key_mode
= mode
;
22049 h
->labelno
= labelno
;
22051 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
22052 if (*found
== NULL
)
22054 else /* This is indeed a duplicate.
22055 Set this label equal to that label. */
22057 fputs ("\t.set ", file
);
22058 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
22059 fprintf (file
, "%d,", labelno
);
22060 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
22061 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
22065 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
22066 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
22067 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
22069 fputs ("\t.set ", file
);
22070 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
22071 fprintf (file
, "%d,", labelno
);
22072 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
22073 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
22081 /* If we're going to put a double constant in the TOC, make sure it's
22082 aligned properly when strict alignment is on. */
22083 if (GET_CODE (x
) == CONST_DOUBLE
22084 && STRICT_ALIGNMENT
22085 && GET_MODE_BITSIZE (mode
) >= 64
22086 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
22087 ASM_OUTPUT_ALIGN (file
, 3);
22090 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
22092 /* Handle FP constants specially. Note that if we have a minimal
22093 TOC, things we put here aren't actually in the TOC, so we can allow
22095 if (GET_CODE (x
) == CONST_DOUBLE
&&
22096 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
22098 REAL_VALUE_TYPE rv
;
22101 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
22102 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
22103 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
22105 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
22109 if (TARGET_MINIMAL_TOC
)
22110 fputs (DOUBLE_INT_ASM_OP
, file
);
22112 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22113 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22114 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22115 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
22116 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22117 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22122 if (TARGET_MINIMAL_TOC
)
22123 fputs ("\t.long ", file
);
22125 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22126 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22127 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22128 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
22129 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
22130 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
22134 else if (GET_CODE (x
) == CONST_DOUBLE
&&
22135 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
22137 REAL_VALUE_TYPE rv
;
22140 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
22142 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
22143 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
22145 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
22149 if (TARGET_MINIMAL_TOC
)
22150 fputs (DOUBLE_INT_ASM_OP
, file
);
22152 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
22153 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22154 fprintf (file
, "0x%lx%08lx\n",
22155 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22160 if (TARGET_MINIMAL_TOC
)
22161 fputs ("\t.long ", file
);
22163 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
22164 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22165 fprintf (file
, "0x%lx,0x%lx\n",
22166 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
22170 else if (GET_CODE (x
) == CONST_DOUBLE
&&
22171 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
22173 REAL_VALUE_TYPE rv
;
22176 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
22177 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
22178 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
22180 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
22184 if (TARGET_MINIMAL_TOC
)
22185 fputs (DOUBLE_INT_ASM_OP
, file
);
22187 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
22188 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
22193 if (TARGET_MINIMAL_TOC
)
22194 fputs ("\t.long ", file
);
22196 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
22197 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
22201 else if (GET_MODE (x
) == VOIDmode
22202 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
22204 unsigned HOST_WIDE_INT low
;
22205 HOST_WIDE_INT high
;
22207 if (GET_CODE (x
) == CONST_DOUBLE
)
22209 low
= CONST_DOUBLE_LOW (x
);
22210 high
= CONST_DOUBLE_HIGH (x
);
22213 #if HOST_BITS_PER_WIDE_INT == 32
22216 high
= (low
& 0x80000000) ? ~0 : 0;
22220 low
= INTVAL (x
) & 0xffffffff;
22221 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
22225 /* TOC entries are always Pmode-sized, but since this
22226 is a bigendian machine then if we're putting smaller
22227 integer constants in the TOC we have to pad them.
22228 (This is still a win over putting the constants in
22229 a separate constant pool, because then we'd have
22230 to have both a TOC entry _and_ the actual constant.)
22232 For a 32-bit target, CONST_INT values are loaded and shifted
22233 entirely within `low' and can be stored in one TOC entry. */
22235 /* It would be easy to make this work, but it doesn't now. */
22236 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
22238 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
22240 #if HOST_BITS_PER_WIDE_INT == 32
22241 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
22242 POINTER_SIZE
, &low
, &high
, 0);
22245 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
22246 high
= (HOST_WIDE_INT
) low
>> 32;
22253 if (TARGET_MINIMAL_TOC
)
22254 fputs (DOUBLE_INT_ASM_OP
, file
);
22256 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
22257 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22258 fprintf (file
, "0x%lx%08lx\n",
22259 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22264 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
22266 if (TARGET_MINIMAL_TOC
)
22267 fputs ("\t.long ", file
);
22269 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
22270 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22271 fprintf (file
, "0x%lx,0x%lx\n",
22272 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
22276 if (TARGET_MINIMAL_TOC
)
22277 fputs ("\t.long ", file
);
22279 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
22280 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
22286 if (GET_CODE (x
) == CONST
)
22288 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
22289 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
22291 base
= XEXP (XEXP (x
, 0), 0);
22292 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
22295 switch (GET_CODE (base
))
22298 name
= XSTR (base
, 0);
22302 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
22303 CODE_LABEL_NUMBER (XEXP (base
, 0)));
22307 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
22311 gcc_unreachable ();
22314 if (TARGET_MINIMAL_TOC
)
22315 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
22318 fputs ("\t.tc ", file
);
22319 RS6000_OUTPUT_BASENAME (file
, name
);
22322 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
22324 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
22326 /* Mark large TOC symbols on AIX with [TE] so they are mapped
22327 after other TOC symbols, reducing overflow of small TOC access
22328 to [TC] symbols. */
22329 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
22330 ? "[TE]," : "[TC],", file
);
22333 /* Currently C++ toc references to vtables can be emitted before it
22334 is decided whether the vtable is public or private. If this is
22335 the case, then the linker will eventually complain that there is
22336 a TOC reference to an unknown section. Thus, for vtables only,
22337 we emit the TOC reference to reference the symbol and not the
22339 if (VTABLE_NAME_P (name
))
22341 RS6000_OUTPUT_BASENAME (file
, name
);
22343 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
22344 else if (offset
> 0)
22345 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
22348 output_addr_const (file
, x
);
22351 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
22352 && SYMBOL_REF_TLS_MODEL (base
) != 0)
22354 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
22355 fputs ("@le", file
);
22356 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
22357 fputs ("@ie", file
);
22358 /* Use global-dynamic for local-dynamic. */
22359 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
22360 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
22363 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
22364 fputs ("\t.tc .", file
);
22365 RS6000_OUTPUT_BASENAME (file
, name
);
22366 fputs ("[TC],", file
);
22367 output_addr_const (file
, x
);
22368 fputs ("@m", file
);
22376 /* Output an assembler pseudo-op to write an ASCII string of N characters
22377 starting at P to FILE.
22379 On the RS/6000, we have to do this using the .byte operation and
22380 write out special characters outside the quoted string.
22381 Also, the assembler is broken; very long strings are truncated,
22382 so we must artificially break them up early. */
22385 output_ascii (FILE *file
, const char *p
, int n
)
22388 int i
, count_string
;
22389 const char *for_string
= "\t.byte \"";
22390 const char *for_decimal
= "\t.byte ";
22391 const char *to_close
= NULL
;
22394 for (i
= 0; i
< n
; i
++)
22397 if (c
>= ' ' && c
< 0177)
22400 fputs (for_string
, file
);
22403 /* Write two quotes to get one. */
22411 for_decimal
= "\"\n\t.byte ";
22415 if (count_string
>= 512)
22417 fputs (to_close
, file
);
22419 for_string
= "\t.byte \"";
22420 for_decimal
= "\t.byte ";
22428 fputs (for_decimal
, file
);
22429 fprintf (file
, "%d", c
);
22431 for_string
= "\n\t.byte \"";
22432 for_decimal
= ", ";
22438 /* Now close the string if we have written one. Then end the line. */
22440 fputs (to_close
, file
);
22443 /* Generate a unique section name for FILENAME for a section type
22444 represented by SECTION_DESC. Output goes into BUF.
22446 SECTION_DESC can be any string, as long as it is different for each
22447 possible section type.
22449 We name the section in the same manner as xlc. The name begins with an
22450 underscore followed by the filename (after stripping any leading directory
22451 names) with the last period replaced by the string SECTION_DESC. If
22452 FILENAME does not contain a period, SECTION_DESC is appended to the end of
22456 rs6000_gen_section_name (char **buf
, const char *filename
,
22457 const char *section_desc
)
22459 const char *q
, *after_last_slash
, *last_period
= 0;
22463 after_last_slash
= filename
;
22464 for (q
= filename
; *q
; q
++)
22467 after_last_slash
= q
+ 1;
22468 else if (*q
== '.')
22472 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
22473 *buf
= (char *) xmalloc (len
);
22478 for (q
= after_last_slash
; *q
; q
++)
22480 if (q
== last_period
)
22482 strcpy (p
, section_desc
);
22483 p
+= strlen (section_desc
);
22487 else if (ISALNUM (*q
))
22491 if (last_period
== 0)
22492 strcpy (p
, section_desc
);
22497 /* Emit profile function. */
22500 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
22502 /* Non-standard profiling for kernels, which just saves LR then calls
22503 _mcount without worrying about arg saves. The idea is to change
22504 the function prologue as little as possible as it isn't easy to
22505 account for arg save/restore code added just for _mcount. */
22506 if (TARGET_PROFILE_KERNEL
)
22509 if (DEFAULT_ABI
== ABI_AIX
)
22511 #ifndef NO_PROFILE_COUNTERS
22512 # define NO_PROFILE_COUNTERS 0
22514 if (NO_PROFILE_COUNTERS
)
22515 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
22516 LCT_NORMAL
, VOIDmode
, 0);
22520 const char *label_name
;
22523 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
22524 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
22525 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
22527 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
22528 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
22531 else if (DEFAULT_ABI
== ABI_DARWIN
)
22533 const char *mcount_name
= RS6000_MCOUNT
;
22534 int caller_addr_regno
= LR_REGNO
;
22536 /* Be conservative and always set this, at least for now. */
22537 crtl
->uses_pic_offset_table
= 1;
22540 /* For PIC code, set up a stub and collect the caller's address
22541 from r0, which is where the prologue puts it. */
22542 if (MACHOPIC_INDIRECT
22543 && crtl
->uses_pic_offset_table
)
22544 caller_addr_regno
= 0;
22546 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
22547 LCT_NORMAL
, VOIDmode
, 1,
22548 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
22552 /* Write function profiler code. */
22555 output_function_profiler (FILE *file
, int labelno
)
22559 switch (DEFAULT_ABI
)
22562 gcc_unreachable ();
22567 warning (0, "no profiling of 64-bit code for this ABI");
22570 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
22571 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
22572 if (NO_PROFILE_COUNTERS
)
22574 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22575 reg_names
[0], reg_names
[1]);
22577 else if (TARGET_SECURE_PLT
&& flag_pic
)
22579 if (TARGET_LINK_STACK
)
22582 get_ppc476_thunk_name (name
);
22583 asm_fprintf (file
, "\tbl %s\n", name
);
22586 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
22587 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22588 reg_names
[0], reg_names
[1]);
22589 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
22590 asm_fprintf (file
, "\taddis %s,%s,",
22591 reg_names
[12], reg_names
[12]);
22592 assemble_name (file
, buf
);
22593 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
22594 assemble_name (file
, buf
);
22595 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
22597 else if (flag_pic
== 1)
22599 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
22600 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22601 reg_names
[0], reg_names
[1]);
22602 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
22603 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
22604 assemble_name (file
, buf
);
22605 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
22607 else if (flag_pic
> 1)
22609 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22610 reg_names
[0], reg_names
[1]);
22611 /* Now, we need to get the address of the label. */
22612 if (TARGET_LINK_STACK
)
22615 get_ppc476_thunk_name (name
);
22616 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
22617 assemble_name (file
, buf
);
22618 fputs ("-.\n1:", file
);
22619 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
22620 asm_fprintf (file
, "\taddi %s,%s,4\n",
22621 reg_names
[11], reg_names
[11]);
22625 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
22626 assemble_name (file
, buf
);
22627 fputs ("-.\n1:", file
);
22628 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
22630 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
22631 reg_names
[0], reg_names
[11]);
22632 asm_fprintf (file
, "\tadd %s,%s,%s\n",
22633 reg_names
[0], reg_names
[0], reg_names
[11]);
22637 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
22638 assemble_name (file
, buf
);
22639 fputs ("@ha\n", file
);
22640 asm_fprintf (file
, "\tstw %s,4(%s)\n",
22641 reg_names
[0], reg_names
[1]);
22642 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
22643 assemble_name (file
, buf
);
22644 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
22647 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22648 fprintf (file
, "\tbl %s%s\n",
22649 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
22654 if (!TARGET_PROFILE_KERNEL
)
22656 /* Don't do anything, done in output_profile_hook (). */
22660 gcc_assert (!TARGET_32BIT
);
22662 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
22663 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
22665 if (cfun
->static_chain_decl
!= NULL
)
22667 asm_fprintf (file
, "\tstd %s,24(%s)\n",
22668 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
22669 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
22670 asm_fprintf (file
, "\tld %s,24(%s)\n",
22671 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
22674 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
22682 /* The following variable value is the last issued insn. */
22684 static rtx last_scheduled_insn
;
22686 /* The following variable helps to balance issuing of load and
22687 store instructions */
22689 static int load_store_pendulum
;
22691 /* Power4 load update and store update instructions are cracked into a
22692 load or store and an integer insn which are executed in the same cycle.
22693 Branches have their own dispatch slot which does not count against the
22694 GCC issue rate, but it changes the program flow so there are no other
22695 instructions to issue in this cycle. */
22698 rs6000_variable_issue_1 (rtx insn
, int more
)
22700 last_scheduled_insn
= insn
;
22701 if (GET_CODE (PATTERN (insn
)) == USE
22702 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22704 cached_can_issue_more
= more
;
22705 return cached_can_issue_more
;
22708 if (insn_terminates_group_p (insn
, current_group
))
22710 cached_can_issue_more
= 0;
22711 return cached_can_issue_more
;
22714 /* If no reservation, but reach here */
22715 if (recog_memoized (insn
) < 0)
22718 if (rs6000_sched_groups
)
22720 if (is_microcoded_insn (insn
))
22721 cached_can_issue_more
= 0;
22722 else if (is_cracked_insn (insn
))
22723 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
22725 cached_can_issue_more
= more
- 1;
22727 return cached_can_issue_more
;
22730 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
22733 cached_can_issue_more
= more
- 1;
22734 return cached_can_issue_more
;
22738 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
22740 int r
= rs6000_variable_issue_1 (insn
, more
);
22742 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
22746 /* Adjust the cost of a scheduling dependency. Return the new cost of
22747 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22750 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
22752 enum attr_type attr_type
;
22754 if (! recog_memoized (insn
))
22757 switch (REG_NOTE_KIND (link
))
22761 /* Data dependency; DEP_INSN writes a register that INSN reads
22762 some cycles later. */
22764 /* Separate a load from a narrower, dependent store. */
22765 if (rs6000_sched_groups
22766 && GET_CODE (PATTERN (insn
)) == SET
22767 && GET_CODE (PATTERN (dep_insn
)) == SET
22768 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
22769 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
22770 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
22771 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
22774 attr_type
= get_attr_type (insn
);
22779 /* Tell the first scheduling pass about the latency between
22780 a mtctr and bctr (and mtlr and br/blr). The first
22781 scheduling pass will not know about this latency since
22782 the mtctr instruction, which has the latency associated
22783 to it, will be generated by reload. */
22786 /* Leave some extra cycles between a compare and its
22787 dependent branch, to inhibit expensive mispredicts. */
22788 if ((rs6000_cpu_attr
== CPU_PPC603
22789 || rs6000_cpu_attr
== CPU_PPC604
22790 || rs6000_cpu_attr
== CPU_PPC604E
22791 || rs6000_cpu_attr
== CPU_PPC620
22792 || rs6000_cpu_attr
== CPU_PPC630
22793 || rs6000_cpu_attr
== CPU_PPC750
22794 || rs6000_cpu_attr
== CPU_PPC7400
22795 || rs6000_cpu_attr
== CPU_PPC7450
22796 || rs6000_cpu_attr
== CPU_PPCE5500
22797 || rs6000_cpu_attr
== CPU_PPCE6500
22798 || rs6000_cpu_attr
== CPU_POWER4
22799 || rs6000_cpu_attr
== CPU_POWER5
22800 || rs6000_cpu_attr
== CPU_POWER7
22801 || rs6000_cpu_attr
== CPU_CELL
)
22802 && recog_memoized (dep_insn
)
22803 && (INSN_CODE (dep_insn
) >= 0))
22805 switch (get_attr_type (dep_insn
))
22809 case TYPE_DELAYED_COMPARE
:
22810 case TYPE_IMUL_COMPARE
:
22811 case TYPE_LMUL_COMPARE
:
22812 case TYPE_FPCOMPARE
:
22813 case TYPE_CR_LOGICAL
:
22814 case TYPE_DELAYED_CR
:
22823 case TYPE_STORE_UX
:
22825 case TYPE_FPSTORE_U
:
22826 case TYPE_FPSTORE_UX
:
22827 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22828 && recog_memoized (dep_insn
)
22829 && (INSN_CODE (dep_insn
) >= 0))
22832 if (GET_CODE (PATTERN (insn
)) != SET
)
22833 /* If this happens, we have to extend this to schedule
22834 optimally. Return default for now. */
22837 /* Adjust the cost for the case where the value written
22838 by a fixed point operation is used as the address
22839 gen value on a store. */
22840 switch (get_attr_type (dep_insn
))
22847 if (! store_data_bypass_p (dep_insn
, insn
))
22851 case TYPE_LOAD_EXT
:
22852 case TYPE_LOAD_EXT_U
:
22853 case TYPE_LOAD_EXT_UX
:
22854 case TYPE_VAR_SHIFT_ROTATE
:
22855 case TYPE_VAR_DELAYED_COMPARE
:
22857 if (! store_data_bypass_p (dep_insn
, insn
))
22863 case TYPE_FAST_COMPARE
:
22866 case TYPE_INSERT_WORD
:
22867 case TYPE_INSERT_DWORD
:
22868 case TYPE_FPLOAD_U
:
22869 case TYPE_FPLOAD_UX
:
22871 case TYPE_STORE_UX
:
22872 case TYPE_FPSTORE_U
:
22873 case TYPE_FPSTORE_UX
:
22875 if (! store_data_bypass_p (dep_insn
, insn
))
22883 case TYPE_IMUL_COMPARE
:
22884 case TYPE_LMUL_COMPARE
:
22886 if (! store_data_bypass_p (dep_insn
, insn
))
22892 if (! store_data_bypass_p (dep_insn
, insn
))
22898 if (! store_data_bypass_p (dep_insn
, insn
))
22911 case TYPE_LOAD_EXT
:
22912 case TYPE_LOAD_EXT_U
:
22913 case TYPE_LOAD_EXT_UX
:
22914 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22915 && recog_memoized (dep_insn
)
22916 && (INSN_CODE (dep_insn
) >= 0))
22919 /* Adjust the cost for the case where the value written
22920 by a fixed point instruction is used within the address
22921 gen portion of a subsequent load(u)(x) */
22922 switch (get_attr_type (dep_insn
))
22929 if (set_to_load_agen (dep_insn
, insn
))
22933 case TYPE_LOAD_EXT
:
22934 case TYPE_LOAD_EXT_U
:
22935 case TYPE_LOAD_EXT_UX
:
22936 case TYPE_VAR_SHIFT_ROTATE
:
22937 case TYPE_VAR_DELAYED_COMPARE
:
22939 if (set_to_load_agen (dep_insn
, insn
))
22945 case TYPE_FAST_COMPARE
:
22948 case TYPE_INSERT_WORD
:
22949 case TYPE_INSERT_DWORD
:
22950 case TYPE_FPLOAD_U
:
22951 case TYPE_FPLOAD_UX
:
22953 case TYPE_STORE_UX
:
22954 case TYPE_FPSTORE_U
:
22955 case TYPE_FPSTORE_UX
:
22957 if (set_to_load_agen (dep_insn
, insn
))
22965 case TYPE_IMUL_COMPARE
:
22966 case TYPE_LMUL_COMPARE
:
22968 if (set_to_load_agen (dep_insn
, insn
))
22974 if (set_to_load_agen (dep_insn
, insn
))
22980 if (set_to_load_agen (dep_insn
, insn
))
22991 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22992 && recog_memoized (dep_insn
)
22993 && (INSN_CODE (dep_insn
) >= 0)
22994 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
23001 /* Fall out to return default cost. */
23005 case REG_DEP_OUTPUT
:
23006 /* Output dependency; DEP_INSN writes a register that INSN writes some
23008 if ((rs6000_cpu
== PROCESSOR_POWER6
)
23009 && recog_memoized (dep_insn
)
23010 && (INSN_CODE (dep_insn
) >= 0))
23012 attr_type
= get_attr_type (insn
);
23017 if (get_attr_type (dep_insn
) == TYPE_FP
)
23021 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
23029 /* Anti dependency; DEP_INSN reads a register that INSN writes some
23034 gcc_unreachable ();
23040 /* Debug version of rs6000_adjust_cost. */
23043 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
23045 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
23051 switch (REG_NOTE_KIND (link
))
23053 default: dep
= "unknown depencency"; break;
23054 case REG_DEP_TRUE
: dep
= "data dependency"; break;
23055 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
23056 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
23060 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
23061 "%s, insn:\n", ret
, cost
, dep
);
23069 /* The function returns a true if INSN is microcoded.
23070 Return false otherwise. */
23073 is_microcoded_insn (rtx insn
)
23075 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23076 || GET_CODE (PATTERN (insn
)) == USE
23077 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23080 if (rs6000_cpu_attr
== CPU_CELL
)
23081 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
23083 if (rs6000_sched_groups
)
23085 enum attr_type type
= get_attr_type (insn
);
23086 if (type
== TYPE_LOAD_EXT_U
23087 || type
== TYPE_LOAD_EXT_UX
23088 || type
== TYPE_LOAD_UX
23089 || type
== TYPE_STORE_UX
23090 || type
== TYPE_MFCR
)
23097 /* The function returns true if INSN is cracked into 2 instructions
23098 by the processor (and therefore occupies 2 issue slots). */
23101 is_cracked_insn (rtx insn
)
23103 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23104 || GET_CODE (PATTERN (insn
)) == USE
23105 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23108 if (rs6000_sched_groups
)
23110 enum attr_type type
= get_attr_type (insn
);
23111 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
23112 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
23113 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
23114 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
23115 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
23116 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
23117 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
23118 || type
== TYPE_INSERT_WORD
)
23125 /* The function returns true if INSN can be issued only from
23126 the branch slot. */
23129 is_branch_slot_insn (rtx insn
)
23131 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23132 || GET_CODE (PATTERN (insn
)) == USE
23133 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23136 if (rs6000_sched_groups
)
23138 enum attr_type type
= get_attr_type (insn
);
23139 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
23147 /* The function returns true if out_inst sets a value that is
23148 used in the address generation computation of in_insn */
23150 set_to_load_agen (rtx out_insn
, rtx in_insn
)
23152 rtx out_set
, in_set
;
23154 /* For performance reasons, only handle the simple case where
23155 both loads are a single_set. */
23156 out_set
= single_set (out_insn
);
23159 in_set
= single_set (in_insn
);
23161 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
23167 /* Try to determine base/offset/size parts of the given MEM.
23168 Return true if successful, false if all the values couldn't
23171 This function only looks for REG or REG+CONST address forms.
23172 REG+REG address form will return false. */
23175 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
23176 HOST_WIDE_INT
*size
)
23179 if MEM_SIZE_KNOWN_P (mem
)
23180 *size
= MEM_SIZE (mem
);
23184 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
23185 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
23187 addr_rtx
= (XEXP (mem
, 0));
23189 if (GET_CODE (addr_rtx
) == REG
)
23194 else if (GET_CODE (addr_rtx
) == PLUS
23195 && CONST_INT_P (XEXP (addr_rtx
, 1)))
23197 *base
= XEXP (addr_rtx
, 0);
23198 *offset
= INTVAL (XEXP (addr_rtx
, 1));
23206 /* The function returns true if the target storage location of
23207 mem1 is adjacent to the target storage location of mem2 */
23208 /* Return 1 if memory locations are adjacent. */
23211 adjacent_mem_locations (rtx mem1
, rtx mem2
)
23214 HOST_WIDE_INT off1
, size1
, off2
, size2
;
23216 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
23217 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
23218 return ((REGNO (reg1
) == REGNO (reg2
))
23219 && ((off1
+ size1
== off2
)
23220 || (off2
+ size2
== off1
)));
23225 /* This function returns true if it can be determined that the two MEM
23226 locations overlap by at least 1 byte based on base reg/offset/size. */
23229 mem_locations_overlap (rtx mem1
, rtx mem2
)
23232 HOST_WIDE_INT off1
, size1
, off2
, size2
;
23234 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
23235 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
23236 return ((REGNO (reg1
) == REGNO (reg2
))
23237 && (((off1
<= off2
) && (off1
+ size1
> off2
))
23238 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
23243 /* A C statement (sans semicolon) to update the integer scheduling
23244 priority INSN_PRIORITY (INSN). Increase the priority to execute the
23245 INSN earlier, reduce the priority to execute INSN later. Do not
23246 define this macro if you do not need to adjust the scheduling
23247 priorities of insns. */
23250 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
23252 rtx load_mem
, str_mem
;
23253 /* On machines (like the 750) which have asymmetric integer units,
23254 where one integer unit can do multiply and divides and the other
23255 can't, reduce the priority of multiply/divide so it is scheduled
23256 before other integer operations. */
23259 if (! INSN_P (insn
))
23262 if (GET_CODE (PATTERN (insn
)) == USE
)
23265 switch (rs6000_cpu_attr
) {
23267 switch (get_attr_type (insn
))
23274 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
23275 priority
, priority
);
23276 if (priority
>= 0 && priority
< 0x01000000)
23283 if (insn_must_be_first_in_group (insn
)
23284 && reload_completed
23285 && current_sched_info
->sched_max_insns_priority
23286 && rs6000_sched_restricted_insns_priority
)
23289 /* Prioritize insns that can be dispatched only in the first
23291 if (rs6000_sched_restricted_insns_priority
== 1)
23292 /* Attach highest priority to insn. This means that in
23293 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
23294 precede 'priority' (critical path) considerations. */
23295 return current_sched_info
->sched_max_insns_priority
;
23296 else if (rs6000_sched_restricted_insns_priority
== 2)
23297 /* Increase priority of insn by a minimal amount. This means that in
23298 haifa-sched.c:ready_sort(), only 'priority' (critical path)
23299 considerations precede dispatch-slot restriction considerations. */
23300 return (priority
+ 1);
23303 if (rs6000_cpu
== PROCESSOR_POWER6
23304 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
23305 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
23306 /* Attach highest priority to insn if the scheduler has just issued two
23307 stores and this instruction is a load, or two loads and this instruction
23308 is a store. Power6 wants loads and stores scheduled alternately
23310 return current_sched_info
->sched_max_insns_priority
;
23315 /* Return true if the instruction is nonpipelined on the Cell. */
23317 is_nonpipeline_insn (rtx insn
)
23319 enum attr_type type
;
23320 if (!insn
|| !NONDEBUG_INSN_P (insn
)
23321 || GET_CODE (PATTERN (insn
)) == USE
23322 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23325 type
= get_attr_type (insn
);
23326 if (type
== TYPE_IMUL
23327 || type
== TYPE_IMUL2
23328 || type
== TYPE_IMUL3
23329 || type
== TYPE_LMUL
23330 || type
== TYPE_IDIV
23331 || type
== TYPE_LDIV
23332 || type
== TYPE_SDIV
23333 || type
== TYPE_DDIV
23334 || type
== TYPE_SSQRT
23335 || type
== TYPE_DSQRT
23336 || type
== TYPE_MFCR
23337 || type
== TYPE_MFCRF
23338 || type
== TYPE_MFJMPR
)
23346 /* Return how many instructions the machine can issue per cycle. */
23349 rs6000_issue_rate (void)
23351 /* Unless scheduling for register pressure, use issue rate of 1 for
23352 first scheduling pass to decrease degradation. */
23353 if (!reload_completed
&& !flag_sched_pressure
)
23356 switch (rs6000_cpu_attr
) {
23358 case CPU_PPC601
: /* ? */
23368 case CPU_PPCE300C2
:
23369 case CPU_PPCE300C3
:
23370 case CPU_PPCE500MC
:
23371 case CPU_PPCE500MC64
:
23392 /* Return how many instructions to look ahead for better insn
23396 rs6000_use_sched_lookahead (void)
23398 switch (rs6000_cpu_attr
)
23405 return (reload_completed
? 8 : 0);
23412 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
23414 rs6000_use_sched_lookahead_guard (rtx insn
)
23416 if (rs6000_cpu_attr
!= CPU_CELL
)
23419 if (insn
== NULL_RTX
|| !INSN_P (insn
))
23422 if (!reload_completed
23423 || is_nonpipeline_insn (insn
)
23424 || is_microcoded_insn (insn
))
23430 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
23431 and return true. */
23434 find_mem_ref (rtx pat
, rtx
*mem_ref
)
23439 /* stack_tie does not produce any real memory traffic. */
23440 if (tie_operand (pat
, VOIDmode
))
23443 if (GET_CODE (pat
) == MEM
)
23449 /* Recursively process the pattern. */
23450 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
23452 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
23456 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
23459 else if (fmt
[i
] == 'E')
23460 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
23462 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
23470 /* Determine if PAT is a PATTERN of a load insn. */
23473 is_load_insn1 (rtx pat
, rtx
*load_mem
)
23475 if (!pat
|| pat
== NULL_RTX
)
23478 if (GET_CODE (pat
) == SET
)
23479 return find_mem_ref (SET_SRC (pat
), load_mem
);
23481 if (GET_CODE (pat
) == PARALLEL
)
23485 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
23486 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
23493 /* Determine if INSN loads from memory. */
23496 is_load_insn (rtx insn
, rtx
*load_mem
)
23498 if (!insn
|| !INSN_P (insn
))
23501 if (GET_CODE (insn
) == CALL_INSN
)
23504 return is_load_insn1 (PATTERN (insn
), load_mem
);
23507 /* Determine if PAT is a PATTERN of a store insn. */
23510 is_store_insn1 (rtx pat
, rtx
*str_mem
)
23512 if (!pat
|| pat
== NULL_RTX
)
23515 if (GET_CODE (pat
) == SET
)
23516 return find_mem_ref (SET_DEST (pat
), str_mem
);
23518 if (GET_CODE (pat
) == PARALLEL
)
23522 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
23523 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
23530 /* Determine if INSN stores to memory. */
23533 is_store_insn (rtx insn
, rtx
*str_mem
)
23535 if (!insn
|| !INSN_P (insn
))
23538 return is_store_insn1 (PATTERN (insn
), str_mem
);
23541 /* Returns whether the dependence between INSN and NEXT is considered
23542 costly by the given target. */
23545 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
23549 rtx load_mem
, str_mem
;
23551 /* If the flag is not enabled - no dependence is considered costly;
23552 allow all dependent insns in the same group.
23553 This is the most aggressive option. */
23554 if (rs6000_sched_costly_dep
== no_dep_costly
)
23557 /* If the flag is set to 1 - a dependence is always considered costly;
23558 do not allow dependent instructions in the same group.
23559 This is the most conservative option. */
23560 if (rs6000_sched_costly_dep
== all_deps_costly
)
23563 insn
= DEP_PRO (dep
);
23564 next
= DEP_CON (dep
);
23566 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
23567 && is_load_insn (next
, &load_mem
)
23568 && is_store_insn (insn
, &str_mem
))
23569 /* Prevent load after store in the same group. */
23572 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
23573 && is_load_insn (next
, &load_mem
)
23574 && is_store_insn (insn
, &str_mem
)
23575 && DEP_TYPE (dep
) == REG_DEP_TRUE
23576 && mem_locations_overlap(str_mem
, load_mem
))
23577 /* Prevent load after store in the same group if it is a true
23581 /* The flag is set to X; dependences with latency >= X are considered costly,
23582 and will not be scheduled in the same group. */
23583 if (rs6000_sched_costly_dep
<= max_dep_latency
23584 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
23590 /* Return the next insn after INSN that is found before TAIL is reached,
23591 skipping any "non-active" insns - insns that will not actually occupy
23592 an issue slot. Return NULL_RTX if such an insn is not found. */
23595 get_next_active_insn (rtx insn
, rtx tail
)
23597 if (insn
== NULL_RTX
|| insn
== tail
)
23602 insn
= NEXT_INSN (insn
);
23603 if (insn
== NULL_RTX
|| insn
== tail
)
23608 || (NONJUMP_INSN_P (insn
)
23609 && GET_CODE (PATTERN (insn
)) != USE
23610 && GET_CODE (PATTERN (insn
)) != CLOBBER
23611 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
23617 /* We are about to begin issuing insns for this clock cycle. */
23620 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
23621 rtx
*ready ATTRIBUTE_UNUSED
,
23622 int *pn_ready ATTRIBUTE_UNUSED
,
23623 int clock_var ATTRIBUTE_UNUSED
)
23625 int n_ready
= *pn_ready
;
23628 fprintf (dump
, "// rs6000_sched_reorder :\n");
23630 /* Reorder the ready list, if the second to last ready insn
23631 is a nonepipeline insn. */
23632 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
23634 if (is_nonpipeline_insn (ready
[n_ready
- 1])
23635 && (recog_memoized (ready
[n_ready
- 2]) > 0))
23636 /* Simply swap first two insns. */
23638 rtx tmp
= ready
[n_ready
- 1];
23639 ready
[n_ready
- 1] = ready
[n_ready
- 2];
23640 ready
[n_ready
- 2] = tmp
;
23644 if (rs6000_cpu
== PROCESSOR_POWER6
)
23645 load_store_pendulum
= 0;
23647 return rs6000_issue_rate ();
23650 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23653 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
23654 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
23657 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
23659 /* For Power6, we need to handle some special cases to try and keep the
23660 store queue from overflowing and triggering expensive flushes.
23662 This code monitors how load and store instructions are being issued
23663 and skews the ready list one way or the other to increase the likelihood
23664 that a desired instruction is issued at the proper time.
23666 A couple of things are done. First, we maintain a "load_store_pendulum"
23667 to track the current state of load/store issue.
23669 - If the pendulum is at zero, then no loads or stores have been
23670 issued in the current cycle so we do nothing.
23672 - If the pendulum is 1, then a single load has been issued in this
23673 cycle and we attempt to locate another load in the ready list to
23676 - If the pendulum is -2, then two stores have already been
23677 issued in this cycle, so we increase the priority of the first load
23678 in the ready list to increase it's likelihood of being chosen first
23681 - If the pendulum is -1, then a single store has been issued in this
23682 cycle and we attempt to locate another store in the ready list to
23683 issue with it, preferring a store to an adjacent memory location to
23684 facilitate store pairing in the store queue.
23686 - If the pendulum is 2, then two loads have already been
23687 issued in this cycle, so we increase the priority of the first store
23688 in the ready list to increase it's likelihood of being chosen first
23691 - If the pendulum < -2 or > 2, then do nothing.
23693 Note: This code covers the most common scenarios. There exist non
23694 load/store instructions which make use of the LSU and which
23695 would need to be accounted for to strictly model the behavior
23696 of the machine. Those instructions are currently unaccounted
23697 for to help minimize compile time overhead of this code.
23699 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
23703 rtx tmp
, load_mem
, str_mem
;
23705 if (is_store_insn (last_scheduled_insn
, &str_mem
))
23706 /* Issuing a store, swing the load_store_pendulum to the left */
23707 load_store_pendulum
--;
23708 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
23709 /* Issuing a load, swing the load_store_pendulum to the right */
23710 load_store_pendulum
++;
23712 return cached_can_issue_more
;
23714 /* If the pendulum is balanced, or there is only one instruction on
23715 the ready list, then all is well, so return. */
23716 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
23717 return cached_can_issue_more
;
23719 if (load_store_pendulum
== 1)
23721 /* A load has been issued in this cycle. Scan the ready list
23722 for another load to issue with it */
23727 if (is_load_insn (ready
[pos
], &load_mem
))
23729 /* Found a load. Move it to the head of the ready list,
23730 and adjust it's priority so that it is more likely to
23733 for (i
=pos
; i
<*pn_ready
-1; i
++)
23734 ready
[i
] = ready
[i
+ 1];
23735 ready
[*pn_ready
-1] = tmp
;
23737 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23738 INSN_PRIORITY (tmp
)++;
23744 else if (load_store_pendulum
== -2)
23746 /* Two stores have been issued in this cycle. Increase the
23747 priority of the first load in the ready list to favor it for
23748 issuing in the next cycle. */
23753 if (is_load_insn (ready
[pos
], &load_mem
)
23755 && INSN_PRIORITY_KNOWN (ready
[pos
]))
23757 INSN_PRIORITY (ready
[pos
])++;
23759 /* Adjust the pendulum to account for the fact that a load
23760 was found and increased in priority. This is to prevent
23761 increasing the priority of multiple loads */
23762 load_store_pendulum
--;
23769 else if (load_store_pendulum
== -1)
23771 /* A store has been issued in this cycle. Scan the ready list for
23772 another store to issue with it, preferring a store to an adjacent
23774 int first_store_pos
= -1;
23780 if (is_store_insn (ready
[pos
], &str_mem
))
23783 /* Maintain the index of the first store found on the
23785 if (first_store_pos
== -1)
23786 first_store_pos
= pos
;
23788 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
23789 && adjacent_mem_locations (str_mem
, str_mem2
))
23791 /* Found an adjacent store. Move it to the head of the
23792 ready list, and adjust it's priority so that it is
23793 more likely to stay there */
23795 for (i
=pos
; i
<*pn_ready
-1; i
++)
23796 ready
[i
] = ready
[i
+ 1];
23797 ready
[*pn_ready
-1] = tmp
;
23799 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23800 INSN_PRIORITY (tmp
)++;
23802 first_store_pos
= -1;
23810 if (first_store_pos
>= 0)
23812 /* An adjacent store wasn't found, but a non-adjacent store was,
23813 so move the non-adjacent store to the front of the ready
23814 list, and adjust its priority so that it is more likely to
23816 tmp
= ready
[first_store_pos
];
23817 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
23818 ready
[i
] = ready
[i
+ 1];
23819 ready
[*pn_ready
-1] = tmp
;
23820 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23821 INSN_PRIORITY (tmp
)++;
23824 else if (load_store_pendulum
== 2)
23826 /* Two loads have been issued in this cycle. Increase the priority
23827 of the first store in the ready list to favor it for issuing in
23833 if (is_store_insn (ready
[pos
], &str_mem
)
23835 && INSN_PRIORITY_KNOWN (ready
[pos
]))
23837 INSN_PRIORITY (ready
[pos
])++;
23839 /* Adjust the pendulum to account for the fact that a store
23840 was found and increased in priority. This is to prevent
23841 increasing the priority of multiple stores */
23842 load_store_pendulum
++;
23851 return cached_can_issue_more
;
23854 /* Return whether the presence of INSN causes a dispatch group termination
23855 of group WHICH_GROUP.
23857 If WHICH_GROUP == current_group, this function will return true if INSN
23858 causes the termination of the current group (i.e, the dispatch group to
23859 which INSN belongs). This means that INSN will be the last insn in the
23860 group it belongs to.
23862 If WHICH_GROUP == previous_group, this function will return true if INSN
23863 causes the termination of the previous group (i.e, the dispatch group that
23864 precedes the group to which INSN belongs). This means that INSN will be
23865 the first insn in the group it belongs to). */
23868 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
23875 first
= insn_must_be_first_in_group (insn
);
23876 last
= insn_must_be_last_in_group (insn
);
23881 if (which_group
== current_group
)
23883 else if (which_group
== previous_group
)
23891 insn_must_be_first_in_group (rtx insn
)
23893 enum attr_type type
;
23896 || GET_CODE (insn
) == NOTE
23897 || DEBUG_INSN_P (insn
)
23898 || GET_CODE (PATTERN (insn
)) == USE
23899 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23902 switch (rs6000_cpu
)
23904 case PROCESSOR_POWER5
:
23905 if (is_cracked_insn (insn
))
23907 case PROCESSOR_POWER4
:
23908 if (is_microcoded_insn (insn
))
23911 if (!rs6000_sched_groups
)
23914 type
= get_attr_type (insn
);
23921 case TYPE_DELAYED_CR
:
23922 case TYPE_CR_LOGICAL
:
23936 case PROCESSOR_POWER6
:
23937 type
= get_attr_type (insn
);
23941 case TYPE_INSERT_DWORD
:
23945 case TYPE_VAR_SHIFT_ROTATE
:
23952 case TYPE_INSERT_WORD
:
23953 case TYPE_DELAYED_COMPARE
:
23954 case TYPE_IMUL_COMPARE
:
23955 case TYPE_LMUL_COMPARE
:
23956 case TYPE_FPCOMPARE
:
23967 case TYPE_LOAD_EXT_UX
:
23969 case TYPE_STORE_UX
:
23970 case TYPE_FPLOAD_U
:
23971 case TYPE_FPLOAD_UX
:
23972 case TYPE_FPSTORE_U
:
23973 case TYPE_FPSTORE_UX
:
23979 case PROCESSOR_POWER7
:
23980 type
= get_attr_type (insn
);
23984 case TYPE_CR_LOGICAL
:
23991 case TYPE_DELAYED_COMPARE
:
23992 case TYPE_VAR_DELAYED_COMPARE
:
23998 case TYPE_LOAD_EXT
:
23999 case TYPE_LOAD_EXT_U
:
24000 case TYPE_LOAD_EXT_UX
:
24002 case TYPE_STORE_UX
:
24003 case TYPE_FPLOAD_U
:
24004 case TYPE_FPLOAD_UX
:
24005 case TYPE_FPSTORE_U
:
24006 case TYPE_FPSTORE_UX
:
24022 insn_must_be_last_in_group (rtx insn
)
24024 enum attr_type type
;
24027 || GET_CODE (insn
) == NOTE
24028 || DEBUG_INSN_P (insn
)
24029 || GET_CODE (PATTERN (insn
)) == USE
24030 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24033 switch (rs6000_cpu
) {
24034 case PROCESSOR_POWER4
:
24035 case PROCESSOR_POWER5
:
24036 if (is_microcoded_insn (insn
))
24039 if (is_branch_slot_insn (insn
))
24043 case PROCESSOR_POWER6
:
24044 type
= get_attr_type (insn
);
24051 case TYPE_VAR_SHIFT_ROTATE
:
24058 case TYPE_DELAYED_COMPARE
:
24059 case TYPE_IMUL_COMPARE
:
24060 case TYPE_LMUL_COMPARE
:
24061 case TYPE_FPCOMPARE
:
24075 case PROCESSOR_POWER7
:
24076 type
= get_attr_type (insn
);
24084 case TYPE_LOAD_EXT_U
:
24085 case TYPE_LOAD_EXT_UX
:
24086 case TYPE_STORE_UX
:
24099 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
24100 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
24103 is_costly_group (rtx
*group_insns
, rtx next_insn
)
24106 int issue_rate
= rs6000_issue_rate ();
24108 for (i
= 0; i
< issue_rate
; i
++)
24110 sd_iterator_def sd_it
;
24112 rtx insn
= group_insns
[i
];
24117 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
24119 rtx next
= DEP_CON (dep
);
24121 if (next
== next_insn
24122 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
24130 /* Utility of the function redefine_groups.
24131 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
24132 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
24133 to keep it "far" (in a separate group) from GROUP_INSNS, following
24134 one of the following schemes, depending on the value of the flag
24135 -minsert_sched_nops = X:
24136 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
24137 in order to force NEXT_INSN into a separate group.
24138 (2) X < sched_finish_regroup_exact: insert exactly X nops.
24139 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
24140 insertion (has a group just ended, how many vacant issue slots remain in the
24141 last group, and how many dispatch groups were encountered so far). */
24144 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
24145 rtx next_insn
, bool *group_end
, int can_issue_more
,
24150 int issue_rate
= rs6000_issue_rate ();
24151 bool end
= *group_end
;
24154 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
24155 return can_issue_more
;
24157 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
24158 return can_issue_more
;
24160 force
= is_costly_group (group_insns
, next_insn
);
24162 return can_issue_more
;
24164 if (sched_verbose
> 6)
24165 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
24166 *group_count
,can_issue_more
);
24168 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
24171 can_issue_more
= 0;
24173 /* Since only a branch can be issued in the last issue_slot, it is
24174 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
24175 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
24176 in this case the last nop will start a new group and the branch
24177 will be forced to the new group. */
24178 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
24181 /* Power6 and Power7 have special group ending nop. */
24182 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
)
24184 nop
= gen_group_ending_nop ();
24185 emit_insn_before (nop
, next_insn
);
24186 can_issue_more
= 0;
24189 while (can_issue_more
> 0)
24192 emit_insn_before (nop
, next_insn
);
24200 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
24202 int n_nops
= rs6000_sched_insert_nops
;
24204 /* Nops can't be issued from the branch slot, so the effective
24205 issue_rate for nops is 'issue_rate - 1'. */
24206 if (can_issue_more
== 0)
24207 can_issue_more
= issue_rate
;
24209 if (can_issue_more
== 0)
24211 can_issue_more
= issue_rate
- 1;
24214 for (i
= 0; i
< issue_rate
; i
++)
24216 group_insns
[i
] = 0;
24223 emit_insn_before (nop
, next_insn
);
24224 if (can_issue_more
== issue_rate
- 1) /* new group begins */
24227 if (can_issue_more
== 0)
24229 can_issue_more
= issue_rate
- 1;
24232 for (i
= 0; i
< issue_rate
; i
++)
24234 group_insns
[i
] = 0;
24240 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
24243 /* Is next_insn going to start a new group? */
24246 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
24247 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
24248 || (can_issue_more
< issue_rate
&&
24249 insn_terminates_group_p (next_insn
, previous_group
)));
24250 if (*group_end
&& end
)
24253 if (sched_verbose
> 6)
24254 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
24255 *group_count
, can_issue_more
);
24256 return can_issue_more
;
24259 return can_issue_more
;
24262 /* This function tries to synch the dispatch groups that the compiler "sees"
24263 with the dispatch groups that the processor dispatcher is expected to
24264 form in practice. It tries to achieve this synchronization by forcing the
24265 estimated processor grouping on the compiler (as opposed to the function
24266 'pad_goups' which tries to force the scheduler's grouping on the processor).
24268 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
24269 examines the (estimated) dispatch groups that will be formed by the processor
24270 dispatcher. It marks these group boundaries to reflect the estimated
24271 processor grouping, overriding the grouping that the scheduler had marked.
24272 Depending on the value of the flag '-minsert-sched-nops' this function can
24273 force certain insns into separate groups or force a certain distance between
24274 them by inserting nops, for example, if there exists a "costly dependence"
24277 The function estimates the group boundaries that the processor will form as
24278 follows: It keeps track of how many vacant issue slots are available after
24279 each insn. A subsequent insn will start a new group if one of the following
24281 - no more vacant issue slots remain in the current dispatch group.
24282 - only the last issue slot, which is the branch slot, is vacant, but the next
24283 insn is not a branch.
24284 - only the last 2 or less issue slots, including the branch slot, are vacant,
24285 which means that a cracked insn (which occupies two issue slots) can't be
24286 issued in this group.
24287 - less than 'issue_rate' slots are vacant, and the next insn always needs to
24288 start a new group. */
24291 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
24293 rtx insn
, next_insn
;
24295 int can_issue_more
;
24298 int group_count
= 0;
24302 issue_rate
= rs6000_issue_rate ();
24303 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
24304 for (i
= 0; i
< issue_rate
; i
++)
24306 group_insns
[i
] = 0;
24308 can_issue_more
= issue_rate
;
24310 insn
= get_next_active_insn (prev_head_insn
, tail
);
24313 while (insn
!= NULL_RTX
)
24315 slot
= (issue_rate
- can_issue_more
);
24316 group_insns
[slot
] = insn
;
24318 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
24319 if (insn_terminates_group_p (insn
, current_group
))
24320 can_issue_more
= 0;
24322 next_insn
= get_next_active_insn (insn
, tail
);
24323 if (next_insn
== NULL_RTX
)
24324 return group_count
+ 1;
24326 /* Is next_insn going to start a new group? */
24328 = (can_issue_more
== 0
24329 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
24330 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
24331 || (can_issue_more
< issue_rate
&&
24332 insn_terminates_group_p (next_insn
, previous_group
)));
24334 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
24335 next_insn
, &group_end
, can_issue_more
,
24341 can_issue_more
= 0;
24342 for (i
= 0; i
< issue_rate
; i
++)
24344 group_insns
[i
] = 0;
24348 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
24349 PUT_MODE (next_insn
, VOIDmode
);
24350 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
24351 PUT_MODE (next_insn
, TImode
);
24354 if (can_issue_more
== 0)
24355 can_issue_more
= issue_rate
;
24358 return group_count
;
24361 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
24362 dispatch group boundaries that the scheduler had marked. Pad with nops
24363 any dispatch groups which have vacant issue slots, in order to force the
24364 scheduler's grouping on the processor dispatcher. The function
24365 returns the number of dispatch groups found. */
24368 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
24370 rtx insn
, next_insn
;
24373 int can_issue_more
;
24375 int group_count
= 0;
24377 /* Initialize issue_rate. */
24378 issue_rate
= rs6000_issue_rate ();
24379 can_issue_more
= issue_rate
;
24381 insn
= get_next_active_insn (prev_head_insn
, tail
);
24382 next_insn
= get_next_active_insn (insn
, tail
);
24384 while (insn
!= NULL_RTX
)
24387 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
24389 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
24391 if (next_insn
== NULL_RTX
)
24396 /* If the scheduler had marked group termination at this location
24397 (between insn and next_insn), and neither insn nor next_insn will
24398 force group termination, pad the group with nops to force group
24401 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
24402 && !insn_terminates_group_p (insn
, current_group
)
24403 && !insn_terminates_group_p (next_insn
, previous_group
))
24405 if (!is_branch_slot_insn (next_insn
))
24408 while (can_issue_more
)
24411 emit_insn_before (nop
, next_insn
);
24416 can_issue_more
= issue_rate
;
24421 next_insn
= get_next_active_insn (insn
, tail
);
24424 return group_count
;
24427 /* We're beginning a new block. Initialize data structures as necessary. */
24430 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
24431 int sched_verbose ATTRIBUTE_UNUSED
,
24432 int max_ready ATTRIBUTE_UNUSED
)
24434 last_scheduled_insn
= NULL_RTX
;
24435 load_store_pendulum
= 0;
24438 /* The following function is called at the end of scheduling BB.
24439 After reload, it inserts nops at insn group bundling. */
24442 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
24447 fprintf (dump
, "=== Finishing schedule.\n");
24449 if (reload_completed
&& rs6000_sched_groups
)
24451 /* Do not run sched_finish hook when selective scheduling enabled. */
24452 if (sel_sched_p ())
24455 if (rs6000_sched_insert_nops
== sched_finish_none
)
24458 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
24459 n_groups
= pad_groups (dump
, sched_verbose
,
24460 current_sched_info
->prev_head
,
24461 current_sched_info
->next_tail
);
24463 n_groups
= redefine_groups (dump
, sched_verbose
,
24464 current_sched_info
->prev_head
,
24465 current_sched_info
->next_tail
);
24467 if (sched_verbose
>= 6)
24469 fprintf (dump
, "ngroups = %d\n", n_groups
);
24470 print_rtl (dump
, current_sched_info
->prev_head
);
24471 fprintf (dump
, "Done finish_sched\n");
24476 struct _rs6000_sched_context
24478 short cached_can_issue_more
;
24479 rtx last_scheduled_insn
;
24480 int load_store_pendulum
;
24483 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
24484 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
24486 /* Allocate store for new scheduling context. */
24488 rs6000_alloc_sched_context (void)
24490 return xmalloc (sizeof (rs6000_sched_context_def
));
24493 /* If CLEAN_P is true then initializes _SC with clean data,
24494 and from the global context otherwise. */
24496 rs6000_init_sched_context (void *_sc
, bool clean_p
)
24498 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
24502 sc
->cached_can_issue_more
= 0;
24503 sc
->last_scheduled_insn
= NULL_RTX
;
24504 sc
->load_store_pendulum
= 0;
24508 sc
->cached_can_issue_more
= cached_can_issue_more
;
24509 sc
->last_scheduled_insn
= last_scheduled_insn
;
24510 sc
->load_store_pendulum
= load_store_pendulum
;
24514 /* Sets the global scheduling context to the one pointed to by _SC. */
24516 rs6000_set_sched_context (void *_sc
)
24518 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
24520 gcc_assert (sc
!= NULL
);
24522 cached_can_issue_more
= sc
->cached_can_issue_more
;
24523 last_scheduled_insn
= sc
->last_scheduled_insn
;
24524 load_store_pendulum
= sc
->load_store_pendulum
;
24529 rs6000_free_sched_context (void *_sc
)
24531 gcc_assert (_sc
!= NULL
);
24537 /* Length in units of the trampoline for entering a nested function. */
24540 rs6000_trampoline_size (void)
24544 switch (DEFAULT_ABI
)
24547 gcc_unreachable ();
24550 ret
= (TARGET_32BIT
) ? 12 : 24;
24555 ret
= (TARGET_32BIT
) ? 40 : 48;
24562 /* Emit RTL insns to initialize the variable parts of a trampoline.
24563 FNADDR is an RTX for the address of the function's pure code.
24564 CXT is an RTX for the static chain value for the function. */
24567 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
24569 int regsize
= (TARGET_32BIT
) ? 4 : 8;
24570 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
24571 rtx ctx_reg
= force_reg (Pmode
, cxt
);
24572 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
24574 switch (DEFAULT_ABI
)
24577 gcc_unreachable ();
24579 /* Under AIX, just build the 3 word function descriptor */
24582 rtx fnmem
, fn_reg
, toc_reg
;
24584 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
24585 error ("You cannot take the address of a nested function if you use "
24586 "the -mno-pointers-to-nested-functions option.");
24588 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
24589 fn_reg
= gen_reg_rtx (Pmode
);
24590 toc_reg
= gen_reg_rtx (Pmode
);
24592 /* Macro to shorten the code expansions below. */
24593 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24595 m_tramp
= replace_equiv_address (m_tramp
, addr
);
24597 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
24598 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
24599 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
24600 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
24601 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
24607 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24610 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
24611 LCT_NORMAL
, VOIDmode
, 4,
24613 GEN_INT (rs6000_trampoline_size ()), SImode
,
24621 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24622 identifier as an argument, so the front end shouldn't look it up. */
24625 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
24627 return is_attribute_p ("altivec", attr_id
);
24630 /* Handle the "altivec" attribute. The attribute may have
24631 arguments as follows:
24633 __attribute__((altivec(vector__)))
24634 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24635 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24637 and may appear more than once (e.g., 'vector bool char') in a
24638 given declaration. */
24641 rs6000_handle_altivec_attribute (tree
*node
,
24642 tree name ATTRIBUTE_UNUSED
,
24644 int flags ATTRIBUTE_UNUSED
,
24645 bool *no_add_attrs
)
24647 tree type
= *node
, result
= NULL_TREE
;
24648 enum machine_mode mode
;
24651 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
24652 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
24653 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
24656 while (POINTER_TYPE_P (type
)
24657 || TREE_CODE (type
) == FUNCTION_TYPE
24658 || TREE_CODE (type
) == METHOD_TYPE
24659 || TREE_CODE (type
) == ARRAY_TYPE
)
24660 type
= TREE_TYPE (type
);
24662 mode
= TYPE_MODE (type
);
24664 /* Check for invalid AltiVec type qualifiers. */
24665 if (type
== long_double_type_node
)
24666 error ("use of %<long double%> in AltiVec types is invalid");
24667 else if (type
== boolean_type_node
)
24668 error ("use of boolean types in AltiVec types is invalid");
24669 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
24670 error ("use of %<complex%> in AltiVec types is invalid");
24671 else if (DECIMAL_FLOAT_MODE_P (mode
))
24672 error ("use of decimal floating point types in AltiVec types is invalid");
24673 else if (!TARGET_VSX
)
24675 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
24678 error ("use of %<long%> in AltiVec types is invalid for "
24679 "64-bit code without -mvsx");
24680 else if (rs6000_warn_altivec_long
)
24681 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24684 else if (type
== long_long_unsigned_type_node
24685 || type
== long_long_integer_type_node
)
24686 error ("use of %<long long%> in AltiVec types is invalid without "
24688 else if (type
== double_type_node
)
24689 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24692 switch (altivec_type
)
24695 unsigned_p
= TYPE_UNSIGNED (type
);
24699 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
24702 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
24705 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
24708 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
24710 case SFmode
: result
= V4SF_type_node
; break;
24711 case DFmode
: result
= V2DF_type_node
; break;
24712 /* If the user says 'vector int bool', we may be handed the 'bool'
24713 attribute _before_ the 'vector' attribute, and so select the
24714 proper type in the 'b' case below. */
24715 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
24716 case V2DImode
: case V2DFmode
:
24724 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
24725 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
24726 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
24727 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
24734 case V8HImode
: result
= pixel_V8HI_type_node
;
24740 /* Propagate qualifiers attached to the element type
24741 onto the vector type. */
24742 if (result
&& result
!= type
&& TYPE_QUALS (type
))
24743 result
= build_qualified_type (result
, TYPE_QUALS (type
));
24745 *no_add_attrs
= true; /* No need to hang on to the attribute. */
24748 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
24753 /* AltiVec defines four built-in scalar types that serve as vector
24754 elements; we must teach the compiler how to mangle them. */
24756 static const char *
24757 rs6000_mangle_type (const_tree type
)
24759 type
= TYPE_MAIN_VARIANT (type
);
24761 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
24762 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
24765 if (type
== bool_char_type_node
) return "U6__boolc";
24766 if (type
== bool_short_type_node
) return "U6__bools";
24767 if (type
== pixel_type_node
) return "u7__pixel";
24768 if (type
== bool_int_type_node
) return "U6__booli";
24769 if (type
== bool_long_type_node
) return "U6__booll";
24771 /* Mangle IBM extended float long double as `g' (__float128) on
24772 powerpc*-linux where long-double-64 previously was the default. */
24773 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
24775 && TARGET_LONG_DOUBLE_128
24776 && !TARGET_IEEEQUAD
)
24779 /* For all other types, use normal C++ mangling. */
24783 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24784 struct attribute_spec.handler. */
24787 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
24788 tree args ATTRIBUTE_UNUSED
,
24789 int flags ATTRIBUTE_UNUSED
,
24790 bool *no_add_attrs
)
24792 if (TREE_CODE (*node
) != FUNCTION_TYPE
24793 && TREE_CODE (*node
) != FIELD_DECL
24794 && TREE_CODE (*node
) != TYPE_DECL
)
24796 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
24798 *no_add_attrs
= true;
24804 /* Set longcall attributes on all functions declared when
24805 rs6000_default_long_calls is true. */
24807 rs6000_set_default_type_attributes (tree type
)
24809 if (rs6000_default_long_calls
24810 && (TREE_CODE (type
) == FUNCTION_TYPE
24811 || TREE_CODE (type
) == METHOD_TYPE
))
24812 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
24814 TYPE_ATTRIBUTES (type
));
24817 darwin_set_default_type_attributes (type
);
24821 /* Return a reference suitable for calling a function with the
24822 longcall attribute. */
24825 rs6000_longcall_ref (rtx call_ref
)
24827 const char *call_name
;
24830 if (GET_CODE (call_ref
) != SYMBOL_REF
)
24833 /* System V adds '.' to the internal name, so skip them. */
24834 call_name
= XSTR (call_ref
, 0);
24835 if (*call_name
== '.')
24837 while (*call_name
== '.')
24840 node
= get_identifier (call_name
);
24841 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
24844 return force_reg (Pmode
, call_ref
);
24847 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24848 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24851 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24852 struct attribute_spec.handler. */
24854 rs6000_handle_struct_attribute (tree
*node
, tree name
,
24855 tree args ATTRIBUTE_UNUSED
,
24856 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
24859 if (DECL_P (*node
))
24861 if (TREE_CODE (*node
) == TYPE_DECL
)
24862 type
= &TREE_TYPE (*node
);
24867 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
24868 || TREE_CODE (*type
) == UNION_TYPE
)))
24870 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
24871 *no_add_attrs
= true;
24874 else if ((is_attribute_p ("ms_struct", name
)
24875 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
24876 || ((is_attribute_p ("gcc_struct", name
)
24877 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
24879 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
24881 *no_add_attrs
= true;
24888 rs6000_ms_bitfield_layout_p (const_tree record_type
)
24890 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
24891 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
24892 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
24895 #ifdef USING_ELFOS_H
24897 /* A get_unnamed_section callback, used for switching to toc_section. */
24900 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
24902 if (DEFAULT_ABI
== ABI_AIX
24903 && TARGET_MINIMAL_TOC
24904 && !TARGET_RELOCATABLE
)
24906 if (!toc_initialized
)
24908 toc_initialized
= 1;
24909 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
24910 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
24911 fprintf (asm_out_file
, "\t.tc ");
24912 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
24913 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24914 fprintf (asm_out_file
, "\n");
24916 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24917 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24918 fprintf (asm_out_file
, " = .+32768\n");
24921 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24923 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
24924 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
24927 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24928 if (!toc_initialized
)
24930 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24931 fprintf (asm_out_file
, " = .+32768\n");
24932 toc_initialized
= 1;
24937 /* Implement TARGET_ASM_INIT_SECTIONS. */
24940 rs6000_elf_asm_init_sections (void)
24943 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
24946 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
24947 SDATA2_SECTION_ASM_OP
);
24950 /* Implement TARGET_SELECT_RTX_SECTION. */
24953 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
24954 unsigned HOST_WIDE_INT align
)
24956 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
24957 return toc_section
;
24959 return default_elf_select_rtx_section (mode
, x
, align
);
24962 /* For a SYMBOL_REF, set generic flags and then perform some
24963 target-specific processing.
24965 When the AIX ABI is requested on a non-AIX system, replace the
24966 function name with the real name (with a leading .) rather than the
24967 function descriptor name. This saves a lot of overriding code to
24968 read the prefixes. */
24970 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
24972 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
24974 default_encode_section_info (decl
, rtl
, first
);
24977 && TREE_CODE (decl
) == FUNCTION_DECL
24979 && DEFAULT_ABI
== ABI_AIX
)
24981 rtx sym_ref
= XEXP (rtl
, 0);
24982 size_t len
= strlen (XSTR (sym_ref
, 0));
24983 char *str
= XALLOCAVEC (char, len
+ 2);
24985 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
24986 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
24991 compare_section_name (const char *section
, const char *templ
)
24995 len
= strlen (templ
);
24996 return (strncmp (section
, templ
, len
) == 0
24997 && (section
[len
] == 0 || section
[len
] == '.'));
25001 rs6000_elf_in_small_data_p (const_tree decl
)
25003 if (rs6000_sdata
== SDATA_NONE
)
25006 /* We want to merge strings, so we never consider them small data. */
25007 if (TREE_CODE (decl
) == STRING_CST
)
25010 /* Functions are never in the small data area. */
25011 if (TREE_CODE (decl
) == FUNCTION_DECL
)
25014 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
25016 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
25017 if (compare_section_name (section
, ".sdata")
25018 || compare_section_name (section
, ".sdata2")
25019 || compare_section_name (section
, ".gnu.linkonce.s")
25020 || compare_section_name (section
, ".sbss")
25021 || compare_section_name (section
, ".sbss2")
25022 || compare_section_name (section
, ".gnu.linkonce.sb")
25023 || strcmp (section
, ".PPC.EMB.sdata0") == 0
25024 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
25029 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
25032 && size
<= g_switch_value
25033 /* If it's not public, and we're not going to reference it there,
25034 there's no need to put it in the small data section. */
25035 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
25042 #endif /* USING_ELFOS_H */
25044 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
25047 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
25049 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
25052 /* Do not place thread-local symbols refs in the object blocks. */
25055 rs6000_use_blocks_for_decl_p (const_tree decl
)
25057 return !DECL_THREAD_LOCAL_P (decl
);
25060 /* Return a REG that occurs in ADDR with coefficient 1.
25061 ADDR can be effectively incremented by incrementing REG.
25063 r0 is special and we must not select it as an address
25064 register by this routine since our caller will try to
25065 increment the returned register via an "la" instruction. */
25068 find_addr_reg (rtx addr
)
25070 while (GET_CODE (addr
) == PLUS
)
25072 if (GET_CODE (XEXP (addr
, 0)) == REG
25073 && REGNO (XEXP (addr
, 0)) != 0)
25074 addr
= XEXP (addr
, 0);
25075 else if (GET_CODE (XEXP (addr
, 1)) == REG
25076 && REGNO (XEXP (addr
, 1)) != 0)
25077 addr
= XEXP (addr
, 1);
25078 else if (CONSTANT_P (XEXP (addr
, 0)))
25079 addr
= XEXP (addr
, 1);
25080 else if (CONSTANT_P (XEXP (addr
, 1)))
25081 addr
= XEXP (addr
, 0);
25083 gcc_unreachable ();
25085 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
25090 rs6000_fatal_bad_address (rtx op
)
25092 fatal_insn ("bad address", op
);
25097 typedef struct branch_island_d
{
25098 tree function_name
;
25104 static vec
<branch_island
, va_gc
> *branch_islands
;
25106 /* Remember to generate a branch island for far calls to the given
25110 add_compiler_branch_island (tree label_name
, tree function_name
,
25113 branch_island bi
= {function_name
, label_name
, line_number
};
25114 vec_safe_push (branch_islands
, bi
);
25117 /* Generate far-jump branch islands for everything recorded in
25118 branch_islands. Invoked immediately after the last instruction of
25119 the epilogue has been emitted; the branch islands must be appended
25120 to, and contiguous with, the function body. Mach-O stubs are
25121 generated in machopic_output_stub(). */
25124 macho_branch_islands (void)
25128 while (!vec_safe_is_empty (branch_islands
))
25130 branch_island
*bi
= &branch_islands
->last ();
25131 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
25132 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
25133 char name_buf
[512];
25134 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
25135 if (name
[0] == '*' || name
[0] == '&')
25136 strcpy (name_buf
, name
+1);
25140 strcpy (name_buf
+1, name
);
25142 strcpy (tmp_buf
, "\n");
25143 strcat (tmp_buf
, label
);
25144 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25145 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
25146 dbxout_stabd (N_SLINE
, bi
->line_number
);
25147 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25150 if (TARGET_LINK_STACK
)
25153 get_ppc476_thunk_name (name
);
25154 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
25155 strcat (tmp_buf
, name
);
25156 strcat (tmp_buf
, "\n");
25157 strcat (tmp_buf
, label
);
25158 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
25162 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
25163 strcat (tmp_buf
, label
);
25164 strcat (tmp_buf
, "_pic\n");
25165 strcat (tmp_buf
, label
);
25166 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
25169 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
25170 strcat (tmp_buf
, name_buf
);
25171 strcat (tmp_buf
, " - ");
25172 strcat (tmp_buf
, label
);
25173 strcat (tmp_buf
, "_pic)\n");
25175 strcat (tmp_buf
, "\tmtlr r0\n");
25177 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
25178 strcat (tmp_buf
, name_buf
);
25179 strcat (tmp_buf
, " - ");
25180 strcat (tmp_buf
, label
);
25181 strcat (tmp_buf
, "_pic)\n");
25183 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
25187 strcat (tmp_buf
, ":\nlis r12,hi16(");
25188 strcat (tmp_buf
, name_buf
);
25189 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
25190 strcat (tmp_buf
, name_buf
);
25191 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
25193 output_asm_insn (tmp_buf
, 0);
25194 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25195 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
25196 dbxout_stabd (N_SLINE
, bi
->line_number
);
25197 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25198 branch_islands
->pop ();
25202 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
25203 already there or not. */
25206 no_previous_def (tree function_name
)
25211 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
25212 if (function_name
== bi
->function_name
)
25217 /* GET_PREV_LABEL gets the label name from the previous definition of
25221 get_prev_label (tree function_name
)
25226 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
25227 if (function_name
== bi
->function_name
)
25228 return bi
->label_name
;
25232 /* INSN is either a function call or a millicode call. It may have an
25233 unconditional jump in its delay slot.
25235 CALL_DEST is the routine we are calling. */
25238 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
25239 int cookie_operand_number
)
25241 static char buf
[256];
25242 if (darwin_emit_branch_islands
25243 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
25244 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
25247 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
25249 if (no_previous_def (funname
))
25251 rtx label_rtx
= gen_label_rtx ();
25252 char *label_buf
, temp_buf
[256];
25253 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
25254 CODE_LABEL_NUMBER (label_rtx
));
25255 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
25256 labelname
= get_identifier (label_buf
);
25257 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
25260 labelname
= get_prev_label (funname
);
25262 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
25263 instruction will reach 'foo', otherwise link as 'bl L42'".
25264 "L42" should be a 'branch island', that will do a far jump to
25265 'foo'. Branch islands are generated in
25266 macho_branch_islands(). */
25267 sprintf (buf
, "jbsr %%z%d,%.246s",
25268 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
25271 sprintf (buf
, "bl %%z%d", dest_operand_number
);
25275 /* Generate PIC and indirect symbol stubs. */
25278 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
25280 unsigned int length
;
25281 char *symbol_name
, *lazy_ptr_name
;
25282 char *local_label_0
;
25283 static int label
= 0;
25285 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25286 symb
= (*targetm
.strip_name_encoding
) (symb
);
25289 length
= strlen (symb
);
25290 symbol_name
= XALLOCAVEC (char, length
+ 32);
25291 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
25293 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
25294 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
25297 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
25299 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
25303 fprintf (file
, "\t.align 5\n");
25305 fprintf (file
, "%s:\n", stub
);
25306 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
25309 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
25310 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
25312 fprintf (file
, "\tmflr r0\n");
25313 if (TARGET_LINK_STACK
)
25316 get_ppc476_thunk_name (name
);
25317 fprintf (file
, "\tbl %s\n", name
);
25318 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
25322 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
25323 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
25325 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
25326 lazy_ptr_name
, local_label_0
);
25327 fprintf (file
, "\tmtlr r0\n");
25328 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
25329 (TARGET_64BIT
? "ldu" : "lwzu"),
25330 lazy_ptr_name
, local_label_0
);
25331 fprintf (file
, "\tmtctr r12\n");
25332 fprintf (file
, "\tbctr\n");
25336 fprintf (file
, "\t.align 4\n");
25338 fprintf (file
, "%s:\n", stub
);
25339 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
25341 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
25342 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
25343 (TARGET_64BIT
? "ldu" : "lwzu"),
25345 fprintf (file
, "\tmtctr r12\n");
25346 fprintf (file
, "\tbctr\n");
25349 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
25350 fprintf (file
, "%s:\n", lazy_ptr_name
);
25351 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
25352 fprintf (file
, "%sdyld_stub_binding_helper\n",
25353 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
25356 /* Legitimize PIC addresses. If the address is already
25357 position-independent, we return ORIG. Newly generated
25358 position-independent addresses go into a reg. This is REG if non
25359 zero, otherwise we allocate register(s) as necessary. */
25361 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
25364 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
25369 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
25370 reg
= gen_reg_rtx (Pmode
);
25372 if (GET_CODE (orig
) == CONST
)
25376 if (GET_CODE (XEXP (orig
, 0)) == PLUS
25377 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
25380 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
25382 /* Use a different reg for the intermediate value, as
25383 it will be marked UNCHANGING. */
25384 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
25385 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
25388 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
25391 if (GET_CODE (offset
) == CONST_INT
)
25393 if (SMALL_INT (offset
))
25394 return plus_constant (Pmode
, base
, INTVAL (offset
));
25395 else if (! reload_in_progress
&& ! reload_completed
)
25396 offset
= force_reg (Pmode
, offset
);
25399 rtx mem
= force_const_mem (Pmode
, orig
);
25400 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
25403 return gen_rtx_PLUS (Pmode
, base
, offset
);
25406 /* Fall back on generic machopic code. */
25407 return machopic_legitimize_pic_address (orig
, mode
, reg
);
25410 /* Output a .machine directive for the Darwin assembler, and call
25411 the generic start_file routine. */
25414 rs6000_darwin_file_start (void)
25416 static const struct
25420 HOST_WIDE_INT if_set
;
25422 { "ppc64", "ppc64", MASK_64BIT
},
25423 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
25424 { "power4", "ppc970", 0 },
25425 { "G5", "ppc970", 0 },
25426 { "7450", "ppc7450", 0 },
25427 { "7400", "ppc7400", MASK_ALTIVEC
},
25428 { "G4", "ppc7400", 0 },
25429 { "750", "ppc750", 0 },
25430 { "740", "ppc750", 0 },
25431 { "G3", "ppc750", 0 },
25432 { "604e", "ppc604e", 0 },
25433 { "604", "ppc604", 0 },
25434 { "603e", "ppc603", 0 },
25435 { "603", "ppc603", 0 },
25436 { "601", "ppc601", 0 },
25437 { NULL
, "ppc", 0 } };
25438 const char *cpu_id
= "";
25441 rs6000_file_start ();
25442 darwin_file_start ();
25444 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
25446 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
25447 cpu_id
= rs6000_default_cpu
;
25449 if (global_options_set
.x_rs6000_cpu_index
)
25450 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
25452 /* Look through the mapping array. Pick the first name that either
25453 matches the argument, has a bit set in IF_SET that is also set
25454 in the target flags, or has a NULL name. */
25457 while (mapping
[i
].arg
!= NULL
25458 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
25459 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
25462 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
25465 #endif /* TARGET_MACHO */
25469 rs6000_elf_reloc_rw_mask (void)
25473 else if (DEFAULT_ABI
== ABI_AIX
)
25479 /* Record an element in the table of global constructors. SYMBOL is
25480 a SYMBOL_REF of the function to be called; PRIORITY is a number
25481 between 0 and MAX_INIT_PRIORITY.
25483 This differs from default_named_section_asm_out_constructor in
25484 that we have special handling for -mrelocatable. */
25486 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
25488 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
25490 const char *section
= ".ctors";
25493 if (priority
!= DEFAULT_INIT_PRIORITY
)
25495 sprintf (buf
, ".ctors.%.5u",
25496 /* Invert the numbering so the linker puts us in the proper
25497 order; constructors are run from right to left, and the
25498 linker sorts in increasing order. */
25499 MAX_INIT_PRIORITY
- priority
);
25503 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
25504 assemble_align (POINTER_SIZE
);
25506 if (TARGET_RELOCATABLE
)
25508 fputs ("\t.long (", asm_out_file
);
25509 output_addr_const (asm_out_file
, symbol
);
25510 fputs (")@fixup\n", asm_out_file
);
25513 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
25516 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
25518 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
25520 const char *section
= ".dtors";
25523 if (priority
!= DEFAULT_INIT_PRIORITY
)
25525 sprintf (buf
, ".dtors.%.5u",
25526 /* Invert the numbering so the linker puts us in the proper
25527 order; constructors are run from right to left, and the
25528 linker sorts in increasing order. */
25529 MAX_INIT_PRIORITY
- priority
);
25533 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
25534 assemble_align (POINTER_SIZE
);
25536 if (TARGET_RELOCATABLE
)
25538 fputs ("\t.long (", asm_out_file
);
25539 output_addr_const (asm_out_file
, symbol
);
25540 fputs (")@fixup\n", asm_out_file
);
25543 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
25547 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
25551 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
25552 ASM_OUTPUT_LABEL (file
, name
);
25553 fputs (DOUBLE_INT_ASM_OP
, file
);
25554 rs6000_output_function_entry (file
, name
);
25555 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
25558 fputs ("\t.size\t", file
);
25559 assemble_name (file
, name
);
25560 fputs (",24\n\t.type\t.", file
);
25561 assemble_name (file
, name
);
25562 fputs (",@function\n", file
);
25563 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
25565 fputs ("\t.globl\t.", file
);
25566 assemble_name (file
, name
);
25571 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
25572 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
25573 rs6000_output_function_entry (file
, name
);
25574 fputs (":\n", file
);
25578 if (TARGET_RELOCATABLE
25579 && !TARGET_SECURE_PLT
25580 && (get_pool_size () != 0 || crtl
->profile
)
25585 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
25587 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
25588 fprintf (file
, "\t.long ");
25589 assemble_name (file
, buf
);
25591 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
25592 assemble_name (file
, buf
);
25596 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
25597 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
25599 if (DEFAULT_ABI
== ABI_AIX
)
25601 const char *desc_name
, *orig_name
;
25603 orig_name
= (*targetm
.strip_name_encoding
) (name
);
25604 desc_name
= orig_name
;
25605 while (*desc_name
== '.')
25608 if (TREE_PUBLIC (decl
))
25609 fprintf (file
, "\t.globl %s\n", desc_name
);
25611 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
25612 fprintf (file
, "%s:\n", desc_name
);
25613 fprintf (file
, "\t.long %s\n", orig_name
);
25614 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
25615 if (DEFAULT_ABI
== ABI_AIX
)
25616 fputs ("\t.long 0\n", file
);
25617 fprintf (file
, "\t.previous\n");
25619 ASM_OUTPUT_LABEL (file
, name
);
25622 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
25624 rs6000_elf_file_end (void)
25626 #ifdef HAVE_AS_GNU_ATTRIBUTE
25627 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
25629 if (rs6000_passes_float
)
25630 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
25631 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
25632 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
25634 if (rs6000_passes_vector
)
25635 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
25636 (TARGET_ALTIVEC_ABI
? 2
25637 : TARGET_SPE_ABI
? 3
25639 if (rs6000_returns_struct
)
25640 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
25641 aix_struct_return
? 2 : 1);
25644 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25646 file_end_indicate_exec_stack ();
25653 rs6000_xcoff_asm_output_anchor (rtx symbol
)
25657 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
25658 SYMBOL_REF_BLOCK_OFFSET (symbol
));
25659 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
25663 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
25665 fputs (GLOBAL_ASM_OP
, stream
);
25666 RS6000_OUTPUT_BASENAME (stream
, name
);
25667 putc ('\n', stream
);
25670 /* A get_unnamed_decl callback, used for read-only sections. PTR
25671 points to the section string variable. */
25674 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
25676 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
25677 *(const char *const *) directive
,
25678 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25681 /* Likewise for read-write sections. */
25684 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
25686 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
25687 *(const char *const *) directive
,
25688 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25692 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
25694 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
25695 *(const char *const *) directive
,
25696 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25699 /* A get_unnamed_section callback, used for switching to toc_section. */
25702 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
25704 if (TARGET_MINIMAL_TOC
)
25706 /* toc_section is always selected at least once from
25707 rs6000_xcoff_file_start, so this is guaranteed to
25708 always be defined once and only once in each file. */
25709 if (!toc_initialized
)
25711 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
25712 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
25713 toc_initialized
= 1;
25715 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
25716 (TARGET_32BIT
? "" : ",3"));
25719 fputs ("\t.toc\n", asm_out_file
);
25722 /* Implement TARGET_ASM_INIT_SECTIONS. */
25725 rs6000_xcoff_asm_init_sections (void)
25727 read_only_data_section
25728 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
25729 &xcoff_read_only_section_name
);
25731 private_data_section
25732 = get_unnamed_section (SECTION_WRITE
,
25733 rs6000_xcoff_output_readwrite_section_asm_op
,
25734 &xcoff_private_data_section_name
);
25737 = get_unnamed_section (SECTION_TLS
,
25738 rs6000_xcoff_output_tls_section_asm_op
,
25739 &xcoff_tls_data_section_name
);
25741 tls_private_data_section
25742 = get_unnamed_section (SECTION_TLS
,
25743 rs6000_xcoff_output_tls_section_asm_op
,
25744 &xcoff_private_data_section_name
);
25746 read_only_private_data_section
25747 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
25748 &xcoff_private_data_section_name
);
25751 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
25753 readonly_data_section
= read_only_data_section
;
25754 exception_section
= data_section
;
25758 rs6000_xcoff_reloc_rw_mask (void)
25764 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
25765 tree decl ATTRIBUTE_UNUSED
)
25768 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
25770 if (flags
& SECTION_CODE
)
25772 else if (flags
& SECTION_TLS
)
25774 else if (flags
& SECTION_WRITE
)
25779 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
25780 (flags
& SECTION_CODE
) ? "." : "",
25781 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
25785 rs6000_xcoff_select_section (tree decl
, int reloc
,
25786 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
25788 if (decl_readonly_section (decl
, reloc
))
25790 if (TREE_PUBLIC (decl
))
25791 return read_only_data_section
;
25793 return read_only_private_data_section
;
25798 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
25800 if (TREE_PUBLIC (decl
))
25801 return tls_data_section
;
25802 else if (bss_initializer_p (decl
))
25804 /* Convert to COMMON to emit in BSS. */
25805 DECL_COMMON (decl
) = 1;
25806 return tls_comm_section
;
25809 return tls_private_data_section
;
25813 if (TREE_PUBLIC (decl
))
25814 return data_section
;
25816 return private_data_section
;
25821 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
25825 /* Use select_section for private and uninitialized data. */
25826 if (!TREE_PUBLIC (decl
)
25827 || DECL_COMMON (decl
)
25828 || DECL_INITIAL (decl
) == NULL_TREE
25829 || DECL_INITIAL (decl
) == error_mark_node
25830 || (flag_zero_initialized_in_bss
25831 && initializer_zerop (DECL_INITIAL (decl
))))
25834 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
25835 name
= (*targetm
.strip_name_encoding
) (name
);
25836 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
25839 /* Select section for constant in constant pool.
25841 On RS/6000, all constants are in the private read-only data area.
25842 However, if this is being placed in the TOC it must be output as a
25846 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
25847 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
25849 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
25850 return toc_section
;
25852 return read_only_private_data_section
;
25855 /* Remove any trailing [DS] or the like from the symbol name. */
25857 static const char *
25858 rs6000_xcoff_strip_name_encoding (const char *name
)
25863 len
= strlen (name
);
25864 if (name
[len
- 1] == ']')
25865 return ggc_alloc_string (name
, len
- 4);
25870 /* Section attributes. AIX is always PIC. */
25872 static unsigned int
25873 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
25875 unsigned int align
;
25876 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
25878 /* Align to at least UNIT size. */
25879 if (flags
& SECTION_CODE
|| !decl
)
25880 align
= MIN_UNITS_PER_WORD
;
25882 /* Increase alignment of large objects if not already stricter. */
25883 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
25884 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
25885 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
25887 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
25890 /* Output at beginning of assembler file.
25892 Initialize the section names for the RS/6000 at this point.
25894 Specify filename, including full path, to assembler.
25896 We want to go into the TOC section so at least one .toc will be emitted.
25897 Also, in order to output proper .bs/.es pairs, we need at least one static
25898 [RW] section emitted.
25900 Finally, declare mcount when profiling to make the assembler happy. */
25903 rs6000_xcoff_file_start (void)
25905 rs6000_gen_section_name (&xcoff_bss_section_name
,
25906 main_input_filename
, ".bss_");
25907 rs6000_gen_section_name (&xcoff_private_data_section_name
,
25908 main_input_filename
, ".rw_");
25909 rs6000_gen_section_name (&xcoff_read_only_section_name
,
25910 main_input_filename
, ".ro_");
25911 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
25912 main_input_filename
, ".tls_");
25913 rs6000_gen_section_name (&xcoff_tbss_section_name
,
25914 main_input_filename
, ".tbss_[UL]");
25916 fputs ("\t.file\t", asm_out_file
);
25917 output_quoted_string (asm_out_file
, main_input_filename
);
25918 fputc ('\n', asm_out_file
);
25919 if (write_symbols
!= NO_DEBUG
)
25920 switch_to_section (private_data_section
);
25921 switch_to_section (text_section
);
25923 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
25924 rs6000_file_start ();
25927 /* Output at end of assembler file.
25928 On the RS/6000, referencing data should automatically pull in text. */
25931 rs6000_xcoff_file_end (void)
25933 switch_to_section (text_section
);
25934 fputs ("_section_.text:\n", asm_out_file
);
25935 switch_to_section (data_section
);
25936 fputs (TARGET_32BIT
25937 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25943 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
25948 default_encode_section_info (decl
, rtl
, first
);
25950 /* Careful not to prod global register variables. */
25953 symbol
= XEXP (rtl
, 0);
25954 if (GET_CODE (symbol
) != SYMBOL_REF
)
25957 flags
= SYMBOL_REF_FLAGS (symbol
);
25959 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
25960 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
25962 SYMBOL_REF_FLAGS (symbol
) = flags
;
25964 #endif /* HAVE_AS_TLS */
25965 #endif /* TARGET_XCOFF */
25967 /* Compute a (partial) cost for rtx X. Return true if the complete
25968 cost has been computed, and false if subexpressions should be
25969 scanned. In either case, *TOTAL contains the cost result. */
25972 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
25973 int *total
, bool speed
)
25975 enum machine_mode mode
= GET_MODE (x
);
25979 /* On the RS/6000, if it is valid in the insn, it is free. */
25981 if (((outer_code
== SET
25982 || outer_code
== PLUS
25983 || outer_code
== MINUS
)
25984 && (satisfies_constraint_I (x
)
25985 || satisfies_constraint_L (x
)))
25986 || (outer_code
== AND
25987 && (satisfies_constraint_K (x
)
25989 ? satisfies_constraint_L (x
)
25990 : satisfies_constraint_J (x
))
25991 || mask_operand (x
, mode
)
25993 && mask64_operand (x
, DImode
))))
25994 || ((outer_code
== IOR
|| outer_code
== XOR
)
25995 && (satisfies_constraint_K (x
)
25997 ? satisfies_constraint_L (x
)
25998 : satisfies_constraint_J (x
))))
25999 || outer_code
== ASHIFT
26000 || outer_code
== ASHIFTRT
26001 || outer_code
== LSHIFTRT
26002 || outer_code
== ROTATE
26003 || outer_code
== ROTATERT
26004 || outer_code
== ZERO_EXTRACT
26005 || (outer_code
== MULT
26006 && satisfies_constraint_I (x
))
26007 || ((outer_code
== DIV
|| outer_code
== UDIV
26008 || outer_code
== MOD
|| outer_code
== UMOD
)
26009 && exact_log2 (INTVAL (x
)) >= 0)
26010 || (outer_code
== COMPARE
26011 && (satisfies_constraint_I (x
)
26012 || satisfies_constraint_K (x
)))
26013 || ((outer_code
== EQ
|| outer_code
== NE
)
26014 && (satisfies_constraint_I (x
)
26015 || satisfies_constraint_K (x
)
26017 ? satisfies_constraint_L (x
)
26018 : satisfies_constraint_J (x
))))
26019 || (outer_code
== GTU
26020 && satisfies_constraint_I (x
))
26021 || (outer_code
== LTU
26022 && satisfies_constraint_P (x
)))
26027 else if ((outer_code
== PLUS
26028 && reg_or_add_cint_operand (x
, VOIDmode
))
26029 || (outer_code
== MINUS
26030 && reg_or_sub_cint_operand (x
, VOIDmode
))
26031 || ((outer_code
== SET
26032 || outer_code
== IOR
26033 || outer_code
== XOR
)
26035 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
26037 *total
= COSTS_N_INSNS (1);
26043 if (mode
== DImode
&& code
== CONST_DOUBLE
)
26045 if ((outer_code
== IOR
|| outer_code
== XOR
)
26046 && CONST_DOUBLE_HIGH (x
) == 0
26047 && (CONST_DOUBLE_LOW (x
)
26048 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
26053 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
26054 || ((outer_code
== SET
26055 || outer_code
== IOR
26056 || outer_code
== XOR
)
26057 && CONST_DOUBLE_HIGH (x
) == 0))
26059 *total
= COSTS_N_INSNS (1);
26069 /* When optimizing for size, MEM should be slightly more expensive
26070 than generating address, e.g., (plus (reg) (const)).
26071 L1 cache latency is about two instructions. */
26072 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
26081 if (FLOAT_MODE_P (mode
))
26082 *total
= rs6000_cost
->fp
;
26084 *total
= COSTS_N_INSNS (1);
26088 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
26089 && satisfies_constraint_I (XEXP (x
, 1)))
26091 if (INTVAL (XEXP (x
, 1)) >= -256
26092 && INTVAL (XEXP (x
, 1)) <= 255)
26093 *total
= rs6000_cost
->mulsi_const9
;
26095 *total
= rs6000_cost
->mulsi_const
;
26097 else if (mode
== SFmode
)
26098 *total
= rs6000_cost
->fp
;
26099 else if (FLOAT_MODE_P (mode
))
26100 *total
= rs6000_cost
->dmul
;
26101 else if (mode
== DImode
)
26102 *total
= rs6000_cost
->muldi
;
26104 *total
= rs6000_cost
->mulsi
;
26108 if (mode
== SFmode
)
26109 *total
= rs6000_cost
->fp
;
26111 *total
= rs6000_cost
->dmul
;
26116 if (FLOAT_MODE_P (mode
))
26118 *total
= mode
== DFmode
? rs6000_cost
->ddiv
26119 : rs6000_cost
->sdiv
;
26126 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
26127 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
26129 if (code
== DIV
|| code
== MOD
)
26131 *total
= COSTS_N_INSNS (2);
26134 *total
= COSTS_N_INSNS (1);
26138 if (GET_MODE (XEXP (x
, 1)) == DImode
)
26139 *total
= rs6000_cost
->divdi
;
26141 *total
= rs6000_cost
->divsi
;
26143 /* Add in shift and subtract for MOD. */
26144 if (code
== MOD
|| code
== UMOD
)
26145 *total
+= COSTS_N_INSNS (2);
26150 *total
= COSTS_N_INSNS (4);
26154 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
26158 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
26162 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
26174 *total
= COSTS_N_INSNS (1);
26182 /* Handle mul_highpart. */
26183 if (outer_code
== TRUNCATE
26184 && GET_CODE (XEXP (x
, 0)) == MULT
)
26186 if (mode
== DImode
)
26187 *total
= rs6000_cost
->muldi
;
26189 *total
= rs6000_cost
->mulsi
;
26192 else if (outer_code
== AND
)
26195 *total
= COSTS_N_INSNS (1);
26200 if (GET_CODE (XEXP (x
, 0)) == MEM
)
26203 *total
= COSTS_N_INSNS (1);
26209 if (!FLOAT_MODE_P (mode
))
26211 *total
= COSTS_N_INSNS (1);
26217 case UNSIGNED_FLOAT
:
26220 case FLOAT_TRUNCATE
:
26221 *total
= rs6000_cost
->fp
;
26225 if (mode
== DFmode
)
26228 *total
= rs6000_cost
->fp
;
26232 switch (XINT (x
, 1))
26235 *total
= rs6000_cost
->fp
;
26247 *total
= COSTS_N_INSNS (1);
26250 else if (FLOAT_MODE_P (mode
)
26251 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
26253 *total
= rs6000_cost
->fp
;
26261 /* Carry bit requires mode == Pmode.
26262 NEG or PLUS already counted so only add one. */
26264 && (outer_code
== NEG
|| outer_code
== PLUS
))
26266 *total
= COSTS_N_INSNS (1);
26269 if (outer_code
== SET
)
26271 if (XEXP (x
, 1) == const0_rtx
)
26273 if (TARGET_ISEL
&& !TARGET_MFCRF
)
26274 *total
= COSTS_N_INSNS (8);
26276 *total
= COSTS_N_INSNS (2);
26279 else if (mode
== Pmode
)
26281 *total
= COSTS_N_INSNS (3);
26290 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
26292 if (TARGET_ISEL
&& !TARGET_MFCRF
)
26293 *total
= COSTS_N_INSNS (8);
26295 *total
= COSTS_N_INSNS (2);
26299 if (outer_code
== COMPARE
)
26313 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
26316 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
26319 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
26322 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
26323 "opno = %d, total = %d, speed = %s, x:\n",
26324 ret
? "complete" : "scan inner",
26325 GET_RTX_NAME (code
),
26326 GET_RTX_NAME (outer_code
),
26329 speed
? "true" : "false");
26336 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
26339 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
26340 addr_space_t as
, bool speed
)
26342 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
26344 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
26345 ret
, speed
? "true" : "false");
26352 /* A C expression returning the cost of moving data from a register of class
26353 CLASS1 to one of CLASS2. */
26356 rs6000_register_move_cost (enum machine_mode mode
,
26357 reg_class_t from
, reg_class_t to
)
26361 if (TARGET_DEBUG_COST
)
26364 /* Moves from/to GENERAL_REGS. */
26365 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
26366 || reg_classes_intersect_p (from
, GENERAL_REGS
))
26368 reg_class_t rclass
= from
;
26370 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
26373 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
26374 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
26375 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
26377 /* It's more expensive to move CR_REGS than CR0_REGS because of the
26379 else if (rclass
== CR_REGS
)
26382 /* For those processors that have slow LR/CTR moves, make them more
26383 expensive than memory in order to bias spills to memory .*/
26384 else if ((rs6000_cpu
== PROCESSOR_POWER6
26385 || rs6000_cpu
== PROCESSOR_POWER7
)
26386 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
26387 ret
= 6 * hard_regno_nregs
[0][mode
];
26390 /* A move will cost one instruction per GPR moved. */
26391 ret
= 2 * hard_regno_nregs
[0][mode
];
26394 /* If we have VSX, we can easily move between FPR or Altivec registers. */
26395 else if (VECTOR_UNIT_VSX_P (mode
)
26396 && reg_classes_intersect_p (to
, VSX_REGS
)
26397 && reg_classes_intersect_p (from
, VSX_REGS
))
26398 ret
= 2 * hard_regno_nregs
[32][mode
];
26400 /* Moving between two similar registers is just one instruction. */
26401 else if (reg_classes_intersect_p (to
, from
))
26402 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
26404 /* Everything else has to go through GENERAL_REGS. */
26406 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
26407 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
26409 if (TARGET_DEBUG_COST
)
26411 if (dbg_cost_ctrl
== 1)
26413 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
26414 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
26415 reg_class_names
[to
]);
26422 /* A C expressions returning the cost of moving data of MODE from a register to
26426 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
26427 bool in ATTRIBUTE_UNUSED
)
26431 if (TARGET_DEBUG_COST
)
26434 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
26435 ret
= 4 * hard_regno_nregs
[0][mode
];
26436 else if (reg_classes_intersect_p (rclass
, FLOAT_REGS
))
26437 ret
= 4 * hard_regno_nregs
[32][mode
];
26438 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
26439 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
26441 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
26443 if (TARGET_DEBUG_COST
)
26445 if (dbg_cost_ctrl
== 1)
26447 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
26448 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
26455 /* Returns a code for a target-specific builtin that implements
26456 reciprocal of the function, or NULL_TREE if not available. */
26459 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
26460 bool sqrt ATTRIBUTE_UNUSED
)
26462 if (optimize_insn_for_size_p ())
26468 case VSX_BUILTIN_XVSQRTDP
:
26469 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
26472 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
26474 case VSX_BUILTIN_XVSQRTSP
:
26475 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
26478 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
26487 case BUILT_IN_SQRT
:
26488 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
26491 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
26493 case BUILT_IN_SQRTF
:
26494 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
26497 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
26504 /* Load up a constant. If the mode is a vector mode, splat the value across
26505 all of the vector elements. */
26508 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
26512 if (mode
== SFmode
|| mode
== DFmode
)
26514 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
26515 reg
= force_reg (mode
, d
);
26517 else if (mode
== V4SFmode
)
26519 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
26520 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
26521 reg
= gen_reg_rtx (mode
);
26522 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
26524 else if (mode
== V2DFmode
)
26526 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
26527 rtvec v
= gen_rtvec (2, d
, d
);
26528 reg
= gen_reg_rtx (mode
);
26529 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
26532 gcc_unreachable ();
26537 /* Generate an FMA instruction. */
26540 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
26542 enum machine_mode mode
= GET_MODE (target
);
26545 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
26546 gcc_assert (dst
!= NULL
);
26549 emit_move_insn (target
, dst
);
26552 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
26555 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
26557 enum machine_mode mode
= GET_MODE (target
);
26560 /* Altivec does not support fms directly;
26561 generate in terms of fma in that case. */
26562 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
26563 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
26566 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
26567 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
26569 gcc_assert (dst
!= NULL
);
26572 emit_move_insn (target
, dst
);
26575 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
26578 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
26580 enum machine_mode mode
= GET_MODE (dst
);
26583 /* This is a tad more complicated, since the fnma_optab is for
26584 a different expression: fma(-m1, m2, a), which is the same
26585 thing except in the case of signed zeros.
26587 Fortunately we know that if FMA is supported that FNMSUB is
26588 also supported in the ISA. Just expand it directly. */
26590 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
26592 r
= gen_rtx_NEG (mode
, a
);
26593 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
26594 r
= gen_rtx_NEG (mode
, r
);
26595 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
26598 /* Newton-Raphson approximation of floating point divide with just 2 passes
26599 (either single precision floating point, or newer machines with higher
26600 accuracy estimates). Support both scalar and vector divide. Assumes no
26601 trapping math and finite arguments. */
26604 rs6000_emit_swdiv_high_precision (rtx dst
, rtx n
, rtx d
)
26606 enum machine_mode mode
= GET_MODE (dst
);
26607 rtx x0
, e0
, e1
, y1
, u0
, v0
;
26608 enum insn_code code
= optab_handler (smul_optab
, mode
);
26609 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26610 rtx one
= rs6000_load_constant_and_splat (mode
, dconst1
);
26612 gcc_assert (code
!= CODE_FOR_nothing
);
26614 /* x0 = 1./d estimate */
26615 x0
= gen_reg_rtx (mode
);
26616 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26617 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
26620 e0
= gen_reg_rtx (mode
);
26621 rs6000_emit_nmsub (e0
, d
, x0
, one
); /* e0 = 1. - (d * x0) */
26623 e1
= gen_reg_rtx (mode
);
26624 rs6000_emit_madd (e1
, e0
, e0
, e0
); /* e1 = (e0 * e0) + e0 */
26626 y1
= gen_reg_rtx (mode
);
26627 rs6000_emit_madd (y1
, e1
, x0
, x0
); /* y1 = (e1 * x0) + x0 */
26629 u0
= gen_reg_rtx (mode
);
26630 emit_insn (gen_mul (u0
, n
, y1
)); /* u0 = n * y1 */
26632 v0
= gen_reg_rtx (mode
);
26633 rs6000_emit_nmsub (v0
, d
, u0
, n
); /* v0 = n - (d * u0) */
26635 rs6000_emit_madd (dst
, v0
, y1
, u0
); /* dst = (v0 * y1) + u0 */
26638 /* Newton-Raphson approximation of floating point divide that has a low
26639 precision estimate. Assumes no trapping math and finite arguments. */
26642 rs6000_emit_swdiv_low_precision (rtx dst
, rtx n
, rtx d
)
26644 enum machine_mode mode
= GET_MODE (dst
);
26645 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
26646 enum insn_code code
= optab_handler (smul_optab
, mode
);
26647 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26649 gcc_assert (code
!= CODE_FOR_nothing
);
26651 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
26653 /* x0 = 1./d estimate */
26654 x0
= gen_reg_rtx (mode
);
26655 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26656 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
26659 e0
= gen_reg_rtx (mode
);
26660 rs6000_emit_nmsub (e0
, d
, x0
, one
); /* e0 = 1. - d * x0 */
26662 y1
= gen_reg_rtx (mode
);
26663 rs6000_emit_madd (y1
, e0
, x0
, x0
); /* y1 = x0 + e0 * x0 */
26665 e1
= gen_reg_rtx (mode
);
26666 emit_insn (gen_mul (e1
, e0
, e0
)); /* e1 = e0 * e0 */
26668 y2
= gen_reg_rtx (mode
);
26669 rs6000_emit_madd (y2
, e1
, y1
, y1
); /* y2 = y1 + e1 * y1 */
26671 e2
= gen_reg_rtx (mode
);
26672 emit_insn (gen_mul (e2
, e1
, e1
)); /* e2 = e1 * e1 */
26674 y3
= gen_reg_rtx (mode
);
26675 rs6000_emit_madd (y3
, e2
, y2
, y2
); /* y3 = y2 + e2 * y2 */
26677 u0
= gen_reg_rtx (mode
);
26678 emit_insn (gen_mul (u0
, n
, y3
)); /* u0 = n * y3 */
26680 v0
= gen_reg_rtx (mode
);
26681 rs6000_emit_nmsub (v0
, d
, u0
, n
); /* v0 = n - d * u0 */
26683 rs6000_emit_madd (dst
, v0
, y3
, u0
); /* dst = u0 + v0 * y3 */
26686 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26687 add a reg_note saying that this was a division. Support both scalar and
26688 vector divide. Assumes no trapping math and finite arguments. */
26691 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
26693 enum machine_mode mode
= GET_MODE (dst
);
26695 if (RS6000_RECIP_HIGH_PRECISION_P (mode
))
26696 rs6000_emit_swdiv_high_precision (dst
, n
, d
);
26698 rs6000_emit_swdiv_low_precision (dst
, n
, d
);
26701 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
26704 /* Newton-Raphson approximation of single/double-precision floating point
26705 rsqrt. Assumes no trapping math and finite arguments. */
26708 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
26710 enum machine_mode mode
= GET_MODE (src
);
26711 rtx x0
= gen_reg_rtx (mode
);
26712 rtx y
= gen_reg_rtx (mode
);
26713 int passes
= (TARGET_RECIP_PRECISION
) ? 2 : 3;
26714 REAL_VALUE_TYPE dconst3_2
;
26717 enum insn_code code
= optab_handler (smul_optab
, mode
);
26718 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26720 gcc_assert (code
!= CODE_FOR_nothing
);
26722 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26723 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
26724 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
26726 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
26728 /* x0 = rsqrt estimate */
26729 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26730 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
26733 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26734 rs6000_emit_msub (y
, src
, halfthree
, src
);
26736 for (i
= 0; i
< passes
; i
++)
26738 rtx x1
= gen_reg_rtx (mode
);
26739 rtx u
= gen_reg_rtx (mode
);
26740 rtx v
= gen_reg_rtx (mode
);
26742 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26743 emit_insn (gen_mul (u
, x0
, x0
));
26744 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
26745 emit_insn (gen_mul (x1
, x0
, v
));
26749 emit_move_insn (dst
, x0
);
26753 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26754 (Power7) targets. DST is the target, and SRC is the argument operand. */
26757 rs6000_emit_popcount (rtx dst
, rtx src
)
26759 enum machine_mode mode
= GET_MODE (dst
);
26762 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26763 if (TARGET_POPCNTD
)
26765 if (mode
== SImode
)
26766 emit_insn (gen_popcntdsi2 (dst
, src
));
26768 emit_insn (gen_popcntddi2 (dst
, src
));
26772 tmp1
= gen_reg_rtx (mode
);
26774 if (mode
== SImode
)
26776 emit_insn (gen_popcntbsi2 (tmp1
, src
));
26777 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
26779 tmp2
= force_reg (SImode
, tmp2
);
26780 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
26784 emit_insn (gen_popcntbdi2 (tmp1
, src
));
26785 tmp2
= expand_mult (DImode
, tmp1
,
26786 GEN_INT ((HOST_WIDE_INT
)
26787 0x01010101 << 32 | 0x01010101),
26789 tmp2
= force_reg (DImode
, tmp2
);
26790 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
26795 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26796 target, and SRC is the argument operand. */
26799 rs6000_emit_parity (rtx dst
, rtx src
)
26801 enum machine_mode mode
= GET_MODE (dst
);
26804 tmp
= gen_reg_rtx (mode
);
26806 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26809 if (mode
== SImode
)
26811 emit_insn (gen_popcntbsi2 (tmp
, src
));
26812 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
26816 emit_insn (gen_popcntbdi2 (tmp
, src
));
26817 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
26822 if (mode
== SImode
)
26824 /* Is mult+shift >= shift+xor+shift+xor? */
26825 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
26827 rtx tmp1
, tmp2
, tmp3
, tmp4
;
26829 tmp1
= gen_reg_rtx (SImode
);
26830 emit_insn (gen_popcntbsi2 (tmp1
, src
));
26832 tmp2
= gen_reg_rtx (SImode
);
26833 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
26834 tmp3
= gen_reg_rtx (SImode
);
26835 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
26837 tmp4
= gen_reg_rtx (SImode
);
26838 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
26839 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
26842 rs6000_emit_popcount (tmp
, src
);
26843 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
26847 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26848 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
26850 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
26852 tmp1
= gen_reg_rtx (DImode
);
26853 emit_insn (gen_popcntbdi2 (tmp1
, src
));
26855 tmp2
= gen_reg_rtx (DImode
);
26856 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
26857 tmp3
= gen_reg_rtx (DImode
);
26858 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
26860 tmp4
= gen_reg_rtx (DImode
);
26861 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
26862 tmp5
= gen_reg_rtx (DImode
);
26863 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
26865 tmp6
= gen_reg_rtx (DImode
);
26866 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
26867 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
26870 rs6000_emit_popcount (tmp
, src
);
26871 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
26875 /* Expand an Altivec constant permutation. Return true if we match
26876 an efficient implementation; false to fall back to VPERM. */
26879 altivec_expand_vec_perm_const (rtx operands
[4])
26881 struct altivec_perm_insn
{
26882 enum insn_code impl
;
26883 unsigned char perm
[16];
26885 static const struct altivec_perm_insn patterns
[] = {
26886 { CODE_FOR_altivec_vpkuhum
,
26887 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26888 { CODE_FOR_altivec_vpkuwum
,
26889 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26890 { CODE_FOR_altivec_vmrghb
,
26891 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26892 { CODE_FOR_altivec_vmrghh
,
26893 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26894 { CODE_FOR_altivec_vmrghw
,
26895 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26896 { CODE_FOR_altivec_vmrglb
,
26897 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26898 { CODE_FOR_altivec_vmrglh
,
26899 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26900 { CODE_FOR_altivec_vmrglw
,
26901 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26904 unsigned int i
, j
, elt
, which
;
26905 unsigned char perm
[16];
26906 rtx target
, op0
, op1
, sel
, x
;
26909 target
= operands
[0];
26914 /* Unpack the constant selector. */
26915 for (i
= which
= 0; i
< 16; ++i
)
26917 rtx e
= XVECEXP (sel
, 0, i
);
26918 elt
= INTVAL (e
) & 31;
26919 which
|= (elt
< 16 ? 1 : 2);
26923 /* Simplify the constant selector based on operands. */
26927 gcc_unreachable ();
26931 if (!rtx_equal_p (op0
, op1
))
26936 for (i
= 0; i
< 16; ++i
)
26948 /* Look for splat patterns. */
26953 for (i
= 0; i
< 16; ++i
)
26954 if (perm
[i
] != elt
)
26958 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
26964 for (i
= 0; i
< 16; i
+= 2)
26965 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
26969 x
= gen_reg_rtx (V8HImode
);
26970 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
26971 GEN_INT (elt
/ 2)));
26972 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26979 for (i
= 0; i
< 16; i
+= 4)
26981 || perm
[i
+ 1] != elt
+ 1
26982 || perm
[i
+ 2] != elt
+ 2
26983 || perm
[i
+ 3] != elt
+ 3)
26987 x
= gen_reg_rtx (V4SImode
);
26988 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
26989 GEN_INT (elt
/ 4)));
26990 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26996 /* Look for merge and pack patterns. */
26997 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
27001 elt
= patterns
[j
].perm
[0];
27002 if (perm
[0] == elt
)
27004 else if (perm
[0] == elt
+ 16)
27008 for (i
= 1; i
< 16; ++i
)
27010 elt
= patterns
[j
].perm
[i
];
27012 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
27013 else if (one_vec
&& elt
>= 16)
27015 if (perm
[i
] != elt
)
27020 enum insn_code icode
= patterns
[j
].impl
;
27021 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
27022 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
27025 x
= op0
, op0
= op1
, op1
= x
;
27026 if (imode
!= V16QImode
)
27028 op0
= gen_lowpart (imode
, op0
);
27029 op1
= gen_lowpart (imode
, op1
);
27031 if (omode
== V16QImode
)
27034 x
= gen_reg_rtx (omode
);
27035 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
27036 if (omode
!= V16QImode
)
27037 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
27045 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
27046 Return true if we match an efficient implementation. */
27049 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
27050 unsigned char perm0
, unsigned char perm1
)
27054 /* If both selectors come from the same operand, fold to single op. */
27055 if ((perm0
& 2) == (perm1
& 2))
27062 /* If both operands are equal, fold to simpler permutation. */
27063 if (rtx_equal_p (op0
, op1
))
27066 perm1
= (perm1
& 1) + 2;
27068 /* If the first selector comes from the second operand, swap. */
27069 else if (perm0
& 2)
27075 x
= op0
, op0
= op1
, op1
= x
;
27077 /* If the second selector does not come from the second operand, fail. */
27078 else if ((perm1
& 2) == 0)
27082 if (target
!= NULL
)
27084 enum machine_mode vmode
, dmode
;
27087 vmode
= GET_MODE (target
);
27088 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
27089 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
27091 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
27092 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
27093 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
27094 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
27100 rs6000_expand_vec_perm_const (rtx operands
[4])
27102 rtx target
, op0
, op1
, sel
;
27103 unsigned char perm0
, perm1
;
27105 target
= operands
[0];
27110 /* Unpack the constant selector. */
27111 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
27112 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
27114 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
27117 /* Test whether a constant permutation is supported. */
27120 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
27121 const unsigned char *sel
)
27123 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
27124 if (TARGET_ALTIVEC
)
27127 /* Check for ps_merge* or evmerge* insns. */
27128 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
27129 || (TARGET_SPE
&& vmode
== V2SImode
))
27131 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
27132 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
27133 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
27139 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
27142 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
27143 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
27145 enum machine_mode imode
;
27149 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
27151 imode
= GET_MODE_INNER (vmode
);
27152 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
27153 imode
= mode_for_vector (imode
, nelt
);
27156 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
27157 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
27159 emit_move_insn (target
, x
);
27162 /* Expand an extract even operation. */
27165 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
27167 enum machine_mode vmode
= GET_MODE (target
);
27168 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
27171 for (i
= 0; i
< nelt
; i
++)
27172 perm
[i
] = GEN_INT (i
* 2);
27174 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
27177 /* Expand a vector interleave operation. */
27180 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
27182 enum machine_mode vmode
= GET_MODE (target
);
27183 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
27186 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
27187 for (i
= 0; i
< nelt
/ 2; i
++)
27189 perm
[i
* 2] = GEN_INT (i
+ high
);
27190 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
27193 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
27196 /* Return an RTX representing where to find the function value of a
27197 function returning MODE. */
27199 rs6000_complex_function_value (enum machine_mode mode
)
27201 unsigned int regno
;
27203 enum machine_mode inner
= GET_MODE_INNER (mode
);
27204 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
27206 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27207 regno
= FP_ARG_RETURN
;
27210 regno
= GP_ARG_RETURN
;
27212 /* 32-bit is OK since it'll go in r3/r4. */
27213 if (TARGET_32BIT
&& inner_bytes
>= 4)
27214 return gen_rtx_REG (mode
, regno
);
27217 if (inner_bytes
>= 8)
27218 return gen_rtx_REG (mode
, regno
);
27220 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
27222 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
27223 GEN_INT (inner_bytes
));
27224 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
27227 /* Target hook for TARGET_FUNCTION_VALUE.
27229 On the SPE, both FPs and vectors are returned in r3.
27231 On RS/6000 an integer value is in r3 and a floating-point value is in
27232 fp1, unless -msoft-float. */
27235 rs6000_function_value (const_tree valtype
,
27236 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
27237 bool outgoing ATTRIBUTE_UNUSED
)
27239 enum machine_mode mode
;
27240 unsigned int regno
;
27242 /* Special handling for structs in darwin64. */
27244 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
27246 CUMULATIVE_ARGS valcum
;
27250 valcum
.fregno
= FP_ARG_MIN_REG
;
27251 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
27252 /* Do a trial code generation as if this were going to be passed as
27253 an argument; if any part goes in memory, we return NULL. */
27254 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
27257 /* Otherwise fall through to standard ABI rules. */
27260 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
27262 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
27263 return gen_rtx_PARALLEL (DImode
,
27265 gen_rtx_EXPR_LIST (VOIDmode
,
27266 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
27268 gen_rtx_EXPR_LIST (VOIDmode
,
27269 gen_rtx_REG (SImode
,
27270 GP_ARG_RETURN
+ 1),
27273 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
27275 return gen_rtx_PARALLEL (DCmode
,
27277 gen_rtx_EXPR_LIST (VOIDmode
,
27278 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
27280 gen_rtx_EXPR_LIST (VOIDmode
,
27281 gen_rtx_REG (SImode
,
27282 GP_ARG_RETURN
+ 1),
27284 gen_rtx_EXPR_LIST (VOIDmode
,
27285 gen_rtx_REG (SImode
,
27286 GP_ARG_RETURN
+ 2),
27288 gen_rtx_EXPR_LIST (VOIDmode
,
27289 gen_rtx_REG (SImode
,
27290 GP_ARG_RETURN
+ 3),
27294 mode
= TYPE_MODE (valtype
);
27295 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
27296 || POINTER_TYPE_P (valtype
))
27297 mode
= TARGET_32BIT
? SImode
: DImode
;
27299 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27300 /* _Decimal128 must use an even/odd register pair. */
27301 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
27302 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
27303 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
27304 regno
= FP_ARG_RETURN
;
27305 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
27306 && targetm
.calls
.split_complex_arg
)
27307 return rs6000_complex_function_value (mode
);
27308 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27309 return register is used in both cases, and we won't see V2DImode/V2DFmode
27310 for pure altivec, combine the two cases. */
27311 else if (TREE_CODE (valtype
) == VECTOR_TYPE
27312 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
27313 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
27314 regno
= ALTIVEC_ARG_RETURN
;
27315 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
27316 && (mode
== DFmode
|| mode
== DCmode
27317 || mode
== TFmode
|| mode
== TCmode
))
27318 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
27320 regno
= GP_ARG_RETURN
;
27322 return gen_rtx_REG (mode
, regno
);
27325 /* Define how to find the value returned by a library function
27326 assuming the value has mode MODE. */
27328 rs6000_libcall_value (enum machine_mode mode
)
27330 unsigned int regno
;
27332 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
27334 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
27335 return gen_rtx_PARALLEL (DImode
,
27337 gen_rtx_EXPR_LIST (VOIDmode
,
27338 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
27340 gen_rtx_EXPR_LIST (VOIDmode
,
27341 gen_rtx_REG (SImode
,
27342 GP_ARG_RETURN
+ 1),
27346 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27347 /* _Decimal128 must use an even/odd register pair. */
27348 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
27349 else if (SCALAR_FLOAT_MODE_P (mode
)
27350 && TARGET_HARD_FLOAT
&& TARGET_FPRS
27351 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
27352 regno
= FP_ARG_RETURN
;
27353 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27354 return register is used in both cases, and we won't see V2DImode/V2DFmode
27355 for pure altivec, combine the two cases. */
27356 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
27357 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
27358 regno
= ALTIVEC_ARG_RETURN
;
27359 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
27360 return rs6000_complex_function_value (mode
);
27361 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
27362 && (mode
== DFmode
|| mode
== DCmode
27363 || mode
== TFmode
|| mode
== TCmode
))
27364 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
27366 regno
= GP_ARG_RETURN
;
27368 return gen_rtx_REG (mode
, regno
);
27372 /* Given FROM and TO register numbers, say whether this elimination is allowed.
27373 Frame pointer elimination is automatically handled.
27375 For the RS/6000, if frame pointer elimination is being done, we would like
27376 to convert ap into fp, not sp.
27378 We need r30 if -mminimal-toc was specified, and there are constant pool
27382 rs6000_can_eliminate (const int from
, const int to
)
27384 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
27385 ? ! frame_pointer_needed
27386 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
27387 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
27391 /* Define the offset between two registers, FROM to be eliminated and its
27392 replacement TO, at the start of a routine. */
27394 rs6000_initial_elimination_offset (int from
, int to
)
27396 rs6000_stack_t
*info
= rs6000_stack_info ();
27397 HOST_WIDE_INT offset
;
27399 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
27400 offset
= info
->push_p
? 0 : -info
->total_size
;
27401 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
27403 offset
= info
->push_p
? 0 : -info
->total_size
;
27404 if (FRAME_GROWS_DOWNWARD
)
27405 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
27407 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
27408 offset
= FRAME_GROWS_DOWNWARD
27409 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
27411 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
27412 offset
= info
->total_size
;
27413 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
27414 offset
= info
->push_p
? info
->total_size
: 0;
27415 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
27418 gcc_unreachable ();
27424 rs6000_dwarf_register_span (rtx reg
)
27428 unsigned regno
= REGNO (reg
);
27429 enum machine_mode mode
= GET_MODE (reg
);
27433 && (SPE_VECTOR_MODE (GET_MODE (reg
))
27434 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
27435 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
27440 regno
= REGNO (reg
);
27442 /* The duality of the SPE register size wreaks all kinds of havoc.
27443 This is a way of distinguishing r0 in 32-bits from r0 in
27445 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
27446 gcc_assert (words
<= 4);
27447 for (i
= 0; i
< words
; i
++, regno
++)
27449 if (BYTES_BIG_ENDIAN
)
27451 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
27452 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
27456 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
27457 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
27461 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
27464 /* Fill in sizes for SPE register high parts in table used by unwinder. */
27467 rs6000_init_dwarf_reg_sizes_extra (tree address
)
27472 enum machine_mode mode
= TYPE_MODE (char_type_node
);
27473 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
27474 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
27475 rtx value
= gen_int_mode (4, mode
);
27477 for (i
= 1201; i
< 1232; i
++)
27479 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
27480 HOST_WIDE_INT offset
27481 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
27483 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
27488 /* Map internal gcc register numbers to DWARF2 register numbers. */
27491 rs6000_dbx_register_number (unsigned int regno
)
27493 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
27495 if (regno
== LR_REGNO
)
27497 if (regno
== CTR_REGNO
)
27499 if (CR_REGNO_P (regno
))
27500 return regno
- CR0_REGNO
+ 86;
27501 if (regno
== CA_REGNO
)
27502 return 101; /* XER */
27503 if (ALTIVEC_REGNO_P (regno
))
27504 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
27505 if (regno
== VRSAVE_REGNO
)
27507 if (regno
== VSCR_REGNO
)
27509 if (regno
== SPE_ACC_REGNO
)
27511 if (regno
== SPEFSCR_REGNO
)
27513 /* SPE high reg number. We get these values of regno from
27514 rs6000_dwarf_register_span. */
27515 gcc_assert (regno
>= 1200 && regno
< 1232);
27519 /* target hook eh_return_filter_mode */
27520 static enum machine_mode
27521 rs6000_eh_return_filter_mode (void)
27523 return TARGET_32BIT
? SImode
: word_mode
;
27526 /* Target hook for scalar_mode_supported_p. */
27528 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
27530 if (DECIMAL_FLOAT_MODE_P (mode
))
27531 return default_decimal_float_supported_p ();
27533 return default_scalar_mode_supported_p (mode
);
27536 /* Target hook for vector_mode_supported_p. */
27538 rs6000_vector_mode_supported_p (enum machine_mode mode
)
27541 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
27544 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
27547 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
27554 /* Target hook for invalid_arg_for_unprototyped_fn. */
27555 static const char *
27556 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
27558 return (!rs6000_darwin64_abi
27560 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
27561 && (funcdecl
== NULL_TREE
27562 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
27563 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
27564 ? N_("AltiVec argument passed to unprototyped function")
27568 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
27569 setup by using __stack_chk_fail_local hidden function instead of
27570 calling __stack_chk_fail directly. Otherwise it is better to call
27571 __stack_chk_fail directly. */
27573 static tree ATTRIBUTE_UNUSED
27574 rs6000_stack_protect_fail (void)
27576 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
27577 ? default_hidden_stack_protect_fail ()
27578 : default_external_stack_protect_fail ();
27582 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
27583 int num_operands ATTRIBUTE_UNUSED
)
27585 if (rs6000_warn_cell_microcode
)
27588 int insn_code_number
= recog_memoized (insn
);
27589 location_t location
= INSN_LOCATION (insn
);
27591 /* Punt on insns we cannot recognize. */
27592 if (insn_code_number
< 0)
27595 temp
= get_insn_template (insn_code_number
, insn
);
27597 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
27598 warning_at (location
, OPT_mwarn_cell_microcode
,
27599 "emitting microcode insn %s\t[%s] #%d",
27600 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
27601 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
27602 warning_at (location
, OPT_mwarn_cell_microcode
,
27603 "emitting conditional microcode insn %s\t[%s] #%d",
27604 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
27608 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
27611 static unsigned HOST_WIDE_INT
27612 rs6000_asan_shadow_offset (void)
27614 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
27618 /* Mask options that we want to support inside of attribute((target)) and
27619 #pragma GCC target operations. Note, we do not include things like
27620 64/32-bit, endianess, hard/soft floating point, etc. that would have
27621 different calling sequences. */
27623 struct rs6000_opt_mask
{
27624 const char *name
; /* option name */
27625 HOST_WIDE_INT mask
; /* mask to set */
27626 bool invert
; /* invert sense of mask */
27627 bool valid_target
; /* option is a target option */
27630 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
27632 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
27633 { "cmpb", OPTION_MASK_CMPB
, false, true },
27634 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
27635 { "fprnd", OPTION_MASK_FPRND
, false, true },
27636 { "hard-dfp", OPTION_MASK_DFP
, false, true },
27637 { "isel", OPTION_MASK_ISEL
, false, true },
27638 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
27639 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
27640 { "mulhw", OPTION_MASK_MULHW
, false, true },
27641 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
27642 { "update", OPTION_MASK_NO_UPDATE
, true , true },
27643 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
27644 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
27645 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
27646 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
27647 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
27648 { "string", OPTION_MASK_STRING
, false, true },
27649 { "vsx", OPTION_MASK_VSX
, false, true },
27650 #ifdef OPTION_MASK_64BIT
27652 { "aix64", OPTION_MASK_64BIT
, false, false },
27653 { "aix32", OPTION_MASK_64BIT
, true, false },
27655 { "64", OPTION_MASK_64BIT
, false, false },
27656 { "32", OPTION_MASK_64BIT
, true, false },
27659 #ifdef OPTION_MASK_EABI
27660 { "eabi", OPTION_MASK_EABI
, false, false },
27662 #ifdef OPTION_MASK_LITTLE_ENDIAN
27663 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
27664 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
27666 #ifdef OPTION_MASK_RELOCATABLE
27667 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
27669 #ifdef OPTION_MASK_STRICT_ALIGN
27670 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
27672 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
27673 { "string", OPTION_MASK_STRING
, false, false },
27676 /* Builtin mask mapping for printing the flags. */
27677 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
27679 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
27680 { "vsx", RS6000_BTM_VSX
, false, false },
27681 { "spe", RS6000_BTM_SPE
, false, false },
27682 { "paired", RS6000_BTM_PAIRED
, false, false },
27683 { "fre", RS6000_BTM_FRE
, false, false },
27684 { "fres", RS6000_BTM_FRES
, false, false },
27685 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
27686 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
27687 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
27688 { "cell", RS6000_BTM_CELL
, false, false },
27691 /* Option variables that we want to support inside attribute((target)) and
27692 #pragma GCC target operations. */
27694 struct rs6000_opt_var
{
27695 const char *name
; /* option name */
27696 size_t global_offset
; /* offset of the option in global_options. */
27697 size_t target_offset
; /* offset of the option in target optiosn. */
27700 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
27703 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
27704 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
27705 { "avoid-indexed-addresses",
27706 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
27707 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
27709 offsetof (struct gcc_options
, x_rs6000_paired_float
),
27710 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
27712 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
27713 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
27716 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27717 parsing. Return true if there were no errors. */
27720 rs6000_inner_target_options (tree args
, bool attr_p
)
27724 if (args
== NULL_TREE
)
27727 else if (TREE_CODE (args
) == STRING_CST
)
27729 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
27732 while ((q
= strtok (p
, ",")) != NULL
)
27734 bool error_p
= false;
27735 bool not_valid_p
= false;
27736 const char *cpu_opt
= NULL
;
27739 if (strncmp (q
, "cpu=", 4) == 0)
27741 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
27742 if (cpu_index
>= 0)
27743 rs6000_cpu_index
= cpu_index
;
27750 else if (strncmp (q
, "tune=", 5) == 0)
27752 int tune_index
= rs6000_cpu_name_lookup (q
+5);
27753 if (tune_index
>= 0)
27754 rs6000_tune_index
= tune_index
;
27764 bool invert
= false;
27768 if (strncmp (r
, "no-", 3) == 0)
27774 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
27775 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
27777 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
27779 if (!rs6000_opt_masks
[i
].valid_target
)
27780 not_valid_p
= true;
27784 rs6000_isa_flags_explicit
|= mask
;
27786 /* VSX needs altivec, so -mvsx automagically sets
27788 if (mask
== OPTION_MASK_VSX
&& !invert
)
27789 mask
|= OPTION_MASK_ALTIVEC
;
27791 if (rs6000_opt_masks
[i
].invert
)
27795 rs6000_isa_flags
&= ~mask
;
27797 rs6000_isa_flags
|= mask
;
27802 if (error_p
&& !not_valid_p
)
27804 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
27805 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
27807 size_t j
= rs6000_opt_vars
[i
].global_offset
;
27808 *((int *) ((char *)&global_options
+ j
)) = !invert
;
27817 const char *eprefix
, *esuffix
;
27822 eprefix
= "__attribute__((__target__(";
27827 eprefix
= "#pragma GCC target ";
27832 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
27834 else if (not_valid_p
)
27835 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
27837 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
27842 else if (TREE_CODE (args
) == TREE_LIST
)
27846 tree value
= TREE_VALUE (args
);
27849 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
27853 args
= TREE_CHAIN (args
);
27855 while (args
!= NULL_TREE
);
27859 gcc_unreachable ();
27864 /* Print out the target options as a list for -mdebug=target. */
27867 rs6000_debug_target_options (tree args
, const char *prefix
)
27869 if (args
== NULL_TREE
)
27870 fprintf (stderr
, "%s<NULL>", prefix
);
27872 else if (TREE_CODE (args
) == STRING_CST
)
27874 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
27877 while ((q
= strtok (p
, ",")) != NULL
)
27880 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
27885 else if (TREE_CODE (args
) == TREE_LIST
)
27889 tree value
= TREE_VALUE (args
);
27892 rs6000_debug_target_options (value
, prefix
);
27895 args
= TREE_CHAIN (args
);
27897 while (args
!= NULL_TREE
);
27901 gcc_unreachable ();
27907 /* Hook to validate attribute((target("..."))). */
27910 rs6000_valid_attribute_p (tree fndecl
,
27911 tree
ARG_UNUSED (name
),
27915 struct cl_target_option cur_target
;
27917 tree old_optimize
= build_optimization_node ();
27918 tree new_target
, new_optimize
;
27919 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
27921 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
27923 if (TARGET_DEBUG_TARGET
)
27925 tree tname
= DECL_NAME (fndecl
);
27926 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
27928 fprintf (stderr
, "function: %.*s\n",
27929 (int) IDENTIFIER_LENGTH (tname
),
27930 IDENTIFIER_POINTER (tname
));
27932 fprintf (stderr
, "function: unknown\n");
27934 fprintf (stderr
, "args:");
27935 rs6000_debug_target_options (args
, " ");
27936 fprintf (stderr
, "\n");
27939 fprintf (stderr
, "flags: 0x%x\n", flags
);
27941 fprintf (stderr
, "--------------------\n");
27944 old_optimize
= build_optimization_node ();
27945 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
27947 /* If the function changed the optimization levels as well as setting target
27948 options, start with the optimizations specified. */
27949 if (func_optimize
&& func_optimize
!= old_optimize
)
27950 cl_optimization_restore (&global_options
,
27951 TREE_OPTIMIZATION (func_optimize
));
27953 /* The target attributes may also change some optimization flags, so update
27954 the optimization options if necessary. */
27955 cl_target_option_save (&cur_target
, &global_options
);
27956 rs6000_cpu_index
= rs6000_tune_index
= -1;
27957 ret
= rs6000_inner_target_options (args
, true);
27959 /* Set up any additional state. */
27962 ret
= rs6000_option_override_internal (false);
27963 new_target
= build_target_option_node ();
27968 new_optimize
= build_optimization_node ();
27975 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
27977 if (old_optimize
!= new_optimize
)
27978 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
27981 cl_target_option_restore (&global_options
, &cur_target
);
27983 if (old_optimize
!= new_optimize
)
27984 cl_optimization_restore (&global_options
,
27985 TREE_OPTIMIZATION (old_optimize
));
27991 /* Hook to validate the current #pragma GCC target and set the state, and
27992 update the macros based on what was changed. If ARGS is NULL, then
27993 POP_TARGET is used to reset the options. */
27996 rs6000_pragma_target_parse (tree args
, tree pop_target
)
27998 tree prev_tree
= build_target_option_node ();
28000 struct cl_target_option
*prev_opt
, *cur_opt
;
28001 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
28002 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
28004 if (TARGET_DEBUG_TARGET
)
28006 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
28007 fprintf (stderr
, "args:");
28008 rs6000_debug_target_options (args
, " ");
28009 fprintf (stderr
, "\n");
28013 fprintf (stderr
, "pop_target:\n");
28014 debug_tree (pop_target
);
28017 fprintf (stderr
, "pop_target: <NULL>\n");
28019 fprintf (stderr
, "--------------------\n");
28024 cur_tree
= ((pop_target
)
28026 : target_option_default_node
);
28027 cl_target_option_restore (&global_options
,
28028 TREE_TARGET_OPTION (cur_tree
));
28032 rs6000_cpu_index
= rs6000_tune_index
= -1;
28033 if (!rs6000_inner_target_options (args
, false)
28034 || !rs6000_option_override_internal (false)
28035 || (cur_tree
= build_target_option_node ()) == NULL_TREE
)
28037 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
28038 fprintf (stderr
, "invalid pragma\n");
28044 target_option_current_node
= cur_tree
;
28046 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
28047 change the macros that are defined. */
28048 if (rs6000_target_modify_macros_ptr
)
28050 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
28051 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
28052 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
28054 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
28055 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
28056 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
28058 diff_bumask
= (prev_bumask
^ cur_bumask
);
28059 diff_flags
= (prev_flags
^ cur_flags
);
28061 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
28063 /* Delete old macros. */
28064 rs6000_target_modify_macros_ptr (false,
28065 prev_flags
& diff_flags
,
28066 prev_bumask
& diff_bumask
);
28068 /* Define new macros. */
28069 rs6000_target_modify_macros_ptr (true,
28070 cur_flags
& diff_flags
,
28071 cur_bumask
& diff_bumask
);
28079 /* Remember the last target of rs6000_set_current_function. */
28080 static GTY(()) tree rs6000_previous_fndecl
;
28082 /* Establish appropriate back-end context for processing the function
28083 FNDECL. The argument might be NULL to indicate processing at top
28084 level, outside of any function scope. */
28086 rs6000_set_current_function (tree fndecl
)
28088 tree old_tree
= (rs6000_previous_fndecl
28089 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
28092 tree new_tree
= (fndecl
28093 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
28096 if (TARGET_DEBUG_TARGET
)
28098 bool print_final
= false;
28099 fprintf (stderr
, "\n==================== rs6000_set_current_function");
28102 fprintf (stderr
, ", fndecl %s (%p)",
28103 (DECL_NAME (fndecl
)
28104 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
28105 : "<unknown>"), (void *)fndecl
);
28107 if (rs6000_previous_fndecl
)
28108 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
28110 fprintf (stderr
, "\n");
28113 fprintf (stderr
, "\nnew fndecl target specific options:\n");
28114 debug_tree (new_tree
);
28115 print_final
= true;
28120 fprintf (stderr
, "\nold fndecl target specific options:\n");
28121 debug_tree (old_tree
);
28122 print_final
= true;
28126 fprintf (stderr
, "--------------------\n");
28129 /* Only change the context if the function changes. This hook is called
28130 several times in the course of compiling a function, and we don't want to
28131 slow things down too much or call target_reinit when it isn't safe. */
28132 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
28134 rs6000_previous_fndecl
= fndecl
;
28135 if (old_tree
== new_tree
)
28140 cl_target_option_restore (&global_options
,
28141 TREE_TARGET_OPTION (new_tree
));
28147 struct cl_target_option
*def
28148 = TREE_TARGET_OPTION (target_option_current_node
);
28150 cl_target_option_restore (&global_options
, def
);
28157 /* Save the current options */
28160 rs6000_function_specific_save (struct cl_target_option
*ptr
)
28162 ptr
->x_rs6000_isa_flags
= rs6000_isa_flags
;
28163 ptr
->x_rs6000_isa_flags_explicit
= rs6000_isa_flags_explicit
;
28166 /* Restore the current options */
28169 rs6000_function_specific_restore (struct cl_target_option
*ptr
)
28171 rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
28172 rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
28173 (void) rs6000_option_override_internal (false);
28176 /* Print the current options */
28179 rs6000_function_specific_print (FILE *file
, int indent
,
28180 struct cl_target_option
*ptr
)
28182 rs6000_print_isa_options (file
, indent
, "Isa options set",
28183 ptr
->x_rs6000_isa_flags
);
28185 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
28186 ptr
->x_rs6000_isa_flags_explicit
);
28189 /* Helper function to print the current isa or misc options on a line. */
28192 rs6000_print_options_internal (FILE *file
,
28194 const char *string
,
28195 HOST_WIDE_INT flags
,
28196 const char *prefix
,
28197 const struct rs6000_opt_mask
*opts
,
28198 size_t num_elements
)
28201 size_t start_column
= 0;
28203 size_t max_column
= 76;
28204 const char *comma
= "";
28205 const char *nl
= "\n";
28208 start_column
+= fprintf (file
, "%*s", indent
, "");
28212 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
28216 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
28218 /* Print the various mask options. */
28219 cur_column
= start_column
;
28220 for (i
= 0; i
< num_elements
; i
++)
28222 if ((flags
& opts
[i
].mask
) != 0)
28224 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
28225 size_t len
= (strlen (comma
)
28228 + strlen (rs6000_opt_masks
[i
].name
));
28231 if (cur_column
> max_column
)
28233 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
28234 cur_column
= start_column
+ len
;
28239 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
28240 rs6000_opt_masks
[i
].name
);
28241 flags
&= ~ opts
[i
].mask
;
28249 /* Helper function to print the current isa options on a line. */
28252 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
28253 HOST_WIDE_INT flags
)
28255 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
28256 &rs6000_opt_masks
[0],
28257 ARRAY_SIZE (rs6000_opt_masks
));
28261 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
28262 HOST_WIDE_INT flags
)
28264 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
28265 &rs6000_builtin_mask_names
[0],
28266 ARRAY_SIZE (rs6000_builtin_mask_names
));
28270 /* Hook to determine if one function can safely inline another. */
28273 rs6000_can_inline_p (tree caller
, tree callee
)
28276 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
28277 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
28279 /* If callee has no option attributes, then it is ok to inline. */
28283 /* If caller has no option attributes, but callee does then it is not ok to
28285 else if (!caller_tree
)
28290 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
28291 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
28293 /* Callee's options should a subset of the caller's, i.e. a vsx function
28294 can inline an altivec function but a non-vsx function can't inline a
28296 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
28297 == callee_opts
->x_rs6000_isa_flags
)
28301 if (TARGET_DEBUG_TARGET
)
28302 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
28303 (DECL_NAME (caller
)
28304 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
28306 (DECL_NAME (callee
)
28307 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
28309 (ret
? "can" : "cannot"));
28314 /* Allocate a stack temp and fixup the address so it meets the particular
28315 memory requirements (either offetable or REG+REG addressing). */
28318 rs6000_allocate_stack_temp (enum machine_mode mode
,
28319 bool offsettable_p
,
28322 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
28323 rtx addr
= XEXP (stack
, 0);
28324 int strict_p
= (reload_in_progress
|| reload_completed
);
28326 if (!legitimate_indirect_address_p (addr
, strict_p
))
28329 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
28330 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
28332 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
28333 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
28339 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
28340 to such a form to deal with memory reference instructions like STFIWX that
28341 only take reg+reg addressing. */
28344 rs6000_address_for_fpconvert (rtx x
)
28346 int strict_p
= (reload_in_progress
|| reload_completed
);
28349 gcc_assert (MEM_P (x
));
28350 addr
= XEXP (x
, 0);
28351 if (! legitimate_indirect_address_p (addr
, strict_p
)
28352 && ! legitimate_indexed_address_p (addr
, strict_p
))
28354 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
28356 rtx reg
= XEXP (addr
, 0);
28357 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
28358 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
28359 gcc_assert (REG_P (reg
));
28360 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
28363 else if (GET_CODE (addr
) == PRE_MODIFY
)
28365 rtx reg
= XEXP (addr
, 0);
28366 rtx expr
= XEXP (addr
, 1);
28367 gcc_assert (REG_P (reg
));
28368 gcc_assert (GET_CODE (expr
) == PLUS
);
28369 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
28373 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
28379 /* Given a memory reference, if it is not in the form for altivec memory
28380 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
28381 convert to the altivec format. */
28384 rs6000_address_for_altivec (rtx x
)
28386 gcc_assert (MEM_P (x
));
28387 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
28389 rtx addr
= XEXP (x
, 0);
28390 int strict_p
= (reload_in_progress
|| reload_completed
);
28392 if (!legitimate_indexed_address_p (addr
, strict_p
)
28393 && !legitimate_indirect_address_p (addr
, strict_p
))
28394 addr
= copy_to_mode_reg (Pmode
, addr
);
28396 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
28397 x
= change_address (x
, GET_MODE (x
), addr
);
28403 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
28405 On the RS/6000, all integer constants are acceptable, most won't be valid
28406 for particular insns, though. Only easy FP constants are acceptable. */
28409 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
28411 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
28414 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
28415 || GET_MODE (x
) == VOIDmode
28416 || (TARGET_POWERPC64
&& mode
== DImode
)
28417 || easy_fp_constant (x
, mode
)
28418 || easy_vector_constant (x
, mode
));
28422 /* A function pointer under AIX is a pointer to a data area whose first word
28423 contains the actual address of the function, whose second word contains a
28424 pointer to its TOC, and whose third word contains a value to place in the
28425 static chain register (r11). Note that if we load the static chain, our
28426 "trampoline" need not have any executable code. */
28429 rs6000_call_indirect_aix (rtx value
, rtx func_desc
, rtx flag
)
28435 rtx stack_toc_offset
;
28437 rtx func_toc_offset
;
28439 rtx func_sc_offset
;
28442 rtx (*call_func
) (rtx
, rtx
, rtx
, rtx
);
28443 rtx (*call_value_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
28445 stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
28446 toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
28448 /* Load up address of the actual function. */
28449 func_desc
= force_reg (Pmode
, func_desc
);
28450 func_addr
= gen_reg_rtx (Pmode
);
28451 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
28456 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_32BIT
);
28457 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_32BIT
);
28458 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_32BIT
);
28459 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28461 call_func
= gen_call_indirect_aix32bit
;
28462 call_value_func
= gen_call_value_indirect_aix32bit
;
28466 call_func
= gen_call_indirect_aix32bit_nor11
;
28467 call_value_func
= gen_call_value_indirect_aix32bit_nor11
;
28472 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_64BIT
);
28473 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_64BIT
);
28474 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_64BIT
);
28475 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28477 call_func
= gen_call_indirect_aix64bit
;
28478 call_value_func
= gen_call_value_indirect_aix64bit
;
28482 call_func
= gen_call_indirect_aix64bit_nor11
;
28483 call_value_func
= gen_call_value_indirect_aix64bit_nor11
;
28487 /* Reserved spot to store the TOC. */
28488 stack_toc_mem
= gen_frame_mem (Pmode
,
28489 gen_rtx_PLUS (Pmode
,
28491 stack_toc_offset
));
28494 gcc_assert (cfun
->machine
);
28496 /* Can we optimize saving the TOC in the prologue or do we need to do it at
28498 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
28499 cfun
->machine
->save_toc_in_prologue
= true;
28503 MEM_VOLATILE_P (stack_toc_mem
) = 1;
28504 emit_move_insn (stack_toc_mem
, toc_reg
);
28507 /* Calculate the address to load the TOC of the called function. We don't
28508 actually load this until the split after reload. */
28509 func_toc_mem
= gen_rtx_MEM (Pmode
,
28510 gen_rtx_PLUS (Pmode
,
28514 /* If we have a static chain, load it up. */
28515 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28517 func_sc_mem
= gen_rtx_MEM (Pmode
,
28518 gen_rtx_PLUS (Pmode
,
28522 sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
28523 emit_move_insn (sc_reg
, func_sc_mem
);
28526 /* Create the call. */
28528 insn
= call_value_func (value
, func_addr
, flag
, func_toc_mem
,
28531 insn
= call_func (func_addr
, flag
, func_toc_mem
, stack_toc_mem
);
28533 emit_call_insn (insn
);
28536 /* Return whether we need to always update the saved TOC pointer when we update
28537 the stack pointer. */
28540 rs6000_save_toc_in_prologue_p (void)
28542 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
28545 #ifdef HAVE_GAS_HIDDEN
28546 # define USE_HIDDEN_LINKONCE 1
28548 # define USE_HIDDEN_LINKONCE 0
28551 /* Fills in the label name that should be used for a 476 link stack thunk. */
28554 get_ppc476_thunk_name (char name
[32])
28556 gcc_assert (TARGET_LINK_STACK
);
28558 if (USE_HIDDEN_LINKONCE
)
28559 sprintf (name
, "__ppc476.get_thunk");
28561 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
28564 /* This function emits the simple thunk routine that is used to preserve
28565 the link stack on the 476 cpu. */
28567 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
28569 rs6000_code_end (void)
28574 if (!TARGET_LINK_STACK
)
28577 get_ppc476_thunk_name (name
);
28579 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
28580 build_function_type_list (void_type_node
, NULL_TREE
));
28581 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
28582 NULL_TREE
, void_type_node
);
28583 TREE_PUBLIC (decl
) = 1;
28584 TREE_STATIC (decl
) = 1;
28587 if (USE_HIDDEN_LINKONCE
)
28589 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
28590 targetm
.asm_out
.unique_section (decl
, 0);
28591 switch_to_section (get_named_section (decl
, NULL
, 0));
28592 DECL_WEAK (decl
) = 1;
28593 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
28594 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
28595 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
28596 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
28601 switch_to_section (text_section
);
28602 ASM_OUTPUT_LABEL (asm_out_file
, name
);
28605 DECL_INITIAL (decl
) = make_node (BLOCK
);
28606 current_function_decl
= decl
;
28607 init_function_start (decl
);
28608 first_function_block_is_cold
= false;
28609 /* Make sure unwind info is emitted for the thunk if needed. */
28610 final_start_function (emit_barrier (), asm_out_file
, 1);
28612 fputs ("\tblr\n", asm_out_file
);
28614 final_end_function ();
28615 init_insn_lengths ();
28616 free_after_compilation (cfun
);
28618 current_function_decl
= NULL
;
28621 /* Add r30 to hard reg set if the prologue sets it up and it is not
28622 pic_offset_table_rtx. */
28625 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
28627 if (!TARGET_SINGLE_PIC_BASE
28629 && TARGET_MINIMAL_TOC
28630 && get_pool_size () != 0)
28631 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
28634 struct gcc_target targetm
= TARGET_INITIALIZER
;
28636 #include "gt-rs6000.h"