1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
30 #include "insn-config.h"
37 #include "addresses.h"
38 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 struct target_reload default_target_reload
;
85 struct target_reload
*this_target_reload
= &default_target_reload
;
88 #define spill_indirect_levels \
89 (this_target_reload->x_spill_indirect_levels)
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx
*reg_last_reload_reg
;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static regset_head reg_has_output_reload
;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload
;
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static unsigned int *reg_max_ref_width
;
106 /* Vector to remember old contents of reg_renumber before spilling. */
107 static short *reg_old_renumber
;
109 /* During reload_as_needed, element N contains the last pseudo regno reloaded
110 into hard register N. If that pseudo reg occupied more than one register,
111 reg_reloaded_contents points to that pseudo for each spill register in
112 use; all of these must remain set for an inheritance to occur. */
113 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
115 /* During reload_as_needed, element N contains the insn for which
116 hard register N was last used. Its contents are significant only
117 when reg_reloaded_valid is set for this register. */
118 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
120 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
121 static HARD_REG_SET reg_reloaded_valid
;
122 /* Indicate if the register was dead at the end of the reload.
123 This is only valid if reg_reloaded_contents is set and valid. */
124 static HARD_REG_SET reg_reloaded_dead
;
126 /* Indicate whether the register's current value is one that is not
127 safe to retain across a call, even for registers that are normally
128 call-saved. This is only meaningful for members of reg_reloaded_valid. */
129 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
131 /* Number of spill-regs so far; number of valid elements of spill_regs. */
134 /* In parallel with spill_regs, contains REG rtx's for those regs.
135 Holds the last rtx used for any given reg, or 0 if it has never
136 been used for spilling yet. This rtx is reused, provided it has
138 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
140 /* In parallel with spill_regs, contains nonzero for a spill reg
141 that was stored after the last time it was used.
142 The precise value is the insn generated to do the store. */
143 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
145 /* This is the register that was stored with spill_reg_store. This is a
146 copy of reload_out / reload_out_reg when the value was stored; if
147 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
148 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
150 /* This table is the inverse mapping of spill_regs:
151 indexed by hard reg number,
152 it contains the position of that reg in spill_regs,
153 or -1 for something that is not in spill_regs.
155 ?!? This is no longer accurate. */
156 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
158 /* This reg set indicates registers that can't be used as spill registers for
159 the currently processed insn. These are the hard registers which are live
160 during the insn, but not allocated to pseudos, as well as fixed
162 static HARD_REG_SET bad_spill_regs
;
164 /* These are the hard registers that can't be used as spill register for any
165 insn. This includes registers used for user variables and registers that
166 we can't eliminate. A register that appears in this set also can't be used
167 to retry register allocation. */
168 static HARD_REG_SET bad_spill_regs_global
;
170 /* Describes order of use of registers for reloading
171 of spilled pseudo-registers. `n_spills' is the number of
172 elements that are actually valid; new ones are added at the end.
174 Both spill_regs and spill_reg_order are used on two occasions:
175 once during find_reload_regs, where they keep track of the spill registers
176 for a single insn, but also during reload_as_needed where they show all
177 the registers ever used by reload. For the latter case, the information
178 is calculated during finish_spills. */
179 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
181 /* This vector of reg sets indicates, for each pseudo, which hard registers
182 may not be used for retrying global allocation because the register was
183 formerly spilled from one of them. If we allowed reallocating a pseudo to
184 a register that it was already allocated to, reload might not
186 static HARD_REG_SET
*pseudo_previous_regs
;
188 /* This vector of reg sets indicates, for each pseudo, which hard
189 registers may not be used for retrying global allocation because they
190 are used as spill registers during one of the insns in which the
192 static HARD_REG_SET
*pseudo_forbidden_regs
;
194 /* All hard regs that have been used as spill registers for any insn are
195 marked in this set. */
196 static HARD_REG_SET used_spill_regs
;
198 /* Index of last register assigned as a spill register. We allocate in
199 a round-robin fashion. */
200 static int last_spill_reg
;
202 /* Record the stack slot for each spilled hard register. */
203 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
205 /* Width allocated so far for that stack slot. */
206 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
208 /* Record which pseudos needed to be spilled. */
209 static regset_head spilled_pseudos
;
211 /* Record which pseudos changed their allocation in finish_spills. */
212 static regset_head changed_allocation_pseudos
;
214 /* Used for communication between order_regs_for_reload and count_pseudo.
215 Used to avoid counting one pseudo twice. */
216 static regset_head pseudos_counted
;
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid
;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
224 int caller_save_needed
;
226 /* Set to 1 while reload_as_needed is operating.
227 Required by some machines to handle any generated moves differently. */
228 int reload_in_progress
= 0;
230 /* This obstack is used for allocation of rtl during register elimination.
231 The allocated storage can be freed once find_reloads has processed the
233 static struct obstack reload_obstack
;
235 /* Points to the beginning of the reload_obstack. All insn_chain structures
236 are allocated first. */
237 static char *reload_startobj
;
239 /* The point after all insn_chain structures. Used to quickly deallocate
240 memory allocated in copy_reloads during calculate_needs_all_insns. */
241 static char *reload_firstobj
;
243 /* This points before all local rtl generated by register elimination.
244 Used to quickly free all memory after processing one insn. */
245 static char *reload_insn_firstobj
;
247 /* List of insn_chain instructions, one for every insn that reload needs to
249 struct insn_chain
*reload_insn_chain
;
251 /* TRUE if we potentially left dead insns in the insn stream and want to
252 run DCE immediately after reload, FALSE otherwise. */
253 static bool need_dce
;
255 /* List of all insns needing reloads. */
256 static struct insn_chain
*insns_need_reload
;
258 /* This structure is used to record information about register eliminations.
259 Each array entry describes one possible way of eliminating a register
260 in favor of another. If there is more than one way of eliminating a
261 particular register, the most preferred should be specified first. */
265 int from
; /* Register number to be eliminated. */
266 int to
; /* Register number used as replacement. */
267 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
268 int can_eliminate
; /* Nonzero if this elimination can be done. */
269 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
270 target hook in previous scan over insns
272 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
273 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
274 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
275 rtx from_rtx
; /* REG rtx for the register to be eliminated.
276 We cannot simply compare the number since
277 we might then spuriously replace a hard
278 register corresponding to a pseudo
279 assigned to the reg to be eliminated. */
280 rtx to_rtx
; /* REG rtx for the replacement. */
283 static struct elim_table
*reg_eliminate
= 0;
285 /* This is an intermediate structure to initialize the table. It has
286 exactly the members provided by ELIMINABLE_REGS. */
287 static const struct elim_table_1
291 } reg_eliminate_1
[] =
293 /* If a set of eliminable registers was specified, define the table from it.
294 Otherwise, default to the normal case of the frame pointer being
295 replaced by the stack pointer. */
297 #ifdef ELIMINABLE_REGS
300 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
303 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
305 /* Record the number of pending eliminations that have an offset not equal
306 to their initial offset. If nonzero, we use a new copy of each
307 replacement result in any insns encountered. */
308 int num_not_at_initial_offset
;
310 /* Count the number of registers that we may be able to eliminate. */
311 static int num_eliminable
;
312 /* And the number of registers that are equivalent to a constant that
313 can be eliminated to frame_pointer / arg_pointer + constant. */
314 static int num_eliminable_invariants
;
316 /* For each label, we record the offset of each elimination. If we reach
317 a label by more than one path and an offset differs, we cannot do the
318 elimination. This information is indexed by the difference of the
319 number of the label and the first label number. We can't offset the
320 pointer itself as this can cause problems on machines with segmented
321 memory. The first table is an array of flags that records whether we
322 have yet encountered a label and the second table is an array of arrays,
323 one entry in the latter array for each elimination. */
325 static int first_label_num
;
326 static char *offsets_known_at
;
327 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
329 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
331 /* Stack of addresses where an rtx has been changed. We can undo the
332 changes by popping items off the stack and restoring the original
333 value at each location.
335 We use this simplistic undo capability rather than copy_rtx as copy_rtx
336 will not make a deep copy of a normally sharable rtx, such as
337 (const (plus (symbol_ref) (const_int))). If such an expression appears
338 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
339 rtx expression would be changed. See PR 42431. */
342 static vec
<rtx_p
> substitute_stack
;
344 /* Number of labels in the current function. */
346 static int num_labels
;
348 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain
*);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain
*, int);
353 static void find_reload_regs (struct insn_chain
*);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx
, enum reg_class
);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx
);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx
, rtx
, int);
362 static void check_eliminable_occurrences (rtx
);
363 static void elimination_effects (rtx
, enum machine_mode
);
364 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
365 static int eliminate_regs_in_insn (rtx
, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx
, const_rtx
, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx
);
372 static void init_eliminable_invariants (rtx
, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET
*);
376 static bool update_eliminables_and_spill (void);
377 static void elimination_costs_in_insn (rtx
);
378 static void spill_hard_reg (unsigned int, int);
379 static int finish_spills (int);
380 static void scan_paradoxical_subregs (rtx
);
381 static void count_pseudo (int);
382 static void order_regs_for_reload (struct insn_chain
*);
383 static void reload_as_needed (int);
384 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
385 static void forget_marked_reloads (regset
);
386 static int reload_reg_class_lower (const void *, const void *);
387 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
389 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
391 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
392 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
394 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
396 static int allocate_reload_reg (struct insn_chain
*, int, int);
397 static int conflicts_with_override (rtx
);
398 static void failed_reload (rtx
, int);
399 static int set_reload_reg (int, int);
400 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
401 static void choose_reload_regs (struct insn_chain
*);
402 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
404 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
406 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
407 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
408 static void emit_reload_insns (struct insn_chain
*);
409 static void delete_output_reload (rtx
, int, int, rtx
);
410 static void delete_address_reloads (rtx
, rtx
);
411 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
412 static void inc_for_reload (rtx
, rtx
, rtx
, int);
414 static void add_auto_inc_notes (rtx
, rtx
);
416 static void substitute (rtx
*, const_rtx
, rtx
);
417 static bool gen_reload_chain_without_interm_reg_p (int, int);
418 static int reloads_conflict (int, int);
419 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
420 static rtx
emit_insn_if_valid_for_reload (rtx
);
422 /* Initialize the reload pass. This is called at the beginning of compilation
423 and may be called again if the target is reinitialized. */
430 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
431 Set spill_indirect_levels to the number of levels such addressing is
432 permitted, zero if it is not permitted at all. */
435 = gen_rtx_MEM (Pmode
,
438 LAST_VIRTUAL_REGISTER
+ 1),
439 gen_int_mode (4, Pmode
)));
440 spill_indirect_levels
= 0;
442 while (memory_address_p (QImode
, tem
))
444 spill_indirect_levels
++;
445 tem
= gen_rtx_MEM (Pmode
, tem
);
448 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
450 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
451 indirect_symref_ok
= memory_address_p (QImode
, tem
);
453 /* See if reg+reg is a valid (and offsettable) address. */
455 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
457 tem
= gen_rtx_PLUS (Pmode
,
458 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
459 gen_rtx_REG (Pmode
, i
));
461 /* This way, we make sure that reg+reg is an offsettable address. */
462 tem
= plus_constant (Pmode
, tem
, 4);
464 if (memory_address_p (QImode
, tem
))
466 double_reg_address_ok
= 1;
471 /* Initialize obstack for our rtl allocation. */
472 if (reload_startobj
== NULL
)
474 gcc_obstack_init (&reload_obstack
);
475 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
478 INIT_REG_SET (&spilled_pseudos
);
479 INIT_REG_SET (&changed_allocation_pseudos
);
480 INIT_REG_SET (&pseudos_counted
);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain
*unused_insn_chains
= 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain
*c
;
492 if (unused_insn_chains
== 0)
494 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
495 INIT_REG_SET (&c
->live_throughout
);
496 INIT_REG_SET (&c
->dead_or_set
);
500 c
= unused_insn_chains
;
501 unused_insn_chains
= c
->next
;
503 c
->is_caller_save_insn
= 0;
504 c
->need_operand_change
= 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
517 reg_set_iterator rsi
;
519 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
521 int r
= reg_renumber
[regno
];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p
|| reload_completed
);
532 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
553 unsigned int regno
= REGNO (x
);
555 if (regno
< FIRST_PSEUDO_REGISTER
)
558 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
562 replace_pseudos_in (loc
, mem_mode
, usage
);
566 if (reg_equiv_constant (regno
))
567 *loc
= reg_equiv_constant (regno
);
568 else if (reg_equiv_invariant (regno
))
569 *loc
= reg_equiv_invariant (regno
);
570 else if (reg_equiv_mem (regno
))
571 *loc
= reg_equiv_mem (regno
);
572 else if (reg_equiv_address (regno
))
573 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
576 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
577 || REGNO (regno_reg_rtx
[regno
]) != regno
);
578 *loc
= regno_reg_rtx
[regno
];
583 else if (code
== MEM
)
585 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
589 /* Process each of our operands recursively. */
590 fmt
= GET_RTX_FORMAT (code
);
591 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
593 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
594 else if (*fmt
== 'E')
595 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
596 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block
*tos
, *worklist
, bb
;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
616 FOR_EACH_BB_FN (bb
, cfun
)
617 bb
->flags
&= ~BB_REACHABLE
;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
621 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos
!= worklist
)
628 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
629 if (!(e
->flags
& EDGE_ABNORMAL
))
631 basic_block src
= e
->src
;
633 if (!(src
->flags
& BB_REACHABLE
))
635 src
->flags
|= BB_REACHABLE
;
642 /* Now see if there's a reachable block with an exceptional incoming
644 FOR_EACH_BB_FN (bb
, cfun
)
645 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size
= vec_safe_length (reg_equivs
);
660 int max_regno
= max_reg_num ();
664 memset (&ze
, 0, sizeof (reg_equivs_t
));
665 vec_safe_reserve (reg_equivs
, max_regno
);
666 for (i
= old_size
; i
< max_regno
; i
++)
667 reg_equivs
->quick_insert (i
, ze
);
671 /* Global variables used by reload and its subroutines. */
673 /* The current basic block while in calculate_elim_costs_all_insns. */
674 static basic_block elim_bb
;
676 /* Set during calculate_needs if an insn needs register elimination. */
677 static int something_needs_elimination
;
678 /* Set during calculate_needs if an insn needs an operand changed. */
679 static int something_needs_operands_changed
;
680 /* Set by alter_regs if we spilled a register to the stack. */
681 static bool something_was_spilled
;
683 /* Nonzero means we couldn't get enough spill regs. */
686 /* Temporary array of pseudo-register number. */
687 static int *temp_pseudo_reg_arr
;
689 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
690 If that insn didn't set the register (i.e., it copied the register to
691 memory), just delete that insn instead of the equivalencing insn plus
692 anything now dead. If we call delete_dead_insn on that insn, we may
693 delete the insn that actually sets the register if the register dies
694 there and that is incorrect. */
698 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
700 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
703 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
705 rtx equiv_insn
= XEXP (list
, 0);
707 /* If we already deleted the insn or if it may trap, we can't
708 delete it. The latter case shouldn't happen, but can
709 if an insn has a variable address, gets a REG_EH_REGION
710 note added to it, and then gets converted into a load
711 from a constant address. */
712 if (NOTE_P (equiv_insn
)
713 || can_throw_internal (equiv_insn
))
715 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
716 delete_dead_insn (equiv_insn
);
718 SET_INSN_DELETED (equiv_insn
);
724 /* Return true if remove_init_insns will delete INSN. */
726 will_delete_init_insn_p (rtx insn
)
728 rtx set
= single_set (insn
);
729 if (!set
|| !REG_P (SET_DEST (set
)))
731 unsigned regno
= REGNO (SET_DEST (set
));
733 if (can_throw_internal (insn
))
736 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
739 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
741 rtx equiv_insn
= XEXP (list
, 0);
742 if (equiv_insn
== insn
)
748 /* Main entry point for the reload pass.
750 FIRST is the first insn of the function being compiled.
752 GLOBAL nonzero means we were called from global_alloc
753 and should attempt to reallocate any pseudoregs that we
754 displace from hard regs we will use for reloads.
755 If GLOBAL is zero, we do not have enough information to do that,
756 so any pseudo reg that is spilled must go to the stack.
758 Return value is TRUE if reload likely left dead insns in the
759 stream and a DCE pass should be run to elimiante them. Else the
760 return value is FALSE. */
763 reload (rtx first
, int global
)
767 struct elim_table
*ep
;
771 /* Make sure even insns with volatile mem refs are recognizable. */
776 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
778 /* Make sure that the last insn in the chain
779 is not something that needs reloading. */
780 emit_note (NOTE_INSN_DELETED
);
782 /* Enable find_equiv_reg to distinguish insns made by reload. */
783 reload_first_uid
= get_max_uid ();
785 #ifdef SECONDARY_MEMORY_NEEDED
786 /* Initialize the secondary memory table. */
787 clear_secondary_mem ();
790 /* We don't have a stack slot for any spill reg yet. */
791 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
792 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
794 /* Initialize the save area information for caller-save, in case some
798 /* Compute which hard registers are now in use
799 as homes for pseudo registers.
800 This is done here rather than (eg) in global_alloc
801 because this point is reached even if not optimizing. */
802 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
805 /* A function that has a nonlocal label that can reach the exit
806 block via non-exceptional paths must save all call-saved
808 if (cfun
->has_nonlocal_label
809 && has_nonexceptional_receiver ())
810 crtl
->saves_all_registers
= 1;
812 if (crtl
->saves_all_registers
)
813 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
814 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
815 df_set_regs_ever_live (i
, true);
817 /* Find all the pseudo registers that didn't get hard regs
818 but do have known equivalent constants or memory slots.
819 These include parameters (known equivalent to parameter slots)
820 and cse'd or loop-moved constant memory addresses.
822 Record constant equivalents in reg_equiv_constant
823 so they will be substituted by find_reloads.
824 Record memory equivalents in reg_mem_equiv so they can
825 be substituted eventually by altering the REG-rtx's. */
828 reg_old_renumber
= XCNEWVEC (short, max_regno
);
829 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
830 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
831 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
833 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
835 init_eliminable_invariants (first
, true);
838 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
839 stack slots to the pseudos that lack hard regs or equivalents.
840 Do not touch virtual registers. */
842 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
843 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
844 temp_pseudo_reg_arr
[n
++] = i
;
847 /* Ask IRA to order pseudo-registers for better stack slot
849 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
851 for (i
= 0; i
< n
; i
++)
852 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
854 /* If we have some registers we think can be eliminated, scan all insns to
855 see if there is an insn that sets one of these registers to something
856 other than itself plus a constant. If so, the register cannot be
857 eliminated. Doing this scan here eliminates an extra pass through the
858 main reload loop in the most common case where register elimination
860 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
862 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
864 maybe_fix_stack_asms ();
866 insns_need_reload
= 0;
867 something_needs_elimination
= 0;
869 /* Initialize to -1, which means take the first spill register. */
872 /* Spill any hard regs that we know we can't eliminate. */
873 CLEAR_HARD_REG_SET (used_spill_regs
);
874 /* There can be multiple ways to eliminate a register;
875 they should be listed adjacently.
876 Elimination for any register fails only if all possible ways fail. */
877 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
880 int can_eliminate
= 0;
883 can_eliminate
|= ep
->can_eliminate
;
886 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
888 spill_hard_reg (from
, 1);
891 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
892 if (frame_pointer_needed
)
893 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
895 finish_spills (global
);
897 /* From now on, we may need to generate moves differently. We may also
898 allow modifications of insns which cause them to not be recognized.
899 Any such modifications will be cleaned up during reload itself. */
900 reload_in_progress
= 1;
902 /* This loop scans the entire function each go-round
903 and repeats until one repetition spills no additional hard regs. */
906 int something_changed
;
908 HOST_WIDE_INT starting_frame_size
;
910 starting_frame_size
= get_frame_size ();
911 something_was_spilled
= false;
913 set_initial_elim_offsets ();
914 set_initial_label_offsets ();
916 /* For each pseudo register that has an equivalent location defined,
917 try to eliminate any eliminable registers (such as the frame pointer)
918 assuming initial offsets for the replacement register, which
921 If the resulting location is directly addressable, substitute
922 the MEM we just got directly for the old REG.
924 If it is not addressable but is a constant or the sum of a hard reg
925 and constant, it is probably not addressable because the constant is
926 out of range, in that case record the address; we will generate
927 hairy code to compute the address in a register each time it is
928 needed. Similarly if it is a hard register, but one that is not
929 valid as an address register.
931 If the location is not addressable, but does not have one of the
932 above forms, assign a stack slot. We have to do this to avoid the
933 potential of producing lots of reloads if, e.g., a location involves
934 a pseudo that didn't get a hard register and has an equivalent memory
935 location that also involves a pseudo that didn't get a hard register.
937 Perhaps at some point we will improve reload_when_needed handling
938 so this problem goes away. But that's very hairy. */
940 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
941 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
943 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
946 if (strict_memory_address_addr_space_p
947 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
949 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
950 else if (CONSTANT_P (XEXP (x
, 0))
951 || (REG_P (XEXP (x
, 0))
952 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
953 || (GET_CODE (XEXP (x
, 0)) == PLUS
954 && REG_P (XEXP (XEXP (x
, 0), 0))
955 && (REGNO (XEXP (XEXP (x
, 0), 0))
956 < FIRST_PSEUDO_REGISTER
)
957 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
958 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
961 /* Make a new stack slot. Then indicate that something
962 changed so we go back and recompute offsets for
963 eliminable registers because the allocation of memory
964 below might change some offset. reg_equiv_{mem,address}
965 will be set up for this pseudo on the next pass around
967 reg_equiv_memory_loc (i
) = 0;
968 reg_equiv_init (i
) = 0;
969 alter_reg (i
, -1, true);
973 if (caller_save_needed
)
976 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
978 /* If we have a stack frame, we must align it now. The
979 stack size may be a part of the offset computation for
980 register elimination. So if this changes the stack size,
981 then repeat the elimination bookkeeping. We don't
982 realign when there is no stack, as that will cause a
983 stack frame when none is needed should
984 STARTING_FRAME_OFFSET not be already aligned to
986 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
988 /* If we allocated another stack slot, redo elimination bookkeeping. */
989 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
991 update_eliminables_and_spill ();
995 if (caller_save_needed
)
997 save_call_clobbered_regs ();
998 /* That might have allocated new insn_chain structures. */
999 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1002 calculate_needs_all_insns (global
);
1004 if (! ira_conflicts_p
)
1005 /* Don't do it for IRA. We need this info because we don't
1006 change live_throughout and dead_or_set for chains when IRA
1008 CLEAR_REG_SET (&spilled_pseudos
);
1012 something_changed
= 0;
1014 /* If we allocated any new memory locations, make another pass
1015 since it might have changed elimination offsets. */
1016 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1017 something_changed
= 1;
1019 /* Even if the frame size remained the same, we might still have
1020 changed elimination offsets, e.g. if find_reloads called
1021 force_const_mem requiring the back end to allocate a constant
1022 pool base register that needs to be saved on the stack. */
1023 else if (!verify_initial_elim_offsets ())
1024 something_changed
= 1;
1026 if (update_eliminables_and_spill ())
1029 something_changed
= 1;
1032 select_reload_regs ();
1036 if (insns_need_reload
!= 0 || did_spill
)
1037 something_changed
|= finish_spills (global
);
1039 if (! something_changed
)
1042 if (caller_save_needed
)
1043 delete_caller_save_insns ();
1045 obstack_free (&reload_obstack
, reload_firstobj
);
1048 /* If global-alloc was run, notify it of any register eliminations we have
1051 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1052 if (ep
->can_eliminate
)
1053 mark_elimination (ep
->from
, ep
->to
);
1055 remove_init_insns ();
1057 /* Use the reload registers where necessary
1058 by generating move instructions to move the must-be-register
1059 values into or out of the reload registers. */
1061 if (insns_need_reload
!= 0 || something_needs_elimination
1062 || something_needs_operands_changed
)
1064 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1066 reload_as_needed (global
);
1068 gcc_assert (old_frame_size
== get_frame_size ());
1070 gcc_assert (verify_initial_elim_offsets ());
1073 /* If we were able to eliminate the frame pointer, show that it is no
1074 longer live at the start of any basic block. If it ls live by
1075 virtue of being in a pseudo, that pseudo will be marked live
1076 and hence the frame pointer will be known to be live via that
1079 if (! frame_pointer_needed
)
1080 FOR_EACH_BB_FN (bb
, cfun
)
1081 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1083 /* Come here (with failure set nonzero) if we can't get enough spill
1087 CLEAR_REG_SET (&changed_allocation_pseudos
);
1088 CLEAR_REG_SET (&spilled_pseudos
);
1089 reload_in_progress
= 0;
1091 /* Now eliminate all pseudo regs by modifying them into
1092 their equivalent memory references.
1093 The REG-rtx's for the pseudos are modified in place,
1094 so all insns that used to refer to them now refer to memory.
1096 For a reg that has a reg_equiv_address, all those insns
1097 were changed by reloading so that no insns refer to it any longer;
1098 but the DECL_RTL of a variable decl may refer to it,
1099 and if so this causes the debugging info to mention the variable. */
1101 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1105 if (reg_equiv_mem (i
))
1106 addr
= XEXP (reg_equiv_mem (i
), 0);
1108 if (reg_equiv_address (i
))
1109 addr
= reg_equiv_address (i
);
1113 if (reg_renumber
[i
] < 0)
1115 rtx reg
= regno_reg_rtx
[i
];
1117 REG_USERVAR_P (reg
) = 0;
1118 PUT_CODE (reg
, MEM
);
1119 XEXP (reg
, 0) = addr
;
1120 if (reg_equiv_memory_loc (i
))
1121 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1123 MEM_ATTRS (reg
) = 0;
1124 MEM_NOTRAP_P (reg
) = 1;
1126 else if (reg_equiv_mem (i
))
1127 XEXP (reg_equiv_mem (i
), 0) = addr
;
1130 /* We don't want complex addressing modes in debug insns
1131 if simpler ones will do, so delegitimize equivalences
1133 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1135 rtx reg
= regno_reg_rtx
[i
];
1139 if (reg_equiv_constant (i
))
1140 equiv
= reg_equiv_constant (i
);
1141 else if (reg_equiv_invariant (i
))
1142 equiv
= reg_equiv_invariant (i
);
1143 else if (reg
&& MEM_P (reg
))
1144 equiv
= targetm
.delegitimize_address (reg
);
1145 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1151 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1153 insn
= DF_REF_INSN (use
);
1155 /* Make sure the next ref is for a different instruction,
1156 so that we're not affected by the rescan. */
1157 next
= DF_REF_NEXT_REG (use
);
1158 while (next
&& DF_REF_INSN (next
) == insn
)
1159 next
= DF_REF_NEXT_REG (next
);
1161 if (DEBUG_INSN_P (insn
))
1165 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1166 df_insn_rescan_debug_internal (insn
);
1169 INSN_VAR_LOCATION_LOC (insn
)
1170 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1177 /* We must set reload_completed now since the cleanup_subreg_operands call
1178 below will re-recognize each insn and reload may have generated insns
1179 which are only valid during and after reload. */
1180 reload_completed
= 1;
1182 /* Make a pass over all the insns and delete all USEs which we inserted
1183 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1184 notes. Delete all CLOBBER insns, except those that refer to the return
1185 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1186 from misarranging variable-array code, and simplify (subreg (reg))
1187 operands. Strip and regenerate REG_INC notes that may have been moved
1190 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1196 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1197 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1199 if ((GET_CODE (PATTERN (insn
)) == USE
1200 /* We mark with QImode USEs introduced by reload itself. */
1201 && (GET_MODE (insn
) == QImode
1202 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1203 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1204 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1205 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1206 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1207 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1208 != stack_pointer_rtx
))
1209 && (!REG_P (XEXP (PATTERN (insn
), 0))
1210 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1216 /* Some CLOBBERs may survive until here and still reference unassigned
1217 pseudos with const equivalent, which may in turn cause ICE in later
1218 passes if the reference remains in place. */
1219 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1220 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1221 VOIDmode
, PATTERN (insn
));
1223 /* Discard obvious no-ops, even without -O. This optimization
1224 is fast and doesn't interfere with debugging. */
1225 if (NONJUMP_INSN_P (insn
)
1226 && GET_CODE (PATTERN (insn
)) == SET
1227 && REG_P (SET_SRC (PATTERN (insn
)))
1228 && REG_P (SET_DEST (PATTERN (insn
)))
1229 && (REGNO (SET_SRC (PATTERN (insn
)))
1230 == REGNO (SET_DEST (PATTERN (insn
)))))
1236 pnote
= ®_NOTES (insn
);
1239 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1240 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1241 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1242 *pnote
= XEXP (*pnote
, 1);
1244 pnote
= &XEXP (*pnote
, 1);
1248 add_auto_inc_notes (insn
, PATTERN (insn
));
1251 /* Simplify (subreg (reg)) if it appears as an operand. */
1252 cleanup_subreg_operands (insn
);
1254 /* Clean up invalid ASMs so that they don't confuse later passes.
1256 if (asm_noperands (PATTERN (insn
)) >= 0)
1258 extract_insn (insn
);
1259 if (!constrain_operands (1))
1261 error_for_asm (insn
,
1262 "%<asm%> operand has impossible constraints");
1269 /* If we are doing generic stack checking, give a warning if this
1270 function's frame size is larger than we expect. */
1271 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1273 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1274 static int verbose_warned
= 0;
1276 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1277 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1278 size
+= UNITS_PER_WORD
;
1280 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1282 warning (0, "frame size too large for reliable stack checking");
1283 if (! verbose_warned
)
1285 warning (0, "try reducing the number of local variables");
1291 free (temp_pseudo_reg_arr
);
1293 /* Indicate that we no longer have known memory locations or constants. */
1296 free (reg_max_ref_width
);
1297 free (reg_old_renumber
);
1298 free (pseudo_previous_regs
);
1299 free (pseudo_forbidden_regs
);
1301 CLEAR_HARD_REG_SET (used_spill_regs
);
1302 for (i
= 0; i
< n_spills
; i
++)
1303 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1305 /* Free all the insn_chain structures at once. */
1306 obstack_free (&reload_obstack
, reload_startobj
);
1307 unused_insn_chains
= 0;
1309 inserted
= fixup_abnormal_edges ();
1311 /* We've possibly turned single trapping insn into multiple ones. */
1312 if (cfun
->can_throw_non_call_exceptions
)
1315 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
1316 bitmap_ones (blocks
);
1317 find_many_sub_basic_blocks (blocks
);
1318 sbitmap_free (blocks
);
1322 commit_edge_insertions ();
1324 /* Replacing pseudos with their memory equivalents might have
1325 created shared rtx. Subsequent passes would get confused
1326 by this, so unshare everything here. */
1327 unshare_all_rtl_again (first
);
1329 #ifdef STACK_BOUNDARY
1330 /* init_emit has set the alignment of the hard frame pointer
1331 to STACK_BOUNDARY. It is very likely no longer valid if
1332 the hard frame pointer was used for register allocation. */
1333 if (!frame_pointer_needed
)
1334 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1337 substitute_stack
.release ();
1339 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1341 reload_completed
= !failure
;
1346 /* Yet another special case. Unfortunately, reg-stack forces people to
1347 write incorrect clobbers in asm statements. These clobbers must not
1348 cause the register to appear in bad_spill_regs, otherwise we'll call
1349 fatal_insn later. We clear the corresponding regnos in the live
1350 register sets to avoid this.
1351 The whole thing is rather sick, I'm afraid. */
1354 maybe_fix_stack_asms (void)
1357 const char *constraints
[MAX_RECOG_OPERANDS
];
1358 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1359 struct insn_chain
*chain
;
1361 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1364 HARD_REG_SET clobbered
, allowed
;
1367 if (! INSN_P (chain
->insn
)
1368 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1370 pat
= PATTERN (chain
->insn
);
1371 if (GET_CODE (pat
) != PARALLEL
)
1374 CLEAR_HARD_REG_SET (clobbered
);
1375 CLEAR_HARD_REG_SET (allowed
);
1377 /* First, make a mask of all stack regs that are clobbered. */
1378 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1380 rtx t
= XVECEXP (pat
, 0, i
);
1381 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1382 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1385 /* Get the operand values and constraints out of the insn. */
1386 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1387 constraints
, operand_mode
, NULL
);
1389 /* For every operand, see what registers are allowed. */
1390 for (i
= 0; i
< noperands
; i
++)
1392 const char *p
= constraints
[i
];
1393 /* For every alternative, we compute the class of registers allowed
1394 for reloading in CLS, and merge its contents into the reg set
1396 int cls
= (int) NO_REGS
;
1402 if (c
== '\0' || c
== ',' || c
== '#')
1404 /* End of one alternative - mark the regs in the current
1405 class, and reset the class. */
1406 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1412 } while (c
!= '\0' && c
!= ',');
1420 case '=': case '+': case '*': case '%': case '?': case '!':
1421 case '0': case '1': case '2': case '3': case '4': case '<':
1422 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1423 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1424 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1425 case TARGET_MEM_CONSTRAINT
:
1429 cls
= (int) reg_class_subunion
[cls
]
1430 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1436 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1440 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1441 cls
= (int) reg_class_subunion
[cls
]
1442 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1445 cls
= (int) reg_class_subunion
[cls
]
1446 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1448 p
+= CONSTRAINT_LEN (c
, p
);
1451 /* Those of the registers which are clobbered, but allowed by the
1452 constraints, must be usable as reload registers. So clear them
1453 out of the life information. */
1454 AND_HARD_REG_SET (allowed
, clobbered
);
1455 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1456 if (TEST_HARD_REG_BIT (allowed
, i
))
1458 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1459 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1466 /* Copy the global variables n_reloads and rld into the corresponding elts
1469 copy_reloads (struct insn_chain
*chain
)
1471 chain
->n_reloads
= n_reloads
;
1472 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1473 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1474 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1477 /* Walk the chain of insns, and determine for each whether it needs reloads
1478 and/or eliminations. Build the corresponding insns_need_reload list, and
1479 set something_needs_elimination as appropriate. */
1481 calculate_needs_all_insns (int global
)
1483 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1484 struct insn_chain
*chain
, *next
= 0;
1486 something_needs_elimination
= 0;
1488 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1489 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1491 rtx insn
= chain
->insn
;
1495 /* Clear out the shortcuts. */
1496 chain
->n_reloads
= 0;
1497 chain
->need_elim
= 0;
1498 chain
->need_reload
= 0;
1499 chain
->need_operand_change
= 0;
1501 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1502 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1503 what effects this has on the known offsets at labels. */
1505 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1506 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1507 set_label_offsets (insn
, insn
, 0);
1511 rtx old_body
= PATTERN (insn
);
1512 int old_code
= INSN_CODE (insn
);
1513 rtx old_notes
= REG_NOTES (insn
);
1514 int did_elimination
= 0;
1515 int operands_changed
= 0;
1517 /* Skip insns that only set an equivalence. */
1518 if (will_delete_init_insn_p (insn
))
1521 /* If needed, eliminate any eliminable registers. */
1522 if (num_eliminable
|| num_eliminable_invariants
)
1523 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1525 /* Analyze the instruction. */
1526 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1527 global
, spill_reg_order
);
1529 /* If a no-op set needs more than one reload, this is likely
1530 to be something that needs input address reloads. We
1531 can't get rid of this cleanly later, and it is of no use
1532 anyway, so discard it now.
1533 We only do this when expensive_optimizations is enabled,
1534 since this complements reload inheritance / output
1535 reload deletion, and it can make debugging harder. */
1536 if (flag_expensive_optimizations
&& n_reloads
> 1)
1538 rtx set
= single_set (insn
);
1541 ((SET_SRC (set
) == SET_DEST (set
)
1542 && REG_P (SET_SRC (set
))
1543 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1544 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1545 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1546 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1547 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1548 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1549 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1550 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1552 if (ira_conflicts_p
)
1553 /* Inform IRA about the insn deletion. */
1554 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1555 REGNO (SET_SRC (set
)));
1557 /* Delete it from the reload chain. */
1559 chain
->prev
->next
= next
;
1561 reload_insn_chain
= next
;
1563 next
->prev
= chain
->prev
;
1564 chain
->next
= unused_insn_chains
;
1565 unused_insn_chains
= chain
;
1570 update_eliminable_offsets ();
1572 /* Remember for later shortcuts which insns had any reloads or
1573 register eliminations. */
1574 chain
->need_elim
= did_elimination
;
1575 chain
->need_reload
= n_reloads
> 0;
1576 chain
->need_operand_change
= operands_changed
;
1578 /* Discard any register replacements done. */
1579 if (did_elimination
)
1581 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1582 PATTERN (insn
) = old_body
;
1583 INSN_CODE (insn
) = old_code
;
1584 REG_NOTES (insn
) = old_notes
;
1585 something_needs_elimination
= 1;
1588 something_needs_operands_changed
|= operands_changed
;
1592 copy_reloads (chain
);
1593 *pprev_reload
= chain
;
1594 pprev_reload
= &chain
->next_need_reload
;
1601 /* This function is called from the register allocator to set up estimates
1602 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1603 an invariant. The structure is similar to calculate_needs_all_insns. */
1606 calculate_elim_costs_all_insns (void)
1608 int *reg_equiv_init_cost
;
1612 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1614 init_eliminable_invariants (get_insns (), false);
1616 set_initial_elim_offsets ();
1617 set_initial_label_offsets ();
1619 FOR_EACH_BB_FN (bb
, cfun
)
1624 FOR_BB_INSNS (bb
, insn
)
1626 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1627 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1628 what effects this has on the known offsets at labels. */
1630 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1631 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1632 set_label_offsets (insn
, insn
, 0);
1636 rtx set
= single_set (insn
);
1638 /* Skip insns that only set an equivalence. */
1639 if (set
&& REG_P (SET_DEST (set
))
1640 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1641 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1642 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1644 unsigned regno
= REGNO (SET_DEST (set
));
1645 rtx init
= reg_equiv_init (regno
);
1648 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1650 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1651 int freq
= REG_FREQ_FROM_BB (bb
);
1653 reg_equiv_init_cost
[regno
] = cost
* freq
;
1657 /* If needed, eliminate any eliminable registers. */
1658 if (num_eliminable
|| num_eliminable_invariants
)
1659 elimination_costs_in_insn (insn
);
1662 update_eliminable_offsets ();
1666 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1668 if (reg_equiv_invariant (i
))
1670 if (reg_equiv_init (i
))
1672 int cost
= reg_equiv_init_cost
[i
];
1675 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1677 ira_adjust_equiv_reg_cost (i
, cost
);
1683 "Reg %d had equivalence, but can't be eliminated\n",
1685 ira_adjust_equiv_reg_cost (i
, 0);
1690 free (reg_equiv_init_cost
);
1691 free (offsets_known_at
);
1694 offsets_known_at
= NULL
;
1697 /* Comparison function for qsort to decide which of two reloads
1698 should be handled first. *P1 and *P2 are the reload numbers. */
1701 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1703 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1706 /* Consider required reloads before optional ones. */
1707 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1711 /* Count all solitary classes before non-solitary ones. */
1712 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1713 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1717 /* Aside from solitaires, consider all multi-reg groups first. */
1718 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1722 /* Consider reloads in order of increasing reg-class number. */
1723 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1727 /* If reloads are equally urgent, sort by reload number,
1728 so that the results of qsort leave nothing to chance. */
1732 /* The cost of spilling each hard reg. */
1733 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1735 /* When spilling multiple hard registers, we use SPILL_COST for the first
1736 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1737 only the first hard reg for a multi-reg pseudo. */
1738 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1740 /* Map of hard regno to pseudo regno currently occupying the hard
1742 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1744 /* Update the spill cost arrays, considering that pseudo REG is live. */
1747 count_pseudo (int reg
)
1749 int freq
= REG_FREQ (reg
);
1750 int r
= reg_renumber
[reg
];
1753 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1754 if (ira_conflicts_p
&& r
< 0)
1757 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1758 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1761 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1763 gcc_assert (r
>= 0);
1765 spill_add_cost
[r
] += freq
;
1766 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1769 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1770 spill_cost
[r
+ nregs
] += freq
;
1774 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1775 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1778 order_regs_for_reload (struct insn_chain
*chain
)
1781 HARD_REG_SET used_by_pseudos
;
1782 HARD_REG_SET used_by_pseudos2
;
1783 reg_set_iterator rsi
;
1785 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1787 memset (spill_cost
, 0, sizeof spill_cost
);
1788 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1789 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1790 hard_regno_to_pseudo_regno
[i
] = -1;
1792 /* Count number of uses of each hard reg by pseudo regs allocated to it
1793 and then order them by decreasing use. First exclude hard registers
1794 that are live in or across this insn. */
1796 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1797 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1798 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1799 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1801 /* Now find out which pseudos are allocated to it, and update
1803 CLEAR_REG_SET (&pseudos_counted
);
1805 EXECUTE_IF_SET_IN_REG_SET
1806 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1810 EXECUTE_IF_SET_IN_REG_SET
1811 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1815 CLEAR_REG_SET (&pseudos_counted
);
1818 /* Vector of reload-numbers showing the order in which the reloads should
1820 static short reload_order
[MAX_RELOADS
];
1822 /* This is used to keep track of the spill regs used in one insn. */
1823 static HARD_REG_SET used_spill_regs_local
;
1825 /* We decided to spill hard register SPILLED, which has a size of
1826 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1827 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1828 update SPILL_COST/SPILL_ADD_COST. */
1831 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1833 int freq
= REG_FREQ (reg
);
1834 int r
= reg_renumber
[reg
];
1837 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1838 if (ira_conflicts_p
&& r
< 0)
1841 gcc_assert (r
>= 0);
1843 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1845 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1846 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1849 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1851 spill_add_cost
[r
] -= freq
;
1854 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1855 spill_cost
[r
+ nregs
] -= freq
;
1859 /* Find reload register to use for reload number ORDER. */
1862 find_reg (struct insn_chain
*chain
, int order
)
1864 int rnum
= reload_order
[order
];
1865 struct reload
*rl
= rld
+ rnum
;
1866 int best_cost
= INT_MAX
;
1868 unsigned int i
, j
, n
;
1870 HARD_REG_SET not_usable
;
1871 HARD_REG_SET used_by_other_reload
;
1872 reg_set_iterator rsi
;
1873 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1874 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1876 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1877 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1878 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1880 CLEAR_HARD_REG_SET (used_by_other_reload
);
1881 for (k
= 0; k
< order
; k
++)
1883 int other
= reload_order
[k
];
1885 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1886 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1887 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1890 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1892 #ifdef REG_ALLOC_ORDER
1893 unsigned int regno
= reg_alloc_order
[i
];
1895 unsigned int regno
= i
;
1898 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1899 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1900 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1902 int this_cost
= spill_cost
[regno
];
1904 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1906 for (j
= 1; j
< this_nregs
; j
++)
1908 this_cost
+= spill_add_cost
[regno
+ j
];
1909 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1910 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1916 if (ira_conflicts_p
)
1918 /* Ask IRA to find a better pseudo-register for
1920 for (n
= j
= 0; j
< this_nregs
; j
++)
1922 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1926 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1927 regno_pseudo_regs
[n
++] = r
;
1929 regno_pseudo_regs
[n
++] = -1;
1931 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1932 best_regno_pseudo_regs
,
1939 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1940 if (regno_pseudo_regs
[j
] < 0)
1947 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1949 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1951 if (this_cost
< best_cost
1952 /* Among registers with equal cost, prefer caller-saved ones, or
1953 use REG_ALLOC_ORDER if it is defined. */
1954 || (this_cost
== best_cost
1955 #ifdef REG_ALLOC_ORDER
1956 && (inv_reg_alloc_order
[regno
]
1957 < inv_reg_alloc_order
[best_reg
])
1959 && call_used_regs
[regno
]
1960 && ! call_used_regs
[best_reg
]
1965 best_cost
= this_cost
;
1973 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1975 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1976 rl
->regno
= best_reg
;
1978 EXECUTE_IF_SET_IN_REG_SET
1979 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1981 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1984 EXECUTE_IF_SET_IN_REG_SET
1985 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1987 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1990 for (i
= 0; i
< rl
->nregs
; i
++)
1992 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1993 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1994 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1995 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
2000 /* Find more reload regs to satisfy the remaining need of an insn, which
2002 Do it by ascending class number, since otherwise a reg
2003 might be spilled for a big class and might fail to count
2004 for a smaller class even though it belongs to that class. */
2007 find_reload_regs (struct insn_chain
*chain
)
2011 /* In order to be certain of getting the registers we need,
2012 we must sort the reloads into order of increasing register class.
2013 Then our grabbing of reload registers will parallel the process
2014 that provided the reload registers. */
2015 for (i
= 0; i
< chain
->n_reloads
; i
++)
2017 /* Show whether this reload already has a hard reg. */
2018 if (chain
->rld
[i
].reg_rtx
)
2020 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2021 chain
->rld
[i
].regno
= regno
;
2023 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2026 chain
->rld
[i
].regno
= -1;
2027 reload_order
[i
] = i
;
2030 n_reloads
= chain
->n_reloads
;
2031 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2033 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2036 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2038 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2040 /* Compute the order of preference for hard registers to spill. */
2042 order_regs_for_reload (chain
);
2044 for (i
= 0; i
< n_reloads
; i
++)
2046 int r
= reload_order
[i
];
2048 /* Ignore reloads that got marked inoperative. */
2049 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2050 && ! rld
[r
].optional
2051 && rld
[r
].regno
== -1)
2052 if (! find_reg (chain
, i
))
2055 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2056 spill_failure (chain
->insn
, rld
[r
].rclass
);
2062 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2063 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2065 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2069 select_reload_regs (void)
2071 struct insn_chain
*chain
;
2073 /* Try to satisfy the needs for each insn. */
2074 for (chain
= insns_need_reload
; chain
!= 0;
2075 chain
= chain
->next_need_reload
)
2076 find_reload_regs (chain
);
2079 /* Delete all insns that were inserted by emit_caller_save_insns during
2082 delete_caller_save_insns (void)
2084 struct insn_chain
*c
= reload_insn_chain
;
2088 while (c
!= 0 && c
->is_caller_save_insn
)
2090 struct insn_chain
*next
= c
->next
;
2093 if (c
== reload_insn_chain
)
2094 reload_insn_chain
= next
;
2098 next
->prev
= c
->prev
;
2100 c
->prev
->next
= next
;
2101 c
->next
= unused_insn_chains
;
2102 unused_insn_chains
= c
;
2110 /* Handle the failure to find a register to spill.
2111 INSN should be one of the insns which needed this particular spill reg. */
2114 spill_failure (rtx insn
, enum reg_class rclass
)
2116 if (asm_noperands (PATTERN (insn
)) >= 0)
2117 error_for_asm (insn
, "can%'t find a register in class %qs while "
2118 "reloading %<asm%>",
2119 reg_class_names
[rclass
]);
2122 error ("unable to find a register to spill in class %qs",
2123 reg_class_names
[rclass
]);
2127 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2128 debug_reload_to_stream (dump_file
);
2130 fatal_insn ("this is the insn:", insn
);
2134 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2135 data that is dead in INSN. */
2138 delete_dead_insn (rtx insn
)
2140 rtx prev
= prev_active_insn (insn
);
2143 /* If the previous insn sets a register that dies in our insn make
2144 a note that we want to run DCE immediately after reload.
2146 We used to delete the previous insn & recurse, but that's wrong for
2147 block local equivalences. Instead of trying to figure out the exact
2148 circumstances where we can delete the potentially dead insns, just
2149 let DCE do the job. */
2150 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2151 && GET_CODE (PATTERN (prev
)) == SET
2152 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2153 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2154 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2155 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2158 SET_INSN_DELETED (insn
);
2161 /* Modify the home of pseudo-reg I.
2162 The new home is present in reg_renumber[I].
2164 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2165 or it may be -1, meaning there is none or it is not relevant.
2166 This is used so that all pseudos spilled from a given hard reg
2167 can share one stack slot. */
2170 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2172 /* When outputting an inline function, this can happen
2173 for a reg that isn't actually used. */
2174 if (regno_reg_rtx
[i
] == 0)
2177 /* If the reg got changed to a MEM at rtl-generation time,
2179 if (!REG_P (regno_reg_rtx
[i
]))
2182 /* Modify the reg-rtx to contain the new hard reg
2183 number or else to contain its pseudo reg number. */
2184 SET_REGNO (regno_reg_rtx
[i
],
2185 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2187 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2188 allocate a stack slot for it. */
2190 if (reg_renumber
[i
] < 0
2191 && REG_N_REFS (i
) > 0
2192 && reg_equiv_constant (i
) == 0
2193 && (reg_equiv_invariant (i
) == 0
2194 || reg_equiv_init (i
) == 0)
2195 && reg_equiv_memory_loc (i
) == 0)
2198 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2199 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2200 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2201 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2202 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2205 something_was_spilled
= true;
2207 if (ira_conflicts_p
)
2209 /* Mark the spill for IRA. */
2210 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2212 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2218 /* Each pseudo reg has an inherent size which comes from its own mode,
2219 and a total size which provides room for paradoxical subregs
2220 which refer to the pseudo reg in wider modes.
2222 We can use a slot already allocated if it provides both
2223 enough inherent space and enough total space.
2224 Otherwise, we allocate a new slot, making sure that it has no less
2225 inherent space, and no less total space, then the previous slot. */
2226 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2230 /* No known place to spill from => no slot to reuse. */
2231 x
= assign_stack_local (mode
, total_size
,
2232 min_align
> inherent_align
2233 || total_size
> inherent_size
? -1 : 0);
2237 /* Cancel the big-endian correction done in assign_stack_local.
2238 Get the address of the beginning of the slot. This is so we
2239 can do a big-endian correction unconditionally below. */
2240 if (BYTES_BIG_ENDIAN
)
2242 adjust
= inherent_size
- total_size
;
2245 = adjust_address_nv (x
, mode_for_size (total_size
2251 if (! dont_share_p
&& ira_conflicts_p
)
2252 /* Inform IRA about allocation a new stack slot. */
2253 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2256 /* Reuse a stack slot if possible. */
2257 else if (spill_stack_slot
[from_reg
] != 0
2258 && spill_stack_slot_width
[from_reg
] >= total_size
2259 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2261 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2262 x
= spill_stack_slot
[from_reg
];
2264 /* Allocate a bigger slot. */
2267 /* Compute maximum size needed, both for inherent size
2268 and for total size. */
2271 if (spill_stack_slot
[from_reg
])
2273 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2275 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2276 if (spill_stack_slot_width
[from_reg
] > total_size
)
2277 total_size
= spill_stack_slot_width
[from_reg
];
2278 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2279 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2282 /* Make a slot with that size. */
2283 x
= assign_stack_local (mode
, total_size
,
2284 min_align
> inherent_align
2285 || total_size
> inherent_size
? -1 : 0);
2288 /* Cancel the big-endian correction done in assign_stack_local.
2289 Get the address of the beginning of the slot. This is so we
2290 can do a big-endian correction unconditionally below. */
2291 if (BYTES_BIG_ENDIAN
)
2293 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2296 = adjust_address_nv (x
, mode_for_size (total_size
2302 spill_stack_slot
[from_reg
] = stack_slot
;
2303 spill_stack_slot_width
[from_reg
] = total_size
;
2306 /* On a big endian machine, the "address" of the slot
2307 is the address of the low part that fits its inherent mode. */
2308 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2309 adjust
+= (total_size
- inherent_size
);
2311 /* If we have any adjustment to make, or if the stack slot is the
2312 wrong mode, make a new stack slot. */
2313 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2315 /* Set all of the memory attributes as appropriate for a spill. */
2316 set_mem_attrs_for_spill (x
);
2318 /* Save the stack slot for later. */
2319 reg_equiv_memory_loc (i
) = x
;
2323 /* Mark the slots in regs_ever_live for the hard regs used by
2324 pseudo-reg number REGNO, accessed in MODE. */
2327 mark_home_live_1 (int regno
, enum machine_mode mode
)
2331 i
= reg_renumber
[regno
];
2334 lim
= end_hard_regno (mode
, i
);
2336 df_set_regs_ever_live (i
++, true);
2339 /* Mark the slots in regs_ever_live for the hard regs
2340 used by pseudo-reg number REGNO. */
2343 mark_home_live (int regno
)
2345 if (reg_renumber
[regno
] >= 0)
2346 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2349 /* This function handles the tracking of elimination offsets around branches.
2351 X is a piece of RTL being scanned.
2353 INSN is the insn that it came from, if any.
2355 INITIAL_P is nonzero if we are to set the offset to be the initial
2356 offset and zero if we are setting the offset of the label to be the
2360 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2362 enum rtx_code code
= GET_CODE (x
);
2365 struct elim_table
*p
;
2370 if (LABEL_REF_NONLOCAL_P (x
))
2375 /* ... fall through ... */
2378 /* If we know nothing about this label, set the desired offsets. Note
2379 that this sets the offset at a label to be the offset before a label
2380 if we don't know anything about the label. This is not correct for
2381 the label after a BARRIER, but is the best guess we can make. If
2382 we guessed wrong, we will suppress an elimination that might have
2383 been possible had we been able to guess correctly. */
2385 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2387 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2388 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2389 = (initial_p
? reg_eliminate
[i
].initial_offset
2390 : reg_eliminate
[i
].offset
);
2391 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2394 /* Otherwise, if this is the definition of a label and it is
2395 preceded by a BARRIER, set our offsets to the known offset of
2399 && (tem
= prev_nonnote_insn (insn
)) != 0
2401 set_offsets_for_label (insn
);
2403 /* If neither of the above cases is true, compare each offset
2404 with those previously recorded and suppress any eliminations
2405 where the offsets disagree. */
2407 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2408 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2409 != (initial_p
? reg_eliminate
[i
].initial_offset
2410 : reg_eliminate
[i
].offset
))
2411 reg_eliminate
[i
].can_eliminate
= 0;
2415 case JUMP_TABLE_DATA
:
2416 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2420 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2422 /* ... fall through ... */
2426 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2427 to indirectly and hence must have all eliminations at their
2429 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2430 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2431 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2437 /* Each of the labels in the parallel or address vector must be
2438 at their initial offsets. We want the first field for PARALLEL
2439 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2441 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2442 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2447 /* We only care about setting PC. If the source is not RETURN,
2448 IF_THEN_ELSE, or a label, disable any eliminations not at
2449 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2450 isn't one of those possibilities. For branches to a label,
2451 call ourselves recursively.
2453 Note that this can disable elimination unnecessarily when we have
2454 a non-local goto since it will look like a non-constant jump to
2455 someplace in the current function. This isn't a significant
2456 problem since such jumps will normally be when all elimination
2457 pairs are back to their initial offsets. */
2459 if (SET_DEST (x
) != pc_rtx
)
2462 switch (GET_CODE (SET_SRC (x
)))
2469 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2473 tem
= XEXP (SET_SRC (x
), 1);
2474 if (GET_CODE (tem
) == LABEL_REF
)
2475 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2476 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2479 tem
= XEXP (SET_SRC (x
), 2);
2480 if (GET_CODE (tem
) == LABEL_REF
)
2481 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2482 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2490 /* If we reach here, all eliminations must be at their initial
2491 offset because we are doing a jump to a variable address. */
2492 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2493 if (p
->offset
!= p
->initial_offset
)
2494 p
->can_eliminate
= 0;
2502 /* Called through for_each_rtx, this function examines every reg that occurs
2503 in PX and adjusts the costs for its elimination which are gathered by IRA.
2504 DATA is the insn in which PX occurs. We do not recurse into MEM
2508 note_reg_elim_costly (rtx
*px
, void *data
)
2510 rtx insn
= (rtx
)data
;
2517 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2518 && reg_equiv_init (REGNO (x
))
2519 && reg_equiv_invariant (REGNO (x
)))
2521 rtx t
= reg_equiv_invariant (REGNO (x
));
2522 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2523 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2524 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2527 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2532 /* Scan X and replace any eliminable registers (such as fp) with a
2533 replacement (such as sp), plus an offset.
2535 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2536 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2537 MEM, we are allowed to replace a sum of a register and the constant zero
2538 with the register, which we cannot do outside a MEM. In addition, we need
2539 to record the fact that a register is referenced outside a MEM.
2541 If INSN is an insn, it is the insn containing X. If we replace a REG
2542 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2543 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2544 the REG is being modified.
2546 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2547 That's used when we eliminate in expressions stored in notes.
2548 This means, do not set ref_outside_mem even if the reference
2551 If FOR_COSTS is true, we are being called before reload in order to
2552 estimate the costs of keeping registers with an equivalence unallocated.
2554 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2555 replacements done assuming all offsets are at their initial values. If
2556 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2557 encounter, return the actual location so that find_reloads will do
2558 the proper thing. */
2561 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2562 bool may_use_invariant
, bool for_costs
)
2564 enum rtx_code code
= GET_CODE (x
);
2565 struct elim_table
*ep
;
2572 if (! current_function_decl
)
2592 /* First handle the case where we encounter a bare register that
2593 is eliminable. Replace it with a PLUS. */
2594 if (regno
< FIRST_PSEUDO_REGISTER
)
2596 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2598 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2599 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2602 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2604 && reg_equiv_invariant (regno
))
2606 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2607 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2608 mem_mode
, insn
, true, for_costs
);
2609 /* There exists at least one use of REGNO that cannot be
2610 eliminated. Prevent the defining insn from being deleted. */
2611 reg_equiv_init (regno
) = NULL_RTX
;
2613 alter_reg (regno
, -1, true);
2617 /* You might think handling MINUS in a manner similar to PLUS is a
2618 good idea. It is not. It has been tried multiple times and every
2619 time the change has had to have been reverted.
2621 Other parts of reload know a PLUS is special (gen_reload for example)
2622 and require special code to handle code a reloaded PLUS operand.
2624 Also consider backends where the flags register is clobbered by a
2625 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2626 lea instruction comes to mind). If we try to reload a MINUS, we
2627 may kill the flags register that was holding a useful value.
2629 So, please before trying to handle MINUS, consider reload as a
2630 whole instead of this little section as well as the backend issues. */
2632 /* If this is the sum of an eliminable register and a constant, rework
2634 if (REG_P (XEXP (x
, 0))
2635 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2636 && CONSTANT_P (XEXP (x
, 1)))
2638 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2640 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2642 /* The only time we want to replace a PLUS with a REG (this
2643 occurs when the constant operand of the PLUS is the negative
2644 of the offset) is when we are inside a MEM. We won't want
2645 to do so at other times because that would change the
2646 structure of the insn in a way that reload can't handle.
2647 We special-case the commonest situation in
2648 eliminate_regs_in_insn, so just replace a PLUS with a
2649 PLUS here, unless inside a MEM. */
2650 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2651 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2654 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2655 plus_constant (Pmode
, XEXP (x
, 1),
2656 ep
->previous_offset
));
2659 /* If the register is not eliminable, we are done since the other
2660 operand is a constant. */
2664 /* If this is part of an address, we want to bring any constant to the
2665 outermost PLUS. We will do this by doing register replacement in
2666 our operands and seeing if a constant shows up in one of them.
2668 Note that there is no risk of modifying the structure of the insn,
2669 since we only get called for its operands, thus we are either
2670 modifying the address inside a MEM, or something like an address
2671 operand of a load-address insn. */
2674 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2676 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2679 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2681 /* If one side is a PLUS and the other side is a pseudo that
2682 didn't get a hard register but has a reg_equiv_constant,
2683 we must replace the constant here since it may no longer
2684 be in the position of any operand. */
2685 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2686 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2687 && reg_renumber
[REGNO (new1
)] < 0
2689 && reg_equiv_constant (REGNO (new1
)) != 0)
2690 new1
= reg_equiv_constant (REGNO (new1
));
2691 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2692 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2693 && reg_renumber
[REGNO (new0
)] < 0
2694 && reg_equiv_constant (REGNO (new0
)) != 0)
2695 new0
= reg_equiv_constant (REGNO (new0
));
2697 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2699 /* As above, if we are not inside a MEM we do not want to
2700 turn a PLUS into something else. We might try to do so here
2701 for an addition of 0 if we aren't optimizing. */
2702 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2703 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2711 /* If this is the product of an eliminable register and a
2712 constant, apply the distribute law and move the constant out
2713 so that we have (plus (mult ..) ..). This is needed in order
2714 to keep load-address insns valid. This case is pathological.
2715 We ignore the possibility of overflow here. */
2716 if (REG_P (XEXP (x
, 0))
2717 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2718 && CONST_INT_P (XEXP (x
, 1)))
2719 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2721 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2724 /* Refs inside notes or in DEBUG_INSNs don't count for
2726 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2727 || GET_CODE (insn
) == INSN_LIST
2728 || DEBUG_INSN_P (insn
))))
2729 ep
->ref_outside_mem
= 1;
2732 plus_constant (Pmode
,
2733 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2734 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2737 /* ... fall through ... */
2741 /* See comments before PLUS about handling MINUS. */
2743 case DIV
: case UDIV
:
2744 case MOD
: case UMOD
:
2745 case AND
: case IOR
: case XOR
:
2746 case ROTATERT
: case ROTATE
:
2747 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2749 case GE
: case GT
: case GEU
: case GTU
:
2750 case LE
: case LT
: case LEU
: case LTU
:
2752 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2754 rtx new1
= XEXP (x
, 1)
2755 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2758 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2759 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2764 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2767 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2769 if (new_rtx
!= XEXP (x
, 0))
2771 /* If this is a REG_DEAD note, it is not valid anymore.
2772 Using the eliminated version could result in creating a
2773 REG_DEAD note for the stack or frame pointer. */
2774 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2776 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2780 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2784 /* ... fall through ... */
2788 /* Now do eliminations in the rest of the chain. If this was
2789 an EXPR_LIST, this might result in allocating more memory than is
2790 strictly needed, but it simplifies the code. */
2793 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2795 if (new_rtx
!= XEXP (x
, 1))
2797 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2805 /* We do not support elimination of a register that is modified.
2806 elimination_effects has already make sure that this does not
2812 /* We do not support elimination of a register that is modified.
2813 elimination_effects has already make sure that this does not
2814 happen. The only remaining case we need to consider here is
2815 that the increment value may be an eliminable register. */
2816 if (GET_CODE (XEXP (x
, 1)) == PLUS
2817 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2819 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2820 insn
, true, for_costs
);
2822 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2823 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2824 gen_rtx_PLUS (GET_MODE (x
),
2825 XEXP (x
, 0), new_rtx
));
2829 case STRICT_LOW_PART
:
2831 case SIGN_EXTEND
: case ZERO_EXTEND
:
2832 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2833 case FLOAT
: case FIX
:
2834 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2843 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2845 if (new_rtx
!= XEXP (x
, 0))
2846 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2850 /* Similar to above processing, but preserve SUBREG_BYTE.
2851 Convert (subreg (mem)) to (mem) if not paradoxical.
2852 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2853 pseudo didn't get a hard reg, we must replace this with the
2854 eliminated version of the memory location because push_reload
2855 may do the replacement in certain circumstances. */
2856 if (REG_P (SUBREG_REG (x
))
2857 && !paradoxical_subreg_p (x
)
2859 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2861 new_rtx
= SUBREG_REG (x
);
2864 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2866 if (new_rtx
!= SUBREG_REG (x
))
2868 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2869 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2872 && ((x_size
< new_size
2873 #ifdef WORD_REGISTER_OPERATIONS
2874 /* On these machines, combine can create rtl of the form
2875 (set (subreg:m1 (reg:m2 R) 0) ...)
2876 where m1 < m2, and expects something interesting to
2877 happen to the entire word. Moreover, it will use the
2878 (reg:m2 R) later, expecting all bits to be preserved.
2879 So if the number of words is the same, preserve the
2880 subreg so that push_reload can see it. */
2881 && ! ((x_size
- 1) / UNITS_PER_WORD
2882 == (new_size
-1 ) / UNITS_PER_WORD
)
2885 || x_size
== new_size
)
2887 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2889 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2895 /* Our only special processing is to pass the mode of the MEM to our
2896 recursive call and copy the flags. While we are here, handle this
2897 case more efficiently. */
2899 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2902 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2903 && !memory_address_p (GET_MODE (x
), new_rtx
))
2904 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2906 return replace_equiv_address_nv (x
, new_rtx
);
2909 /* Handle insn_list USE that a call to a pure function may generate. */
2910 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2912 if (new_rtx
!= XEXP (x
, 0))
2913 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2918 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2928 /* Process each of our operands recursively. If any have changed, make a
2930 fmt
= GET_RTX_FORMAT (code
);
2931 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2935 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2937 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2939 x
= shallow_copy_rtx (x
);
2942 XEXP (x
, i
) = new_rtx
;
2944 else if (*fmt
== 'E')
2947 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2949 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2951 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2953 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2957 x
= shallow_copy_rtx (x
);
2960 XVEC (x
, i
) = new_v
;
2963 XVECEXP (x
, i
, j
) = new_rtx
;
2972 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2974 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2977 /* Scan rtx X for modifications of elimination target registers. Update
2978 the table of eliminables to reflect the changed state. MEM_MODE is
2979 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2982 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2984 enum rtx_code code
= GET_CODE (x
);
2985 struct elim_table
*ep
;
3007 /* First handle the case where we encounter a bare register that
3008 is eliminable. Replace it with a PLUS. */
3009 if (regno
< FIRST_PSEUDO_REGISTER
)
3011 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3013 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3016 ep
->ref_outside_mem
= 1;
3021 else if (reg_renumber
[regno
] < 0
3023 && reg_equiv_constant (regno
)
3024 && ! function_invariant_p (reg_equiv_constant (regno
)))
3025 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3034 /* If we modify the source of an elimination rule, disable it. */
3035 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3036 if (ep
->from_rtx
== XEXP (x
, 0))
3037 ep
->can_eliminate
= 0;
3039 /* If we modify the target of an elimination rule by adding a constant,
3040 update its offset. If we modify the target in any other way, we'll
3041 have to disable the rule as well. */
3042 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3043 if (ep
->to_rtx
== XEXP (x
, 0))
3045 int size
= GET_MODE_SIZE (mem_mode
);
3047 /* If more bytes than MEM_MODE are pushed, account for them. */
3048 #ifdef PUSH_ROUNDING
3049 if (ep
->to_rtx
== stack_pointer_rtx
)
3050 size
= PUSH_ROUNDING (size
);
3052 if (code
== PRE_DEC
|| code
== POST_DEC
)
3054 else if (code
== PRE_INC
|| code
== POST_INC
)
3056 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3058 if (GET_CODE (XEXP (x
, 1)) == PLUS
3059 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3060 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3061 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3063 ep
->can_eliminate
= 0;
3067 /* These two aren't unary operators. */
3068 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3071 /* Fall through to generic unary operation case. */
3072 case STRICT_LOW_PART
:
3074 case SIGN_EXTEND
: case ZERO_EXTEND
:
3075 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3076 case FLOAT
: case FIX
:
3077 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3086 elimination_effects (XEXP (x
, 0), mem_mode
);
3090 if (REG_P (SUBREG_REG (x
))
3091 && (GET_MODE_SIZE (GET_MODE (x
))
3092 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3094 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3097 elimination_effects (SUBREG_REG (x
), mem_mode
);
3101 /* If using a register that is the source of an eliminate we still
3102 think can be performed, note it cannot be performed since we don't
3103 know how this register is used. */
3104 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3105 if (ep
->from_rtx
== XEXP (x
, 0))
3106 ep
->can_eliminate
= 0;
3108 elimination_effects (XEXP (x
, 0), mem_mode
);
3112 /* If clobbering a register that is the replacement register for an
3113 elimination we still think can be performed, note that it cannot
3114 be performed. Otherwise, we need not be concerned about it. */
3115 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3116 if (ep
->to_rtx
== XEXP (x
, 0))
3117 ep
->can_eliminate
= 0;
3119 elimination_effects (XEXP (x
, 0), mem_mode
);
3123 /* Check for setting a register that we know about. */
3124 if (REG_P (SET_DEST (x
)))
3126 /* See if this is setting the replacement register for an
3129 If DEST is the hard frame pointer, we do nothing because we
3130 assume that all assignments to the frame pointer are for
3131 non-local gotos and are being done at a time when they are valid
3132 and do not disturb anything else. Some machines want to
3133 eliminate a fake argument pointer (or even a fake frame pointer)
3134 with either the real frame or the stack pointer. Assignments to
3135 the hard frame pointer must not prevent this elimination. */
3137 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3139 if (ep
->to_rtx
== SET_DEST (x
)
3140 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3142 /* If it is being incremented, adjust the offset. Otherwise,
3143 this elimination can't be done. */
3144 rtx src
= SET_SRC (x
);
3146 if (GET_CODE (src
) == PLUS
3147 && XEXP (src
, 0) == SET_DEST (x
)
3148 && CONST_INT_P (XEXP (src
, 1)))
3149 ep
->offset
-= INTVAL (XEXP (src
, 1));
3151 ep
->can_eliminate
= 0;
3155 elimination_effects (SET_DEST (x
), VOIDmode
);
3156 elimination_effects (SET_SRC (x
), VOIDmode
);
3160 /* Our only special processing is to pass the mode of the MEM to our
3162 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3169 fmt
= GET_RTX_FORMAT (code
);
3170 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3173 elimination_effects (XEXP (x
, i
), mem_mode
);
3174 else if (*fmt
== 'E')
3175 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3176 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3180 /* Descend through rtx X and verify that no references to eliminable registers
3181 remain. If any do remain, mark the involved register as not
3185 check_eliminable_occurrences (rtx x
)
3194 code
= GET_CODE (x
);
3196 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3198 struct elim_table
*ep
;
3200 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3201 if (ep
->from_rtx
== x
)
3202 ep
->can_eliminate
= 0;
3206 fmt
= GET_RTX_FORMAT (code
);
3207 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3210 check_eliminable_occurrences (XEXP (x
, i
));
3211 else if (*fmt
== 'E')
3214 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3215 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3220 /* Scan INSN and eliminate all eliminable registers in it.
3222 If REPLACE is nonzero, do the replacement destructively. Also
3223 delete the insn as dead it if it is setting an eliminable register.
3225 If REPLACE is zero, do all our allocations in reload_obstack.
3227 If no eliminations were done and this insn doesn't require any elimination
3228 processing (these are not identical conditions: it might be updating sp,
3229 but not referencing fp; this needs to be seen during reload_as_needed so
3230 that the offset between fp and sp can be taken into consideration), zero
3231 is returned. Otherwise, 1 is returned. */
3234 eliminate_regs_in_insn (rtx insn
, int replace
)
3236 int icode
= recog_memoized (insn
);
3237 rtx old_body
= PATTERN (insn
);
3238 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3239 rtx old_set
= single_set (insn
);
3243 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3244 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3245 struct elim_table
*ep
;
3246 rtx plus_src
, plus_cst_src
;
3248 if (! insn_is_asm
&& icode
< 0)
3250 gcc_assert (DEBUG_INSN_P (insn
)
3251 || GET_CODE (PATTERN (insn
)) == USE
3252 || GET_CODE (PATTERN (insn
)) == CLOBBER
3253 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3254 if (DEBUG_INSN_P (insn
))
3255 INSN_VAR_LOCATION_LOC (insn
)
3256 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3260 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3261 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3263 /* Check for setting an eliminable register. */
3264 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3265 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3267 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3268 /* If this is setting the frame pointer register to the
3269 hardware frame pointer register and this is an elimination
3270 that will be done (tested above), this insn is really
3271 adjusting the frame pointer downward to compensate for
3272 the adjustment done before a nonlocal goto. */
3273 if (ep
->from
== FRAME_POINTER_REGNUM
3274 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3276 rtx base
= SET_SRC (old_set
);
3277 rtx base_insn
= insn
;
3278 HOST_WIDE_INT offset
= 0;
3280 while (base
!= ep
->to_rtx
)
3282 rtx prev_insn
, prev_set
;
3284 if (GET_CODE (base
) == PLUS
3285 && CONST_INT_P (XEXP (base
, 1)))
3287 offset
+= INTVAL (XEXP (base
, 1));
3288 base
= XEXP (base
, 0);
3290 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3291 && (prev_set
= single_set (prev_insn
)) != 0
3292 && rtx_equal_p (SET_DEST (prev_set
), base
))
3294 base
= SET_SRC (prev_set
);
3295 base_insn
= prev_insn
;
3301 if (base
== ep
->to_rtx
)
3303 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3304 offset
- ep
->offset
);
3306 new_body
= old_body
;
3309 new_body
= copy_insn (old_body
);
3310 if (REG_NOTES (insn
))
3311 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3313 PATTERN (insn
) = new_body
;
3314 old_set
= single_set (insn
);
3316 /* First see if this insn remains valid when we
3317 make the change. If not, keep the INSN_CODE
3318 the same and let reload fit it up. */
3319 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3320 validate_change (insn
, &SET_DEST (old_set
),
3322 if (! apply_change_group ())
3324 SET_SRC (old_set
) = src
;
3325 SET_DEST (old_set
) = ep
->to_rtx
;
3334 /* In this case this insn isn't serving a useful purpose. We
3335 will delete it in reload_as_needed once we know that this
3336 elimination is, in fact, being done.
3338 If REPLACE isn't set, we can't delete this insn, but needn't
3339 process it since it won't be used unless something changes. */
3342 delete_dead_insn (insn
);
3350 /* We allow one special case which happens to work on all machines we
3351 currently support: a single set with the source or a REG_EQUAL
3352 note being a PLUS of an eliminable register and a constant. */
3353 plus_src
= plus_cst_src
= 0;
3354 if (old_set
&& REG_P (SET_DEST (old_set
)))
3356 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3357 plus_src
= SET_SRC (old_set
);
3358 /* First see if the source is of the form (plus (...) CST). */
3360 && CONST_INT_P (XEXP (plus_src
, 1)))
3361 plus_cst_src
= plus_src
;
3362 else if (REG_P (SET_SRC (old_set
))
3365 /* Otherwise, see if we have a REG_EQUAL note of the form
3366 (plus (...) CST). */
3368 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3370 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3371 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3372 && GET_CODE (XEXP (links
, 0)) == PLUS
3373 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3375 plus_cst_src
= XEXP (links
, 0);
3381 /* Check that the first operand of the PLUS is a hard reg or
3382 the lowpart subreg of one. */
3385 rtx reg
= XEXP (plus_cst_src
, 0);
3386 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3387 reg
= SUBREG_REG (reg
);
3389 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3395 rtx reg
= XEXP (plus_cst_src
, 0);
3396 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3398 if (GET_CODE (reg
) == SUBREG
)
3399 reg
= SUBREG_REG (reg
);
3401 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3402 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3404 rtx to_rtx
= ep
->to_rtx
;
3405 offset
+= ep
->offset
;
3406 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3408 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3409 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3411 /* If we have a nonzero offset, and the source is already
3412 a simple REG, the following transformation would
3413 increase the cost of the insn by replacing a simple REG
3414 with (plus (reg sp) CST). So try only when we already
3415 had a PLUS before. */
3416 if (offset
== 0 || plus_src
)
3418 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3421 new_body
= old_body
;
3424 new_body
= copy_insn (old_body
);
3425 if (REG_NOTES (insn
))
3426 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3428 PATTERN (insn
) = new_body
;
3429 old_set
= single_set (insn
);
3431 /* First see if this insn remains valid when we make the
3432 change. If not, try to replace the whole pattern with
3433 a simple set (this may help if the original insn was a
3434 PARALLEL that was only recognized as single_set due to
3435 REG_UNUSED notes). If this isn't valid either, keep
3436 the INSN_CODE the same and let reload fix it up. */
3437 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3439 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3440 SET_DEST (old_set
), new_src
);
3442 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3443 SET_SRC (old_set
) = new_src
;
3450 /* This can't have an effect on elimination offsets, so skip right
3456 /* Determine the effects of this insn on elimination offsets. */
3457 elimination_effects (old_body
, VOIDmode
);
3459 /* Eliminate all eliminable registers occurring in operands that
3460 can be handled by reload. */
3461 extract_insn (insn
);
3462 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3464 orig_operand
[i
] = recog_data
.operand
[i
];
3465 substed_operand
[i
] = recog_data
.operand
[i
];
3467 /* For an asm statement, every operand is eliminable. */
3468 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3470 bool is_set_src
, in_plus
;
3472 /* Check for setting a register that we know about. */
3473 if (recog_data
.operand_type
[i
] != OP_IN
3474 && REG_P (orig_operand
[i
]))
3476 /* If we are assigning to a register that can be eliminated, it
3477 must be as part of a PARALLEL, since the code above handles
3478 single SETs. We must indicate that we can no longer
3479 eliminate this reg. */
3480 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3482 if (ep
->from_rtx
== orig_operand
[i
])
3483 ep
->can_eliminate
= 0;
3486 /* Companion to the above plus substitution, we can allow
3487 invariants as the source of a plain move. */
3490 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3494 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3495 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3499 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3500 replace
? insn
: NULL_RTX
,
3501 is_set_src
|| in_plus
, false);
3502 if (substed_operand
[i
] != orig_operand
[i
])
3504 /* Terminate the search in check_eliminable_occurrences at
3506 *recog_data
.operand_loc
[i
] = 0;
3508 /* If an output operand changed from a REG to a MEM and INSN is an
3509 insn, write a CLOBBER insn. */
3510 if (recog_data
.operand_type
[i
] != OP_IN
3511 && REG_P (orig_operand
[i
])
3512 && MEM_P (substed_operand
[i
])
3514 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3518 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3519 *recog_data
.dup_loc
[i
]
3520 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3522 /* If any eliminable remain, they aren't eliminable anymore. */
3523 check_eliminable_occurrences (old_body
);
3525 /* Substitute the operands; the new values are in the substed_operand
3527 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3528 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3529 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3530 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3532 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3533 re-recognize the insn. We do this in case we had a simple addition
3534 but now can do this as a load-address. This saves an insn in this
3536 If re-recognition fails, the old insn code number will still be used,
3537 and some register operands may have changed into PLUS expressions.
3538 These will be handled by find_reloads by loading them into a register
3543 /* If we aren't replacing things permanently and we changed something,
3544 make another copy to ensure that all the RTL is new. Otherwise
3545 things can go wrong if find_reload swaps commutative operands
3546 and one is inside RTL that has been copied while the other is not. */
3547 new_body
= old_body
;
3550 new_body
= copy_insn (old_body
);
3551 if (REG_NOTES (insn
))
3552 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3554 PATTERN (insn
) = new_body
;
3556 /* If we had a move insn but now we don't, rerecognize it. This will
3557 cause spurious re-recognition if the old move had a PARALLEL since
3558 the new one still will, but we can't call single_set without
3559 having put NEW_BODY into the insn and the re-recognition won't
3560 hurt in this rare case. */
3561 /* ??? Why this huge if statement - why don't we just rerecognize the
3565 && ((REG_P (SET_SRC (old_set
))
3566 && (GET_CODE (new_body
) != SET
3567 || !REG_P (SET_SRC (new_body
))))
3568 /* If this was a load from or store to memory, compare
3569 the MEM in recog_data.operand to the one in the insn.
3570 If they are not equal, then rerecognize the insn. */
3572 && ((MEM_P (SET_SRC (old_set
))
3573 && SET_SRC (old_set
) != recog_data
.operand
[1])
3574 || (MEM_P (SET_DEST (old_set
))
3575 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3576 /* If this was an add insn before, rerecognize. */
3577 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3579 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3581 INSN_CODE (insn
) = new_icode
;
3585 /* Restore the old body. If there were any changes to it, we made a copy
3586 of it while the changes were still in place, so we'll correctly return
3587 a modified insn below. */
3590 /* Restore the old body. */
3591 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3592 /* Restoring a top-level match_parallel would clobber the new_body
3593 we installed in the insn. */
3594 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3595 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3596 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3597 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3600 /* Update all elimination pairs to reflect the status after the current
3601 insn. The changes we make were determined by the earlier call to
3602 elimination_effects.
3604 We also detect cases where register elimination cannot be done,
3605 namely, if a register would be both changed and referenced outside a MEM
3606 in the resulting insn since such an insn is often undefined and, even if
3607 not, we cannot know what meaning will be given to it. Note that it is
3608 valid to have a register used in an address in an insn that changes it
3609 (presumably with a pre- or post-increment or decrement).
3611 If anything changes, return nonzero. */
3613 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3615 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3616 ep
->can_eliminate
= 0;
3618 ep
->ref_outside_mem
= 0;
3620 if (ep
->previous_offset
!= ep
->offset
)
3625 /* If we changed something, perform elimination in REG_NOTES. This is
3626 needed even when REPLACE is zero because a REG_DEAD note might refer
3627 to a register that we eliminate and could cause a different number
3628 of spill registers to be needed in the final reload pass than in
3630 if (val
&& REG_NOTES (insn
) != 0)
3632 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3638 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3639 register allocator. INSN is the instruction we need to examine, we perform
3640 eliminations in its operands and record cases where eliminating a reg with
3641 an invariant equivalence would add extra cost. */
3644 elimination_costs_in_insn (rtx insn
)
3646 int icode
= recog_memoized (insn
);
3647 rtx old_body
= PATTERN (insn
);
3648 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3649 rtx old_set
= single_set (insn
);
3651 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3652 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3653 struct elim_table
*ep
;
3654 rtx plus_src
, plus_cst_src
;
3657 if (! insn_is_asm
&& icode
< 0)
3659 gcc_assert (DEBUG_INSN_P (insn
)
3660 || GET_CODE (PATTERN (insn
)) == USE
3661 || GET_CODE (PATTERN (insn
)) == CLOBBER
3662 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3666 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3667 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3669 /* Check for setting an eliminable register. */
3670 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3671 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3675 /* We allow one special case which happens to work on all machines we
3676 currently support: a single set with the source or a REG_EQUAL
3677 note being a PLUS of an eliminable register and a constant. */
3678 plus_src
= plus_cst_src
= 0;
3680 if (old_set
&& REG_P (SET_DEST (old_set
)))
3683 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3684 plus_src
= SET_SRC (old_set
);
3685 /* First see if the source is of the form (plus (...) CST). */
3687 && CONST_INT_P (XEXP (plus_src
, 1)))
3688 plus_cst_src
= plus_src
;
3689 else if (REG_P (SET_SRC (old_set
))
3692 /* Otherwise, see if we have a REG_EQUAL note of the form
3693 (plus (...) CST). */
3695 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3697 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3698 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3699 && GET_CODE (XEXP (links
, 0)) == PLUS
3700 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3702 plus_cst_src
= XEXP (links
, 0);
3709 /* Determine the effects of this insn on elimination offsets. */
3710 elimination_effects (old_body
, VOIDmode
);
3712 /* Eliminate all eliminable registers occurring in operands that
3713 can be handled by reload. */
3714 extract_insn (insn
);
3715 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3716 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3718 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3720 orig_operand
[i
] = recog_data
.operand
[i
];
3722 /* For an asm statement, every operand is eliminable. */
3723 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3725 bool is_set_src
, in_plus
;
3727 /* Check for setting a register that we know about. */
3728 if (recog_data
.operand_type
[i
] != OP_IN
3729 && REG_P (orig_operand
[i
]))
3731 /* If we are assigning to a register that can be eliminated, it
3732 must be as part of a PARALLEL, since the code above handles
3733 single SETs. We must indicate that we can no longer
3734 eliminate this reg. */
3735 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3737 if (ep
->from_rtx
== orig_operand
[i
])
3738 ep
->can_eliminate
= 0;
3741 /* Companion to the above plus substitution, we can allow
3742 invariants as the source of a plain move. */
3744 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3746 if (is_set_src
&& !sets_reg_p
)
3747 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3749 if (plus_src
&& sets_reg_p
3750 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3751 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3754 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3756 is_set_src
|| in_plus
, true);
3757 /* Terminate the search in check_eliminable_occurrences at
3759 *recog_data
.operand_loc
[i
] = 0;
3763 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3764 *recog_data
.dup_loc
[i
]
3765 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3767 /* If any eliminable remain, they aren't eliminable anymore. */
3768 check_eliminable_occurrences (old_body
);
3770 /* Restore the old body. */
3771 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3772 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3773 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3774 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3776 /* Update all elimination pairs to reflect the status after the current
3777 insn. The changes we make were determined by the earlier call to
3778 elimination_effects. */
3780 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3782 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3783 ep
->can_eliminate
= 0;
3785 ep
->ref_outside_mem
= 0;
3791 /* Loop through all elimination pairs.
3792 Recalculate the number not at initial offset.
3794 Compute the maximum offset (minimum offset if the stack does not
3795 grow downward) for each elimination pair. */
3798 update_eliminable_offsets (void)
3800 struct elim_table
*ep
;
3802 num_not_at_initial_offset
= 0;
3803 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3805 ep
->previous_offset
= ep
->offset
;
3806 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3807 num_not_at_initial_offset
++;
3811 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3812 replacement we currently believe is valid, mark it as not eliminable if X
3813 modifies DEST in any way other than by adding a constant integer to it.
3815 If DEST is the frame pointer, we do nothing because we assume that
3816 all assignments to the hard frame pointer are nonlocal gotos and are being
3817 done at a time when they are valid and do not disturb anything else.
3818 Some machines want to eliminate a fake argument pointer with either the
3819 frame or stack pointer. Assignments to the hard frame pointer must not
3820 prevent this elimination.
3822 Called via note_stores from reload before starting its passes to scan
3823 the insns of the function. */
3826 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3830 /* A SUBREG of a hard register here is just changing its mode. We should
3831 not see a SUBREG of an eliminable hard register, but check just in
3833 if (GET_CODE (dest
) == SUBREG
)
3834 dest
= SUBREG_REG (dest
);
3836 if (dest
== hard_frame_pointer_rtx
)
3839 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3840 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3841 && (GET_CODE (x
) != SET
3842 || GET_CODE (SET_SRC (x
)) != PLUS
3843 || XEXP (SET_SRC (x
), 0) != dest
3844 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3846 reg_eliminate
[i
].can_eliminate_previous
3847 = reg_eliminate
[i
].can_eliminate
= 0;
3852 /* Verify that the initial elimination offsets did not change since the
3853 last call to set_initial_elim_offsets. This is used to catch cases
3854 where something illegal happened during reload_as_needed that could
3855 cause incorrect code to be generated if we did not check for it. */
3858 verify_initial_elim_offsets (void)
3862 if (!num_eliminable
)
3865 #ifdef ELIMINABLE_REGS
3867 struct elim_table
*ep
;
3869 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3871 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3872 if (t
!= ep
->initial_offset
)
3877 INITIAL_FRAME_POINTER_OFFSET (t
);
3878 if (t
!= reg_eliminate
[0].initial_offset
)
3885 /* Reset all offsets on eliminable registers to their initial values. */
3888 set_initial_elim_offsets (void)
3890 struct elim_table
*ep
= reg_eliminate
;
3892 #ifdef ELIMINABLE_REGS
3893 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3895 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3896 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3899 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3900 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3903 num_not_at_initial_offset
= 0;
3906 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3909 set_initial_eh_label_offset (rtx label
)
3911 set_label_offsets (label
, NULL_RTX
, 1);
3914 /* Initialize the known label offsets.
3915 Set a known offset for each forced label to be at the initial offset
3916 of each elimination. We do this because we assume that all
3917 computed jumps occur from a location where each elimination is
3918 at its initial offset.
3919 For all other labels, show that we don't know the offsets. */
3922 set_initial_label_offsets (void)
3925 memset (offsets_known_at
, 0, num_labels
);
3927 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3929 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3931 for (x
= nonlocal_goto_handler_labels
; x
; x
= XEXP (x
, 1))
3933 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3935 for_each_eh_label (set_initial_eh_label_offset
);
3938 /* Set all elimination offsets to the known values for the code label given
3942 set_offsets_for_label (rtx insn
)
3945 int label_nr
= CODE_LABEL_NUMBER (insn
);
3946 struct elim_table
*ep
;
3948 num_not_at_initial_offset
= 0;
3949 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3951 ep
->offset
= ep
->previous_offset
3952 = offsets_at
[label_nr
- first_label_num
][i
];
3953 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3954 num_not_at_initial_offset
++;
3958 /* See if anything that happened changes which eliminations are valid.
3959 For example, on the SPARC, whether or not the frame pointer can
3960 be eliminated can depend on what registers have been used. We need
3961 not check some conditions again (such as flag_omit_frame_pointer)
3962 since they can't have changed. */
3965 update_eliminables (HARD_REG_SET
*pset
)
3967 int previous_frame_pointer_needed
= frame_pointer_needed
;
3968 struct elim_table
*ep
;
3970 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3971 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3972 && targetm
.frame_pointer_required ())
3973 #ifdef ELIMINABLE_REGS
3974 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3977 ep
->can_eliminate
= 0;
3979 /* Look for the case where we have discovered that we can't replace
3980 register A with register B and that means that we will now be
3981 trying to replace register A with register C. This means we can
3982 no longer replace register C with register B and we need to disable
3983 such an elimination, if it exists. This occurs often with A == ap,
3984 B == sp, and C == fp. */
3986 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3988 struct elim_table
*op
;
3991 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3993 /* Find the current elimination for ep->from, if there is a
3995 for (op
= reg_eliminate
;
3996 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3997 if (op
->from
== ep
->from
&& op
->can_eliminate
)
4003 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
4005 for (op
= reg_eliminate
;
4006 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
4007 if (op
->from
== new_to
&& op
->to
== ep
->to
)
4008 op
->can_eliminate
= 0;
4012 /* See if any registers that we thought we could eliminate the previous
4013 time are no longer eliminable. If so, something has changed and we
4014 must spill the register. Also, recompute the number of eliminable
4015 registers and see if the frame pointer is needed; it is if there is
4016 no elimination of the frame pointer that we can perform. */
4018 frame_pointer_needed
= 1;
4019 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4021 if (ep
->can_eliminate
4022 && ep
->from
== FRAME_POINTER_REGNUM
4023 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4024 && (! SUPPORTS_STACK_ALIGNMENT
4025 || ! crtl
->stack_realign_needed
))
4026 frame_pointer_needed
= 0;
4028 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4030 ep
->can_eliminate_previous
= 0;
4031 SET_HARD_REG_BIT (*pset
, ep
->from
);
4036 /* If we didn't need a frame pointer last time, but we do now, spill
4037 the hard frame pointer. */
4038 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4039 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4042 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4043 Return true iff a register was spilled. */
4046 update_eliminables_and_spill (void)
4049 bool did_spill
= false;
4050 HARD_REG_SET to_spill
;
4051 CLEAR_HARD_REG_SET (to_spill
);
4052 update_eliminables (&to_spill
);
4053 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
4055 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4056 if (TEST_HARD_REG_BIT (to_spill
, i
))
4058 spill_hard_reg (i
, 1);
4061 /* Regardless of the state of spills, if we previously had
4062 a register that we thought we could eliminate, but now can
4063 not eliminate, we must run another pass.
4065 Consider pseudos which have an entry in reg_equiv_* which
4066 reference an eliminable register. We must make another pass
4067 to update reg_equiv_* so that we do not substitute in the
4068 old value from when we thought the elimination could be
4074 /* Return true if X is used as the target register of an elimination. */
4077 elimination_target_reg_p (rtx x
)
4079 struct elim_table
*ep
;
4081 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4082 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4088 /* Initialize the table of registers to eliminate.
4089 Pre-condition: global flag frame_pointer_needed has been set before
4090 calling this function. */
4093 init_elim_table (void)
4095 struct elim_table
*ep
;
4096 #ifdef ELIMINABLE_REGS
4097 const struct elim_table_1
*ep1
;
4101 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4105 #ifdef ELIMINABLE_REGS
4106 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4107 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4109 ep
->from
= ep1
->from
;
4111 ep
->can_eliminate
= ep
->can_eliminate_previous
4112 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4113 && ! (ep
->to
== STACK_POINTER_REGNUM
4114 && frame_pointer_needed
4115 && (! SUPPORTS_STACK_ALIGNMENT
4116 || ! stack_realign_fp
)));
4119 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4120 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4121 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4122 = ! frame_pointer_needed
;
4125 /* Count the number of eliminable registers and build the FROM and TO
4126 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4127 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4128 We depend on this. */
4129 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4131 num_eliminable
+= ep
->can_eliminate
;
4132 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4133 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4137 /* Find all the pseudo registers that didn't get hard regs
4138 but do have known equivalent constants or memory slots.
4139 These include parameters (known equivalent to parameter slots)
4140 and cse'd or loop-moved constant memory addresses.
4142 Record constant equivalents in reg_equiv_constant
4143 so they will be substituted by find_reloads.
4144 Record memory equivalents in reg_mem_equiv so they can
4145 be substituted eventually by altering the REG-rtx's. */
4148 init_eliminable_invariants (rtx first
, bool do_subregs
)
4155 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4157 reg_max_ref_width
= NULL
;
4159 num_eliminable_invariants
= 0;
4161 first_label_num
= get_first_label_num ();
4162 num_labels
= max_label_num () - first_label_num
;
4164 /* Allocate the tables used to store offset information at labels. */
4165 offsets_known_at
= XNEWVEC (char, num_labels
);
4166 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4168 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4169 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4170 find largest such for each pseudo. FIRST is the head of the insn
4173 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4175 rtx set
= single_set (insn
);
4177 /* We may introduce USEs that we want to remove at the end, so
4178 we'll mark them with QImode. Make sure there are no
4179 previously-marked insns left by say regmove. */
4180 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4181 && GET_MODE (insn
) != VOIDmode
)
4182 PUT_MODE (insn
, VOIDmode
);
4184 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4185 scan_paradoxical_subregs (PATTERN (insn
));
4187 if (set
!= 0 && REG_P (SET_DEST (set
)))
4189 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4195 i
= REGNO (SET_DEST (set
));
4198 if (i
<= LAST_VIRTUAL_REGISTER
)
4201 /* If flag_pic and we have constant, verify it's legitimate. */
4203 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4205 /* It can happen that a REG_EQUIV note contains a MEM
4206 that is not a legitimate memory operand. As later
4207 stages of reload assume that all addresses found
4208 in the reg_equiv_* arrays were originally legitimate,
4209 we ignore such REG_EQUIV notes. */
4210 if (memory_operand (x
, VOIDmode
))
4212 /* Always unshare the equivalence, so we can
4213 substitute into this insn without touching the
4215 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4217 else if (function_invariant_p (x
))
4219 enum machine_mode mode
;
4221 mode
= GET_MODE (SET_DEST (set
));
4222 if (GET_CODE (x
) == PLUS
)
4224 /* This is PLUS of frame pointer and a constant,
4225 and might be shared. Unshare it. */
4226 reg_equiv_invariant (i
) = copy_rtx (x
);
4227 num_eliminable_invariants
++;
4229 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4231 reg_equiv_invariant (i
) = x
;
4232 num_eliminable_invariants
++;
4234 else if (targetm
.legitimate_constant_p (mode
, x
))
4235 reg_equiv_constant (i
) = x
;
4238 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4239 if (! reg_equiv_memory_loc (i
))
4240 reg_equiv_init (i
) = NULL_RTX
;
4245 reg_equiv_init (i
) = NULL_RTX
;
4250 reg_equiv_init (i
) = NULL_RTX
;
4255 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4256 if (reg_equiv_init (i
))
4258 fprintf (dump_file
, "init_insns for %u: ", i
);
4259 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4260 fprintf (dump_file
, "\n");
4264 /* Indicate that we no longer have known memory locations or constants.
4265 Free all data involved in tracking these. */
4268 free_reg_equiv (void)
4272 free (offsets_known_at
);
4275 offsets_known_at
= 0;
4277 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4278 if (reg_equiv_alt_mem_list (i
))
4279 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4280 vec_free (reg_equivs
);
4283 /* Kick all pseudos out of hard register REGNO.
4285 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4286 because we found we can't eliminate some register. In the case, no pseudos
4287 are allowed to be in the register, even if they are only in a block that
4288 doesn't require spill registers, unlike the case when we are spilling this
4289 hard reg to produce another spill register.
4291 Return nonzero if any pseudos needed to be kicked out. */
4294 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4300 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4301 df_set_regs_ever_live (regno
, true);
4304 /* Spill every pseudo reg that was allocated to this reg
4305 or to something that overlaps this reg. */
4307 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4308 if (reg_renumber
[i
] >= 0
4309 && (unsigned int) reg_renumber
[i
] <= regno
4310 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4311 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4314 /* After find_reload_regs has been run for all insn that need reloads,
4315 and/or spill_hard_regs was called, this function is used to actually
4316 spill pseudo registers and try to reallocate them. It also sets up the
4317 spill_regs array for use by choose_reload_regs. */
4320 finish_spills (int global
)
4322 struct insn_chain
*chain
;
4323 int something_changed
= 0;
4325 reg_set_iterator rsi
;
4327 /* Build the spill_regs array for the function. */
4328 /* If there are some registers still to eliminate and one of the spill regs
4329 wasn't ever used before, additional stack space may have to be
4330 allocated to store this register. Thus, we may have changed the offset
4331 between the stack and frame pointers, so mark that something has changed.
4333 One might think that we need only set VAL to 1 if this is a call-used
4334 register. However, the set of registers that must be saved by the
4335 prologue is not identical to the call-used set. For example, the
4336 register used by the call insn for the return PC is a call-used register,
4337 but must be saved by the prologue. */
4340 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4341 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4343 spill_reg_order
[i
] = n_spills
;
4344 spill_regs
[n_spills
++] = i
;
4345 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4346 something_changed
= 1;
4347 df_set_regs_ever_live (i
, true);
4350 spill_reg_order
[i
] = -1;
4352 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4353 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4355 /* Record the current hard register the pseudo is allocated to
4356 in pseudo_previous_regs so we avoid reallocating it to the
4357 same hard reg in a later pass. */
4358 gcc_assert (reg_renumber
[i
] >= 0);
4360 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4361 /* Mark it as no longer having a hard register home. */
4362 reg_renumber
[i
] = -1;
4363 if (ira_conflicts_p
)
4364 /* Inform IRA about the change. */
4365 ira_mark_allocation_change (i
);
4366 /* We will need to scan everything again. */
4367 something_changed
= 1;
4370 /* Retry global register allocation if possible. */
4371 if (global
&& ira_conflicts_p
)
4375 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4376 /* For every insn that needs reloads, set the registers used as spill
4377 regs in pseudo_forbidden_regs for every pseudo live across the
4379 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4381 EXECUTE_IF_SET_IN_REG_SET
4382 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4384 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4385 chain
->used_spill_regs
);
4387 EXECUTE_IF_SET_IN_REG_SET
4388 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4390 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4391 chain
->used_spill_regs
);
4395 /* Retry allocating the pseudos spilled in IRA and the
4396 reload. For each reg, merge the various reg sets that
4397 indicate which hard regs can't be used, and call
4398 ira_reassign_pseudos. */
4399 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4400 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4402 if (reg_renumber
[i
] < 0)
4403 temp_pseudo_reg_arr
[n
++] = i
;
4405 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4407 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4408 bad_spill_regs_global
,
4409 pseudo_forbidden_regs
, pseudo_previous_regs
,
4411 something_changed
= 1;
4413 /* Fix up the register information in the insn chain.
4414 This involves deleting those of the spilled pseudos which did not get
4415 a new hard register home from the live_{before,after} sets. */
4416 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4418 HARD_REG_SET used_by_pseudos
;
4419 HARD_REG_SET used_by_pseudos2
;
4421 if (! ira_conflicts_p
)
4423 /* Don't do it for IRA because IRA and the reload still can
4424 assign hard registers to the spilled pseudos on next
4425 reload iterations. */
4426 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4427 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4429 /* Mark any unallocated hard regs as available for spills. That
4430 makes inheritance work somewhat better. */
4431 if (chain
->need_reload
)
4433 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4434 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4435 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4437 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4438 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4439 /* Value of chain->used_spill_regs from previous iteration
4440 may be not included in the value calculated here because
4441 of possible removing caller-saves insns (see function
4442 delete_caller_save_insns. */
4443 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4444 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4448 CLEAR_REG_SET (&changed_allocation_pseudos
);
4449 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4450 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4452 int regno
= reg_renumber
[i
];
4453 if (reg_old_renumber
[i
] == regno
)
4456 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4458 alter_reg (i
, reg_old_renumber
[i
], false);
4459 reg_old_renumber
[i
] = regno
;
4463 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4465 fprintf (dump_file
, " Register %d now in %d.\n\n",
4466 i
, reg_renumber
[i
]);
4470 return something_changed
;
4473 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4476 scan_paradoxical_subregs (rtx x
)
4480 enum rtx_code code
= GET_CODE (x
);
4496 if (REG_P (SUBREG_REG (x
))
4497 && (GET_MODE_SIZE (GET_MODE (x
))
4498 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4500 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4501 = GET_MODE_SIZE (GET_MODE (x
));
4502 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4510 fmt
= GET_RTX_FORMAT (code
);
4511 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4514 scan_paradoxical_subregs (XEXP (x
, i
));
4515 else if (fmt
[i
] == 'E')
4518 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4519 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4524 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4525 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4526 and apply the corresponding narrowing subreg to *OTHER_PTR.
4527 Return true if the operands were changed, false otherwise. */
4530 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4532 rtx op
, inner
, other
, tem
;
4535 if (!paradoxical_subreg_p (op
))
4537 inner
= SUBREG_REG (op
);
4540 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4544 /* If the lowpart operation turned a hard register into a subreg,
4545 rather than simplifying it to another hard register, then the
4546 mode change cannot be properly represented. For example, OTHER
4547 might be valid in its current mode, but not in the new one. */
4548 if (GET_CODE (tem
) == SUBREG
4550 && HARD_REGISTER_P (other
))
4558 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4559 examine all of the reload insns between PREV and NEXT exclusive, and
4560 annotate all that may trap. */
4563 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4565 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4568 if (!insn_could_throw_p (insn
))
4569 remove_note (insn
, note
);
4570 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4573 /* Reload pseudo-registers into hard regs around each insn as needed.
4574 Additional register load insns are output before the insn that needs it
4575 and perhaps store insns after insns that modify the reloaded pseudo reg.
4577 reg_last_reload_reg and reg_reloaded_contents keep track of
4578 which registers are already available in reload registers.
4579 We update these for the reloads that we perform,
4580 as the insns are scanned. */
4583 reload_as_needed (int live_known
)
4585 struct insn_chain
*chain
;
4586 #if defined (AUTO_INC_DEC)
4591 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4592 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4593 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4594 INIT_REG_SET (®_has_output_reload
);
4595 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4596 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4598 set_initial_elim_offsets ();
4600 /* Generate a marker insn that we will move around. */
4601 marker
= emit_note (NOTE_INSN_DELETED
);
4602 unlink_insn_chain (marker
, marker
);
4604 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4607 rtx insn
= chain
->insn
;
4608 rtx old_next
= NEXT_INSN (insn
);
4610 rtx old_prev
= PREV_INSN (insn
);
4613 if (will_delete_init_insn_p (insn
))
4616 /* If we pass a label, copy the offsets from the label information
4617 into the current offsets of each elimination. */
4619 set_offsets_for_label (insn
);
4621 else if (INSN_P (insn
))
4623 regset_head regs_to_forget
;
4624 INIT_REG_SET (®s_to_forget
);
4625 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4627 /* If this is a USE and CLOBBER of a MEM, ensure that any
4628 references to eliminable registers have been removed. */
4630 if ((GET_CODE (PATTERN (insn
)) == USE
4631 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4632 && MEM_P (XEXP (PATTERN (insn
), 0)))
4633 XEXP (XEXP (PATTERN (insn
), 0), 0)
4634 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4635 GET_MODE (XEXP (PATTERN (insn
), 0)),
4638 /* If we need to do register elimination processing, do so.
4639 This might delete the insn, in which case we are done. */
4640 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4642 eliminate_regs_in_insn (insn
, 1);
4645 update_eliminable_offsets ();
4646 CLEAR_REG_SET (®s_to_forget
);
4651 /* If need_elim is nonzero but need_reload is zero, one might think
4652 that we could simply set n_reloads to 0. However, find_reloads
4653 could have done some manipulation of the insn (such as swapping
4654 commutative operands), and these manipulations are lost during
4655 the first pass for every insn that needs register elimination.
4656 So the actions of find_reloads must be redone here. */
4658 if (! chain
->need_elim
&& ! chain
->need_reload
4659 && ! chain
->need_operand_change
)
4661 /* First find the pseudo regs that must be reloaded for this insn.
4662 This info is returned in the tables reload_... (see reload.h).
4663 Also modify the body of INSN by substituting RELOAD
4664 rtx's for those pseudo regs. */
4667 CLEAR_REG_SET (®_has_output_reload
);
4668 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4670 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4676 rtx next
= NEXT_INSN (insn
);
4679 /* ??? PREV can get deleted by reload inheritance.
4680 Work around this by emitting a marker note. */
4681 prev
= PREV_INSN (insn
);
4682 reorder_insns_nobb (marker
, marker
, prev
);
4684 /* Now compute which reload regs to reload them into. Perhaps
4685 reusing reload regs from previous insns, or else output
4686 load insns to reload them. Maybe output store insns too.
4687 Record the choices of reload reg in reload_reg_rtx. */
4688 choose_reload_regs (chain
);
4690 /* Generate the insns to reload operands into or out of
4691 their reload regs. */
4692 emit_reload_insns (chain
);
4694 /* Substitute the chosen reload regs from reload_reg_rtx
4695 into the insn's body (or perhaps into the bodies of other
4696 load and store insn that we just made for reloading
4697 and that we moved the structure into). */
4698 subst_reloads (insn
);
4700 prev
= PREV_INSN (marker
);
4701 unlink_insn_chain (marker
, marker
);
4703 /* Adjust the exception region notes for loads and stores. */
4704 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4705 fixup_eh_region_note (insn
, prev
, next
);
4707 /* Adjust the location of REG_ARGS_SIZE. */
4708 p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4711 remove_note (insn
, p
);
4712 fixup_args_size_notes (prev
, PREV_INSN (next
),
4713 INTVAL (XEXP (p
, 0)));
4716 /* If this was an ASM, make sure that all the reload insns
4717 we have generated are valid. If not, give an error
4719 if (asm_noperands (PATTERN (insn
)) >= 0)
4720 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4721 if (p
!= insn
&& INSN_P (p
)
4722 && GET_CODE (PATTERN (p
)) != USE
4723 && (recog_memoized (p
) < 0
4724 || (extract_insn (p
), ! constrain_operands (1))))
4726 error_for_asm (insn
,
4727 "%<asm%> operand requires "
4728 "impossible reload");
4733 if (num_eliminable
&& chain
->need_elim
)
4734 update_eliminable_offsets ();
4736 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4737 is no longer validly lying around to save a future reload.
4738 Note that this does not detect pseudos that were reloaded
4739 for this insn in order to be stored in
4740 (obeying register constraints). That is correct; such reload
4741 registers ARE still valid. */
4742 forget_marked_reloads (®s_to_forget
);
4743 CLEAR_REG_SET (®s_to_forget
);
4745 /* There may have been CLOBBER insns placed after INSN. So scan
4746 between INSN and NEXT and use them to forget old reloads. */
4747 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4748 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4749 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4752 /* Likewise for regs altered by auto-increment in this insn.
4753 REG_INC notes have been changed by reloading:
4754 find_reloads_address_1 records substitutions for them,
4755 which have been performed by subst_reloads above. */
4756 for (i
= n_reloads
- 1; i
>= 0; i
--)
4758 rtx in_reg
= rld
[i
].in_reg
;
4761 enum rtx_code code
= GET_CODE (in_reg
);
4762 /* PRE_INC / PRE_DEC will have the reload register ending up
4763 with the same value as the stack slot, but that doesn't
4764 hold true for POST_INC / POST_DEC. Either we have to
4765 convert the memory access to a true POST_INC / POST_DEC,
4766 or we can't use the reload register for inheritance. */
4767 if ((code
== POST_INC
|| code
== POST_DEC
)
4768 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4769 REGNO (rld
[i
].reg_rtx
))
4770 /* Make sure it is the inc/dec pseudo, and not
4771 some other (e.g. output operand) pseudo. */
4772 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4773 == REGNO (XEXP (in_reg
, 0))))
4776 rtx reload_reg
= rld
[i
].reg_rtx
;
4777 enum machine_mode mode
= GET_MODE (reload_reg
);
4781 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4783 /* We really want to ignore REG_INC notes here, so
4784 use PATTERN (p) as argument to reg_set_p . */
4785 if (reg_set_p (reload_reg
, PATTERN (p
)))
4787 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4793 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4795 validate_replace_rtx_group (reload_reg
,
4797 n
= verify_changes (0);
4799 /* We must also verify that the constraints
4800 are met after the replacement. Make sure
4801 extract_insn is only called for an insn
4802 where the replacements were found to be
4807 n
= constrain_operands (1);
4810 /* If the constraints were not met, then
4811 undo the replacement, else confirm it. */
4815 confirm_change_group ();
4821 add_reg_note (p
, REG_INC
, reload_reg
);
4822 /* Mark this as having an output reload so that the
4823 REG_INC processing code below won't invalidate
4824 the reload for inheritance. */
4825 SET_HARD_REG_BIT (reg_is_output_reload
,
4826 REGNO (reload_reg
));
4827 SET_REGNO_REG_SET (®_has_output_reload
,
4828 REGNO (XEXP (in_reg
, 0)));
4831 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4834 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4835 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4836 REGNO (rld
[i
].reg_rtx
))
4837 /* Make sure it is the inc/dec pseudo, and not
4838 some other (e.g. output operand) pseudo. */
4839 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4840 == REGNO (XEXP (in_reg
, 0))))
4842 SET_HARD_REG_BIT (reg_is_output_reload
,
4843 REGNO (rld
[i
].reg_rtx
));
4844 SET_REGNO_REG_SET (®_has_output_reload
,
4845 REGNO (XEXP (in_reg
, 0)));
4847 else if (code
== PRE_INC
|| code
== PRE_DEC
4848 || code
== POST_INC
|| code
== POST_DEC
)
4850 int in_regno
= REGNO (XEXP (in_reg
, 0));
4852 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4855 bool forget_p
= true;
4857 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4858 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4861 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4864 if (x
== reg_reloaded_insn
[in_hard_regno
])
4870 /* If for some reasons, we didn't set up
4871 reg_last_reload_reg in this insn,
4872 invalidate inheritance from previous
4873 insns for the incremented/decremented
4874 register. Such registers will be not in
4875 reg_has_output_reload. Invalidate it
4876 also if the corresponding element in
4877 reg_reloaded_insn is also
4880 forget_old_reloads_1 (XEXP (in_reg
, 0),
4886 /* If a pseudo that got a hard register is auto-incremented,
4887 we must purge records of copying it into pseudos without
4889 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4890 if (REG_NOTE_KIND (x
) == REG_INC
)
4892 /* See if this pseudo reg was reloaded in this insn.
4893 If so, its last-reload info is still valid
4894 because it is based on this insn's reload. */
4895 for (i
= 0; i
< n_reloads
; i
++)
4896 if (rld
[i
].out
== XEXP (x
, 0))
4900 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4904 /* A reload reg's contents are unknown after a label. */
4906 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4908 /* Don't assume a reload reg is still good after a call insn
4909 if it is a call-used reg, or if it contains a value that will
4910 be partially clobbered by the call. */
4911 else if (CALL_P (insn
))
4913 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4914 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4916 /* If this is a call to a setjmp-type function, we must not
4917 reuse any reload reg contents across the call; that will
4918 just be clobbered by other uses of the register in later
4919 code, before the longjmp. */
4920 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4921 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4926 free (reg_last_reload_reg
);
4927 CLEAR_REG_SET (®_has_output_reload
);
4930 /* Discard all record of any value reloaded from X,
4931 or reloaded in X from someplace else;
4932 unless X is an output reload reg of the current insn.
4934 X may be a hard reg (the reload reg)
4935 or it may be a pseudo reg that was reloaded from.
4937 When DATA is non-NULL just mark the registers in regset
4938 to be forgotten later. */
4941 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4946 regset regs
= (regset
) data
;
4948 /* note_stores does give us subregs of hard regs,
4949 subreg_regno_offset requires a hard reg. */
4950 while (GET_CODE (x
) == SUBREG
)
4952 /* We ignore the subreg offset when calculating the regno,
4953 because we are using the entire underlying hard register
4963 if (regno
>= FIRST_PSEUDO_REGISTER
)
4969 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4970 /* Storing into a spilled-reg invalidates its contents.
4971 This can happen if a block-local pseudo is allocated to that reg
4972 and it wasn't spilled because this block's total need is 0.
4973 Then some insn might have an optional reload and use this reg. */
4975 for (i
= 0; i
< nr
; i
++)
4976 /* But don't do this if the reg actually serves as an output
4977 reload reg in the current instruction. */
4979 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4981 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4982 spill_reg_store
[regno
+ i
] = 0;
4988 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4991 /* Since value of X has changed,
4992 forget any value previously copied from it. */
4995 /* But don't forget a copy if this is the output reload
4996 that establishes the copy's validity. */
4998 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4999 reg_last_reload_reg
[regno
+ nr
] = 0;
5003 /* Forget the reloads marked in regset by previous function. */
5005 forget_marked_reloads (regset regs
)
5008 reg_set_iterator rsi
;
5009 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
5011 if (reg
< FIRST_PSEUDO_REGISTER
5012 /* But don't do this if the reg actually serves as an output
5013 reload reg in the current instruction. */
5015 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
5017 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
5018 spill_reg_store
[reg
] = 0;
5021 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
5022 reg_last_reload_reg
[reg
] = 0;
5026 /* The following HARD_REG_SETs indicate when each hard register is
5027 used for a reload of various parts of the current insn. */
5029 /* If reg is unavailable for all reloads. */
5030 static HARD_REG_SET reload_reg_unavailable
;
5031 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5032 static HARD_REG_SET reload_reg_used
;
5033 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5034 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5035 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5036 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5037 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5038 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5039 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5040 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5041 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5042 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5043 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5044 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5045 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5046 static HARD_REG_SET reload_reg_used_in_op_addr
;
5047 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5048 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5049 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5050 static HARD_REG_SET reload_reg_used_in_insn
;
5051 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5052 static HARD_REG_SET reload_reg_used_in_other_addr
;
5054 /* If reg is in use as a reload reg for any sort of reload. */
5055 static HARD_REG_SET reload_reg_used_at_all
;
5057 /* If reg is use as an inherited reload. We just mark the first register
5059 static HARD_REG_SET reload_reg_used_for_inherit
;
5061 /* Records which hard regs are used in any way, either as explicit use or
5062 by being allocated to a pseudo during any point of the current insn. */
5063 static HARD_REG_SET reg_used_in_insn
;
5065 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5066 TYPE. MODE is used to indicate how many consecutive regs are
5070 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5071 enum machine_mode mode
)
5076 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5079 case RELOAD_FOR_INPUT_ADDRESS
:
5080 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5083 case RELOAD_FOR_INPADDR_ADDRESS
:
5084 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5087 case RELOAD_FOR_OUTPUT_ADDRESS
:
5088 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5091 case RELOAD_FOR_OUTADDR_ADDRESS
:
5092 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5095 case RELOAD_FOR_OPERAND_ADDRESS
:
5096 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5099 case RELOAD_FOR_OPADDR_ADDR
:
5100 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5103 case RELOAD_FOR_OTHER_ADDRESS
:
5104 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5107 case RELOAD_FOR_INPUT
:
5108 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5111 case RELOAD_FOR_OUTPUT
:
5112 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5115 case RELOAD_FOR_INSN
:
5116 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5120 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5123 /* Similarly, but show REGNO is no longer in use for a reload. */
5126 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5127 enum reload_type type
, enum machine_mode mode
)
5129 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5130 unsigned int start_regno
, end_regno
, r
;
5132 /* A complication is that for some reload types, inheritance might
5133 allow multiple reloads of the same types to share a reload register.
5134 We set check_opnum if we have to check only reloads with the same
5135 operand number, and check_any if we have to check all reloads. */
5136 int check_opnum
= 0;
5138 HARD_REG_SET
*used_in_set
;
5143 used_in_set
= &reload_reg_used
;
5146 case RELOAD_FOR_INPUT_ADDRESS
:
5147 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5150 case RELOAD_FOR_INPADDR_ADDRESS
:
5152 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5155 case RELOAD_FOR_OUTPUT_ADDRESS
:
5156 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5159 case RELOAD_FOR_OUTADDR_ADDRESS
:
5161 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5164 case RELOAD_FOR_OPERAND_ADDRESS
:
5165 used_in_set
= &reload_reg_used_in_op_addr
;
5168 case RELOAD_FOR_OPADDR_ADDR
:
5170 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5173 case RELOAD_FOR_OTHER_ADDRESS
:
5174 used_in_set
= &reload_reg_used_in_other_addr
;
5178 case RELOAD_FOR_INPUT
:
5179 used_in_set
= &reload_reg_used_in_input
[opnum
];
5182 case RELOAD_FOR_OUTPUT
:
5183 used_in_set
= &reload_reg_used_in_output
[opnum
];
5186 case RELOAD_FOR_INSN
:
5187 used_in_set
= &reload_reg_used_in_insn
;
5192 /* We resolve conflicts with remaining reloads of the same type by
5193 excluding the intervals of reload registers by them from the
5194 interval of freed reload registers. Since we only keep track of
5195 one set of interval bounds, we might have to exclude somewhat
5196 more than what would be necessary if we used a HARD_REG_SET here.
5197 But this should only happen very infrequently, so there should
5198 be no reason to worry about it. */
5200 start_regno
= regno
;
5201 end_regno
= regno
+ nregs
;
5202 if (check_opnum
|| check_any
)
5204 for (i
= n_reloads
- 1; i
>= 0; i
--)
5206 if (rld
[i
].when_needed
== type
5207 && (check_any
|| rld
[i
].opnum
== opnum
)
5210 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5211 unsigned int conflict_end
5212 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5214 /* If there is an overlap with the first to-be-freed register,
5215 adjust the interval start. */
5216 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5217 start_regno
= conflict_end
;
5218 /* Otherwise, if there is a conflict with one of the other
5219 to-be-freed registers, adjust the interval end. */
5220 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5221 end_regno
= conflict_start
;
5226 for (r
= start_regno
; r
< end_regno
; r
++)
5227 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5230 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5231 specified by OPNUM and TYPE. */
5234 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5238 /* In use for a RELOAD_OTHER means it's not available for anything. */
5239 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5240 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5246 /* In use for anything means we can't use it for RELOAD_OTHER. */
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5248 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5249 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5250 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5253 for (i
= 0; i
< reload_n_operands
; i
++)
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5256 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5257 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5258 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5259 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5264 case RELOAD_FOR_INPUT
:
5265 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5266 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5269 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5272 /* If it is used for some other input, can't use it. */
5273 for (i
= 0; i
< reload_n_operands
; i
++)
5274 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5277 /* If it is used in a later operand's address, can't use it. */
5278 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5279 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5280 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5285 case RELOAD_FOR_INPUT_ADDRESS
:
5286 /* Can't use a register if it is used for an input address for this
5287 operand or used as an input in an earlier one. */
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5289 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5292 for (i
= 0; i
< opnum
; i
++)
5293 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5298 case RELOAD_FOR_INPADDR_ADDRESS
:
5299 /* Can't use a register if it is used for an input address
5300 for this operand or used as an input in an earlier
5302 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5305 for (i
= 0; i
< opnum
; i
++)
5306 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5311 case RELOAD_FOR_OUTPUT_ADDRESS
:
5312 /* Can't use a register if it is used for an output address for this
5313 operand or used as an output in this or a later operand. Note
5314 that multiple output operands are emitted in reverse order, so
5315 the conflicting ones are those with lower indices. */
5316 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5319 for (i
= 0; i
<= opnum
; i
++)
5320 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5325 case RELOAD_FOR_OUTADDR_ADDRESS
:
5326 /* Can't use a register if it is used for an output address
5327 for this operand or used as an output in this or a
5328 later operand. Note that multiple output operands are
5329 emitted in reverse order, so the conflicting ones are
5330 those with lower indices. */
5331 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5334 for (i
= 0; i
<= opnum
; i
++)
5335 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5340 case RELOAD_FOR_OPERAND_ADDRESS
:
5341 for (i
= 0; i
< reload_n_operands
; i
++)
5342 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5345 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5346 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5348 case RELOAD_FOR_OPADDR_ADDR
:
5349 for (i
= 0; i
< reload_n_operands
; i
++)
5350 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5353 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5355 case RELOAD_FOR_OUTPUT
:
5356 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5357 outputs, or an operand address for this or an earlier output.
5358 Note that multiple output operands are emitted in reverse order,
5359 so the conflicting ones are those with higher indices. */
5360 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5363 for (i
= 0; i
< reload_n_operands
; i
++)
5364 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5367 for (i
= opnum
; i
< reload_n_operands
; i
++)
5368 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5369 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5374 case RELOAD_FOR_INSN
:
5375 for (i
= 0; i
< reload_n_operands
; i
++)
5376 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5377 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5380 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5381 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5383 case RELOAD_FOR_OTHER_ADDRESS
:
5384 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5391 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5392 the number RELOADNUM, is still available in REGNO at the end of the insn.
5394 We can assume that the reload reg was already tested for availability
5395 at the time it is needed, and we should not check this again,
5396 in case the reg has already been marked in use. */
5399 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5401 int opnum
= rld
[reloadnum
].opnum
;
5402 enum reload_type type
= rld
[reloadnum
].when_needed
;
5405 /* See if there is a reload with the same type for this operand, using
5406 the same register. This case is not handled by the code below. */
5407 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5412 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5414 reg
= rld
[i
].reg_rtx
;
5415 if (reg
== NULL_RTX
)
5417 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5418 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5425 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5426 its value must reach the end. */
5429 /* If this use is for part of the insn,
5430 its value reaches if no subsequent part uses the same register.
5431 Just like the above function, don't try to do this with lots
5434 case RELOAD_FOR_OTHER_ADDRESS
:
5435 /* Here we check for everything else, since these don't conflict
5436 with anything else and everything comes later. */
5438 for (i
= 0; i
< reload_n_operands
; i
++)
5439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5440 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5441 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5442 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5443 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5444 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5447 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5448 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5449 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5450 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5452 case RELOAD_FOR_INPUT_ADDRESS
:
5453 case RELOAD_FOR_INPADDR_ADDRESS
:
5454 /* Similar, except that we check only for this and subsequent inputs
5455 and the address of only subsequent inputs and we do not need
5456 to check for RELOAD_OTHER objects since they are known not to
5459 for (i
= opnum
; i
< reload_n_operands
; i
++)
5460 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5463 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5464 could be killed if the register is also used by reload with type
5465 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5466 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5467 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5470 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5471 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5472 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5475 for (i
= 0; i
< reload_n_operands
; i
++)
5476 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5477 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5478 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5481 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5484 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5485 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5486 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5488 case RELOAD_FOR_INPUT
:
5489 /* Similar to input address, except we start at the next operand for
5490 both input and input address and we do not check for
5491 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5494 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5496 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5497 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5500 /* ... fall through ... */
5502 case RELOAD_FOR_OPERAND_ADDRESS
:
5503 /* Check outputs and their addresses. */
5505 for (i
= 0; i
< reload_n_operands
; i
++)
5506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5507 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5508 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5511 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5513 case RELOAD_FOR_OPADDR_ADDR
:
5514 for (i
= 0; i
< reload_n_operands
; i
++)
5515 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5516 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5517 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5520 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5521 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5522 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5524 case RELOAD_FOR_INSN
:
5525 /* These conflict with other outputs with RELOAD_OTHER. So
5526 we need only check for output addresses. */
5528 opnum
= reload_n_operands
;
5530 /* ... fall through ... */
5532 case RELOAD_FOR_OUTPUT
:
5533 case RELOAD_FOR_OUTPUT_ADDRESS
:
5534 case RELOAD_FOR_OUTADDR_ADDRESS
:
5535 /* We already know these can't conflict with a later output. So the
5536 only thing to check are later output addresses.
5537 Note that multiple output operands are emitted in reverse order,
5538 so the conflicting ones are those with lower indices. */
5539 for (i
= 0; i
< opnum
; i
++)
5540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5541 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5544 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5545 could be killed if the register is also used by reload with type
5546 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5547 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5548 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5558 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5559 every register in REG. */
5562 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5566 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5567 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5573 /* Returns whether R1 and R2 are uniquely chained: the value of one
5574 is used by the other, and that value is not used by any other
5575 reload for this insn. This is used to partially undo the decision
5576 made in find_reloads when in the case of multiple
5577 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5578 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5579 reloads. This code tries to avoid the conflict created by that
5580 change. It might be cleaner to explicitly keep track of which
5581 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5582 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5583 this after the fact. */
5585 reloads_unique_chain_p (int r1
, int r2
)
5589 /* We only check input reloads. */
5590 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5593 /* Avoid anything with output reloads. */
5594 if (rld
[r1
].out
|| rld
[r2
].out
)
5597 /* "chained" means one reload is a component of the other reload,
5598 not the same as the other reload. */
5599 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5600 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5601 || rld
[r1
].optional
|| rld
[r2
].optional
5602 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5603 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5606 /* The following loop assumes that r1 is the reload that feeds r2. */
5614 for (i
= 0; i
< n_reloads
; i
++)
5615 /* Look for input reloads that aren't our two */
5616 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5618 /* If our reload is mentioned at all, it isn't a simple chain. */
5619 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5625 /* The recursive function change all occurrences of WHAT in *WHERE
5628 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5637 if (*where
== what
|| rtx_equal_p (*where
, what
))
5639 /* Record the location of the changed rtx. */
5640 substitute_stack
.safe_push (where
);
5645 code
= GET_CODE (*where
);
5646 fmt
= GET_RTX_FORMAT (code
);
5647 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5653 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5654 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5656 else if (fmt
[i
] == 'e')
5657 substitute (&XEXP (*where
, i
), what
, repl
);
5661 /* The function returns TRUE if chain of reload R1 and R2 (in any
5662 order) can be evaluated without usage of intermediate register for
5663 the reload containing another reload. It is important to see
5664 gen_reload to understand what the function is trying to do. As an
5665 example, let us have reload chain
5668 r1: <something> + const
5670 and reload R2 got reload reg HR. The function returns true if
5671 there is a correct insn HR = HR + <something>. Otherwise,
5672 gen_reload will use intermediate register (and this is the reload
5673 reg for R1) to reload <something>.
5675 We need this function to find a conflict for chain reloads. In our
5676 example, if HR = HR + <something> is incorrect insn, then we cannot
5677 use HR as a reload register for R2. If we do use it then we get a
5686 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5688 /* Assume other cases in gen_reload are not possible for
5689 chain reloads or do need an intermediate hard registers. */
5693 rtx last
= get_last_insn ();
5695 /* Make r2 a component of r1. */
5696 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5702 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5703 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5704 gcc_assert (regno
>= 0);
5705 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5707 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5709 /* If IN is a paradoxical SUBREG, remove it and try to put the
5710 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5711 strip_paradoxical_subreg (&in
, &out
);
5713 if (GET_CODE (in
) == PLUS
5714 && (REG_P (XEXP (in
, 0))
5715 || GET_CODE (XEXP (in
, 0)) == SUBREG
5716 || MEM_P (XEXP (in
, 0)))
5717 && (REG_P (XEXP (in
, 1))
5718 || GET_CODE (XEXP (in
, 1)) == SUBREG
5719 || CONSTANT_P (XEXP (in
, 1))
5720 || MEM_P (XEXP (in
, 1))))
5722 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5723 code
= recog_memoized (insn
);
5728 extract_insn (insn
);
5729 /* We want constrain operands to treat this insn strictly in
5730 its validity determination, i.e., the way it would after
5731 reload has completed. */
5732 result
= constrain_operands (1);
5735 delete_insns_since (last
);
5738 /* Restore the original value at each changed address within R1. */
5739 while (!substitute_stack
.is_empty ())
5741 rtx
*where
= substitute_stack
.pop ();
5742 *where
= rld
[r2
].in
;
5748 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5751 This function uses the same algorithm as reload_reg_free_p above. */
5754 reloads_conflict (int r1
, int r2
)
5756 enum reload_type r1_type
= rld
[r1
].when_needed
;
5757 enum reload_type r2_type
= rld
[r2
].when_needed
;
5758 int r1_opnum
= rld
[r1
].opnum
;
5759 int r2_opnum
= rld
[r2
].opnum
;
5761 /* RELOAD_OTHER conflicts with everything. */
5762 if (r2_type
== RELOAD_OTHER
)
5765 /* Otherwise, check conflicts differently for each type. */
5769 case RELOAD_FOR_INPUT
:
5770 return (r2_type
== RELOAD_FOR_INSN
5771 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5772 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5773 || r2_type
== RELOAD_FOR_INPUT
5774 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5775 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5776 && r2_opnum
> r1_opnum
));
5778 case RELOAD_FOR_INPUT_ADDRESS
:
5779 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5780 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5782 case RELOAD_FOR_INPADDR_ADDRESS
:
5783 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5784 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5786 case RELOAD_FOR_OUTPUT_ADDRESS
:
5787 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5788 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5790 case RELOAD_FOR_OUTADDR_ADDRESS
:
5791 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5792 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5794 case RELOAD_FOR_OPERAND_ADDRESS
:
5795 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5796 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5797 && (!reloads_unique_chain_p (r1
, r2
)
5798 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5800 case RELOAD_FOR_OPADDR_ADDR
:
5801 return (r2_type
== RELOAD_FOR_INPUT
5802 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5804 case RELOAD_FOR_OUTPUT
:
5805 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5806 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5807 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5808 && r2_opnum
>= r1_opnum
));
5810 case RELOAD_FOR_INSN
:
5811 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5812 || r2_type
== RELOAD_FOR_INSN
5813 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5815 case RELOAD_FOR_OTHER_ADDRESS
:
5816 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5826 /* Indexed by reload number, 1 if incoming value
5827 inherited from previous insns. */
5828 static char reload_inherited
[MAX_RELOADS
];
5830 /* For an inherited reload, this is the insn the reload was inherited from,
5831 if we know it. Otherwise, this is 0. */
5832 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5834 /* If nonzero, this is a place to get the value of the reload,
5835 rather than using reload_in. */
5836 static rtx reload_override_in
[MAX_RELOADS
];
5838 /* For each reload, the hard register number of the register used,
5839 or -1 if we did not need a register for this reload. */
5840 static int reload_spill_index
[MAX_RELOADS
];
5842 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5843 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5845 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5846 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5848 /* Subroutine of free_for_value_p, used to check a single register.
5849 START_REGNO is the starting regno of the full reload register
5850 (possibly comprising multiple hard registers) that we are considering. */
5853 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5854 enum reload_type type
, rtx value
, rtx out
,
5855 int reloadnum
, int ignore_address_reloads
)
5858 /* Set if we see an input reload that must not share its reload register
5859 with any new earlyclobber, but might otherwise share the reload
5860 register with an output or input-output reload. */
5861 int check_earlyclobber
= 0;
5865 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5868 if (out
== const0_rtx
)
5874 /* We use some pseudo 'time' value to check if the lifetimes of the
5875 new register use would overlap with the one of a previous reload
5876 that is not read-only or uses a different value.
5877 The 'time' used doesn't have to be linear in any shape or form, just
5879 Some reload types use different 'buckets' for each operand.
5880 So there are MAX_RECOG_OPERANDS different time values for each
5882 We compute TIME1 as the time when the register for the prospective
5883 new reload ceases to be live, and TIME2 for each existing
5884 reload as the time when that the reload register of that reload
5886 Where there is little to be gained by exact lifetime calculations,
5887 we just make conservative assumptions, i.e. a longer lifetime;
5888 this is done in the 'default:' cases. */
5891 case RELOAD_FOR_OTHER_ADDRESS
:
5892 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5893 time1
= copy
? 0 : 1;
5896 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5898 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5899 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5900 respectively, to the time values for these, we get distinct time
5901 values. To get distinct time values for each operand, we have to
5902 multiply opnum by at least three. We round that up to four because
5903 multiply by four is often cheaper. */
5904 case RELOAD_FOR_INPADDR_ADDRESS
:
5905 time1
= opnum
* 4 + 2;
5907 case RELOAD_FOR_INPUT_ADDRESS
:
5908 time1
= opnum
* 4 + 3;
5910 case RELOAD_FOR_INPUT
:
5911 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5912 executes (inclusive). */
5913 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5915 case RELOAD_FOR_OPADDR_ADDR
:
5917 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5918 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5920 case RELOAD_FOR_OPERAND_ADDRESS
:
5921 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5923 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5925 case RELOAD_FOR_OUTADDR_ADDRESS
:
5926 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5928 case RELOAD_FOR_OUTPUT_ADDRESS
:
5929 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5932 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5935 for (i
= 0; i
< n_reloads
; i
++)
5937 rtx reg
= rld
[i
].reg_rtx
;
5938 if (reg
&& REG_P (reg
)
5939 && ((unsigned) regno
- true_regnum (reg
)
5940 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5943 rtx other_input
= rld
[i
].in
;
5945 /* If the other reload loads the same input value, that
5946 will not cause a conflict only if it's loading it into
5947 the same register. */
5948 if (true_regnum (reg
) != start_regno
)
5949 other_input
= NULL_RTX
;
5950 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5951 || rld
[i
].out
|| out
)
5954 switch (rld
[i
].when_needed
)
5956 case RELOAD_FOR_OTHER_ADDRESS
:
5959 case RELOAD_FOR_INPADDR_ADDRESS
:
5960 /* find_reloads makes sure that a
5961 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5962 by at most one - the first -
5963 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5964 address reload is inherited, the address address reload
5965 goes away, so we can ignore this conflict. */
5966 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5967 && ignore_address_reloads
5968 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5969 Then the address address is still needed to store
5970 back the new address. */
5971 && ! rld
[reloadnum
].out
)
5973 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5974 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5976 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5977 && ignore_address_reloads
5978 /* Unless we are reloading an auto_inc expression. */
5979 && ! rld
[reloadnum
].out
)
5981 time2
= rld
[i
].opnum
* 4 + 2;
5983 case RELOAD_FOR_INPUT_ADDRESS
:
5984 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5985 && ignore_address_reloads
5986 && ! rld
[reloadnum
].out
)
5988 time2
= rld
[i
].opnum
* 4 + 3;
5990 case RELOAD_FOR_INPUT
:
5991 time2
= rld
[i
].opnum
* 4 + 4;
5992 check_earlyclobber
= 1;
5994 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5995 == MAX_RECOG_OPERAND * 4 */
5996 case RELOAD_FOR_OPADDR_ADDR
:
5997 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5998 && ignore_address_reloads
5999 && ! rld
[reloadnum
].out
)
6001 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
6003 case RELOAD_FOR_OPERAND_ADDRESS
:
6004 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
6005 check_earlyclobber
= 1;
6007 case RELOAD_FOR_INSN
:
6008 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6010 case RELOAD_FOR_OUTPUT
:
6011 /* All RELOAD_FOR_OUTPUT reloads become live just after the
6012 instruction is executed. */
6013 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6015 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6016 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6018 case RELOAD_FOR_OUTADDR_ADDRESS
:
6019 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
6020 && ignore_address_reloads
6021 && ! rld
[reloadnum
].out
)
6023 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
6025 case RELOAD_FOR_OUTPUT_ADDRESS
:
6026 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
6029 /* If there is no conflict in the input part, handle this
6030 like an output reload. */
6031 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
6033 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6034 /* Earlyclobbered outputs must conflict with inputs. */
6035 if (earlyclobber_operand_p (rld
[i
].out
))
6036 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6041 /* RELOAD_OTHER might be live beyond instruction execution,
6042 but this is not obvious when we set time2 = 1. So check
6043 here if there might be a problem with the new reload
6044 clobbering the register used by the RELOAD_OTHER. */
6052 && (! rld
[i
].in
|| rld
[i
].out
6053 || ! rtx_equal_p (other_input
, value
)))
6054 || (out
&& rld
[reloadnum
].out_reg
6055 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6061 /* Earlyclobbered outputs must conflict with inputs. */
6062 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6068 /* Return 1 if the value in reload reg REGNO, as used by a reload
6069 needed for the part of the insn specified by OPNUM and TYPE,
6070 may be used to load VALUE into it.
6072 MODE is the mode in which the register is used, this is needed to
6073 determine how many hard regs to test.
6075 Other read-only reloads with the same value do not conflict
6076 unless OUT is nonzero and these other reloads have to live while
6077 output reloads live.
6078 If OUT is CONST0_RTX, this is a special case: it means that the
6079 test should not be for using register REGNO as reload register, but
6080 for copying from register REGNO into the reload register.
6082 RELOADNUM is the number of the reload we want to load this value for;
6083 a reload does not conflict with itself.
6085 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6086 reloads that load an address for the very reload we are considering.
6088 The caller has to make sure that there is no conflict with the return
6092 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6093 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6094 int ignore_address_reloads
)
6096 int nregs
= hard_regno_nregs
[regno
][mode
];
6098 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6099 value
, out
, reloadnum
,
6100 ignore_address_reloads
))
6105 /* Return nonzero if the rtx X is invariant over the current function. */
6106 /* ??? Actually, the places where we use this expect exactly what is
6107 tested here, and not everything that is function invariant. In
6108 particular, the frame pointer and arg pointer are special cased;
6109 pic_offset_table_rtx is not, and we must not spill these things to
6113 function_invariant_p (const_rtx x
)
6117 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6119 if (GET_CODE (x
) == PLUS
6120 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6121 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6126 /* Determine whether the reload reg X overlaps any rtx'es used for
6127 overriding inheritance. Return nonzero if so. */
6130 conflicts_with_override (rtx x
)
6133 for (i
= 0; i
< n_reloads
; i
++)
6134 if (reload_override_in
[i
]
6135 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6140 /* Give an error message saying we failed to find a reload for INSN,
6141 and clear out reload R. */
6143 failed_reload (rtx insn
, int r
)
6145 if (asm_noperands (PATTERN (insn
)) < 0)
6146 /* It's the compiler's fault. */
6147 fatal_insn ("could not find a spill register", insn
);
6149 /* It's the user's fault; the operand's mode and constraint
6150 don't match. Disable this reload so we don't crash in final. */
6151 error_for_asm (insn
,
6152 "%<asm%> operand constraint incompatible with operand size");
6156 rld
[r
].optional
= 1;
6157 rld
[r
].secondary_p
= 1;
6160 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6161 for reload R. If it's valid, get an rtx for it. Return nonzero if
6164 set_reload_reg (int i
, int r
)
6166 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6168 int regno ATTRIBUTE_UNUSED
;
6169 rtx reg
= spill_reg_rtx
[i
];
6171 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6172 spill_reg_rtx
[i
] = reg
6173 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6175 regno
= true_regnum (reg
);
6177 /* Detect when the reload reg can't hold the reload mode.
6178 This used to be one `if', but Sequent compiler can't handle that. */
6179 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6181 enum machine_mode test_mode
= VOIDmode
;
6183 test_mode
= GET_MODE (rld
[r
].in
);
6184 /* If rld[r].in has VOIDmode, it means we will load it
6185 in whatever mode the reload reg has: to wit, rld[r].mode.
6186 We have already tested that for validity. */
6187 /* Aside from that, we need to test that the expressions
6188 to reload from or into have modes which are valid for this
6189 reload register. Otherwise the reload insns would be invalid. */
6190 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6191 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6192 if (! (rld
[r
].out
!= 0
6193 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6195 /* The reg is OK. */
6198 /* Mark as in use for this insn the reload regs we use
6200 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6201 rld
[r
].when_needed
, rld
[r
].mode
);
6203 rld
[r
].reg_rtx
= reg
;
6204 reload_spill_index
[r
] = spill_regs
[i
];
6211 /* Find a spill register to use as a reload register for reload R.
6212 LAST_RELOAD is nonzero if this is the last reload for the insn being
6215 Set rld[R].reg_rtx to the register allocated.
6217 We return 1 if successful, or 0 if we couldn't find a spill reg and
6218 we didn't change anything. */
6221 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6226 /* If we put this reload ahead, thinking it is a group,
6227 then insist on finding a group. Otherwise we can grab a
6228 reg that some other reload needs.
6229 (That can happen when we have a 68000 DATA_OR_FP_REG
6230 which is a group of data regs or one fp reg.)
6231 We need not be so restrictive if there are no more reloads
6234 ??? Really it would be nicer to have smarter handling
6235 for that kind of reg class, where a problem like this is normal.
6236 Perhaps those classes should be avoided for reloading
6237 by use of more alternatives. */
6239 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6241 /* If we want a single register and haven't yet found one,
6242 take any reg in the right class and not in use.
6243 If we want a consecutive group, here is where we look for it.
6245 We use three passes so we can first look for reload regs to
6246 reuse, which are already in use for other reloads in this insn,
6247 and only then use additional registers which are not "bad", then
6248 finally any register.
6250 I think that maximizing reuse is needed to make sure we don't
6251 run out of reload regs. Suppose we have three reloads, and
6252 reloads A and B can share regs. These need two regs.
6253 Suppose A and B are given different regs.
6254 That leaves none for C. */
6255 for (pass
= 0; pass
< 3; pass
++)
6257 /* I is the index in spill_regs.
6258 We advance it round-robin between insns to use all spill regs
6259 equally, so that inherited reloads have a chance
6260 of leapfrogging each other. */
6264 for (count
= 0; count
< n_spills
; count
++)
6266 int rclass
= (int) rld
[r
].rclass
;
6272 regnum
= spill_regs
[i
];
6274 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6277 /* We check reload_reg_used to make sure we
6278 don't clobber the return register. */
6279 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6280 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6281 rld
[r
].when_needed
, rld
[r
].in
,
6283 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6284 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6285 /* Look first for regs to share, then for unshared. But
6286 don't share regs used for inherited reloads; they are
6287 the ones we want to preserve. */
6289 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6291 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6294 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6296 /* During the second pass we want to avoid reload registers
6297 which are "bad" for this reload. */
6299 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6302 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6303 (on 68000) got us two FP regs. If NR is 1,
6304 we would reject both of them. */
6307 /* If we need only one reg, we have already won. */
6310 /* But reject a single reg if we demand a group. */
6315 /* Otherwise check that as many consecutive regs as we need
6316 are available here. */
6319 int regno
= regnum
+ nr
- 1;
6320 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6321 && spill_reg_order
[regno
] >= 0
6322 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6323 rld
[r
].when_needed
)))
6332 /* If we found something on the current pass, omit later passes. */
6333 if (count
< n_spills
)
6337 /* We should have found a spill register by now. */
6338 if (count
>= n_spills
)
6341 /* I is the index in SPILL_REG_RTX of the reload register we are to
6342 allocate. Get an rtx for it and find its register number. */
6344 return set_reload_reg (i
, r
);
6347 /* Initialize all the tables needed to allocate reload registers.
6348 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6349 is the array we use to restore the reg_rtx field for every reload. */
6352 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6356 for (i
= 0; i
< n_reloads
; i
++)
6357 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6359 memset (reload_inherited
, 0, MAX_RELOADS
);
6360 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6361 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6363 CLEAR_HARD_REG_SET (reload_reg_used
);
6364 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6365 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6366 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6367 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6368 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6370 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6373 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6374 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6375 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6376 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6377 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6378 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6381 for (i
= 0; i
< reload_n_operands
; i
++)
6383 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6384 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6385 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6386 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6387 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6388 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6391 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6393 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6395 for (i
= 0; i
< n_reloads
; i
++)
6396 /* If we have already decided to use a certain register,
6397 don't use it in another way. */
6399 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6400 rld
[i
].when_needed
, rld
[i
].mode
);
6403 #ifdef SECONDARY_MEMORY_NEEDED
6404 /* If X is not a subreg, return it unmodified. If it is a subreg,
6405 look up whether we made a replacement for the SUBREG_REG. Return
6406 either the replacement or the SUBREG_REG. */
6409 replaced_subreg (rtx x
)
6411 if (GET_CODE (x
) == SUBREG
)
6412 return find_replacement (&SUBREG_REG (x
));
6417 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6418 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6419 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6420 otherwise it is NULL. */
6423 compute_reload_subreg_offset (enum machine_mode outermode
,
6425 enum machine_mode innermode
)
6428 enum machine_mode middlemode
;
6431 return subreg_lowpart_offset (outermode
, innermode
);
6433 outer_offset
= SUBREG_BYTE (subreg
);
6434 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6436 /* If SUBREG is paradoxical then return the normal lowpart offset
6437 for OUTERMODE and INNERMODE. Our caller has already checked
6438 that OUTERMODE fits in INNERMODE. */
6439 if (outer_offset
== 0
6440 && GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (middlemode
))
6441 return subreg_lowpart_offset (outermode
, innermode
);
6443 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6444 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6445 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6448 /* Assign hard reg targets for the pseudo-registers we must reload
6449 into hard regs for this insn.
6450 Also output the instructions to copy them in and out of the hard regs.
6452 For machines with register classes, we are responsible for
6453 finding a reload reg in the proper class. */
6456 choose_reload_regs (struct insn_chain
*chain
)
6458 rtx insn
= chain
->insn
;
6460 unsigned int max_group_size
= 1;
6461 enum reg_class group_class
= NO_REGS
;
6462 int pass
, win
, inheritance
;
6464 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6466 /* In order to be certain of getting the registers we need,
6467 we must sort the reloads into order of increasing register class.
6468 Then our grabbing of reload registers will parallel the process
6469 that provided the reload registers.
6471 Also note whether any of the reloads wants a consecutive group of regs.
6472 If so, record the maximum size of the group desired and what
6473 register class contains all the groups needed by this insn. */
6475 for (j
= 0; j
< n_reloads
; j
++)
6477 reload_order
[j
] = j
;
6478 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6480 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6481 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6482 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6485 reload_spill_index
[j
] = -1;
6487 if (rld
[j
].nregs
> 1)
6489 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6491 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6494 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6498 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6500 /* If -O, try first with inheritance, then turning it off.
6501 If not -O, don't do inheritance.
6502 Using inheritance when not optimizing leads to paradoxes
6503 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6504 because one side of the comparison might be inherited. */
6506 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6508 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6510 /* Process the reloads in order of preference just found.
6511 Beyond this point, subregs can be found in reload_reg_rtx.
6513 This used to look for an existing reloaded home for all of the
6514 reloads, and only then perform any new reloads. But that could lose
6515 if the reloads were done out of reg-class order because a later
6516 reload with a looser constraint might have an old home in a register
6517 needed by an earlier reload with a tighter constraint.
6519 To solve this, we make two passes over the reloads, in the order
6520 described above. In the first pass we try to inherit a reload
6521 from a previous insn. If there is a later reload that needs a
6522 class that is a proper subset of the class being processed, we must
6523 also allocate a spill register during the first pass.
6525 Then make a second pass over the reloads to allocate any reloads
6526 that haven't been given registers yet. */
6528 for (j
= 0; j
< n_reloads
; j
++)
6530 int r
= reload_order
[j
];
6531 rtx search_equiv
= NULL_RTX
;
6533 /* Ignore reloads that got marked inoperative. */
6534 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6535 && ! rld
[r
].secondary_p
)
6538 /* If find_reloads chose to use reload_in or reload_out as a reload
6539 register, we don't need to chose one. Otherwise, try even if it
6540 found one since we might save an insn if we find the value lying
6542 Try also when reload_in is a pseudo without a hard reg. */
6543 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6544 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6545 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6546 && !MEM_P (rld
[r
].in
)
6547 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6550 #if 0 /* No longer needed for correct operation.
6551 It might give better code, or might not; worth an experiment? */
6552 /* If this is an optional reload, we can't inherit from earlier insns
6553 until we are sure that any non-optional reloads have been allocated.
6554 The following code takes advantage of the fact that optional reloads
6555 are at the end of reload_order. */
6556 if (rld
[r
].optional
!= 0)
6557 for (i
= 0; i
< j
; i
++)
6558 if ((rld
[reload_order
[i
]].out
!= 0
6559 || rld
[reload_order
[i
]].in
!= 0
6560 || rld
[reload_order
[i
]].secondary_p
)
6561 && ! rld
[reload_order
[i
]].optional
6562 && rld
[reload_order
[i
]].reg_rtx
== 0)
6563 allocate_reload_reg (chain
, reload_order
[i
], 0);
6566 /* First see if this pseudo is already available as reloaded
6567 for a previous insn. We cannot try to inherit for reloads
6568 that are smaller than the maximum number of registers needed
6569 for groups unless the register we would allocate cannot be used
6572 We could check here to see if this is a secondary reload for
6573 an object that is already in a register of the desired class.
6574 This would avoid the need for the secondary reload register.
6575 But this is complex because we can't easily determine what
6576 objects might want to be loaded via this reload. So let a
6577 register be allocated here. In `emit_reload_insns' we suppress
6578 one of the loads in the case described above. */
6584 enum machine_mode mode
= VOIDmode
;
6585 rtx subreg
= NULL_RTX
;
6589 else if (REG_P (rld
[r
].in
))
6591 regno
= REGNO (rld
[r
].in
);
6592 mode
= GET_MODE (rld
[r
].in
);
6594 else if (REG_P (rld
[r
].in_reg
))
6596 regno
= REGNO (rld
[r
].in_reg
);
6597 mode
= GET_MODE (rld
[r
].in_reg
);
6599 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6600 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6602 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6603 if (regno
< FIRST_PSEUDO_REGISTER
)
6604 regno
= subreg_regno (rld
[r
].in_reg
);
6607 subreg
= rld
[r
].in_reg
;
6608 byte
= SUBREG_BYTE (subreg
);
6610 mode
= GET_MODE (rld
[r
].in_reg
);
6613 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6614 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6616 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6617 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6618 rld
[r
].out
= rld
[r
].in
;
6622 /* This won't work, since REGNO can be a pseudo reg number.
6623 Also, it takes much more hair to keep track of all the things
6624 that can invalidate an inherited reload of part of a pseudoreg. */
6625 else if (GET_CODE (rld
[r
].in
) == SUBREG
6626 && REG_P (SUBREG_REG (rld
[r
].in
)))
6627 regno
= subreg_regno (rld
[r
].in
);
6631 && reg_last_reload_reg
[regno
] != 0
6632 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6633 >= GET_MODE_SIZE (mode
) + byte
)
6634 #ifdef CANNOT_CHANGE_MODE_CLASS
6635 /* Verify that the register it's in can be used in
6637 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6638 GET_MODE (reg_last_reload_reg
[regno
]),
6643 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6644 rtx last_reg
= reg_last_reload_reg
[regno
];
6646 i
= REGNO (last_reg
);
6647 byte
= compute_reload_subreg_offset (mode
,
6649 GET_MODE (last_reg
));
6650 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6651 last_class
= REGNO_REG_CLASS (i
);
6653 if (reg_reloaded_contents
[i
] == regno
6654 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6655 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6656 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6657 /* Even if we can't use this register as a reload
6658 register, we might use it for reload_override_in,
6659 if copying it to the desired class is cheap
6661 || ((register_move_cost (mode
, last_class
, rclass
)
6662 < memory_move_cost (mode
, rclass
, true))
6663 && (secondary_reload_class (1, rclass
, mode
,
6666 #ifdef SECONDARY_MEMORY_NEEDED
6667 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6672 && (rld
[r
].nregs
== max_group_size
6673 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6675 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6676 rld
[r
].when_needed
, rld
[r
].in
,
6679 /* If a group is needed, verify that all the subsequent
6680 registers still have their values intact. */
6681 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6684 for (k
= 1; k
< nr
; k
++)
6685 if (reg_reloaded_contents
[i
+ k
] != regno
6686 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6694 last_reg
= (GET_MODE (last_reg
) == mode
6695 ? last_reg
: gen_rtx_REG (mode
, i
));
6698 for (k
= 0; k
< nr
; k
++)
6699 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6702 /* We found a register that contains the
6703 value we need. If this register is the
6704 same as an `earlyclobber' operand of the
6705 current insn, just mark it as a place to
6706 reload from since we can't use it as the
6707 reload register itself. */
6709 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6710 if (reg_overlap_mentioned_for_reload_p
6711 (reg_last_reload_reg
[regno
],
6712 reload_earlyclobbers
[i1
]))
6715 if (i1
!= n_earlyclobbers
6716 || ! (free_for_value_p (i
, rld
[r
].mode
,
6718 rld
[r
].when_needed
, rld
[r
].in
,
6720 /* Don't use it if we'd clobber a pseudo reg. */
6721 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6723 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6724 /* Don't clobber the frame pointer. */
6725 || (i
== HARD_FRAME_POINTER_REGNUM
6726 && frame_pointer_needed
6728 /* Don't really use the inherited spill reg
6729 if we need it wider than we've got it. */
6730 || (GET_MODE_SIZE (rld
[r
].mode
)
6731 > GET_MODE_SIZE (mode
))
6734 /* If find_reloads chose reload_out as reload
6735 register, stay with it - that leaves the
6736 inherited register for subsequent reloads. */
6737 || (rld
[r
].out
&& rld
[r
].reg_rtx
6738 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6740 if (! rld
[r
].optional
)
6742 reload_override_in
[r
] = last_reg
;
6743 reload_inheritance_insn
[r
]
6744 = reg_reloaded_insn
[i
];
6750 /* We can use this as a reload reg. */
6751 /* Mark the register as in use for this part of
6753 mark_reload_reg_in_use (i
,
6757 rld
[r
].reg_rtx
= last_reg
;
6758 reload_inherited
[r
] = 1;
6759 reload_inheritance_insn
[r
]
6760 = reg_reloaded_insn
[i
];
6761 reload_spill_index
[r
] = i
;
6762 for (k
= 0; k
< nr
; k
++)
6763 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6771 /* Here's another way to see if the value is already lying around. */
6774 && ! reload_inherited
[r
]
6776 && (CONSTANT_P (rld
[r
].in
)
6777 || GET_CODE (rld
[r
].in
) == PLUS
6778 || REG_P (rld
[r
].in
)
6779 || MEM_P (rld
[r
].in
))
6780 && (rld
[r
].nregs
== max_group_size
6781 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6782 search_equiv
= rld
[r
].in
;
6787 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6788 -1, NULL
, 0, rld
[r
].mode
);
6794 regno
= REGNO (equiv
);
6797 /* This must be a SUBREG of a hard register.
6798 Make a new REG since this might be used in an
6799 address and not all machines support SUBREGs
6801 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6802 regno
= subreg_regno (equiv
);
6803 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6804 /* If we choose EQUIV as the reload register, but the
6805 loop below decides to cancel the inheritance, we'll
6806 end up reloading EQUIV in rld[r].mode, not the mode
6807 it had originally. That isn't safe when EQUIV isn't
6808 available as a spill register since its value might
6809 still be live at this point. */
6810 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6811 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6816 /* If we found a spill reg, reject it unless it is free
6817 and of the desired class. */
6821 int bad_for_class
= 0;
6822 int max_regno
= regno
+ rld
[r
].nregs
;
6824 for (i
= regno
; i
< max_regno
; i
++)
6826 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6828 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6833 && ! free_for_value_p (regno
, rld
[r
].mode
,
6834 rld
[r
].opnum
, rld
[r
].when_needed
,
6835 rld
[r
].in
, rld
[r
].out
, r
, 1))
6840 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6843 /* We found a register that contains the value we need.
6844 If this register is the same as an `earlyclobber' operand
6845 of the current insn, just mark it as a place to reload from
6846 since we can't use it as the reload register itself. */
6849 for (i
= 0; i
< n_earlyclobbers
; i
++)
6850 if (reg_overlap_mentioned_for_reload_p (equiv
,
6851 reload_earlyclobbers
[i
]))
6853 if (! rld
[r
].optional
)
6854 reload_override_in
[r
] = equiv
;
6859 /* If the equiv register we have found is explicitly clobbered
6860 in the current insn, it depends on the reload type if we
6861 can use it, use it for reload_override_in, or not at all.
6862 In particular, we then can't use EQUIV for a
6863 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6867 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6868 switch (rld
[r
].when_needed
)
6870 case RELOAD_FOR_OTHER_ADDRESS
:
6871 case RELOAD_FOR_INPADDR_ADDRESS
:
6872 case RELOAD_FOR_INPUT_ADDRESS
:
6873 case RELOAD_FOR_OPADDR_ADDR
:
6876 case RELOAD_FOR_INPUT
:
6877 case RELOAD_FOR_OPERAND_ADDRESS
:
6878 if (! rld
[r
].optional
)
6879 reload_override_in
[r
] = equiv
;
6885 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6886 switch (rld
[r
].when_needed
)
6888 case RELOAD_FOR_OTHER_ADDRESS
:
6889 case RELOAD_FOR_INPADDR_ADDRESS
:
6890 case RELOAD_FOR_INPUT_ADDRESS
:
6891 case RELOAD_FOR_OPADDR_ADDR
:
6892 case RELOAD_FOR_OPERAND_ADDRESS
:
6893 case RELOAD_FOR_INPUT
:
6896 if (! rld
[r
].optional
)
6897 reload_override_in
[r
] = equiv
;
6905 /* If we found an equivalent reg, say no code need be generated
6906 to load it, and use it as our reload reg. */
6908 && (regno
!= HARD_FRAME_POINTER_REGNUM
6909 || !frame_pointer_needed
))
6911 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6913 rld
[r
].reg_rtx
= equiv
;
6914 reload_spill_index
[r
] = regno
;
6915 reload_inherited
[r
] = 1;
6917 /* If reg_reloaded_valid is not set for this register,
6918 there might be a stale spill_reg_store lying around.
6919 We must clear it, since otherwise emit_reload_insns
6920 might delete the store. */
6921 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6922 spill_reg_store
[regno
] = NULL_RTX
;
6923 /* If any of the hard registers in EQUIV are spill
6924 registers, mark them as in use for this insn. */
6925 for (k
= 0; k
< nr
; k
++)
6927 i
= spill_reg_order
[regno
+ k
];
6930 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6933 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6940 /* If we found a register to use already, or if this is an optional
6941 reload, we are done. */
6942 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6946 /* No longer needed for correct operation. Might or might
6947 not give better code on the average. Want to experiment? */
6949 /* See if there is a later reload that has a class different from our
6950 class that intersects our class or that requires less register
6951 than our reload. If so, we must allocate a register to this
6952 reload now, since that reload might inherit a previous reload
6953 and take the only available register in our class. Don't do this
6954 for optional reloads since they will force all previous reloads
6955 to be allocated. Also don't do this for reloads that have been
6958 for (i
= j
+ 1; i
< n_reloads
; i
++)
6960 int s
= reload_order
[i
];
6962 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6963 && ! rld
[s
].secondary_p
)
6967 if ((rld
[s
].rclass
!= rld
[r
].rclass
6968 && reg_classes_intersect_p (rld
[r
].rclass
,
6970 || rld
[s
].nregs
< rld
[r
].nregs
)
6977 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6981 /* Now allocate reload registers for anything non-optional that
6982 didn't get one yet. */
6983 for (j
= 0; j
< n_reloads
; j
++)
6985 int r
= reload_order
[j
];
6987 /* Ignore reloads that got marked inoperative. */
6988 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6991 /* Skip reloads that already have a register allocated or are
6993 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6996 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
7000 /* If that loop got all the way, we have won. */
7007 /* Loop around and try without any inheritance. */
7012 /* First undo everything done by the failed attempt
7013 to allocate with inheritance. */
7014 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
7016 /* Some sanity tests to verify that the reloads found in the first
7017 pass are identical to the ones we have now. */
7018 gcc_assert (chain
->n_reloads
== n_reloads
);
7020 for (i
= 0; i
< n_reloads
; i
++)
7022 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
7024 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
7025 for (j
= 0; j
< n_spills
; j
++)
7026 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
7027 if (! set_reload_reg (j
, i
))
7028 failed_reload (chain
->insn
, i
);
7032 /* If we thought we could inherit a reload, because it seemed that
7033 nothing else wanted the same reload register earlier in the insn,
7034 verify that assumption, now that all reloads have been assigned.
7035 Likewise for reloads where reload_override_in has been set. */
7037 /* If doing expensive optimizations, do one preliminary pass that doesn't
7038 cancel any inheritance, but removes reloads that have been needed only
7039 for reloads that we know can be inherited. */
7040 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
7042 for (j
= 0; j
< n_reloads
; j
++)
7044 int r
= reload_order
[j
];
7046 #ifdef SECONDARY_MEMORY_NEEDED
7049 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
7050 check_reg
= rld
[r
].reg_rtx
;
7051 else if (reload_override_in
[r
]
7052 && (REG_P (reload_override_in
[r
])
7053 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
7054 check_reg
= reload_override_in
[r
];
7057 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
7058 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
7059 (reload_inherited
[r
]
7060 ? rld
[r
].out
: const0_rtx
),
7065 reload_inherited
[r
] = 0;
7066 reload_override_in
[r
] = 0;
7068 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7069 reload_override_in, then we do not need its related
7070 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7071 likewise for other reload types.
7072 We handle this by removing a reload when its only replacement
7073 is mentioned in reload_in of the reload we are going to inherit.
7074 A special case are auto_inc expressions; even if the input is
7075 inherited, we still need the address for the output. We can
7076 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7077 If we succeeded removing some reload and we are doing a preliminary
7078 pass just to remove such reloads, make another pass, since the
7079 removal of one reload might allow us to inherit another one. */
7081 && rld
[r
].out
!= rld
[r
].in
7082 && remove_address_replacements (rld
[r
].in
))
7087 #ifdef SECONDARY_MEMORY_NEEDED
7088 /* If we needed a memory location for the reload, we also have to
7089 remove its related reloads. */
7091 && rld
[r
].out
!= rld
[r
].in
7092 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7093 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7094 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7095 rld
[r
].rclass
, rld
[r
].inmode
)
7096 && remove_address_replacements
7097 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7098 rld
[r
].when_needed
)))
7107 /* Now that reload_override_in is known valid,
7108 actually override reload_in. */
7109 for (j
= 0; j
< n_reloads
; j
++)
7110 if (reload_override_in
[j
])
7111 rld
[j
].in
= reload_override_in
[j
];
7113 /* If this reload won't be done because it has been canceled or is
7114 optional and not inherited, clear reload_reg_rtx so other
7115 routines (such as subst_reloads) don't get confused. */
7116 for (j
= 0; j
< n_reloads
; j
++)
7117 if (rld
[j
].reg_rtx
!= 0
7118 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7119 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7120 && ! rld
[j
].secondary_p
)))
7122 int regno
= true_regnum (rld
[j
].reg_rtx
);
7124 if (spill_reg_order
[regno
] >= 0)
7125 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7126 rld
[j
].when_needed
, rld
[j
].mode
);
7128 reload_spill_index
[j
] = -1;
7131 /* Record which pseudos and which spill regs have output reloads. */
7132 for (j
= 0; j
< n_reloads
; j
++)
7134 int r
= reload_order
[j
];
7136 i
= reload_spill_index
[r
];
7138 /* I is nonneg if this reload uses a register.
7139 If rld[r].reg_rtx is 0, this is an optional reload
7140 that we opted to ignore. */
7141 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7142 && rld
[r
].reg_rtx
!= 0)
7144 int nregno
= REGNO (rld
[r
].out_reg
);
7147 if (nregno
< FIRST_PSEUDO_REGISTER
)
7148 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7151 SET_REGNO_REG_SET (®_has_output_reload
,
7155 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7157 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7158 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7159 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7164 /* Deallocate the reload register for reload R. This is called from
7165 remove_address_replacements. */
7168 deallocate_reload_reg (int r
)
7172 if (! rld
[r
].reg_rtx
)
7174 regno
= true_regnum (rld
[r
].reg_rtx
);
7176 if (spill_reg_order
[regno
] >= 0)
7177 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7179 reload_spill_index
[r
] = -1;
7182 /* These arrays are filled by emit_reload_insns and its subroutines. */
7183 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7184 static rtx other_input_address_reload_insns
= 0;
7185 static rtx other_input_reload_insns
= 0;
7186 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7187 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7188 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7189 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7190 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7191 static rtx operand_reload_insns
= 0;
7192 static rtx other_operand_reload_insns
= 0;
7193 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7195 /* Values to be put in spill_reg_store are put here first. Instructions
7196 must only be placed here if the associated reload register reaches
7197 the end of the instruction's reload sequence. */
7198 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7199 static HARD_REG_SET reg_reloaded_died
;
7201 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7202 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7203 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7204 adjusted register, and return true. Otherwise, return false. */
7206 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7207 enum reg_class new_class
,
7208 enum machine_mode new_mode
)
7213 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7215 unsigned regno
= REGNO (reg
);
7217 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7219 if (GET_MODE (reg
) != new_mode
)
7221 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7223 if (hard_regno_nregs
[regno
][new_mode
]
7224 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7226 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7234 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7235 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7236 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7237 adjusted register, and return true. Otherwise, return false. */
7239 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7240 enum insn_code icode
)
7243 enum reg_class new_class
= scratch_reload_class (icode
);
7244 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7246 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7247 new_class
, new_mode
);
7250 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7251 has the number J. OLD contains the value to be used as input. */
7254 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7257 rtx insn
= chain
->insn
;
7259 rtx oldequiv_reg
= 0;
7262 enum machine_mode mode
;
7265 /* delete_output_reload is only invoked properly if old contains
7266 the original pseudo register. Since this is replaced with a
7267 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7268 find the pseudo in RELOAD_IN_REG. This is also used to
7269 determine whether a secondary reload is needed. */
7270 if (reload_override_in
[j
]
7271 && (REG_P (rl
->in_reg
)
7272 || (GET_CODE (rl
->in_reg
) == SUBREG
7273 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7280 else if (REG_P (oldequiv
))
7281 oldequiv_reg
= oldequiv
;
7282 else if (GET_CODE (oldequiv
) == SUBREG
)
7283 oldequiv_reg
= SUBREG_REG (oldequiv
);
7285 reloadreg
= reload_reg_rtx_for_input
[j
];
7286 mode
= GET_MODE (reloadreg
);
7288 /* If we are reloading from a register that was recently stored in
7289 with an output-reload, see if we can prove there was
7290 actually no need to store the old value in it. */
7292 if (optimize
&& REG_P (oldequiv
)
7293 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7294 && spill_reg_store
[REGNO (oldequiv
)]
7296 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7297 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7299 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7301 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7304 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7305 oldequiv
= SUBREG_REG (oldequiv
);
7306 if (GET_MODE (oldequiv
) != VOIDmode
7307 && mode
!= GET_MODE (oldequiv
))
7308 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7310 /* Switch to the right place to emit the reload insns. */
7311 switch (rl
->when_needed
)
7314 where
= &other_input_reload_insns
;
7316 case RELOAD_FOR_INPUT
:
7317 where
= &input_reload_insns
[rl
->opnum
];
7319 case RELOAD_FOR_INPUT_ADDRESS
:
7320 where
= &input_address_reload_insns
[rl
->opnum
];
7322 case RELOAD_FOR_INPADDR_ADDRESS
:
7323 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7325 case RELOAD_FOR_OUTPUT_ADDRESS
:
7326 where
= &output_address_reload_insns
[rl
->opnum
];
7328 case RELOAD_FOR_OUTADDR_ADDRESS
:
7329 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7331 case RELOAD_FOR_OPERAND_ADDRESS
:
7332 where
= &operand_reload_insns
;
7334 case RELOAD_FOR_OPADDR_ADDR
:
7335 where
= &other_operand_reload_insns
;
7337 case RELOAD_FOR_OTHER_ADDRESS
:
7338 where
= &other_input_address_reload_insns
;
7344 push_to_sequence (*where
);
7346 /* Auto-increment addresses must be reloaded in a special way. */
7347 if (rl
->out
&& ! rl
->out_reg
)
7349 /* We are not going to bother supporting the case where a
7350 incremented register can't be copied directly from
7351 OLDEQUIV since this seems highly unlikely. */
7352 gcc_assert (rl
->secondary_in_reload
< 0);
7354 if (reload_inherited
[j
])
7355 oldequiv
= reloadreg
;
7357 old
= XEXP (rl
->in_reg
, 0);
7359 /* Prevent normal processing of this reload. */
7361 /* Output a special code sequence for this case. */
7362 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7365 /* If we are reloading a pseudo-register that was set by the previous
7366 insn, see if we can get rid of that pseudo-register entirely
7367 by redirecting the previous insn into our reload register. */
7369 else if (optimize
&& REG_P (old
)
7370 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7371 && dead_or_set_p (insn
, old
)
7372 /* This is unsafe if some other reload
7373 uses the same reg first. */
7374 && ! conflicts_with_override (reloadreg
)
7375 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7376 rl
->when_needed
, old
, rl
->out
, j
, 0))
7378 rtx temp
= PREV_INSN (insn
);
7379 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7380 temp
= PREV_INSN (temp
);
7382 && NONJUMP_INSN_P (temp
)
7383 && GET_CODE (PATTERN (temp
)) == SET
7384 && SET_DEST (PATTERN (temp
)) == old
7385 /* Make sure we can access insn_operand_constraint. */
7386 && asm_noperands (PATTERN (temp
)) < 0
7387 /* This is unsafe if operand occurs more than once in current
7388 insn. Perhaps some occurrences aren't reloaded. */
7389 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7391 rtx old
= SET_DEST (PATTERN (temp
));
7392 /* Store into the reload register instead of the pseudo. */
7393 SET_DEST (PATTERN (temp
)) = reloadreg
;
7395 /* Verify that resulting insn is valid.
7397 Note that we have replaced the destination of TEMP with
7398 RELOADREG. If TEMP references RELOADREG within an
7399 autoincrement addressing mode, then the resulting insn
7400 is ill-formed and we must reject this optimization. */
7401 extract_insn (temp
);
7402 if (constrain_operands (1)
7404 && ! find_reg_note (temp
, REG_INC
, reloadreg
)
7408 /* If the previous insn is an output reload, the source is
7409 a reload register, and its spill_reg_store entry will
7410 contain the previous destination. This is now
7412 if (REG_P (SET_SRC (PATTERN (temp
)))
7413 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7415 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7416 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7419 /* If these are the only uses of the pseudo reg,
7420 pretend for GDB it lives in the reload reg we used. */
7421 if (REG_N_DEATHS (REGNO (old
)) == 1
7422 && REG_N_SETS (REGNO (old
)) == 1)
7424 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7425 if (ira_conflicts_p
)
7426 /* Inform IRA about the change. */
7427 ira_mark_allocation_change (REGNO (old
));
7428 alter_reg (REGNO (old
), -1, false);
7432 /* Adjust any debug insns between temp and insn. */
7433 while ((temp
= NEXT_INSN (temp
)) != insn
)
7434 if (DEBUG_INSN_P (temp
))
7435 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7437 gcc_assert (NOTE_P (temp
));
7441 SET_DEST (PATTERN (temp
)) = old
;
7446 /* We can't do that, so output an insn to load RELOADREG. */
7448 /* If we have a secondary reload, pick up the secondary register
7449 and icode, if any. If OLDEQUIV and OLD are different or
7450 if this is an in-out reload, recompute whether or not we
7451 still need a secondary register and what the icode should
7452 be. If we still need a secondary register and the class or
7453 icode is different, go back to reloading from OLD if using
7454 OLDEQUIV means that we got the wrong type of register. We
7455 cannot have different class or icode due to an in-out reload
7456 because we don't make such reloads when both the input and
7457 output need secondary reload registers. */
7459 if (! special
&& rl
->secondary_in_reload
>= 0)
7461 rtx second_reload_reg
= 0;
7462 rtx third_reload_reg
= 0;
7463 int secondary_reload
= rl
->secondary_in_reload
;
7464 rtx real_oldequiv
= oldequiv
;
7467 enum insn_code icode
;
7468 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7470 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7471 and similarly for OLD.
7472 See comments in get_secondary_reload in reload.c. */
7473 /* If it is a pseudo that cannot be replaced with its
7474 equivalent MEM, we must fall back to reload_in, which
7475 will have all the necessary substitutions registered.
7476 Likewise for a pseudo that can't be replaced with its
7477 equivalent constant.
7479 Take extra care for subregs of such pseudos. Note that
7480 we cannot use reg_equiv_mem in this case because it is
7481 not in the right mode. */
7484 if (GET_CODE (tmp
) == SUBREG
)
7485 tmp
= SUBREG_REG (tmp
);
7487 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7488 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7489 || reg_equiv_constant (REGNO (tmp
)) != 0))
7491 if (! reg_equiv_mem (REGNO (tmp
))
7492 || num_not_at_initial_offset
7493 || GET_CODE (oldequiv
) == SUBREG
)
7494 real_oldequiv
= rl
->in
;
7496 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7500 if (GET_CODE (tmp
) == SUBREG
)
7501 tmp
= SUBREG_REG (tmp
);
7503 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7504 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7505 || reg_equiv_constant (REGNO (tmp
)) != 0))
7507 if (! reg_equiv_mem (REGNO (tmp
))
7508 || num_not_at_initial_offset
7509 || GET_CODE (old
) == SUBREG
)
7512 real_old
= reg_equiv_mem (REGNO (tmp
));
7515 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7516 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7518 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7520 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7521 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7522 /* We'd have to add more code for quartary reloads. */
7523 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7525 icode
= rl
->secondary_in_icode
;
7527 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7528 || (rl
->in
!= 0 && rl
->out
!= 0))
7530 secondary_reload_info sri
, sri2
;
7531 enum reg_class new_class
, new_t_class
;
7533 sri
.icode
= CODE_FOR_nothing
;
7534 sri
.prev_sri
= NULL
;
7536 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7540 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7541 second_reload_reg
= 0;
7542 else if (new_class
== NO_REGS
)
7544 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7546 (enum insn_code
) sri
.icode
))
7548 icode
= (enum insn_code
) sri
.icode
;
7549 third_reload_reg
= 0;
7554 real_oldequiv
= real_old
;
7557 else if (sri
.icode
!= CODE_FOR_nothing
)
7558 /* We currently lack a way to express this in reloads. */
7562 sri2
.icode
= CODE_FOR_nothing
;
7563 sri2
.prev_sri
= &sri
;
7565 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7568 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7570 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7574 third_reload_reg
= 0;
7575 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7580 real_oldequiv
= real_old
;
7583 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7585 rtx intermediate
= second_reload_reg
;
7587 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7589 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7593 second_reload_reg
= intermediate
;
7594 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7599 real_oldequiv
= real_old
;
7602 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7604 rtx intermediate
= second_reload_reg
;
7606 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7608 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7611 second_reload_reg
= intermediate
;
7612 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7617 real_oldequiv
= real_old
;
7622 /* This could be handled more intelligently too. */
7624 real_oldequiv
= real_old
;
7629 /* If we still need a secondary reload register, check
7630 to see if it is being used as a scratch or intermediate
7631 register and generate code appropriately. If we need
7632 a scratch register, use REAL_OLDEQUIV since the form of
7633 the insn may depend on the actual address if it is
7636 if (second_reload_reg
)
7638 if (icode
!= CODE_FOR_nothing
)
7640 /* We'd have to add extra code to handle this case. */
7641 gcc_assert (!third_reload_reg
);
7643 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7644 second_reload_reg
));
7649 /* See if we need a scratch register to load the
7650 intermediate register (a tertiary reload). */
7651 if (tertiary_icode
!= CODE_FOR_nothing
)
7653 emit_insn ((GEN_FCN (tertiary_icode
)
7654 (second_reload_reg
, real_oldequiv
,
7655 third_reload_reg
)));
7657 else if (third_reload_reg
)
7659 gen_reload (third_reload_reg
, real_oldequiv
,
7662 gen_reload (second_reload_reg
, third_reload_reg
,
7667 gen_reload (second_reload_reg
, real_oldequiv
,
7671 oldequiv
= second_reload_reg
;
7676 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7678 rtx real_oldequiv
= oldequiv
;
7680 if ((REG_P (oldequiv
)
7681 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7682 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7683 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7684 || (GET_CODE (oldequiv
) == SUBREG
7685 && REG_P (SUBREG_REG (oldequiv
))
7686 && (REGNO (SUBREG_REG (oldequiv
))
7687 >= FIRST_PSEUDO_REGISTER
)
7688 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7689 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7690 || (CONSTANT_P (oldequiv
)
7691 && (targetm
.preferred_reload_class (oldequiv
,
7692 REGNO_REG_CLASS (REGNO (reloadreg
)))
7694 real_oldequiv
= rl
->in
;
7695 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7699 if (cfun
->can_throw_non_call_exceptions
)
7700 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7702 /* End this sequence. */
7703 *where
= get_insns ();
7706 /* Update reload_override_in so that delete_address_reloads_1
7707 can see the actual register usage. */
7709 reload_override_in
[j
] = oldequiv
;
7712 /* Generate insns to for the output reload RL, which is for the insn described
7713 by CHAIN and has the number J. */
7715 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7719 rtx insn
= chain
->insn
;
7722 enum machine_mode mode
;
7726 if (rl
->when_needed
== RELOAD_OTHER
)
7729 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7731 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7732 mode
= GET_MODE (rl_reg_rtx
);
7734 reloadreg
= rl_reg_rtx
;
7736 /* If we need two reload regs, set RELOADREG to the intermediate
7737 one, since it will be stored into OLD. We might need a secondary
7738 register only for an input reload, so check again here. */
7740 if (rl
->secondary_out_reload
>= 0)
7743 int secondary_reload
= rl
->secondary_out_reload
;
7744 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7746 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7747 && reg_equiv_mem (REGNO (old
)) != 0)
7748 real_old
= reg_equiv_mem (REGNO (old
));
7750 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7752 rtx second_reloadreg
= reloadreg
;
7753 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7755 /* See if RELOADREG is to be used as a scratch register
7756 or as an intermediate register. */
7757 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7759 /* We'd have to add extra code to handle this case. */
7760 gcc_assert (tertiary_reload
< 0);
7762 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7763 (real_old
, second_reloadreg
, reloadreg
)));
7768 /* See if we need both a scratch and intermediate reload
7771 enum insn_code tertiary_icode
7772 = rld
[secondary_reload
].secondary_out_icode
;
7774 /* We'd have to add more code for quartary reloads. */
7775 gcc_assert (tertiary_reload
< 0
7776 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7778 if (GET_MODE (reloadreg
) != mode
)
7779 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7781 if (tertiary_icode
!= CODE_FOR_nothing
)
7783 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7785 /* Copy primary reload reg to secondary reload reg.
7786 (Note that these have been swapped above, then
7787 secondary reload reg to OLD using our insn.) */
7789 /* If REAL_OLD is a paradoxical SUBREG, remove it
7790 and try to put the opposite SUBREG on
7792 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7794 gen_reload (reloadreg
, second_reloadreg
,
7795 rl
->opnum
, rl
->when_needed
);
7796 emit_insn ((GEN_FCN (tertiary_icode
)
7797 (real_old
, reloadreg
, third_reloadreg
)));
7803 /* Copy between the reload regs here and then to
7806 gen_reload (reloadreg
, second_reloadreg
,
7807 rl
->opnum
, rl
->when_needed
);
7808 if (tertiary_reload
>= 0)
7810 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7812 gen_reload (third_reloadreg
, reloadreg
,
7813 rl
->opnum
, rl
->when_needed
);
7814 reloadreg
= third_reloadreg
;
7821 /* Output the last reload insn. */
7826 /* Don't output the last reload if OLD is not the dest of
7827 INSN and is in the src and is clobbered by INSN. */
7828 if (! flag_expensive_optimizations
7830 || !(set
= single_set (insn
))
7831 || rtx_equal_p (old
, SET_DEST (set
))
7832 || !reg_mentioned_p (old
, SET_SRC (set
))
7833 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7834 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7835 gen_reload (old
, reloadreg
, rl
->opnum
,
7839 /* Look at all insns we emitted, just to be safe. */
7840 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7843 rtx pat
= PATTERN (p
);
7845 /* If this output reload doesn't come from a spill reg,
7846 clear any memory of reloaded copies of the pseudo reg.
7847 If this output reload comes from a spill reg,
7848 reg_has_output_reload will make this do nothing. */
7849 note_stores (pat
, forget_old_reloads_1
, NULL
);
7851 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7853 rtx set
= single_set (insn
);
7854 if (reload_spill_index
[j
] < 0
7856 && SET_SRC (set
) == rl_reg_rtx
)
7858 int src
= REGNO (SET_SRC (set
));
7860 reload_spill_index
[j
] = src
;
7861 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7862 if (find_regno_note (insn
, REG_DEAD
, src
))
7863 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7865 if (HARD_REGISTER_P (rl_reg_rtx
))
7867 int s
= rl
->secondary_out_reload
;
7868 set
= single_set (p
);
7869 /* If this reload copies only to the secondary reload
7870 register, the secondary reload does the actual
7872 if (s
>= 0 && set
== NULL_RTX
)
7873 /* We can't tell what function the secondary reload
7874 has and where the actual store to the pseudo is
7875 made; leave new_spill_reg_store alone. */
7878 && SET_SRC (set
) == rl_reg_rtx
7879 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7881 /* Usually the next instruction will be the
7882 secondary reload insn; if we can confirm
7883 that it is, setting new_spill_reg_store to
7884 that insn will allow an extra optimization. */
7885 rtx s_reg
= rld
[s
].reg_rtx
;
7886 rtx next
= NEXT_INSN (p
);
7887 rld
[s
].out
= rl
->out
;
7888 rld
[s
].out_reg
= rl
->out_reg
;
7889 set
= single_set (next
);
7890 if (set
&& SET_SRC (set
) == s_reg
7891 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7893 SET_HARD_REG_BIT (reg_is_output_reload
,
7895 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7898 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7899 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7904 if (rl
->when_needed
== RELOAD_OTHER
)
7906 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7907 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7910 output_reload_insns
[rl
->opnum
] = get_insns ();
7912 if (cfun
->can_throw_non_call_exceptions
)
7913 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7918 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7919 and has the number J. */
7921 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7923 rtx insn
= chain
->insn
;
7924 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7925 ? rl
->in_reg
: rl
->in
);
7926 rtx reg_rtx
= rl
->reg_rtx
;
7930 enum machine_mode mode
;
7932 /* Determine the mode to reload in.
7933 This is very tricky because we have three to choose from.
7934 There is the mode the insn operand wants (rl->inmode).
7935 There is the mode of the reload register RELOADREG.
7936 There is the intrinsic mode of the operand, which we could find
7937 by stripping some SUBREGs.
7938 It turns out that RELOADREG's mode is irrelevant:
7939 we can change that arbitrarily.
7941 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7942 then the reload reg may not support QImode moves, so use SImode.
7943 If foo is in memory due to spilling a pseudo reg, this is safe,
7944 because the QImode value is in the least significant part of a
7945 slot big enough for a SImode. If foo is some other sort of
7946 memory reference, then it is impossible to reload this case,
7947 so previous passes had better make sure this never happens.
7949 Then consider a one-word union which has SImode and one of its
7950 members is a float, being fetched as (SUBREG:SF union:SI).
7951 We must fetch that as SFmode because we could be loading into
7952 a float-only register. In this case OLD's mode is correct.
7954 Consider an immediate integer: it has VOIDmode. Here we need
7955 to get a mode from something else.
7957 In some cases, there is a fourth mode, the operand's
7958 containing mode. If the insn specifies a containing mode for
7959 this operand, it overrides all others.
7961 I am not sure whether the algorithm here is always right,
7962 but it does the right things in those cases. */
7964 mode
= GET_MODE (old
);
7965 if (mode
== VOIDmode
)
7968 /* We cannot use gen_lowpart_common since it can do the wrong thing
7969 when REG_RTX has a multi-word mode. Note that REG_RTX must
7970 always be a REG here. */
7971 if (GET_MODE (reg_rtx
) != mode
)
7972 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7974 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7977 /* AUTO_INC reloads need to be handled even if inherited. We got an
7978 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7979 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7980 && ! rtx_equal_p (reg_rtx
, old
)
7982 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7984 /* When inheriting a wider reload, we have a MEM in rl->in,
7985 e.g. inheriting a SImode output reload for
7986 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7987 if (optimize
&& reload_inherited
[j
] && rl
->in
7989 && MEM_P (rl
->in_reg
)
7990 && reload_spill_index
[j
] >= 0
7991 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7992 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7994 /* If we are reloading a register that was recently stored in with an
7995 output-reload, see if we can prove there was
7996 actually no need to store the old value in it. */
7999 && (reload_inherited
[j
] || reload_override_in
[j
])
8002 && spill_reg_store
[REGNO (reg_rtx
)] != 0
8004 /* There doesn't seem to be any reason to restrict this to pseudos
8005 and doing so loses in the case where we are copying from a
8006 register of the wrong class. */
8007 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
8009 /* The insn might have already some references to stackslots
8010 replaced by MEMs, while reload_out_reg still names the
8012 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
8013 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
8014 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
8017 /* Do output reloading for reload RL, which is for the insn described by
8018 CHAIN and has the number J.
8019 ??? At some point we need to support handling output reloads of
8020 JUMP_INSNs or insns that set cc0. */
8022 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
8025 rtx insn
= chain
->insn
;
8026 /* If this is an output reload that stores something that is
8027 not loaded in this same reload, see if we can eliminate a previous
8029 rtx pseudo
= rl
->out_reg
;
8030 rtx reg_rtx
= rl
->reg_rtx
;
8032 if (rl
->out
&& reg_rtx
)
8034 enum machine_mode mode
;
8036 /* Determine the mode to reload in.
8037 See comments above (for input reloading). */
8038 mode
= GET_MODE (rl
->out
);
8039 if (mode
== VOIDmode
)
8041 /* VOIDmode should never happen for an output. */
8042 if (asm_noperands (PATTERN (insn
)) < 0)
8043 /* It's the compiler's fault. */
8044 fatal_insn ("VOIDmode on an output", insn
);
8045 error_for_asm (insn
, "output operand is constant in %<asm%>");
8046 /* Prevent crash--use something we know is valid. */
8048 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8050 if (GET_MODE (reg_rtx
) != mode
)
8051 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8053 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8058 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8059 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8060 && reg_last_reload_reg
[REGNO (pseudo
)])
8062 int pseudo_no
= REGNO (pseudo
);
8063 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8065 /* We don't need to test full validity of last_regno for
8066 inherit here; we only want to know if the store actually
8067 matches the pseudo. */
8068 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8069 && reg_reloaded_contents
[last_regno
] == pseudo_no
8070 && spill_reg_store
[last_regno
]
8071 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8072 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8078 || rtx_equal_p (old
, reg_rtx
))
8081 /* An output operand that dies right away does need a reload,
8082 but need not be copied from it. Show the new location in the
8084 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8085 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8087 XEXP (note
, 0) = reg_rtx
;
8090 /* Likewise for a SUBREG of an operand that dies. */
8091 else if (GET_CODE (old
) == SUBREG
8092 && REG_P (SUBREG_REG (old
))
8093 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8096 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8099 else if (GET_CODE (old
) == SCRATCH
)
8100 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8101 but we don't want to make an output reload. */
8104 /* If is a JUMP_INSN, we can't support output reloads yet. */
8105 gcc_assert (NONJUMP_INSN_P (insn
));
8107 emit_output_reload_insns (chain
, rld
+ j
, j
);
8110 /* A reload copies values of MODE from register SRC to register DEST.
8111 Return true if it can be treated for inheritance purposes like a
8112 group of reloads, each one reloading a single hard register. The
8113 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8114 occupy the same number of hard registers. */
8117 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8118 int src ATTRIBUTE_UNUSED
,
8119 enum machine_mode mode ATTRIBUTE_UNUSED
)
8121 #ifdef CANNOT_CHANGE_MODE_CLASS
8122 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8123 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8129 /* Output insns to reload values in and out of the chosen reload regs. */
8132 emit_reload_insns (struct insn_chain
*chain
)
8134 rtx insn
= chain
->insn
;
8138 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8140 for (j
= 0; j
< reload_n_operands
; j
++)
8141 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8142 = inpaddr_address_reload_insns
[j
]
8143 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8144 = outaddr_address_reload_insns
[j
]
8145 = other_output_reload_insns
[j
] = 0;
8146 other_input_address_reload_insns
= 0;
8147 other_input_reload_insns
= 0;
8148 operand_reload_insns
= 0;
8149 other_operand_reload_insns
= 0;
8151 /* Dump reloads into the dump file. */
8154 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8155 debug_reload_to_stream (dump_file
);
8158 for (j
= 0; j
< n_reloads
; j
++)
8159 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8163 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8164 new_spill_reg_store
[i
] = 0;
8167 /* Now output the instructions to copy the data into and out of the
8168 reload registers. Do these in the order that the reloads were reported,
8169 since reloads of base and index registers precede reloads of operands
8170 and the operands may need the base and index registers reloaded. */
8172 for (j
= 0; j
< n_reloads
; j
++)
8174 do_input_reload (chain
, rld
+ j
, j
);
8175 do_output_reload (chain
, rld
+ j
, j
);
8178 /* Now write all the insns we made for reloads in the order expected by
8179 the allocation functions. Prior to the insn being reloaded, we write
8180 the following reloads:
8182 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8184 RELOAD_OTHER reloads.
8186 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8187 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8188 RELOAD_FOR_INPUT reload for the operand.
8190 RELOAD_FOR_OPADDR_ADDRS reloads.
8192 RELOAD_FOR_OPERAND_ADDRESS reloads.
8194 After the insn being reloaded, we write the following:
8196 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8197 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8198 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8199 reloads for the operand. The RELOAD_OTHER output reloads are
8200 output in descending order by reload number. */
8202 emit_insn_before (other_input_address_reload_insns
, insn
);
8203 emit_insn_before (other_input_reload_insns
, insn
);
8205 for (j
= 0; j
< reload_n_operands
; j
++)
8207 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8208 emit_insn_before (input_address_reload_insns
[j
], insn
);
8209 emit_insn_before (input_reload_insns
[j
], insn
);
8212 emit_insn_before (other_operand_reload_insns
, insn
);
8213 emit_insn_before (operand_reload_insns
, insn
);
8215 for (j
= 0; j
< reload_n_operands
; j
++)
8217 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8218 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8219 x
= emit_insn_after (output_reload_insns
[j
], x
);
8220 emit_insn_after (other_output_reload_insns
[j
], x
);
8223 /* For all the spill regs newly reloaded in this instruction,
8224 record what they were reloaded from, so subsequent instructions
8225 can inherit the reloads.
8227 Update spill_reg_store for the reloads of this insn.
8228 Copy the elements that were updated in the loop above. */
8230 for (j
= 0; j
< n_reloads
; j
++)
8232 int r
= reload_order
[j
];
8233 int i
= reload_spill_index
[r
];
8235 /* If this is a non-inherited input reload from a pseudo, we must
8236 clear any memory of a previous store to the same pseudo. Only do
8237 something if there will not be an output reload for the pseudo
8239 if (rld
[r
].in_reg
!= 0
8240 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8242 rtx reg
= rld
[r
].in_reg
;
8244 if (GET_CODE (reg
) == SUBREG
)
8245 reg
= SUBREG_REG (reg
);
8248 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8249 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8251 int nregno
= REGNO (reg
);
8253 if (reg_last_reload_reg
[nregno
])
8255 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8257 if (reg_reloaded_contents
[last_regno
] == nregno
)
8258 spill_reg_store
[last_regno
] = 0;
8263 /* I is nonneg if this reload used a register.
8264 If rld[r].reg_rtx is 0, this is an optional reload
8265 that we opted to ignore. */
8267 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8269 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8272 /* For a multi register reload, we need to check if all or part
8273 of the value lives to the end. */
8274 for (k
= 0; k
< nr
; k
++)
8275 if (reload_reg_reaches_end_p (i
+ k
, r
))
8276 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8278 /* Maybe the spill reg contains a copy of reload_out. */
8280 && (REG_P (rld
[r
].out
)
8282 ? REG_P (rld
[r
].out_reg
)
8283 /* The reload value is an auto-modification of
8284 some kind. For PRE_INC, POST_INC, PRE_DEC
8285 and POST_DEC, we record an equivalence
8286 between the reload register and the operand
8287 on the optimistic assumption that we can make
8288 the equivalence hold. reload_as_needed must
8289 then either make it hold or invalidate the
8292 PRE_MODIFY and POST_MODIFY addresses are reloaded
8293 somewhat differently, and allowing them here leads
8295 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8296 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8300 reg
= reload_reg_rtx_for_output
[r
];
8301 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8303 enum machine_mode mode
= GET_MODE (reg
);
8304 int regno
= REGNO (reg
);
8305 int nregs
= hard_regno_nregs
[regno
][mode
];
8306 rtx out
= (REG_P (rld
[r
].out
)
8310 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8311 int out_regno
= REGNO (out
);
8312 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8313 : hard_regno_nregs
[out_regno
][mode
]);
8316 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8317 spill_reg_stored_to
[regno
] = out
;
8318 reg_last_reload_reg
[out_regno
] = reg
;
8320 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8321 && nregs
== out_nregs
8322 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8324 /* If OUT_REGNO is a hard register, it may occupy more than
8325 one register. If it does, say what is in the
8326 rest of the registers assuming that both registers
8327 agree on how many words the object takes. If not,
8328 invalidate the subsequent registers. */
8330 if (HARD_REGISTER_NUM_P (out_regno
))
8331 for (k
= 1; k
< out_nregs
; k
++)
8332 reg_last_reload_reg
[out_regno
+ k
]
8333 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8335 /* Now do the inverse operation. */
8336 for (k
= 0; k
< nregs
; k
++)
8338 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8339 reg_reloaded_contents
[regno
+ k
]
8340 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8343 reg_reloaded_insn
[regno
+ k
] = insn
;
8344 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8345 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8346 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8349 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8354 /* Maybe the spill reg contains a copy of reload_in. Only do
8355 something if there will not be an output reload for
8356 the register being reloaded. */
8357 else if (rld
[r
].out_reg
== 0
8359 && ((REG_P (rld
[r
].in
)
8360 && !HARD_REGISTER_P (rld
[r
].in
)
8361 && !REGNO_REG_SET_P (®_has_output_reload
,
8363 || (REG_P (rld
[r
].in_reg
)
8364 && !REGNO_REG_SET_P (®_has_output_reload
,
8365 REGNO (rld
[r
].in_reg
))))
8366 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8370 reg
= reload_reg_rtx_for_input
[r
];
8371 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8373 enum machine_mode mode
;
8381 mode
= GET_MODE (reg
);
8382 regno
= REGNO (reg
);
8383 nregs
= hard_regno_nregs
[regno
][mode
];
8384 if (REG_P (rld
[r
].in
)
8385 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8387 else if (REG_P (rld
[r
].in_reg
))
8390 in
= XEXP (rld
[r
].in_reg
, 0);
8391 in_regno
= REGNO (in
);
8393 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8394 : hard_regno_nregs
[in_regno
][mode
]);
8396 reg_last_reload_reg
[in_regno
] = reg
;
8398 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8399 && nregs
== in_nregs
8400 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8402 if (HARD_REGISTER_NUM_P (in_regno
))
8403 for (k
= 1; k
< in_nregs
; k
++)
8404 reg_last_reload_reg
[in_regno
+ k
]
8405 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8407 /* Unless we inherited this reload, show we haven't
8408 recently done a store.
8409 Previous stores of inherited auto_inc expressions
8410 also have to be discarded. */
8411 if (! reload_inherited
[r
]
8412 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8413 spill_reg_store
[regno
] = 0;
8415 for (k
= 0; k
< nregs
; k
++)
8417 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8418 reg_reloaded_contents
[regno
+ k
]
8419 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8422 reg_reloaded_insn
[regno
+ k
] = insn
;
8423 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8424 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8425 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8428 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8435 /* The following if-statement was #if 0'd in 1.34 (or before...).
8436 It's reenabled in 1.35 because supposedly nothing else
8437 deals with this problem. */
8439 /* If a register gets output-reloaded from a non-spill register,
8440 that invalidates any previous reloaded copy of it.
8441 But forget_old_reloads_1 won't get to see it, because
8442 it thinks only about the original insn. So invalidate it here.
8443 Also do the same thing for RELOAD_OTHER constraints where the
8444 output is discarded. */
8446 && ((rld
[r
].out
!= 0
8447 && (REG_P (rld
[r
].out
)
8448 || (MEM_P (rld
[r
].out
)
8449 && REG_P (rld
[r
].out_reg
))))
8450 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8451 && REG_P (rld
[r
].out_reg
))))
8453 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8454 ? rld
[r
].out
: rld
[r
].out_reg
);
8455 int out_regno
= REGNO (out
);
8456 enum machine_mode mode
= GET_MODE (out
);
8458 /* REG_RTX is now set or clobbered by the main instruction.
8459 As the comment above explains, forget_old_reloads_1 only
8460 sees the original instruction, and there is no guarantee
8461 that the original instruction also clobbered REG_RTX.
8462 For example, if find_reloads sees that the input side of
8463 a matched operand pair dies in this instruction, it may
8464 use the input register as the reload register.
8466 Calling forget_old_reloads_1 is a waste of effort if
8467 REG_RTX is also the output register.
8469 If we know that REG_RTX holds the value of a pseudo
8470 register, the code after the call will record that fact. */
8471 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8472 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8474 if (!HARD_REGISTER_NUM_P (out_regno
))
8476 rtx src_reg
, store_insn
= NULL_RTX
;
8478 reg_last_reload_reg
[out_regno
] = 0;
8480 /* If we can find a hard register that is stored, record
8481 the storing insn so that we may delete this insn with
8482 delete_output_reload. */
8483 src_reg
= reload_reg_rtx_for_output
[r
];
8487 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8488 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8494 /* If this is an optional reload, try to find the
8495 source reg from an input reload. */
8496 rtx set
= single_set (insn
);
8497 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8501 src_reg
= SET_SRC (set
);
8503 for (k
= 0; k
< n_reloads
; k
++)
8505 if (rld
[k
].in
== src_reg
)
8507 src_reg
= reload_reg_rtx_for_input
[k
];
8513 if (src_reg
&& REG_P (src_reg
)
8514 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8516 int src_regno
, src_nregs
, k
;
8519 gcc_assert (GET_MODE (src_reg
) == mode
);
8520 src_regno
= REGNO (src_reg
);
8521 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8522 /* The place where to find a death note varies with
8523 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8524 necessarily checked exactly in the code that moves
8525 notes, so just check both locations. */
8526 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8527 if (! note
&& store_insn
)
8528 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8529 for (k
= 0; k
< src_nregs
; k
++)
8531 spill_reg_store
[src_regno
+ k
] = store_insn
;
8532 spill_reg_stored_to
[src_regno
+ k
] = out
;
8533 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8534 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8535 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8536 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8537 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8539 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8542 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8544 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8546 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8548 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8550 reg_last_reload_reg
[out_regno
] = src_reg
;
8551 /* We have to set reg_has_output_reload here, or else
8552 forget_old_reloads_1 will clear reg_last_reload_reg
8554 SET_REGNO_REG_SET (®_has_output_reload
,
8560 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8562 for (k
= 0; k
< out_nregs
; k
++)
8563 reg_last_reload_reg
[out_regno
+ k
] = 0;
8567 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8570 /* Go through the motions to emit INSN and test if it is strictly valid.
8571 Return the emitted insn if valid, else return NULL. */
8574 emit_insn_if_valid_for_reload (rtx insn
)
8576 rtx last
= get_last_insn ();
8579 insn
= emit_insn (insn
);
8580 code
= recog_memoized (insn
);
8584 extract_insn (insn
);
8585 /* We want constrain operands to treat this insn strictly in its
8586 validity determination, i.e., the way it would after reload has
8588 if (constrain_operands (1))
8592 delete_insns_since (last
);
8596 /* Emit code to perform a reload from IN (which may be a reload register) to
8597 OUT (which may also be a reload register). IN or OUT is from operand
8598 OPNUM with reload type TYPE.
8600 Returns first insn emitted. */
8603 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8605 rtx last
= get_last_insn ();
8607 #ifdef SECONDARY_MEMORY_NEEDED
8611 /* If IN is a paradoxical SUBREG, remove it and try to put the
8612 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8613 if (!strip_paradoxical_subreg (&in
, &out
))
8614 strip_paradoxical_subreg (&out
, &in
);
8616 /* How to do this reload can get quite tricky. Normally, we are being
8617 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8618 register that didn't get a hard register. In that case we can just
8619 call emit_move_insn.
8621 We can also be asked to reload a PLUS that adds a register or a MEM to
8622 another register, constant or MEM. This can occur during frame pointer
8623 elimination and while reloading addresses. This case is handled by
8624 trying to emit a single insn to perform the add. If it is not valid,
8625 we use a two insn sequence.
8627 Or we can be asked to reload an unary operand that was a fragment of
8628 an addressing mode, into a register. If it isn't recognized as-is,
8629 we try making the unop operand and the reload-register the same:
8630 (set reg:X (unop:X expr:Y))
8631 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8633 Finally, we could be called to handle an 'o' constraint by putting
8634 an address into a register. In that case, we first try to do this
8635 with a named pattern of "reload_load_address". If no such pattern
8636 exists, we just emit a SET insn and hope for the best (it will normally
8637 be valid on machines that use 'o').
8639 This entire process is made complex because reload will never
8640 process the insns we generate here and so we must ensure that
8641 they will fit their constraints and also by the fact that parts of
8642 IN might be being reloaded separately and replaced with spill registers.
8643 Because of this, we are, in some sense, just guessing the right approach
8644 here. The one listed above seems to work.
8646 ??? At some point, this whole thing needs to be rethought. */
8648 if (GET_CODE (in
) == PLUS
8649 && (REG_P (XEXP (in
, 0))
8650 || GET_CODE (XEXP (in
, 0)) == SUBREG
8651 || MEM_P (XEXP (in
, 0)))
8652 && (REG_P (XEXP (in
, 1))
8653 || GET_CODE (XEXP (in
, 1)) == SUBREG
8654 || CONSTANT_P (XEXP (in
, 1))
8655 || MEM_P (XEXP (in
, 1))))
8657 /* We need to compute the sum of a register or a MEM and another
8658 register, constant, or MEM, and put it into the reload
8659 register. The best possible way of doing this is if the machine
8660 has a three-operand ADD insn that accepts the required operands.
8662 The simplest approach is to try to generate such an insn and see if it
8663 is recognized and matches its constraints. If so, it can be used.
8665 It might be better not to actually emit the insn unless it is valid,
8666 but we need to pass the insn as an operand to `recog' and
8667 `extract_insn' and it is simpler to emit and then delete the insn if
8668 not valid than to dummy things up. */
8670 rtx op0
, op1
, tem
, insn
;
8671 enum insn_code code
;
8673 op0
= find_replacement (&XEXP (in
, 0));
8674 op1
= find_replacement (&XEXP (in
, 1));
8676 /* Since constraint checking is strict, commutativity won't be
8677 checked, so we need to do that here to avoid spurious failure
8678 if the add instruction is two-address and the second operand
8679 of the add is the same as the reload reg, which is frequently
8680 the case. If the insn would be A = B + A, rearrange it so
8681 it will be A = A + B as constrain_operands expects. */
8683 if (REG_P (XEXP (in
, 1))
8684 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8685 tem
= op0
, op0
= op1
, op1
= tem
;
8687 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8688 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8690 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8694 /* If that failed, we must use a conservative two-insn sequence.
8696 Use a move to copy one operand into the reload register. Prefer
8697 to reload a constant, MEM or pseudo since the move patterns can
8698 handle an arbitrary operand. If OP1 is not a constant, MEM or
8699 pseudo and OP1 is not a valid operand for an add instruction, then
8702 After reloading one of the operands into the reload register, add
8703 the reload register to the output register.
8705 If there is another way to do this for a specific machine, a
8706 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8709 code
= optab_handler (add_optab
, GET_MODE (out
));
8711 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8713 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8714 || (code
!= CODE_FOR_nothing
8715 && !insn_operand_matches (code
, 2, op1
)))
8716 tem
= op0
, op0
= op1
, op1
= tem
;
8718 gen_reload (out
, op0
, opnum
, type
);
8720 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8721 This fixes a problem on the 32K where the stack pointer cannot
8722 be used as an operand of an add insn. */
8724 if (rtx_equal_p (op0
, op1
))
8727 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8730 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8731 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8735 /* If that failed, copy the address register to the reload register.
8736 Then add the constant to the reload register. */
8738 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8739 gen_reload (out
, op1
, opnum
, type
);
8740 insn
= emit_insn (gen_add2_insn (out
, op0
));
8741 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8744 #ifdef SECONDARY_MEMORY_NEEDED
8745 /* If we need a memory location to do the move, do it that way. */
8746 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8747 (REG_P (tem1
) && REG_P (tem2
)))
8748 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8749 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8750 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8751 REGNO_REG_CLASS (REGNO (tem2
)),
8754 /* Get the memory to use and rewrite both registers to its mode. */
8755 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8757 if (GET_MODE (loc
) != GET_MODE (out
))
8758 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8760 if (GET_MODE (loc
) != GET_MODE (in
))
8761 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8763 gen_reload (loc
, in
, opnum
, type
);
8764 gen_reload (out
, loc
, opnum
, type
);
8767 else if (REG_P (out
) && UNARY_P (in
))
8774 op1
= find_replacement (&XEXP (in
, 0));
8775 if (op1
!= XEXP (in
, 0))
8776 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8778 /* First, try a plain SET. */
8779 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8783 /* If that failed, move the inner operand to the reload
8784 register, and try the same unop with the inner expression
8785 replaced with the reload register. */
8787 if (GET_MODE (op1
) != GET_MODE (out
))
8788 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8792 gen_reload (out_moded
, op1
, opnum
, type
);
8795 = gen_rtx_SET (VOIDmode
, out
,
8796 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8798 insn
= emit_insn_if_valid_for_reload (insn
);
8801 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8805 fatal_insn ("failure trying to reload:", set
);
8807 /* If IN is a simple operand, use gen_move_insn. */
8808 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8810 tem
= emit_insn (gen_move_insn (out
, in
));
8811 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8812 mark_jump_label (in
, tem
, 0);
8815 #ifdef HAVE_reload_load_address
8816 else if (HAVE_reload_load_address
)
8817 emit_insn (gen_reload_load_address (out
, in
));
8820 /* Otherwise, just write (set OUT IN) and hope for the best. */
8822 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8824 /* Return the first insn emitted.
8825 We can not just return get_last_insn, because there may have
8826 been multiple instructions emitted. Also note that gen_move_insn may
8827 emit more than one insn itself, so we can not assume that there is one
8828 insn emitted per emit_insn_before call. */
8830 return last
? NEXT_INSN (last
) : get_insns ();
8833 /* Delete a previously made output-reload whose result we now believe
8834 is not needed. First we double-check.
8836 INSN is the insn now being processed.
8837 LAST_RELOAD_REG is the hard register number for which we want to delete
8838 the last output reload.
8839 J is the reload-number that originally used REG. The caller has made
8840 certain that reload J doesn't use REG any longer for input.
8841 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8844 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8846 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8847 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8850 int n_inherited
= 0;
8856 /* It is possible that this reload has been only used to set another reload
8857 we eliminated earlier and thus deleted this instruction too. */
8858 if (INSN_DELETED_P (output_reload_insn
))
8861 /* Get the raw pseudo-register referred to. */
8863 while (GET_CODE (reg
) == SUBREG
)
8864 reg
= SUBREG_REG (reg
);
8865 substed
= reg_equiv_memory_loc (REGNO (reg
));
8867 /* This is unsafe if the operand occurs more often in the current
8868 insn than it is inherited. */
8869 for (k
= n_reloads
- 1; k
>= 0; k
--)
8871 rtx reg2
= rld
[k
].in
;
8874 if (MEM_P (reg2
) || reload_override_in
[k
])
8875 reg2
= rld
[k
].in_reg
;
8877 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8878 reg2
= XEXP (rld
[k
].in_reg
, 0);
8880 while (GET_CODE (reg2
) == SUBREG
)
8881 reg2
= SUBREG_REG (reg2
);
8882 if (rtx_equal_p (reg2
, reg
))
8884 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8890 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8891 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8892 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8895 n_occurrences
+= count_occurrences (PATTERN (insn
),
8896 eliminate_regs (substed
, VOIDmode
,
8898 for (i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8900 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8901 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8903 if (n_occurrences
> n_inherited
)
8906 regno
= REGNO (reg
);
8907 if (regno
>= FIRST_PSEUDO_REGISTER
)
8910 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8912 /* If the pseudo-reg we are reloading is no longer referenced
8913 anywhere between the store into it and here,
8914 and we're within the same basic block, then the value can only
8915 pass through the reload reg and end up here.
8916 Otherwise, give up--return. */
8917 for (i1
= NEXT_INSN (output_reload_insn
);
8918 i1
!= insn
; i1
= NEXT_INSN (i1
))
8920 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8922 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8923 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8925 /* If this is USE in front of INSN, we only have to check that
8926 there are no more references than accounted for by inheritance. */
8927 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8929 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8930 i1
= NEXT_INSN (i1
);
8932 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8938 /* We will be deleting the insn. Remove the spill reg information. */
8939 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8941 spill_reg_store
[last_reload_reg
+ k
] = 0;
8942 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8945 /* The caller has already checked that REG dies or is set in INSN.
8946 It has also checked that we are optimizing, and thus some
8947 inaccuracies in the debugging information are acceptable.
8948 So we could just delete output_reload_insn. But in some cases
8949 we can improve the debugging information without sacrificing
8950 optimization - maybe even improving the code: See if the pseudo
8951 reg has been completely replaced with reload regs. If so, delete
8952 the store insn and forget we had a stack slot for the pseudo. */
8953 if (rld
[j
].out
!= rld
[j
].in
8954 && REG_N_DEATHS (REGNO (reg
)) == 1
8955 && REG_N_SETS (REGNO (reg
)) == 1
8956 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8957 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8961 /* We know that it was used only between here and the beginning of
8962 the current basic block. (We also know that the last use before
8963 INSN was the output reload we are thinking of deleting, but never
8964 mind that.) Search that range; see if any ref remains. */
8965 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8967 rtx set
= single_set (i2
);
8969 /* Uses which just store in the pseudo don't count,
8970 since if they are the only uses, they are dead. */
8971 if (set
!= 0 && SET_DEST (set
) == reg
)
8973 if (LABEL_P (i2
) || JUMP_P (i2
))
8975 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8976 && reg_mentioned_p (reg
, PATTERN (i2
)))
8978 /* Some other ref remains; just delete the output reload we
8980 delete_address_reloads (output_reload_insn
, insn
);
8981 delete_insn (output_reload_insn
);
8986 /* Delete the now-dead stores into this pseudo. Note that this
8987 loop also takes care of deleting output_reload_insn. */
8988 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8990 rtx set
= single_set (i2
);
8992 if (set
!= 0 && SET_DEST (set
) == reg
)
8994 delete_address_reloads (i2
, insn
);
8997 if (LABEL_P (i2
) || JUMP_P (i2
))
9001 /* For the debugging info, say the pseudo lives in this reload reg. */
9002 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
9003 if (ira_conflicts_p
)
9004 /* Inform IRA about the change. */
9005 ira_mark_allocation_change (REGNO (reg
));
9006 alter_reg (REGNO (reg
), -1, false);
9010 delete_address_reloads (output_reload_insn
, insn
);
9011 delete_insn (output_reload_insn
);
9015 /* We are going to delete DEAD_INSN. Recursively delete loads of
9016 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9017 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
9019 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
9021 rtx set
= single_set (dead_insn
);
9022 rtx set2
, dst
, prev
, next
;
9025 rtx dst
= SET_DEST (set
);
9027 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
9029 /* If we deleted the store from a reloaded post_{in,de}c expression,
9030 we can delete the matching adds. */
9031 prev
= PREV_INSN (dead_insn
);
9032 next
= NEXT_INSN (dead_insn
);
9033 if (! prev
|| ! next
)
9035 set
= single_set (next
);
9036 set2
= single_set (prev
);
9038 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
9039 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
9040 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
9042 dst
= SET_DEST (set
);
9043 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9044 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9045 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9046 || (INTVAL (XEXP (SET_SRC (set
), 1))
9047 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9049 delete_related_insns (prev
);
9050 delete_related_insns (next
);
9053 /* Subfunction of delete_address_reloads: process registers found in X. */
9055 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
9057 rtx prev
, set
, dst
, i2
;
9059 enum rtx_code code
= GET_CODE (x
);
9063 const char *fmt
= GET_RTX_FORMAT (code
);
9064 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9067 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9068 else if (fmt
[i
] == 'E')
9070 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9071 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9078 if (spill_reg_order
[REGNO (x
)] < 0)
9081 /* Scan backwards for the insn that sets x. This might be a way back due
9083 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9085 code
= GET_CODE (prev
);
9086 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9090 if (reg_set_p (x
, PATTERN (prev
)))
9092 if (reg_referenced_p (x
, PATTERN (prev
)))
9095 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9097 /* Check that PREV only sets the reload register. */
9098 set
= single_set (prev
);
9101 dst
= SET_DEST (set
);
9103 || ! rtx_equal_p (dst
, x
))
9105 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9107 /* Check if DST was used in a later insn -
9108 it might have been inherited. */
9109 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9115 if (reg_referenced_p (dst
, PATTERN (i2
)))
9117 /* If there is a reference to the register in the current insn,
9118 it might be loaded in a non-inherited reload. If no other
9119 reload uses it, that means the register is set before
9121 if (i2
== current_insn
)
9123 for (j
= n_reloads
- 1; j
>= 0; j
--)
9124 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9125 || reload_override_in
[j
] == dst
)
9127 for (j
= n_reloads
- 1; j
>= 0; j
--)
9128 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9137 /* If DST is still live at CURRENT_INSN, check if it is used for
9138 any reload. Note that even if CURRENT_INSN sets DST, we still
9139 have to check the reloads. */
9140 if (i2
== current_insn
)
9142 for (j
= n_reloads
- 1; j
>= 0; j
--)
9143 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9144 || reload_override_in
[j
] == dst
)
9146 /* ??? We can't finish the loop here, because dst might be
9147 allocated to a pseudo in this block if no reload in this
9148 block needs any of the classes containing DST - see
9149 spill_hard_reg. There is no easy way to tell this, so we
9150 have to scan till the end of the basic block. */
9152 if (reg_set_p (dst
, PATTERN (i2
)))
9156 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9157 reg_reloaded_contents
[REGNO (dst
)] = -1;
9161 /* Output reload-insns to reload VALUE into RELOADREG.
9162 VALUE is an autoincrement or autodecrement RTX whose operand
9163 is a register or memory location;
9164 so reloading involves incrementing that location.
9165 IN is either identical to VALUE, or some cheaper place to reload from.
9167 INC_AMOUNT is the number to increment or decrement by (always positive).
9168 This cannot be deduced from VALUE. */
9171 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9173 /* REG or MEM to be copied and incremented. */
9174 rtx incloc
= find_replacement (&XEXP (value
, 0));
9175 /* Nonzero if increment after copying. */
9176 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9177 || GET_CODE (value
) == POST_MODIFY
);
9182 rtx real_in
= in
== value
? incloc
: in
;
9184 /* No hard register is equivalent to this register after
9185 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9186 we could inc/dec that register as well (maybe even using it for
9187 the source), but I'm not sure it's worth worrying about. */
9189 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9191 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9193 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9194 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9198 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9199 inc_amount
= -inc_amount
;
9201 inc
= GEN_INT (inc_amount
);
9204 /* If this is post-increment, first copy the location to the reload reg. */
9205 if (post
&& real_in
!= reloadreg
)
9206 emit_insn (gen_move_insn (reloadreg
, real_in
));
9210 /* See if we can directly increment INCLOC. Use a method similar to
9211 that in gen_reload. */
9213 last
= get_last_insn ();
9214 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9215 gen_rtx_PLUS (GET_MODE (incloc
),
9218 code
= recog_memoized (add_insn
);
9221 extract_insn (add_insn
);
9222 if (constrain_operands (1))
9224 /* If this is a pre-increment and we have incremented the value
9225 where it lives, copy the incremented value to RELOADREG to
9226 be used as an address. */
9229 emit_insn (gen_move_insn (reloadreg
, incloc
));
9233 delete_insns_since (last
);
9236 /* If couldn't do the increment directly, must increment in RELOADREG.
9237 The way we do this depends on whether this is pre- or post-increment.
9238 For pre-increment, copy INCLOC to the reload register, increment it
9239 there, then save back. */
9243 if (in
!= reloadreg
)
9244 emit_insn (gen_move_insn (reloadreg
, real_in
));
9245 emit_insn (gen_add2_insn (reloadreg
, inc
));
9246 emit_insn (gen_move_insn (incloc
, reloadreg
));
9251 Because this might be a jump insn or a compare, and because RELOADREG
9252 may not be available after the insn in an input reload, we must do
9253 the incrementation before the insn being reloaded for.
9255 We have already copied IN to RELOADREG. Increment the copy in
9256 RELOADREG, save that back, then decrement RELOADREG so it has
9257 the original value. */
9259 emit_insn (gen_add2_insn (reloadreg
, inc
));
9260 emit_insn (gen_move_insn (incloc
, reloadreg
));
9261 if (CONST_INT_P (inc
))
9262 emit_insn (gen_add2_insn (reloadreg
,
9263 gen_int_mode (-INTVAL (inc
),
9264 GET_MODE (reloadreg
))));
9266 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9272 add_auto_inc_notes (rtx insn
, rtx x
)
9274 enum rtx_code code
= GET_CODE (x
);
9278 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9280 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9284 /* Scan all the operand sub-expressions. */
9285 fmt
= GET_RTX_FORMAT (code
);
9286 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9289 add_auto_inc_notes (insn
, XEXP (x
, i
));
9290 else if (fmt
[i
] == 'E')
9291 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9292 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));