1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
89 #include "basic-block.h"
90 #include "insn-config.h"
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94 #include "insn-attr.h"
96 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
102 #include "tree-pass.h"
104 #include "valtrack.h"
107 #include "statistics.h"
109 #include "rtl-iter.h"
111 /* Number of attempts to combine instructions in this function. */
113 static int combine_attempts
;
115 /* Number of attempts that got as far as substitution in this function. */
117 static int combine_merges
;
119 /* Number of instructions combined with added SETs in this function. */
121 static int combine_extras
;
123 /* Number of instructions combined in this function. */
125 static int combine_successes
;
127 /* Totals over entire compilation. */
129 static int total_attempts
, total_merges
, total_extras
, total_successes
;
131 /* combine_instructions may try to replace the right hand side of the
132 second instruction with the value of an associated REG_EQUAL note
133 before throwing it at try_combine. That is problematic when there
134 is a REG_DEAD note for a register used in the old right hand side
135 and can cause distribute_notes to do wrong things. This is the
136 second instruction if it has been so modified, null otherwise. */
138 static rtx_insn
*i2mod
;
140 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 static rtx i2mod_old_rhs
;
144 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
146 static rtx i2mod_new_rhs
;
148 typedef struct reg_stat_struct
{
149 /* Record last point of death of (hard or pseudo) register n. */
150 rtx_insn
*last_death
;
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
205 int last_set_table_tick
;
207 /* Record the value of label_tick when the value for register n is placed in
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
217 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
218 char last_set_sign_bit_copies
;
219 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
225 char last_set_invalid
;
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
237 If an entry is zero, it means that we don't know anything special. */
239 unsigned char sign_bit_copies
;
241 unsigned HOST_WIDE_INT nonzero_bits
;
243 /* Record the value of the label_tick when the last truncation
244 happened. The field truncated_to_mode is only valid if
245 truncation_label == label_tick. */
247 int truncation_label
;
249 /* Record the last truncation seen for this register. If truncation
250 is not a nop to this mode we might be able to save an explicit
251 truncation if we know that value already contains a truncated
254 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
258 static vec
<reg_stat_type
> reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx_insn
*subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx_insn
*added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link
*next
;
320 static struct insn_link
**uid_log_links
;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack
;
332 /* Allocate a link. */
334 static inline struct insn_link
*
335 alloc_insn_link (rtx_insn
*insn
, struct insn_link
*next
)
338 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
339 sizeof (struct insn_link
));
345 /* Incremented for each basic block. */
347 static int label_tick
;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start
;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode
;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid
;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
376 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
377 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
390 rtx_insn
*other_insn
;
393 static struct undobuf undobuf
;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences
;
400 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
402 unsigned HOST_WIDE_INT
,
403 unsigned HOST_WIDE_INT
*);
404 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx
*, rtx
);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx_insn
*);
411 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
412 static int cant_combine_insn_p (rtx_insn
*);
413 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
414 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
415 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
416 static int contains_muldiv (rtx
);
417 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
419 static void undo_all (void);
420 static void undo_commit (void);
421 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
422 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
423 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
424 static rtx
simplify_if_then_else (rtx
);
425 static rtx
simplify_set (rtx
);
426 static rtx
simplify_logical (rtx
);
427 static rtx
expand_compound_operation (rtx
);
428 static const_rtx
expand_field_assignment (const_rtx
);
429 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
430 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
431 static rtx
extract_left_shift (rtx
, int);
432 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
433 unsigned HOST_WIDE_INT
*);
434 static rtx
canon_reg_for_combine (rtx
, rtx
);
435 static rtx
force_to_mode (rtx
, enum machine_mode
,
436 unsigned HOST_WIDE_INT
, int);
437 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
438 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
439 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
440 static rtx
make_field_assignment (rtx
);
441 static rtx
apply_distributive_law (rtx
);
442 static rtx
distribute_and_simplify_rtx (rtx
, int);
443 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
444 unsigned HOST_WIDE_INT
);
445 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
446 unsigned HOST_WIDE_INT
);
447 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
448 HOST_WIDE_INT
, enum machine_mode
, int *);
449 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
450 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
452 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
453 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
454 static enum rtx_code
simplify_compare_const (enum rtx_code
, enum machine_mode
,
456 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
457 static void update_table_tick (rtx
);
458 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
459 static void check_promoted_subreg (rtx_insn
*, rtx
);
460 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
461 static void record_dead_and_set_regs (rtx_insn
*);
462 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
463 static rtx
get_last_value (const_rtx
);
464 static int use_crosses_set_p (const_rtx
, int);
465 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
466 static int reg_dead_at_p (rtx
, rtx_insn
*);
467 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
468 static int reg_bitfield_target_p (rtx
, rtx
);
469 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
470 static void distribute_links (struct insn_link
*);
471 static void mark_used_regs_combine (rtx
);
472 static void record_promoted_value (rtx_insn
*, rtx
);
473 static bool unmentioned_reg_p (rtx
, rtx
);
474 static void record_truncated_values (rtx
*, void *);
475 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
476 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
497 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
500 /* Convenience wrapper for the canonicalize_comparison target hook.
501 Target hooks cannot use enum rtx_code. */
503 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
504 bool op0_preserve_value
)
506 int code_int
= (int)*code
;
507 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
508 *code
= (enum rtx_code
)code_int
;
511 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
512 PATTERN can not be split. Otherwise, it returns an insn sequence.
513 This is a wrapper around split_insns which ensures that the
514 reg_stat vector is made larger if the splitter creates a new
518 combine_split_insns (rtx pattern
, rtx insn
)
523 ret
= safe_as_a
<rtx_insn
*> (split_insns (pattern
, insn
));
524 nregs
= max_reg_num ();
525 if (nregs
> reg_stat
.length ())
526 reg_stat
.safe_grow_cleared (nregs
);
530 /* This is used by find_single_use to locate an rtx in LOC that
531 contains exactly one use of DEST, which is typically either a REG
532 or CC0. It returns a pointer to the innermost rtx expression
533 containing DEST. Appearances of DEST that are being used to
534 totally replace it are not counted. */
537 find_single_use_1 (rtx dest
, rtx
*loc
)
540 enum rtx_code code
= GET_CODE (x
);
556 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
557 of a REG that occupies all of the REG, the insn uses DEST if
558 it is mentioned in the destination or the source. Otherwise, we
559 need just check the source. */
560 if (GET_CODE (SET_DEST (x
)) != CC0
561 && GET_CODE (SET_DEST (x
)) != PC
562 && !REG_P (SET_DEST (x
))
563 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
564 && REG_P (SUBREG_REG (SET_DEST (x
)))
565 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
566 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
567 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
568 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
571 return find_single_use_1 (dest
, &SET_SRC (x
));
575 return find_single_use_1 (dest
, &XEXP (x
, 0));
581 /* If it wasn't one of the common cases above, check each expression and
582 vector of this code. Look for a unique usage of DEST. */
584 fmt
= GET_RTX_FORMAT (code
);
585 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
589 if (dest
== XEXP (x
, i
)
590 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
591 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
594 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
597 result
= this_result
;
598 else if (this_result
)
599 /* Duplicate usage. */
602 else if (fmt
[i
] == 'E')
606 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
608 if (XVECEXP (x
, i
, j
) == dest
610 && REG_P (XVECEXP (x
, i
, j
))
611 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
614 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
617 result
= this_result
;
618 else if (this_result
)
628 /* See if DEST, produced in INSN, is used only a single time in the
629 sequel. If so, return a pointer to the innermost rtx expression in which
632 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
634 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
635 care about REG_DEAD notes or LOG_LINKS.
637 Otherwise, we find the single use by finding an insn that has a
638 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
639 only referenced once in that insn, we know that it must be the first
640 and last insn referencing DEST. */
643 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
648 struct insn_link
*link
;
653 next
= NEXT_INSN (insn
);
655 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
658 result
= find_single_use_1 (dest
, &PATTERN (next
));
668 bb
= BLOCK_FOR_INSN (insn
);
669 for (next
= NEXT_INSN (insn
);
670 next
&& BLOCK_FOR_INSN (next
) == bb
;
671 next
= NEXT_INSN (next
))
672 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
674 FOR_EACH_LOG_LINK (link
, next
)
675 if (link
->insn
== insn
)
680 result
= find_single_use_1 (dest
, &PATTERN (next
));
690 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
691 insn. The substitution can be undone by undo_all. If INTO is already
692 set to NEWVAL, do not record this change. Because computing NEWVAL might
693 also call SUBST, we have to compute it before we put anything into
697 do_SUBST (rtx
*into
, rtx newval
)
702 if (oldval
== newval
)
705 /* We'd like to catch as many invalid transformations here as
706 possible. Unfortunately, there are way too many mode changes
707 that are perfectly valid, so we'd waste too much effort for
708 little gain doing the checks here. Focus on catching invalid
709 transformations involving integer constants. */
710 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
711 && CONST_INT_P (newval
))
713 /* Sanity check that we're replacing oldval with a CONST_INT
714 that is a valid sign-extension for the original mode. */
715 gcc_assert (INTVAL (newval
)
716 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
718 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
719 CONST_INT is not valid, because after the replacement, the
720 original mode would be gone. Unfortunately, we can't tell
721 when do_SUBST is called to replace the operand thereof, so we
722 perform this test on oldval instead, checking whether an
723 invalid replacement took place before we got here. */
724 gcc_assert (!(GET_CODE (oldval
) == SUBREG
725 && CONST_INT_P (SUBREG_REG (oldval
))));
726 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
727 && CONST_INT_P (XEXP (oldval
, 0))));
731 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
733 buf
= XNEW (struct undo
);
735 buf
->kind
= UNDO_RTX
;
737 buf
->old_contents
.r
= oldval
;
740 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
743 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
745 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
746 for the value of a HOST_WIDE_INT value (including CONST_INT) is
750 do_SUBST_INT (int *into
, int newval
)
755 if (oldval
== newval
)
759 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
761 buf
= XNEW (struct undo
);
763 buf
->kind
= UNDO_INT
;
765 buf
->old_contents
.i
= oldval
;
768 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
771 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
773 /* Similar to SUBST, but just substitute the mode. This is used when
774 changing the mode of a pseudo-register, so that any other
775 references to the entry in the regno_reg_rtx array will change as
779 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
782 enum machine_mode oldval
= GET_MODE (*into
);
784 if (oldval
== newval
)
788 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
790 buf
= XNEW (struct undo
);
792 buf
->kind
= UNDO_MODE
;
794 buf
->old_contents
.m
= oldval
;
795 adjust_reg_mode (*into
, newval
);
797 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
800 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
803 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
806 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
809 struct insn_link
* oldval
= *into
;
811 if (oldval
== newval
)
815 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
817 buf
= XNEW (struct undo
);
819 buf
->kind
= UNDO_LINKS
;
821 buf
->old_contents
.l
= oldval
;
824 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
827 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
830 /* Subroutine of try_combine. Determine whether the replacement patterns
831 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
832 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
833 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
834 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
835 of all the instructions can be estimated and the replacements are more
836 expensive than the original sequence. */
839 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
840 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
842 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
843 int new_i2_cost
, new_i3_cost
;
844 int old_cost
, new_cost
;
846 /* Lookup the original insn_rtx_costs. */
847 i2_cost
= INSN_COST (i2
);
848 i3_cost
= INSN_COST (i3
);
852 i1_cost
= INSN_COST (i1
);
855 i0_cost
= INSN_COST (i0
);
856 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
857 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
861 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
862 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
868 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
869 i1_cost
= i0_cost
= 0;
872 /* Calculate the replacement insn_rtx_costs. */
873 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
876 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
877 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
878 ? new_i2_cost
+ new_i3_cost
: 0;
882 new_cost
= new_i3_cost
;
886 if (undobuf
.other_insn
)
888 int old_other_cost
, new_other_cost
;
890 old_other_cost
= INSN_COST (undobuf
.other_insn
);
891 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
892 if (old_other_cost
> 0 && new_other_cost
> 0)
894 old_cost
+= old_other_cost
;
895 new_cost
+= new_other_cost
;
901 /* Disallow this combination if both new_cost and old_cost are greater than
902 zero, and new_cost is greater than old cost. */
903 if (old_cost
> 0 && new_cost
> old_cost
)
910 "rejecting combination of insns %d, %d, %d and %d\n",
911 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
913 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
914 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
919 "rejecting combination of insns %d, %d and %d\n",
920 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
921 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
922 i1_cost
, i2_cost
, i3_cost
, old_cost
);
927 "rejecting combination of insns %d and %d\n",
928 INSN_UID (i2
), INSN_UID (i3
));
929 fprintf (dump_file
, "original costs %d + %d = %d\n",
930 i2_cost
, i3_cost
, old_cost
);
935 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
936 new_i2_cost
, new_i3_cost
, new_cost
);
939 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
945 /* Update the uid_insn_cost array with the replacement costs. */
946 INSN_COST (i2
) = new_i2_cost
;
947 INSN_COST (i3
) = new_i3_cost
;
959 /* Delete any insns that copy a register to itself. */
962 delete_noop_moves (void)
964 rtx_insn
*insn
, *next
;
967 FOR_EACH_BB_FN (bb
, cfun
)
969 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
971 next
= NEXT_INSN (insn
);
972 if (INSN_P (insn
) && noop_move_p (insn
))
975 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
977 delete_insn_and_edges (insn
);
984 /* Fill in log links field for all insns. */
987 create_log_links (void)
994 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
996 /* Pass through each block from the end, recording the uses of each
997 register and establishing log links when def is encountered.
998 Note that we do not clear next_use array in order to save time,
999 so we have to test whether the use is in the same basic block as def.
1001 There are a few cases below when we do not consider the definition or
1002 usage -- these are taken from original flow.c did. Don't ask me why it is
1003 done this way; I don't know and if it works, I don't want to know. */
1005 FOR_EACH_BB_FN (bb
, cfun
)
1007 FOR_BB_INSNS_REVERSE (bb
, insn
)
1009 if (!NONDEBUG_INSN_P (insn
))
1012 /* Log links are created only once. */
1013 gcc_assert (!LOG_LINKS (insn
));
1015 FOR_EACH_INSN_DEF (def
, insn
)
1017 int regno
= DF_REF_REGNO (def
);
1020 if (!next_use
[regno
])
1023 /* Do not consider if it is pre/post modification in MEM. */
1024 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1027 /* Do not make the log link for frame pointer. */
1028 if ((regno
== FRAME_POINTER_REGNUM
1029 && (! reload_completed
|| frame_pointer_needed
))
1030 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1031 || (regno
== HARD_FRAME_POINTER_REGNUM
1032 && (! reload_completed
|| frame_pointer_needed
))
1034 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1035 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1040 use_insn
= next_use
[regno
];
1041 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1045 We don't build a LOG_LINK for hard registers contained
1046 in ASM_OPERANDs. If these registers get replaced,
1047 we might wind up changing the semantics of the insn,
1048 even if reload can make what appear to be valid
1049 assignments later. */
1050 if (regno
>= FIRST_PSEUDO_REGISTER
1051 || asm_noperands (PATTERN (use_insn
)) < 0)
1053 /* Don't add duplicate links between instructions. */
1054 struct insn_link
*links
;
1055 FOR_EACH_LOG_LINK (links
, use_insn
)
1056 if (insn
== links
->insn
)
1060 LOG_LINKS (use_insn
)
1061 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1064 next_use
[regno
] = NULL
;
1067 FOR_EACH_INSN_USE (use
, insn
)
1069 int regno
= DF_REF_REGNO (use
);
1071 /* Do not consider the usage of the stack pointer
1072 by function call. */
1073 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1076 next_use
[regno
] = insn
;
1084 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1085 true if we found a LOG_LINK that proves that A feeds B. This only works
1086 if there are no instructions between A and B which could have a link
1087 depending on A, since in that case we would not record a link for B.
1088 We also check the implicit dependency created by a cc0 setter/user
1092 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1094 struct insn_link
*links
;
1095 FOR_EACH_LOG_LINK (links
, b
)
1096 if (links
->insn
== a
)
1105 /* Main entry point for combiner. F is the first insn of the function.
1106 NREGS is the first unused pseudo-reg number.
1108 Return nonzero if the combiner has turned an indirect jump
1109 instruction into a direct jump. */
1111 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1113 rtx_insn
*insn
, *next
;
1117 struct insn_link
*links
, *nextlinks
;
1119 basic_block last_bb
;
1121 int new_direct_jump_p
= 0;
1123 for (first
= f
; first
&& !INSN_P (first
); )
1124 first
= NEXT_INSN (first
);
1128 combine_attempts
= 0;
1131 combine_successes
= 0;
1133 rtl_hooks
= combine_rtl_hooks
;
1135 reg_stat
.safe_grow_cleared (nregs
);
1137 init_recog_no_volatile ();
1139 /* Allocate array for insn info. */
1140 max_uid_known
= get_max_uid ();
1141 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1142 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1143 gcc_obstack_init (&insn_link_obstack
);
1145 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1147 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1148 problems when, for example, we have j <<= 1 in a loop. */
1150 nonzero_sign_valid
= 0;
1151 label_tick
= label_tick_ebb_start
= 1;
1153 /* Scan all SETs and see if we can deduce anything about what
1154 bits are known to be zero for some registers and how many copies
1155 of the sign bit are known to exist for those registers.
1157 Also set any known values so that we can use it while searching
1158 for what bits are known to be set. */
1160 setup_incoming_promotions (first
);
1161 /* Allow the entry block and the first block to fall into the same EBB.
1162 Conceptually the incoming promotions are assigned to the entry block. */
1163 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1165 create_log_links ();
1166 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1168 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1173 if (!single_pred_p (this_basic_block
)
1174 || single_pred (this_basic_block
) != last_bb
)
1175 label_tick_ebb_start
= label_tick
;
1176 last_bb
= this_basic_block
;
1178 FOR_BB_INSNS (this_basic_block
, insn
)
1179 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1185 subst_low_luid
= DF_INSN_LUID (insn
);
1188 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1190 record_dead_and_set_regs (insn
);
1193 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1194 if (REG_NOTE_KIND (links
) == REG_INC
)
1195 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1199 /* Record the current insn_rtx_cost of this instruction. */
1200 if (NONJUMP_INSN_P (insn
))
1201 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1202 optimize_this_for_speed_p
);
1204 fprintf (dump_file
, "insn_cost %d: %d\n",
1205 INSN_UID (insn
), INSN_COST (insn
));
1209 nonzero_sign_valid
= 1;
1211 /* Now scan all the insns in forward order. */
1212 label_tick
= label_tick_ebb_start
= 1;
1214 setup_incoming_promotions (first
);
1215 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1216 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1218 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1220 rtx_insn
*last_combined_insn
= NULL
;
1221 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1226 if (!single_pred_p (this_basic_block
)
1227 || single_pred (this_basic_block
) != last_bb
)
1228 label_tick_ebb_start
= label_tick
;
1229 last_bb
= this_basic_block
;
1231 rtl_profile_for_bb (this_basic_block
);
1232 for (insn
= BB_HEAD (this_basic_block
);
1233 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1234 insn
= next
? next
: NEXT_INSN (insn
))
1237 if (!NONDEBUG_INSN_P (insn
))
1240 while (last_combined_insn
1241 && last_combined_insn
->deleted ())
1242 last_combined_insn
= PREV_INSN (last_combined_insn
);
1243 if (last_combined_insn
== NULL_RTX
1244 || BARRIER_P (last_combined_insn
)
1245 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1246 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1247 last_combined_insn
= insn
;
1249 /* See if we know about function return values before this
1250 insn based upon SUBREG flags. */
1251 check_promoted_subreg (insn
, PATTERN (insn
));
1253 /* See if we can find hardregs and subreg of pseudos in
1254 narrower modes. This could help turning TRUNCATEs
1256 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1258 /* Try this insn with each insn it links back to. */
1260 FOR_EACH_LOG_LINK (links
, insn
)
1261 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1262 NULL
, &new_direct_jump_p
,
1263 last_combined_insn
)) != 0)
1265 statistics_counter_event (cfun
, "two-insn combine", 1);
1269 /* Try each sequence of three linked insns ending with this one. */
1271 if (max_combine
>= 3)
1272 FOR_EACH_LOG_LINK (links
, insn
)
1274 rtx_insn
*link
= links
->insn
;
1276 /* If the linked insn has been replaced by a note, then there
1277 is no point in pursuing this chain any further. */
1281 FOR_EACH_LOG_LINK (nextlinks
, link
)
1282 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1283 NULL
, &new_direct_jump_p
,
1284 last_combined_insn
)) != 0)
1286 statistics_counter_event (cfun
, "three-insn combine", 1);
1292 /* Try to combine a jump insn that uses CC0
1293 with a preceding insn that sets CC0, and maybe with its
1294 logical predecessor as well.
1295 This is how we make decrement-and-branch insns.
1296 We need this special code because data flow connections
1297 via CC0 do not get entered in LOG_LINKS. */
1300 && (prev
= prev_nonnote_insn (insn
)) != 0
1301 && NONJUMP_INSN_P (prev
)
1302 && sets_cc0_p (PATTERN (prev
)))
1304 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1306 last_combined_insn
)) != 0)
1309 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1310 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1311 NULL
, &new_direct_jump_p
,
1312 last_combined_insn
)) != 0)
1316 /* Do the same for an insn that explicitly references CC0. */
1317 if (NONJUMP_INSN_P (insn
)
1318 && (prev
= prev_nonnote_insn (insn
)) != 0
1319 && NONJUMP_INSN_P (prev
)
1320 && sets_cc0_p (PATTERN (prev
))
1321 && GET_CODE (PATTERN (insn
)) == SET
1322 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1324 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1326 last_combined_insn
)) != 0)
1329 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1330 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1331 NULL
, &new_direct_jump_p
,
1332 last_combined_insn
)) != 0)
1336 /* Finally, see if any of the insns that this insn links to
1337 explicitly references CC0. If so, try this insn, that insn,
1338 and its predecessor if it sets CC0. */
1339 FOR_EACH_LOG_LINK (links
, insn
)
1340 if (NONJUMP_INSN_P (links
->insn
)
1341 && GET_CODE (PATTERN (links
->insn
)) == SET
1342 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1343 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1344 && NONJUMP_INSN_P (prev
)
1345 && sets_cc0_p (PATTERN (prev
))
1346 && (next
= try_combine (insn
, links
->insn
,
1347 prev
, NULL
, &new_direct_jump_p
,
1348 last_combined_insn
)) != 0)
1352 /* Try combining an insn with two different insns whose results it
1354 if (max_combine
>= 3)
1355 FOR_EACH_LOG_LINK (links
, insn
)
1356 for (nextlinks
= links
->next
; nextlinks
;
1357 nextlinks
= nextlinks
->next
)
1358 if ((next
= try_combine (insn
, links
->insn
,
1359 nextlinks
->insn
, NULL
,
1361 last_combined_insn
)) != 0)
1364 statistics_counter_event (cfun
, "three-insn combine", 1);
1368 /* Try four-instruction combinations. */
1369 if (max_combine
>= 4)
1370 FOR_EACH_LOG_LINK (links
, insn
)
1372 struct insn_link
*next1
;
1373 rtx_insn
*link
= links
->insn
;
1375 /* If the linked insn has been replaced by a note, then there
1376 is no point in pursuing this chain any further. */
1380 FOR_EACH_LOG_LINK (next1
, link
)
1382 rtx_insn
*link1
= next1
->insn
;
1385 /* I0 -> I1 -> I2 -> I3. */
1386 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1387 if ((next
= try_combine (insn
, link
, link1
,
1390 last_combined_insn
)) != 0)
1392 statistics_counter_event (cfun
, "four-insn combine", 1);
1395 /* I0, I1 -> I2, I2 -> I3. */
1396 for (nextlinks
= next1
->next
; nextlinks
;
1397 nextlinks
= nextlinks
->next
)
1398 if ((next
= try_combine (insn
, link
, link1
,
1401 last_combined_insn
)) != 0)
1403 statistics_counter_event (cfun
, "four-insn combine", 1);
1408 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1410 rtx_insn
*link1
= next1
->insn
;
1413 /* I0 -> I2; I1, I2 -> I3. */
1414 FOR_EACH_LOG_LINK (nextlinks
, link
)
1415 if ((next
= try_combine (insn
, link
, link1
,
1418 last_combined_insn
)) != 0)
1420 statistics_counter_event (cfun
, "four-insn combine", 1);
1423 /* I0 -> I1; I1, I2 -> I3. */
1424 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1425 if ((next
= try_combine (insn
, link
, link1
,
1428 last_combined_insn
)) != 0)
1430 statistics_counter_event (cfun
, "four-insn combine", 1);
1436 /* Try this insn with each REG_EQUAL note it links back to. */
1437 FOR_EACH_LOG_LINK (links
, insn
)
1440 rtx_insn
*temp
= links
->insn
;
1441 if ((set
= single_set (temp
)) != 0
1442 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1443 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1444 /* Avoid using a register that may already been marked
1445 dead by an earlier instruction. */
1446 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1447 && (GET_MODE (note
) == VOIDmode
1448 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1449 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1451 /* Temporarily replace the set's source with the
1452 contents of the REG_EQUAL note. The insn will
1453 be deleted or recognized by try_combine. */
1454 rtx orig
= SET_SRC (set
);
1455 SET_SRC (set
) = note
;
1457 i2mod_old_rhs
= copy_rtx (orig
);
1458 i2mod_new_rhs
= copy_rtx (note
);
1459 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1461 last_combined_insn
);
1465 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1468 SET_SRC (set
) = orig
;
1473 record_dead_and_set_regs (insn
);
1480 default_rtl_profile ();
1482 new_direct_jump_p
|= purge_all_dead_edges ();
1483 delete_noop_moves ();
1486 obstack_free (&insn_link_obstack
, NULL
);
1487 free (uid_log_links
);
1488 free (uid_insn_cost
);
1489 reg_stat
.release ();
1492 struct undo
*undo
, *next
;
1493 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1501 total_attempts
+= combine_attempts
;
1502 total_merges
+= combine_merges
;
1503 total_extras
+= combine_extras
;
1504 total_successes
+= combine_successes
;
1506 nonzero_sign_valid
= 0;
1507 rtl_hooks
= general_rtl_hooks
;
1509 /* Make recognizer allow volatile MEMs again. */
1512 return new_direct_jump_p
;
1515 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1518 init_reg_last (void)
1523 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1524 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1527 /* Set up any promoted values for incoming argument registers. */
1530 setup_incoming_promotions (rtx_insn
*first
)
1533 bool strictly_local
= false;
1535 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1536 arg
= DECL_CHAIN (arg
))
1538 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1540 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1542 /* Only continue if the incoming argument is in a register. */
1546 /* Determine, if possible, whether all call sites of the current
1547 function lie within the current compilation unit. (This does
1548 take into account the exporting of a function via taking its
1549 address, and so forth.) */
1550 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1552 /* The mode and signedness of the argument before any promotions happen
1553 (equal to the mode of the pseudo holding it at that stage). */
1554 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1555 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1557 /* The mode and signedness of the argument after any source language and
1558 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1559 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1560 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1562 /* The mode and signedness of the argument as it is actually passed,
1563 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1564 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1565 TREE_TYPE (cfun
->decl
), 0);
1567 /* The mode of the register in which the argument is being passed. */
1568 mode4
= GET_MODE (reg
);
1570 /* Eliminate sign extensions in the callee when:
1571 (a) A mode promotion has occurred; */
1574 /* (b) The mode of the register is the same as the mode of
1575 the argument as it is passed; */
1578 /* (c) There's no language level extension; */
1581 /* (c.1) All callers are from the current compilation unit. If that's
1582 the case we don't have to rely on an ABI, we only have to know
1583 what we're generating right now, and we know that we will do the
1584 mode1 to mode2 promotion with the given sign. */
1585 else if (!strictly_local
)
1587 /* (c.2) The combination of the two promotions is useful. This is
1588 true when the signs match, or if the first promotion is unsigned.
1589 In the later case, (sign_extend (zero_extend x)) is the same as
1590 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1596 /* Record that the value was promoted from mode1 to mode3,
1597 so that any sign extension at the head of the current
1598 function may be eliminated. */
1599 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1600 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1601 record_value_for_reg (reg
, first
, x
);
1605 /* Called via note_stores. If X is a pseudo that is narrower than
1606 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1608 If we are setting only a portion of X and we can't figure out what
1609 portion, assume all bits will be used since we don't know what will
1612 Similarly, set how many bits of X are known to be copies of the sign bit
1613 at all locations in the function. This is the smallest number implied
1617 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1619 rtx_insn
*insn
= (rtx_insn
*) data
;
1623 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1624 /* If this register is undefined at the start of the file, we can't
1625 say what its contents were. */
1626 && ! REGNO_REG_SET_P
1627 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1628 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1630 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1632 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1634 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1635 rsp
->sign_bit_copies
= 1;
1639 /* If this register is being initialized using itself, and the
1640 register is uninitialized in this basic block, and there are
1641 no LOG_LINKS which set the register, then part of the
1642 register is uninitialized. In that case we can't assume
1643 anything about the number of nonzero bits.
1645 ??? We could do better if we checked this in
1646 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1647 could avoid making assumptions about the insn which initially
1648 sets the register, while still using the information in other
1649 insns. We would have to be careful to check every insn
1650 involved in the combination. */
1653 && reg_referenced_p (x
, PATTERN (insn
))
1654 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1657 struct insn_link
*link
;
1659 FOR_EACH_LOG_LINK (link
, insn
)
1660 if (dead_or_set_p (link
->insn
, x
))
1664 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1665 rsp
->sign_bit_copies
= 1;
1670 /* If this is a complex assignment, see if we can convert it into a
1671 simple assignment. */
1672 set
= expand_field_assignment (set
);
1674 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1675 set what we know about X. */
1677 if (SET_DEST (set
) == x
1678 || (paradoxical_subreg_p (SET_DEST (set
))
1679 && SUBREG_REG (SET_DEST (set
)) == x
))
1681 rtx src
= SET_SRC (set
);
1683 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1684 /* If X is narrower than a word and SRC is a non-negative
1685 constant that would appear negative in the mode of X,
1686 sign-extend it for use in reg_stat[].nonzero_bits because some
1687 machines (maybe most) will actually do the sign-extension
1688 and this is the conservative approach.
1690 ??? For 2.5, try to tighten up the MD files in this regard
1691 instead of this kludge. */
1693 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1694 && CONST_INT_P (src
)
1696 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1697 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1700 /* Don't call nonzero_bits if it cannot change anything. */
1701 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1702 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1703 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1704 if (rsp
->sign_bit_copies
== 0
1705 || rsp
->sign_bit_copies
> num
)
1706 rsp
->sign_bit_copies
= num
;
1710 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1711 rsp
->sign_bit_copies
= 1;
1716 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1717 optionally insns that were previously combined into I3 or that will be
1718 combined into the merger of INSN and I3. The order is PRED, PRED2,
1719 INSN, SUCC, SUCC2, I3.
1721 Return 0 if the combination is not allowed for any reason.
1723 If the combination is allowed, *PDEST will be set to the single
1724 destination of INSN and *PSRC to the single source, and this function
1728 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1729 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1730 rtx
*pdest
, rtx
*psrc
)
1739 bool all_adjacent
= true;
1740 int (*is_volatile_p
) (const_rtx
);
1746 if (next_active_insn (succ2
) != i3
)
1747 all_adjacent
= false;
1748 if (next_active_insn (succ
) != succ2
)
1749 all_adjacent
= false;
1751 else if (next_active_insn (succ
) != i3
)
1752 all_adjacent
= false;
1753 if (next_active_insn (insn
) != succ
)
1754 all_adjacent
= false;
1756 else if (next_active_insn (insn
) != i3
)
1757 all_adjacent
= false;
1759 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1760 or a PARALLEL consisting of such a SET and CLOBBERs.
1762 If INSN has CLOBBER parallel parts, ignore them for our processing.
1763 By definition, these happen during the execution of the insn. When it
1764 is merged with another insn, all bets are off. If they are, in fact,
1765 needed and aren't also supplied in I3, they may be added by
1766 recog_for_combine. Otherwise, it won't match.
1768 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1771 Get the source and destination of INSN. If more than one, can't
1774 if (GET_CODE (PATTERN (insn
)) == SET
)
1775 set
= PATTERN (insn
);
1776 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1777 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1779 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1781 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1783 switch (GET_CODE (elt
))
1785 /* This is important to combine floating point insns
1786 for the SH4 port. */
1788 /* Combining an isolated USE doesn't make sense.
1789 We depend here on combinable_i3pat to reject them. */
1790 /* The code below this loop only verifies that the inputs of
1791 the SET in INSN do not change. We call reg_set_between_p
1792 to verify that the REG in the USE does not change between
1794 If the USE in INSN was for a pseudo register, the matching
1795 insn pattern will likely match any register; combining this
1796 with any other USE would only be safe if we knew that the
1797 used registers have identical values, or if there was
1798 something to tell them apart, e.g. different modes. For
1799 now, we forgo such complicated tests and simply disallow
1800 combining of USES of pseudo registers with any other USE. */
1801 if (REG_P (XEXP (elt
, 0))
1802 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1804 rtx i3pat
= PATTERN (i3
);
1805 int i
= XVECLEN (i3pat
, 0) - 1;
1806 unsigned int regno
= REGNO (XEXP (elt
, 0));
1810 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1812 if (GET_CODE (i3elt
) == USE
1813 && REG_P (XEXP (i3elt
, 0))
1814 && (REGNO (XEXP (i3elt
, 0)) == regno
1815 ? reg_set_between_p (XEXP (elt
, 0),
1816 PREV_INSN (insn
), i3
)
1817 : regno
>= FIRST_PSEUDO_REGISTER
))
1824 /* We can ignore CLOBBERs. */
1829 /* Ignore SETs whose result isn't used but not those that
1830 have side-effects. */
1831 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1832 && insn_nothrow_p (insn
)
1833 && !side_effects_p (elt
))
1836 /* If we have already found a SET, this is a second one and
1837 so we cannot combine with this insn. */
1845 /* Anything else means we can't combine. */
1851 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1852 so don't do anything with it. */
1853 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1862 /* The simplification in expand_field_assignment may call back to
1863 get_last_value, so set safe guard here. */
1864 subst_low_luid
= DF_INSN_LUID (insn
);
1866 set
= expand_field_assignment (set
);
1867 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1869 /* Don't eliminate a store in the stack pointer. */
1870 if (dest
== stack_pointer_rtx
1871 /* Don't combine with an insn that sets a register to itself if it has
1872 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1873 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1874 /* Can't merge an ASM_OPERANDS. */
1875 || GET_CODE (src
) == ASM_OPERANDS
1876 /* Can't merge a function call. */
1877 || GET_CODE (src
) == CALL
1878 /* Don't eliminate a function call argument. */
1880 && (find_reg_fusage (i3
, USE
, dest
)
1882 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1883 && global_regs
[REGNO (dest
)])))
1884 /* Don't substitute into an incremented register. */
1885 || FIND_REG_INC_NOTE (i3
, dest
)
1886 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1887 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1888 /* Don't substitute into a non-local goto, this confuses CFG. */
1889 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1890 /* Make sure that DEST is not used after SUCC but before I3. */
1893 && (reg_used_between_p (dest
, succ2
, i3
)
1894 || reg_used_between_p (dest
, succ
, succ2
)))
1895 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1896 /* Make sure that the value that is to be substituted for the register
1897 does not use any registers whose values alter in between. However,
1898 If the insns are adjacent, a use can't cross a set even though we
1899 think it might (this can happen for a sequence of insns each setting
1900 the same destination; last_set of that register might point to
1901 a NOTE). If INSN has a REG_EQUIV note, the register is always
1902 equivalent to the memory so the substitution is valid even if there
1903 are intervening stores. Also, don't move a volatile asm or
1904 UNSPEC_VOLATILE across any other insns. */
1907 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1908 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1909 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1910 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1911 /* Don't combine across a CALL_INSN, because that would possibly
1912 change whether the life span of some REGs crosses calls or not,
1913 and it is a pain to update that information.
1914 Exception: if source is a constant, moving it later can't hurt.
1915 Accept that as a special case. */
1916 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1919 /* DEST must either be a REG or CC0. */
1922 /* If register alignment is being enforced for multi-word items in all
1923 cases except for parameters, it is possible to have a register copy
1924 insn referencing a hard register that is not allowed to contain the
1925 mode being copied and which would not be valid as an operand of most
1926 insns. Eliminate this problem by not combining with such an insn.
1928 Also, on some machines we don't want to extend the life of a hard
1932 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1933 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1934 /* Don't extend the life of a hard register unless it is
1935 user variable (if we have few registers) or it can't
1936 fit into the desired register (meaning something special
1938 Also avoid substituting a return register into I3, because
1939 reload can't handle a conflict with constraints of other
1941 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1942 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1945 else if (GET_CODE (dest
) != CC0
)
1949 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1950 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1951 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1953 /* Don't substitute for a register intended as a clobberable
1955 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1956 if (rtx_equal_p (reg
, dest
))
1959 /* If the clobber represents an earlyclobber operand, we must not
1960 substitute an expression containing the clobbered register.
1961 As we do not analyze the constraint strings here, we have to
1962 make the conservative assumption. However, if the register is
1963 a fixed hard reg, the clobber cannot represent any operand;
1964 we leave it up to the machine description to either accept or
1965 reject use-and-clobber patterns. */
1967 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1968 || !fixed_regs
[REGNO (reg
)])
1969 if (reg_overlap_mentioned_p (reg
, src
))
1973 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1974 or not), reject, unless nothing volatile comes between it and I3 */
1976 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1978 /* Make sure neither succ nor succ2 contains a volatile reference. */
1979 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1981 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1983 /* We'll check insns between INSN and I3 below. */
1986 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1987 to be an explicit register variable, and was chosen for a reason. */
1989 if (GET_CODE (src
) == ASM_OPERANDS
1990 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1993 /* If INSN contains volatile references (specifically volatile MEMs),
1994 we cannot combine across any other volatile references.
1995 Even if INSN doesn't contain volatile references, any intervening
1996 volatile insn might affect machine state. */
1998 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2002 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2003 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2006 /* If INSN contains an autoincrement or autodecrement, make sure that
2007 register is not used between there and I3, and not already used in
2008 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2009 Also insist that I3 not be a jump; if it were one
2010 and the incremented register were spilled, we would lose. */
2013 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2014 if (REG_NOTE_KIND (link
) == REG_INC
2016 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2017 || (pred
!= NULL_RTX
2018 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2019 || (pred2
!= NULL_RTX
2020 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2021 || (succ
!= NULL_RTX
2022 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2023 || (succ2
!= NULL_RTX
2024 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2025 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2030 /* Don't combine an insn that follows a CC0-setting insn.
2031 An insn that uses CC0 must not be separated from the one that sets it.
2032 We do, however, allow I2 to follow a CC0-setting insn if that insn
2033 is passed as I1; in that case it will be deleted also.
2034 We also allow combining in this case if all the insns are adjacent
2035 because that would leave the two CC0 insns adjacent as well.
2036 It would be more logical to test whether CC0 occurs inside I1 or I2,
2037 but that would be much slower, and this ought to be equivalent. */
2039 p
= prev_nonnote_insn (insn
);
2040 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2045 /* If we get here, we have passed all the tests and the combination is
2054 /* LOC is the location within I3 that contains its pattern or the component
2055 of a PARALLEL of the pattern. We validate that it is valid for combining.
2057 One problem is if I3 modifies its output, as opposed to replacing it
2058 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2059 doing so would produce an insn that is not equivalent to the original insns.
2063 (set (reg:DI 101) (reg:DI 100))
2064 (set (subreg:SI (reg:DI 101) 0) <foo>)
2066 This is NOT equivalent to:
2068 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2069 (set (reg:DI 101) (reg:DI 100))])
2071 Not only does this modify 100 (in which case it might still be valid
2072 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2074 We can also run into a problem if I2 sets a register that I1
2075 uses and I1 gets directly substituted into I3 (not via I2). In that
2076 case, we would be getting the wrong value of I2DEST into I3, so we
2077 must reject the combination. This case occurs when I2 and I1 both
2078 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2079 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2080 of a SET must prevent combination from occurring. The same situation
2081 can occur for I0, in which case I0_NOT_IN_SRC is set.
2083 Before doing the above check, we first try to expand a field assignment
2084 into a set of logical operations.
2086 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2087 we place a register that is both set and used within I3. If more than one
2088 such register is detected, we fail.
2090 Return 1 if the combination is valid, zero otherwise. */
2093 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2094 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2098 if (GET_CODE (x
) == SET
)
2101 rtx dest
= SET_DEST (set
);
2102 rtx src
= SET_SRC (set
);
2103 rtx inner_dest
= dest
;
2106 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2107 || GET_CODE (inner_dest
) == SUBREG
2108 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2109 inner_dest
= XEXP (inner_dest
, 0);
2111 /* Check for the case where I3 modifies its output, as discussed
2112 above. We don't want to prevent pseudos from being combined
2113 into the address of a MEM, so only prevent the combination if
2114 i1 or i2 set the same MEM. */
2115 if ((inner_dest
!= dest
&&
2116 (!MEM_P (inner_dest
)
2117 || rtx_equal_p (i2dest
, inner_dest
)
2118 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2119 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2120 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2121 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2122 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2124 /* This is the same test done in can_combine_p except we can't test
2125 all_adjacent; we don't have to, since this instruction will stay
2126 in place, thus we are not considering increasing the lifetime of
2129 Also, if this insn sets a function argument, combining it with
2130 something that might need a spill could clobber a previous
2131 function argument; the all_adjacent test in can_combine_p also
2132 checks this; here, we do a more specific test for this case. */
2134 || (REG_P (inner_dest
)
2135 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2136 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2137 GET_MODE (inner_dest
))))
2138 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2139 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2142 /* If DEST is used in I3, it is being killed in this insn, so
2143 record that for later. We have to consider paradoxical
2144 subregs here, since they kill the whole register, but we
2145 ignore partial subregs, STRICT_LOW_PART, etc.
2146 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2147 STACK_POINTER_REGNUM, since these are always considered to be
2148 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2150 if (GET_CODE (subdest
) == SUBREG
2151 && (GET_MODE_SIZE (GET_MODE (subdest
))
2152 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2153 subdest
= SUBREG_REG (subdest
);
2156 && reg_referenced_p (subdest
, PATTERN (i3
))
2157 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2158 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2159 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2161 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2162 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2163 || ! fixed_regs
[REGNO (subdest
)])
2165 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2167 if (*pi3dest_killed
)
2170 *pi3dest_killed
= subdest
;
2174 else if (GET_CODE (x
) == PARALLEL
)
2178 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2179 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2180 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2187 /* Return 1 if X is an arithmetic expression that contains a multiplication
2188 and division. We don't count multiplications by powers of two here. */
2191 contains_muldiv (rtx x
)
2193 switch (GET_CODE (x
))
2195 case MOD
: case DIV
: case UMOD
: case UDIV
:
2199 return ! (CONST_INT_P (XEXP (x
, 1))
2200 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2203 return contains_muldiv (XEXP (x
, 0))
2204 || contains_muldiv (XEXP (x
, 1));
2207 return contains_muldiv (XEXP (x
, 0));
2213 /* Determine whether INSN can be used in a combination. Return nonzero if
2214 not. This is used in try_combine to detect early some cases where we
2215 can't perform combinations. */
2218 cant_combine_insn_p (rtx_insn
*insn
)
2223 /* If this isn't really an insn, we can't do anything.
2224 This can occur when flow deletes an insn that it has merged into an
2225 auto-increment address. */
2226 if (! INSN_P (insn
))
2229 /* Never combine loads and stores involving hard regs that are likely
2230 to be spilled. The register allocator can usually handle such
2231 reg-reg moves by tying. If we allow the combiner to make
2232 substitutions of likely-spilled regs, reload might die.
2233 As an exception, we allow combinations involving fixed regs; these are
2234 not available to the register allocator so there's no risk involved. */
2236 set
= single_set (insn
);
2239 src
= SET_SRC (set
);
2240 dest
= SET_DEST (set
);
2241 if (GET_CODE (src
) == SUBREG
)
2242 src
= SUBREG_REG (src
);
2243 if (GET_CODE (dest
) == SUBREG
)
2244 dest
= SUBREG_REG (dest
);
2245 if (REG_P (src
) && REG_P (dest
)
2246 && ((HARD_REGISTER_P (src
)
2247 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2248 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2249 || (HARD_REGISTER_P (dest
)
2250 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2251 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2257 struct likely_spilled_retval_info
2259 unsigned regno
, nregs
;
2263 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2264 hard registers that are known to be written to / clobbered in full. */
2266 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2268 struct likely_spilled_retval_info
*const info
=
2269 (struct likely_spilled_retval_info
*) data
;
2270 unsigned regno
, nregs
;
2273 if (!REG_P (XEXP (set
, 0)))
2276 if (regno
>= info
->regno
+ info
->nregs
)
2278 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2279 if (regno
+ nregs
<= info
->regno
)
2281 new_mask
= (2U << (nregs
- 1)) - 1;
2282 if (regno
< info
->regno
)
2283 new_mask
>>= info
->regno
- regno
;
2285 new_mask
<<= regno
- info
->regno
;
2286 info
->mask
&= ~new_mask
;
2289 /* Return nonzero iff part of the return value is live during INSN, and
2290 it is likely spilled. This can happen when more than one insn is needed
2291 to copy the return value, e.g. when we consider to combine into the
2292 second copy insn for a complex value. */
2295 likely_spilled_retval_p (rtx_insn
*insn
)
2297 rtx_insn
*use
= BB_END (this_basic_block
);
2300 unsigned regno
, nregs
;
2301 /* We assume here that no machine mode needs more than
2302 32 hard registers when the value overlaps with a register
2303 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2305 struct likely_spilled_retval_info info
;
2307 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2309 reg
= XEXP (PATTERN (use
), 0);
2310 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2312 regno
= REGNO (reg
);
2313 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2316 mask
= (2U << (nregs
- 1)) - 1;
2318 /* Disregard parts of the return value that are set later. */
2322 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2324 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2327 /* Check if any of the (probably) live return value registers is
2332 if ((mask
& 1 << nregs
)
2333 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2339 /* Adjust INSN after we made a change to its destination.
2341 Changing the destination can invalidate notes that say something about
2342 the results of the insn and a LOG_LINK pointing to the insn. */
2345 adjust_for_new_dest (rtx_insn
*insn
)
2347 /* For notes, be conservative and simply remove them. */
2348 remove_reg_equal_equiv_notes (insn
);
2350 /* The new insn will have a destination that was previously the destination
2351 of an insn just above it. Call distribute_links to make a LOG_LINK from
2352 the next use of that destination. */
2353 distribute_links (alloc_insn_link (insn
, NULL
));
2355 df_insn_rescan (insn
);
2358 /* Return TRUE if combine can reuse reg X in mode MODE.
2359 ADDED_SETS is nonzero if the original set is still required. */
2361 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2369 /* Allow hard registers if the new mode is legal, and occupies no more
2370 registers than the old mode. */
2371 if (regno
< FIRST_PSEUDO_REGISTER
)
2372 return (HARD_REGNO_MODE_OK (regno
, mode
)
2373 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2374 >= hard_regno_nregs
[regno
][mode
]));
2376 /* Or a pseudo that is only used once. */
2377 return (REG_N_SETS (regno
) == 1 && !added_sets
2378 && !REG_USERVAR_P (x
));
2382 /* Check whether X, the destination of a set, refers to part of
2383 the register specified by REG. */
2386 reg_subword_p (rtx x
, rtx reg
)
2388 /* Check that reg is an integer mode register. */
2389 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2392 if (GET_CODE (x
) == STRICT_LOW_PART
2393 || GET_CODE (x
) == ZERO_EXTRACT
)
2396 return GET_CODE (x
) == SUBREG
2397 && SUBREG_REG (x
) == reg
2398 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2401 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2402 Note that the INSN should be deleted *after* removing dead edges, so
2403 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2404 but not for a (set (pc) (label_ref FOO)). */
2407 update_cfg_for_uncondjump (rtx_insn
*insn
)
2409 basic_block bb
= BLOCK_FOR_INSN (insn
);
2410 gcc_assert (BB_END (bb
) == insn
);
2412 purge_dead_edges (bb
);
2415 if (EDGE_COUNT (bb
->succs
) == 1)
2419 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2421 /* Remove barriers from the footer if there are any. */
2422 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2423 if (BARRIER_P (insn
))
2425 if (PREV_INSN (insn
))
2426 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2428 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2429 if (NEXT_INSN (insn
))
2430 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2432 else if (LABEL_P (insn
))
2437 /* Try to combine the insns I0, I1 and I2 into I3.
2438 Here I0, I1 and I2 appear earlier than I3.
2439 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2442 If we are combining more than two insns and the resulting insn is not
2443 recognized, try splitting it into two insns. If that happens, I2 and I3
2444 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2445 Otherwise, I0, I1 and I2 are pseudo-deleted.
2447 Return 0 if the combination does not work. Then nothing is changed.
2448 If we did the combination, return the insn at which combine should
2451 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2452 new direct jump instruction.
2454 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2455 been I3 passed to an earlier try_combine within the same basic
2459 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2460 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2462 /* New patterns for I3 and I2, respectively. */
2463 rtx newpat
, newi2pat
= 0;
2464 rtvec newpat_vec_with_clobbers
= 0;
2465 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2466 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2468 int added_sets_0
, added_sets_1
, added_sets_2
;
2469 /* Total number of SETs to put into I3. */
2471 /* Nonzero if I2's or I1's body now appears in I3. */
2472 int i2_is_used
= 0, i1_is_used
= 0;
2473 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2474 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2475 /* Contains I3 if the destination of I3 is used in its source, which means
2476 that the old life of I3 is being killed. If that usage is placed into
2477 I2 and not in I3, a REG_DEAD note must be made. */
2478 rtx i3dest_killed
= 0;
2479 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2480 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2481 /* Copy of SET_SRC of I1 and I0, if needed. */
2482 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2483 /* Set if I2DEST was reused as a scratch register. */
2484 bool i2scratch
= false;
2485 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2486 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2487 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2488 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2489 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2490 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2491 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2492 /* Notes that must be added to REG_NOTES in I3 and I2. */
2493 rtx new_i3_notes
, new_i2_notes
;
2494 /* Notes that we substituted I3 into I2 instead of the normal case. */
2495 int i3_subst_into_i2
= 0;
2496 /* Notes that I1, I2 or I3 is a MULT operation. */
2499 int changed_i3_dest
= 0;
2502 rtx_insn
*temp_insn
;
2504 struct insn_link
*link
;
2506 rtx new_other_notes
;
2509 /* Only try four-insn combinations when there's high likelihood of
2510 success. Look for simple insns, such as loads of constants or
2511 binary operations involving a constant. */
2518 if (!flag_expensive_optimizations
)
2521 for (i
= 0; i
< 4; i
++)
2523 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2524 rtx set
= single_set (insn
);
2528 src
= SET_SRC (set
);
2529 if (CONSTANT_P (src
))
2534 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2536 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2537 || GET_CODE (src
) == LSHIFTRT
)
2540 if (ngood
< 2 && nshift
< 2)
2544 /* Exit early if one of the insns involved can't be used for
2546 if (cant_combine_insn_p (i3
)
2547 || cant_combine_insn_p (i2
)
2548 || (i1
&& cant_combine_insn_p (i1
))
2549 || (i0
&& cant_combine_insn_p (i0
))
2550 || likely_spilled_retval_p (i3
))
2554 undobuf
.other_insn
= 0;
2556 /* Reset the hard register usage information. */
2557 CLEAR_HARD_REG_SET (newpat_used_regs
);
2559 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2562 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2563 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2565 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2566 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2568 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2569 INSN_UID (i2
), INSN_UID (i3
));
2572 /* If multiple insns feed into one of I2 or I3, they can be in any
2573 order. To simplify the code below, reorder them in sequence. */
2574 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2575 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2576 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2577 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2578 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2579 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2581 added_links_insn
= 0;
2583 /* First check for one important special case that the code below will
2584 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2585 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2586 we may be able to replace that destination with the destination of I3.
2587 This occurs in the common code where we compute both a quotient and
2588 remainder into a structure, in which case we want to do the computation
2589 directly into the structure to avoid register-register copies.
2591 Note that this case handles both multiple sets in I2 and also cases
2592 where I2 has a number of CLOBBERs inside the PARALLEL.
2594 We make very conservative checks below and only try to handle the
2595 most common cases of this. For example, we only handle the case
2596 where I2 and I3 are adjacent to avoid making difficult register
2599 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2600 && REG_P (SET_SRC (PATTERN (i3
)))
2601 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2602 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2603 && GET_CODE (PATTERN (i2
)) == PARALLEL
2604 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2605 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2606 below would need to check what is inside (and reg_overlap_mentioned_p
2607 doesn't support those codes anyway). Don't allow those destinations;
2608 the resulting insn isn't likely to be recognized anyway. */
2609 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2610 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2611 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2612 SET_DEST (PATTERN (i3
)))
2613 && next_active_insn (i2
) == i3
)
2615 rtx p2
= PATTERN (i2
);
2617 /* Make sure that the destination of I3,
2618 which we are going to substitute into one output of I2,
2619 is not used within another output of I2. We must avoid making this:
2620 (parallel [(set (mem (reg 69)) ...)
2621 (set (reg 69) ...)])
2622 which is not well-defined as to order of actions.
2623 (Besides, reload can't handle output reloads for this.)
2625 The problem can also happen if the dest of I3 is a memory ref,
2626 if another dest in I2 is an indirect memory ref. */
2627 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2628 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2629 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2630 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2631 SET_DEST (XVECEXP (p2
, 0, i
))))
2634 if (i
== XVECLEN (p2
, 0))
2635 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2636 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2637 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2642 subst_low_luid
= DF_INSN_LUID (i2
);
2644 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2645 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2646 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2647 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2649 /* Replace the dest in I2 with our dest and make the resulting
2650 insn the new pattern for I3. Then skip to where we validate
2651 the pattern. Everything was set up above. */
2652 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2654 i3_subst_into_i2
= 1;
2655 goto validate_replacement
;
2659 /* If I2 is setting a pseudo to a constant and I3 is setting some
2660 sub-part of it to another constant, merge them by making a new
2663 && (temp_expr
= single_set (i2
)) != 0
2664 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2665 && GET_CODE (PATTERN (i3
)) == SET
2666 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2667 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2669 rtx dest
= SET_DEST (PATTERN (i3
));
2673 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2675 if (CONST_INT_P (XEXP (dest
, 1))
2676 && CONST_INT_P (XEXP (dest
, 2)))
2678 width
= INTVAL (XEXP (dest
, 1));
2679 offset
= INTVAL (XEXP (dest
, 2));
2680 dest
= XEXP (dest
, 0);
2681 if (BITS_BIG_ENDIAN
)
2682 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2687 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2688 dest
= XEXP (dest
, 0);
2689 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2695 /* If this is the low part, we're done. */
2696 if (subreg_lowpart_p (dest
))
2698 /* Handle the case where inner is twice the size of outer. */
2699 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2700 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2701 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2702 /* Otherwise give up for now. */
2709 rtx inner
= SET_SRC (PATTERN (i3
));
2710 rtx outer
= SET_SRC (temp_expr
);
2713 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2714 std::make_pair (inner
, GET_MODE (dest
)),
2719 subst_low_luid
= DF_INSN_LUID (i2
);
2720 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2721 i2dest
= SET_DEST (temp_expr
);
2722 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2724 /* Replace the source in I2 with the new constant and make the
2725 resulting insn the new pattern for I3. Then skip to where we
2726 validate the pattern. Everything was set up above. */
2727 SUBST (SET_SRC (temp_expr
),
2728 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2730 newpat
= PATTERN (i2
);
2732 /* The dest of I3 has been replaced with the dest of I2. */
2733 changed_i3_dest
= 1;
2734 goto validate_replacement
;
2739 /* If we have no I1 and I2 looks like:
2740 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2742 make up a dummy I1 that is
2745 (set (reg:CC X) (compare:CC Y (const_int 0)))
2747 (We can ignore any trailing CLOBBERs.)
2749 This undoes a previous combination and allows us to match a branch-and-
2752 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2753 && XVECLEN (PATTERN (i2
), 0) >= 2
2754 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2755 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2757 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2758 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2759 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2760 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2761 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2762 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2764 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2765 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2770 /* We make I1 with the same INSN_UID as I2. This gives it
2771 the same DF_INSN_LUID for value tracking. Our fake I1 will
2772 never appear in the insn stream so giving it the same INSN_UID
2773 as I2 will not cause a problem. */
2775 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2776 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2778 INSN_UID (i1
) = INSN_UID (i2
);
2780 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2781 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2782 SET_DEST (PATTERN (i1
)));
2783 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2788 /* Verify that I2 and I1 are valid for combining. */
2789 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2790 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2792 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2799 /* Record whether I2DEST is used in I2SRC and similarly for the other
2800 cases. Knowing this will help in register status updating below. */
2801 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2802 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2803 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2804 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2805 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2806 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2807 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2808 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2809 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2811 /* For the earlier insns, determine which of the subsequent ones they
2813 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2814 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2815 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2816 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2817 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2819 /* Ensure that I3's pattern can be the destination of combines. */
2820 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2821 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2822 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2823 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2830 /* See if any of the insns is a MULT operation. Unless one is, we will
2831 reject a combination that is, since it must be slower. Be conservative
2833 if (GET_CODE (i2src
) == MULT
2834 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2835 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2836 || (GET_CODE (PATTERN (i3
)) == SET
2837 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2840 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2841 We used to do this EXCEPT in one case: I3 has a post-inc in an
2842 output operand. However, that exception can give rise to insns like
2844 which is a famous insn on the PDP-11 where the value of r3 used as the
2845 source was model-dependent. Avoid this sort of thing. */
2848 if (!(GET_CODE (PATTERN (i3
)) == SET
2849 && REG_P (SET_SRC (PATTERN (i3
)))
2850 && MEM_P (SET_DEST (PATTERN (i3
)))
2851 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2852 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2853 /* It's not the exception. */
2858 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2859 if (REG_NOTE_KIND (link
) == REG_INC
2860 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2862 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2870 /* See if the SETs in I1 or I2 need to be kept around in the merged
2871 instruction: whenever the value set there is still needed past I3.
2872 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2874 For the SET in I1, we have two cases: if I1 and I2 independently feed
2875 into I3, the set in I1 needs to be kept around unless I1DEST dies
2876 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2877 in I1 needs to be kept around unless I1DEST dies or is set in either
2878 I2 or I3. The same considerations apply to I0. */
2880 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2883 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2884 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2889 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2890 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2891 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2892 && dead_or_set_p (i2
, i0dest
)));
2896 /* We are about to copy insns for the case where they need to be kept
2897 around. Check that they can be copied in the merged instruction. */
2899 if (targetm
.cannot_copy_insn_p
2900 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2901 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2902 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2908 /* If the set in I2 needs to be kept around, we must make a copy of
2909 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2910 PATTERN (I2), we are only substituting for the original I1DEST, not into
2911 an already-substituted copy. This also prevents making self-referential
2912 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2917 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2918 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2920 i2pat
= copy_rtx (PATTERN (i2
));
2925 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2926 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2928 i1pat
= copy_rtx (PATTERN (i1
));
2933 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2934 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2936 i0pat
= copy_rtx (PATTERN (i0
));
2941 /* Substitute in the latest insn for the regs set by the earlier ones. */
2943 maxreg
= max_reg_num ();
2948 /* Many machines that don't use CC0 have insns that can both perform an
2949 arithmetic operation and set the condition code. These operations will
2950 be represented as a PARALLEL with the first element of the vector
2951 being a COMPARE of an arithmetic operation with the constant zero.
2952 The second element of the vector will set some pseudo to the result
2953 of the same arithmetic operation. If we simplify the COMPARE, we won't
2954 match such a pattern and so will generate an extra insn. Here we test
2955 for this case, where both the comparison and the operation result are
2956 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2957 I2SRC. Later we will make the PARALLEL that contains I2. */
2959 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2960 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2961 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2962 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2965 rtx
*cc_use_loc
= NULL
;
2966 rtx_insn
*cc_use_insn
= NULL
;
2967 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2968 enum machine_mode compare_mode
, orig_compare_mode
;
2969 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2971 newpat
= PATTERN (i3
);
2972 newpat_dest
= SET_DEST (newpat
);
2973 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2975 if (undobuf
.other_insn
== 0
2976 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2979 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2980 compare_code
= simplify_compare_const (compare_code
,
2981 GET_MODE (i2dest
), op0
, &op1
);
2982 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2985 /* Do the rest only if op1 is const0_rtx, which may be the
2986 result of simplification. */
2987 if (op1
== const0_rtx
)
2989 /* If a single use of the CC is found, prepare to modify it
2990 when SELECT_CC_MODE returns a new CC-class mode, or when
2991 the above simplify_compare_const() returned a new comparison
2992 operator. undobuf.other_insn is assigned the CC use insn
2993 when modifying it. */
2996 #ifdef SELECT_CC_MODE
2997 enum machine_mode new_mode
2998 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2999 if (new_mode
!= orig_compare_mode
3000 && can_change_dest_mode (SET_DEST (newpat
),
3001 added_sets_2
, new_mode
))
3003 unsigned int regno
= REGNO (newpat_dest
);
3004 compare_mode
= new_mode
;
3005 if (regno
< FIRST_PSEUDO_REGISTER
)
3006 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3009 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3010 newpat_dest
= regno_reg_rtx
[regno
];
3014 /* Cases for modifying the CC-using comparison. */
3015 if (compare_code
!= orig_compare_code
3016 /* ??? Do we need to verify the zero rtx? */
3017 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3019 /* Replace cc_use_loc with entire new RTX. */
3021 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3022 newpat_dest
, const0_rtx
));
3023 undobuf
.other_insn
= cc_use_insn
;
3025 else if (compare_mode
!= orig_compare_mode
)
3027 /* Just replace the CC reg with a new mode. */
3028 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3029 undobuf
.other_insn
= cc_use_insn
;
3033 /* Now we modify the current newpat:
3034 First, SET_DEST(newpat) is updated if the CC mode has been
3035 altered. For targets without SELECT_CC_MODE, this should be
3037 if (compare_mode
!= orig_compare_mode
)
3038 SUBST (SET_DEST (newpat
), newpat_dest
);
3039 /* This is always done to propagate i2src into newpat. */
3040 SUBST (SET_SRC (newpat
),
3041 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3042 /* Create new version of i2pat if needed; the below PARALLEL
3043 creation needs this to work correctly. */
3044 if (! rtx_equal_p (i2src
, op0
))
3045 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3051 if (i2_is_used
== 0)
3053 /* It is possible that the source of I2 or I1 may be performing
3054 an unneeded operation, such as a ZERO_EXTEND of something
3055 that is known to have the high part zero. Handle that case
3056 by letting subst look at the inner insns.
3058 Another way to do this would be to have a function that tries
3059 to simplify a single insn instead of merging two or more
3060 insns. We don't do this because of the potential of infinite
3061 loops and because of the potential extra memory required.
3062 However, doing it the way we are is a bit of a kludge and
3063 doesn't catch all cases.
3065 But only do this if -fexpensive-optimizations since it slows
3066 things down and doesn't usually win.
3068 This is not done in the COMPARE case above because the
3069 unmodified I2PAT is used in the PARALLEL and so a pattern
3070 with a modified I2SRC would not match. */
3072 if (flag_expensive_optimizations
)
3074 /* Pass pc_rtx so no substitutions are done, just
3078 subst_low_luid
= DF_INSN_LUID (i1
);
3079 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3082 subst_low_luid
= DF_INSN_LUID (i2
);
3083 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3086 n_occurrences
= 0; /* `subst' counts here */
3087 subst_low_luid
= DF_INSN_LUID (i2
);
3089 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3090 copy of I2SRC each time we substitute it, in order to avoid creating
3091 self-referential RTL when we will be substituting I1SRC for I1DEST
3092 later. Likewise if I0 feeds into I2, either directly or indirectly
3093 through I1, and I0DEST is in I0SRC. */
3094 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3095 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3096 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3097 && i0dest_in_i0src
));
3100 /* Record whether I2's body now appears within I3's body. */
3101 i2_is_used
= n_occurrences
;
3104 /* If we already got a failure, don't try to do more. Otherwise, try to
3105 substitute I1 if we have it. */
3107 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3109 /* Check that an autoincrement side-effect on I1 has not been lost.
3110 This happens if I1DEST is mentioned in I2 and dies there, and
3111 has disappeared from the new pattern. */
3112 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3114 && dead_or_set_p (i2
, i1dest
)
3115 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3116 /* Before we can do this substitution, we must redo the test done
3117 above (see detailed comments there) that ensures I1DEST isn't
3118 mentioned in any SETs in NEWPAT that are field assignments. */
3119 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3127 subst_low_luid
= DF_INSN_LUID (i1
);
3129 /* If the following substitution will modify I1SRC, make a copy of it
3130 for the case where it is substituted for I1DEST in I2PAT later. */
3131 if (added_sets_2
&& i1_feeds_i2_n
)
3132 i1src_copy
= copy_rtx (i1src
);
3134 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3135 copy of I1SRC each time we substitute it, in order to avoid creating
3136 self-referential RTL when we will be substituting I0SRC for I0DEST
3138 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3139 i0_feeds_i1_n
&& i0dest_in_i0src
);
3142 /* Record whether I1's body now appears within I3's body. */
3143 i1_is_used
= n_occurrences
;
3146 /* Likewise for I0 if we have it. */
3148 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3150 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3151 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3152 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3153 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3154 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3161 /* If the following substitution will modify I0SRC, make a copy of it
3162 for the case where it is substituted for I0DEST in I1PAT later. */
3163 if (added_sets_1
&& i0_feeds_i1_n
)
3164 i0src_copy
= copy_rtx (i0src
);
3165 /* And a copy for I0DEST in I2PAT substitution. */
3166 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3167 || (i0_feeds_i2_n
)))
3168 i0src_copy2
= copy_rtx (i0src
);
3171 subst_low_luid
= DF_INSN_LUID (i0
);
3172 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3176 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3177 to count all the ways that I2SRC and I1SRC can be used. */
3178 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3179 && i2_is_used
+ added_sets_2
> 1)
3180 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3181 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3183 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3184 && (n_occurrences
+ added_sets_0
3185 + (added_sets_1
&& i0_feeds_i1_n
)
3186 + (added_sets_2
&& i0_feeds_i2_n
)
3188 /* Fail if we tried to make a new register. */
3189 || max_reg_num () != maxreg
3190 /* Fail if we couldn't do something and have a CLOBBER. */
3191 || GET_CODE (newpat
) == CLOBBER
3192 /* Fail if this new pattern is a MULT and we didn't have one before
3193 at the outer level. */
3194 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3201 /* If the actions of the earlier insns must be kept
3202 in addition to substituting them into the latest one,
3203 we must make a new PARALLEL for the latest insn
3204 to hold additional the SETs. */
3206 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3208 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3211 if (GET_CODE (newpat
) == PARALLEL
)
3213 rtvec old
= XVEC (newpat
, 0);
3214 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3215 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3216 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3217 sizeof (old
->elem
[0]) * old
->num_elem
);
3222 total_sets
= 1 + extra_sets
;
3223 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3224 XVECEXP (newpat
, 0, 0) = old
;
3228 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3234 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3236 XVECEXP (newpat
, 0, --total_sets
) = t
;
3242 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3243 i0_feeds_i1_n
&& i0dest_in_i0src
);
3244 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3245 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3247 XVECEXP (newpat
, 0, --total_sets
) = t
;
3251 validate_replacement
:
3253 /* Note which hard regs this insn has as inputs. */
3254 mark_used_regs_combine (newpat
);
3256 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3257 consider splitting this pattern, we might need these clobbers. */
3258 if (i1
&& GET_CODE (newpat
) == PARALLEL
3259 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3261 int len
= XVECLEN (newpat
, 0);
3263 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3264 for (i
= 0; i
< len
; i
++)
3265 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3268 /* Is the result of combination a valid instruction? */
3269 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3271 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3272 the second SET's destination is a register that is unused and isn't
3273 marked as an instruction that might trap in an EH region. In that case,
3274 we just need the first SET. This can occur when simplifying a divmod
3275 insn. We *must* test for this case here because the code below that
3276 splits two independent SETs doesn't handle this case correctly when it
3277 updates the register status.
3279 It's pointless doing this if we originally had two sets, one from
3280 i3, and one from i2. Combining then splitting the parallel results
3281 in the original i2 again plus an invalid insn (which we delete).
3282 The net effect is only to move instructions around, which makes
3283 debug info less accurate.
3285 Also check the case where the first SET's destination is unused.
3286 That would not cause incorrect code, but does cause an unneeded
3289 if (insn_code_number
< 0
3290 && !(added_sets_2
&& i1
== 0)
3291 && GET_CODE (newpat
) == PARALLEL
3292 && XVECLEN (newpat
, 0) == 2
3293 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3294 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3295 && asm_noperands (newpat
) < 0)
3297 rtx set0
= XVECEXP (newpat
, 0, 0);
3298 rtx set1
= XVECEXP (newpat
, 0, 1);
3300 if (((REG_P (SET_DEST (set1
))
3301 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3302 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3303 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3304 && insn_nothrow_p (i3
)
3305 && !side_effects_p (SET_SRC (set1
)))
3308 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3311 else if (((REG_P (SET_DEST (set0
))
3312 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3313 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3314 && find_reg_note (i3
, REG_UNUSED
,
3315 SUBREG_REG (SET_DEST (set0
)))))
3316 && insn_nothrow_p (i3
)
3317 && !side_effects_p (SET_SRC (set0
)))
3320 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3322 if (insn_code_number
>= 0)
3323 changed_i3_dest
= 1;
3327 /* If we were combining three insns and the result is a simple SET
3328 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3329 insns. There are two ways to do this. It can be split using a
3330 machine-specific method (like when you have an addition of a large
3331 constant) or by combine in the function find_split_point. */
3333 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3334 && asm_noperands (newpat
) < 0)
3336 rtx parallel
, *split
;
3337 rtx_insn
*m_split_insn
;
3339 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3340 use I2DEST as a scratch register will help. In the latter case,
3341 convert I2DEST to the mode of the source of NEWPAT if we can. */
3343 m_split_insn
= combine_split_insns (newpat
, i3
);
3345 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3346 inputs of NEWPAT. */
3348 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3349 possible to try that as a scratch reg. This would require adding
3350 more code to make it work though. */
3352 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3354 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3356 /* First try to split using the original register as a
3357 scratch register. */
3358 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3359 gen_rtvec (2, newpat
,
3360 gen_rtx_CLOBBER (VOIDmode
,
3362 m_split_insn
= combine_split_insns (parallel
, i3
);
3364 /* If that didn't work, try changing the mode of I2DEST if
3366 if (m_split_insn
== 0
3367 && new_mode
!= GET_MODE (i2dest
)
3368 && new_mode
!= VOIDmode
3369 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3371 enum machine_mode old_mode
= GET_MODE (i2dest
);
3374 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3375 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3378 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3379 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3382 parallel
= (gen_rtx_PARALLEL
3384 gen_rtvec (2, newpat
,
3385 gen_rtx_CLOBBER (VOIDmode
,
3387 m_split_insn
= combine_split_insns (parallel
, i3
);
3389 if (m_split_insn
== 0
3390 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3394 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3395 buf
= undobuf
.undos
;
3396 undobuf
.undos
= buf
->next
;
3397 buf
->next
= undobuf
.frees
;
3398 undobuf
.frees
= buf
;
3402 i2scratch
= m_split_insn
!= 0;
3405 /* If recog_for_combine has discarded clobbers, try to use them
3406 again for the split. */
3407 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3409 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3410 m_split_insn
= combine_split_insns (parallel
, i3
);
3413 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3415 rtx m_split_pat
= PATTERN (m_split_insn
);
3416 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3417 if (insn_code_number
>= 0)
3418 newpat
= m_split_pat
;
3420 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3421 && (next_nonnote_nondebug_insn (i2
) == i3
3422 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3425 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3426 newi2pat
= PATTERN (m_split_insn
);
3428 i3set
= single_set (NEXT_INSN (m_split_insn
));
3429 i2set
= single_set (m_split_insn
);
3431 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3433 /* If I2 or I3 has multiple SETs, we won't know how to track
3434 register status, so don't use these insns. If I2's destination
3435 is used between I2 and I3, we also can't use these insns. */
3437 if (i2_code_number
>= 0 && i2set
&& i3set
3438 && (next_nonnote_nondebug_insn (i2
) == i3
3439 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3440 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3442 if (insn_code_number
>= 0)
3445 /* It is possible that both insns now set the destination of I3.
3446 If so, we must show an extra use of it. */
3448 if (insn_code_number
>= 0)
3450 rtx new_i3_dest
= SET_DEST (i3set
);
3451 rtx new_i2_dest
= SET_DEST (i2set
);
3453 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3454 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3455 || GET_CODE (new_i3_dest
) == SUBREG
)
3456 new_i3_dest
= XEXP (new_i3_dest
, 0);
3458 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3459 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3460 || GET_CODE (new_i2_dest
) == SUBREG
)
3461 new_i2_dest
= XEXP (new_i2_dest
, 0);
3463 if (REG_P (new_i3_dest
)
3464 && REG_P (new_i2_dest
)
3465 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3466 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3470 /* If we can split it and use I2DEST, go ahead and see if that
3471 helps things be recognized. Verify that none of the registers
3472 are set between I2 and I3. */
3473 if (insn_code_number
< 0
3474 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3478 /* We need I2DEST in the proper mode. If it is a hard register
3479 or the only use of a pseudo, we can change its mode.
3480 Make sure we don't change a hard register to have a mode that
3481 isn't valid for it, or change the number of registers. */
3482 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3483 || GET_MODE (*split
) == VOIDmode
3484 || can_change_dest_mode (i2dest
, added_sets_2
,
3486 && (next_nonnote_nondebug_insn (i2
) == i3
3487 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3488 /* We can't overwrite I2DEST if its value is still used by
3490 && ! reg_referenced_p (i2dest
, newpat
))
3492 rtx newdest
= i2dest
;
3493 enum rtx_code split_code
= GET_CODE (*split
);
3494 enum machine_mode split_mode
= GET_MODE (*split
);
3495 bool subst_done
= false;
3496 newi2pat
= NULL_RTX
;
3500 /* *SPLIT may be part of I2SRC, so make sure we have the
3501 original expression around for later debug processing.
3502 We should not need I2SRC any more in other cases. */
3503 if (MAY_HAVE_DEBUG_INSNS
)
3504 i2src
= copy_rtx (i2src
);
3508 /* Get NEWDEST as a register in the proper mode. We have already
3509 validated that we can do this. */
3510 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3512 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3513 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3516 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3517 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3521 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3522 an ASHIFT. This can occur if it was inside a PLUS and hence
3523 appeared to be a memory address. This is a kludge. */
3524 if (split_code
== MULT
3525 && CONST_INT_P (XEXP (*split
, 1))
3526 && INTVAL (XEXP (*split
, 1)) > 0
3527 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3529 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3530 XEXP (*split
, 0), GEN_INT (i
)));
3531 /* Update split_code because we may not have a multiply
3533 split_code
= GET_CODE (*split
);
3536 #ifdef INSN_SCHEDULING
3537 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3538 be written as a ZERO_EXTEND. */
3539 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3541 #ifdef LOAD_EXTEND_OP
3542 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3543 what it really is. */
3544 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3546 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3547 SUBREG_REG (*split
)));
3550 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3551 SUBREG_REG (*split
)));
3555 /* Attempt to split binary operators using arithmetic identities. */
3556 if (BINARY_P (SET_SRC (newpat
))
3557 && split_mode
== GET_MODE (SET_SRC (newpat
))
3558 && ! side_effects_p (SET_SRC (newpat
)))
3560 rtx setsrc
= SET_SRC (newpat
);
3561 enum machine_mode mode
= GET_MODE (setsrc
);
3562 enum rtx_code code
= GET_CODE (setsrc
);
3563 rtx src_op0
= XEXP (setsrc
, 0);
3564 rtx src_op1
= XEXP (setsrc
, 1);
3566 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3567 if (rtx_equal_p (src_op0
, src_op1
))
3569 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3570 SUBST (XEXP (setsrc
, 0), newdest
);
3571 SUBST (XEXP (setsrc
, 1), newdest
);
3574 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3575 else if ((code
== PLUS
|| code
== MULT
)
3576 && GET_CODE (src_op0
) == code
3577 && GET_CODE (XEXP (src_op0
, 0)) == code
3578 && (INTEGRAL_MODE_P (mode
)
3579 || (FLOAT_MODE_P (mode
)
3580 && flag_unsafe_math_optimizations
)))
3582 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3583 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3584 rtx r
= XEXP (src_op0
, 1);
3587 /* Split both "((X op Y) op X) op Y" and
3588 "((X op Y) op Y) op X" as "T op T" where T is
3590 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3591 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3593 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3595 SUBST (XEXP (setsrc
, 0), newdest
);
3596 SUBST (XEXP (setsrc
, 1), newdest
);
3599 /* Split "((X op X) op Y) op Y)" as "T op T" where
3601 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3603 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3604 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3605 SUBST (XEXP (setsrc
, 0), newdest
);
3606 SUBST (XEXP (setsrc
, 1), newdest
);
3614 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3615 SUBST (*split
, newdest
);
3618 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3620 /* recog_for_combine might have added CLOBBERs to newi2pat.
3621 Make sure NEWPAT does not depend on the clobbered regs. */
3622 if (GET_CODE (newi2pat
) == PARALLEL
)
3623 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3624 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3626 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3627 if (reg_overlap_mentioned_p (reg
, newpat
))
3634 /* If the split point was a MULT and we didn't have one before,
3635 don't use one now. */
3636 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3637 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3641 /* Check for a case where we loaded from memory in a narrow mode and
3642 then sign extended it, but we need both registers. In that case,
3643 we have a PARALLEL with both loads from the same memory location.
3644 We can split this into a load from memory followed by a register-register
3645 copy. This saves at least one insn, more if register allocation can
3648 We cannot do this if the destination of the first assignment is a
3649 condition code register or cc0. We eliminate this case by making sure
3650 the SET_DEST and SET_SRC have the same mode.
3652 We cannot do this if the destination of the second assignment is
3653 a register that we have already assumed is zero-extended. Similarly
3654 for a SUBREG of such a register. */
3656 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3657 && GET_CODE (newpat
) == PARALLEL
3658 && XVECLEN (newpat
, 0) == 2
3659 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3660 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3661 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3662 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3663 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3664 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3665 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3666 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3668 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3669 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3670 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3672 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3673 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3674 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3675 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3676 != GET_MODE_MASK (word_mode
))))
3677 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3678 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3680 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3681 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3682 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3683 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3684 != GET_MODE_MASK (word_mode
)))))
3685 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3686 SET_SRC (XVECEXP (newpat
, 0, 1)))
3687 && ! find_reg_note (i3
, REG_UNUSED
,
3688 SET_DEST (XVECEXP (newpat
, 0, 0))))
3692 newi2pat
= XVECEXP (newpat
, 0, 0);
3693 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3694 newpat
= XVECEXP (newpat
, 0, 1);
3695 SUBST (SET_SRC (newpat
),
3696 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3697 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3699 if (i2_code_number
>= 0)
3700 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3702 if (insn_code_number
>= 0)
3706 /* Similarly, check for a case where we have a PARALLEL of two independent
3707 SETs but we started with three insns. In this case, we can do the sets
3708 as two separate insns. This case occurs when some SET allows two
3709 other insns to combine, but the destination of that SET is still live. */
3711 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3712 && GET_CODE (newpat
) == PARALLEL
3713 && XVECLEN (newpat
, 0) == 2
3714 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3715 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3716 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3717 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3718 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3719 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3720 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3721 XVECEXP (newpat
, 0, 0))
3722 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3723 XVECEXP (newpat
, 0, 1))
3724 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3725 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3727 rtx set0
= XVECEXP (newpat
, 0, 0);
3728 rtx set1
= XVECEXP (newpat
, 0, 1);
3730 /* Normally, it doesn't matter which of the two is done first,
3731 but the one that references cc0 can't be the second, and
3732 one which uses any regs/memory set in between i2 and i3 can't
3733 be first. The PARALLEL might also have been pre-existing in i3,
3734 so we need to make sure that we won't wrongly hoist a SET to i2
3735 that would conflict with a death note present in there. */
3736 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3737 && !(REG_P (SET_DEST (set1
))
3738 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3739 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3740 && find_reg_note (i2
, REG_DEAD
,
3741 SUBREG_REG (SET_DEST (set1
))))
3743 && !reg_referenced_p (cc0_rtx
, set0
)
3745 /* If I3 is a jump, ensure that set0 is a jump so that
3746 we do not create invalid RTL. */
3747 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3753 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3754 && !(REG_P (SET_DEST (set0
))
3755 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3756 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3757 && find_reg_note (i2
, REG_DEAD
,
3758 SUBREG_REG (SET_DEST (set0
))))
3760 && !reg_referenced_p (cc0_rtx
, set1
)
3762 /* If I3 is a jump, ensure that set1 is a jump so that
3763 we do not create invalid RTL. */
3764 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3776 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3778 if (i2_code_number
>= 0)
3780 /* recog_for_combine might have added CLOBBERs to newi2pat.
3781 Make sure NEWPAT does not depend on the clobbered regs. */
3782 if (GET_CODE (newi2pat
) == PARALLEL
)
3784 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3785 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3787 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3788 if (reg_overlap_mentioned_p (reg
, newpat
))
3796 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3800 /* If it still isn't recognized, fail and change things back the way they
3802 if ((insn_code_number
< 0
3803 /* Is the result a reasonable ASM_OPERANDS? */
3804 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3810 /* If we had to change another insn, make sure it is valid also. */
3811 if (undobuf
.other_insn
)
3813 CLEAR_HARD_REG_SET (newpat_used_regs
);
3815 other_pat
= PATTERN (undobuf
.other_insn
);
3816 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3819 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3827 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3828 they are adjacent to each other or not. */
3830 rtx_insn
*p
= prev_nonnote_insn (i3
);
3831 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3832 && sets_cc0_p (newi2pat
))
3840 /* Only allow this combination if insn_rtx_costs reports that the
3841 replacement instructions are cheaper than the originals. */
3842 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3848 if (MAY_HAVE_DEBUG_INSNS
)
3852 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3853 if (undo
->kind
== UNDO_MODE
)
3855 rtx reg
= *undo
->where
.r
;
3856 enum machine_mode new_mode
= GET_MODE (reg
);
3857 enum machine_mode old_mode
= undo
->old_contents
.m
;
3859 /* Temporarily revert mode back. */
3860 adjust_reg_mode (reg
, old_mode
);
3862 if (reg
== i2dest
&& i2scratch
)
3864 /* If we used i2dest as a scratch register with a
3865 different mode, substitute it for the original
3866 i2src while its original mode is temporarily
3867 restored, and then clear i2scratch so that we don't
3868 do it again later. */
3869 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3872 /* Put back the new mode. */
3873 adjust_reg_mode (reg
, new_mode
);
3877 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3878 rtx_insn
*first
, *last
;
3883 last
= last_combined_insn
;
3888 last
= undobuf
.other_insn
;
3890 if (DF_INSN_LUID (last
)
3891 < DF_INSN_LUID (last_combined_insn
))
3892 last
= last_combined_insn
;
3895 /* We're dealing with a reg that changed mode but not
3896 meaning, so we want to turn it into a subreg for
3897 the new mode. However, because of REG sharing and
3898 because its mode had already changed, we have to do
3899 it in two steps. First, replace any debug uses of
3900 reg, with its original mode temporarily restored,
3901 with this copy we have created; then, replace the
3902 copy with the SUBREG of the original shared reg,
3903 once again changed to the new mode. */
3904 propagate_for_debug (first
, last
, reg
, tempreg
,
3906 adjust_reg_mode (reg
, new_mode
);
3907 propagate_for_debug (first
, last
, tempreg
,
3908 lowpart_subreg (old_mode
, reg
, new_mode
),
3914 /* If we will be able to accept this, we have made a
3915 change to the destination of I3. This requires us to
3916 do a few adjustments. */
3918 if (changed_i3_dest
)
3920 PATTERN (i3
) = newpat
;
3921 adjust_for_new_dest (i3
);
3924 /* We now know that we can do this combination. Merge the insns and
3925 update the status of registers and LOG_LINKS. */
3927 if (undobuf
.other_insn
)
3931 PATTERN (undobuf
.other_insn
) = other_pat
;
3933 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3934 ensure that they are still valid. Then add any non-duplicate
3935 notes added by recog_for_combine. */
3936 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3938 next
= XEXP (note
, 1);
3940 if ((REG_NOTE_KIND (note
) == REG_DEAD
3941 && !reg_referenced_p (XEXP (note
, 0),
3942 PATTERN (undobuf
.other_insn
)))
3943 ||(REG_NOTE_KIND (note
) == REG_UNUSED
3944 && !reg_set_p (XEXP (note
, 0),
3945 PATTERN (undobuf
.other_insn
))))
3946 remove_note (undobuf
.other_insn
, note
);
3949 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3950 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
3957 struct insn_link
*link
;
3960 /* I3 now uses what used to be its destination and which is now
3961 I2's destination. This requires us to do a few adjustments. */
3962 PATTERN (i3
) = newpat
;
3963 adjust_for_new_dest (i3
);
3965 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3968 However, some later insn might be using I2's dest and have
3969 a LOG_LINK pointing at I3. We must remove this link.
3970 The simplest way to remove the link is to point it at I1,
3971 which we know will be a NOTE. */
3973 /* newi2pat is usually a SET here; however, recog_for_combine might
3974 have added some clobbers. */
3975 if (GET_CODE (newi2pat
) == PARALLEL
)
3976 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3978 ni2dest
= SET_DEST (newi2pat
);
3980 for (insn
= NEXT_INSN (i3
);
3981 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
3982 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3983 insn
= NEXT_INSN (insn
))
3985 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3987 FOR_EACH_LOG_LINK (link
, insn
)
3988 if (link
->insn
== i3
)
3997 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3998 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4001 /* Compute which registers we expect to eliminate. newi2pat may be setting
4002 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4003 same as i3dest, in which case newi2pat may be setting i1dest. */
4004 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4005 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4008 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4009 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4012 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
4013 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4017 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4019 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4020 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4022 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4024 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4026 /* Ensure that we do not have something that should not be shared but
4027 occurs multiple times in the new insns. Check this by first
4028 resetting all the `used' flags and then copying anything is shared. */
4030 reset_used_flags (i3notes
);
4031 reset_used_flags (i2notes
);
4032 reset_used_flags (i1notes
);
4033 reset_used_flags (i0notes
);
4034 reset_used_flags (newpat
);
4035 reset_used_flags (newi2pat
);
4036 if (undobuf
.other_insn
)
4037 reset_used_flags (PATTERN (undobuf
.other_insn
));
4039 i3notes
= copy_rtx_if_shared (i3notes
);
4040 i2notes
= copy_rtx_if_shared (i2notes
);
4041 i1notes
= copy_rtx_if_shared (i1notes
);
4042 i0notes
= copy_rtx_if_shared (i0notes
);
4043 newpat
= copy_rtx_if_shared (newpat
);
4044 newi2pat
= copy_rtx_if_shared (newi2pat
);
4045 if (undobuf
.other_insn
)
4046 reset_used_flags (PATTERN (undobuf
.other_insn
));
4048 INSN_CODE (i3
) = insn_code_number
;
4049 PATTERN (i3
) = newpat
;
4051 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4053 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4055 reset_used_flags (call_usage
);
4056 call_usage
= copy_rtx (call_usage
);
4060 /* I2SRC must still be meaningful at this point. Some splitting
4061 operations can invalidate I2SRC, but those operations do not
4064 replace_rtx (call_usage
, i2dest
, i2src
);
4068 replace_rtx (call_usage
, i1dest
, i1src
);
4070 replace_rtx (call_usage
, i0dest
, i0src
);
4072 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4075 if (undobuf
.other_insn
)
4076 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4078 /* We had one special case above where I2 had more than one set and
4079 we replaced a destination of one of those sets with the destination
4080 of I3. In that case, we have to update LOG_LINKS of insns later
4081 in this basic block. Note that this (expensive) case is rare.
4083 Also, in this case, we must pretend that all REG_NOTEs for I2
4084 actually came from I3, so that REG_UNUSED notes from I2 will be
4085 properly handled. */
4087 if (i3_subst_into_i2
)
4089 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4090 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4091 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4092 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4093 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4094 && ! find_reg_note (i2
, REG_UNUSED
,
4095 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4096 for (temp_insn
= NEXT_INSN (i2
);
4098 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4099 || BB_HEAD (this_basic_block
) != temp_insn
);
4100 temp_insn
= NEXT_INSN (temp_insn
))
4101 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4102 FOR_EACH_LOG_LINK (link
, temp_insn
)
4103 if (link
->insn
== i2
)
4109 while (XEXP (link
, 1))
4110 link
= XEXP (link
, 1);
4111 XEXP (link
, 1) = i2notes
;
4118 LOG_LINKS (i3
) = NULL
;
4120 LOG_LINKS (i2
) = NULL
;
4125 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4126 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4128 INSN_CODE (i2
) = i2_code_number
;
4129 PATTERN (i2
) = newi2pat
;
4133 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4134 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4136 SET_INSN_DELETED (i2
);
4141 LOG_LINKS (i1
) = NULL
;
4143 if (MAY_HAVE_DEBUG_INSNS
)
4144 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4146 SET_INSN_DELETED (i1
);
4151 LOG_LINKS (i0
) = NULL
;
4153 if (MAY_HAVE_DEBUG_INSNS
)
4154 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4156 SET_INSN_DELETED (i0
);
4159 /* Get death notes for everything that is now used in either I3 or
4160 I2 and used to die in a previous insn. If we built two new
4161 patterns, move from I1 to I2 then I2 to I3 so that we get the
4162 proper movement on registers that I2 modifies. */
4165 from_luid
= DF_INSN_LUID (i0
);
4167 from_luid
= DF_INSN_LUID (i1
);
4169 from_luid
= DF_INSN_LUID (i2
);
4171 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4172 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4174 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4176 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4177 elim_i2
, elim_i1
, elim_i0
);
4179 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4180 elim_i2
, elim_i1
, elim_i0
);
4182 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4183 elim_i2
, elim_i1
, elim_i0
);
4185 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4186 elim_i2
, elim_i1
, elim_i0
);
4188 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4189 elim_i2
, elim_i1
, elim_i0
);
4191 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4192 know these are REG_UNUSED and want them to go to the desired insn,
4193 so we always pass it as i3. */
4195 if (newi2pat
&& new_i2_notes
)
4196 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4200 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4203 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4204 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4205 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4206 in that case, it might delete I2. Similarly for I2 and I1.
4207 Show an additional death due to the REG_DEAD note we make here. If
4208 we discard it in distribute_notes, we will decrement it again. */
4212 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4213 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4214 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4217 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4218 elim_i2
, elim_i1
, elim_i0
);
4221 if (i2dest_in_i2src
)
4223 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4224 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4225 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4226 NULL_RTX
, NULL_RTX
);
4228 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4229 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4232 if (i1dest_in_i1src
)
4234 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4235 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4236 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4237 NULL_RTX
, NULL_RTX
);
4239 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4240 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4243 if (i0dest_in_i0src
)
4245 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4246 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4247 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4248 NULL_RTX
, NULL_RTX
);
4250 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4251 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4254 distribute_links (i3links
);
4255 distribute_links (i2links
);
4256 distribute_links (i1links
);
4257 distribute_links (i0links
);
4261 struct insn_link
*link
;
4262 rtx_insn
*i2_insn
= 0;
4263 rtx i2_val
= 0, set
;
4265 /* The insn that used to set this register doesn't exist, and
4266 this life of the register may not exist either. See if one of
4267 I3's links points to an insn that sets I2DEST. If it does,
4268 that is now the last known value for I2DEST. If we don't update
4269 this and I2 set the register to a value that depended on its old
4270 contents, we will get confused. If this insn is used, thing
4271 will be set correctly in combine_instructions. */
4272 FOR_EACH_LOG_LINK (link
, i3
)
4273 if ((set
= single_set (link
->insn
)) != 0
4274 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4275 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4277 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4279 /* If the reg formerly set in I2 died only once and that was in I3,
4280 zero its use count so it won't make `reload' do any work. */
4282 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4283 && ! i2dest_in_i2src
)
4284 INC_REG_N_SETS (REGNO (i2dest
), -1);
4287 if (i1
&& REG_P (i1dest
))
4289 struct insn_link
*link
;
4290 rtx_insn
*i1_insn
= 0;
4291 rtx i1_val
= 0, set
;
4293 FOR_EACH_LOG_LINK (link
, i3
)
4294 if ((set
= single_set (link
->insn
)) != 0
4295 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4296 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4298 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4300 if (! added_sets_1
&& ! i1dest_in_i1src
)
4301 INC_REG_N_SETS (REGNO (i1dest
), -1);
4304 if (i0
&& REG_P (i0dest
))
4306 struct insn_link
*link
;
4307 rtx_insn
*i0_insn
= 0;
4308 rtx i0_val
= 0, set
;
4310 FOR_EACH_LOG_LINK (link
, i3
)
4311 if ((set
= single_set (link
->insn
)) != 0
4312 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4313 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4315 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4317 if (! added_sets_0
&& ! i0dest_in_i0src
)
4318 INC_REG_N_SETS (REGNO (i0dest
), -1);
4321 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4322 been made to this insn. The order is important, because newi2pat
4323 can affect nonzero_bits of newpat. */
4325 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4326 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4329 if (undobuf
.other_insn
!= NULL_RTX
)
4333 fprintf (dump_file
, "modifying other_insn ");
4334 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4336 df_insn_rescan (undobuf
.other_insn
);
4339 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4343 fprintf (dump_file
, "modifying insn i0 ");
4344 dump_insn_slim (dump_file
, i0
);
4346 df_insn_rescan (i0
);
4349 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4353 fprintf (dump_file
, "modifying insn i1 ");
4354 dump_insn_slim (dump_file
, i1
);
4356 df_insn_rescan (i1
);
4359 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4363 fprintf (dump_file
, "modifying insn i2 ");
4364 dump_insn_slim (dump_file
, i2
);
4366 df_insn_rescan (i2
);
4369 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4373 fprintf (dump_file
, "modifying insn i3 ");
4374 dump_insn_slim (dump_file
, i3
);
4376 df_insn_rescan (i3
);
4379 /* Set new_direct_jump_p if a new return or simple jump instruction
4380 has been created. Adjust the CFG accordingly. */
4381 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4383 *new_direct_jump_p
= 1;
4384 mark_jump_label (PATTERN (i3
), i3
, 0);
4385 update_cfg_for_uncondjump (i3
);
4388 if (undobuf
.other_insn
!= NULL_RTX
4389 && (returnjump_p (undobuf
.other_insn
)
4390 || any_uncondjump_p (undobuf
.other_insn
)))
4392 *new_direct_jump_p
= 1;
4393 update_cfg_for_uncondjump (undobuf
.other_insn
);
4396 /* A noop might also need cleaning up of CFG, if it comes from the
4397 simplification of a jump. */
4399 && GET_CODE (newpat
) == SET
4400 && SET_SRC (newpat
) == pc_rtx
4401 && SET_DEST (newpat
) == pc_rtx
)
4403 *new_direct_jump_p
= 1;
4404 update_cfg_for_uncondjump (i3
);
4407 if (undobuf
.other_insn
!= NULL_RTX
4408 && JUMP_P (undobuf
.other_insn
)
4409 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4410 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4411 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4413 *new_direct_jump_p
= 1;
4414 update_cfg_for_uncondjump (undobuf
.other_insn
);
4417 combine_successes
++;
4420 if (added_links_insn
4421 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4422 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4423 return added_links_insn
;
4425 return newi2pat
? i2
: i3
;
4428 /* Undo all the modifications recorded in undobuf. */
4433 struct undo
*undo
, *next
;
4435 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4441 *undo
->where
.r
= undo
->old_contents
.r
;
4444 *undo
->where
.i
= undo
->old_contents
.i
;
4447 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4450 *undo
->where
.l
= undo
->old_contents
.l
;
4456 undo
->next
= undobuf
.frees
;
4457 undobuf
.frees
= undo
;
4463 /* We've committed to accepting the changes we made. Move all
4464 of the undos to the free list. */
4469 struct undo
*undo
, *next
;
4471 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4474 undo
->next
= undobuf
.frees
;
4475 undobuf
.frees
= undo
;
4480 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4481 where we have an arithmetic expression and return that point. LOC will
4484 try_combine will call this function to see if an insn can be split into
4488 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4491 enum rtx_code code
= GET_CODE (x
);
4493 unsigned HOST_WIDE_INT len
= 0;
4494 HOST_WIDE_INT pos
= 0;
4496 rtx inner
= NULL_RTX
;
4498 /* First special-case some codes. */
4502 #ifdef INSN_SCHEDULING
4503 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4505 if (MEM_P (SUBREG_REG (x
)))
4508 return find_split_point (&SUBREG_REG (x
), insn
, false);
4512 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4513 using LO_SUM and HIGH. */
4514 if (GET_CODE (XEXP (x
, 0)) == CONST
4515 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4517 enum machine_mode address_mode
= get_address_mode (x
);
4520 gen_rtx_LO_SUM (address_mode
,
4521 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4523 return &XEXP (XEXP (x
, 0), 0);
4527 /* If we have a PLUS whose second operand is a constant and the
4528 address is not valid, perhaps will can split it up using
4529 the machine-specific way to split large constants. We use
4530 the first pseudo-reg (one of the virtual regs) as a placeholder;
4531 it will not remain in the result. */
4532 if (GET_CODE (XEXP (x
, 0)) == PLUS
4533 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4534 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4535 MEM_ADDR_SPACE (x
)))
4537 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4538 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4542 /* This should have produced two insns, each of which sets our
4543 placeholder. If the source of the second is a valid address,
4544 we can make put both sources together and make a split point
4548 && NEXT_INSN (seq
) != NULL_RTX
4549 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4550 && NONJUMP_INSN_P (seq
)
4551 && GET_CODE (PATTERN (seq
)) == SET
4552 && SET_DEST (PATTERN (seq
)) == reg
4553 && ! reg_mentioned_p (reg
,
4554 SET_SRC (PATTERN (seq
)))
4555 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4556 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4557 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4558 && memory_address_addr_space_p
4559 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4560 MEM_ADDR_SPACE (x
)))
4562 rtx src1
= SET_SRC (PATTERN (seq
));
4563 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4565 /* Replace the placeholder in SRC2 with SRC1. If we can
4566 find where in SRC2 it was placed, that can become our
4567 split point and we can replace this address with SRC2.
4568 Just try two obvious places. */
4570 src2
= replace_rtx (src2
, reg
, src1
);
4572 if (XEXP (src2
, 0) == src1
)
4573 split
= &XEXP (src2
, 0);
4574 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4575 && XEXP (XEXP (src2
, 0), 0) == src1
)
4576 split
= &XEXP (XEXP (src2
, 0), 0);
4580 SUBST (XEXP (x
, 0), src2
);
4585 /* If that didn't work, perhaps the first operand is complex and
4586 needs to be computed separately, so make a split point there.
4587 This will occur on machines that just support REG + CONST
4588 and have a constant moved through some previous computation. */
4590 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4591 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4592 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4593 return &XEXP (XEXP (x
, 0), 0);
4596 /* If we have a PLUS whose first operand is complex, try computing it
4597 separately by making a split there. */
4598 if (GET_CODE (XEXP (x
, 0)) == PLUS
4599 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4601 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4602 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4603 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4604 return &XEXP (XEXP (x
, 0), 0);
4609 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4610 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4611 we need to put the operand into a register. So split at that
4614 if (SET_DEST (x
) == cc0_rtx
4615 && GET_CODE (SET_SRC (x
)) != COMPARE
4616 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4617 && !OBJECT_P (SET_SRC (x
))
4618 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4619 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4620 return &SET_SRC (x
);
4623 /* See if we can split SET_SRC as it stands. */
4624 split
= find_split_point (&SET_SRC (x
), insn
, true);
4625 if (split
&& split
!= &SET_SRC (x
))
4628 /* See if we can split SET_DEST as it stands. */
4629 split
= find_split_point (&SET_DEST (x
), insn
, false);
4630 if (split
&& split
!= &SET_DEST (x
))
4633 /* See if this is a bitfield assignment with everything constant. If
4634 so, this is an IOR of an AND, so split it into that. */
4635 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4636 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4637 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4638 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4639 && CONST_INT_P (SET_SRC (x
))
4640 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4641 + INTVAL (XEXP (SET_DEST (x
), 2)))
4642 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4643 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4645 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4646 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4647 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4648 rtx dest
= XEXP (SET_DEST (x
), 0);
4649 enum machine_mode mode
= GET_MODE (dest
);
4650 unsigned HOST_WIDE_INT mask
4651 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4654 if (BITS_BIG_ENDIAN
)
4655 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4657 or_mask
= gen_int_mode (src
<< pos
, mode
);
4660 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4663 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4665 simplify_gen_binary (IOR
, mode
,
4666 simplify_gen_binary (AND
, mode
,
4671 SUBST (SET_DEST (x
), dest
);
4673 split
= find_split_point (&SET_SRC (x
), insn
, true);
4674 if (split
&& split
!= &SET_SRC (x
))
4678 /* Otherwise, see if this is an operation that we can split into two.
4679 If so, try to split that. */
4680 code
= GET_CODE (SET_SRC (x
));
4685 /* If we are AND'ing with a large constant that is only a single
4686 bit and the result is only being used in a context where we
4687 need to know if it is zero or nonzero, replace it with a bit
4688 extraction. This will avoid the large constant, which might
4689 have taken more than one insn to make. If the constant were
4690 not a valid argument to the AND but took only one insn to make,
4691 this is no worse, but if it took more than one insn, it will
4694 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4695 && REG_P (XEXP (SET_SRC (x
), 0))
4696 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4697 && REG_P (SET_DEST (x
))
4698 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4699 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4700 && XEXP (*split
, 0) == SET_DEST (x
)
4701 && XEXP (*split
, 1) == const0_rtx
)
4703 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4704 XEXP (SET_SRC (x
), 0),
4705 pos
, NULL_RTX
, 1, 1, 0, 0);
4706 if (extraction
!= 0)
4708 SUBST (SET_SRC (x
), extraction
);
4709 return find_split_point (loc
, insn
, false);
4715 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4716 is known to be on, this can be converted into a NEG of a shift. */
4717 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4718 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4719 && 1 <= (pos
= exact_log2
4720 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4721 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4723 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4727 gen_rtx_LSHIFTRT (mode
,
4728 XEXP (SET_SRC (x
), 0),
4731 split
= find_split_point (&SET_SRC (x
), insn
, true);
4732 if (split
&& split
!= &SET_SRC (x
))
4738 inner
= XEXP (SET_SRC (x
), 0);
4740 /* We can't optimize if either mode is a partial integer
4741 mode as we don't know how many bits are significant
4743 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4744 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4748 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4754 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4755 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4757 inner
= XEXP (SET_SRC (x
), 0);
4758 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4759 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4761 if (BITS_BIG_ENDIAN
)
4762 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4763 unsignedp
= (code
== ZERO_EXTRACT
);
4772 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4774 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4776 /* For unsigned, we have a choice of a shift followed by an
4777 AND or two shifts. Use two shifts for field sizes where the
4778 constant might be too large. We assume here that we can
4779 always at least get 8-bit constants in an AND insn, which is
4780 true for every current RISC. */
4782 if (unsignedp
&& len
<= 8)
4784 unsigned HOST_WIDE_INT mask
4785 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4789 (mode
, gen_lowpart (mode
, inner
),
4791 gen_int_mode (mask
, mode
)));
4793 split
= find_split_point (&SET_SRC (x
), insn
, true);
4794 if (split
&& split
!= &SET_SRC (x
))
4801 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4802 gen_rtx_ASHIFT (mode
,
4803 gen_lowpart (mode
, inner
),
4804 GEN_INT (GET_MODE_PRECISION (mode
)
4806 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4808 split
= find_split_point (&SET_SRC (x
), insn
, true);
4809 if (split
&& split
!= &SET_SRC (x
))
4814 /* See if this is a simple operation with a constant as the second
4815 operand. It might be that this constant is out of range and hence
4816 could be used as a split point. */
4817 if (BINARY_P (SET_SRC (x
))
4818 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4819 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4820 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4821 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4822 return &XEXP (SET_SRC (x
), 1);
4824 /* Finally, see if this is a simple operation with its first operand
4825 not in a register. The operation might require this operand in a
4826 register, so return it as a split point. We can always do this
4827 because if the first operand were another operation, we would have
4828 already found it as a split point. */
4829 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4830 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4831 return &XEXP (SET_SRC (x
), 0);
4837 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4838 it is better to write this as (not (ior A B)) so we can split it.
4839 Similarly for IOR. */
4840 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4843 gen_rtx_NOT (GET_MODE (x
),
4844 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4846 XEXP (XEXP (x
, 0), 0),
4847 XEXP (XEXP (x
, 1), 0))));
4848 return find_split_point (loc
, insn
, set_src
);
4851 /* Many RISC machines have a large set of logical insns. If the
4852 second operand is a NOT, put it first so we will try to split the
4853 other operand first. */
4854 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4856 rtx tem
= XEXP (x
, 0);
4857 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4858 SUBST (XEXP (x
, 1), tem
);
4864 /* Canonicalization can produce (minus A (mult B C)), where C is a
4865 constant. It may be better to try splitting (plus (mult B -C) A)
4866 instead if this isn't a multiply by a power of two. */
4867 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4868 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4869 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4871 enum machine_mode mode
= GET_MODE (x
);
4872 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4873 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4874 SUBST (*loc
, gen_rtx_PLUS (mode
,
4876 XEXP (XEXP (x
, 1), 0),
4877 gen_int_mode (other_int
,
4880 return find_split_point (loc
, insn
, set_src
);
4883 /* Split at a multiply-accumulate instruction. However if this is
4884 the SET_SRC, we likely do not have such an instruction and it's
4885 worthless to try this split. */
4886 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4893 /* Otherwise, select our actions depending on our rtx class. */
4894 switch (GET_RTX_CLASS (code
))
4896 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4898 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4901 /* ... fall through ... */
4903 case RTX_COMM_ARITH
:
4905 case RTX_COMM_COMPARE
:
4906 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4909 /* ... fall through ... */
4911 /* Some machines have (and (shift ...) ...) insns. If X is not
4912 an AND, but XEXP (X, 0) is, use it as our split point. */
4913 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4914 return &XEXP (x
, 0);
4916 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4922 /* Otherwise, we don't have a split point. */
4927 /* Throughout X, replace FROM with TO, and return the result.
4928 The result is TO if X is FROM;
4929 otherwise the result is X, but its contents may have been modified.
4930 If they were modified, a record was made in undobuf so that
4931 undo_all will (among other things) return X to its original state.
4933 If the number of changes necessary is too much to record to undo,
4934 the excess changes are not made, so the result is invalid.
4935 The changes already made can still be undone.
4936 undobuf.num_undo is incremented for such changes, so by testing that
4937 the caller can tell whether the result is valid.
4939 `n_occurrences' is incremented each time FROM is replaced.
4941 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4943 IN_COND is nonzero if we are at the top level of a condition.
4945 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4946 by copying if `n_occurrences' is nonzero. */
4949 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4951 enum rtx_code code
= GET_CODE (x
);
4952 enum machine_mode op0_mode
= VOIDmode
;
4957 /* Two expressions are equal if they are identical copies of a shared
4958 RTX or if they are both registers with the same register number
4961 #define COMBINE_RTX_EQUAL_P(X,Y) \
4963 || (REG_P (X) && REG_P (Y) \
4964 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4966 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4969 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4972 /* If X and FROM are the same register but different modes, they
4973 will not have been seen as equal above. However, the log links code
4974 will make a LOG_LINKS entry for that case. If we do nothing, we
4975 will try to rerecognize our original insn and, when it succeeds,
4976 we will delete the feeding insn, which is incorrect.
4978 So force this insn not to match in this (rare) case. */
4979 if (! in_dest
&& code
== REG
&& REG_P (from
)
4980 && reg_overlap_mentioned_p (x
, from
))
4981 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4983 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4984 of which may contain things that can be combined. */
4985 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4988 /* It is possible to have a subexpression appear twice in the insn.
4989 Suppose that FROM is a register that appears within TO.
4990 Then, after that subexpression has been scanned once by `subst',
4991 the second time it is scanned, TO may be found. If we were
4992 to scan TO here, we would find FROM within it and create a
4993 self-referent rtl structure which is completely wrong. */
4994 if (COMBINE_RTX_EQUAL_P (x
, to
))
4997 /* Parallel asm_operands need special attention because all of the
4998 inputs are shared across the arms. Furthermore, unsharing the
4999 rtl results in recognition failures. Failure to handle this case
5000 specially can result in circular rtl.
5002 Solve this by doing a normal pass across the first entry of the
5003 parallel, and only processing the SET_DESTs of the subsequent
5006 if (code
== PARALLEL
5007 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5008 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5010 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5012 /* If this substitution failed, this whole thing fails. */
5013 if (GET_CODE (new_rtx
) == CLOBBER
5014 && XEXP (new_rtx
, 0) == const0_rtx
)
5017 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5019 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5021 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5024 && GET_CODE (dest
) != CC0
5025 && GET_CODE (dest
) != PC
)
5027 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5029 /* If this substitution failed, this whole thing fails. */
5030 if (GET_CODE (new_rtx
) == CLOBBER
5031 && XEXP (new_rtx
, 0) == const0_rtx
)
5034 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5040 len
= GET_RTX_LENGTH (code
);
5041 fmt
= GET_RTX_FORMAT (code
);
5043 /* We don't need to process a SET_DEST that is a register, CC0,
5044 or PC, so set up to skip this common case. All other cases
5045 where we want to suppress replacing something inside a
5046 SET_SRC are handled via the IN_DEST operand. */
5048 && (REG_P (SET_DEST (x
))
5049 || GET_CODE (SET_DEST (x
)) == CC0
5050 || GET_CODE (SET_DEST (x
)) == PC
))
5053 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5056 op0_mode
= GET_MODE (XEXP (x
, 0));
5058 for (i
= 0; i
< len
; i
++)
5063 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5065 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5067 new_rtx
= (unique_copy
&& n_occurrences
5068 ? copy_rtx (to
) : to
);
5073 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5076 /* If this substitution failed, this whole thing
5078 if (GET_CODE (new_rtx
) == CLOBBER
5079 && XEXP (new_rtx
, 0) == const0_rtx
)
5083 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5086 else if (fmt
[i
] == 'e')
5088 /* If this is a register being set, ignore it. */
5089 new_rtx
= XEXP (x
, i
);
5092 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5094 || code
== STRICT_LOW_PART
))
5097 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5099 /* In general, don't install a subreg involving two
5100 modes not tieable. It can worsen register
5101 allocation, and can even make invalid reload
5102 insns, since the reg inside may need to be copied
5103 from in the outside mode, and that may be invalid
5104 if it is an fp reg copied in integer mode.
5106 We allow two exceptions to this: It is valid if
5107 it is inside another SUBREG and the mode of that
5108 SUBREG and the mode of the inside of TO is
5109 tieable and it is valid if X is a SET that copies
5112 if (GET_CODE (to
) == SUBREG
5113 && ! MODES_TIEABLE_P (GET_MODE (to
),
5114 GET_MODE (SUBREG_REG (to
)))
5115 && ! (code
== SUBREG
5116 && MODES_TIEABLE_P (GET_MODE (x
),
5117 GET_MODE (SUBREG_REG (to
))))
5119 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5122 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5126 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5127 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5130 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5132 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5136 /* If we are in a SET_DEST, suppress most cases unless we
5137 have gone inside a MEM, in which case we want to
5138 simplify the address. We assume here that things that
5139 are actually part of the destination have their inner
5140 parts in the first expression. This is true for SUBREG,
5141 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5142 things aside from REG and MEM that should appear in a
5144 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5146 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5147 || code
== ZERO_EXTRACT
))
5150 code
== IF_THEN_ELSE
&& i
== 0,
5153 /* If we found that we will have to reject this combination,
5154 indicate that by returning the CLOBBER ourselves, rather than
5155 an expression containing it. This will speed things up as
5156 well as prevent accidents where two CLOBBERs are considered
5157 to be equal, thus producing an incorrect simplification. */
5159 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5162 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5164 enum machine_mode mode
= GET_MODE (x
);
5166 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5167 GET_MODE (SUBREG_REG (x
)),
5170 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5172 else if (CONST_SCALAR_INT_P (new_rtx
)
5173 && GET_CODE (x
) == ZERO_EXTEND
)
5175 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5176 new_rtx
, GET_MODE (XEXP (x
, 0)));
5180 SUBST (XEXP (x
, i
), new_rtx
);
5185 /* Check if we are loading something from the constant pool via float
5186 extension; in this case we would undo compress_float_constant
5187 optimization and degenerate constant load to an immediate value. */
5188 if (GET_CODE (x
) == FLOAT_EXTEND
5189 && MEM_P (XEXP (x
, 0))
5190 && MEM_READONLY_P (XEXP (x
, 0)))
5192 rtx tmp
= avoid_constant_pool_reference (x
);
5197 /* Try to simplify X. If the simplification changed the code, it is likely
5198 that further simplification will help, so loop, but limit the number
5199 of repetitions that will be performed. */
5201 for (i
= 0; i
< 4; i
++)
5203 /* If X is sufficiently simple, don't bother trying to do anything
5205 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5206 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5208 if (GET_CODE (x
) == code
)
5211 code
= GET_CODE (x
);
5213 /* We no longer know the original mode of operand 0 since we
5214 have changed the form of X) */
5215 op0_mode
= VOIDmode
;
5221 /* Simplify X, a piece of RTL. We just operate on the expression at the
5222 outer level; call `subst' to simplify recursively. Return the new
5225 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5226 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5230 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5233 enum rtx_code code
= GET_CODE (x
);
5234 enum machine_mode mode
= GET_MODE (x
);
5238 /* If this is a commutative operation, put a constant last and a complex
5239 expression first. We don't need to do this for comparisons here. */
5240 if (COMMUTATIVE_ARITH_P (x
)
5241 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5244 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5245 SUBST (XEXP (x
, 1), temp
);
5248 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5249 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5250 things. Check for cases where both arms are testing the same
5253 Don't do anything if all operands are very simple. */
5256 && ((!OBJECT_P (XEXP (x
, 0))
5257 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5258 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5259 || (!OBJECT_P (XEXP (x
, 1))
5260 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5261 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5263 && (!OBJECT_P (XEXP (x
, 0))
5264 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5265 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5267 rtx cond
, true_rtx
, false_rtx
;
5269 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5271 /* If everything is a comparison, what we have is highly unlikely
5272 to be simpler, so don't use it. */
5273 && ! (COMPARISON_P (x
)
5274 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5276 rtx cop1
= const0_rtx
;
5277 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5279 if (cond_code
== NE
&& COMPARISON_P (cond
))
5282 /* Simplify the alternative arms; this may collapse the true and
5283 false arms to store-flag values. Be careful to use copy_rtx
5284 here since true_rtx or false_rtx might share RTL with x as a
5285 result of the if_then_else_cond call above. */
5286 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5287 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5289 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5290 is unlikely to be simpler. */
5291 if (general_operand (true_rtx
, VOIDmode
)
5292 && general_operand (false_rtx
, VOIDmode
))
5294 enum rtx_code reversed
;
5296 /* Restarting if we generate a store-flag expression will cause
5297 us to loop. Just drop through in this case. */
5299 /* If the result values are STORE_FLAG_VALUE and zero, we can
5300 just make the comparison operation. */
5301 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5302 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5304 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5305 && ((reversed
= reversed_comparison_code_parts
5306 (cond_code
, cond
, cop1
, NULL
))
5308 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5311 /* Likewise, we can make the negate of a comparison operation
5312 if the result values are - STORE_FLAG_VALUE and zero. */
5313 else if (CONST_INT_P (true_rtx
)
5314 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5315 && false_rtx
== const0_rtx
)
5316 x
= simplify_gen_unary (NEG
, mode
,
5317 simplify_gen_relational (cond_code
,
5321 else if (CONST_INT_P (false_rtx
)
5322 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5323 && true_rtx
== const0_rtx
5324 && ((reversed
= reversed_comparison_code_parts
5325 (cond_code
, cond
, cop1
, NULL
))
5327 x
= simplify_gen_unary (NEG
, mode
,
5328 simplify_gen_relational (reversed
,
5333 return gen_rtx_IF_THEN_ELSE (mode
,
5334 simplify_gen_relational (cond_code
,
5339 true_rtx
, false_rtx
);
5341 code
= GET_CODE (x
);
5342 op0_mode
= VOIDmode
;
5347 /* Try to fold this expression in case we have constants that weren't
5350 switch (GET_RTX_CLASS (code
))
5353 if (op0_mode
== VOIDmode
)
5354 op0_mode
= GET_MODE (XEXP (x
, 0));
5355 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5358 case RTX_COMM_COMPARE
:
5360 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5361 if (cmp_mode
== VOIDmode
)
5363 cmp_mode
= GET_MODE (XEXP (x
, 1));
5364 if (cmp_mode
== VOIDmode
)
5365 cmp_mode
= op0_mode
;
5367 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5368 XEXP (x
, 0), XEXP (x
, 1));
5371 case RTX_COMM_ARITH
:
5373 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5375 case RTX_BITFIELD_OPS
:
5377 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5378 XEXP (x
, 1), XEXP (x
, 2));
5387 code
= GET_CODE (temp
);
5388 op0_mode
= VOIDmode
;
5389 mode
= GET_MODE (temp
);
5392 /* First see if we can apply the inverse distributive law. */
5393 if (code
== PLUS
|| code
== MINUS
5394 || code
== AND
|| code
== IOR
|| code
== XOR
)
5396 x
= apply_distributive_law (x
);
5397 code
= GET_CODE (x
);
5398 op0_mode
= VOIDmode
;
5401 /* If CODE is an associative operation not otherwise handled, see if we
5402 can associate some operands. This can win if they are constants or
5403 if they are logically related (i.e. (a & b) & a). */
5404 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5405 || code
== AND
|| code
== IOR
|| code
== XOR
5406 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5407 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5408 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5410 if (GET_CODE (XEXP (x
, 0)) == code
)
5412 rtx other
= XEXP (XEXP (x
, 0), 0);
5413 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5414 rtx inner_op1
= XEXP (x
, 1);
5417 /* Make sure we pass the constant operand if any as the second
5418 one if this is a commutative operation. */
5419 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5421 rtx tem
= inner_op0
;
5422 inner_op0
= inner_op1
;
5425 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5426 : code
== DIV
? MULT
5428 mode
, inner_op0
, inner_op1
);
5430 /* For commutative operations, try the other pair if that one
5432 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5434 other
= XEXP (XEXP (x
, 0), 1);
5435 inner
= simplify_binary_operation (code
, mode
,
5436 XEXP (XEXP (x
, 0), 0),
5441 return simplify_gen_binary (code
, mode
, other
, inner
);
5445 /* A little bit of algebraic simplification here. */
5449 /* Ensure that our address has any ASHIFTs converted to MULT in case
5450 address-recognizing predicates are called later. */
5451 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5452 SUBST (XEXP (x
, 0), temp
);
5456 if (op0_mode
== VOIDmode
)
5457 op0_mode
= GET_MODE (SUBREG_REG (x
));
5459 /* See if this can be moved to simplify_subreg. */
5460 if (CONSTANT_P (SUBREG_REG (x
))
5461 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5462 /* Don't call gen_lowpart if the inner mode
5463 is VOIDmode and we cannot simplify it, as SUBREG without
5464 inner mode is invalid. */
5465 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5466 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5467 return gen_lowpart (mode
, SUBREG_REG (x
));
5469 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5473 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5478 /* If op is known to have all lower bits zero, the result is zero. */
5480 && SCALAR_INT_MODE_P (mode
)
5481 && SCALAR_INT_MODE_P (op0_mode
)
5482 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5483 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5484 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5485 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5486 & GET_MODE_MASK (mode
)) == 0)
5487 return CONST0_RTX (mode
);
5490 /* Don't change the mode of the MEM if that would change the meaning
5492 if (MEM_P (SUBREG_REG (x
))
5493 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5494 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5495 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5496 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5498 /* Note that we cannot do any narrowing for non-constants since
5499 we might have been counting on using the fact that some bits were
5500 zero. We now do this in the SET. */
5505 temp
= expand_compound_operation (XEXP (x
, 0));
5507 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5508 replaced by (lshiftrt X C). This will convert
5509 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5511 if (GET_CODE (temp
) == ASHIFTRT
5512 && CONST_INT_P (XEXP (temp
, 1))
5513 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5514 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5515 INTVAL (XEXP (temp
, 1)));
5517 /* If X has only a single bit that might be nonzero, say, bit I, convert
5518 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5519 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5520 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5521 or a SUBREG of one since we'd be making the expression more
5522 complex if it was just a register. */
5525 && ! (GET_CODE (temp
) == SUBREG
5526 && REG_P (SUBREG_REG (temp
)))
5527 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5529 rtx temp1
= simplify_shift_const
5530 (NULL_RTX
, ASHIFTRT
, mode
,
5531 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5532 GET_MODE_PRECISION (mode
) - 1 - i
),
5533 GET_MODE_PRECISION (mode
) - 1 - i
);
5535 /* If all we did was surround TEMP with the two shifts, we
5536 haven't improved anything, so don't use it. Otherwise,
5537 we are better off with TEMP1. */
5538 if (GET_CODE (temp1
) != ASHIFTRT
5539 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5540 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5546 /* We can't handle truncation to a partial integer mode here
5547 because we don't know the real bitsize of the partial
5549 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5552 if (HWI_COMPUTABLE_MODE_P (mode
))
5554 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5555 GET_MODE_MASK (mode
), 0));
5557 /* We can truncate a constant value and return it. */
5558 if (CONST_INT_P (XEXP (x
, 0)))
5559 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5561 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5562 whose value is a comparison can be replaced with a subreg if
5563 STORE_FLAG_VALUE permits. */
5564 if (HWI_COMPUTABLE_MODE_P (mode
)
5565 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5566 && (temp
= get_last_value (XEXP (x
, 0)))
5567 && COMPARISON_P (temp
))
5568 return gen_lowpart (mode
, XEXP (x
, 0));
5572 /* (const (const X)) can become (const X). Do it this way rather than
5573 returning the inner CONST since CONST can be shared with a
5575 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5576 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5581 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5582 can add in an offset. find_split_point will split this address up
5583 again if it doesn't match. */
5584 if (GET_CODE (XEXP (x
, 0)) == HIGH
5585 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5591 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5592 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5593 bit-field and can be replaced by either a sign_extend or a
5594 sign_extract. The `and' may be a zero_extend and the two
5595 <c>, -<c> constants may be reversed. */
5596 if (GET_CODE (XEXP (x
, 0)) == XOR
5597 && CONST_INT_P (XEXP (x
, 1))
5598 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5599 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5600 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5601 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5602 && HWI_COMPUTABLE_MODE_P (mode
)
5603 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5604 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5605 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5606 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5607 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5608 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5609 == (unsigned int) i
+ 1))))
5610 return simplify_shift_const
5611 (NULL_RTX
, ASHIFTRT
, mode
,
5612 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5613 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5614 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5615 GET_MODE_PRECISION (mode
) - (i
+ 1));
5617 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5618 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5619 the bitsize of the mode - 1. This allows simplification of
5620 "a = (b & 8) == 0;" */
5621 if (XEXP (x
, 1) == constm1_rtx
5622 && !REG_P (XEXP (x
, 0))
5623 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5624 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5625 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5626 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5627 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5628 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5629 GET_MODE_PRECISION (mode
) - 1),
5630 GET_MODE_PRECISION (mode
) - 1);
5632 /* If we are adding two things that have no bits in common, convert
5633 the addition into an IOR. This will often be further simplified,
5634 for example in cases like ((a & 1) + (a & 2)), which can
5637 if (HWI_COMPUTABLE_MODE_P (mode
)
5638 && (nonzero_bits (XEXP (x
, 0), mode
)
5639 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5641 /* Try to simplify the expression further. */
5642 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5643 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5645 /* If we could, great. If not, do not go ahead with the IOR
5646 replacement, since PLUS appears in many special purpose
5647 address arithmetic instructions. */
5648 if (GET_CODE (temp
) != CLOBBER
5649 && (GET_CODE (temp
) != IOR
5650 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5651 || XEXP (temp
, 1) != XEXP (x
, 1))
5652 && (XEXP (temp
, 0) != XEXP (x
, 1)
5653 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5659 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5660 (and <foo> (const_int pow2-1)) */
5661 if (GET_CODE (XEXP (x
, 1)) == AND
5662 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5663 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5664 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5665 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5666 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5670 /* If we have (mult (plus A B) C), apply the distributive law and then
5671 the inverse distributive law to see if things simplify. This
5672 occurs mostly in addresses, often when unrolling loops. */
5674 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5676 rtx result
= distribute_and_simplify_rtx (x
, 0);
5681 /* Try simplify a*(b/c) as (a*b)/c. */
5682 if (FLOAT_MODE_P (mode
) && flag_associative_math
5683 && GET_CODE (XEXP (x
, 0)) == DIV
)
5685 rtx tem
= simplify_binary_operation (MULT
, mode
,
5686 XEXP (XEXP (x
, 0), 0),
5689 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5694 /* If this is a divide by a power of two, treat it as a shift if
5695 its first operand is a shift. */
5696 if (CONST_INT_P (XEXP (x
, 1))
5697 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5698 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5699 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5700 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5701 || GET_CODE (XEXP (x
, 0)) == ROTATE
5702 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5703 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5707 case GT
: case GTU
: case GE
: case GEU
:
5708 case LT
: case LTU
: case LE
: case LEU
:
5709 case UNEQ
: case LTGT
:
5710 case UNGT
: case UNGE
:
5711 case UNLT
: case UNLE
:
5712 case UNORDERED
: case ORDERED
:
5713 /* If the first operand is a condition code, we can't do anything
5715 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5716 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5717 && ! CC0_P (XEXP (x
, 0))))
5719 rtx op0
= XEXP (x
, 0);
5720 rtx op1
= XEXP (x
, 1);
5721 enum rtx_code new_code
;
5723 if (GET_CODE (op0
) == COMPARE
)
5724 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5726 /* Simplify our comparison, if possible. */
5727 new_code
= simplify_comparison (code
, &op0
, &op1
);
5729 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5730 if only the low-order bit is possibly nonzero in X (such as when
5731 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5732 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5733 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5736 Remove any ZERO_EXTRACT we made when thinking this was a
5737 comparison. It may now be simpler to use, e.g., an AND. If a
5738 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5739 the call to make_compound_operation in the SET case.
5741 Don't apply these optimizations if the caller would
5742 prefer a comparison rather than a value.
5743 E.g., for the condition in an IF_THEN_ELSE most targets need
5744 an explicit comparison. */
5749 else if (STORE_FLAG_VALUE
== 1
5750 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5751 && op1
== const0_rtx
5752 && mode
== GET_MODE (op0
)
5753 && nonzero_bits (op0
, mode
) == 1)
5754 return gen_lowpart (mode
,
5755 expand_compound_operation (op0
));
5757 else if (STORE_FLAG_VALUE
== 1
5758 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5759 && op1
== const0_rtx
5760 && mode
== GET_MODE (op0
)
5761 && (num_sign_bit_copies (op0
, mode
)
5762 == GET_MODE_PRECISION (mode
)))
5764 op0
= expand_compound_operation (op0
);
5765 return simplify_gen_unary (NEG
, mode
,
5766 gen_lowpart (mode
, op0
),
5770 else if (STORE_FLAG_VALUE
== 1
5771 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5772 && op1
== const0_rtx
5773 && mode
== GET_MODE (op0
)
5774 && nonzero_bits (op0
, mode
) == 1)
5776 op0
= expand_compound_operation (op0
);
5777 return simplify_gen_binary (XOR
, mode
,
5778 gen_lowpart (mode
, op0
),
5782 else if (STORE_FLAG_VALUE
== 1
5783 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5784 && op1
== const0_rtx
5785 && mode
== GET_MODE (op0
)
5786 && (num_sign_bit_copies (op0
, mode
)
5787 == GET_MODE_PRECISION (mode
)))
5789 op0
= expand_compound_operation (op0
);
5790 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5793 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5798 else if (STORE_FLAG_VALUE
== -1
5799 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5800 && op1
== const0_rtx
5801 && (num_sign_bit_copies (op0
, mode
)
5802 == GET_MODE_PRECISION (mode
)))
5803 return gen_lowpart (mode
,
5804 expand_compound_operation (op0
));
5806 else if (STORE_FLAG_VALUE
== -1
5807 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5808 && op1
== const0_rtx
5809 && mode
== GET_MODE (op0
)
5810 && nonzero_bits (op0
, mode
) == 1)
5812 op0
= expand_compound_operation (op0
);
5813 return simplify_gen_unary (NEG
, mode
,
5814 gen_lowpart (mode
, op0
),
5818 else if (STORE_FLAG_VALUE
== -1
5819 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5820 && op1
== const0_rtx
5821 && mode
== GET_MODE (op0
)
5822 && (num_sign_bit_copies (op0
, mode
)
5823 == GET_MODE_PRECISION (mode
)))
5825 op0
= expand_compound_operation (op0
);
5826 return simplify_gen_unary (NOT
, mode
,
5827 gen_lowpart (mode
, op0
),
5831 /* If X is 0/1, (eq X 0) is X-1. */
5832 else if (STORE_FLAG_VALUE
== -1
5833 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5834 && op1
== const0_rtx
5835 && mode
== GET_MODE (op0
)
5836 && nonzero_bits (op0
, mode
) == 1)
5838 op0
= expand_compound_operation (op0
);
5839 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5842 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5843 one bit that might be nonzero, we can convert (ne x 0) to
5844 (ashift x c) where C puts the bit in the sign bit. Remove any
5845 AND with STORE_FLAG_VALUE when we are done, since we are only
5846 going to test the sign bit. */
5847 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5848 && HWI_COMPUTABLE_MODE_P (mode
)
5849 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5850 && op1
== const0_rtx
5851 && mode
== GET_MODE (op0
)
5852 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5854 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5855 expand_compound_operation (op0
),
5856 GET_MODE_PRECISION (mode
) - 1 - i
);
5857 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5863 /* If the code changed, return a whole new comparison.
5864 We also need to avoid using SUBST in cases where
5865 simplify_comparison has widened a comparison with a CONST_INT,
5866 since in that case the wider CONST_INT may fail the sanity
5867 checks in do_SUBST. */
5868 if (new_code
!= code
5869 || (CONST_INT_P (op1
)
5870 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5871 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5872 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5874 /* Otherwise, keep this operation, but maybe change its operands.
5875 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5876 SUBST (XEXP (x
, 0), op0
);
5877 SUBST (XEXP (x
, 1), op1
);
5882 return simplify_if_then_else (x
);
5888 /* If we are processing SET_DEST, we are done. */
5892 return expand_compound_operation (x
);
5895 return simplify_set (x
);
5899 return simplify_logical (x
);
5906 /* If this is a shift by a constant amount, simplify it. */
5907 if (CONST_INT_P (XEXP (x
, 1)))
5908 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5909 INTVAL (XEXP (x
, 1)));
5911 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5913 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5914 ((unsigned HOST_WIDE_INT
) 1
5915 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5927 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5930 simplify_if_then_else (rtx x
)
5932 enum machine_mode mode
= GET_MODE (x
);
5933 rtx cond
= XEXP (x
, 0);
5934 rtx true_rtx
= XEXP (x
, 1);
5935 rtx false_rtx
= XEXP (x
, 2);
5936 enum rtx_code true_code
= GET_CODE (cond
);
5937 int comparison_p
= COMPARISON_P (cond
);
5940 enum rtx_code false_code
;
5943 /* Simplify storing of the truth value. */
5944 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5945 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5946 XEXP (cond
, 0), XEXP (cond
, 1));
5948 /* Also when the truth value has to be reversed. */
5950 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5951 && (reversed
= reversed_comparison (cond
, mode
)))
5954 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5955 in it is being compared against certain values. Get the true and false
5956 comparisons and see if that says anything about the value of each arm. */
5959 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5961 && REG_P (XEXP (cond
, 0)))
5964 rtx from
= XEXP (cond
, 0);
5965 rtx true_val
= XEXP (cond
, 1);
5966 rtx false_val
= true_val
;
5969 /* If FALSE_CODE is EQ, swap the codes and arms. */
5971 if (false_code
== EQ
)
5973 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5974 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5977 /* If we are comparing against zero and the expression being tested has
5978 only a single bit that might be nonzero, that is its value when it is
5979 not equal to zero. Similarly if it is known to be -1 or 0. */
5981 if (true_code
== EQ
&& true_val
== const0_rtx
5982 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5985 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5987 else if (true_code
== EQ
&& true_val
== const0_rtx
5988 && (num_sign_bit_copies (from
, GET_MODE (from
))
5989 == GET_MODE_PRECISION (GET_MODE (from
))))
5992 false_val
= constm1_rtx
;
5995 /* Now simplify an arm if we know the value of the register in the
5996 branch and it is used in the arm. Be careful due to the potential
5997 of locally-shared RTL. */
5999 if (reg_mentioned_p (from
, true_rtx
))
6000 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6002 pc_rtx
, pc_rtx
, 0, 0, 0);
6003 if (reg_mentioned_p (from
, false_rtx
))
6004 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6006 pc_rtx
, pc_rtx
, 0, 0, 0);
6008 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6009 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6011 true_rtx
= XEXP (x
, 1);
6012 false_rtx
= XEXP (x
, 2);
6013 true_code
= GET_CODE (cond
);
6016 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6017 reversed, do so to avoid needing two sets of patterns for
6018 subtract-and-branch insns. Similarly if we have a constant in the true
6019 arm, the false arm is the same as the first operand of the comparison, or
6020 the false arm is more complicated than the true arm. */
6023 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6024 && (true_rtx
== pc_rtx
6025 || (CONSTANT_P (true_rtx
)
6026 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6027 || true_rtx
== const0_rtx
6028 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6029 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6030 && !OBJECT_P (false_rtx
))
6031 || reg_mentioned_p (true_rtx
, false_rtx
)
6032 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6034 true_code
= reversed_comparison_code (cond
, NULL
);
6035 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6036 SUBST (XEXP (x
, 1), false_rtx
);
6037 SUBST (XEXP (x
, 2), true_rtx
);
6039 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6042 /* It is possible that the conditional has been simplified out. */
6043 true_code
= GET_CODE (cond
);
6044 comparison_p
= COMPARISON_P (cond
);
6047 /* If the two arms are identical, we don't need the comparison. */
6049 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6052 /* Convert a == b ? b : a to "a". */
6053 if (true_code
== EQ
&& ! side_effects_p (cond
)
6054 && !HONOR_NANS (mode
)
6055 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6056 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6058 else if (true_code
== NE
&& ! side_effects_p (cond
)
6059 && !HONOR_NANS (mode
)
6060 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6061 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6064 /* Look for cases where we have (abs x) or (neg (abs X)). */
6066 if (GET_MODE_CLASS (mode
) == MODE_INT
6068 && XEXP (cond
, 1) == const0_rtx
6069 && GET_CODE (false_rtx
) == NEG
6070 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6071 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6072 && ! side_effects_p (true_rtx
))
6077 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6081 simplify_gen_unary (NEG
, mode
,
6082 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6088 /* Look for MIN or MAX. */
6090 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6092 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6093 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6094 && ! side_effects_p (cond
))
6099 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6102 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6105 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6108 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6113 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6114 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6115 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6116 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6117 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6118 neither 1 or -1, but it isn't worth checking for. */
6120 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6122 && GET_MODE_CLASS (mode
) == MODE_INT
6123 && ! side_effects_p (x
))
6125 rtx t
= make_compound_operation (true_rtx
, SET
);
6126 rtx f
= make_compound_operation (false_rtx
, SET
);
6127 rtx cond_op0
= XEXP (cond
, 0);
6128 rtx cond_op1
= XEXP (cond
, 1);
6129 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6130 enum machine_mode m
= mode
;
6131 rtx z
= 0, c1
= NULL_RTX
;
6133 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6134 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6135 || GET_CODE (t
) == ASHIFT
6136 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6137 && rtx_equal_p (XEXP (t
, 0), f
))
6138 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6140 /* If an identity-zero op is commutative, check whether there
6141 would be a match if we swapped the operands. */
6142 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6143 || GET_CODE (t
) == XOR
)
6144 && rtx_equal_p (XEXP (t
, 1), f
))
6145 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6146 else if (GET_CODE (t
) == SIGN_EXTEND
6147 && (GET_CODE (XEXP (t
, 0)) == PLUS
6148 || GET_CODE (XEXP (t
, 0)) == MINUS
6149 || GET_CODE (XEXP (t
, 0)) == IOR
6150 || GET_CODE (XEXP (t
, 0)) == XOR
6151 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6152 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6153 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6154 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6155 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6156 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6157 && (num_sign_bit_copies (f
, GET_MODE (f
))
6159 (GET_MODE_PRECISION (mode
)
6160 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6162 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6163 extend_op
= SIGN_EXTEND
;
6164 m
= GET_MODE (XEXP (t
, 0));
6166 else if (GET_CODE (t
) == SIGN_EXTEND
6167 && (GET_CODE (XEXP (t
, 0)) == PLUS
6168 || GET_CODE (XEXP (t
, 0)) == IOR
6169 || GET_CODE (XEXP (t
, 0)) == XOR
)
6170 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6171 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6172 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6173 && (num_sign_bit_copies (f
, GET_MODE (f
))
6175 (GET_MODE_PRECISION (mode
)
6176 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6178 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6179 extend_op
= SIGN_EXTEND
;
6180 m
= GET_MODE (XEXP (t
, 0));
6182 else if (GET_CODE (t
) == ZERO_EXTEND
6183 && (GET_CODE (XEXP (t
, 0)) == PLUS
6184 || GET_CODE (XEXP (t
, 0)) == MINUS
6185 || GET_CODE (XEXP (t
, 0)) == IOR
6186 || GET_CODE (XEXP (t
, 0)) == XOR
6187 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6188 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6189 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6190 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6191 && HWI_COMPUTABLE_MODE_P (mode
)
6192 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6193 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6194 && ((nonzero_bits (f
, GET_MODE (f
))
6195 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6198 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6199 extend_op
= ZERO_EXTEND
;
6200 m
= GET_MODE (XEXP (t
, 0));
6202 else if (GET_CODE (t
) == ZERO_EXTEND
6203 && (GET_CODE (XEXP (t
, 0)) == PLUS
6204 || GET_CODE (XEXP (t
, 0)) == IOR
6205 || GET_CODE (XEXP (t
, 0)) == XOR
)
6206 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6207 && HWI_COMPUTABLE_MODE_P (mode
)
6208 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6209 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6210 && ((nonzero_bits (f
, GET_MODE (f
))
6211 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6214 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6215 extend_op
= ZERO_EXTEND
;
6216 m
= GET_MODE (XEXP (t
, 0));
6221 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6222 cond_op0
, cond_op1
),
6223 pc_rtx
, pc_rtx
, 0, 0, 0);
6224 temp
= simplify_gen_binary (MULT
, m
, temp
,
6225 simplify_gen_binary (MULT
, m
, c1
,
6227 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6228 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6230 if (extend_op
!= UNKNOWN
)
6231 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6237 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6238 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6239 negation of a single bit, we can convert this operation to a shift. We
6240 can actually do this more generally, but it doesn't seem worth it. */
6242 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6243 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6244 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6245 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6246 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6247 == GET_MODE_PRECISION (mode
))
6248 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6250 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6251 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6253 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6254 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6255 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6256 && GET_MODE (XEXP (cond
, 0)) == mode
6257 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6258 == nonzero_bits (XEXP (cond
, 0), mode
)
6259 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6260 return XEXP (cond
, 0);
6265 /* Simplify X, a SET expression. Return the new expression. */
6268 simplify_set (rtx x
)
6270 rtx src
= SET_SRC (x
);
6271 rtx dest
= SET_DEST (x
);
6272 enum machine_mode mode
6273 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6274 rtx_insn
*other_insn
;
6277 /* (set (pc) (return)) gets written as (return). */
6278 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6281 /* Now that we know for sure which bits of SRC we are using, see if we can
6282 simplify the expression for the object knowing that we only need the
6285 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6287 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6288 SUBST (SET_SRC (x
), src
);
6291 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6292 the comparison result and try to simplify it unless we already have used
6293 undobuf.other_insn. */
6294 if ((GET_MODE_CLASS (mode
) == MODE_CC
6295 || GET_CODE (src
) == COMPARE
6297 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6298 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6299 && COMPARISON_P (*cc_use
)
6300 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6302 enum rtx_code old_code
= GET_CODE (*cc_use
);
6303 enum rtx_code new_code
;
6305 int other_changed
= 0;
6306 rtx inner_compare
= NULL_RTX
;
6307 enum machine_mode compare_mode
= GET_MODE (dest
);
6309 if (GET_CODE (src
) == COMPARE
)
6311 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6312 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6314 inner_compare
= op0
;
6315 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6319 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6321 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6324 new_code
= old_code
;
6325 else if (!CONSTANT_P (tmp
))
6327 new_code
= GET_CODE (tmp
);
6328 op0
= XEXP (tmp
, 0);
6329 op1
= XEXP (tmp
, 1);
6333 rtx pat
= PATTERN (other_insn
);
6334 undobuf
.other_insn
= other_insn
;
6335 SUBST (*cc_use
, tmp
);
6337 /* Attempt to simplify CC user. */
6338 if (GET_CODE (pat
) == SET
)
6340 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6341 if (new_rtx
!= NULL_RTX
)
6342 SUBST (SET_SRC (pat
), new_rtx
);
6345 /* Convert X into a no-op move. */
6346 SUBST (SET_DEST (x
), pc_rtx
);
6347 SUBST (SET_SRC (x
), pc_rtx
);
6351 /* Simplify our comparison, if possible. */
6352 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6354 #ifdef SELECT_CC_MODE
6355 /* If this machine has CC modes other than CCmode, check to see if we
6356 need to use a different CC mode here. */
6357 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6358 compare_mode
= GET_MODE (op0
);
6359 else if (inner_compare
6360 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6361 && new_code
== old_code
6362 && op0
== XEXP (inner_compare
, 0)
6363 && op1
== XEXP (inner_compare
, 1))
6364 compare_mode
= GET_MODE (inner_compare
);
6366 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6369 /* If the mode changed, we have to change SET_DEST, the mode in the
6370 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6371 a hard register, just build new versions with the proper mode. If it
6372 is a pseudo, we lose unless it is only time we set the pseudo, in
6373 which case we can safely change its mode. */
6374 if (compare_mode
!= GET_MODE (dest
))
6376 if (can_change_dest_mode (dest
, 0, compare_mode
))
6378 unsigned int regno
= REGNO (dest
);
6381 if (regno
< FIRST_PSEUDO_REGISTER
)
6382 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6385 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6386 new_dest
= regno_reg_rtx
[regno
];
6389 SUBST (SET_DEST (x
), new_dest
);
6390 SUBST (XEXP (*cc_use
, 0), new_dest
);
6397 #endif /* SELECT_CC_MODE */
6399 /* If the code changed, we have to build a new comparison in
6400 undobuf.other_insn. */
6401 if (new_code
!= old_code
)
6403 int other_changed_previously
= other_changed
;
6404 unsigned HOST_WIDE_INT mask
;
6405 rtx old_cc_use
= *cc_use
;
6407 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6411 /* If the only change we made was to change an EQ into an NE or
6412 vice versa, OP0 has only one bit that might be nonzero, and OP1
6413 is zero, check if changing the user of the condition code will
6414 produce a valid insn. If it won't, we can keep the original code
6415 in that insn by surrounding our operation with an XOR. */
6417 if (((old_code
== NE
&& new_code
== EQ
)
6418 || (old_code
== EQ
&& new_code
== NE
))
6419 && ! other_changed_previously
&& op1
== const0_rtx
6420 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6421 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6423 rtx pat
= PATTERN (other_insn
), note
= 0;
6425 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6426 && ! check_asm_operands (pat
)))
6428 *cc_use
= old_cc_use
;
6431 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6439 undobuf
.other_insn
= other_insn
;
6441 /* Otherwise, if we didn't previously have a COMPARE in the
6442 correct mode, we need one. */
6443 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6445 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6448 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6450 SUBST (SET_SRC (x
), op0
);
6453 /* Otherwise, update the COMPARE if needed. */
6454 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6456 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6462 /* Get SET_SRC in a form where we have placed back any
6463 compound expressions. Then do the checks below. */
6464 src
= make_compound_operation (src
, SET
);
6465 SUBST (SET_SRC (x
), src
);
6468 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6469 and X being a REG or (subreg (reg)), we may be able to convert this to
6470 (set (subreg:m2 x) (op)).
6472 We can always do this if M1 is narrower than M2 because that means that
6473 we only care about the low bits of the result.
6475 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6476 perform a narrower operation than requested since the high-order bits will
6477 be undefined. On machine where it is defined, this transformation is safe
6478 as long as M1 and M2 have the same number of words. */
6480 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6481 && !OBJECT_P (SUBREG_REG (src
))
6482 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6484 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6485 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6486 #ifndef WORD_REGISTER_OPERATIONS
6487 && (GET_MODE_SIZE (GET_MODE (src
))
6488 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6490 #ifdef CANNOT_CHANGE_MODE_CLASS
6491 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6492 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6493 GET_MODE (SUBREG_REG (src
)),
6497 || (GET_CODE (dest
) == SUBREG
6498 && REG_P (SUBREG_REG (dest
)))))
6500 SUBST (SET_DEST (x
),
6501 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6503 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6505 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6509 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6512 && GET_CODE (src
) == SUBREG
6513 && subreg_lowpart_p (src
)
6514 && (GET_MODE_PRECISION (GET_MODE (src
))
6515 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6517 rtx inner
= SUBREG_REG (src
);
6518 enum machine_mode inner_mode
= GET_MODE (inner
);
6520 /* Here we make sure that we don't have a sign bit on. */
6521 if (val_signbit_known_clear_p (GET_MODE (src
),
6522 nonzero_bits (inner
, inner_mode
)))
6524 SUBST (SET_SRC (x
), inner
);
6530 #ifdef LOAD_EXTEND_OP
6531 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6532 would require a paradoxical subreg. Replace the subreg with a
6533 zero_extend to avoid the reload that would otherwise be required. */
6535 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6536 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6537 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6538 && SUBREG_BYTE (src
) == 0
6539 && paradoxical_subreg_p (src
)
6540 && MEM_P (SUBREG_REG (src
)))
6543 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6544 GET_MODE (src
), SUBREG_REG (src
)));
6550 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6551 are comparing an item known to be 0 or -1 against 0, use a logical
6552 operation instead. Check for one of the arms being an IOR of the other
6553 arm with some value. We compute three terms to be IOR'ed together. In
6554 practice, at most two will be nonzero. Then we do the IOR's. */
6556 if (GET_CODE (dest
) != PC
6557 && GET_CODE (src
) == IF_THEN_ELSE
6558 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6559 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6560 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6561 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6562 #ifdef HAVE_conditional_move
6563 && ! can_conditionally_move_p (GET_MODE (src
))
6565 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6566 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6567 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6568 && ! side_effects_p (src
))
6570 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6571 ? XEXP (src
, 1) : XEXP (src
, 2));
6572 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6573 ? XEXP (src
, 2) : XEXP (src
, 1));
6574 rtx term1
= const0_rtx
, term2
, term3
;
6576 if (GET_CODE (true_rtx
) == IOR
6577 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6578 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6579 else if (GET_CODE (true_rtx
) == IOR
6580 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6581 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6582 else if (GET_CODE (false_rtx
) == IOR
6583 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6584 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6585 else if (GET_CODE (false_rtx
) == IOR
6586 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6587 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6589 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6590 XEXP (XEXP (src
, 0), 0), true_rtx
);
6591 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6592 simplify_gen_unary (NOT
, GET_MODE (src
),
6593 XEXP (XEXP (src
, 0), 0),
6598 simplify_gen_binary (IOR
, GET_MODE (src
),
6599 simplify_gen_binary (IOR
, GET_MODE (src
),
6606 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6607 whole thing fail. */
6608 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6610 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6613 /* Convert this into a field assignment operation, if possible. */
6614 return make_field_assignment (x
);
6617 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6621 simplify_logical (rtx x
)
6623 enum machine_mode mode
= GET_MODE (x
);
6624 rtx op0
= XEXP (x
, 0);
6625 rtx op1
= XEXP (x
, 1);
6627 switch (GET_CODE (x
))
6630 /* We can call simplify_and_const_int only if we don't lose
6631 any (sign) bits when converting INTVAL (op1) to
6632 "unsigned HOST_WIDE_INT". */
6633 if (CONST_INT_P (op1
)
6634 && (HWI_COMPUTABLE_MODE_P (mode
)
6635 || INTVAL (op1
) > 0))
6637 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6638 if (GET_CODE (x
) != AND
)
6645 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6646 apply the distributive law and then the inverse distributive
6647 law to see if things simplify. */
6648 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6650 rtx result
= distribute_and_simplify_rtx (x
, 0);
6654 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6656 rtx result
= distribute_and_simplify_rtx (x
, 1);
6663 /* If we have (ior (and A B) C), apply the distributive law and then
6664 the inverse distributive law to see if things simplify. */
6666 if (GET_CODE (op0
) == AND
)
6668 rtx result
= distribute_and_simplify_rtx (x
, 0);
6673 if (GET_CODE (op1
) == AND
)
6675 rtx result
= distribute_and_simplify_rtx (x
, 1);
6688 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6689 operations" because they can be replaced with two more basic operations.
6690 ZERO_EXTEND is also considered "compound" because it can be replaced with
6691 an AND operation, which is simpler, though only one operation.
6693 The function expand_compound_operation is called with an rtx expression
6694 and will convert it to the appropriate shifts and AND operations,
6695 simplifying at each stage.
6697 The function make_compound_operation is called to convert an expression
6698 consisting of shifts and ANDs into the equivalent compound expression.
6699 It is the inverse of this function, loosely speaking. */
6702 expand_compound_operation (rtx x
)
6704 unsigned HOST_WIDE_INT pos
= 0, len
;
6706 unsigned int modewidth
;
6709 switch (GET_CODE (x
))
6714 /* We can't necessarily use a const_int for a multiword mode;
6715 it depends on implicitly extending the value.
6716 Since we don't know the right way to extend it,
6717 we can't tell whether the implicit way is right.
6719 Even for a mode that is no wider than a const_int,
6720 we can't win, because we need to sign extend one of its bits through
6721 the rest of it, and we don't know which bit. */
6722 if (CONST_INT_P (XEXP (x
, 0)))
6725 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6726 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6727 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6728 reloaded. If not for that, MEM's would very rarely be safe.
6730 Reject MODEs bigger than a word, because we might not be able
6731 to reference a two-register group starting with an arbitrary register
6732 (and currently gen_lowpart might crash for a SUBREG). */
6734 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6737 /* Reject MODEs that aren't scalar integers because turning vector
6738 or complex modes into shifts causes problems. */
6740 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6743 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6744 /* If the inner object has VOIDmode (the only way this can happen
6745 is if it is an ASM_OPERANDS), we can't do anything since we don't
6746 know how much masking to do. */
6755 /* ... fall through ... */
6758 /* If the operand is a CLOBBER, just return it. */
6759 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6762 if (!CONST_INT_P (XEXP (x
, 1))
6763 || !CONST_INT_P (XEXP (x
, 2))
6764 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6767 /* Reject MODEs that aren't scalar integers because turning vector
6768 or complex modes into shifts causes problems. */
6770 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6773 len
= INTVAL (XEXP (x
, 1));
6774 pos
= INTVAL (XEXP (x
, 2));
6776 /* This should stay within the object being extracted, fail otherwise. */
6777 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6780 if (BITS_BIG_ENDIAN
)
6781 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6788 /* Convert sign extension to zero extension, if we know that the high
6789 bit is not set, as this is easier to optimize. It will be converted
6790 back to cheaper alternative in make_extraction. */
6791 if (GET_CODE (x
) == SIGN_EXTEND
6792 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6793 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6794 & ~(((unsigned HOST_WIDE_INT
)
6795 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6799 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6800 rtx temp2
= expand_compound_operation (temp
);
6802 /* Make sure this is a profitable operation. */
6803 if (set_src_cost (x
, optimize_this_for_speed_p
)
6804 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6806 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6807 > set_src_cost (temp
, optimize_this_for_speed_p
))
6813 /* We can optimize some special cases of ZERO_EXTEND. */
6814 if (GET_CODE (x
) == ZERO_EXTEND
)
6816 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6817 know that the last value didn't have any inappropriate bits
6819 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6820 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6821 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6822 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6823 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6824 return XEXP (XEXP (x
, 0), 0);
6826 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6827 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6828 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6829 && subreg_lowpart_p (XEXP (x
, 0))
6830 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6831 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6832 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6833 return SUBREG_REG (XEXP (x
, 0));
6835 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6836 is a comparison and STORE_FLAG_VALUE permits. This is like
6837 the first case, but it works even when GET_MODE (x) is larger
6838 than HOST_WIDE_INT. */
6839 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6840 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6841 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6842 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6843 <= HOST_BITS_PER_WIDE_INT
)
6844 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6845 return XEXP (XEXP (x
, 0), 0);
6847 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6848 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6849 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6850 && subreg_lowpart_p (XEXP (x
, 0))
6851 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6852 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6853 <= HOST_BITS_PER_WIDE_INT
)
6854 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6855 return SUBREG_REG (XEXP (x
, 0));
6859 /* If we reach here, we want to return a pair of shifts. The inner
6860 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6861 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6862 logical depending on the value of UNSIGNEDP.
6864 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6865 converted into an AND of a shift.
6867 We must check for the case where the left shift would have a negative
6868 count. This can happen in a case like (x >> 31) & 255 on machines
6869 that can't shift by a constant. On those machines, we would first
6870 combine the shift with the AND to produce a variable-position
6871 extraction. Then the constant of 31 would be substituted in
6872 to produce such a position. */
6874 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6875 if (modewidth
>= pos
+ len
)
6877 enum machine_mode mode
= GET_MODE (x
);
6878 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6879 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6881 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6882 tem
, modewidth
- pos
- len
);
6883 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6884 mode
, tem
, modewidth
- len
);
6886 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6887 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6888 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6891 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6893 /* Any other cases we can't handle. */
6896 /* If we couldn't do this for some reason, return the original
6898 if (GET_CODE (tem
) == CLOBBER
)
6904 /* X is a SET which contains an assignment of one object into
6905 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6906 or certain SUBREGS). If possible, convert it into a series of
6909 We half-heartedly support variable positions, but do not at all
6910 support variable lengths. */
6913 expand_field_assignment (const_rtx x
)
6916 rtx pos
; /* Always counts from low bit. */
6918 rtx mask
, cleared
, masked
;
6919 enum machine_mode compute_mode
;
6921 /* Loop until we find something we can't simplify. */
6924 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6925 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6927 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6928 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6929 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6931 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6932 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6934 inner
= XEXP (SET_DEST (x
), 0);
6935 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6936 pos
= XEXP (SET_DEST (x
), 2);
6938 /* A constant position should stay within the width of INNER. */
6939 if (CONST_INT_P (pos
)
6940 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6943 if (BITS_BIG_ENDIAN
)
6945 if (CONST_INT_P (pos
))
6946 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6948 else if (GET_CODE (pos
) == MINUS
6949 && CONST_INT_P (XEXP (pos
, 1))
6950 && (INTVAL (XEXP (pos
, 1))
6951 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6952 /* If position is ADJUST - X, new position is X. */
6953 pos
= XEXP (pos
, 0);
6956 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
6957 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6958 gen_int_mode (prec
- len
,
6965 /* A SUBREG between two modes that occupy the same numbers of words
6966 can be done by moving the SUBREG to the source. */
6967 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6968 /* We need SUBREGs to compute nonzero_bits properly. */
6969 && nonzero_sign_valid
6970 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6971 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6972 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6973 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6975 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6977 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6984 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6985 inner
= SUBREG_REG (inner
);
6987 compute_mode
= GET_MODE (inner
);
6989 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6990 if (! SCALAR_INT_MODE_P (compute_mode
))
6992 enum machine_mode imode
;
6994 /* Don't do anything for vector or complex integral types. */
6995 if (! FLOAT_MODE_P (compute_mode
))
6998 /* Try to find an integral mode to pun with. */
6999 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7000 if (imode
== BLKmode
)
7003 compute_mode
= imode
;
7004 inner
= gen_lowpart (imode
, inner
);
7007 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7008 if (len
>= HOST_BITS_PER_WIDE_INT
)
7011 /* Now compute the equivalent expression. Make a copy of INNER
7012 for the SET_DEST in case it is a MEM into which we will substitute;
7013 we don't want shared RTL in that case. */
7014 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7016 cleared
= simplify_gen_binary (AND
, compute_mode
,
7017 simplify_gen_unary (NOT
, compute_mode
,
7018 simplify_gen_binary (ASHIFT
,
7023 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7024 simplify_gen_binary (
7026 gen_lowpart (compute_mode
, SET_SRC (x
)),
7030 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7031 simplify_gen_binary (IOR
, compute_mode
,
7038 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7039 it is an RTX that represents the (variable) starting position; otherwise,
7040 POS is the (constant) starting bit position. Both are counted from the LSB.
7042 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7044 IN_DEST is nonzero if this is a reference in the destination of a SET.
7045 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7046 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7049 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7050 ZERO_EXTRACT should be built even for bits starting at bit 0.
7052 MODE is the desired mode of the result (if IN_DEST == 0).
7054 The result is an RTX for the extraction or NULL_RTX if the target
7058 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7059 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7060 int in_dest
, int in_compare
)
7062 /* This mode describes the size of the storage area
7063 to fetch the overall value from. Within that, we
7064 ignore the POS lowest bits, etc. */
7065 enum machine_mode is_mode
= GET_MODE (inner
);
7066 enum machine_mode inner_mode
;
7067 enum machine_mode wanted_inner_mode
;
7068 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7069 enum machine_mode pos_mode
= word_mode
;
7070 enum machine_mode extraction_mode
= word_mode
;
7071 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7073 rtx orig_pos_rtx
= pos_rtx
;
7074 HOST_WIDE_INT orig_pos
;
7076 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7077 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7079 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7081 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7082 consider just the QI as the memory to extract from.
7083 The subreg adds or removes high bits; its mode is
7084 irrelevant to the meaning of this extraction,
7085 since POS and LEN count from the lsb. */
7086 if (MEM_P (SUBREG_REG (inner
)))
7087 is_mode
= GET_MODE (SUBREG_REG (inner
));
7088 inner
= SUBREG_REG (inner
);
7090 else if (GET_CODE (inner
) == ASHIFT
7091 && CONST_INT_P (XEXP (inner
, 1))
7092 && pos_rtx
== 0 && pos
== 0
7093 && len
> UINTVAL (XEXP (inner
, 1)))
7095 /* We're extracting the least significant bits of an rtx
7096 (ashift X (const_int C)), where LEN > C. Extract the
7097 least significant (LEN - C) bits of X, giving an rtx
7098 whose mode is MODE, then shift it left C times. */
7099 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7100 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7101 unsignedp
, in_dest
, in_compare
);
7103 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7105 else if (GET_CODE (inner
) == TRUNCATE
)
7106 inner
= XEXP (inner
, 0);
7108 inner_mode
= GET_MODE (inner
);
7110 /* See if this can be done without an extraction. We never can if the
7111 width of the field is not the same as that of some integer mode. For
7112 registers, we can only avoid the extraction if the position is at the
7113 low-order bit and this is either not in the destination or we have the
7114 appropriate STRICT_LOW_PART operation available.
7116 For MEM, we can avoid an extract if the field starts on an appropriate
7117 boundary and we can change the mode of the memory reference. */
7119 if (tmode
!= BLKmode
7120 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7122 && (inner_mode
== tmode
7124 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7125 || reg_truncated_to_mode (tmode
, inner
))
7128 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7129 || (MEM_P (inner
) && pos_rtx
== 0
7131 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7132 : BITS_PER_UNIT
)) == 0
7133 /* We can't do this if we are widening INNER_MODE (it
7134 may not be aligned, for one thing). */
7135 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7136 && (inner_mode
== tmode
7137 || (! mode_dependent_address_p (XEXP (inner
, 0),
7138 MEM_ADDR_SPACE (inner
))
7139 && ! MEM_VOLATILE_P (inner
))))))
7141 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7142 field. If the original and current mode are the same, we need not
7143 adjust the offset. Otherwise, we do if bytes big endian.
7145 If INNER is not a MEM, get a piece consisting of just the field
7146 of interest (in this case POS % BITS_PER_WORD must be 0). */
7150 HOST_WIDE_INT offset
;
7152 /* POS counts from lsb, but make OFFSET count in memory order. */
7153 if (BYTES_BIG_ENDIAN
)
7154 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7156 offset
= pos
/ BITS_PER_UNIT
;
7158 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7160 else if (REG_P (inner
))
7162 if (tmode
!= inner_mode
)
7164 /* We can't call gen_lowpart in a DEST since we
7165 always want a SUBREG (see below) and it would sometimes
7166 return a new hard register. */
7169 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7171 if (WORDS_BIG_ENDIAN
7172 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7173 final_word
= ((GET_MODE_SIZE (inner_mode
)
7174 - GET_MODE_SIZE (tmode
))
7175 / UNITS_PER_WORD
) - final_word
;
7177 final_word
*= UNITS_PER_WORD
;
7178 if (BYTES_BIG_ENDIAN
&&
7179 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7180 final_word
+= (GET_MODE_SIZE (inner_mode
)
7181 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7183 /* Avoid creating invalid subregs, for example when
7184 simplifying (x>>32)&255. */
7185 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7188 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7191 new_rtx
= gen_lowpart (tmode
, inner
);
7197 new_rtx
= force_to_mode (inner
, tmode
,
7198 len
>= HOST_BITS_PER_WIDE_INT
7199 ? ~(unsigned HOST_WIDE_INT
) 0
7200 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7203 /* If this extraction is going into the destination of a SET,
7204 make a STRICT_LOW_PART unless we made a MEM. */
7207 return (MEM_P (new_rtx
) ? new_rtx
7208 : (GET_CODE (new_rtx
) != SUBREG
7209 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7210 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7215 if (CONST_SCALAR_INT_P (new_rtx
))
7216 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7217 mode
, new_rtx
, tmode
);
7219 /* If we know that no extraneous bits are set, and that the high
7220 bit is not set, convert the extraction to the cheaper of
7221 sign and zero extension, that are equivalent in these cases. */
7222 if (flag_expensive_optimizations
7223 && (HWI_COMPUTABLE_MODE_P (tmode
)
7224 && ((nonzero_bits (new_rtx
, tmode
)
7225 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7228 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7229 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7231 /* Prefer ZERO_EXTENSION, since it gives more information to
7233 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7234 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7239 /* Otherwise, sign- or zero-extend unless we already are in the
7242 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7246 /* Unless this is a COMPARE or we have a funny memory reference,
7247 don't do anything with zero-extending field extracts starting at
7248 the low-order bit since they are simple AND operations. */
7249 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7250 && ! in_compare
&& unsignedp
)
7253 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7254 if the position is not a constant and the length is not 1. In all
7255 other cases, we would only be going outside our object in cases when
7256 an original shift would have been undefined. */
7258 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7259 || (pos_rtx
!= 0 && len
!= 1)))
7262 enum extraction_pattern pattern
= (in_dest
? EP_insv
7263 : unsignedp
? EP_extzv
: EP_extv
);
7265 /* If INNER is not from memory, we want it to have the mode of a register
7266 extraction pattern's structure operand, or word_mode if there is no
7267 such pattern. The same applies to extraction_mode and pos_mode
7268 and their respective operands.
7270 For memory, assume that the desired extraction_mode and pos_mode
7271 are the same as for a register operation, since at present we don't
7272 have named patterns for aligned memory structures. */
7273 struct extraction_insn insn
;
7274 if (get_best_reg_extraction_insn (&insn
, pattern
,
7275 GET_MODE_BITSIZE (inner_mode
), mode
))
7277 wanted_inner_reg_mode
= insn
.struct_mode
;
7278 pos_mode
= insn
.pos_mode
;
7279 extraction_mode
= insn
.field_mode
;
7282 /* Never narrow an object, since that might not be safe. */
7284 if (mode
!= VOIDmode
7285 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7286 extraction_mode
= mode
;
7289 wanted_inner_mode
= wanted_inner_reg_mode
;
7292 /* Be careful not to go beyond the extracted object and maintain the
7293 natural alignment of the memory. */
7294 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7295 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7296 > GET_MODE_BITSIZE (wanted_inner_mode
))
7298 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7299 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7305 if (BITS_BIG_ENDIAN
)
7307 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7308 BITS_BIG_ENDIAN style. If position is constant, compute new
7309 position. Otherwise, build subtraction.
7310 Note that POS is relative to the mode of the original argument.
7311 If it's a MEM we need to recompute POS relative to that.
7312 However, if we're extracting from (or inserting into) a register,
7313 we want to recompute POS relative to wanted_inner_mode. */
7314 int width
= (MEM_P (inner
)
7315 ? GET_MODE_BITSIZE (is_mode
)
7316 : GET_MODE_BITSIZE (wanted_inner_mode
));
7319 pos
= width
- len
- pos
;
7322 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7323 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7325 /* POS may be less than 0 now, but we check for that below.
7326 Note that it can only be less than 0 if !MEM_P (inner). */
7329 /* If INNER has a wider mode, and this is a constant extraction, try to
7330 make it smaller and adjust the byte to point to the byte containing
7332 if (wanted_inner_mode
!= VOIDmode
7333 && inner_mode
!= wanted_inner_mode
7335 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7337 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7338 && ! MEM_VOLATILE_P (inner
))
7342 /* The computations below will be correct if the machine is big
7343 endian in both bits and bytes or little endian in bits and bytes.
7344 If it is mixed, we must adjust. */
7346 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7347 adjust OFFSET to compensate. */
7348 if (BYTES_BIG_ENDIAN
7349 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7350 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7352 /* We can now move to the desired byte. */
7353 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7354 * GET_MODE_SIZE (wanted_inner_mode
);
7355 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7357 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7358 && is_mode
!= wanted_inner_mode
)
7359 offset
= (GET_MODE_SIZE (is_mode
)
7360 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7362 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7365 /* If INNER is not memory, get it into the proper mode. If we are changing
7366 its mode, POS must be a constant and smaller than the size of the new
7368 else if (!MEM_P (inner
))
7370 /* On the LHS, don't create paradoxical subregs implicitely truncating
7371 the register unless TRULY_NOOP_TRUNCATION. */
7373 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7377 if (GET_MODE (inner
) != wanted_inner_mode
7379 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7385 inner
= force_to_mode (inner
, wanted_inner_mode
,
7387 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7388 ? ~(unsigned HOST_WIDE_INT
) 0
7389 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7394 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7395 have to zero extend. Otherwise, we can just use a SUBREG. */
7397 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7399 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7400 GET_MODE (pos_rtx
));
7402 /* If we know that no extraneous bits are set, and that the high
7403 bit is not set, convert extraction to cheaper one - either
7404 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7406 if (flag_expensive_optimizations
7407 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7408 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7409 & ~(((unsigned HOST_WIDE_INT
)
7410 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7414 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7415 GET_MODE (pos_rtx
));
7417 /* Prefer ZERO_EXTENSION, since it gives more information to
7419 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7420 < set_src_cost (temp
, optimize_this_for_speed_p
))
7426 /* Make POS_RTX unless we already have it and it is correct. If we don't
7427 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7429 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7430 pos_rtx
= orig_pos_rtx
;
7432 else if (pos_rtx
== 0)
7433 pos_rtx
= GEN_INT (pos
);
7435 /* Make the required operation. See if we can use existing rtx. */
7436 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7437 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7439 new_rtx
= gen_lowpart (mode
, new_rtx
);
7444 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7445 with any other operations in X. Return X without that shift if so. */
7448 extract_left_shift (rtx x
, int count
)
7450 enum rtx_code code
= GET_CODE (x
);
7451 enum machine_mode mode
= GET_MODE (x
);
7457 /* This is the shift itself. If it is wide enough, we will return
7458 either the value being shifted if the shift count is equal to
7459 COUNT or a shift for the difference. */
7460 if (CONST_INT_P (XEXP (x
, 1))
7461 && INTVAL (XEXP (x
, 1)) >= count
)
7462 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7463 INTVAL (XEXP (x
, 1)) - count
);
7467 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7468 return simplify_gen_unary (code
, mode
, tem
, mode
);
7472 case PLUS
: case IOR
: case XOR
: case AND
:
7473 /* If we can safely shift this constant and we find the inner shift,
7474 make a new operation. */
7475 if (CONST_INT_P (XEXP (x
, 1))
7476 && (UINTVAL (XEXP (x
, 1))
7477 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7478 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7480 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7481 return simplify_gen_binary (code
, mode
, tem
,
7482 gen_int_mode (val
, mode
));
7493 /* Look at the expression rooted at X. Look for expressions
7494 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7495 Form these expressions.
7497 Return the new rtx, usually just X.
7499 Also, for machines like the VAX that don't have logical shift insns,
7500 try to convert logical to arithmetic shift operations in cases where
7501 they are equivalent. This undoes the canonicalizations to logical
7502 shifts done elsewhere.
7504 We try, as much as possible, to re-use rtl expressions to save memory.
7506 IN_CODE says what kind of expression we are processing. Normally, it is
7507 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7508 being kludges), it is MEM. When processing the arguments of a comparison
7509 or a COMPARE against zero, it is COMPARE. */
7512 make_compound_operation (rtx x
, enum rtx_code in_code
)
7514 enum rtx_code code
= GET_CODE (x
);
7515 enum machine_mode mode
= GET_MODE (x
);
7516 int mode_width
= GET_MODE_PRECISION (mode
);
7518 enum rtx_code next_code
;
7524 /* Select the code to be used in recursive calls. Once we are inside an
7525 address, we stay there. If we have a comparison, set to COMPARE,
7526 but once inside, go back to our default of SET. */
7528 next_code
= (code
== MEM
? MEM
7529 : ((code
== PLUS
|| code
== MINUS
)
7530 && SCALAR_INT_MODE_P (mode
)) ? MEM
7531 : ((code
== COMPARE
|| COMPARISON_P (x
))
7532 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7533 : in_code
== COMPARE
? SET
: in_code
);
7535 /* Process depending on the code of this operation. If NEW is set
7536 nonzero, it will be returned. */
7541 /* Convert shifts by constants into multiplications if inside
7543 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7544 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7545 && INTVAL (XEXP (x
, 1)) >= 0
7546 && SCALAR_INT_MODE_P (mode
))
7548 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7549 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7551 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7552 if (GET_CODE (new_rtx
) == NEG
)
7554 new_rtx
= XEXP (new_rtx
, 0);
7557 multval
= trunc_int_for_mode (multval
, mode
);
7558 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7565 lhs
= make_compound_operation (lhs
, next_code
);
7566 rhs
= make_compound_operation (rhs
, next_code
);
7567 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7568 && SCALAR_INT_MODE_P (mode
))
7570 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7572 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7574 else if (GET_CODE (lhs
) == MULT
7575 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7577 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7578 simplify_gen_unary (NEG
, mode
,
7581 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7585 SUBST (XEXP (x
, 0), lhs
);
7586 SUBST (XEXP (x
, 1), rhs
);
7589 x
= gen_lowpart (mode
, new_rtx
);
7595 lhs
= make_compound_operation (lhs
, next_code
);
7596 rhs
= make_compound_operation (rhs
, next_code
);
7597 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7598 && SCALAR_INT_MODE_P (mode
))
7600 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7602 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7604 else if (GET_CODE (rhs
) == MULT
7605 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7607 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7608 simplify_gen_unary (NEG
, mode
,
7611 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7615 SUBST (XEXP (x
, 0), lhs
);
7616 SUBST (XEXP (x
, 1), rhs
);
7619 return gen_lowpart (mode
, new_rtx
);
7622 /* If the second operand is not a constant, we can't do anything
7624 if (!CONST_INT_P (XEXP (x
, 1)))
7627 /* If the constant is a power of two minus one and the first operand
7628 is a logical right shift, make an extraction. */
7629 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7630 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7632 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7633 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7634 0, in_code
== COMPARE
);
7637 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7638 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7639 && subreg_lowpart_p (XEXP (x
, 0))
7640 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7641 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7643 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7645 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7646 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7647 0, in_code
== COMPARE
);
7649 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7650 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7651 || GET_CODE (XEXP (x
, 0)) == IOR
)
7652 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7653 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7654 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7656 /* Apply the distributive law, and then try to make extractions. */
7657 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7658 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7660 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7662 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7665 /* If we are have (and (rotate X C) M) and C is larger than the number
7666 of bits in M, this is an extraction. */
7668 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7669 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7670 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7671 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7673 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7674 new_rtx
= make_extraction (mode
, new_rtx
,
7675 (GET_MODE_PRECISION (mode
)
7676 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7677 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7680 /* On machines without logical shifts, if the operand of the AND is
7681 a logical shift and our mask turns off all the propagated sign
7682 bits, we can replace the logical shift with an arithmetic shift. */
7683 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7684 && !have_insn_for (LSHIFTRT
, mode
)
7685 && have_insn_for (ASHIFTRT
, mode
)
7686 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7687 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7688 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7689 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7691 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7693 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7694 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7696 gen_rtx_ASHIFTRT (mode
,
7697 make_compound_operation
7698 (XEXP (XEXP (x
, 0), 0), next_code
),
7699 XEXP (XEXP (x
, 0), 1)));
7702 /* If the constant is one less than a power of two, this might be
7703 representable by an extraction even if no shift is present.
7704 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7705 we are in a COMPARE. */
7706 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7707 new_rtx
= make_extraction (mode
,
7708 make_compound_operation (XEXP (x
, 0),
7710 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7712 /* If we are in a comparison and this is an AND with a power of two,
7713 convert this into the appropriate bit extract. */
7714 else if (in_code
== COMPARE
7715 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7716 new_rtx
= make_extraction (mode
,
7717 make_compound_operation (XEXP (x
, 0),
7719 i
, NULL_RTX
, 1, 1, 0, 1);
7724 /* If the sign bit is known to be zero, replace this with an
7725 arithmetic shift. */
7726 if (have_insn_for (ASHIFTRT
, mode
)
7727 && ! have_insn_for (LSHIFTRT
, mode
)
7728 && mode_width
<= HOST_BITS_PER_WIDE_INT
7729 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7731 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7732 make_compound_operation (XEXP (x
, 0),
7738 /* ... fall through ... */
7744 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7745 this is a SIGN_EXTRACT. */
7746 if (CONST_INT_P (rhs
)
7747 && GET_CODE (lhs
) == ASHIFT
7748 && CONST_INT_P (XEXP (lhs
, 1))
7749 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7750 && INTVAL (XEXP (lhs
, 1)) >= 0
7751 && INTVAL (rhs
) < mode_width
)
7753 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7754 new_rtx
= make_extraction (mode
, new_rtx
,
7755 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7756 NULL_RTX
, mode_width
- INTVAL (rhs
),
7757 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7761 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7762 If so, try to merge the shifts into a SIGN_EXTEND. We could
7763 also do this for some cases of SIGN_EXTRACT, but it doesn't
7764 seem worth the effort; the case checked for occurs on Alpha. */
7767 && ! (GET_CODE (lhs
) == SUBREG
7768 && (OBJECT_P (SUBREG_REG (lhs
))))
7769 && CONST_INT_P (rhs
)
7770 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7771 && INTVAL (rhs
) < mode_width
7772 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7773 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7774 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7775 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7780 /* Call ourselves recursively on the inner expression. If we are
7781 narrowing the object and it has a different RTL code from
7782 what it originally did, do this SUBREG as a force_to_mode. */
7784 rtx inner
= SUBREG_REG (x
), simplified
;
7785 enum rtx_code subreg_code
= in_code
;
7787 /* If in_code is COMPARE, it isn't always safe to pass it through
7788 to the recursive make_compound_operation call. */
7789 if (subreg_code
== COMPARE
7790 && (!subreg_lowpart_p (x
)
7791 || GET_CODE (inner
) == SUBREG
7792 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7793 is (const_int 0), rather than
7794 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7795 || (GET_CODE (inner
) == AND
7796 && CONST_INT_P (XEXP (inner
, 1))
7797 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7798 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7799 >= GET_MODE_BITSIZE (mode
))))
7802 tem
= make_compound_operation (inner
, subreg_code
);
7805 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7809 if (GET_CODE (tem
) != GET_CODE (inner
)
7810 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7811 && subreg_lowpart_p (x
))
7814 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7816 /* If we have something other than a SUBREG, we might have
7817 done an expansion, so rerun ourselves. */
7818 if (GET_CODE (newer
) != SUBREG
)
7819 newer
= make_compound_operation (newer
, in_code
);
7821 /* force_to_mode can expand compounds. If it just re-expanded the
7822 compound, use gen_lowpart to convert to the desired mode. */
7823 if (rtx_equal_p (newer
, x
)
7824 /* Likewise if it re-expanded the compound only partially.
7825 This happens for SUBREG of ZERO_EXTRACT if they extract
7826 the same number of bits. */
7827 || (GET_CODE (newer
) == SUBREG
7828 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7829 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7830 && GET_CODE (inner
) == AND
7831 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7832 return gen_lowpart (GET_MODE (x
), tem
);
7848 x
= gen_lowpart (mode
, new_rtx
);
7849 code
= GET_CODE (x
);
7852 /* Now recursively process each operand of this operation. We need to
7853 handle ZERO_EXTEND specially so that we don't lose track of the
7855 if (GET_CODE (x
) == ZERO_EXTEND
)
7857 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7858 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7859 new_rtx
, GET_MODE (XEXP (x
, 0)));
7862 SUBST (XEXP (x
, 0), new_rtx
);
7866 fmt
= GET_RTX_FORMAT (code
);
7867 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7870 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7871 SUBST (XEXP (x
, i
), new_rtx
);
7873 else if (fmt
[i
] == 'E')
7874 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7876 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7877 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7881 /* If this is a commutative operation, the changes to the operands
7882 may have made it noncanonical. */
7883 if (COMMUTATIVE_ARITH_P (x
)
7884 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7887 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7888 SUBST (XEXP (x
, 1), tem
);
7894 /* Given M see if it is a value that would select a field of bits
7895 within an item, but not the entire word. Return -1 if not.
7896 Otherwise, return the starting position of the field, where 0 is the
7899 *PLEN is set to the length of the field. */
7902 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7904 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7905 int pos
= m
? ctz_hwi (m
) : -1;
7909 /* Now shift off the low-order zero bits and see if we have a
7910 power of two minus 1. */
7911 len
= exact_log2 ((m
>> pos
) + 1);
7920 /* If X refers to a register that equals REG in value, replace these
7921 references with REG. */
7923 canon_reg_for_combine (rtx x
, rtx reg
)
7930 enum rtx_code code
= GET_CODE (x
);
7931 switch (GET_RTX_CLASS (code
))
7934 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7935 if (op0
!= XEXP (x
, 0))
7936 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7941 case RTX_COMM_ARITH
:
7942 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7943 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7944 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7945 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7949 case RTX_COMM_COMPARE
:
7950 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7951 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7952 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7953 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7954 GET_MODE (op0
), op0
, op1
);
7958 case RTX_BITFIELD_OPS
:
7959 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7960 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7961 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7962 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7963 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7964 GET_MODE (op0
), op0
, op1
, op2
);
7969 if (rtx_equal_p (get_last_value (reg
), x
)
7970 || rtx_equal_p (reg
, get_last_value (x
)))
7979 fmt
= GET_RTX_FORMAT (code
);
7981 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7984 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7985 if (op
!= XEXP (x
, i
))
7995 else if (fmt
[i
] == 'E')
7998 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8000 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8001 if (op
!= XVECEXP (x
, i
, j
))
8008 XVECEXP (x
, i
, j
) = op
;
8019 /* Return X converted to MODE. If the value is already truncated to
8020 MODE we can just return a subreg even though in the general case we
8021 would need an explicit truncation. */
8024 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
8026 if (!CONST_INT_P (x
)
8027 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8028 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8029 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8031 /* Bit-cast X into an integer mode. */
8032 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8033 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8034 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8038 return gen_lowpart (mode
, x
);
8041 /* See if X can be simplified knowing that we will only refer to it in
8042 MODE and will only refer to those bits that are nonzero in MASK.
8043 If other bits are being computed or if masking operations are done
8044 that select a superset of the bits in MASK, they can sometimes be
8047 Return a possibly simplified expression, but always convert X to
8048 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8050 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8051 are all off in X. This is used when X will be complemented, by either
8052 NOT, NEG, or XOR. */
8055 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8058 enum rtx_code code
= GET_CODE (x
);
8059 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8060 enum machine_mode op_mode
;
8061 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8064 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8065 code below will do the wrong thing since the mode of such an
8066 expression is VOIDmode.
8068 Also do nothing if X is a CLOBBER; this can happen if X was
8069 the return value from a call to gen_lowpart. */
8070 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8073 /* We want to perform the operation in its present mode unless we know
8074 that the operation is valid in MODE, in which case we do the operation
8076 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8077 && have_insn_for (code
, mode
))
8078 ? mode
: GET_MODE (x
));
8080 /* It is not valid to do a right-shift in a narrower mode
8081 than the one it came in with. */
8082 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8083 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8084 op_mode
= GET_MODE (x
);
8086 /* Truncate MASK to fit OP_MODE. */
8088 mask
&= GET_MODE_MASK (op_mode
);
8090 /* When we have an arithmetic operation, or a shift whose count we
8091 do not know, we need to assume that all bits up to the highest-order
8092 bit in MASK will be needed. This is how we form such a mask. */
8093 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8094 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8096 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8099 /* Determine what bits of X are guaranteed to be (non)zero. */
8100 nonzero
= nonzero_bits (x
, mode
);
8102 /* If none of the bits in X are needed, return a zero. */
8103 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8106 /* If X is a CONST_INT, return a new one. Do this here since the
8107 test below will fail. */
8108 if (CONST_INT_P (x
))
8110 if (SCALAR_INT_MODE_P (mode
))
8111 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8114 x
= GEN_INT (INTVAL (x
) & mask
);
8115 return gen_lowpart_common (mode
, x
);
8119 /* If X is narrower than MODE and we want all the bits in X's mode, just
8120 get X in the proper mode. */
8121 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8122 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8123 return gen_lowpart (mode
, x
);
8125 /* We can ignore the effect of a SUBREG if it narrows the mode or
8126 if the constant masks to zero all the bits the mode doesn't have. */
8127 if (GET_CODE (x
) == SUBREG
8128 && subreg_lowpart_p (x
)
8129 && ((GET_MODE_SIZE (GET_MODE (x
))
8130 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8132 & GET_MODE_MASK (GET_MODE (x
))
8133 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8134 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8136 /* The arithmetic simplifications here only work for scalar integer modes. */
8137 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8138 return gen_lowpart_or_truncate (mode
, x
);
8143 /* If X is a (clobber (const_int)), return it since we know we are
8144 generating something that won't match. */
8151 x
= expand_compound_operation (x
);
8152 if (GET_CODE (x
) != code
)
8153 return force_to_mode (x
, mode
, mask
, next_select
);
8157 /* Similarly for a truncate. */
8158 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8161 /* If this is an AND with a constant, convert it into an AND
8162 whose constant is the AND of that constant with MASK. If it
8163 remains an AND of MASK, delete it since it is redundant. */
8165 if (CONST_INT_P (XEXP (x
, 1)))
8167 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8168 mask
& INTVAL (XEXP (x
, 1)));
8170 /* If X is still an AND, see if it is an AND with a mask that
8171 is just some low-order bits. If so, and it is MASK, we don't
8174 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8175 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8179 /* If it remains an AND, try making another AND with the bits
8180 in the mode mask that aren't in MASK turned on. If the
8181 constant in the AND is wide enough, this might make a
8182 cheaper constant. */
8184 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8185 && GET_MODE_MASK (GET_MODE (x
)) != mask
8186 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8188 unsigned HOST_WIDE_INT cval
8189 = UINTVAL (XEXP (x
, 1))
8190 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8193 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8194 gen_int_mode (cval
, GET_MODE (x
)));
8195 if (set_src_cost (y
, optimize_this_for_speed_p
)
8196 < set_src_cost (x
, optimize_this_for_speed_p
))
8206 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8207 low-order bits (as in an alignment operation) and FOO is already
8208 aligned to that boundary, mask C1 to that boundary as well.
8209 This may eliminate that PLUS and, later, the AND. */
8212 unsigned int width
= GET_MODE_PRECISION (mode
);
8213 unsigned HOST_WIDE_INT smask
= mask
;
8215 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8216 number, sign extend it. */
8218 if (width
< HOST_BITS_PER_WIDE_INT
8219 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8220 smask
|= HOST_WIDE_INT_M1U
<< width
;
8222 if (CONST_INT_P (XEXP (x
, 1))
8223 && exact_log2 (- smask
) >= 0
8224 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8225 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8226 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8227 (INTVAL (XEXP (x
, 1)) & smask
)),
8228 mode
, smask
, next_select
);
8231 /* ... fall through ... */
8234 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8235 most significant bit in MASK since carries from those bits will
8236 affect the bits we are interested in. */
8241 /* If X is (minus C Y) where C's least set bit is larger than any bit
8242 in the mask, then we may replace with (neg Y). */
8243 if (CONST_INT_P (XEXP (x
, 0))
8244 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8246 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8248 return force_to_mode (x
, mode
, mask
, next_select
);
8251 /* Similarly, if C contains every bit in the fuller_mask, then we may
8252 replace with (not Y). */
8253 if (CONST_INT_P (XEXP (x
, 0))
8254 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8256 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8257 XEXP (x
, 1), GET_MODE (x
));
8258 return force_to_mode (x
, mode
, mask
, next_select
);
8266 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8267 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8268 operation which may be a bitfield extraction. Ensure that the
8269 constant we form is not wider than the mode of X. */
8271 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8272 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8273 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8274 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8275 && CONST_INT_P (XEXP (x
, 1))
8276 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8277 + floor_log2 (INTVAL (XEXP (x
, 1))))
8278 < GET_MODE_PRECISION (GET_MODE (x
)))
8279 && (UINTVAL (XEXP (x
, 1))
8280 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8282 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8283 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8285 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8286 XEXP (XEXP (x
, 0), 0), temp
);
8287 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8288 XEXP (XEXP (x
, 0), 1));
8289 return force_to_mode (x
, mode
, mask
, next_select
);
8293 /* For most binary operations, just propagate into the operation and
8294 change the mode if we have an operation of that mode. */
8296 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8297 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8299 /* If we ended up truncating both operands, truncate the result of the
8300 operation instead. */
8301 if (GET_CODE (op0
) == TRUNCATE
8302 && GET_CODE (op1
) == TRUNCATE
)
8304 op0
= XEXP (op0
, 0);
8305 op1
= XEXP (op1
, 0);
8308 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8309 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8311 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8312 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8316 /* For left shifts, do the same, but just for the first operand.
8317 However, we cannot do anything with shifts where we cannot
8318 guarantee that the counts are smaller than the size of the mode
8319 because such a count will have a different meaning in a
8322 if (! (CONST_INT_P (XEXP (x
, 1))
8323 && INTVAL (XEXP (x
, 1)) >= 0
8324 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8325 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8326 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8327 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8330 /* If the shift count is a constant and we can do arithmetic in
8331 the mode of the shift, refine which bits we need. Otherwise, use the
8332 conservative form of the mask. */
8333 if (CONST_INT_P (XEXP (x
, 1))
8334 && INTVAL (XEXP (x
, 1)) >= 0
8335 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8336 && HWI_COMPUTABLE_MODE_P (op_mode
))
8337 mask
>>= INTVAL (XEXP (x
, 1));
8341 op0
= gen_lowpart_or_truncate (op_mode
,
8342 force_to_mode (XEXP (x
, 0), op_mode
,
8343 mask
, next_select
));
8345 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8346 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8350 /* Here we can only do something if the shift count is a constant,
8351 this shift constant is valid for the host, and we can do arithmetic
8354 if (CONST_INT_P (XEXP (x
, 1))
8355 && INTVAL (XEXP (x
, 1)) >= 0
8356 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8357 && HWI_COMPUTABLE_MODE_P (op_mode
))
8359 rtx inner
= XEXP (x
, 0);
8360 unsigned HOST_WIDE_INT inner_mask
;
8362 /* Select the mask of the bits we need for the shift operand. */
8363 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8365 /* We can only change the mode of the shift if we can do arithmetic
8366 in the mode of the shift and INNER_MASK is no wider than the
8367 width of X's mode. */
8368 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8369 op_mode
= GET_MODE (x
);
8371 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8373 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8374 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8377 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8378 shift and AND produces only copies of the sign bit (C2 is one less
8379 than a power of two), we can do this with just a shift. */
8381 if (GET_CODE (x
) == LSHIFTRT
8382 && CONST_INT_P (XEXP (x
, 1))
8383 /* The shift puts one of the sign bit copies in the least significant
8385 && ((INTVAL (XEXP (x
, 1))
8386 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8387 >= GET_MODE_PRECISION (GET_MODE (x
)))
8388 && exact_log2 (mask
+ 1) >= 0
8389 /* Number of bits left after the shift must be more than the mask
8391 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8392 <= GET_MODE_PRECISION (GET_MODE (x
)))
8393 /* Must be more sign bit copies than the mask needs. */
8394 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8395 >= exact_log2 (mask
+ 1)))
8396 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8397 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8398 - exact_log2 (mask
+ 1)));
8403 /* If we are just looking for the sign bit, we don't need this shift at
8404 all, even if it has a variable count. */
8405 if (val_signbit_p (GET_MODE (x
), mask
))
8406 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8408 /* If this is a shift by a constant, get a mask that contains those bits
8409 that are not copies of the sign bit. We then have two cases: If
8410 MASK only includes those bits, this can be a logical shift, which may
8411 allow simplifications. If MASK is a single-bit field not within
8412 those bits, we are requesting a copy of the sign bit and hence can
8413 shift the sign bit to the appropriate location. */
8415 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8416 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8420 /* If the considered data is wider than HOST_WIDE_INT, we can't
8421 represent a mask for all its bits in a single scalar.
8422 But we only care about the lower bits, so calculate these. */
8424 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8426 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8428 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8429 is the number of bits a full-width mask would have set.
8430 We need only shift if these are fewer than nonzero can
8431 hold. If not, we must keep all bits set in nonzero. */
8433 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8434 < HOST_BITS_PER_WIDE_INT
)
8435 nonzero
>>= INTVAL (XEXP (x
, 1))
8436 + HOST_BITS_PER_WIDE_INT
8437 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8441 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8442 nonzero
>>= INTVAL (XEXP (x
, 1));
8445 if ((mask
& ~nonzero
) == 0)
8447 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8448 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8449 if (GET_CODE (x
) != ASHIFTRT
)
8450 return force_to_mode (x
, mode
, mask
, next_select
);
8453 else if ((i
= exact_log2 (mask
)) >= 0)
8455 x
= simplify_shift_const
8456 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8457 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8459 if (GET_CODE (x
) != ASHIFTRT
)
8460 return force_to_mode (x
, mode
, mask
, next_select
);
8464 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8465 even if the shift count isn't a constant. */
8467 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8468 XEXP (x
, 0), XEXP (x
, 1));
8472 /* If this is a zero- or sign-extension operation that just affects bits
8473 we don't care about, remove it. Be sure the call above returned
8474 something that is still a shift. */
8476 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8477 && CONST_INT_P (XEXP (x
, 1))
8478 && INTVAL (XEXP (x
, 1)) >= 0
8479 && (INTVAL (XEXP (x
, 1))
8480 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8481 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8482 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8483 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8490 /* If the shift count is constant and we can do computations
8491 in the mode of X, compute where the bits we care about are.
8492 Otherwise, we can't do anything. Don't change the mode of
8493 the shift or propagate MODE into the shift, though. */
8494 if (CONST_INT_P (XEXP (x
, 1))
8495 && INTVAL (XEXP (x
, 1)) >= 0)
8497 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8499 gen_int_mode (mask
, GET_MODE (x
)),
8501 if (temp
&& CONST_INT_P (temp
))
8502 x
= simplify_gen_binary (code
, GET_MODE (x
),
8503 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8504 INTVAL (temp
), next_select
),
8510 /* If we just want the low-order bit, the NEG isn't needed since it
8511 won't change the low-order bit. */
8513 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8515 /* We need any bits less significant than the most significant bit in
8516 MASK since carries from those bits will affect the bits we are
8522 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8523 same as the XOR case above. Ensure that the constant we form is not
8524 wider than the mode of X. */
8526 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8527 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8528 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8529 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8530 < GET_MODE_PRECISION (GET_MODE (x
)))
8531 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8533 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8535 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8536 XEXP (XEXP (x
, 0), 0), temp
);
8537 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8538 temp
, XEXP (XEXP (x
, 0), 1));
8540 return force_to_mode (x
, mode
, mask
, next_select
);
8543 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8544 use the full mask inside the NOT. */
8548 op0
= gen_lowpart_or_truncate (op_mode
,
8549 force_to_mode (XEXP (x
, 0), mode
, mask
,
8551 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8552 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8556 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8557 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8558 which is equal to STORE_FLAG_VALUE. */
8559 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8560 && XEXP (x
, 1) == const0_rtx
8561 && GET_MODE (XEXP (x
, 0)) == mode
8562 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8563 && (nonzero_bits (XEXP (x
, 0), mode
)
8564 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8565 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8570 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8571 written in a narrower mode. We play it safe and do not do so. */
8573 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8574 force_to_mode (XEXP (x
, 1), mode
,
8575 mask
, next_select
));
8576 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8577 force_to_mode (XEXP (x
, 2), mode
,
8578 mask
, next_select
));
8579 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8580 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8581 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8589 /* Ensure we return a value of the proper mode. */
8590 return gen_lowpart_or_truncate (mode
, x
);
8593 /* Return nonzero if X is an expression that has one of two values depending on
8594 whether some other value is zero or nonzero. In that case, we return the
8595 value that is being tested, *PTRUE is set to the value if the rtx being
8596 returned has a nonzero value, and *PFALSE is set to the other alternative.
8598 If we return zero, we set *PTRUE and *PFALSE to X. */
8601 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8603 enum machine_mode mode
= GET_MODE (x
);
8604 enum rtx_code code
= GET_CODE (x
);
8605 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8606 unsigned HOST_WIDE_INT nz
;
8608 /* If we are comparing a value against zero, we are done. */
8609 if ((code
== NE
|| code
== EQ
)
8610 && XEXP (x
, 1) == const0_rtx
)
8612 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8613 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8617 /* If this is a unary operation whose operand has one of two values, apply
8618 our opcode to compute those values. */
8619 else if (UNARY_P (x
)
8620 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8622 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8623 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8624 GET_MODE (XEXP (x
, 0)));
8628 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8629 make can't possibly match and would suppress other optimizations. */
8630 else if (code
== COMPARE
)
8633 /* If this is a binary operation, see if either side has only one of two
8634 values. If either one does or if both do and they are conditional on
8635 the same value, compute the new true and false values. */
8636 else if (BINARY_P (x
))
8638 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8639 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8641 if ((cond0
!= 0 || cond1
!= 0)
8642 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8644 /* If if_then_else_cond returned zero, then true/false are the
8645 same rtl. We must copy one of them to prevent invalid rtl
8648 true0
= copy_rtx (true0
);
8649 else if (cond1
== 0)
8650 true1
= copy_rtx (true1
);
8652 if (COMPARISON_P (x
))
8654 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8656 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8661 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8662 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8665 return cond0
? cond0
: cond1
;
8668 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8669 operands is zero when the other is nonzero, and vice-versa,
8670 and STORE_FLAG_VALUE is 1 or -1. */
8672 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8673 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8675 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8677 rtx op0
= XEXP (XEXP (x
, 0), 1);
8678 rtx op1
= XEXP (XEXP (x
, 1), 1);
8680 cond0
= XEXP (XEXP (x
, 0), 0);
8681 cond1
= XEXP (XEXP (x
, 1), 0);
8683 if (COMPARISON_P (cond0
)
8684 && COMPARISON_P (cond1
)
8685 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8686 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8687 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8688 || ((swap_condition (GET_CODE (cond0
))
8689 == reversed_comparison_code (cond1
, NULL
))
8690 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8691 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8692 && ! side_effects_p (x
))
8694 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8695 *pfalse
= simplify_gen_binary (MULT
, mode
,
8697 ? simplify_gen_unary (NEG
, mode
,
8705 /* Similarly for MULT, AND and UMIN, except that for these the result
8707 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8708 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8709 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8711 cond0
= XEXP (XEXP (x
, 0), 0);
8712 cond1
= XEXP (XEXP (x
, 1), 0);
8714 if (COMPARISON_P (cond0
)
8715 && COMPARISON_P (cond1
)
8716 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8717 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8718 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8719 || ((swap_condition (GET_CODE (cond0
))
8720 == reversed_comparison_code (cond1
, NULL
))
8721 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8722 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8723 && ! side_effects_p (x
))
8725 *ptrue
= *pfalse
= const0_rtx
;
8731 else if (code
== IF_THEN_ELSE
)
8733 /* If we have IF_THEN_ELSE already, extract the condition and
8734 canonicalize it if it is NE or EQ. */
8735 cond0
= XEXP (x
, 0);
8736 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8737 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8738 return XEXP (cond0
, 0);
8739 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8741 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8742 return XEXP (cond0
, 0);
8748 /* If X is a SUBREG, we can narrow both the true and false values
8749 if the inner expression, if there is a condition. */
8750 else if (code
== SUBREG
8751 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8754 true0
= simplify_gen_subreg (mode
, true0
,
8755 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8756 false0
= simplify_gen_subreg (mode
, false0
,
8757 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8758 if (true0
&& false0
)
8766 /* If X is a constant, this isn't special and will cause confusions
8767 if we treat it as such. Likewise if it is equivalent to a constant. */
8768 else if (CONSTANT_P (x
)
8769 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8772 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8773 will be least confusing to the rest of the compiler. */
8774 else if (mode
== BImode
)
8776 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8780 /* If X is known to be either 0 or -1, those are the true and
8781 false values when testing X. */
8782 else if (x
== constm1_rtx
|| x
== const0_rtx
8783 || (mode
!= VOIDmode
8784 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8786 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8790 /* Likewise for 0 or a single bit. */
8791 else if (HWI_COMPUTABLE_MODE_P (mode
)
8792 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8794 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8798 /* Otherwise fail; show no condition with true and false values the same. */
8799 *ptrue
= *pfalse
= x
;
8803 /* Return the value of expression X given the fact that condition COND
8804 is known to be true when applied to REG as its first operand and VAL
8805 as its second. X is known to not be shared and so can be modified in
8808 We only handle the simplest cases, and specifically those cases that
8809 arise with IF_THEN_ELSE expressions. */
8812 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8814 enum rtx_code code
= GET_CODE (x
);
8819 if (side_effects_p (x
))
8822 /* If either operand of the condition is a floating point value,
8823 then we have to avoid collapsing an EQ comparison. */
8825 && rtx_equal_p (x
, reg
)
8826 && ! FLOAT_MODE_P (GET_MODE (x
))
8827 && ! FLOAT_MODE_P (GET_MODE (val
)))
8830 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8833 /* If X is (abs REG) and we know something about REG's relationship
8834 with zero, we may be able to simplify this. */
8836 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8839 case GE
: case GT
: case EQ
:
8842 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8844 GET_MODE (XEXP (x
, 0)));
8849 /* The only other cases we handle are MIN, MAX, and comparisons if the
8850 operands are the same as REG and VAL. */
8852 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8854 if (rtx_equal_p (XEXP (x
, 0), val
))
8855 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8857 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8859 if (COMPARISON_P (x
))
8861 if (comparison_dominates_p (cond
, code
))
8862 return const_true_rtx
;
8864 code
= reversed_comparison_code (x
, NULL
);
8866 && comparison_dominates_p (cond
, code
))
8871 else if (code
== SMAX
|| code
== SMIN
8872 || code
== UMIN
|| code
== UMAX
)
8874 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8876 /* Do not reverse the condition when it is NE or EQ.
8877 This is because we cannot conclude anything about
8878 the value of 'SMAX (x, y)' when x is not equal to y,
8879 but we can when x equals y. */
8880 if ((code
== SMAX
|| code
== UMAX
)
8881 && ! (cond
== EQ
|| cond
== NE
))
8882 cond
= reverse_condition (cond
);
8887 return unsignedp
? x
: XEXP (x
, 1);
8889 return unsignedp
? x
: XEXP (x
, 0);
8891 return unsignedp
? XEXP (x
, 1) : x
;
8893 return unsignedp
? XEXP (x
, 0) : x
;
8900 else if (code
== SUBREG
)
8902 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8903 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8905 if (SUBREG_REG (x
) != r
)
8907 /* We must simplify subreg here, before we lose track of the
8908 original inner_mode. */
8909 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8910 inner_mode
, SUBREG_BYTE (x
));
8914 SUBST (SUBREG_REG (x
), r
);
8919 /* We don't have to handle SIGN_EXTEND here, because even in the
8920 case of replacing something with a modeless CONST_INT, a
8921 CONST_INT is already (supposed to be) a valid sign extension for
8922 its narrower mode, which implies it's already properly
8923 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8924 story is different. */
8925 else if (code
== ZERO_EXTEND
)
8927 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8928 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8930 if (XEXP (x
, 0) != r
)
8932 /* We must simplify the zero_extend here, before we lose
8933 track of the original inner_mode. */
8934 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8939 SUBST (XEXP (x
, 0), r
);
8945 fmt
= GET_RTX_FORMAT (code
);
8946 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8949 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8950 else if (fmt
[i
] == 'E')
8951 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8952 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8959 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8960 assignment as a field assignment. */
8963 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8965 if (x
== y
|| rtx_equal_p (x
, y
))
8968 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8971 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8972 Note that all SUBREGs of MEM are paradoxical; otherwise they
8973 would have been rewritten. */
8974 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8975 && MEM_P (SUBREG_REG (y
))
8976 && rtx_equal_p (SUBREG_REG (y
),
8977 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8980 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8981 && MEM_P (SUBREG_REG (x
))
8982 && rtx_equal_p (SUBREG_REG (x
),
8983 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8986 /* We used to see if get_last_value of X and Y were the same but that's
8987 not correct. In one direction, we'll cause the assignment to have
8988 the wrong destination and in the case, we'll import a register into this
8989 insn that might have already have been dead. So fail if none of the
8990 above cases are true. */
8994 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8995 Return that assignment if so.
8997 We only handle the most common cases. */
9000 make_field_assignment (rtx x
)
9002 rtx dest
= SET_DEST (x
);
9003 rtx src
= SET_SRC (x
);
9008 unsigned HOST_WIDE_INT len
;
9010 enum machine_mode mode
;
9012 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9013 a clear of a one-bit field. We will have changed it to
9014 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9017 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9018 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9019 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9020 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9022 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9025 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9029 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9030 && subreg_lowpart_p (XEXP (src
, 0))
9031 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9032 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9033 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9034 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9035 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9036 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9038 assign
= make_extraction (VOIDmode
, dest
, 0,
9039 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9042 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9046 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9048 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9049 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9050 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9052 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9055 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9059 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9060 SRC is an AND with all bits of that field set, then we can discard
9062 if (GET_CODE (dest
) == ZERO_EXTRACT
9063 && CONST_INT_P (XEXP (dest
, 1))
9064 && GET_CODE (src
) == AND
9065 && CONST_INT_P (XEXP (src
, 1)))
9067 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9068 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9069 unsigned HOST_WIDE_INT ze_mask
;
9071 if (width
>= HOST_BITS_PER_WIDE_INT
)
9074 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9076 /* Complete overlap. We can remove the source AND. */
9077 if ((and_mask
& ze_mask
) == ze_mask
)
9078 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9080 /* Partial overlap. We can reduce the source AND. */
9081 if ((and_mask
& ze_mask
) != and_mask
)
9083 mode
= GET_MODE (src
);
9084 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9085 gen_int_mode (and_mask
& ze_mask
, mode
));
9086 return gen_rtx_SET (VOIDmode
, dest
, src
);
9090 /* The other case we handle is assignments into a constant-position
9091 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9092 a mask that has all one bits except for a group of zero bits and
9093 OTHER is known to have zeros where C1 has ones, this is such an
9094 assignment. Compute the position and length from C1. Shift OTHER
9095 to the appropriate position, force it to the required mode, and
9096 make the extraction. Check for the AND in both operands. */
9098 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9101 rhs
= expand_compound_operation (XEXP (src
, 0));
9102 lhs
= expand_compound_operation (XEXP (src
, 1));
9104 if (GET_CODE (rhs
) == AND
9105 && CONST_INT_P (XEXP (rhs
, 1))
9106 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9107 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9108 else if (GET_CODE (lhs
) == AND
9109 && CONST_INT_P (XEXP (lhs
, 1))
9110 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9111 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9115 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9116 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9117 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9118 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9121 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9125 /* The mode to use for the source is the mode of the assignment, or of
9126 what is inside a possible STRICT_LOW_PART. */
9127 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9128 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9130 /* Shift OTHER right POS places and make it the source, restricting it
9131 to the proper length and mode. */
9133 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9137 src
= force_to_mode (src
, mode
,
9138 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9139 ? ~(unsigned HOST_WIDE_INT
) 0
9140 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9143 /* If SRC is masked by an AND that does not make a difference in
9144 the value being stored, strip it. */
9145 if (GET_CODE (assign
) == ZERO_EXTRACT
9146 && CONST_INT_P (XEXP (assign
, 1))
9147 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9148 && GET_CODE (src
) == AND
9149 && CONST_INT_P (XEXP (src
, 1))
9150 && UINTVAL (XEXP (src
, 1))
9151 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9152 src
= XEXP (src
, 0);
9154 return gen_rtx_SET (VOIDmode
, assign
, src
);
9157 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9161 apply_distributive_law (rtx x
)
9163 enum rtx_code code
= GET_CODE (x
);
9164 enum rtx_code inner_code
;
9165 rtx lhs
, rhs
, other
;
9168 /* Distributivity is not true for floating point as it can change the
9169 value. So we don't do it unless -funsafe-math-optimizations. */
9170 if (FLOAT_MODE_P (GET_MODE (x
))
9171 && ! flag_unsafe_math_optimizations
)
9174 /* The outer operation can only be one of the following: */
9175 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9176 && code
!= PLUS
&& code
!= MINUS
)
9182 /* If either operand is a primitive we can't do anything, so get out
9184 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9187 lhs
= expand_compound_operation (lhs
);
9188 rhs
= expand_compound_operation (rhs
);
9189 inner_code
= GET_CODE (lhs
);
9190 if (inner_code
!= GET_CODE (rhs
))
9193 /* See if the inner and outer operations distribute. */
9200 /* These all distribute except over PLUS. */
9201 if (code
== PLUS
|| code
== MINUS
)
9206 if (code
!= PLUS
&& code
!= MINUS
)
9211 /* This is also a multiply, so it distributes over everything. */
9214 /* This used to handle SUBREG, but this turned out to be counter-
9215 productive, since (subreg (op ...)) usually is not handled by
9216 insn patterns, and this "optimization" therefore transformed
9217 recognizable patterns into unrecognizable ones. Therefore the
9218 SUBREG case was removed from here.
9220 It is possible that distributing SUBREG over arithmetic operations
9221 leads to an intermediate result than can then be optimized further,
9222 e.g. by moving the outer SUBREG to the other side of a SET as done
9223 in simplify_set. This seems to have been the original intent of
9224 handling SUBREGs here.
9226 However, with current GCC this does not appear to actually happen,
9227 at least on major platforms. If some case is found where removing
9228 the SUBREG case here prevents follow-on optimizations, distributing
9229 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9235 /* Set LHS and RHS to the inner operands (A and B in the example
9236 above) and set OTHER to the common operand (C in the example).
9237 There is only one way to do this unless the inner operation is
9239 if (COMMUTATIVE_ARITH_P (lhs
)
9240 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9241 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9242 else if (COMMUTATIVE_ARITH_P (lhs
)
9243 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9244 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9245 else if (COMMUTATIVE_ARITH_P (lhs
)
9246 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9247 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9248 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9249 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9253 /* Form the new inner operation, seeing if it simplifies first. */
9254 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9256 /* There is one exception to the general way of distributing:
9257 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9258 if (code
== XOR
&& inner_code
== IOR
)
9261 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9264 /* We may be able to continuing distributing the result, so call
9265 ourselves recursively on the inner operation before forming the
9266 outer operation, which we return. */
9267 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9268 apply_distributive_law (tem
), other
);
9271 /* See if X is of the form (* (+ A B) C), and if so convert to
9272 (+ (* A C) (* B C)) and try to simplify.
9274 Most of the time, this results in no change. However, if some of
9275 the operands are the same or inverses of each other, simplifications
9278 For example, (and (ior A B) (not B)) can occur as the result of
9279 expanding a bit field assignment. When we apply the distributive
9280 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9281 which then simplifies to (and (A (not B))).
9283 Note that no checks happen on the validity of applying the inverse
9284 distributive law. This is pointless since we can do it in the
9285 few places where this routine is called.
9287 N is the index of the term that is decomposed (the arithmetic operation,
9288 i.e. (+ A B) in the first example above). !N is the index of the term that
9289 is distributed, i.e. of C in the first example above. */
9291 distribute_and_simplify_rtx (rtx x
, int n
)
9293 enum machine_mode mode
;
9294 enum rtx_code outer_code
, inner_code
;
9295 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9297 /* Distributivity is not true for floating point as it can change the
9298 value. So we don't do it unless -funsafe-math-optimizations. */
9299 if (FLOAT_MODE_P (GET_MODE (x
))
9300 && ! flag_unsafe_math_optimizations
)
9303 decomposed
= XEXP (x
, n
);
9304 if (!ARITHMETIC_P (decomposed
))
9307 mode
= GET_MODE (x
);
9308 outer_code
= GET_CODE (x
);
9309 distributed
= XEXP (x
, !n
);
9311 inner_code
= GET_CODE (decomposed
);
9312 inner_op0
= XEXP (decomposed
, 0);
9313 inner_op1
= XEXP (decomposed
, 1);
9315 /* Special case (and (xor B C) (not A)), which is equivalent to
9316 (xor (ior A B) (ior A C)) */
9317 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9319 distributed
= XEXP (distributed
, 0);
9325 /* Distribute the second term. */
9326 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9327 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9331 /* Distribute the first term. */
9332 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9333 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9336 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9338 if (GET_CODE (tmp
) != outer_code
9339 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9340 < set_src_cost (x
, optimize_this_for_speed_p
)))
9346 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9347 in MODE. Return an equivalent form, if different from (and VAROP
9348 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9351 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9352 unsigned HOST_WIDE_INT constop
)
9354 unsigned HOST_WIDE_INT nonzero
;
9355 unsigned HOST_WIDE_INT orig_constop
;
9360 orig_constop
= constop
;
9361 if (GET_CODE (varop
) == CLOBBER
)
9364 /* Simplify VAROP knowing that we will be only looking at some of the
9367 Note by passing in CONSTOP, we guarantee that the bits not set in
9368 CONSTOP are not significant and will never be examined. We must
9369 ensure that is the case by explicitly masking out those bits
9370 before returning. */
9371 varop
= force_to_mode (varop
, mode
, constop
, 0);
9373 /* If VAROP is a CLOBBER, we will fail so return it. */
9374 if (GET_CODE (varop
) == CLOBBER
)
9377 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9378 to VAROP and return the new constant. */
9379 if (CONST_INT_P (varop
))
9380 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9382 /* See what bits may be nonzero in VAROP. Unlike the general case of
9383 a call to nonzero_bits, here we don't care about bits outside
9386 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9388 /* Turn off all bits in the constant that are known to already be zero.
9389 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9390 which is tested below. */
9394 /* If we don't have any bits left, return zero. */
9398 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9399 a power of two, we can replace this with an ASHIFT. */
9400 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9401 && (i
= exact_log2 (constop
)) >= 0)
9402 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9404 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9405 or XOR, then try to apply the distributive law. This may eliminate
9406 operations if either branch can be simplified because of the AND.
9407 It may also make some cases more complex, but those cases probably
9408 won't match a pattern either with or without this. */
9410 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9414 apply_distributive_law
9415 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9416 simplify_and_const_int (NULL_RTX
,
9420 simplify_and_const_int (NULL_RTX
,
9425 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9426 the AND and see if one of the operands simplifies to zero. If so, we
9427 may eliminate it. */
9429 if (GET_CODE (varop
) == PLUS
9430 && exact_log2 (constop
+ 1) >= 0)
9434 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9435 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9436 if (o0
== const0_rtx
)
9438 if (o1
== const0_rtx
)
9442 /* Make a SUBREG if necessary. If we can't make it, fail. */
9443 varop
= gen_lowpart (mode
, varop
);
9444 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9447 /* If we are only masking insignificant bits, return VAROP. */
9448 if (constop
== nonzero
)
9451 if (varop
== orig_varop
&& constop
== orig_constop
)
9454 /* Otherwise, return an AND. */
9455 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9459 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9462 Return an equivalent form, if different from X. Otherwise, return X. If
9463 X is zero, we are to always construct the equivalent form. */
9466 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9467 unsigned HOST_WIDE_INT constop
)
9469 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9474 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9475 gen_int_mode (constop
, mode
));
9476 if (GET_MODE (x
) != mode
)
9477 x
= gen_lowpart (mode
, x
);
9481 /* Given a REG, X, compute which bits in X can be nonzero.
9482 We don't care about bits outside of those defined in MODE.
9484 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9485 a shift, AND, or zero_extract, we can do better. */
9488 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9489 const_rtx known_x ATTRIBUTE_UNUSED
,
9490 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9491 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9492 unsigned HOST_WIDE_INT
*nonzero
)
9497 /* If X is a register whose nonzero bits value is current, use it.
9498 Otherwise, if X is a register whose value we can find, use that
9499 value. Otherwise, use the previously-computed global nonzero bits
9500 for this register. */
9502 rsp
= ®_stat
[REGNO (x
)];
9503 if (rsp
->last_set_value
!= 0
9504 && (rsp
->last_set_mode
== mode
9505 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9506 && GET_MODE_CLASS (mode
) == MODE_INT
))
9507 && ((rsp
->last_set_label
>= label_tick_ebb_start
9508 && rsp
->last_set_label
< label_tick
)
9509 || (rsp
->last_set_label
== label_tick
9510 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9511 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9512 && REG_N_SETS (REGNO (x
)) == 1
9514 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9517 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9519 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9520 /* We don't know anything about the upper bits. */
9521 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9527 tem
= get_last_value (x
);
9531 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9532 /* If X is narrower than MODE and TEM is a non-negative
9533 constant that would appear negative in the mode of X,
9534 sign-extend it for use in reg_nonzero_bits because some
9535 machines (maybe most) will actually do the sign-extension
9536 and this is the conservative approach.
9538 ??? For 2.5, try to tighten up the MD files in this regard
9539 instead of this kludge. */
9541 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9542 && CONST_INT_P (tem
)
9544 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9545 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9549 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9551 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9553 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9554 /* We don't know anything about the upper bits. */
9555 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9563 /* Return the number of bits at the high-order end of X that are known to
9564 be equal to the sign bit. X will be used in mode MODE; if MODE is
9565 VOIDmode, X will be used in its own mode. The returned value will always
9566 be between 1 and the number of bits in MODE. */
9569 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9570 const_rtx known_x ATTRIBUTE_UNUSED
,
9571 enum machine_mode known_mode
9573 unsigned int known_ret ATTRIBUTE_UNUSED
,
9574 unsigned int *result
)
9579 rsp
= ®_stat
[REGNO (x
)];
9580 if (rsp
->last_set_value
!= 0
9581 && rsp
->last_set_mode
== mode
9582 && ((rsp
->last_set_label
>= label_tick_ebb_start
9583 && rsp
->last_set_label
< label_tick
)
9584 || (rsp
->last_set_label
== label_tick
9585 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9586 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9587 && REG_N_SETS (REGNO (x
)) == 1
9589 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9592 *result
= rsp
->last_set_sign_bit_copies
;
9596 tem
= get_last_value (x
);
9600 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9601 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9602 *result
= rsp
->sign_bit_copies
;
9607 /* Return the number of "extended" bits there are in X, when interpreted
9608 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9609 unsigned quantities, this is the number of high-order zero bits.
9610 For signed quantities, this is the number of copies of the sign bit
9611 minus 1. In both case, this function returns the number of "spare"
9612 bits. For example, if two quantities for which this function returns
9613 at least 1 are added, the addition is known not to overflow.
9615 This function will always return 0 unless called during combine, which
9616 implies that it must be called from a define_split. */
9619 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9621 if (nonzero_sign_valid
== 0)
9625 ? (HWI_COMPUTABLE_MODE_P (mode
)
9626 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9627 - floor_log2 (nonzero_bits (x
, mode
)))
9629 : num_sign_bit_copies (x
, mode
) - 1);
9632 /* This function is called from `simplify_shift_const' to merge two
9633 outer operations. Specifically, we have already found that we need
9634 to perform operation *POP0 with constant *PCONST0 at the outermost
9635 position. We would now like to also perform OP1 with constant CONST1
9636 (with *POP0 being done last).
9638 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9639 the resulting operation. *PCOMP_P is set to 1 if we would need to
9640 complement the innermost operand, otherwise it is unchanged.
9642 MODE is the mode in which the operation will be done. No bits outside
9643 the width of this mode matter. It is assumed that the width of this mode
9644 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9646 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9647 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9648 result is simply *PCONST0.
9650 If the resulting operation cannot be expressed as one operation, we
9651 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9654 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9656 enum rtx_code op0
= *pop0
;
9657 HOST_WIDE_INT const0
= *pconst0
;
9659 const0
&= GET_MODE_MASK (mode
);
9660 const1
&= GET_MODE_MASK (mode
);
9662 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9666 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9669 if (op1
== UNKNOWN
|| op0
== SET
)
9672 else if (op0
== UNKNOWN
)
9673 op0
= op1
, const0
= const1
;
9675 else if (op0
== op1
)
9699 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9700 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9703 /* If the two constants aren't the same, we can't do anything. The
9704 remaining six cases can all be done. */
9705 else if (const0
!= const1
)
9713 /* (a & b) | b == b */
9715 else /* op1 == XOR */
9716 /* (a ^ b) | b == a | b */
9722 /* (a & b) ^ b == (~a) & b */
9723 op0
= AND
, *pcomp_p
= 1;
9724 else /* op1 == IOR */
9725 /* (a | b) ^ b == a & ~b */
9726 op0
= AND
, const0
= ~const0
;
9731 /* (a | b) & b == b */
9733 else /* op1 == XOR */
9734 /* (a ^ b) & b) == (~a) & b */
9741 /* Check for NO-OP cases. */
9742 const0
&= GET_MODE_MASK (mode
);
9744 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9746 else if (const0
== 0 && op0
== AND
)
9748 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9754 /* ??? Slightly redundant with the above mask, but not entirely.
9755 Moving this above means we'd have to sign-extend the mode mask
9756 for the final test. */
9757 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9758 *pconst0
= trunc_int_for_mode (const0
, mode
);
9763 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9764 the shift in. The original shift operation CODE is performed on OP in
9765 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9766 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9767 result of the shift is subject to operation OUTER_CODE with operand
9770 static enum machine_mode
9771 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9772 enum machine_mode orig_mode
, enum machine_mode mode
,
9773 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9775 if (orig_mode
== mode
)
9777 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9779 /* In general we can't perform in wider mode for right shift and rotate. */
9783 /* We can still widen if the bits brought in from the left are identical
9784 to the sign bit of ORIG_MODE. */
9785 if (num_sign_bit_copies (op
, mode
)
9786 > (unsigned) (GET_MODE_PRECISION (mode
)
9787 - GET_MODE_PRECISION (orig_mode
)))
9792 /* Similarly here but with zero bits. */
9793 if (HWI_COMPUTABLE_MODE_P (mode
)
9794 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9797 /* We can also widen if the bits brought in will be masked off. This
9798 operation is performed in ORIG_MODE. */
9799 if (outer_code
== AND
)
9801 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9804 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9820 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9821 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9822 if we cannot simplify it. Otherwise, return a simplified value.
9824 The shift is normally computed in the widest mode we find in VAROP, as
9825 long as it isn't a different number of words than RESULT_MODE. Exceptions
9826 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9829 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9830 rtx varop
, int orig_count
)
9832 enum rtx_code orig_code
= code
;
9833 rtx orig_varop
= varop
;
9835 enum machine_mode mode
= result_mode
;
9836 enum machine_mode shift_mode
, tmode
;
9837 unsigned int mode_words
9838 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9839 /* We form (outer_op (code varop count) (outer_const)). */
9840 enum rtx_code outer_op
= UNKNOWN
;
9841 HOST_WIDE_INT outer_const
= 0;
9842 int complement_p
= 0;
9845 /* Make sure and truncate the "natural" shift on the way in. We don't
9846 want to do this inside the loop as it makes it more difficult to
9848 if (SHIFT_COUNT_TRUNCATED
)
9849 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9851 /* If we were given an invalid count, don't do anything except exactly
9852 what was requested. */
9854 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9859 /* Unless one of the branches of the `if' in this loop does a `continue',
9860 we will `break' the loop after the `if'. */
9864 /* If we have an operand of (clobber (const_int 0)), fail. */
9865 if (GET_CODE (varop
) == CLOBBER
)
9868 /* Convert ROTATERT to ROTATE. */
9869 if (code
== ROTATERT
)
9871 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9873 if (VECTOR_MODE_P (result_mode
))
9874 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9876 count
= bitsize
- count
;
9879 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9880 mode
, outer_op
, outer_const
);
9882 /* Handle cases where the count is greater than the size of the mode
9883 minus 1. For ASHIFT, use the size minus one as the count (this can
9884 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9885 take the count modulo the size. For other shifts, the result is
9888 Since these shifts are being produced by the compiler by combining
9889 multiple operations, each of which are defined, we know what the
9890 result is supposed to be. */
9892 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9894 if (code
== ASHIFTRT
)
9895 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9896 else if (code
== ROTATE
|| code
== ROTATERT
)
9897 count
%= GET_MODE_PRECISION (shift_mode
);
9900 /* We can't simply return zero because there may be an
9908 /* If we discovered we had to complement VAROP, leave. Making a NOT
9909 here would cause an infinite loop. */
9913 /* An arithmetic right shift of a quantity known to be -1 or 0
9915 if (code
== ASHIFTRT
9916 && (num_sign_bit_copies (varop
, shift_mode
)
9917 == GET_MODE_PRECISION (shift_mode
)))
9923 /* If we are doing an arithmetic right shift and discarding all but
9924 the sign bit copies, this is equivalent to doing a shift by the
9925 bitsize minus one. Convert it into that shift because it will often
9926 allow other simplifications. */
9928 if (code
== ASHIFTRT
9929 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9930 >= GET_MODE_PRECISION (shift_mode
)))
9931 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9933 /* We simplify the tests below and elsewhere by converting
9934 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9935 `make_compound_operation' will convert it to an ASHIFTRT for
9936 those machines (such as VAX) that don't have an LSHIFTRT. */
9937 if (code
== ASHIFTRT
9938 && val_signbit_known_clear_p (shift_mode
,
9939 nonzero_bits (varop
, shift_mode
)))
9942 if (((code
== LSHIFTRT
9943 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9944 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9946 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9947 && !((nonzero_bits (varop
, shift_mode
) << count
)
9948 & GET_MODE_MASK (shift_mode
))))
9949 && !side_effects_p (varop
))
9952 switch (GET_CODE (varop
))
9958 new_rtx
= expand_compound_operation (varop
);
9959 if (new_rtx
!= varop
)
9967 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9968 minus the width of a smaller mode, we can do this with a
9969 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9970 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9971 && ! mode_dependent_address_p (XEXP (varop
, 0),
9972 MEM_ADDR_SPACE (varop
))
9973 && ! MEM_VOLATILE_P (varop
)
9974 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9975 MODE_INT
, 1)) != BLKmode
)
9977 new_rtx
= adjust_address_nv (varop
, tmode
,
9978 BYTES_BIG_ENDIAN
? 0
9979 : count
/ BITS_PER_UNIT
);
9981 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9982 : ZERO_EXTEND
, mode
, new_rtx
);
9989 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9990 the same number of words as what we've seen so far. Then store
9991 the widest mode in MODE. */
9992 if (subreg_lowpart_p (varop
)
9993 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9994 > GET_MODE_SIZE (GET_MODE (varop
)))
9995 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9996 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9998 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9999 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10001 varop
= SUBREG_REG (varop
);
10002 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10003 mode
= GET_MODE (varop
);
10009 /* Some machines use MULT instead of ASHIFT because MULT
10010 is cheaper. But it is still better on those machines to
10011 merge two shifts into one. */
10012 if (CONST_INT_P (XEXP (varop
, 1))
10013 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10016 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10018 GEN_INT (exact_log2 (
10019 UINTVAL (XEXP (varop
, 1)))));
10025 /* Similar, for when divides are cheaper. */
10026 if (CONST_INT_P (XEXP (varop
, 1))
10027 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10030 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10032 GEN_INT (exact_log2 (
10033 UINTVAL (XEXP (varop
, 1)))));
10039 /* If we are extracting just the sign bit of an arithmetic
10040 right shift, that shift is not needed. However, the sign
10041 bit of a wider mode may be different from what would be
10042 interpreted as the sign bit in a narrower mode, so, if
10043 the result is narrower, don't discard the shift. */
10044 if (code
== LSHIFTRT
10045 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10046 && (GET_MODE_BITSIZE (result_mode
)
10047 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10049 varop
= XEXP (varop
, 0);
10053 /* ... fall through ... */
10058 /* Here we have two nested shifts. The result is usually the
10059 AND of a new shift with a mask. We compute the result below. */
10060 if (CONST_INT_P (XEXP (varop
, 1))
10061 && INTVAL (XEXP (varop
, 1)) >= 0
10062 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10063 && HWI_COMPUTABLE_MODE_P (result_mode
)
10064 && HWI_COMPUTABLE_MODE_P (mode
)
10065 && !VECTOR_MODE_P (result_mode
))
10067 enum rtx_code first_code
= GET_CODE (varop
);
10068 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10069 unsigned HOST_WIDE_INT mask
;
10072 /* We have one common special case. We can't do any merging if
10073 the inner code is an ASHIFTRT of a smaller mode. However, if
10074 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10075 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10076 we can convert it to
10077 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10078 This simplifies certain SIGN_EXTEND operations. */
10079 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10080 && count
== (GET_MODE_PRECISION (result_mode
)
10081 - GET_MODE_PRECISION (GET_MODE (varop
))))
10083 /* C3 has the low-order C1 bits zero. */
10085 mask
= GET_MODE_MASK (mode
)
10086 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10088 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10089 XEXP (varop
, 0), mask
);
10090 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10092 count
= first_count
;
10097 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10098 than C1 high-order bits equal to the sign bit, we can convert
10099 this to either an ASHIFT or an ASHIFTRT depending on the
10102 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10104 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10105 && GET_MODE (varop
) == shift_mode
10106 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10109 varop
= XEXP (varop
, 0);
10110 count
-= first_count
;
10120 /* There are some cases we can't do. If CODE is ASHIFTRT,
10121 we can only do this if FIRST_CODE is also ASHIFTRT.
10123 We can't do the case when CODE is ROTATE and FIRST_CODE is
10126 If the mode of this shift is not the mode of the outer shift,
10127 we can't do this if either shift is a right shift or ROTATE.
10129 Finally, we can't do any of these if the mode is too wide
10130 unless the codes are the same.
10132 Handle the case where the shift codes are the same
10135 if (code
== first_code
)
10137 if (GET_MODE (varop
) != result_mode
10138 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10139 || code
== ROTATE
))
10142 count
+= first_count
;
10143 varop
= XEXP (varop
, 0);
10147 if (code
== ASHIFTRT
10148 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10149 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10150 || (GET_MODE (varop
) != result_mode
10151 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10152 || first_code
== ROTATE
10153 || code
== ROTATE
)))
10156 /* To compute the mask to apply after the shift, shift the
10157 nonzero bits of the inner shift the same way the
10158 outer shift will. */
10160 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10164 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10167 /* Give up if we can't compute an outer operation to use. */
10169 || !CONST_INT_P (mask_rtx
)
10170 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10172 result_mode
, &complement_p
))
10175 /* If the shifts are in the same direction, we add the
10176 counts. Otherwise, we subtract them. */
10177 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10178 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10179 count
+= first_count
;
10181 count
-= first_count
;
10183 /* If COUNT is positive, the new shift is usually CODE,
10184 except for the two exceptions below, in which case it is
10185 FIRST_CODE. If the count is negative, FIRST_CODE should
10188 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10189 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10191 else if (count
< 0)
10192 code
= first_code
, count
= -count
;
10194 varop
= XEXP (varop
, 0);
10198 /* If we have (A << B << C) for any shift, we can convert this to
10199 (A << C << B). This wins if A is a constant. Only try this if
10200 B is not a constant. */
10202 else if (GET_CODE (varop
) == code
10203 && CONST_INT_P (XEXP (varop
, 0))
10204 && !CONST_INT_P (XEXP (varop
, 1)))
10206 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10209 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10216 if (VECTOR_MODE_P (mode
))
10219 /* Make this fit the case below. */
10220 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10226 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10227 with C the size of VAROP - 1 and the shift is logical if
10228 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10229 we have an (le X 0) operation. If we have an arithmetic shift
10230 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10231 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10233 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10234 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10235 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10236 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10237 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10238 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10241 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10244 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10245 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10250 /* If we have (shift (logical)), move the logical to the outside
10251 to allow it to possibly combine with another logical and the
10252 shift to combine with another shift. This also canonicalizes to
10253 what a ZERO_EXTRACT looks like. Also, some machines have
10254 (and (shift)) insns. */
10256 if (CONST_INT_P (XEXP (varop
, 1))
10257 /* We can't do this if we have (ashiftrt (xor)) and the
10258 constant has its sign bit set in shift_mode with shift_mode
10259 wider than result_mode. */
10260 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10261 && result_mode
!= shift_mode
10262 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10264 && (new_rtx
= simplify_const_binary_operation
10265 (code
, result_mode
,
10266 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10267 GEN_INT (count
))) != 0
10268 && CONST_INT_P (new_rtx
)
10269 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10270 INTVAL (new_rtx
), result_mode
, &complement_p
))
10272 varop
= XEXP (varop
, 0);
10276 /* If we can't do that, try to simplify the shift in each arm of the
10277 logical expression, make a new logical expression, and apply
10278 the inverse distributive law. This also can't be done for
10279 (ashiftrt (xor)) where we've widened the shift and the constant
10280 changes the sign bit. */
10281 if (CONST_INT_P (XEXP (varop
, 1))
10282 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10283 && result_mode
!= shift_mode
10284 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10287 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10288 XEXP (varop
, 0), count
);
10289 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10290 XEXP (varop
, 1), count
);
10292 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10294 varop
= apply_distributive_law (varop
);
10302 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10303 says that the sign bit can be tested, FOO has mode MODE, C is
10304 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10305 that may be nonzero. */
10306 if (code
== LSHIFTRT
10307 && XEXP (varop
, 1) == const0_rtx
10308 && GET_MODE (XEXP (varop
, 0)) == result_mode
10309 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10310 && HWI_COMPUTABLE_MODE_P (result_mode
)
10311 && STORE_FLAG_VALUE
== -1
10312 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10313 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10316 varop
= XEXP (varop
, 0);
10323 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10324 than the number of bits in the mode is equivalent to A. */
10325 if (code
== LSHIFTRT
10326 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10327 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10329 varop
= XEXP (varop
, 0);
10334 /* NEG commutes with ASHIFT since it is multiplication. Move the
10335 NEG outside to allow shifts to combine. */
10337 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10340 varop
= XEXP (varop
, 0);
10346 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10347 is one less than the number of bits in the mode is
10348 equivalent to (xor A 1). */
10349 if (code
== LSHIFTRT
10350 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10351 && XEXP (varop
, 1) == constm1_rtx
10352 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10353 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10357 varop
= XEXP (varop
, 0);
10361 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10362 that might be nonzero in BAR are those being shifted out and those
10363 bits are known zero in FOO, we can replace the PLUS with FOO.
10364 Similarly in the other operand order. This code occurs when
10365 we are computing the size of a variable-size array. */
10367 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10368 && count
< HOST_BITS_PER_WIDE_INT
10369 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10370 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10371 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10373 varop
= XEXP (varop
, 0);
10376 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10377 && count
< HOST_BITS_PER_WIDE_INT
10378 && HWI_COMPUTABLE_MODE_P (result_mode
)
10379 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10381 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10382 & nonzero_bits (XEXP (varop
, 1),
10385 varop
= XEXP (varop
, 1);
10389 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10391 && CONST_INT_P (XEXP (varop
, 1))
10392 && (new_rtx
= simplify_const_binary_operation
10393 (ASHIFT
, result_mode
,
10394 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10395 GEN_INT (count
))) != 0
10396 && CONST_INT_P (new_rtx
)
10397 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10398 INTVAL (new_rtx
), result_mode
, &complement_p
))
10400 varop
= XEXP (varop
, 0);
10404 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10405 signbit', and attempt to change the PLUS to an XOR and move it to
10406 the outer operation as is done above in the AND/IOR/XOR case
10407 leg for shift(logical). See details in logical handling above
10408 for reasoning in doing so. */
10409 if (code
== LSHIFTRT
10410 && CONST_INT_P (XEXP (varop
, 1))
10411 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10412 && (new_rtx
= simplify_const_binary_operation
10413 (code
, result_mode
,
10414 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10415 GEN_INT (count
))) != 0
10416 && CONST_INT_P (new_rtx
)
10417 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10418 INTVAL (new_rtx
), result_mode
, &complement_p
))
10420 varop
= XEXP (varop
, 0);
10427 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10428 with C the size of VAROP - 1 and the shift is logical if
10429 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10430 we have a (gt X 0) operation. If the shift is arithmetic with
10431 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10432 we have a (neg (gt X 0)) operation. */
10434 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10435 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10436 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10437 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10438 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10439 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10440 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10443 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10446 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10447 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10454 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10455 if the truncate does not affect the value. */
10456 if (code
== LSHIFTRT
10457 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10458 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10459 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10460 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10461 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10463 rtx varop_inner
= XEXP (varop
, 0);
10466 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10467 XEXP (varop_inner
, 0),
10469 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10470 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10483 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10484 outer_op
, outer_const
);
10486 /* We have now finished analyzing the shift. The result should be
10487 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10488 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10489 to the result of the shift. OUTER_CONST is the relevant constant,
10490 but we must turn off all bits turned off in the shift. */
10492 if (outer_op
== UNKNOWN
10493 && orig_code
== code
&& orig_count
== count
10494 && varop
== orig_varop
10495 && shift_mode
== GET_MODE (varop
))
10498 /* Make a SUBREG if necessary. If we can't make it, fail. */
10499 varop
= gen_lowpart (shift_mode
, varop
);
10500 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10503 /* If we have an outer operation and we just made a shift, it is
10504 possible that we could have simplified the shift were it not
10505 for the outer operation. So try to do the simplification
10508 if (outer_op
!= UNKNOWN
)
10509 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10514 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10516 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10517 turn off all the bits that the shift would have turned off. */
10518 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10519 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10520 GET_MODE_MASK (result_mode
) >> orig_count
);
10522 /* Do the remainder of the processing in RESULT_MODE. */
10523 x
= gen_lowpart_or_truncate (result_mode
, x
);
10525 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10528 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10530 if (outer_op
!= UNKNOWN
)
10532 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10533 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10534 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10536 if (outer_op
== AND
)
10537 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10538 else if (outer_op
== SET
)
10540 /* This means that we have determined that the result is
10541 equivalent to a constant. This should be rare. */
10542 if (!side_effects_p (x
))
10543 x
= GEN_INT (outer_const
);
10545 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10546 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10548 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10549 GEN_INT (outer_const
));
10555 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10556 The result of the shift is RESULT_MODE. If we cannot simplify it,
10557 return X or, if it is NULL, synthesize the expression with
10558 simplify_gen_binary. Otherwise, return a simplified value.
10560 The shift is normally computed in the widest mode we find in VAROP, as
10561 long as it isn't a different number of words than RESULT_MODE. Exceptions
10562 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10565 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10566 rtx varop
, int count
)
10568 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10573 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10574 if (GET_MODE (x
) != result_mode
)
10575 x
= gen_lowpart (result_mode
, x
);
10580 /* Like recog, but we receive the address of a pointer to a new pattern.
10581 We try to match the rtx that the pointer points to.
10582 If that fails, we may try to modify or replace the pattern,
10583 storing the replacement into the same pointer object.
10585 Modifications include deletion or addition of CLOBBERs.
10587 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10588 the CLOBBERs are placed.
10590 The value is the final insn code from the pattern ultimately matched,
10594 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10596 rtx pat
= *pnewpat
;
10597 rtx pat_without_clobbers
;
10598 int insn_code_number
;
10599 int num_clobbers_to_add
= 0;
10601 rtx notes
= NULL_RTX
;
10602 rtx old_notes
, old_pat
;
10605 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10606 we use to indicate that something didn't match. If we find such a
10607 thing, force rejection. */
10608 if (GET_CODE (pat
) == PARALLEL
)
10609 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10610 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10611 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10614 old_pat
= PATTERN (insn
);
10615 old_notes
= REG_NOTES (insn
);
10616 PATTERN (insn
) = pat
;
10617 REG_NOTES (insn
) = NULL_RTX
;
10619 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10620 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10622 if (insn_code_number
< 0)
10623 fputs ("Failed to match this instruction:\n", dump_file
);
10625 fputs ("Successfully matched this instruction:\n", dump_file
);
10626 print_rtl_single (dump_file
, pat
);
10629 /* If it isn't, there is the possibility that we previously had an insn
10630 that clobbered some register as a side effect, but the combined
10631 insn doesn't need to do that. So try once more without the clobbers
10632 unless this represents an ASM insn. */
10634 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10635 && GET_CODE (pat
) == PARALLEL
)
10639 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10640 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10643 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10647 SUBST_INT (XVECLEN (pat
, 0), pos
);
10650 pat
= XVECEXP (pat
, 0, 0);
10652 PATTERN (insn
) = pat
;
10653 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10654 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10656 if (insn_code_number
< 0)
10657 fputs ("Failed to match this instruction:\n", dump_file
);
10659 fputs ("Successfully matched this instruction:\n", dump_file
);
10660 print_rtl_single (dump_file
, pat
);
10664 pat_without_clobbers
= pat
;
10666 PATTERN (insn
) = old_pat
;
10667 REG_NOTES (insn
) = old_notes
;
10669 /* Recognize all noop sets, these will be killed by followup pass. */
10670 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10671 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10673 /* If we had any clobbers to add, make a new pattern than contains
10674 them. Then check to make sure that all of them are dead. */
10675 if (num_clobbers_to_add
)
10677 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10678 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10679 ? (XVECLEN (pat
, 0)
10680 + num_clobbers_to_add
)
10681 : num_clobbers_to_add
+ 1));
10683 if (GET_CODE (pat
) == PARALLEL
)
10684 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10685 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10687 XVECEXP (newpat
, 0, 0) = pat
;
10689 add_clobbers (newpat
, insn_code_number
);
10691 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10692 i
< XVECLEN (newpat
, 0); i
++)
10694 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10695 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10697 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10699 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10700 notes
= alloc_reg_note (REG_UNUSED
,
10701 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10707 if (insn_code_number
>= 0
10708 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10710 old_pat
= PATTERN (insn
);
10711 old_notes
= REG_NOTES (insn
);
10712 old_icode
= INSN_CODE (insn
);
10713 PATTERN (insn
) = pat
;
10714 REG_NOTES (insn
) = notes
;
10716 /* Allow targets to reject combined insn. */
10717 if (!targetm
.legitimate_combined_insn (insn
))
10719 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10720 fputs ("Instruction not appropriate for target.",
10723 /* Callers expect recog_for_combine to strip
10724 clobbers from the pattern on failure. */
10725 pat
= pat_without_clobbers
;
10728 insn_code_number
= -1;
10731 PATTERN (insn
) = old_pat
;
10732 REG_NOTES (insn
) = old_notes
;
10733 INSN_CODE (insn
) = old_icode
;
10739 return insn_code_number
;
10742 /* Like gen_lowpart_general but for use by combine. In combine it
10743 is not possible to create any new pseudoregs. However, it is
10744 safe to create invalid memory addresses, because combine will
10745 try to recognize them and all they will do is make the combine
10748 If for some reason this cannot do its job, an rtx
10749 (clobber (const_int 0)) is returned.
10750 An insn containing that will not be recognized. */
10753 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10755 enum machine_mode imode
= GET_MODE (x
);
10756 unsigned int osize
= GET_MODE_SIZE (omode
);
10757 unsigned int isize
= GET_MODE_SIZE (imode
);
10760 if (omode
== imode
)
10763 /* We can only support MODE being wider than a word if X is a
10764 constant integer or has a mode the same size. */
10765 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10766 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10769 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10770 won't know what to do. So we will strip off the SUBREG here and
10771 process normally. */
10772 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10774 x
= SUBREG_REG (x
);
10776 /* For use in case we fall down into the address adjustments
10777 further below, we need to adjust the known mode and size of
10778 x; imode and isize, since we just adjusted x. */
10779 imode
= GET_MODE (x
);
10781 if (imode
== omode
)
10784 isize
= GET_MODE_SIZE (imode
);
10787 result
= gen_lowpart_common (omode
, x
);
10796 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10798 if (MEM_VOLATILE_P (x
)
10799 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10802 /* If we want to refer to something bigger than the original memref,
10803 generate a paradoxical subreg instead. That will force a reload
10804 of the original memref X. */
10806 return gen_rtx_SUBREG (omode
, x
, 0);
10808 if (WORDS_BIG_ENDIAN
)
10809 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10811 /* Adjust the address so that the address-after-the-data is
10813 if (BYTES_BIG_ENDIAN
)
10814 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10816 return adjust_address_nv (x
, omode
, offset
);
10819 /* If X is a comparison operator, rewrite it in a new mode. This
10820 probably won't match, but may allow further simplifications. */
10821 else if (COMPARISON_P (x
))
10822 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10824 /* If we couldn't simplify X any other way, just enclose it in a
10825 SUBREG. Normally, this SUBREG won't match, but some patterns may
10826 include an explicit SUBREG or we may simplify it further in combine. */
10832 offset
= subreg_lowpart_offset (omode
, imode
);
10833 if (imode
== VOIDmode
)
10835 imode
= int_mode_for_mode (omode
);
10836 x
= gen_lowpart_common (imode
, x
);
10840 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10846 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10849 /* Try to simplify a comparison between OP0 and a constant OP1,
10850 where CODE is the comparison code that will be tested, into a
10851 (CODE OP0 const0_rtx) form.
10853 The result is a possibly different comparison code to use.
10854 *POP1 may be updated. */
10856 static enum rtx_code
10857 simplify_compare_const (enum rtx_code code
, enum machine_mode mode
,
10858 rtx op0
, rtx
*pop1
)
10860 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10861 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10863 /* Get the constant we are comparing against and turn off all bits
10864 not on in our mode. */
10865 if (mode
!= VOIDmode
)
10866 const_op
= trunc_int_for_mode (const_op
, mode
);
10868 /* If we are comparing against a constant power of two and the value
10869 being compared can only have that single bit nonzero (e.g., it was
10870 `and'ed with that bit), we can replace this with a comparison
10873 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10874 || code
== LT
|| code
== LTU
)
10875 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10876 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10877 && (nonzero_bits (op0
, mode
)
10878 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10880 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10884 /* Similarly, if we are comparing a value known to be either -1 or
10885 0 with -1, change it to the opposite comparison against zero. */
10887 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10888 || code
== GEU
|| code
== LTU
)
10889 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10891 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10895 /* Do some canonicalizations based on the comparison code. We prefer
10896 comparisons against zero and then prefer equality comparisons.
10897 If we can reduce the size of a constant, we will do that too. */
10901 /* < C is equivalent to <= (C - 1) */
10906 /* ... fall through to LE case below. */
10912 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10919 /* If we are doing a <= 0 comparison on a value known to have
10920 a zero sign bit, we can replace this with == 0. */
10921 else if (const_op
== 0
10922 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10923 && (nonzero_bits (op0
, mode
)
10924 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10930 /* >= C is equivalent to > (C - 1). */
10935 /* ... fall through to GT below. */
10941 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10948 /* If we are doing a > 0 comparison on a value known to have
10949 a zero sign bit, we can replace this with != 0. */
10950 else if (const_op
== 0
10951 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10952 && (nonzero_bits (op0
, mode
)
10953 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10959 /* < C is equivalent to <= (C - 1). */
10964 /* ... fall through ... */
10966 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10967 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10968 && (unsigned HOST_WIDE_INT
) const_op
10969 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10979 /* unsigned <= 0 is equivalent to == 0 */
10982 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10983 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10984 && (unsigned HOST_WIDE_INT
) const_op
10985 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10993 /* >= C is equivalent to > (C - 1). */
10998 /* ... fall through ... */
11001 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11002 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11003 && (unsigned HOST_WIDE_INT
) const_op
11004 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11014 /* unsigned > 0 is equivalent to != 0 */
11017 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11018 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11019 && (unsigned HOST_WIDE_INT
) const_op
11020 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11031 *pop1
= GEN_INT (const_op
);
11035 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11036 comparison code that will be tested.
11038 The result is a possibly different comparison code to use. *POP0 and
11039 *POP1 may be updated.
11041 It is possible that we might detect that a comparison is either always
11042 true or always false. However, we do not perform general constant
11043 folding in combine, so this knowledge isn't useful. Such tautologies
11044 should have been detected earlier. Hence we ignore all such cases. */
11046 static enum rtx_code
11047 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11053 enum machine_mode mode
, tmode
;
11055 /* Try a few ways of applying the same transformation to both operands. */
11058 #ifndef WORD_REGISTER_OPERATIONS
11059 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11060 so check specially. */
11061 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11062 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11063 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11064 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11065 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11066 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11067 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11068 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11069 && CONST_INT_P (XEXP (op0
, 1))
11070 && XEXP (op0
, 1) == XEXP (op1
, 1)
11071 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11072 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11073 && (INTVAL (XEXP (op0
, 1))
11074 == (GET_MODE_PRECISION (GET_MODE (op0
))
11075 - (GET_MODE_PRECISION
11076 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11078 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11079 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11083 /* If both operands are the same constant shift, see if we can ignore the
11084 shift. We can if the shift is a rotate or if the bits shifted out of
11085 this shift are known to be zero for both inputs and if the type of
11086 comparison is compatible with the shift. */
11087 if (GET_CODE (op0
) == GET_CODE (op1
)
11088 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11089 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11090 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11091 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11092 || (GET_CODE (op0
) == ASHIFTRT
11093 && (code
!= GTU
&& code
!= LTU
11094 && code
!= GEU
&& code
!= LEU
)))
11095 && CONST_INT_P (XEXP (op0
, 1))
11096 && INTVAL (XEXP (op0
, 1)) >= 0
11097 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11098 && XEXP (op0
, 1) == XEXP (op1
, 1))
11100 enum machine_mode mode
= GET_MODE (op0
);
11101 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11102 int shift_count
= INTVAL (XEXP (op0
, 1));
11104 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11105 mask
&= (mask
>> shift_count
) << shift_count
;
11106 else if (GET_CODE (op0
) == ASHIFT
)
11107 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11109 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11110 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11111 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11116 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11117 SUBREGs are of the same mode, and, in both cases, the AND would
11118 be redundant if the comparison was done in the narrower mode,
11119 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11120 and the operand's possibly nonzero bits are 0xffffff01; in that case
11121 if we only care about QImode, we don't need the AND). This case
11122 occurs if the output mode of an scc insn is not SImode and
11123 STORE_FLAG_VALUE == 1 (e.g., the 386).
11125 Similarly, check for a case where the AND's are ZERO_EXTEND
11126 operations from some narrower mode even though a SUBREG is not
11129 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11130 && CONST_INT_P (XEXP (op0
, 1))
11131 && CONST_INT_P (XEXP (op1
, 1)))
11133 rtx inner_op0
= XEXP (op0
, 0);
11134 rtx inner_op1
= XEXP (op1
, 0);
11135 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11136 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11139 if (paradoxical_subreg_p (inner_op0
)
11140 && GET_CODE (inner_op1
) == SUBREG
11141 && (GET_MODE (SUBREG_REG (inner_op0
))
11142 == GET_MODE (SUBREG_REG (inner_op1
)))
11143 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11144 <= HOST_BITS_PER_WIDE_INT
)
11145 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11146 GET_MODE (SUBREG_REG (inner_op0
)))))
11147 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11148 GET_MODE (SUBREG_REG (inner_op1
))))))
11150 op0
= SUBREG_REG (inner_op0
);
11151 op1
= SUBREG_REG (inner_op1
);
11153 /* The resulting comparison is always unsigned since we masked
11154 off the original sign bit. */
11155 code
= unsigned_condition (code
);
11161 for (tmode
= GET_CLASS_NARROWEST_MODE
11162 (GET_MODE_CLASS (GET_MODE (op0
)));
11163 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11164 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11166 op0
= gen_lowpart (tmode
, inner_op0
);
11167 op1
= gen_lowpart (tmode
, inner_op1
);
11168 code
= unsigned_condition (code
);
11177 /* If both operands are NOT, we can strip off the outer operation
11178 and adjust the comparison code for swapped operands; similarly for
11179 NEG, except that this must be an equality comparison. */
11180 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11181 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11182 && (code
== EQ
|| code
== NE
)))
11183 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11189 /* If the first operand is a constant, swap the operands and adjust the
11190 comparison code appropriately, but don't do this if the second operand
11191 is already a constant integer. */
11192 if (swap_commutative_operands_p (op0
, op1
))
11194 tem
= op0
, op0
= op1
, op1
= tem
;
11195 code
= swap_condition (code
);
11198 /* We now enter a loop during which we will try to simplify the comparison.
11199 For the most part, we only are concerned with comparisons with zero,
11200 but some things may really be comparisons with zero but not start
11201 out looking that way. */
11203 while (CONST_INT_P (op1
))
11205 enum machine_mode mode
= GET_MODE (op0
);
11206 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11207 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11208 int equality_comparison_p
;
11209 int sign_bit_comparison_p
;
11210 int unsigned_comparison_p
;
11211 HOST_WIDE_INT const_op
;
11213 /* We only want to handle integral modes. This catches VOIDmode,
11214 CCmode, and the floating-point modes. An exception is that we
11215 can handle VOIDmode if OP0 is a COMPARE or a comparison
11218 if (GET_MODE_CLASS (mode
) != MODE_INT
11219 && ! (mode
== VOIDmode
11220 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11223 /* Try to simplify the compare to constant, possibly changing the
11224 comparison op, and/or changing op1 to zero. */
11225 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11226 const_op
= INTVAL (op1
);
11228 /* Compute some predicates to simplify code below. */
11230 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11231 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11232 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11235 /* If this is a sign bit comparison and we can do arithmetic in
11236 MODE, say that we will only be needing the sign bit of OP0. */
11237 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11238 op0
= force_to_mode (op0
, mode
,
11239 (unsigned HOST_WIDE_INT
) 1
11240 << (GET_MODE_PRECISION (mode
) - 1),
11243 /* Now try cases based on the opcode of OP0. If none of the cases
11244 does a "continue", we exit this loop immediately after the
11247 switch (GET_CODE (op0
))
11250 /* If we are extracting a single bit from a variable position in
11251 a constant that has only a single bit set and are comparing it
11252 with zero, we can convert this into an equality comparison
11253 between the position and the location of the single bit. */
11254 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11255 have already reduced the shift count modulo the word size. */
11256 if (!SHIFT_COUNT_TRUNCATED
11257 && CONST_INT_P (XEXP (op0
, 0))
11258 && XEXP (op0
, 1) == const1_rtx
11259 && equality_comparison_p
&& const_op
== 0
11260 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11262 if (BITS_BIG_ENDIAN
)
11263 i
= BITS_PER_WORD
- 1 - i
;
11265 op0
= XEXP (op0
, 2);
11269 /* Result is nonzero iff shift count is equal to I. */
11270 code
= reverse_condition (code
);
11274 /* ... fall through ... */
11277 tem
= expand_compound_operation (op0
);
11286 /* If testing for equality, we can take the NOT of the constant. */
11287 if (equality_comparison_p
11288 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11290 op0
= XEXP (op0
, 0);
11295 /* If just looking at the sign bit, reverse the sense of the
11297 if (sign_bit_comparison_p
)
11299 op0
= XEXP (op0
, 0);
11300 code
= (code
== GE
? LT
: GE
);
11306 /* If testing for equality, we can take the NEG of the constant. */
11307 if (equality_comparison_p
11308 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11310 op0
= XEXP (op0
, 0);
11315 /* The remaining cases only apply to comparisons with zero. */
11319 /* When X is ABS or is known positive,
11320 (neg X) is < 0 if and only if X != 0. */
11322 if (sign_bit_comparison_p
11323 && (GET_CODE (XEXP (op0
, 0)) == ABS
11324 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11325 && (nonzero_bits (XEXP (op0
, 0), mode
)
11326 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11329 op0
= XEXP (op0
, 0);
11330 code
= (code
== LT
? NE
: EQ
);
11334 /* If we have NEG of something whose two high-order bits are the
11335 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11336 if (num_sign_bit_copies (op0
, mode
) >= 2)
11338 op0
= XEXP (op0
, 0);
11339 code
= swap_condition (code
);
11345 /* If we are testing equality and our count is a constant, we
11346 can perform the inverse operation on our RHS. */
11347 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11348 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11349 op1
, XEXP (op0
, 1))) != 0)
11351 op0
= XEXP (op0
, 0);
11356 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11357 a particular bit. Convert it to an AND of a constant of that
11358 bit. This will be converted into a ZERO_EXTRACT. */
11359 if (const_op
== 0 && sign_bit_comparison_p
11360 && CONST_INT_P (XEXP (op0
, 1))
11361 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11363 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11364 ((unsigned HOST_WIDE_INT
) 1
11366 - INTVAL (XEXP (op0
, 1)))));
11367 code
= (code
== LT
? NE
: EQ
);
11371 /* Fall through. */
11374 /* ABS is ignorable inside an equality comparison with zero. */
11375 if (const_op
== 0 && equality_comparison_p
)
11377 op0
= XEXP (op0
, 0);
11383 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11384 (compare FOO CONST) if CONST fits in FOO's mode and we
11385 are either testing inequality or have an unsigned
11386 comparison with ZERO_EXTEND or a signed comparison with
11387 SIGN_EXTEND. But don't do it if we don't have a compare
11388 insn of the given mode, since we'd have to revert it
11389 later on, and then we wouldn't know whether to sign- or
11391 mode
= GET_MODE (XEXP (op0
, 0));
11392 if (GET_MODE_CLASS (mode
) == MODE_INT
11393 && ! unsigned_comparison_p
11394 && HWI_COMPUTABLE_MODE_P (mode
)
11395 && trunc_int_for_mode (const_op
, mode
) == const_op
11396 && have_insn_for (COMPARE
, mode
))
11398 op0
= XEXP (op0
, 0);
11404 /* Check for the case where we are comparing A - C1 with C2, that is
11406 (subreg:MODE (plus (A) (-C1))) op (C2)
11408 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11409 comparison in the wider mode. One of the following two conditions
11410 must be true in order for this to be valid:
11412 1. The mode extension results in the same bit pattern being added
11413 on both sides and the comparison is equality or unsigned. As
11414 C2 has been truncated to fit in MODE, the pattern can only be
11417 2. The mode extension results in the sign bit being copied on
11420 The difficulty here is that we have predicates for A but not for
11421 (A - C1) so we need to check that C1 is within proper bounds so
11422 as to perturbate A as little as possible. */
11424 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11425 && subreg_lowpart_p (op0
)
11426 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11427 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11428 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11430 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11431 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11432 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11435 && (unsigned HOST_WIDE_INT
) c1
11436 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11437 && (equality_comparison_p
|| unsigned_comparison_p
)
11438 /* (A - C1) zero-extends if it is positive and sign-extends
11439 if it is negative, C2 both zero- and sign-extends. */
11440 && ((0 == (nonzero_bits (a
, inner_mode
)
11441 & ~GET_MODE_MASK (mode
))
11443 /* (A - C1) sign-extends if it is positive and 1-extends
11444 if it is negative, C2 both sign- and 1-extends. */
11445 || (num_sign_bit_copies (a
, inner_mode
)
11446 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11449 || ((unsigned HOST_WIDE_INT
) c1
11450 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11451 /* (A - C1) always sign-extends, like C2. */
11452 && num_sign_bit_copies (a
, inner_mode
)
11453 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11454 - (mode_width
- 1))))
11456 op0
= SUBREG_REG (op0
);
11461 /* If the inner mode is narrower and we are extracting the low part,
11462 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11463 if (subreg_lowpart_p (op0
)
11464 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11465 /* Fall through */ ;
11469 /* ... fall through ... */
11472 mode
= GET_MODE (XEXP (op0
, 0));
11473 if (GET_MODE_CLASS (mode
) == MODE_INT
11474 && (unsigned_comparison_p
|| equality_comparison_p
)
11475 && HWI_COMPUTABLE_MODE_P (mode
)
11476 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11478 && have_insn_for (COMPARE
, mode
))
11480 op0
= XEXP (op0
, 0);
11486 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11487 this for equality comparisons due to pathological cases involving
11489 if (equality_comparison_p
11490 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11491 op1
, XEXP (op0
, 1))))
11493 op0
= XEXP (op0
, 0);
11498 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11499 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11500 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11502 op0
= XEXP (XEXP (op0
, 0), 0);
11503 code
= (code
== LT
? EQ
: NE
);
11509 /* We used to optimize signed comparisons against zero, but that
11510 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11511 arrive here as equality comparisons, or (GEU, LTU) are
11512 optimized away. No need to special-case them. */
11514 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11515 (eq B (minus A C)), whichever simplifies. We can only do
11516 this for equality comparisons due to pathological cases involving
11518 if (equality_comparison_p
11519 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11520 XEXP (op0
, 1), op1
)))
11522 op0
= XEXP (op0
, 0);
11527 if (equality_comparison_p
11528 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11529 XEXP (op0
, 0), op1
)))
11531 op0
= XEXP (op0
, 1);
11536 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11537 of bits in X minus 1, is one iff X > 0. */
11538 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11539 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11540 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11541 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11543 op0
= XEXP (op0
, 1);
11544 code
= (code
== GE
? LE
: GT
);
11550 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11551 if C is zero or B is a constant. */
11552 if (equality_comparison_p
11553 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11554 XEXP (op0
, 1), op1
)))
11556 op0
= XEXP (op0
, 0);
11563 case UNEQ
: case LTGT
:
11564 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11565 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11566 case UNORDERED
: case ORDERED
:
11567 /* We can't do anything if OP0 is a condition code value, rather
11568 than an actual data value. */
11570 || CC0_P (XEXP (op0
, 0))
11571 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11574 /* Get the two operands being compared. */
11575 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11576 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11578 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11580 /* Check for the cases where we simply want the result of the
11581 earlier test or the opposite of that result. */
11582 if (code
== NE
|| code
== EQ
11583 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11584 && (code
== LT
|| code
== GE
)))
11586 enum rtx_code new_code
;
11587 if (code
== LT
|| code
== NE
)
11588 new_code
= GET_CODE (op0
);
11590 new_code
= reversed_comparison_code (op0
, NULL
);
11592 if (new_code
!= UNKNOWN
)
11603 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11605 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11606 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11607 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11609 op0
= XEXP (op0
, 1);
11610 code
= (code
== GE
? GT
: LE
);
11616 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11617 will be converted to a ZERO_EXTRACT later. */
11618 if (const_op
== 0 && equality_comparison_p
11619 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11620 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11622 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11623 XEXP (XEXP (op0
, 0), 1));
11624 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11628 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11629 zero and X is a comparison and C1 and C2 describe only bits set
11630 in STORE_FLAG_VALUE, we can compare with X. */
11631 if (const_op
== 0 && equality_comparison_p
11632 && mode_width
<= HOST_BITS_PER_WIDE_INT
11633 && CONST_INT_P (XEXP (op0
, 1))
11634 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11635 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11636 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11637 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11639 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11640 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11641 if ((~STORE_FLAG_VALUE
& mask
) == 0
11642 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11643 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11644 && COMPARISON_P (tem
))))
11646 op0
= XEXP (XEXP (op0
, 0), 0);
11651 /* If we are doing an equality comparison of an AND of a bit equal
11652 to the sign bit, replace this with a LT or GE comparison of
11653 the underlying value. */
11654 if (equality_comparison_p
11656 && CONST_INT_P (XEXP (op0
, 1))
11657 && mode_width
<= HOST_BITS_PER_WIDE_INT
11658 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11659 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11661 op0
= XEXP (op0
, 0);
11662 code
= (code
== EQ
? GE
: LT
);
11666 /* If this AND operation is really a ZERO_EXTEND from a narrower
11667 mode, the constant fits within that mode, and this is either an
11668 equality or unsigned comparison, try to do this comparison in
11673 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11674 -> (ne:DI (reg:SI 4) (const_int 0))
11676 unless TRULY_NOOP_TRUNCATION allows it or the register is
11677 known to hold a value of the required mode the
11678 transformation is invalid. */
11679 if ((equality_comparison_p
|| unsigned_comparison_p
)
11680 && CONST_INT_P (XEXP (op0
, 1))
11681 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11682 & GET_MODE_MASK (mode
))
11684 && const_op
>> i
== 0
11685 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11686 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11687 || (REG_P (XEXP (op0
, 0))
11688 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11690 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11694 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11695 fits in both M1 and M2 and the SUBREG is either paradoxical
11696 or represents the low part, permute the SUBREG and the AND
11698 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11700 unsigned HOST_WIDE_INT c1
;
11701 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11702 /* Require an integral mode, to avoid creating something like
11704 if (SCALAR_INT_MODE_P (tmode
)
11705 /* It is unsafe to commute the AND into the SUBREG if the
11706 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11707 not defined. As originally written the upper bits
11708 have a defined value due to the AND operation.
11709 However, if we commute the AND inside the SUBREG then
11710 they no longer have defined values and the meaning of
11711 the code has been changed. */
11713 #ifdef WORD_REGISTER_OPERATIONS
11714 || (mode_width
> GET_MODE_PRECISION (tmode
)
11715 && mode_width
<= BITS_PER_WORD
)
11717 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11718 && subreg_lowpart_p (XEXP (op0
, 0))))
11719 && CONST_INT_P (XEXP (op0
, 1))
11720 && mode_width
<= HOST_BITS_PER_WIDE_INT
11721 && HWI_COMPUTABLE_MODE_P (tmode
)
11722 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11723 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11725 && c1
!= GET_MODE_MASK (tmode
))
11727 op0
= simplify_gen_binary (AND
, tmode
,
11728 SUBREG_REG (XEXP (op0
, 0)),
11729 gen_int_mode (c1
, tmode
));
11730 op0
= gen_lowpart (mode
, op0
);
11735 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11736 if (const_op
== 0 && equality_comparison_p
11737 && XEXP (op0
, 1) == const1_rtx
11738 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11740 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11741 XEXP (XEXP (op0
, 0), 0), 1);
11742 code
= (code
== NE
? EQ
: NE
);
11746 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11747 (eq (and (lshiftrt X) 1) 0).
11748 Also handle the case where (not X) is expressed using xor. */
11749 if (const_op
== 0 && equality_comparison_p
11750 && XEXP (op0
, 1) == const1_rtx
11751 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11753 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11754 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11756 if (GET_CODE (shift_op
) == NOT
11757 || (GET_CODE (shift_op
) == XOR
11758 && CONST_INT_P (XEXP (shift_op
, 1))
11759 && CONST_INT_P (shift_count
)
11760 && HWI_COMPUTABLE_MODE_P (mode
)
11761 && (UINTVAL (XEXP (shift_op
, 1))
11762 == (unsigned HOST_WIDE_INT
) 1
11763 << INTVAL (shift_count
))))
11766 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11767 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11768 code
= (code
== NE
? EQ
: NE
);
11775 /* If we have (compare (ashift FOO N) (const_int C)) and
11776 the high order N bits of FOO (N+1 if an inequality comparison)
11777 are known to be zero, we can do this by comparing FOO with C
11778 shifted right N bits so long as the low-order N bits of C are
11780 if (CONST_INT_P (XEXP (op0
, 1))
11781 && INTVAL (XEXP (op0
, 1)) >= 0
11782 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11783 < HOST_BITS_PER_WIDE_INT
)
11784 && (((unsigned HOST_WIDE_INT
) const_op
11785 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11787 && mode_width
<= HOST_BITS_PER_WIDE_INT
11788 && (nonzero_bits (XEXP (op0
, 0), mode
)
11789 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11790 + ! equality_comparison_p
))) == 0)
11792 /* We must perform a logical shift, not an arithmetic one,
11793 as we want the top N bits of C to be zero. */
11794 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11796 temp
>>= INTVAL (XEXP (op0
, 1));
11797 op1
= gen_int_mode (temp
, mode
);
11798 op0
= XEXP (op0
, 0);
11802 /* If we are doing a sign bit comparison, it means we are testing
11803 a particular bit. Convert it to the appropriate AND. */
11804 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11805 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11807 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11808 ((unsigned HOST_WIDE_INT
) 1
11810 - INTVAL (XEXP (op0
, 1)))));
11811 code
= (code
== LT
? NE
: EQ
);
11815 /* If this an equality comparison with zero and we are shifting
11816 the low bit to the sign bit, we can convert this to an AND of the
11818 if (const_op
== 0 && equality_comparison_p
11819 && CONST_INT_P (XEXP (op0
, 1))
11820 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11822 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11828 /* If this is an equality comparison with zero, we can do this
11829 as a logical shift, which might be much simpler. */
11830 if (equality_comparison_p
&& const_op
== 0
11831 && CONST_INT_P (XEXP (op0
, 1)))
11833 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11835 INTVAL (XEXP (op0
, 1)));
11839 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11840 do the comparison in a narrower mode. */
11841 if (! unsigned_comparison_p
11842 && CONST_INT_P (XEXP (op0
, 1))
11843 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11844 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11845 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11846 MODE_INT
, 1)) != BLKmode
11847 && (((unsigned HOST_WIDE_INT
) const_op
11848 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11849 <= GET_MODE_MASK (tmode
)))
11851 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11855 /* Likewise if OP0 is a PLUS of a sign extension with a
11856 constant, which is usually represented with the PLUS
11857 between the shifts. */
11858 if (! unsigned_comparison_p
11859 && CONST_INT_P (XEXP (op0
, 1))
11860 && GET_CODE (XEXP (op0
, 0)) == PLUS
11861 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11862 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11863 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11864 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11865 MODE_INT
, 1)) != BLKmode
11866 && (((unsigned HOST_WIDE_INT
) const_op
11867 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11868 <= GET_MODE_MASK (tmode
)))
11870 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11871 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11872 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11873 add_const
, XEXP (op0
, 1));
11875 op0
= simplify_gen_binary (PLUS
, tmode
,
11876 gen_lowpart (tmode
, inner
),
11881 /* ... fall through ... */
11883 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11884 the low order N bits of FOO are known to be zero, we can do this
11885 by comparing FOO with C shifted left N bits so long as no
11886 overflow occurs. Even if the low order N bits of FOO aren't known
11887 to be zero, if the comparison is >= or < we can use the same
11888 optimization and for > or <= by setting all the low
11889 order N bits in the comparison constant. */
11890 if (CONST_INT_P (XEXP (op0
, 1))
11891 && INTVAL (XEXP (op0
, 1)) > 0
11892 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11893 && mode_width
<= HOST_BITS_PER_WIDE_INT
11894 && (((unsigned HOST_WIDE_INT
) const_op
11895 + (GET_CODE (op0
) != LSHIFTRT
11896 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11899 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11901 unsigned HOST_WIDE_INT low_bits
11902 = (nonzero_bits (XEXP (op0
, 0), mode
)
11903 & (((unsigned HOST_WIDE_INT
) 1
11904 << INTVAL (XEXP (op0
, 1))) - 1));
11905 if (low_bits
== 0 || !equality_comparison_p
)
11907 /* If the shift was logical, then we must make the condition
11909 if (GET_CODE (op0
) == LSHIFTRT
)
11910 code
= unsigned_condition (code
);
11912 const_op
<<= INTVAL (XEXP (op0
, 1));
11914 && (code
== GT
|| code
== GTU
11915 || code
== LE
|| code
== LEU
))
11917 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11918 op1
= GEN_INT (const_op
);
11919 op0
= XEXP (op0
, 0);
11924 /* If we are using this shift to extract just the sign bit, we
11925 can replace this with an LT or GE comparison. */
11927 && (equality_comparison_p
|| sign_bit_comparison_p
)
11928 && CONST_INT_P (XEXP (op0
, 1))
11929 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11931 op0
= XEXP (op0
, 0);
11932 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11944 /* Now make any compound operations involved in this comparison. Then,
11945 check for an outmost SUBREG on OP0 that is not doing anything or is
11946 paradoxical. The latter transformation must only be performed when
11947 it is known that the "extra" bits will be the same in op0 and op1 or
11948 that they don't matter. There are three cases to consider:
11950 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11951 care bits and we can assume they have any convenient value. So
11952 making the transformation is safe.
11954 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11955 In this case the upper bits of op0 are undefined. We should not make
11956 the simplification in that case as we do not know the contents of
11959 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11960 UNKNOWN. In that case we know those bits are zeros or ones. We must
11961 also be sure that they are the same as the upper bits of op1.
11963 We can never remove a SUBREG for a non-equality comparison because
11964 the sign bit is in a different place in the underlying object. */
11966 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11967 op1
= make_compound_operation (op1
, SET
);
11969 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11970 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11971 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11972 && (code
== NE
|| code
== EQ
))
11974 if (paradoxical_subreg_p (op0
))
11976 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11978 if (REG_P (SUBREG_REG (op0
)))
11980 op0
= SUBREG_REG (op0
);
11981 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11984 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11985 <= HOST_BITS_PER_WIDE_INT
)
11986 && (nonzero_bits (SUBREG_REG (op0
),
11987 GET_MODE (SUBREG_REG (op0
)))
11988 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11990 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11992 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11993 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11994 op0
= SUBREG_REG (op0
), op1
= tem
;
11998 /* We now do the opposite procedure: Some machines don't have compare
11999 insns in all modes. If OP0's mode is an integer mode smaller than a
12000 word and we can't do a compare in that mode, see if there is a larger
12001 mode for which we can do the compare. There are a number of cases in
12002 which we can use the wider mode. */
12004 mode
= GET_MODE (op0
);
12005 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12006 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12007 && ! have_insn_for (COMPARE
, mode
))
12008 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12009 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12010 tmode
= GET_MODE_WIDER_MODE (tmode
))
12011 if (have_insn_for (COMPARE
, tmode
))
12015 /* If this is a test for negative, we can make an explicit
12016 test of the sign bit. Test this first so we can use
12017 a paradoxical subreg to extend OP0. */
12019 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12020 && HWI_COMPUTABLE_MODE_P (mode
))
12022 unsigned HOST_WIDE_INT sign
12023 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12024 op0
= simplify_gen_binary (AND
, tmode
,
12025 gen_lowpart (tmode
, op0
),
12026 gen_int_mode (sign
, tmode
));
12027 code
= (code
== LT
) ? NE
: EQ
;
12031 /* If the only nonzero bits in OP0 and OP1 are those in the
12032 narrower mode and this is an equality or unsigned comparison,
12033 we can use the wider mode. Similarly for sign-extended
12034 values, in which case it is true for all comparisons. */
12035 zero_extended
= ((code
== EQ
|| code
== NE
12036 || code
== GEU
|| code
== GTU
12037 || code
== LEU
|| code
== LTU
)
12038 && (nonzero_bits (op0
, tmode
)
12039 & ~GET_MODE_MASK (mode
)) == 0
12040 && ((CONST_INT_P (op1
)
12041 || (nonzero_bits (op1
, tmode
)
12042 & ~GET_MODE_MASK (mode
)) == 0)));
12045 || ((num_sign_bit_copies (op0
, tmode
)
12046 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12047 - GET_MODE_PRECISION (mode
)))
12048 && (num_sign_bit_copies (op1
, tmode
)
12049 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12050 - GET_MODE_PRECISION (mode
)))))
12052 /* If OP0 is an AND and we don't have an AND in MODE either,
12053 make a new AND in the proper mode. */
12054 if (GET_CODE (op0
) == AND
12055 && !have_insn_for (AND
, mode
))
12056 op0
= simplify_gen_binary (AND
, tmode
,
12057 gen_lowpart (tmode
,
12059 gen_lowpart (tmode
,
12065 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12066 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12070 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12071 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12078 /* We may have changed the comparison operands. Re-canonicalize. */
12079 if (swap_commutative_operands_p (op0
, op1
))
12081 tem
= op0
, op0
= op1
, op1
= tem
;
12082 code
= swap_condition (code
);
12085 /* If this machine only supports a subset of valid comparisons, see if we
12086 can convert an unsupported one into a supported one. */
12087 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12095 /* Utility function for record_value_for_reg. Count number of
12100 enum rtx_code code
= GET_CODE (x
);
12104 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12105 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12107 rtx x0
= XEXP (x
, 0);
12108 rtx x1
= XEXP (x
, 1);
12111 return 1 + 2 * count_rtxs (x0
);
12113 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12114 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12115 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12116 return 2 + 2 * count_rtxs (x0
)
12117 + count_rtxs (x
== XEXP (x1
, 0)
12118 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12120 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12121 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12122 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12123 return 2 + 2 * count_rtxs (x1
)
12124 + count_rtxs (x
== XEXP (x0
, 0)
12125 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12128 fmt
= GET_RTX_FORMAT (code
);
12129 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12131 ret
+= count_rtxs (XEXP (x
, i
));
12132 else if (fmt
[i
] == 'E')
12133 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12134 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12139 /* Utility function for following routine. Called when X is part of a value
12140 being stored into last_set_value. Sets last_set_table_tick
12141 for each register mentioned. Similar to mention_regs in cse.c */
12144 update_table_tick (rtx x
)
12146 enum rtx_code code
= GET_CODE (x
);
12147 const char *fmt
= GET_RTX_FORMAT (code
);
12152 unsigned int regno
= REGNO (x
);
12153 unsigned int endregno
= END_REGNO (x
);
12156 for (r
= regno
; r
< endregno
; r
++)
12158 reg_stat_type
*rsp
= ®_stat
[r
];
12159 rsp
->last_set_table_tick
= label_tick
;
12165 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12168 /* Check for identical subexpressions. If x contains
12169 identical subexpression we only have to traverse one of
12171 if (i
== 0 && ARITHMETIC_P (x
))
12173 /* Note that at this point x1 has already been
12175 rtx x0
= XEXP (x
, 0);
12176 rtx x1
= XEXP (x
, 1);
12178 /* If x0 and x1 are identical then there is no need to
12183 /* If x0 is identical to a subexpression of x1 then while
12184 processing x1, x0 has already been processed. Thus we
12185 are done with x. */
12186 if (ARITHMETIC_P (x1
)
12187 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12190 /* If x1 is identical to a subexpression of x0 then we
12191 still have to process the rest of x0. */
12192 if (ARITHMETIC_P (x0
)
12193 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12195 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12200 update_table_tick (XEXP (x
, i
));
12202 else if (fmt
[i
] == 'E')
12203 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12204 update_table_tick (XVECEXP (x
, i
, j
));
12207 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12208 are saying that the register is clobbered and we no longer know its
12209 value. If INSN is zero, don't update reg_stat[].last_set; this is
12210 only permitted with VALUE also zero and is used to invalidate the
12214 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12216 unsigned int regno
= REGNO (reg
);
12217 unsigned int endregno
= END_REGNO (reg
);
12219 reg_stat_type
*rsp
;
12221 /* If VALUE contains REG and we have a previous value for REG, substitute
12222 the previous value. */
12223 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12227 /* Set things up so get_last_value is allowed to see anything set up to
12229 subst_low_luid
= DF_INSN_LUID (insn
);
12230 tem
= get_last_value (reg
);
12232 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12233 it isn't going to be useful and will take a lot of time to process,
12234 so just use the CLOBBER. */
12238 if (ARITHMETIC_P (tem
)
12239 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12240 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12241 tem
= XEXP (tem
, 0);
12242 else if (count_occurrences (value
, reg
, 1) >= 2)
12244 /* If there are two or more occurrences of REG in VALUE,
12245 prevent the value from growing too much. */
12246 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12247 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12250 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12254 /* For each register modified, show we don't know its value, that
12255 we don't know about its bitwise content, that its value has been
12256 updated, and that we don't know the location of the death of the
12258 for (i
= regno
; i
< endregno
; i
++)
12260 rsp
= ®_stat
[i
];
12263 rsp
->last_set
= insn
;
12265 rsp
->last_set_value
= 0;
12266 rsp
->last_set_mode
= VOIDmode
;
12267 rsp
->last_set_nonzero_bits
= 0;
12268 rsp
->last_set_sign_bit_copies
= 0;
12269 rsp
->last_death
= 0;
12270 rsp
->truncated_to_mode
= VOIDmode
;
12273 /* Mark registers that are being referenced in this value. */
12275 update_table_tick (value
);
12277 /* Now update the status of each register being set.
12278 If someone is using this register in this block, set this register
12279 to invalid since we will get confused between the two lives in this
12280 basic block. This makes using this register always invalid. In cse, we
12281 scan the table to invalidate all entries using this register, but this
12282 is too much work for us. */
12284 for (i
= regno
; i
< endregno
; i
++)
12286 rsp
= ®_stat
[i
];
12287 rsp
->last_set_label
= label_tick
;
12289 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12290 rsp
->last_set_invalid
= 1;
12292 rsp
->last_set_invalid
= 0;
12295 /* The value being assigned might refer to X (like in "x++;"). In that
12296 case, we must replace it with (clobber (const_int 0)) to prevent
12298 rsp
= ®_stat
[regno
];
12299 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12301 value
= copy_rtx (value
);
12302 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12306 /* For the main register being modified, update the value, the mode, the
12307 nonzero bits, and the number of sign bit copies. */
12309 rsp
->last_set_value
= value
;
12313 enum machine_mode mode
= GET_MODE (reg
);
12314 subst_low_luid
= DF_INSN_LUID (insn
);
12315 rsp
->last_set_mode
= mode
;
12316 if (GET_MODE_CLASS (mode
) == MODE_INT
12317 && HWI_COMPUTABLE_MODE_P (mode
))
12318 mode
= nonzero_bits_mode
;
12319 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12320 rsp
->last_set_sign_bit_copies
12321 = num_sign_bit_copies (value
, GET_MODE (reg
));
12325 /* Called via note_stores from record_dead_and_set_regs to handle one
12326 SET or CLOBBER in an insn. DATA is the instruction in which the
12327 set is occurring. */
12330 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12332 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12334 if (GET_CODE (dest
) == SUBREG
)
12335 dest
= SUBREG_REG (dest
);
12337 if (!record_dead_insn
)
12340 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12346 /* If we are setting the whole register, we know its value. Otherwise
12347 show that we don't know the value. We can handle SUBREG in
12349 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12350 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12351 else if (GET_CODE (setter
) == SET
12352 && GET_CODE (SET_DEST (setter
)) == SUBREG
12353 && SUBREG_REG (SET_DEST (setter
)) == dest
12354 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12355 && subreg_lowpart_p (SET_DEST (setter
)))
12356 record_value_for_reg (dest
, record_dead_insn
,
12357 gen_lowpart (GET_MODE (dest
),
12358 SET_SRC (setter
)));
12360 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12362 else if (MEM_P (dest
)
12363 /* Ignore pushes, they clobber nothing. */
12364 && ! push_operand (dest
, GET_MODE (dest
)))
12365 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12368 /* Update the records of when each REG was most recently set or killed
12369 for the things done by INSN. This is the last thing done in processing
12370 INSN in the combiner loop.
12372 We update reg_stat[], in particular fields last_set, last_set_value,
12373 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12374 last_death, and also the similar information mem_last_set (which insn
12375 most recently modified memory) and last_call_luid (which insn was the
12376 most recent subroutine call). */
12379 record_dead_and_set_regs (rtx_insn
*insn
)
12384 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12386 if (REG_NOTE_KIND (link
) == REG_DEAD
12387 && REG_P (XEXP (link
, 0)))
12389 unsigned int regno
= REGNO (XEXP (link
, 0));
12390 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12392 for (i
= regno
; i
< endregno
; i
++)
12394 reg_stat_type
*rsp
;
12396 rsp
= ®_stat
[i
];
12397 rsp
->last_death
= insn
;
12400 else if (REG_NOTE_KIND (link
) == REG_INC
)
12401 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12406 hard_reg_set_iterator hrsi
;
12407 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12409 reg_stat_type
*rsp
;
12411 rsp
= ®_stat
[i
];
12412 rsp
->last_set_invalid
= 1;
12413 rsp
->last_set
= insn
;
12414 rsp
->last_set_value
= 0;
12415 rsp
->last_set_mode
= VOIDmode
;
12416 rsp
->last_set_nonzero_bits
= 0;
12417 rsp
->last_set_sign_bit_copies
= 0;
12418 rsp
->last_death
= 0;
12419 rsp
->truncated_to_mode
= VOIDmode
;
12422 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12424 /* We can't combine into a call pattern. Remember, though, that
12425 the return value register is set at this LUID. We could
12426 still replace a register with the return value from the
12427 wrong subroutine call! */
12428 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12431 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12434 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12435 register present in the SUBREG, so for each such SUBREG go back and
12436 adjust nonzero and sign bit information of the registers that are
12437 known to have some zero/sign bits set.
12439 This is needed because when combine blows the SUBREGs away, the
12440 information on zero/sign bits is lost and further combines can be
12441 missed because of that. */
12444 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12446 struct insn_link
*links
;
12448 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12449 enum machine_mode mode
= GET_MODE (subreg
);
12451 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12454 for (links
= LOG_LINKS (insn
); links
;)
12456 reg_stat_type
*rsp
;
12458 insn
= links
->insn
;
12459 set
= single_set (insn
);
12461 if (! set
|| !REG_P (SET_DEST (set
))
12462 || REGNO (SET_DEST (set
)) != regno
12463 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12465 links
= links
->next
;
12469 rsp
= ®_stat
[regno
];
12470 if (rsp
->last_set
== insn
)
12472 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12473 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12476 if (REG_P (SET_SRC (set
)))
12478 regno
= REGNO (SET_SRC (set
));
12479 links
= LOG_LINKS (insn
);
12486 /* Check if X, a register, is known to contain a value already
12487 truncated to MODE. In this case we can use a subreg to refer to
12488 the truncated value even though in the generic case we would need
12489 an explicit truncation. */
12492 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12494 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12495 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12498 || rsp
->truncation_label
< label_tick_ebb_start
)
12500 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12502 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12507 /* If X is a hard reg or a subreg record the mode that the register is
12508 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12509 to turn a truncate into a subreg using this information. Return true
12510 if traversing X is complete. */
12513 record_truncated_value (rtx x
)
12515 enum machine_mode truncated_mode
;
12516 reg_stat_type
*rsp
;
12518 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12520 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12521 truncated_mode
= GET_MODE (x
);
12523 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12526 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12529 x
= SUBREG_REG (x
);
12531 /* ??? For hard-regs we now record everything. We might be able to
12532 optimize this using last_set_mode. */
12533 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12534 truncated_mode
= GET_MODE (x
);
12538 rsp
= ®_stat
[REGNO (x
)];
12539 if (rsp
->truncated_to_mode
== 0
12540 || rsp
->truncation_label
< label_tick_ebb_start
12541 || (GET_MODE_SIZE (truncated_mode
)
12542 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12544 rsp
->truncated_to_mode
= truncated_mode
;
12545 rsp
->truncation_label
= label_tick
;
12551 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12552 the modes they are used in. This can help truning TRUNCATEs into
12556 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12558 subrtx_var_iterator::array_type array
;
12559 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12560 if (record_truncated_value (*iter
))
12561 iter
.skip_subrtxes ();
12564 /* Scan X for promoted SUBREGs. For each one found,
12565 note what it implies to the registers used in it. */
12568 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12570 if (GET_CODE (x
) == SUBREG
12571 && SUBREG_PROMOTED_VAR_P (x
)
12572 && REG_P (SUBREG_REG (x
)))
12573 record_promoted_value (insn
, x
);
12576 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12579 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12583 check_promoted_subreg (insn
, XEXP (x
, i
));
12587 if (XVEC (x
, i
) != 0)
12588 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12589 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12595 /* Verify that all the registers and memory references mentioned in *LOC are
12596 still valid. *LOC was part of a value set in INSN when label_tick was
12597 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12598 the invalid references with (clobber (const_int 0)) and return 1. This
12599 replacement is useful because we often can get useful information about
12600 the form of a value (e.g., if it was produced by a shift that always
12601 produces -1 or 0) even though we don't know exactly what registers it
12602 was produced from. */
12605 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12608 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12609 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12614 unsigned int regno
= REGNO (x
);
12615 unsigned int endregno
= END_REGNO (x
);
12618 for (j
= regno
; j
< endregno
; j
++)
12620 reg_stat_type
*rsp
= ®_stat
[j
];
12621 if (rsp
->last_set_invalid
12622 /* If this is a pseudo-register that was only set once and not
12623 live at the beginning of the function, it is always valid. */
12624 || (! (regno
>= FIRST_PSEUDO_REGISTER
12625 && REG_N_SETS (regno
) == 1
12626 && (!REGNO_REG_SET_P
12627 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12629 && rsp
->last_set_label
> tick
))
12632 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12639 /* If this is a memory reference, make sure that there were no stores after
12640 it that might have clobbered the value. We don't have alias info, so we
12641 assume any store invalidates it. Moreover, we only have local UIDs, so
12642 we also assume that there were stores in the intervening basic blocks. */
12643 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12644 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12647 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12651 for (i
= 0; i
< len
; i
++)
12655 /* Check for identical subexpressions. If x contains
12656 identical subexpression we only have to traverse one of
12658 if (i
== 1 && ARITHMETIC_P (x
))
12660 /* Note that at this point x0 has already been checked
12661 and found valid. */
12662 rtx x0
= XEXP (x
, 0);
12663 rtx x1
= XEXP (x
, 1);
12665 /* If x0 and x1 are identical then x is also valid. */
12669 /* If x1 is identical to a subexpression of x0 then
12670 while checking x0, x1 has already been checked. Thus
12671 it is valid and so as x. */
12672 if (ARITHMETIC_P (x0
)
12673 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12676 /* If x0 is identical to a subexpression of x1 then x is
12677 valid iff the rest of x1 is valid. */
12678 if (ARITHMETIC_P (x1
)
12679 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12681 get_last_value_validate (&XEXP (x1
,
12682 x0
== XEXP (x1
, 0) ? 1 : 0),
12683 insn
, tick
, replace
);
12686 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12690 else if (fmt
[i
] == 'E')
12691 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12692 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12693 insn
, tick
, replace
) == 0)
12697 /* If we haven't found a reason for it to be invalid, it is valid. */
12701 /* Get the last value assigned to X, if known. Some registers
12702 in the value may be replaced with (clobber (const_int 0)) if their value
12703 is known longer known reliably. */
12706 get_last_value (const_rtx x
)
12708 unsigned int regno
;
12710 reg_stat_type
*rsp
;
12712 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12713 then convert it to the desired mode. If this is a paradoxical SUBREG,
12714 we cannot predict what values the "extra" bits might have. */
12715 if (GET_CODE (x
) == SUBREG
12716 && subreg_lowpart_p (x
)
12717 && !paradoxical_subreg_p (x
)
12718 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12719 return gen_lowpart (GET_MODE (x
), value
);
12725 rsp
= ®_stat
[regno
];
12726 value
= rsp
->last_set_value
;
12728 /* If we don't have a value, or if it isn't for this basic block and
12729 it's either a hard register, set more than once, or it's a live
12730 at the beginning of the function, return 0.
12732 Because if it's not live at the beginning of the function then the reg
12733 is always set before being used (is never used without being set).
12734 And, if it's set only once, and it's always set before use, then all
12735 uses must have the same last value, even if it's not from this basic
12739 || (rsp
->last_set_label
< label_tick_ebb_start
12740 && (regno
< FIRST_PSEUDO_REGISTER
12741 || REG_N_SETS (regno
) != 1
12743 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12746 /* If the value was set in a later insn than the ones we are processing,
12747 we can't use it even if the register was only set once. */
12748 if (rsp
->last_set_label
== label_tick
12749 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12752 /* If the value has all its registers valid, return it. */
12753 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12756 /* Otherwise, make a copy and replace any invalid register with
12757 (clobber (const_int 0)). If that fails for some reason, return 0. */
12759 value
= copy_rtx (value
);
12760 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12766 /* Return nonzero if expression X refers to a REG or to memory
12767 that is set in an instruction more recent than FROM_LUID. */
12770 use_crosses_set_p (const_rtx x
, int from_luid
)
12774 enum rtx_code code
= GET_CODE (x
);
12778 unsigned int regno
= REGNO (x
);
12779 unsigned endreg
= END_REGNO (x
);
12781 #ifdef PUSH_ROUNDING
12782 /* Don't allow uses of the stack pointer to be moved,
12783 because we don't know whether the move crosses a push insn. */
12784 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12787 for (; regno
< endreg
; regno
++)
12789 reg_stat_type
*rsp
= ®_stat
[regno
];
12791 && rsp
->last_set_label
== label_tick
12792 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12798 if (code
== MEM
&& mem_last_set
> from_luid
)
12801 fmt
= GET_RTX_FORMAT (code
);
12803 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12808 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12809 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12812 else if (fmt
[i
] == 'e'
12813 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12819 /* Define three variables used for communication between the following
12822 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12823 static int reg_dead_flag
;
12825 /* Function called via note_stores from reg_dead_at_p.
12827 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12828 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12831 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12833 unsigned int regno
, endregno
;
12838 regno
= REGNO (dest
);
12839 endregno
= END_REGNO (dest
);
12840 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12841 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12844 /* Return nonzero if REG is known to be dead at INSN.
12846 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12847 referencing REG, it is dead. If we hit a SET referencing REG, it is
12848 live. Otherwise, see if it is live or dead at the start of the basic
12849 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12850 must be assumed to be always live. */
12853 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
12858 /* Set variables for reg_dead_at_p_1. */
12859 reg_dead_regno
= REGNO (reg
);
12860 reg_dead_endregno
= END_REGNO (reg
);
12864 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12865 we allow the machine description to decide whether use-and-clobber
12866 patterns are OK. */
12867 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12869 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12870 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12874 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12875 beginning of basic block. */
12876 block
= BLOCK_FOR_INSN (insn
);
12881 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12883 return reg_dead_flag
== 1 ? 1 : 0;
12885 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12889 if (insn
== BB_HEAD (block
))
12892 insn
= PREV_INSN (insn
);
12895 /* Look at live-in sets for the basic block that we were in. */
12896 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12897 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12903 /* Note hard registers in X that are used. */
12906 mark_used_regs_combine (rtx x
)
12908 RTX_CODE code
= GET_CODE (x
);
12909 unsigned int regno
;
12920 case ADDR_DIFF_VEC
:
12923 /* CC0 must die in the insn after it is set, so we don't need to take
12924 special note of it here. */
12930 /* If we are clobbering a MEM, mark any hard registers inside the
12931 address as used. */
12932 if (MEM_P (XEXP (x
, 0)))
12933 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12938 /* A hard reg in a wide mode may really be multiple registers.
12939 If so, mark all of them just like the first. */
12940 if (regno
< FIRST_PSEUDO_REGISTER
)
12942 /* None of this applies to the stack, frame or arg pointers. */
12943 if (regno
== STACK_POINTER_REGNUM
12944 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12945 || regno
== HARD_FRAME_POINTER_REGNUM
12947 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12948 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12950 || regno
== FRAME_POINTER_REGNUM
)
12953 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12959 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12961 rtx testreg
= SET_DEST (x
);
12963 while (GET_CODE (testreg
) == SUBREG
12964 || GET_CODE (testreg
) == ZERO_EXTRACT
12965 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12966 testreg
= XEXP (testreg
, 0);
12968 if (MEM_P (testreg
))
12969 mark_used_regs_combine (XEXP (testreg
, 0));
12971 mark_used_regs_combine (SET_SRC (x
));
12979 /* Recursively scan the operands of this expression. */
12982 const char *fmt
= GET_RTX_FORMAT (code
);
12984 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12987 mark_used_regs_combine (XEXP (x
, i
));
12988 else if (fmt
[i
] == 'E')
12992 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12993 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12999 /* Remove register number REGNO from the dead registers list of INSN.
13001 Return the note used to record the death, if there was one. */
13004 remove_death (unsigned int regno
, rtx_insn
*insn
)
13006 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13009 remove_note (insn
, note
);
13014 /* For each register (hardware or pseudo) used within expression X, if its
13015 death is in an instruction with luid between FROM_LUID (inclusive) and
13016 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13017 list headed by PNOTES.
13019 That said, don't move registers killed by maybe_kill_insn.
13021 This is done when X is being merged by combination into TO_INSN. These
13022 notes will then be distributed as needed. */
13025 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13030 enum rtx_code code
= GET_CODE (x
);
13034 unsigned int regno
= REGNO (x
);
13035 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13037 /* Don't move the register if it gets killed in between from and to. */
13038 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13039 && ! reg_referenced_p (x
, maybe_kill_insn
))
13043 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13044 && DF_INSN_LUID (where_dead
) >= from_luid
13045 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13047 rtx note
= remove_death (regno
, where_dead
);
13049 /* It is possible for the call above to return 0. This can occur
13050 when last_death points to I2 or I1 that we combined with.
13051 In that case make a new note.
13053 We must also check for the case where X is a hard register
13054 and NOTE is a death note for a range of hard registers
13055 including X. In that case, we must put REG_DEAD notes for
13056 the remaining registers in place of NOTE. */
13058 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13059 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13060 > GET_MODE_SIZE (GET_MODE (x
))))
13062 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13063 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13064 unsigned int ourend
= END_HARD_REGNO (x
);
13067 for (i
= deadregno
; i
< deadend
; i
++)
13068 if (i
< regno
|| i
>= ourend
)
13069 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13072 /* If we didn't find any note, or if we found a REG_DEAD note that
13073 covers only part of the given reg, and we have a multi-reg hard
13074 register, then to be safe we must check for REG_DEAD notes
13075 for each register other than the first. They could have
13076 their own REG_DEAD notes lying around. */
13077 else if ((note
== 0
13079 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13080 < GET_MODE_SIZE (GET_MODE (x
)))))
13081 && regno
< FIRST_PSEUDO_REGISTER
13082 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13084 unsigned int ourend
= END_HARD_REGNO (x
);
13085 unsigned int i
, offset
;
13089 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13093 for (i
= regno
+ offset
; i
< ourend
; i
++)
13094 move_deaths (regno_reg_rtx
[i
],
13095 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13098 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13100 XEXP (note
, 1) = *pnotes
;
13104 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13110 else if (GET_CODE (x
) == SET
)
13112 rtx dest
= SET_DEST (x
);
13114 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13116 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13117 that accesses one word of a multi-word item, some
13118 piece of everything register in the expression is used by
13119 this insn, so remove any old death. */
13120 /* ??? So why do we test for equality of the sizes? */
13122 if (GET_CODE (dest
) == ZERO_EXTRACT
13123 || GET_CODE (dest
) == STRICT_LOW_PART
13124 || (GET_CODE (dest
) == SUBREG
13125 && (((GET_MODE_SIZE (GET_MODE (dest
))
13126 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13127 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13128 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13130 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13134 /* If this is some other SUBREG, we know it replaces the entire
13135 value, so use that as the destination. */
13136 if (GET_CODE (dest
) == SUBREG
)
13137 dest
= SUBREG_REG (dest
);
13139 /* If this is a MEM, adjust deaths of anything used in the address.
13140 For a REG (the only other possibility), the entire value is
13141 being replaced so the old value is not used in this insn. */
13144 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13149 else if (GET_CODE (x
) == CLOBBER
)
13152 len
= GET_RTX_LENGTH (code
);
13153 fmt
= GET_RTX_FORMAT (code
);
13155 for (i
= 0; i
< len
; i
++)
13160 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13161 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13164 else if (fmt
[i
] == 'e')
13165 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13169 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13170 pattern of an insn. X must be a REG. */
13173 reg_bitfield_target_p (rtx x
, rtx body
)
13177 if (GET_CODE (body
) == SET
)
13179 rtx dest
= SET_DEST (body
);
13181 unsigned int regno
, tregno
, endregno
, endtregno
;
13183 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13184 target
= XEXP (dest
, 0);
13185 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13186 target
= SUBREG_REG (XEXP (dest
, 0));
13190 if (GET_CODE (target
) == SUBREG
)
13191 target
= SUBREG_REG (target
);
13193 if (!REG_P (target
))
13196 tregno
= REGNO (target
), regno
= REGNO (x
);
13197 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13198 return target
== x
;
13200 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13201 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13203 return endregno
> tregno
&& regno
< endtregno
;
13206 else if (GET_CODE (body
) == PARALLEL
)
13207 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13208 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13214 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13215 as appropriate. I3 and I2 are the insns resulting from the combination
13216 insns including FROM (I2 may be zero).
13218 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13219 not need REG_DEAD notes because they are being substituted for. This
13220 saves searching in the most common cases.
13222 Each note in the list is either ignored or placed on some insns, depending
13223 on the type of note. */
13226 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13227 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13229 rtx note
, next_note
;
13231 rtx_insn
*tem_insn
;
13233 for (note
= notes
; note
; note
= next_note
)
13235 rtx_insn
*place
= 0, *place2
= 0;
13237 next_note
= XEXP (note
, 1);
13238 switch (REG_NOTE_KIND (note
))
13242 /* Doesn't matter much where we put this, as long as it's somewhere.
13243 It is preferable to keep these notes on branches, which is most
13244 likely to be i3. */
13248 case REG_NON_LOCAL_GOTO
:
13253 gcc_assert (i2
&& JUMP_P (i2
));
13258 case REG_EH_REGION
:
13259 /* These notes must remain with the call or trapping instruction. */
13262 else if (i2
&& CALL_P (i2
))
13266 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13267 if (may_trap_p (i3
))
13269 else if (i2
&& may_trap_p (i2
))
13271 /* ??? Otherwise assume we've combined things such that we
13272 can now prove that the instructions can't trap. Drop the
13273 note in this case. */
13277 case REG_ARGS_SIZE
:
13278 /* ??? How to distribute between i3-i1. Assume i3 contains the
13279 entire adjustment. Assert i3 contains at least some adjust. */
13280 if (!noop_move_p (i3
))
13282 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13283 /* fixup_args_size_notes looks at REG_NORETURN note,
13284 so ensure the note is placed there first. */
13288 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13289 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13293 XEXP (n
, 1) = REG_NOTES (i3
);
13294 REG_NOTES (i3
) = n
;
13298 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13299 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13300 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13301 gcc_assert (old_size
!= args_size
13303 && !ACCUMULATE_OUTGOING_ARGS
13304 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13311 case REG_CALL_DECL
:
13312 /* These notes must remain with the call. It should not be
13313 possible for both I2 and I3 to be a call. */
13318 gcc_assert (i2
&& CALL_P (i2
));
13324 /* Any clobbers for i3 may still exist, and so we must process
13325 REG_UNUSED notes from that insn.
13327 Any clobbers from i2 or i1 can only exist if they were added by
13328 recog_for_combine. In that case, recog_for_combine created the
13329 necessary REG_UNUSED notes. Trying to keep any original
13330 REG_UNUSED notes from these insns can cause incorrect output
13331 if it is for the same register as the original i3 dest.
13332 In that case, we will notice that the register is set in i3,
13333 and then add a REG_UNUSED note for the destination of i3, which
13334 is wrong. However, it is possible to have REG_UNUSED notes from
13335 i2 or i1 for register which were both used and clobbered, so
13336 we keep notes from i2 or i1 if they will turn into REG_DEAD
13339 /* If this register is set or clobbered in I3, put the note there
13340 unless there is one already. */
13341 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13343 if (from_insn
!= i3
)
13346 if (! (REG_P (XEXP (note
, 0))
13347 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13348 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13351 /* Otherwise, if this register is used by I3, then this register
13352 now dies here, so we must put a REG_DEAD note here unless there
13354 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13355 && ! (REG_P (XEXP (note
, 0))
13356 ? find_regno_note (i3
, REG_DEAD
,
13357 REGNO (XEXP (note
, 0)))
13358 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13360 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13368 /* These notes say something about results of an insn. We can
13369 only support them if they used to be on I3 in which case they
13370 remain on I3. Otherwise they are ignored.
13372 If the note refers to an expression that is not a constant, we
13373 must also ignore the note since we cannot tell whether the
13374 equivalence is still true. It might be possible to do
13375 slightly better than this (we only have a problem if I2DEST
13376 or I1DEST is present in the expression), but it doesn't
13377 seem worth the trouble. */
13379 if (from_insn
== i3
13380 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13385 /* These notes say something about how a register is used. They must
13386 be present on any use of the register in I2 or I3. */
13387 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13390 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13399 case REG_LABEL_TARGET
:
13400 case REG_LABEL_OPERAND
:
13401 /* This can show up in several ways -- either directly in the
13402 pattern, or hidden off in the constant pool with (or without?)
13403 a REG_EQUAL note. */
13404 /* ??? Ignore the without-reg_equal-note problem for now. */
13405 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13406 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13407 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13408 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13412 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13413 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13414 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13415 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13423 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13424 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13426 if (place
&& JUMP_P (place
)
13427 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13428 && (JUMP_LABEL (place
) == NULL
13429 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13431 rtx label
= JUMP_LABEL (place
);
13434 JUMP_LABEL (place
) = XEXP (note
, 0);
13435 else if (LABEL_P (label
))
13436 LABEL_NUSES (label
)--;
13439 if (place2
&& JUMP_P (place2
)
13440 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13441 && (JUMP_LABEL (place2
) == NULL
13442 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13444 rtx label
= JUMP_LABEL (place2
);
13447 JUMP_LABEL (place2
) = XEXP (note
, 0);
13448 else if (LABEL_P (label
))
13449 LABEL_NUSES (label
)--;
13455 /* This note says something about the value of a register prior
13456 to the execution of an insn. It is too much trouble to see
13457 if the note is still correct in all situations. It is better
13458 to simply delete it. */
13462 /* If we replaced the right hand side of FROM_INSN with a
13463 REG_EQUAL note, the original use of the dying register
13464 will not have been combined into I3 and I2. In such cases,
13465 FROM_INSN is guaranteed to be the first of the combined
13466 instructions, so we simply need to search back before
13467 FROM_INSN for the previous use or set of this register,
13468 then alter the notes there appropriately.
13470 If the register is used as an input in I3, it dies there.
13471 Similarly for I2, if it is nonzero and adjacent to I3.
13473 If the register is not used as an input in either I3 or I2
13474 and it is not one of the registers we were supposed to eliminate,
13475 there are two possibilities. We might have a non-adjacent I2
13476 or we might have somehow eliminated an additional register
13477 from a computation. For example, we might have had A & B where
13478 we discover that B will always be zero. In this case we will
13479 eliminate the reference to A.
13481 In both cases, we must search to see if we can find a previous
13482 use of A and put the death note there. */
13485 && from_insn
== i2mod
13486 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13487 tem_insn
= from_insn
;
13491 && CALL_P (from_insn
)
13492 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13494 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13496 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13497 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13499 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13501 && reg_overlap_mentioned_p (XEXP (note
, 0),
13503 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13504 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13511 basic_block bb
= this_basic_block
;
13513 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13515 if (!NONDEBUG_INSN_P (tem_insn
))
13517 if (tem_insn
== BB_HEAD (bb
))
13522 /* If the register is being set at TEM_INSN, see if that is all
13523 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13524 into a REG_UNUSED note instead. Don't delete sets to
13525 global register vars. */
13526 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13527 || !global_regs
[REGNO (XEXP (note
, 0))])
13528 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13530 rtx set
= single_set (tem_insn
);
13531 rtx inner_dest
= 0;
13533 rtx_insn
*cc0_setter
= NULL
;
13537 for (inner_dest
= SET_DEST (set
);
13538 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13539 || GET_CODE (inner_dest
) == SUBREG
13540 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13541 inner_dest
= XEXP (inner_dest
, 0))
13544 /* Verify that it was the set, and not a clobber that
13545 modified the register.
13547 CC0 targets must be careful to maintain setter/user
13548 pairs. If we cannot delete the setter due to side
13549 effects, mark the user with an UNUSED note instead
13552 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13553 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13555 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13556 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13557 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13561 /* Move the notes and links of TEM_INSN elsewhere.
13562 This might delete other dead insns recursively.
13563 First set the pattern to something that won't use
13565 rtx old_notes
= REG_NOTES (tem_insn
);
13567 PATTERN (tem_insn
) = pc_rtx
;
13568 REG_NOTES (tem_insn
) = NULL
;
13570 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13571 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13572 distribute_links (LOG_LINKS (tem_insn
));
13574 SET_INSN_DELETED (tem_insn
);
13575 if (tem_insn
== i2
)
13579 /* Delete the setter too. */
13582 PATTERN (cc0_setter
) = pc_rtx
;
13583 old_notes
= REG_NOTES (cc0_setter
);
13584 REG_NOTES (cc0_setter
) = NULL
;
13586 distribute_notes (old_notes
, cc0_setter
,
13588 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13589 distribute_links (LOG_LINKS (cc0_setter
));
13591 SET_INSN_DELETED (cc0_setter
);
13592 if (cc0_setter
== i2
)
13599 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13601 /* If there isn't already a REG_UNUSED note, put one
13602 here. Do not place a REG_DEAD note, even if
13603 the register is also used here; that would not
13604 match the algorithm used in lifetime analysis
13605 and can cause the consistency check in the
13606 scheduler to fail. */
13607 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13608 REGNO (XEXP (note
, 0))))
13613 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13614 || (CALL_P (tem_insn
)
13615 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
13619 /* If we are doing a 3->2 combination, and we have a
13620 register which formerly died in i3 and was not used
13621 by i2, which now no longer dies in i3 and is used in
13622 i2 but does not die in i2, and place is between i2
13623 and i3, then we may need to move a link from place to
13625 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13627 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13628 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13630 struct insn_link
*links
= LOG_LINKS (place
);
13631 LOG_LINKS (place
) = NULL
;
13632 distribute_links (links
);
13637 if (tem_insn
== BB_HEAD (bb
))
13643 /* If the register is set or already dead at PLACE, we needn't do
13644 anything with this note if it is still a REG_DEAD note.
13645 We check here if it is set at all, not if is it totally replaced,
13646 which is what `dead_or_set_p' checks, so also check for it being
13649 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13651 unsigned int regno
= REGNO (XEXP (note
, 0));
13652 reg_stat_type
*rsp
= ®_stat
[regno
];
13654 if (dead_or_set_p (place
, XEXP (note
, 0))
13655 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13657 /* Unless the register previously died in PLACE, clear
13658 last_death. [I no longer understand why this is
13660 if (rsp
->last_death
!= place
)
13661 rsp
->last_death
= 0;
13665 rsp
->last_death
= place
;
13667 /* If this is a death note for a hard reg that is occupying
13668 multiple registers, ensure that we are still using all
13669 parts of the object. If we find a piece of the object
13670 that is unused, we must arrange for an appropriate REG_DEAD
13671 note to be added for it. However, we can't just emit a USE
13672 and tag the note to it, since the register might actually
13673 be dead; so we recourse, and the recursive call then finds
13674 the previous insn that used this register. */
13676 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13677 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13679 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13680 bool all_used
= true;
13683 for (i
= regno
; i
< endregno
; i
++)
13684 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13685 && ! find_regno_fusage (place
, USE
, i
))
13686 || dead_or_set_regno_p (place
, i
))
13694 /* Put only REG_DEAD notes for pieces that are
13695 not already dead or set. */
13697 for (i
= regno
; i
< endregno
;
13698 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13700 rtx piece
= regno_reg_rtx
[i
];
13701 basic_block bb
= this_basic_block
;
13703 if (! dead_or_set_p (place
, piece
)
13704 && ! reg_bitfield_target_p (piece
,
13707 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13710 distribute_notes (new_note
, place
, place
,
13711 NULL
, NULL_RTX
, NULL_RTX
,
13714 else if (! refers_to_regno_p (i
, i
+ 1,
13715 PATTERN (place
), 0)
13716 && ! find_regno_fusage (place
, USE
, i
))
13717 for (tem_insn
= PREV_INSN (place
); ;
13718 tem_insn
= PREV_INSN (tem_insn
))
13720 if (!NONDEBUG_INSN_P (tem_insn
))
13722 if (tem_insn
== BB_HEAD (bb
))
13726 if (dead_or_set_p (tem_insn
, piece
)
13727 || reg_bitfield_target_p (piece
,
13728 PATTERN (tem_insn
)))
13730 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
13743 /* Any other notes should not be present at this point in the
13745 gcc_unreachable ();
13750 XEXP (note
, 1) = REG_NOTES (place
);
13751 REG_NOTES (place
) = note
;
13755 add_shallow_copy_of_reg_note (place2
, note
);
13759 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13760 I3, I2, and I1 to new locations. This is also called to add a link
13761 pointing at I3 when I3's destination is changed. */
13764 distribute_links (struct insn_link
*links
)
13766 struct insn_link
*link
, *next_link
;
13768 for (link
= links
; link
; link
= next_link
)
13770 rtx_insn
*place
= 0;
13774 next_link
= link
->next
;
13776 /* If the insn that this link points to is a NOTE or isn't a single
13777 set, ignore it. In the latter case, it isn't clear what we
13778 can do other than ignore the link, since we can't tell which
13779 register it was for. Such links wouldn't be used by combine
13782 It is not possible for the destination of the target of the link to
13783 have been changed by combine. The only potential of this is if we
13784 replace I3, I2, and I1 by I3 and I2. But in that case the
13785 destination of I2 also remains unchanged. */
13787 if (NOTE_P (link
->insn
)
13788 || (set
= single_set (link
->insn
)) == 0)
13791 reg
= SET_DEST (set
);
13792 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13793 || GET_CODE (reg
) == STRICT_LOW_PART
)
13794 reg
= XEXP (reg
, 0);
13796 /* A LOG_LINK is defined as being placed on the first insn that uses
13797 a register and points to the insn that sets the register. Start
13798 searching at the next insn after the target of the link and stop
13799 when we reach a set of the register or the end of the basic block.
13801 Note that this correctly handles the link that used to point from
13802 I3 to I2. Also note that not much searching is typically done here
13803 since most links don't point very far away. */
13805 for (insn
= NEXT_INSN (link
->insn
);
13806 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13807 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13808 insn
= NEXT_INSN (insn
))
13809 if (DEBUG_INSN_P (insn
))
13811 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13813 if (reg_referenced_p (reg
, PATTERN (insn
)))
13817 else if (CALL_P (insn
)
13818 && find_reg_fusage (insn
, USE
, reg
))
13823 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13826 /* If we found a place to put the link, place it there unless there
13827 is already a link to the same insn as LINK at that point. */
13831 struct insn_link
*link2
;
13833 FOR_EACH_LOG_LINK (link2
, place
)
13834 if (link2
->insn
== link
->insn
)
13839 link
->next
= LOG_LINKS (place
);
13840 LOG_LINKS (place
) = link
;
13842 /* Set added_links_insn to the earliest insn we added a
13844 if (added_links_insn
== 0
13845 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13846 added_links_insn
= place
;
13852 /* Check for any register or memory mentioned in EQUIV that is not
13853 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13854 of EXPR where some registers may have been replaced by constants. */
13857 unmentioned_reg_p (rtx equiv
, rtx expr
)
13859 subrtx_iterator::array_type array
;
13860 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
13862 const_rtx x
= *iter
;
13863 if ((REG_P (x
) || MEM_P (x
))
13864 && !reg_mentioned_p (x
, expr
))
13870 DEBUG_FUNCTION
void
13871 dump_combine_stats (FILE *file
)
13875 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13876 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13880 dump_combine_total_stats (FILE *file
)
13884 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13885 total_attempts
, total_merges
, total_extras
, total_successes
);
13888 /* Try combining insns through substitution. */
13889 static unsigned int
13890 rest_of_handle_combine (void)
13892 int rebuild_jump_labels_after_combine
;
13894 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13895 df_note_add_problem ();
13898 regstat_init_n_sets_and_refs ();
13900 rebuild_jump_labels_after_combine
13901 = combine_instructions (get_insns (), max_reg_num ());
13903 /* Combining insns may have turned an indirect jump into a
13904 direct jump. Rebuild the JUMP_LABEL fields of jumping
13906 if (rebuild_jump_labels_after_combine
)
13908 timevar_push (TV_JUMP
);
13909 rebuild_jump_labels (get_insns ());
13911 timevar_pop (TV_JUMP
);
13914 regstat_free_n_sets_and_refs ();
13920 const pass_data pass_data_combine
=
13922 RTL_PASS
, /* type */
13923 "combine", /* name */
13924 OPTGROUP_NONE
, /* optinfo_flags */
13925 TV_COMBINE
, /* tv_id */
13926 PROP_cfglayout
, /* properties_required */
13927 0, /* properties_provided */
13928 0, /* properties_destroyed */
13929 0, /* todo_flags_start */
13930 TODO_df_finish
, /* todo_flags_finish */
13933 class pass_combine
: public rtl_opt_pass
13936 pass_combine (gcc::context
*ctxt
)
13937 : rtl_opt_pass (pass_data_combine
, ctxt
)
13940 /* opt_pass methods: */
13941 virtual bool gate (function
*) { return (optimize
> 0); }
13942 virtual unsigned int execute (function
*)
13944 return rest_of_handle_combine ();
13947 }; // class pass_combine
13949 } // anon namespace
13952 make_pass_combine (gcc::context
*ctxt
)
13954 return new pass_combine (ctxt
);