1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "stor-layout.h"
29 #include "stringpool.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
38 #include "insn-attr.h"
48 #include "diagnostic-core.h"
49 #include "dominance.h"
55 #include "cfgcleanup.h"
57 #include "basic-block.h"
61 #include "tm-constrs.h"
65 #include "target-def.h"
67 /* Array of valid operand punctuation characters. */
68 static char m32r_punct_chars
[256];
70 /* Machine-specific symbol_ref flags. */
71 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
72 #define SYMBOL_REF_MODEL(X) \
73 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
75 /* For string literals, etc. */
76 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
78 /* Forward declaration. */
79 static void m32r_option_override (void);
80 static void init_reg_tables (void);
81 static void block_move_call (rtx
, rtx
, rtx
);
82 static int m32r_is_insn (rtx
);
83 static bool m32r_legitimate_address_p (machine_mode
, rtx
, bool);
84 static rtx
m32r_legitimize_address (rtx
, rtx
, machine_mode
);
85 static bool m32r_mode_dependent_address_p (const_rtx
, addr_space_t
);
86 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
87 static void m32r_print_operand (FILE *, rtx
, int);
88 static void m32r_print_operand_address (FILE *, rtx
);
89 static bool m32r_print_operand_punct_valid_p (unsigned char code
);
90 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
91 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
93 static void m32r_file_start (void);
95 static int m32r_adjust_priority (rtx_insn
*, int);
96 static int m32r_issue_rate (void);
98 static void m32r_encode_section_info (tree
, rtx
, int);
99 static bool m32r_in_small_data_p (const_tree
);
100 static bool m32r_return_in_memory (const_tree
, const_tree
);
101 static rtx
m32r_function_value (const_tree
, const_tree
, bool);
102 static rtx
m32r_libcall_value (machine_mode
, const_rtx
);
103 static bool m32r_function_value_regno_p (const unsigned int);
104 static void m32r_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
106 static void init_idents (void);
107 static bool m32r_rtx_costs (rtx
, int, int, int, int *, bool speed
);
108 static int m32r_memory_move_cost (machine_mode
, reg_class_t
, bool);
109 static bool m32r_pass_by_reference (cumulative_args_t
, machine_mode
,
111 static int m32r_arg_partial_bytes (cumulative_args_t
, machine_mode
,
113 static rtx
m32r_function_arg (cumulative_args_t
, machine_mode
,
115 static void m32r_function_arg_advance (cumulative_args_t
, machine_mode
,
117 static bool m32r_can_eliminate (const int, const int);
118 static void m32r_conditional_register_usage (void);
119 static void m32r_trampoline_init (rtx
, tree
, rtx
);
120 static bool m32r_legitimate_constant_p (machine_mode
, rtx
);
122 /* M32R specific attributes. */
124 static const struct attribute_spec m32r_attribute_table
[] =
126 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
127 affects_type_identity } */
128 { "interrupt", 0, 0, true, false, false, NULL
, false },
129 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
,
131 { NULL
, 0, 0, false, false, false, NULL
, false }
134 /* Initialize the GCC target structure. */
135 #undef TARGET_ATTRIBUTE_TABLE
136 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
138 #undef TARGET_LEGITIMATE_ADDRESS_P
139 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
140 #undef TARGET_LEGITIMIZE_ADDRESS
141 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
142 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
143 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
150 #undef TARGET_PRINT_OPERAND
151 #define TARGET_PRINT_OPERAND m32r_print_operand
152 #undef TARGET_PRINT_OPERAND_ADDRESS
153 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
154 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
155 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
157 #undef TARGET_ASM_FUNCTION_PROLOGUE
158 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
159 #undef TARGET_ASM_FUNCTION_EPILOGUE
160 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
162 #undef TARGET_ASM_FILE_START
163 #define TARGET_ASM_FILE_START m32r_file_start
165 #undef TARGET_SCHED_ADJUST_PRIORITY
166 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
167 #undef TARGET_SCHED_ISSUE_RATE
168 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
170 #undef TARGET_OPTION_OVERRIDE
171 #define TARGET_OPTION_OVERRIDE m32r_option_override
173 #undef TARGET_ENCODE_SECTION_INFO
174 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
175 #undef TARGET_IN_SMALL_DATA_P
176 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
179 #undef TARGET_MEMORY_MOVE_COST
180 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
181 #undef TARGET_RTX_COSTS
182 #define TARGET_RTX_COSTS m32r_rtx_costs
183 #undef TARGET_ADDRESS_COST
184 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
186 #undef TARGET_PROMOTE_PROTOTYPES
187 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
188 #undef TARGET_RETURN_IN_MEMORY
189 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
191 #undef TARGET_FUNCTION_VALUE
192 #define TARGET_FUNCTION_VALUE m32r_function_value
193 #undef TARGET_LIBCALL_VALUE
194 #define TARGET_LIBCALL_VALUE m32r_libcall_value
195 #undef TARGET_FUNCTION_VALUE_REGNO_P
196 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
198 #undef TARGET_SETUP_INCOMING_VARARGS
199 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
200 #undef TARGET_MUST_PASS_IN_STACK
201 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
202 #undef TARGET_PASS_BY_REFERENCE
203 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
204 #undef TARGET_ARG_PARTIAL_BYTES
205 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
206 #undef TARGET_FUNCTION_ARG
207 #define TARGET_FUNCTION_ARG m32r_function_arg
208 #undef TARGET_FUNCTION_ARG_ADVANCE
209 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
211 #undef TARGET_CAN_ELIMINATE
212 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
214 #undef TARGET_CONDITIONAL_REGISTER_USAGE
215 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
217 #undef TARGET_TRAMPOLINE_INIT
218 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
220 #undef TARGET_LEGITIMATE_CONSTANT_P
221 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
223 struct gcc_target targetm
= TARGET_INITIALIZER
;
225 /* Called by m32r_option_override to initialize various things. */
232 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
233 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
234 m32r_punct_chars
['#'] = 1;
235 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
237 /* Provide default value if not specified. */
238 if (!global_options_set
.x_g_switch_value
)
239 g_switch_value
= SDATA_DEFAULT_SIZE
;
243 m32r_option_override (void)
245 /* These need to be done at start up.
246 It's convenient to do them here. */
248 SUBTARGET_OVERRIDE_OPTIONS
;
251 /* Vectors to keep interesting information about registers where it can easily
252 be got. We use to use the actual mode value as the bit number, but there
253 is (or may be) more than 32 modes now. Instead we use two tables: one
254 indexed by hard register number, and one indexed by mode. */
256 /* The purpose of m32r_mode_class is to shrink the range of modes so that
257 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
258 mapped into one m32r_mode_class mode. */
263 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
264 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
267 /* Modes for condition codes. */
268 #define C_MODES (1 << (int) C_MODE)
270 /* Modes for single-word and smaller quantities. */
271 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
273 /* Modes for double-word and smaller quantities. */
274 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
276 /* Modes for quad-word and smaller quantities. */
277 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
279 /* Modes for accumulators. */
280 #define A_MODES (1 << (int) A_MODE)
282 /* Value is 1 if register/mode pair is acceptable on arc. */
284 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
286 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
287 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
288 S_MODES
, C_MODES
, A_MODES
, A_MODES
291 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
293 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
296 init_reg_tables (void)
300 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
302 machine_mode m
= (machine_mode
) i
;
304 switch (GET_MODE_CLASS (m
))
307 case MODE_PARTIAL_INT
:
308 case MODE_COMPLEX_INT
:
309 if (GET_MODE_SIZE (m
) <= 4)
310 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
311 else if (GET_MODE_SIZE (m
) == 8)
312 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
313 else if (GET_MODE_SIZE (m
) == 16)
314 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
315 else if (GET_MODE_SIZE (m
) == 32)
316 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
318 m32r_mode_class
[i
] = 0;
321 case MODE_COMPLEX_FLOAT
:
322 if (GET_MODE_SIZE (m
) <= 4)
323 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
324 else if (GET_MODE_SIZE (m
) == 8)
325 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
326 else if (GET_MODE_SIZE (m
) == 16)
327 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
328 else if (GET_MODE_SIZE (m
) == 32)
329 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
331 m32r_mode_class
[i
] = 0;
334 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
337 m32r_mode_class
[i
] = 0;
342 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
345 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
346 else if (i
== ARG_POINTER_REGNUM
)
347 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
349 m32r_regno_reg_class
[i
] = NO_REGS
;
353 /* M32R specific attribute support.
355 interrupt - for interrupt functions
357 model - select code model used to access object
359 small: addresses use 24 bits, use bl to make calls
360 medium: addresses use 32 bits, use bl to make calls
361 large: addresses use 32 bits, use seth/add3/jl to make calls
363 Grep for MODEL in m32r.h for more info. */
365 static tree small_ident1
;
366 static tree small_ident2
;
367 static tree medium_ident1
;
368 static tree medium_ident2
;
369 static tree large_ident1
;
370 static tree large_ident2
;
375 if (small_ident1
== 0)
377 small_ident1
= get_identifier ("small");
378 small_ident2
= get_identifier ("__small__");
379 medium_ident1
= get_identifier ("medium");
380 medium_ident2
= get_identifier ("__medium__");
381 large_ident1
= get_identifier ("large");
382 large_ident2
= get_identifier ("__large__");
386 /* Handle an "model" attribute; arguments as in
387 struct attribute_spec.handler. */
389 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
390 tree args
, int flags ATTRIBUTE_UNUSED
,
396 arg
= TREE_VALUE (args
);
398 if (arg
!= small_ident1
399 && arg
!= small_ident2
400 && arg
!= medium_ident1
401 && arg
!= medium_ident2
402 && arg
!= large_ident1
403 && arg
!= large_ident2
)
405 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
406 IDENTIFIER_POINTER (name
));
407 *no_add_attrs
= true;
413 /* Encode section information of DECL, which is either a VAR_DECL,
414 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
416 For the M32R we want to record:
418 - whether the object lives in .sdata/.sbss.
419 - what code model should be used to access the object
423 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
427 enum m32r_model model
;
429 default_encode_section_info (decl
, rtl
, first
);
434 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
441 id
= TREE_VALUE (TREE_VALUE (model_attr
));
443 if (id
== small_ident1
|| id
== small_ident2
)
444 model
= M32R_MODEL_SMALL
;
445 else if (id
== medium_ident1
|| id
== medium_ident2
)
446 model
= M32R_MODEL_MEDIUM
;
447 else if (id
== large_ident1
|| id
== large_ident2
)
448 model
= M32R_MODEL_LARGE
;
450 gcc_unreachable (); /* shouldn't happen */
454 if (TARGET_MODEL_SMALL
)
455 model
= M32R_MODEL_SMALL
;
456 else if (TARGET_MODEL_MEDIUM
)
457 model
= M32R_MODEL_MEDIUM
;
458 else if (TARGET_MODEL_LARGE
)
459 model
= M32R_MODEL_LARGE
;
461 gcc_unreachable (); /* shouldn't happen */
463 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
466 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
469 /* Only mark the object as being small data area addressable if
470 it hasn't been explicitly marked with a code model.
472 The user can explicitly put an object in the small data area with the
473 section attribute. If the object is in sdata/sbss and marked with a
474 code model do both [put the object in .sdata and mark it as being
475 addressed with a specific code model - don't mark it as being addressed
476 with an SDA reloc though]. This is ok and might be useful at times. If
477 the object doesn't fit the linker will give an error. */
480 m32r_in_small_data_p (const_tree decl
)
484 if (TREE_CODE (decl
) != VAR_DECL
)
487 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
490 section
= DECL_SECTION_NAME (decl
);
493 if (strcmp (section
, ".sdata") == 0 || strcmp (section
, ".sbss") == 0)
498 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
500 int size
= int_size_in_bytes (TREE_TYPE (decl
));
502 if (size
> 0 && size
<= g_switch_value
)
510 /* Do anything needed before RTL is emitted for each function. */
513 m32r_init_expanders (void)
515 /* ??? At one point there was code here. The function is left in
516 to make it easy to experiment. */
520 call_operand (rtx op
, machine_mode mode
)
525 return call_address_operand (op
, mode
);
528 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
531 small_data_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
533 if (! TARGET_SDATA_USE
)
536 if (GET_CODE (op
) == SYMBOL_REF
)
537 return SYMBOL_REF_SMALL_P (op
);
539 if (GET_CODE (op
) == CONST
540 && GET_CODE (XEXP (op
, 0)) == PLUS
541 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
542 && satisfies_constraint_J (XEXP (XEXP (op
, 0), 1)))
543 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
548 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
551 addr24_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
558 if (GET_CODE (op
) == LABEL_REF
)
559 return TARGET_ADDR24
;
561 if (GET_CODE (op
) == SYMBOL_REF
)
563 else if (GET_CODE (op
) == CONST
564 && GET_CODE (XEXP (op
, 0)) == PLUS
565 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
566 && satisfies_constraint_M (XEXP (XEXP (op
, 0), 1)))
567 sym
= XEXP (XEXP (op
, 0), 0);
571 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
575 && (CONSTANT_POOL_ADDRESS_P (sym
)
576 || LIT_NAME_P (XSTR (sym
, 0))))
582 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
585 addr32_operand (rtx op
, machine_mode mode
)
589 if (GET_CODE (op
) == LABEL_REF
)
590 return TARGET_ADDR32
;
592 if (GET_CODE (op
) == SYMBOL_REF
)
594 else if (GET_CODE (op
) == CONST
595 && GET_CODE (XEXP (op
, 0)) == PLUS
596 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
597 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
599 sym
= XEXP (XEXP (op
, 0), 0);
603 return (! addr24_operand (sym
, mode
)
604 && ! small_data_operand (sym
, mode
));
607 /* Return 1 if OP is a function that can be called with the `bl' insn. */
610 call26_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
615 if (GET_CODE (op
) == SYMBOL_REF
)
616 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
618 return TARGET_CALL26
;
621 /* Return 1 if OP is a DImode const we want to handle inline.
622 This must match the code in the movdi pattern.
623 It is used by the 'G' constraint. */
626 easy_di_const (rtx op
)
628 rtx high_rtx
, low_rtx
;
629 HOST_WIDE_INT high
, low
;
631 split_double (op
, &high_rtx
, &low_rtx
);
632 high
= INTVAL (high_rtx
);
633 low
= INTVAL (low_rtx
);
634 /* Pick constants loadable with 2 16-bit `ldi' insns. */
635 if (high
>= -128 && high
<= 127
636 && low
>= -128 && low
<= 127)
641 /* Return 1 if OP is a DFmode const we want to handle inline.
642 This must match the code in the movdf pattern.
643 It is used by the 'H' constraint. */
646 easy_df_const (rtx op
)
651 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
652 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
653 if (l
[0] == 0 && l
[1] == 0)
655 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
660 /* Return 1 if OP is (mem (reg ...)).
661 This is used in insn length calcs. */
664 memreg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
666 return MEM_P (op
) && REG_P (XEXP (op
, 0));
669 /* Return nonzero if TYPE must be passed by indirect reference. */
672 m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
673 machine_mode mode
, const_tree type
,
674 bool named ATTRIBUTE_UNUSED
)
679 size
= int_size_in_bytes (type
);
681 size
= GET_MODE_SIZE (mode
);
683 return (size
< 0 || size
> 8);
688 /* X and Y are two things to compare using CODE. Emit the compare insn and
689 return the rtx for compare [arg0 of the if_then_else].
690 If need_compare is true then the comparison insn must be generated, rather
691 than being subsumed into the following branch instruction. */
694 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
696 enum rtx_code compare_code
;
697 enum rtx_code branch_code
;
698 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
703 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
704 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
705 case LT
: compare_code
= LT
; branch_code
= NE
; break;
706 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
707 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
708 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
709 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
710 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
711 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
712 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
720 switch (compare_code
)
723 if (satisfies_constraint_P (y
) /* Reg equal to small const. */
726 rtx tmp
= gen_reg_rtx (SImode
);
728 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
732 else if (CONSTANT_P (y
)) /* Reg equal to const. */
734 rtx tmp
= force_reg (GET_MODE (x
), y
);
738 if (register_operand (y
, SImode
) /* Reg equal to reg. */
739 || y
== const0_rtx
) /* Reg equal to zero. */
741 emit_insn (gen_cmp_eqsi_insn (x
, y
));
743 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
748 if (register_operand (y
, SImode
)
749 || satisfies_constraint_P (y
))
751 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
756 emit_insn (gen_cmp_ltsi_insn (x
, y
));
763 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
764 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
769 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
771 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
772 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
776 emit_insn (gen_cmp_ltsi_insn (x
, y
));
783 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
788 if (register_operand (y
, SImode
)
789 || satisfies_constraint_P (y
))
791 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
796 emit_insn (gen_cmp_ltusi_insn (x
, y
));
803 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
804 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
809 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
811 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
812 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
816 emit_insn (gen_cmp_ltusi_insn (x
, y
));
823 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
833 /* Reg/reg equal comparison. */
834 if (compare_code
== EQ
835 && register_operand (y
, SImode
))
836 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
838 /* Reg/zero signed comparison. */
839 if ((compare_code
== EQ
|| compare_code
== LT
)
841 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
843 /* Reg/smallconst equal comparison. */
844 if (compare_code
== EQ
845 && satisfies_constraint_P (y
))
847 rtx tmp
= gen_reg_rtx (SImode
);
849 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
850 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
853 /* Reg/const equal comparison. */
854 if (compare_code
== EQ
857 rtx tmp
= force_reg (GET_MODE (x
), y
);
859 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
866 y
= force_reg (GET_MODE (x
), y
);
869 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
872 y
= force_reg (GET_MODE (x
), y
);
876 switch (compare_code
)
879 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
882 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
885 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
892 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
896 gen_cond_store (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
898 machine_mode mode
= GET_MODE (op0
);
900 gcc_assert (mode
== SImode
);
904 if (!register_operand (op1
, mode
))
905 op1
= force_reg (mode
, op1
);
907 if (TARGET_M32RX
|| TARGET_M32R2
)
909 if (!reg_or_zero_operand (op2
, mode
))
910 op2
= force_reg (mode
, op2
);
912 emit_insn (gen_seq_insn_m32rx (op0
, op1
, op2
));
915 if (CONST_INT_P (op2
) && INTVAL (op2
) == 0)
917 emit_insn (gen_seq_zero_insn (op0
, op1
));
921 if (!reg_or_eq_int16_operand (op2
, mode
))
922 op2
= force_reg (mode
, op2
);
924 emit_insn (gen_seq_insn (op0
, op1
, op2
));
928 if (!CONST_INT_P (op2
)
929 || (INTVAL (op2
) != 0 && satisfies_constraint_K (op2
)))
933 if (reload_completed
|| reload_in_progress
)
936 reg
= gen_reg_rtx (SImode
);
937 emit_insn (gen_xorsi3 (reg
, op1
, op2
));
940 if (!register_operand (op1
, mode
))
941 op1
= force_reg (mode
, op1
);
943 emit_insn (gen_sne_zero_insn (op0
, op1
));
958 if (!register_operand (op1
, mode
))
959 op1
= force_reg (mode
, op1
);
961 if (!reg_or_int16_operand (op2
, mode
))
962 op2
= force_reg (mode
, op2
);
964 emit_insn (gen_slt_insn (op0
, op1
, op2
));
977 if (!register_operand (op1
, mode
))
978 op1
= force_reg (mode
, op1
);
980 if (!reg_or_int16_operand (op2
, mode
))
981 op2
= force_reg (mode
, op2
);
983 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
988 if (!register_operand (op1
, mode
))
989 op1
= force_reg (mode
, op1
);
991 if (!reg_or_int16_operand (op2
, mode
))
992 op2
= force_reg (mode
, op2
);
995 emit_insn (gen_sge_insn (op0
, op1
, op2
));
997 emit_insn (gen_sgeu_insn (op0
, op1
, op2
));
1002 if (!register_operand (op1
, mode
))
1003 op1
= force_reg (mode
, op1
);
1005 if (CONST_INT_P (op2
))
1007 HOST_WIDE_INT value
= INTVAL (op2
);
1008 if (value
>= 2147483647)
1010 emit_move_insn (op0
, const1_rtx
);
1014 op2
= GEN_INT (value
+ 1);
1015 if (value
< -32768 || value
>= 32767)
1016 op2
= force_reg (mode
, op2
);
1019 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
1021 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1025 if (!register_operand (op2
, mode
))
1026 op2
= force_reg (mode
, op2
);
1029 emit_insn (gen_sleu_insn (op0
, op1
, op2
));
1031 emit_insn (gen_sle_insn (op0
, op1
, op2
));
1040 /* Split a 2 word move (DI or DF) into component parts. */
1043 gen_split_move_double (rtx operands
[])
1045 machine_mode mode
= GET_MODE (operands
[0]);
1046 rtx dest
= operands
[0];
1047 rtx src
= operands
[1];
1050 /* We might have (SUBREG (MEM)) here, so just get rid of the
1051 subregs to make this code simpler. It is safe to call
1052 alter_subreg any time after reload. */
1053 if (GET_CODE (dest
) == SUBREG
)
1054 alter_subreg (&dest
, true);
1055 if (GET_CODE (src
) == SUBREG
)
1056 alter_subreg (&src
, true);
1061 int dregno
= REGNO (dest
);
1066 int sregno
= REGNO (src
);
1068 int reverse
= (dregno
== sregno
+ 1);
1070 /* We normally copy the low-numbered register first. However, if
1071 the first register operand 0 is the same as the second register of
1072 operand 1, we must copy in the opposite order. */
1073 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
1074 operand_subword (src
, reverse
, TRUE
, mode
)));
1076 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
1077 operand_subword (src
, !reverse
, TRUE
, mode
)));
1080 /* Reg = constant. */
1081 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
1084 split_double (src
, &words
[0], &words
[1]);
1085 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
1088 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
1093 else if (MEM_P (src
))
1095 /* If the high-address word is used in the address, we must load it
1096 last. Otherwise, load it first. */
1097 int reverse
= refers_to_regno_p (dregno
, XEXP (src
, 0));
1099 /* We used to optimize loads from single registers as
1103 if r3 were not used subsequently. However, the REG_NOTES aren't
1104 propagated correctly by the reload phase, and it can cause bad
1105 code to be generated. We could still try:
1107 ld r1,r3+; ld r2,r3; addi r3,-4
1109 which saves 2 bytes and doesn't force longword alignment. */
1110 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
1111 adjust_address (src
, SImode
,
1112 reverse
* UNITS_PER_WORD
)));
1114 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
1115 adjust_address (src
, SImode
,
1116 !reverse
* UNITS_PER_WORD
)));
1123 /* We used to optimize loads from single registers as
1127 if r3 were not used subsequently. However, the REG_NOTES aren't
1128 propagated correctly by the reload phase, and it can cause bad
1129 code to be generated. We could still try:
1131 st r1,r3; st r2,+r3; addi r3,-4
1133 which saves 2 bytes and doesn't force longword alignment. */
1134 else if (MEM_P (dest
) && REG_P (src
))
1136 emit_insn (gen_rtx_SET (adjust_address (dest
, SImode
, 0),
1137 operand_subword (src
, 0, TRUE
, mode
)));
1139 emit_insn (gen_rtx_SET (adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1140 operand_subword (src
, 1, TRUE
, mode
)));
1153 m32r_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1154 tree type
, bool named ATTRIBUTE_UNUSED
)
1156 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1160 (((mode
== BLKmode
&& type
)
1161 ? (unsigned int) int_size_in_bytes (type
)
1162 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1165 if (*cum
>= M32R_MAX_PARM_REGS
)
1167 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1168 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1172 return words
* UNITS_PER_WORD
;
1175 /* The ROUND_ADVANCE* macros are local to this file. */
1176 /* Round SIZE up to a word boundary. */
1177 #define ROUND_ADVANCE(SIZE) \
1178 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1180 /* Round arg MODE/TYPE up to the next word boundary. */
1181 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1182 ((MODE) == BLKmode \
1183 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1184 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1186 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1187 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1189 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1190 a reg. This includes arguments that have to be passed by reference as the
1191 pointer to them is passed in a reg if one is available (and that is what
1193 This macro is only used in this file. */
1194 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1195 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1197 /* Determine where to put an argument to a function.
1198 Value is zero to push the argument on the stack,
1199 or a hard register in which to store the argument.
1201 MODE is the argument's machine mode.
1202 TYPE is the data type of the argument (as a tree).
1203 This is null for libcalls where that information may
1205 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1206 the preceding args and about the function being called.
1207 NAMED is nonzero if this argument is a named parameter
1208 (otherwise it is an extra parameter matching an ellipsis). */
1209 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1210 and the rest are pushed. */
1213 m32r_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1214 const_tree type ATTRIBUTE_UNUSED
,
1215 bool named ATTRIBUTE_UNUSED
)
1217 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1219 return (PASS_IN_REG_P (*cum
, mode
, type
)
1220 ? gen_rtx_REG (mode
, ROUND_ADVANCE_CUM (*cum
, mode
, type
))
1224 /* Update the data in CUM to advance over an argument
1225 of mode MODE and data type TYPE.
1226 (TYPE is null for libcalls where that information may not be available.) */
1229 m32r_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1230 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1232 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1234 *cum
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1235 + ROUND_ADVANCE_ARG (mode
, type
));
1238 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1241 m32r_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1243 cumulative_args_t dummy
= pack_cumulative_args (NULL
);
1245 return m32r_pass_by_reference (dummy
, TYPE_MODE (type
), type
, false);
1248 /* Worker function for TARGET_FUNCTION_VALUE. */
1251 m32r_function_value (const_tree valtype
,
1252 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1253 bool outgoing ATTRIBUTE_UNUSED
)
1255 return gen_rtx_REG (TYPE_MODE (valtype
), 0);
1258 /* Worker function for TARGET_LIBCALL_VALUE. */
1261 m32r_libcall_value (machine_mode mode
,
1262 const_rtx fun ATTRIBUTE_UNUSED
)
1264 return gen_rtx_REG (mode
, 0);
1267 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1269 ??? What about r1 in DI/DF values. */
1272 m32r_function_value_regno_p (const unsigned int regno
)
1274 return (regno
== 0);
1277 /* Do any needed setup for a variadic function. For the M32R, we must
1278 create a register parameter block, and then copy any anonymous arguments
1279 in registers to memory.
1281 CUM has not been updated for the last named argument which has type TYPE
1282 and mode MODE, and we rely on this fact. */
1285 m32r_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
1286 tree type
, int *pretend_size
, int no_rtl
)
1293 /* All BLKmode values are passed by reference. */
1294 gcc_assert (mode
!= BLKmode
);
1296 first_anon_arg
= (ROUND_ADVANCE_CUM (*get_cumulative_args (cum
), mode
, type
)
1297 + ROUND_ADVANCE_ARG (mode
, type
));
1299 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1301 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1302 int first_reg_offset
= first_anon_arg
;
1303 /* Size in words to "pretend" allocate. */
1304 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1307 regblock
= gen_frame_mem (BLKmode
,
1308 plus_constant (Pmode
, arg_pointer_rtx
,
1309 FIRST_PARM_OFFSET (0)));
1310 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1311 move_block_from_reg (first_reg_offset
, regblock
, size
);
1313 *pretend_size
= (size
* UNITS_PER_WORD
);
1318 /* Return true if INSN is real instruction bearing insn. */
1321 m32r_is_insn (rtx insn
)
1323 return (NONDEBUG_INSN_P (insn
)
1324 && GET_CODE (PATTERN (insn
)) != USE
1325 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
1328 /* Increase the priority of long instructions so that the
1329 short instructions are scheduled ahead of the long ones. */
1332 m32r_adjust_priority (rtx_insn
*insn
, int priority
)
1334 if (m32r_is_insn (insn
)
1335 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1342 /* Indicate how many instructions can be issued at the same time.
1343 This is sort of a lie. The m32r can issue only 1 long insn at
1344 once, but it can issue 2 short insns. The default therefore is
1345 set at 2, but this can be overridden by the command line option
1349 m32r_issue_rate (void)
1351 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1354 /* Cost functions. */
1355 /* Memory is 3 times as expensive as registers.
1356 ??? Is that the right way to look at it? */
1359 m32r_memory_move_cost (machine_mode mode
,
1360 reg_class_t rclass ATTRIBUTE_UNUSED
,
1361 bool in ATTRIBUTE_UNUSED
)
1363 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1370 m32r_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
1371 int opno ATTRIBUTE_UNUSED
, int *total
,
1372 bool speed ATTRIBUTE_UNUSED
)
1376 /* Small integers are as cheap as registers. 4 byte values can be
1377 fetched as immediate constants - let's give that the cost of an
1380 if (INT16_P (INTVAL (x
)))
1390 *total
= COSTS_N_INSNS (1);
1397 split_double (x
, &high
, &low
);
1398 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1399 + !INT16_P (INTVAL (low
)));
1404 *total
= COSTS_N_INSNS (3);
1411 *total
= COSTS_N_INSNS (10);
1419 /* Type of function DECL.
1421 The result is cached. To reset the cache at the end of a function,
1422 call with DECL = NULL_TREE. */
1424 enum m32r_function_type
1425 m32r_compute_function_type (tree decl
)
1428 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1429 /* Last function we were called for. */
1430 static tree last_fn
= NULL_TREE
;
1432 /* Resetting the cached value? */
1433 if (decl
== NULL_TREE
)
1435 fn_type
= M32R_FUNCTION_UNKNOWN
;
1436 last_fn
= NULL_TREE
;
1440 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1443 /* Compute function type. */
1444 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1445 ? M32R_FUNCTION_INTERRUPT
1446 : M32R_FUNCTION_NORMAL
);
1451 \f/* Function prologue/epilogue handlers. */
1453 /* M32R stack frames look like:
1455 Before call After call
1456 +-----------------------+ +-----------------------+
1458 high | local variables, | | local variables, |
1459 mem | reg save area, etc. | | reg save area, etc. |
1461 +-----------------------+ +-----------------------+
1463 | arguments on stack. | | arguments on stack. |
1465 SP+0->+-----------------------+ +-----------------------+
1466 | reg parm save area, |
1467 | only created for |
1468 | variable argument |
1470 +-----------------------+
1471 | previous frame ptr |
1472 +-----------------------+
1474 | register save area |
1476 +-----------------------+
1478 +-----------------------+
1482 +-----------------------+
1484 | alloca allocations |
1486 +-----------------------+
1488 low | arguments on stack |
1490 SP+0->+-----------------------+
1493 1) The "reg parm save area" does not exist for non variable argument fns.
1494 2) The "reg parm save area" can be eliminated completely if we saved regs
1495 containing anonymous args separately but that complicates things too
1496 much (so it's not done).
1497 3) The return address is saved after the register save area so as to have as
1498 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1500 /* Structure to be filled in by m32r_compute_frame_size with register
1501 save masks, and offsets for the current function. */
1502 struct m32r_frame_info
1504 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1505 unsigned int extra_size
; /* # bytes of extra stuff. */
1506 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1507 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1508 unsigned int reg_size
; /* # bytes needed to store regs. */
1509 unsigned int var_size
; /* # bytes that variables take up. */
1510 unsigned int gmask
; /* Mask of saved gp registers. */
1511 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1512 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1513 int initialized
; /* Nonzero if frame size already calculated. */
1516 /* Current frame information calculated by m32r_compute_frame_size. */
1517 static struct m32r_frame_info current_frame_info
;
1519 /* Zero structure to initialize current_frame_info. */
1520 static struct m32r_frame_info zero_frame_info
;
1522 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1523 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1525 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1526 The return address and frame pointer are treated separately.
1527 Don't consider them here. */
1528 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1529 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1530 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1532 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1533 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1535 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1536 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1538 /* Return the bytes needed to compute the frame pointer from the current
1541 SIZE is the size needed for local variables. */
1544 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1547 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1548 unsigned int reg_size
;
1550 enum m32r_function_type fn_type
;
1552 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1555 var_size
= M32R_STACK_ALIGN (size
);
1556 args_size
= M32R_STACK_ALIGN (crtl
->outgoing_args_size
);
1557 pretend_size
= crtl
->args
.pretend_args_size
;
1558 extra_size
= FIRST_PARM_OFFSET (0);
1559 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1563 /* See if this is an interrupt handler. Call used registers must be saved
1565 fn_type
= m32r_compute_function_type (current_function_decl
);
1566 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1568 /* Calculate space needed for registers. */
1569 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1571 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1572 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1574 reg_size
+= UNITS_PER_WORD
;
1575 gmask
|= 1 << regno
;
1579 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1580 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1582 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1584 total_size
+= reg_size
;
1586 /* ??? Not sure this is necessary, and I don't think the epilogue
1587 handler will do the right thing if this changes total_size. */
1588 total_size
= M32R_STACK_ALIGN (total_size
);
1590 /* frame_size = total_size - (pretend_size + reg_size); */
1592 /* Save computed information. */
1593 current_frame_info
.total_size
= total_size
;
1594 current_frame_info
.extra_size
= extra_size
;
1595 current_frame_info
.pretend_size
= pretend_size
;
1596 current_frame_info
.var_size
= var_size
;
1597 current_frame_info
.args_size
= args_size
;
1598 current_frame_info
.reg_size
= reg_size
;
1599 current_frame_info
.gmask
= gmask
;
1600 current_frame_info
.initialized
= reload_completed
;
1602 /* Ok, we're done. */
1606 /* Worker function for TARGET_CAN_ELIMINATE. */
1609 m32r_can_eliminate (const int from
, const int to
)
1611 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1612 ? ! frame_pointer_needed
1617 /* The table we use to reference PIC data. */
1618 static rtx global_offset_table
;
1621 m32r_reload_lr (rtx sp
, int size
)
1623 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1626 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, sp
)));
1627 else if (size
< 32768)
1628 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
,
1629 gen_rtx_PLUS (Pmode
, sp
,
1633 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1635 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1636 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1637 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, tmp
)));
1644 m32r_load_pic_register (void)
1646 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1647 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1648 GEN_INT (TARGET_MODEL_SMALL
)));
1650 /* Need to emit this whether or not we obey regdecls,
1651 since setjmp/longjmp can cause life info to screw up. */
1652 emit_use (pic_offset_table_rtx
);
1655 /* Expand the m32r prologue as a series of insns. */
1658 m32r_expand_prologue (void)
1663 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1666 if (! current_frame_info
.initialized
)
1667 m32r_compute_frame_size (get_frame_size ());
1669 if (flag_stack_usage_info
)
1670 current_function_static_stack_size
= current_frame_info
.total_size
;
1672 gmask
= current_frame_info
.gmask
;
1674 /* These cases shouldn't happen. Catch them now. */
1675 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1677 /* Allocate space for register arguments if this is a variadic function. */
1678 if (current_frame_info
.pretend_size
!= 0)
1680 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1681 the wrong result on a 64-bit host. */
1682 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1683 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1685 GEN_INT (-pretend_size
)));
1688 /* Save any registers we need to and set up fp. */
1689 if (current_frame_info
.save_fp
)
1690 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1692 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1694 /* Save any needed call-saved regs (and call-used if this is an
1695 interrupt handler). */
1696 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1698 if ((gmask
& (1 << regno
)) != 0)
1699 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1700 gen_rtx_REG (Pmode
, regno
)));
1703 if (current_frame_info
.save_lr
)
1704 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1705 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1707 /* Allocate the stack frame. */
1708 frame_size
= (current_frame_info
.total_size
1709 - (current_frame_info
.pretend_size
1710 + current_frame_info
.reg_size
));
1712 if (frame_size
== 0)
1713 ; /* Nothing to do. */
1714 else if (frame_size
<= 32768)
1715 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1716 GEN_INT (-frame_size
)));
1719 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1721 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1722 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1725 if (frame_pointer_needed
)
1726 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1729 /* Push lr for mcount (form_pc, x). */
1730 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1731 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1735 m32r_load_pic_register ();
1736 m32r_reload_lr (stack_pointer_rtx
,
1737 (crtl
->profile
? 0 : frame_size
));
1740 if (crtl
->profile
&& !pic_reg_used
)
1741 emit_insn (gen_blockage ());
1745 /* Set up the stack and frame pointer (if desired) for the function.
1746 Note, if this is changed, you need to mirror the changes in
1747 m32r_compute_frame_size which calculates the prolog size. */
1750 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1752 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1754 /* If this is an interrupt handler, mark it as such. */
1755 if (M32R_INTERRUPT_P (fn_type
))
1756 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1758 if (! current_frame_info
.initialized
)
1759 m32r_compute_frame_size (size
);
1761 /* This is only for the human reader. */
1763 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1765 current_frame_info
.var_size
,
1766 current_frame_info
.reg_size
/ 4,
1767 current_frame_info
.args_size
,
1768 current_frame_info
.extra_size
);
1771 /* Output RTL to pop register REGNO from the stack. */
1778 x
= emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode
, regno
),
1779 stack_pointer_rtx
));
1780 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
1783 /* Expand the m32r epilogue as a series of insns. */
1786 m32r_expand_epilogue (void)
1789 int noepilogue
= FALSE
;
1792 gcc_assert (current_frame_info
.initialized
);
1793 total_size
= current_frame_info
.total_size
;
1795 if (total_size
== 0)
1797 rtx insn
= get_last_insn ();
1799 /* If the last insn was a BARRIER, we don't have to write any code
1800 because a jump (aka return) was put there. */
1801 if (insn
&& NOTE_P (insn
))
1802 insn
= prev_nonnote_insn (insn
);
1803 if (insn
&& BARRIER_P (insn
))
1809 unsigned int var_size
= current_frame_info
.var_size
;
1810 unsigned int args_size
= current_frame_info
.args_size
;
1811 unsigned int gmask
= current_frame_info
.gmask
;
1812 int can_trust_sp_p
= !cfun
->calls_alloca
;
1814 if (flag_exceptions
)
1815 emit_insn (gen_blockage ());
1817 /* The first thing to do is point the sp at the bottom of the register
1821 unsigned int reg_offset
= var_size
+ args_size
;
1823 if (reg_offset
== 0)
1824 ; /* Nothing to do. */
1825 else if (reg_offset
< 32768)
1826 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1827 GEN_INT (reg_offset
)));
1830 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1832 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1833 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1837 else if (frame_pointer_needed
)
1839 unsigned int reg_offset
= var_size
+ args_size
;
1841 if (reg_offset
== 0)
1842 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1843 else if (reg_offset
< 32768)
1844 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_rtx
,
1845 GEN_INT (reg_offset
)));
1848 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1850 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1851 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1852 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1859 if (current_frame_info
.save_lr
)
1860 pop (RETURN_ADDR_REGNUM
);
1862 /* Restore any saved registers, in reverse order of course. */
1863 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1864 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1866 if ((gmask
& (1L << regno
)) != 0)
1870 if (current_frame_info
.save_fp
)
1871 pop (FRAME_POINTER_REGNUM
);
1873 /* Remove varargs area if present. */
1874 if (current_frame_info
.pretend_size
!= 0)
1875 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1876 GEN_INT (current_frame_info
.pretend_size
)));
1878 emit_insn (gen_blockage ());
1882 /* Do any necessary cleanup after a function to restore stack, frame,
1886 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED
,
1887 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1889 /* Reset state info for each function. */
1890 current_frame_info
= zero_frame_info
;
1891 m32r_compute_function_type (NULL_TREE
);
1894 /* Return nonzero if this function is known to have a null or 1 instruction
1898 direct_return (void)
1900 if (!reload_completed
)
1903 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl
)))
1906 if (! current_frame_info
.initialized
)
1907 m32r_compute_frame_size (get_frame_size ());
1909 return current_frame_info
.total_size
== 0;
1916 m32r_legitimate_pic_operand_p (rtx x
)
1918 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1921 if (GET_CODE (x
) == CONST
1922 && GET_CODE (XEXP (x
, 0)) == PLUS
1923 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1924 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1925 && (CONST_INT_P (XEXP (XEXP (x
, 0), 1))))
1932 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1935 printf("m32r_legitimize_pic_address()\n");
1938 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1940 rtx pic_ref
, address
;
1945 gcc_assert (!reload_in_progress
&& !reload_completed
);
1946 reg
= gen_reg_rtx (Pmode
);
1952 address
= gen_reg_rtx (Pmode
);
1956 crtl
->uses_pic_offset_table
= 1;
1958 if (GET_CODE (orig
) == LABEL_REF
1959 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
1961 emit_insn (gen_gotoff_load_addr (reg
, orig
));
1962 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1966 emit_insn (gen_pic_load_addr (address
, orig
));
1968 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1969 pic_ref
= gen_const_mem (Pmode
, address
);
1970 emit_move_insn (reg
, pic_ref
);
1973 else if (GET_CODE (orig
) == CONST
)
1977 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1978 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
1983 gcc_assert (!reload_in_progress
&& !reload_completed
);
1984 reg
= gen_reg_rtx (Pmode
);
1987 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1989 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
1991 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
1993 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
1998 if (CONST_INT_P (offset
))
2000 if (INT16_P (INTVAL (offset
)))
2001 return plus_constant (Pmode
, base
, INTVAL (offset
));
2004 gcc_assert (! reload_in_progress
&& ! reload_completed
);
2005 offset
= force_reg (Pmode
, offset
);
2009 return gen_rtx_PLUS (Pmode
, base
, offset
);
2016 m32r_legitimize_address (rtx x
, rtx orig_x ATTRIBUTE_UNUSED
,
2017 machine_mode mode ATTRIBUTE_UNUSED
)
2020 return m32r_legitimize_pic_address (x
, NULL_RTX
);
2025 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2028 m32r_mode_dependent_address_p (const_rtx addr
, addr_space_t as ATTRIBUTE_UNUSED
)
2030 if (GET_CODE (addr
) == LO_SUM
)
2036 /* Nested function support. */
2038 /* Emit RTL insns to initialize the variable parts of a trampoline.
2039 FNADDR is an RTX for the address of the function's pure code.
2040 CXT is an RTX for the static chain value for the function. */
2043 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2044 rtx fnaddr ATTRIBUTE_UNUSED
,
2045 rtx cxt ATTRIBUTE_UNUSED
)
2050 m32r_file_start (void)
2052 default_file_start ();
2054 if (flag_verbose_asm
)
2055 fprintf (asm_out_file
,
2056 "%s M32R/D special options: -G %d\n",
2057 ASM_COMMENT_START
, g_switch_value
);
2059 if (TARGET_LITTLE_ENDIAN
)
2060 fprintf (asm_out_file
, "\t.little\n");
2063 /* Print operand X (an rtx) in assembler syntax to file FILE.
2064 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2065 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2068 m32r_print_operand (FILE * file
, rtx x
, int code
)
2074 /* The 's' and 'p' codes are used by output_block_move() to
2075 indicate post-increment 's'tores and 'p're-increment loads. */
2078 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2080 output_operand_lossage ("invalid operand to %%s code");
2085 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2087 output_operand_lossage ("invalid operand to %%p code");
2091 /* Write second word of DImode or DFmode reference,
2092 register or memory. */
2094 fputs (reg_names
[REGNO (x
)+1], file
);
2097 fprintf (file
, "@(");
2098 /* Handle possible auto-increment. Since it is pre-increment and
2099 we have already done it, we can just use an offset of four. */
2100 /* ??? This is taken from rs6000.c I think. I don't think it is
2101 currently necessary, but keep it around. */
2102 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2103 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2104 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 4));
2106 output_address (plus_constant (Pmode
, XEXP (x
, 0), 4));
2110 output_operand_lossage ("invalid operand to %%R code");
2113 case 'H' : /* High word. */
2114 case 'L' : /* Low word. */
2117 /* L = least significant word, H = most significant word. */
2118 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2119 fputs (reg_names
[REGNO (x
)], file
);
2121 fputs (reg_names
[REGNO (x
)+1], file
);
2123 else if (CONST_INT_P (x
)
2124 || GET_CODE (x
) == CONST_DOUBLE
)
2128 split_double (x
, &first
, &second
);
2129 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2130 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2133 output_operand_lossage ("invalid operand to %%H/%%L code");
2140 if (GET_CODE (x
) != CONST_DOUBLE
2141 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2142 fatal_insn ("bad insn for 'A'", x
);
2144 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2145 fprintf (file
, "%s", str
);
2149 case 'B' : /* Bottom half. */
2150 case 'T' : /* Top half. */
2151 /* Output the argument to a `seth' insn (sets the Top half-word).
2152 For constants output arguments to a seth/or3 pair to set Top and
2153 Bottom halves. For symbols output arguments to a seth/add3 pair to
2154 set Top and Bottom halves. The difference exists because for
2155 constants seth/or3 is more readable but for symbols we need to use
2156 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2157 switch (GET_CODE (x
))
2164 split_double (x
, &first
, &second
);
2165 x
= WORDS_BIG_ENDIAN
? second
: first
;
2166 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2168 ? INTVAL (x
) & 0xffff
2169 : (INTVAL (x
) >> 16) & 0xffff));
2175 && small_data_operand (x
, VOIDmode
))
2177 fputs ("sda(", file
);
2178 output_addr_const (file
, x
);
2184 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2185 output_addr_const (file
, x
);
2189 output_operand_lossage ("invalid operand to %%T/%%B code");
2196 /* Output a load/store with update indicator if appropriate. */
2199 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2200 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2204 output_operand_lossage ("invalid operand to %%U code");
2208 /* Print a constant value negated. */
2209 if (CONST_INT_P (x
))
2210 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2212 output_operand_lossage ("invalid operand to %%N code");
2216 /* Print a const_int in hex. Used in comments. */
2217 if (CONST_INT_P (x
))
2218 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2222 fputs (IMMEDIATE_PREFIX
, file
);
2226 /* Do nothing special. */
2231 output_operand_lossage ("invalid operand output code");
2234 switch (GET_CODE (x
))
2237 fputs (reg_names
[REGNO (x
)], file
);
2242 if (GET_CODE (addr
) == PRE_INC
)
2244 if (!REG_P (XEXP (addr
, 0)))
2245 fatal_insn ("pre-increment address is not a register", x
);
2247 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2249 else if (GET_CODE (addr
) == PRE_DEC
)
2251 if (!REG_P (XEXP (addr
, 0)))
2252 fatal_insn ("pre-decrement address is not a register", x
);
2254 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2256 else if (GET_CODE (addr
) == POST_INC
)
2258 if (!REG_P (XEXP (addr
, 0)))
2259 fatal_insn ("post-increment address is not a register", x
);
2261 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2266 output_address (XEXP (x
, 0));
2272 /* We handle SFmode constants here as output_addr_const doesn't. */
2273 if (GET_MODE (x
) == SFmode
)
2278 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2279 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2280 fprintf (file
, "0x%08lx", l
);
2284 /* Fall through. Let output_addr_const deal with it. */
2287 output_addr_const (file
, x
);
2292 /* Print a memory address as an operand to reference that memory location. */
2295 m32r_print_operand_address (FILE * file
, rtx addr
)
2301 switch (GET_CODE (addr
))
2304 fputs (reg_names
[REGNO (addr
)], file
);
2308 if (CONST_INT_P (XEXP (addr
, 0)))
2309 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2310 else if (CONST_INT_P (XEXP (addr
, 1)))
2311 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2313 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2316 /* Print the offset first (if present) to conform to the manual. */
2320 fprintf (file
, "%d,", offset
);
2321 fputs (reg_names
[REGNO (base
)], file
);
2323 /* The chip doesn't support this, but left in for generality. */
2324 else if (REG_P (index
))
2325 fprintf (file
, "%s,%s",
2326 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2327 /* Not sure this can happen, but leave in for now. */
2328 else if (GET_CODE (index
) == SYMBOL_REF
)
2330 output_addr_const (file
, index
);
2332 fputs (reg_names
[REGNO (base
)], file
);
2335 fatal_insn ("bad address", addr
);
2337 else if (GET_CODE (base
) == LO_SUM
)
2339 gcc_assert (!index
&& REG_P (XEXP (base
, 0)));
2340 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2341 fputs ("sda(", file
);
2343 fputs ("low(", file
);
2344 output_addr_const (file
, plus_constant (Pmode
, XEXP (base
, 1),
2347 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2350 fatal_insn ("bad address", addr
);
2354 if (!REG_P (XEXP (addr
, 0)))
2355 fatal_insn ("lo_sum not of register", addr
);
2356 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2357 fputs ("sda(", file
);
2359 fputs ("low(", file
);
2360 output_addr_const (file
, XEXP (addr
, 1));
2362 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2365 case PRE_INC
: /* Assume SImode. */
2366 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2369 case PRE_DEC
: /* Assume SImode. */
2370 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2373 case POST_INC
: /* Assume SImode. */
2374 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2378 output_addr_const (file
, addr
);
2384 m32r_print_operand_punct_valid_p (unsigned char code
)
2386 return m32r_punct_chars
[code
];
2389 /* Return true if the operands are the constants 0 and 1. */
2392 zero_and_one (rtx operand1
, rtx operand2
)
2395 CONST_INT_P (operand1
)
2396 && CONST_INT_P (operand2
)
2397 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2398 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2401 /* Generate the correct assembler code to handle the conditional loading of a
2402 value into a register. It is known that the operands satisfy the
2403 conditional_move_operand() function above. The destination is operand[0].
2404 The condition is operand [1]. The 'true' value is operand [2] and the
2405 'false' value is operand [3]. */
2408 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2410 static char buffer
[100];
2411 const char * dest
= reg_names
[REGNO (operands
[0])];
2415 /* Destination must be a register. */
2416 gcc_assert (REG_P (operands
[0]));
2417 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2418 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2420 /* Check to see if the test is reversed. */
2421 if (GET_CODE (operands
[1]) == NE
)
2423 rtx tmp
= operands
[2];
2424 operands
[2] = operands
[3];
2428 sprintf (buffer
, "mvfc %s, cbr", dest
);
2430 /* If the true value was '0' then we need to invert the results of the move. */
2431 if (INTVAL (operands
[2]) == 0)
2432 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2438 /* Returns true if the registers contained in the two
2439 rtl expressions are different. */
2442 m32r_not_same_reg (rtx a
, rtx b
)
2447 while (GET_CODE (a
) == SUBREG
)
2453 while (GET_CODE (b
) == SUBREG
)
2459 return reg_a
!= reg_b
;
2464 m32r_function_symbol (const char *name
)
2466 int extra_flags
= 0;
2467 enum m32r_model model
;
2468 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2470 if (TARGET_MODEL_SMALL
)
2471 model
= M32R_MODEL_SMALL
;
2472 else if (TARGET_MODEL_MEDIUM
)
2473 model
= M32R_MODEL_MEDIUM
;
2474 else if (TARGET_MODEL_LARGE
)
2475 model
= M32R_MODEL_LARGE
;
2477 gcc_unreachable (); /* Shouldn't happen. */
2478 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2481 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2486 /* Use a library function to move some bytes. */
2489 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2491 /* We want to pass the size as Pmode, which will normally be SImode
2492 but will be DImode if we are using 64-bit longs and pointers. */
2493 if (GET_MODE (bytes_rtx
) != VOIDmode
2494 && GET_MODE (bytes_rtx
) != Pmode
)
2495 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2497 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL
,
2498 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2499 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2500 TYPE_UNSIGNED (sizetype
)),
2501 TYPE_MODE (sizetype
));
2504 /* Expand string/block move operations.
2506 operands[0] is the pointer to the destination.
2507 operands[1] is the pointer to the source.
2508 operands[2] is the number of bytes to move.
2509 operands[3] is the alignment.
2511 Returns 1 upon success, 0 otherwise. */
2514 m32r_expand_block_move (rtx operands
[])
2516 rtx orig_dst
= operands
[0];
2517 rtx orig_src
= operands
[1];
2518 rtx bytes_rtx
= operands
[2];
2519 rtx align_rtx
= operands
[3];
2520 int constp
= CONST_INT_P (bytes_rtx
);
2521 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2522 int align
= INTVAL (align_rtx
);
2527 if (constp
&& bytes
<= 0)
2530 /* Move the address into scratch registers. */
2531 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2532 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2534 if (align
> UNITS_PER_WORD
)
2535 align
= UNITS_PER_WORD
;
2537 /* If we prefer size over speed, always use a function call.
2538 If we do not know the size, use a function call.
2539 If the blocks are not word aligned, use a function call. */
2540 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2542 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2546 leftover
= bytes
% MAX_MOVE_BYTES
;
2549 /* If necessary, generate a loop to handle the bulk of the copy. */
2552 rtx_code_label
*label
= NULL
;
2553 rtx final_src
= NULL_RTX
;
2554 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2555 rtx rounded_total
= GEN_INT (bytes
);
2556 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2557 rtx new_src_reg
= gen_reg_rtx (SImode
);
2559 /* If we are going to have to perform this loop more than
2560 once, then generate a label and compute the address the
2561 source register will contain upon completion of the final
2563 if (bytes
> MAX_MOVE_BYTES
)
2565 final_src
= gen_reg_rtx (Pmode
);
2568 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2571 emit_insn (gen_movsi (final_src
, rounded_total
));
2572 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2575 label
= gen_label_rtx ();
2579 /* It is known that output_block_move() will update src_reg to point
2580 to the word after the end of the source block, and dst_reg to point
2581 to the last word of the destination block, provided that the block
2582 is MAX_MOVE_BYTES long. */
2583 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2584 new_dst_reg
, new_src_reg
));
2585 emit_move_insn (dst_reg
, new_dst_reg
);
2586 emit_move_insn (src_reg
, new_src_reg
);
2587 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2589 if (bytes
> MAX_MOVE_BYTES
)
2591 rtx test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2592 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2597 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2598 gen_reg_rtx (SImode
),
2599 gen_reg_rtx (SImode
)));
2604 /* Emit load/stores for a small constant word aligned block_move.
2606 operands[0] is the memory address of the destination.
2607 operands[1] is the memory address of the source.
2608 operands[2] is the number of bytes to move.
2609 operands[3] is a temp register.
2610 operands[4] is a temp register. */
2613 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2615 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2619 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2621 /* We do not have a post-increment store available, so the first set of
2622 stores are done without any increment, then the remaining ones can use
2623 the pre-increment addressing mode.
2625 Note: expand_block_move() also relies upon this behavior when building
2626 loops to copy large blocks. */
2635 output_asm_insn ("ld\t%5, %p1", operands
);
2636 output_asm_insn ("ld\t%6, %p1", operands
);
2637 output_asm_insn ("st\t%5, @%0", operands
);
2638 output_asm_insn ("st\t%6, %s0", operands
);
2642 output_asm_insn ("ld\t%5, %p1", operands
);
2643 output_asm_insn ("ld\t%6, %p1", operands
);
2644 output_asm_insn ("st\t%5, %s0", operands
);
2645 output_asm_insn ("st\t%6, %s0", operands
);
2650 else if (bytes
>= 4)
2655 output_asm_insn ("ld\t%5, %p1", operands
);
2658 output_asm_insn ("ld\t%6, %p1", operands
);
2661 output_asm_insn ("st\t%5, @%0", operands
);
2663 output_asm_insn ("st\t%5, %s0", operands
);
2669 /* Get the entire next word, even though we do not want all of it.
2670 The saves us from doing several smaller loads, and we assume that
2671 we cannot cause a page fault when at least part of the word is in
2672 valid memory [since we don't get called if things aren't properly
2674 int dst_offset
= first_time
? 0 : 4;
2675 /* The amount of increment we have to make to the
2676 destination pointer. */
2677 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2678 /* The same for the source pointer. */
2679 int src_inc_amount
= bytes
;
2683 /* If got_extra is true then we have already loaded
2684 the next word as part of loading and storing the previous word. */
2686 output_asm_insn ("ld\t%6, @%1", operands
);
2692 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2693 my_operands
[0] = operands
[5];
2694 my_operands
[1] = GEN_INT (dst_offset
);
2695 my_operands
[2] = operands
[0];
2696 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2698 /* If there is a byte left to store then increment the
2699 destination address and shift the contents of the source
2700 register down by 8 bits. We could not do the address
2701 increment in the store half word instruction, because it does
2702 not have an auto increment mode. */
2703 if (bytes
> 0) /* assert (bytes == 1) */
2714 my_operands
[0] = operands
[6];
2715 my_operands
[1] = GEN_INT (last_shift
);
2716 output_asm_insn ("srai\t%0, #%1", my_operands
);
2717 my_operands
[0] = operands
[6];
2718 my_operands
[1] = GEN_INT (dst_offset
);
2719 my_operands
[2] = operands
[0];
2720 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2723 /* Update the destination pointer if needed. We have to do
2724 this so that the patterns matches what we output in this
2727 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2729 my_operands
[0] = operands
[0];
2730 my_operands
[1] = GEN_INT (dst_inc_amount
);
2731 output_asm_insn ("addi\t%0, #%1", my_operands
);
2734 /* Update the source pointer if needed. We have to do this
2735 so that the patterns matches what we output in this
2738 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2740 my_operands
[0] = operands
[1];
2741 my_operands
[1] = GEN_INT (src_inc_amount
);
2742 output_asm_insn ("addi\t%0, #%1", my_operands
);
2752 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2755 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2756 unsigned int new_reg
)
2758 /* Interrupt routines can't clobber any register that isn't already used. */
2759 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2760 && !df_regs_ever_live_p (new_reg
))
2767 m32r_return_addr (int count
)
2772 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
2776 m32r_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2778 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
2779 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2780 0x017e8e17 : 0x178e7e01, SImode
));
2781 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
2782 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2783 0x0c00ae86 : 0x86ae000c, SImode
));
2784 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
2785 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2786 0xe627871e : 0x1e8727e6, SImode
));
2787 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
2788 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2789 0xc616c626 : 0x26c61fc6, SImode
));
2790 emit_move_insn (adjust_address (m_tramp
, SImode
, 16),
2792 emit_move_insn (adjust_address (m_tramp
, SImode
, 20),
2793 XEXP (DECL_RTL (fndecl
), 0));
2795 if (m32r_cache_flush_trap
>= 0)
2796 emit_insn (gen_flush_icache
2797 (validize_mem (adjust_address (m_tramp
, SImode
, 0)),
2798 gen_int_mode (m32r_cache_flush_trap
, SImode
)));
2799 else if (m32r_cache_flush_func
&& m32r_cache_flush_func
[0])
2800 emit_library_call (m32r_function_symbol (m32r_cache_flush_func
),
2801 LCT_NORMAL
, VOIDmode
, 3, XEXP (m_tramp
, 0), Pmode
,
2802 gen_int_mode (TRAMPOLINE_SIZE
, SImode
), SImode
,
2803 GEN_INT (3), SImode
);
2806 /* True if X is a reg that can be used as a base reg. */
2809 m32r_rtx_ok_for_base_p (const_rtx x
, bool strict
)
2816 if (GPR_P (REGNO (x
)))
2821 if (GPR_P (REGNO (x
))
2822 || REGNO (x
) == ARG_POINTER_REGNUM
2823 || ! HARD_REGISTER_P (x
))
2831 m32r_rtx_ok_for_offset_p (const_rtx x
)
2833 return (CONST_INT_P (x
) && INT16_P (INTVAL (x
)));
2837 m32r_legitimate_offset_addres_p (machine_mode mode ATTRIBUTE_UNUSED
,
2838 const_rtx x
, bool strict
)
2840 if (GET_CODE (x
) == PLUS
2841 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2842 && m32r_rtx_ok_for_offset_p (XEXP (x
, 1)))
2848 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2849 since more than one instruction will be required. */
2852 m32r_legitimate_lo_sum_addres_p (machine_mode mode
, const_rtx x
,
2855 if (GET_CODE (x
) == LO_SUM
2856 && (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2857 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2858 && CONSTANT_P (XEXP (x
, 1)))
2864 /* Is this a load and increment operation. */
2867 m32r_load_postinc_p (machine_mode mode
, const_rtx x
, bool strict
)
2869 if ((mode
== SImode
|| mode
== SFmode
)
2870 && GET_CODE (x
) == POST_INC
2871 && REG_P (XEXP (x
, 0))
2872 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2878 /* Is this an increment/decrement and store operation. */
2881 m32r_store_preinc_predec_p (machine_mode mode
, const_rtx x
, bool strict
)
2883 if ((mode
== SImode
|| mode
== SFmode
)
2884 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
2885 && REG_P (XEXP (x
, 0)) \
2886 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2892 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2895 m32r_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2897 if (m32r_rtx_ok_for_base_p (x
, strict
)
2898 || m32r_legitimate_offset_addres_p (mode
, x
, strict
)
2899 || m32r_legitimate_lo_sum_addres_p (mode
, x
, strict
)
2900 || m32r_load_postinc_p (mode
, x
, strict
)
2901 || m32r_store_preinc_predec_p (mode
, x
, strict
))
2908 m32r_conditional_register_usage (void)
2912 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2913 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2917 /* Implement TARGET_LEGITIMATE_CONSTANT_P
2919 We don't allow (plus symbol large-constant) as the relocations can't
2920 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2921 We allow all CONST_DOUBLE's as the md file patterns will force the
2922 constant to memory if they can't handle them. */
2925 m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2927 return !(GET_CODE (x
) == CONST
2928 && GET_CODE (XEXP (x
, 0)) == PLUS
2929 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2930 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
2931 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
2932 && UINTVAL (XEXP (XEXP (x
, 0), 1)) > 32767);