riscv: thead: Add support for the XTheadMemIdx ISA extension
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / xtheadmemidx-uindex-xtheadbb-update.c
blobee0486a526e4b2a00e23c4899bab71e34a062c9c
1 /* { dg-do compile } */
2 /* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
3 /* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx" { target { rv64 } } } */
4 /* { dg-options "-march=rv32gc_xtheadbb_xtheadmemidx" { target { rv32 } } } */
6 #include "xtheadmemidx-helpers.h"
8 LRU_REG_IMM_UPD(int8_t, 0)
9 LRU_REG_IMM_UPD(uint8_t, 1)
10 LRU_REG_IMM_UPD(int16_t, 2)
11 LRU_REG_IMM_UPD(uint16_t, 3)
12 LRU_REG_IMM_UPD(int32_t, 0)
13 #if __riscv_xlen == 64
14 LRU_REG_IMM_UPD(uint32_t, 1)
15 LRU_REG_IMM_UPD(int64_t, 2)
16 #endif
18 SRU_REG_IMM_UPD(int8_t, 3)
19 SRU_REG_IMM_UPD(int16_t, 0)
20 SRU_REG_IMM_UPD(int32_t, 1)
21 #if __riscv_xlen == 64
22 SRU_REG_IMM_UPD(int64_t, 2)
23 #endif
25 /* If the shifted value is used later, we cannot eliminate it. */
26 /* { dg-final { scan-assembler-times {\mslli\M} 5 { target { rv32 } } } } */
27 /* { dg-final { scan-assembler-times {\mslli\M} 8 { target { rv64 } } } } */