gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2020 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #define IN_TARGET_CODE 1
  21
  22 #include "config.h"
  23 #include "system.h"
  24 #include "coretypes.h"
  25 #include "tm.h"
  26
  27 const char *host_detect_local_cpu (int argc, const char **argv);
  28
  29 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  30 #include "cpuid.h"
  31 #include "common/config/i386/cpuinfo.h"
  32 #include "common/config/i386/i386-isas.h"
  33
  34 struct cache_desc
  35 {
  36   unsigned sizekb;
  37   unsigned assoc;
  38   unsigned line;
  39 };
  40
  41 /* Returns command line parameters that describe size and
  42    cache line size of the processor caches.  */
  43
  44 static char *
  45 describe_cache (struct cache_desc level1, struct cache_desc level2)
  46 {
  47   char size[100], line[100], size2[100];
  48
  49   /* At the moment, gcc does not use the information
  50      about the associativity of the cache.  */
  51
  52   snprintf (size, sizeof (size),
  53             "--param l1-cache-size=%u ", level1.sizekb);
  54   snprintf (line, sizeof (line),
  55             "--param l1-cache-line-size=%u ", level1.line);
  56
  57   snprintf (size2, sizeof (size2),
  58             "--param l2-cache-size=%u ", level2.sizekb);
  59
  60   return concat (size, line, size2, NULL);
  61 }
  62
  63 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  64
  65 static void
  66 detect_l2_cache (struct cache_desc *level2)
  67 {
  68   unsigned eax, ebx, ecx, edx;
  69   unsigned assoc;
  70
  71   __cpuid (0x80000006, eax, ebx, ecx, edx);
  72
  73   level2->sizekb = (ecx >> 16) & 0xffff;
  74   level2->line = ecx & 0xff;
  75
  76   assoc = (ecx >> 12) & 0xf;
  77   if (assoc == 6)
  78     assoc = 8;
  79   else if (assoc == 8)
  80     assoc = 16;
  81   else if (assoc >= 0xa && assoc <= 0xc)
  82     assoc = 32 + (assoc - 0xa) * 16;
  83   else if (assoc >= 0xd && assoc <= 0xe)
  84     assoc = 96 + (assoc - 0xd) * 32;
  85
  86   level2->assoc = assoc;
  87 }
  88
  89 /* Returns the description of caches for an AMD processor.  */
  90
  91 static const char *
  92 detect_caches_amd (unsigned max_ext_level)
  93 {
  94   unsigned eax, ebx, ecx, edx;
  95
  96   struct cache_desc level1, level2 = {0, 0, 0};
  97
  98   if (max_ext_level < 0x80000005)
  99     return "";
 100
 101   __cpuid (0x80000005, eax, ebx, ecx, edx);
 102
 103   level1.sizekb = (ecx >> 24) & 0xff;
 104   level1.assoc = (ecx >> 16) & 0xff;
 105   level1.line = ecx & 0xff;
 106
 107   if (max_ext_level >= 0x80000006)
 108     detect_l2_cache (&level2);
 109
 110   return describe_cache (level1, level2);
 111 }
 112
 113 /* Decodes the size, the associativity and the cache line size of
 114    L1/L2 caches of an Intel processor.  Values are based on
 115    "Intel Processor Identification and the CPUID Instruction"
 116    [Application Note 485], revision -032, December 2007.  */
 117
 118 static void
 119 decode_caches_intel (unsigned reg, bool xeon_mp,
 120                      struct cache_desc *level1, struct cache_desc *level2)
 121 {
 122   int i;
 123
 124   for (i = 24; i >= 0; i -= 8)
 125     switch ((reg >> i) & 0xff)
 126       {
 127       case 0x0a:
 128         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 129         break;
 130       case 0x0c:
 131         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 132         break;
 133       case 0x0d:
 134         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 135         break;
 136       case 0x0e:
 137         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 138         break;
 139       case 0x21:
 140         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 141         break;
 142       case 0x24:
 143         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 144         break;
 145       case 0x2c:
 146         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 147         break;
 148       case 0x39:
 149         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 150         break;
 151       case 0x3a:
 152         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 153         break;
 154       case 0x3b:
 155         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 156         break;
 157       case 0x3c:
 158         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 159         break;
 160       case 0x3d:
 161         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 162         break;
 163       case 0x3e:
 164         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 165         break;
 166       case 0x41:
 167         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 168         break;
 169       case 0x42:
 170         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 171         break;
 172       case 0x43:
 173         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 174         break;
 175       case 0x44:
 176         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 177         break;
 178       case 0x45:
 179         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 180         break;
 181       case 0x48:
 182         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 183         break;
 184       case 0x49:
 185         if (xeon_mp)
 186           break;
 187         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 188         break;
 189       case 0x4e:
 190         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 191         break;
 192       case 0x60:
 193         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 194         break;
 195       case 0x66:
 196         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 197         break;
 198       case 0x67:
 199         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 200         break;
 201       case 0x68:
 202         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 203         break;
 204       case 0x78:
 205         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 206         break;
 207       case 0x79:
 208         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 209         break;
 210       case 0x7a:
 211         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 212         break;
 213       case 0x7b:
 214         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 215         break;
 216       case 0x7c:
 217         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 218         break;
 219       case 0x7d:
 220         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 221         break;
 222       case 0x7f:
 223         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 224         break;
 225       case 0x80:
 226         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 227         break;
 228       case 0x82:
 229         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 230         break;
 231       case 0x83:
 232         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 233         break;
 234       case 0x84:
 235         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 236         break;
 237       case 0x85:
 238         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 239         break;
 240       case 0x86:
 241         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 242         break;
 243       case 0x87:
 244         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 245
 246       default:
 247         break;
 248       }
 249 }
 250
 251 /* Detect cache parameters using CPUID function 2.  */
 252
 253 static void
 254 detect_caches_cpuid2 (bool xeon_mp,
 255                       struct cache_desc *level1, struct cache_desc *level2)
 256 {
 257   unsigned regs[4];
 258   int nreps, i;
 259
 260   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 261
 262   nreps = regs[0] & 0x0f;
 263   regs[0] &= ~0x0f;
 264
 265   while (--nreps >= 0)
 266     {
 267       for (i = 0; i < 4; i++)
 268         if (regs[i] && !((regs[i] >> 31) & 1))
 269           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 270
 271       if (nreps)
 272         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 273     }
 274 }
 275
 276 /* Detect cache parameters using CPUID function 4. This
 277    method doesn't require hardcoded tables.  */
 278
 279 enum cache_type
 280 {
 281   CACHE_END = 0,
 282   CACHE_DATA = 1,
 283   CACHE_INST = 2,
 284   CACHE_UNIFIED = 3
 285 };
 286
 287 static void
 288 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 289                       struct cache_desc *level3)
 290 {
 291   struct cache_desc *cache;
 292
 293   unsigned eax, ebx, ecx, edx;
 294   int count;
 295
 296   for (count = 0;; count++)
 297     {
 298       __cpuid_count(4, count, eax, ebx, ecx, edx);
 299       switch (eax & 0x1f)
 300         {
 301         case CACHE_END:
 302           return;
 303         case CACHE_DATA:
 304         case CACHE_UNIFIED:
 305           {
 306             switch ((eax >> 5) & 0x07)
 307               {
 308               case 1:
 309                 cache = level1;
 310                 break;
 311               case 2:
 312                 cache = level2;
 313                 break;
 314               case 3:
 315                 cache = level3;
 316                 break;
 317               default:
 318                 cache = NULL;
 319               }
 320
 321             if (cache)
 322               {
 323                 unsigned sets = ecx + 1;
 324                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 325
 326                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 327                 cache->line = (ebx & 0x0fff) + 1;
 328
 329                 cache->sizekb = (cache->assoc * part
 330                                  * cache->line * sets) / 1024;
 331               }
 332           }
 333         default:
 334           break;
 335         }
 336     }
 337 }
 338
 339 /* Returns the description of caches for an Intel processor.  */
 340
 341 static const char *
 342 detect_caches_intel (bool xeon_mp, unsigned max_level,
 343                      unsigned max_ext_level, unsigned *l2sizekb)
 344 {
 345   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 346
 347   if (max_level >= 4)
 348     detect_caches_cpuid4 (&level1, &level2, &level3);
 349   else if (max_level >= 2)
 350     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 351   else
 352     return "";
 353
 354   if (level1.sizekb == 0)
 355     return "";
 356
 357   /* Let the L3 replace the L2. This assumes inclusive caches
 358      and single threaded program for now. */
 359   if (level3.sizekb)
 360     level2 = level3;
 361
 362   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 363      method if other methods fail to provide L2 cache parameters.  */
 364   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 365     detect_l2_cache (&level2);
 366
 367   *l2sizekb = level2.sizekb;
 368
 369   return describe_cache (level1, level2);
 370 }
 371
 372 /* This will be called by the spec parser in gcc.c when it sees
 373    a %:local_cpu_detect(args) construct.  Currently it will be called
 374    with either "arch" or "tune" as argument depending on if -march=native
 375    or -mtune=native is to be substituted.
 376
 377    It returns a string containing new command line parameters to be
 378    put at the place of the above two options, depending on what CPU
 379    this is executed.  E.g. "-march=k8" on an AMD64 machine
 380    for -march=native.
 381
 382    ARGC and ARGV are set depending on the actual arguments given
 383    in the spec.  */
 384
 385 const char *host_detect_local_cpu (int argc, const char **argv)
 386 {
 387   enum processor_type processor = PROCESSOR_I386;
 388   const char *cpu = "i386";
 389
 390   const char *cache = "";
 391   const char *options = "";
 392
 393   unsigned int ebx, ecx, edx;
 394
 395   unsigned int max_level, ext_level;
 396
 397   unsigned int vendor;
 398   unsigned int model, family;
 399
 400   bool arch;
 401
 402   unsigned int l2sizekb = 0;
 403
 404   if (argc < 1)
 405     return NULL;
 406
 407   arch = !strcmp (argv[0], "arch");
 408
 409   if (!arch && strcmp (argv[0], "tune"))
 410     return NULL;
 411
 412   struct __processor_model cpu_model = { };
 413   struct __processor_model2 cpu_model2 = { };
 414   unsigned int cpu_features2[SIZE_OF_CPU_FEATURES] = { };
 415
 416   if (cpu_indicator_init (&cpu_model, &cpu_model2, cpu_features2) != 0)
 417     goto done;
 418
 419   vendor = cpu_model.__cpu_vendor;
 420   family = cpu_model2.__cpu_family;
 421   model = cpu_model2.__cpu_model;
 422   max_level = cpu_model2.__cpu_max_level;
 423   ext_level = cpu_model2.__cpu_ext_level;
 424
 425   if (!arch)
 426     {
 427       if (vendor == VENDOR_AMD
 428           || vendor == VENDOR_CENTAUR
 429           || vendor == VENDOR_CYRIX
 430           || vendor == VENDOR_NSC)
 431         cache = detect_caches_amd (ext_level);
 432       else if (vendor == VENDOR_INTEL)
 433         {
 434           bool xeon_mp = (family == 15 && model == 6);
 435           cache = detect_caches_intel (xeon_mp, max_level,
 436                                        ext_level, &l2sizekb);
 437         }
 438     }
 439
 440   /* Extended features */
 441 #define has_feature(f) \
 442   has_cpu_feature (&cpu_model, cpu_features2, f)
 443
 444   if (vendor == VENDOR_AMD)
 445     {
 446       unsigned int name;
 447
 448       /* Detect geode processor by its processor signature.  */
 449       if (ext_level >= 0x80000002)
 450         __cpuid (0x80000002, name, ebx, ecx, edx);
 451       else
 452         name = 0;
 453
 454       if (name == signature_NSC_ebx)
 455         processor = PROCESSOR_GEODE;
 456       else if (has_feature (FEATURE_MOVBE) && family == 22)
 457         processor = PROCESSOR_BTVER2;
 458       else if (has_feature (FEATURE_CLWB))
 459         processor = PROCESSOR_ZNVER2;
 460       else if (has_feature (FEATURE_CLZERO))
 461         processor = PROCESSOR_ZNVER1;
 462       else if (has_feature (FEATURE_AVX2))
 463         processor = PROCESSOR_BDVER4;
 464       else if (has_feature (FEATURE_XSAVEOPT))
 465         processor = PROCESSOR_BDVER3;
 466       else if (has_feature (FEATURE_BMI))
 467         processor = PROCESSOR_BDVER2;
 468       else if (has_feature (FEATURE_XOP))
 469         processor = PROCESSOR_BDVER1;
 470       else if (has_feature (FEATURE_SSE4_A)
 471                && has_feature (FEATURE_SSSE3))
 472         processor = PROCESSOR_BTVER1;
 473       else if (has_feature (FEATURE_SSE4_A))
 474         processor = PROCESSOR_AMDFAM10;
 475       else if (has_feature (FEATURE_SSE2)
 476                || has_feature (FEATURE_LM))
 477         processor = PROCESSOR_K8;
 478       else if (has_feature (FEATURE_3DNOWP) && family == 6)
 479         processor = PROCESSOR_ATHLON;
 480       else if (has_feature (FEATURE_MMX))
 481         processor = PROCESSOR_K6;
 482       else
 483         processor = PROCESSOR_PENTIUM;
 484     }
 485   else if (vendor == VENDOR_CENTAUR)
 486     {
 487       processor = PROCESSOR_GENERIC;
 488
 489       switch (family)
 490         {
 491         default:
 492           /* We have no idea.  */
 493           break;
 494
 495         case 5:
 496           if (has_feature (FEATURE_3DNOW)
 497               || has_feature (FEATURE_MMX))
 498             processor = PROCESSOR_I486;
 499           break;
 500
 501         case 6:
 502           if (has_feature (FEATURE_LM))
 503             processor = PROCESSOR_K8;
 504           else if (model >= 9)
 505             processor = PROCESSOR_PENTIUMPRO;
 506           else if (model >= 6)
 507             processor = PROCESSOR_I486;
 508         }
 509     }
 510   else
 511     {
 512       switch (family)
 513         {
 514         case 4:
 515           processor = PROCESSOR_I486;
 516           break;
 517         case 5:
 518           processor = PROCESSOR_PENTIUM;
 519           break;
 520         case 6:
 521           processor = PROCESSOR_PENTIUMPRO;
 522           break;
 523         case 15:
 524           processor = PROCESSOR_PENTIUM4;
 525           break;
 526         default:
 527           /* We have no idea.  */
 528           processor = PROCESSOR_GENERIC;
 529         }
 530     }
 531
 532   switch (processor)
 533     {
 534     case PROCESSOR_I386:
 535       /* Default.  */
 536       break;
 537     case PROCESSOR_I486:
 538       if (arch && vendor == VENDOR_CENTAUR)
 539         {
 540           if (model >= 6)
 541             cpu = "c3";
 542           else if (has_feature (FEATURE_3DNOW))
 543             cpu = "winchip2";
 544           else
 545             /* Assume WinChip C6.  */
 546             cpu = "winchip-c6";
 547         }
 548       else
 549         cpu = "i486";
 550       break;
 551     case PROCESSOR_PENTIUM:
 552       if (arch && has_feature (FEATURE_MMX))
 553         cpu = "pentium-mmx";
 554       else
 555         cpu = "pentium";
 556       break;
 557     case PROCESSOR_PENTIUMPRO:
 558       cpu = get_intel_cpu (&cpu_model, &cpu_model2, cpu_features2);
 559       if (cpu == NULL)
 560         {
 561           if (arch)
 562             {
 563               /* This is unknown family 0x6 CPU.  */
 564               if (has_feature (FEATURE_AVX))
 565                 {
 566                   if (has_feature (FEATURE_AVX512VP2INTERSECT))
 567                     {
 568                       if (has_feature (FEATURE_TSXLDTRK))
 569                         /* Assume Sapphire Rapids.  */
 570                         cpu = "sapphirerapids";
 571                       else
 572                         /* Assume Tiger Lake */
 573                         cpu = "tigerlake";
 574                     }
 575                   /* Assume Cooper Lake */
 576                   else if (has_feature (FEATURE_AVX512BF16))
 577                     cpu = "cooperlake";
 578                   /* Assume Ice Lake Server.  */
 579                   else if (has_feature (FEATURE_WBNOINVD))
 580                     cpu = "icelake-server";
 581                 /* Assume Ice Lake.  */
 582                 else if (has_feature (FEATURE_AVX512BITALG))
 583                   cpu = "icelake-client";
 584                 /* Assume Cannon Lake.  */
 585                 else if (has_feature (FEATURE_AVX512VBMI))
 586                   cpu = "cannonlake";
 587                 /* Assume Knights Mill.  */
 588                 else if (has_feature (FEATURE_AVX5124VNNIW))
 589                   cpu = "knm";
 590                 /* Assume Knights Landing.  */
 591                 else if (has_feature (FEATURE_AVX512ER))
 592                   cpu = "knl";
 593                 /* Assume Skylake with AVX-512.  */
 594                 else if (has_feature (FEATURE_AVX512F))
 595                   cpu = "skylake-avx512";
 596                  /* Assume Alder Lake */
 597                 else if (has_feature (FEATURE_SERIALIZE))
 598                     cpu = "alderlake";
 599                 /* Assume Skylake.  */
 600                 else if (has_feature (FEATURE_CLFLUSHOPT))
 601                   cpu = "skylake";
 602                 /* Assume Broadwell.  */
 603                 else if (has_feature (FEATURE_ADX))
 604                   cpu = "broadwell";
 605                 else if (has_feature (FEATURE_AVX2))
 606                 /* Assume Haswell.  */
 607                   cpu = "haswell";
 608                 else
 609                 /* Assume Sandy Bridge.  */
 610                   cpu = "sandybridge";
 611               }
 612               else if (has_feature (FEATURE_SSE4_2))
 613                 {
 614                   if (has_feature (FEATURE_GFNI))
 615                     /* Assume Tremont.  */
 616                     cpu = "tremont";
 617                   else if (has_feature (FEATURE_SGX))
 618                     /* Assume Goldmont Plus.  */
 619                     cpu = "goldmont-plus";
 620                   else if (has_feature (FEATURE_XSAVE))
 621                     /* Assume Goldmont.  */
 622                     cpu = "goldmont";
 623                   else if (has_feature (FEATURE_MOVBE))
 624                     /* Assume Silvermont.  */
 625                     cpu = "silvermont";
 626                   else
 627                     /* Assume Nehalem.  */
 628                     cpu = "nehalem";
 629                 }
 630               else if (has_feature (FEATURE_SSSE3))
 631                 {
 632                   if (has_feature (FEATURE_MOVBE))
 633                     /* Assume Bonnell.  */
 634                     cpu = "bonnell";
 635                   else
 636                     /* Assume Core 2.  */
 637                     cpu = "core2";
 638                 }
 639               else if (has_feature (FEATURE_LM))
 640                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 641                    -march=native would be unusable for 64-bit compilations,
 642                    as all the CPUs below are 32-bit only.  */
 643                 cpu = "x86-64";
 644               else if (has_feature (FEATURE_SSE3))
 645                 {
 646                   if (vendor == VENDOR_CENTAUR)
 647                     /* C7 / Eden "Esther" */
 648                     cpu = "c7";
 649                   else
 650                     /* It is Core Duo.  */
 651                     cpu = "pentium-m";
 652                 }
 653               else if (has_feature (FEATURE_SSE2))
 654                 /* It is Pentium M.  */
 655                 cpu = "pentium-m";
 656               else if (has_feature (FEATURE_SSE))
 657                 {
 658                   if (vendor == VENDOR_CENTAUR)
 659                     {
 660                       if (model >= 9)
 661                         /* Eden "Nehemiah" */
 662                         cpu = "nehemiah";
 663                       else
 664                         cpu = "c3-2";
 665                     }
 666                   else
 667                     /* It is Pentium III.  */
 668                     cpu = "pentium3";
 669                 }
 670               else if (has_feature (FEATURE_MMX))
 671                 /* It is Pentium II.  */
 672                 cpu = "pentium2";
 673               else
 674                 /* Default to Pentium Pro.  */
 675                 cpu = "pentiumpro";
 676             }
 677           else
 678             /* For -mtune, we default to -mtune=generic.  */
 679             cpu = "generic";
 680         }
 681       break;
 682     case PROCESSOR_PENTIUM4:
 683       if (has_feature (FEATURE_SSE3))
 684         {
 685           if (has_feature (FEATURE_LM))
 686             cpu = "nocona";
 687           else
 688             cpu = "prescott";
 689         }
 690       else
 691         cpu = "pentium4";
 692       break;
 693     case PROCESSOR_GEODE:
 694       cpu = "geode";
 695       break;
 696     case PROCESSOR_K6:
 697       if (arch && has_feature (FEATURE_3DNOW))
 698         cpu = "k6-3";
 699       else
 700         cpu = "k6";
 701       break;
 702     case PROCESSOR_ATHLON:
 703       if (arch && has_feature (FEATURE_SSE))
 704         cpu = "athlon-4";
 705       else
 706         cpu = "athlon";
 707       break;
 708     case PROCESSOR_K8:
 709       if (arch)
 710         {
 711           if (vendor == VENDOR_CENTAUR)
 712             {
 713               if (has_feature (FEATURE_SSE4_1))
 714                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 715                 cpu = "nano-3000";
 716               else if (has_feature (FEATURE_SSSE3))
 717                 /* Nano 1000 | Nano 2000 */
 718                 cpu = "nano";
 719               else if (has_feature (FEATURE_SSE3))
 720                 /* Eden X2 */
 721                 cpu = "eden-x2";
 722               else
 723                 /* Default to k8 */
 724                 cpu = "k8";
 725             }
 726           else if (has_feature (FEATURE_SSE3))
 727             cpu = "k8-sse3";
 728           else
 729             cpu = "k8";
 730         }
 731       else
 732         /* For -mtune, we default to -mtune=k8 */
 733         cpu = "k8";
 734       break;
 735     case PROCESSOR_AMDFAM10:
 736       cpu = "amdfam10";
 737       break;
 738     case PROCESSOR_BDVER1:
 739       cpu = "bdver1";
 740       break;
 741     case PROCESSOR_BDVER2:
 742       cpu = "bdver2";
 743       break;
 744     case PROCESSOR_BDVER3:
 745       cpu = "bdver3";
 746       break;
 747     case PROCESSOR_BDVER4:
 748       cpu = "bdver4";
 749       break;
 750     case PROCESSOR_ZNVER1:
 751       cpu = "znver1";
 752       break;
 753     case PROCESSOR_ZNVER2:
 754       cpu = "znver2";
 755       break;
 756     case PROCESSOR_BTVER1:
 757       cpu = "btver1";
 758       break;
 759     case PROCESSOR_BTVER2:
 760       cpu = "btver2";
 761       break;
 762
 763     default:
 764       /* Use something reasonable.  */
 765       if (arch)
 766         {
 767           if (has_feature (FEATURE_SSSE3))
 768             cpu = "core2";
 769           else if (has_feature (FEATURE_SSE3))
 770             {
 771               if (has_feature (FEATURE_LM))
 772                 cpu = "nocona";
 773               else
 774                 cpu = "prescott";
 775             }
 776           else if (has_feature (FEATURE_LM))
 777             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 778                -march=native would be unusable for 64-bit compilations,
 779                as all the CPUs below are 32-bit only.  */
 780             cpu = "x86-64";
 781           else if (has_feature (FEATURE_SSE2))
 782             cpu = "pentium4";
 783           else if (has_feature (FEATURE_CMOV))
 784             cpu = "pentiumpro";
 785           else if (has_feature (FEATURE_MMX))
 786             cpu = "pentium-mmx";
 787           else if (has_feature (FEATURE_CMPXCHG8B))
 788             cpu = "pentium";
 789         }
 790       else
 791         cpu = "generic";
 792     }
 793
 794   if (arch)
 795     {
 796       unsigned int i;
 797       const char *const neg_option = " -mno-";
 798       for (i = 0; i < ARRAY_SIZE (isa_names_table); i++)
 799         if (isa_names_table[i].option)
 800           {
 801             if (has_feature (isa_names_table[i].feature))
 802               options = concat (options, " ",
 803                                 isa_names_table[i].option, NULL);
 804             else
 805               options = concat (options, neg_option,
 806                                 isa_names_table[i].option + 2, NULL);
 807           }
 808     }
 809
 810 done:
 811   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 812 }
 813 #else
 814
 815 /* If we are compiling with GCC where %EBX register is fixed, then the
 816    driver will just ignore -march and -mtune "native" target and will leave
 817    to the newly built compiler to generate code for its default target.  */
 818
 819 const char *host_detect_local_cpu (int, const char **)
 820 {
 821   return NULL;
 822 }
 823 #endif /* __GNUC__ */