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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
110 #ifndef CHECK_STACK_LIMIT
111 #define CHECK_STACK_LIMIT (-1)
112 #endif
114 /* Return index of given mode in mult and division cost tables. */
115 #define MODE_INDEX(mode) \
116 ((mode) == QImode ? 0 \
117 : (mode) == HImode ? 1 \
118 : (mode) == SImode ? 2 \
119 : (mode) == DImode ? 3 \
120 : 4)
122 /* Processor costs (relative to an add) */
123 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
124 #define COSTS_N_BYTES(N) ((N) * 2)
126 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
135 const
158 in QImode, HImode and SImode.
159 Relative to reg-reg move (2). */
163 in SFmode, DFmode and XFmode */
165 in SFmode, DFmode and XFmode */
168 in SImode and DImode */
170 in SImode and DImode */
173 in SImode, DImode and TImode */
175 in SImode, DImode and TImode */
188 ix86_size_memcpy,
189 ix86_size_memset,
201 };
203 /* Processor costs (relative to an add) */
206 DUMMY_STRINGOP_ALGS};
209 DUMMY_STRINGOP_ALGS};
211 static const
234 in QImode, HImode and SImode.
235 Relative to reg-reg move (2). */
239 in SFmode, DFmode and XFmode */
241 in SFmode, DFmode and XFmode */
244 in SImode and DImode */
246 in SImode and DImode */
249 in SImode, DImode and TImode */
251 in SImode, DImode and TImode */
264 i386_memcpy,
265 i386_memset,
277 };
281 DUMMY_STRINGOP_ALGS};
284 DUMMY_STRINGOP_ALGS};
286 static const
309 in QImode, HImode and SImode.
310 Relative to reg-reg move (2). */
314 in SFmode, DFmode and XFmode */
316 in SFmode, DFmode and XFmode */
319 in SImode and DImode */
321 in SImode and DImode */
324 in SImode, DImode and TImode */
326 in SImode, DImode and TImode */
329 shared for code and data, so 4kB is
330 not really precise. */
341 i486_memcpy,
342 i486_memset,
354 };
358 DUMMY_STRINGOP_ALGS};
361 DUMMY_STRINGOP_ALGS};
363 static const
386 in QImode, HImode and SImode.
387 Relative to reg-reg move (2). */
391 in SFmode, DFmode and XFmode */
393 in SFmode, DFmode and XFmode */
396 in SImode and DImode */
398 in SImode and DImode */
401 in SImode, DImode and TImode */
403 in SImode, DImode and TImode */
416 pentium_memcpy,
417 pentium_memset,
429 };
431 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
432 (we ensure the alignment). For small blocks inline loop is still a
433 noticeable win, for bigger blocks either rep movsl or rep movsb is
434 way to go. Rep movsb has apparently more expensive startup time in CPU,
435 but after 4K the difference is down in the noise. */
440 DUMMY_STRINGOP_ALGS};
445 DUMMY_STRINGOP_ALGS};
446 static const
469 in QImode, HImode and SImode.
470 Relative to reg-reg move (2). */
474 in SFmode, DFmode and XFmode */
476 in SFmode, DFmode and XFmode */
479 in SImode and DImode */
481 in SImode and DImode */
484 in SImode, DImode and TImode */
486 in SImode, DImode and TImode */
499 pentiumpro_memcpy,
500 pentiumpro_memset,
512 };
516 DUMMY_STRINGOP_ALGS};
519 DUMMY_STRINGOP_ALGS};
520 static const
543 in QImode, HImode and SImode.
544 Relative to reg-reg move (2). */
548 in SFmode, DFmode and XFmode */
550 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
574 geode_memcpy,
575 geode_memset,
587 };
591 DUMMY_STRINGOP_ALGS};
594 DUMMY_STRINGOP_ALGS};
595 static const
618 in QImode, HImode and SImode.
619 Relative to reg-reg move (2). */
623 in SFmode, DFmode and XFmode */
625 in SFmode, DFmode and XFmode */
628 in SImode and DImode */
630 in SImode and DImode */
633 in SImode, DImode and TImode */
635 in SImode, DImode and TImode */
639 have integrated l2 cache, but
640 optimizing for k6 is not important
641 enough to worry about that. */
651 k6_memcpy,
652 k6_memset,
664 };
666 /* For some reason, Athlon deals better with REP prefix (relative to loops)
667 compared to K8. Alignment becomes important after 8 bytes for memcpy and
668 128 bytes for memset. */
671 DUMMY_STRINGOP_ALGS};
674 DUMMY_STRINGOP_ALGS};
675 static const
698 in QImode, HImode and SImode.
699 Relative to reg-reg move (2). */
703 in SFmode, DFmode and XFmode */
705 in SFmode, DFmode and XFmode */
708 in SImode and DImode */
710 in SImode and DImode */
713 in SImode, DImode and TImode */
715 in SImode, DImode and TImode */
728 athlon_memcpy,
729 athlon_memset,
741 };
743 /* K8 has optimized REP instruction for medium sized blocks, but for very
744 small blocks it is better to use loop. For large blocks, libcall can
745 do nontemporary accesses and beat inline considerably. */
756 static const
779 in QImode, HImode and SImode.
780 Relative to reg-reg move (2). */
784 in SFmode, DFmode and XFmode */
786 in SFmode, DFmode and XFmode */
789 in SImode and DImode */
791 in SImode and DImode */
794 in SImode, DImode and TImode */
796 in SImode, DImode and TImode */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 k8_memcpy,
816 k8_memset,
828 };
830 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
831 very small blocks it is better to use loop. For large blocks, libcall can
832 do nontemporary accesses and beat inline considerably. */
865 in QImode, HImode and SImode.
866 Relative to reg-reg move (2). */
870 in SFmode, DFmode and XFmode */
872 in SFmode, DFmode and XFmode */
875 in SImode and DImode */
877 in SImode and DImode */
880 in SImode, DImode and TImode */
882 in SImode, DImode and TImode */
884 /* On K8:
885 MOVD reg64, xmmreg Double FSTORE 4
886 MOVD reg32, xmmreg Double FSTORE 4
887 On AMDFAM10:
888 MOVD reg64, xmmreg Double FADD 3
889 1/1 1/1
890 MOVD reg32, xmmreg Double FADD 3
891 1/1 1/1 */
895 /* New AMD processors never drop prefetches; if they cannot be performed
896 immediately, they are queued. We set number of simultaneous prefetches
897 to a large constant to reflect this (it probably is not a good idea not
898 to limit number of prefetches at all, as their execution also takes some
899 time). */
909 amdfam10_memcpy,
910 amdfam10_memset,
922 };
924 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
925 very small blocks it is better to use loop. For large blocks, libcall
926 can do nontemporary accesses and beat inline considerably. */
960 in QImode, HImode and SImode.
961 Relative to reg-reg move (2). */
965 in SFmode, DFmode and XFmode */
967 in SFmode, DFmode and XFmode */
970 in SImode and DImode */
972 in SImode and DImode */
975 in SImode, DImode and TImode */
977 in SImode, DImode and TImode */
979 /* On K8:
980 MOVD reg64, xmmreg Double FSTORE 4
981 MOVD reg32, xmmreg Double FSTORE 4
982 On AMDFAM10:
983 MOVD reg64, xmmreg Double FADD 3
984 1/1 1/1
985 MOVD reg32, xmmreg Double FADD 3
986 1/1 1/1 */
990 /* New AMD processors never drop prefetches; if they cannot be performed
991 immediately, they are queued. We set number of simultaneous prefetches
992 to a large constant to reflect this (it probably is not a good idea not
993 to limit number of prefetches at all, as their execution also takes some
994 time). */
1004 bdver1_memcpy,
1005 bdver1_memset,
1017 };
1019 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1020 very small blocks it is better to use loop. For large blocks, libcall
1021 can do nontemporary accesses and beat inline considerably. */
1056 in QImode, HImode and SImode.
1057 Relative to reg-reg move (2). */
1061 in SFmode, DFmode and XFmode */
1063 in SFmode, DFmode and XFmode */
1066 in SImode and DImode */
1068 in SImode and DImode */
1071 in SImode, DImode and TImode */
1073 in SImode, DImode and TImode */
1075 /* On K8:
1076 MOVD reg64, xmmreg Double FSTORE 4
1077 MOVD reg32, xmmreg Double FSTORE 4
1078 On AMDFAM10:
1079 MOVD reg64, xmmreg Double FADD 3
1080 1/1 1/1
1081 MOVD reg32, xmmreg Double FADD 3
1082 1/1 1/1 */
1086 /* New AMD processors never drop prefetches; if they cannot be performed
1087 immediately, they are queued. We set number of simultaneous prefetches
1088 to a large constant to reflect this (it probably is not a good idea not
1089 to limit number of prefetches at all, as their execution also takes some
1090 time). */
1100 bdver2_memcpy,
1101 bdver2_memset,
1113 };
1116 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1117 very small blocks it is better to use loop. For large blocks, libcall
1118 can do nontemporary accesses and beat inline considerably. */
1151 in QImode, HImode and SImode.
1152 Relative to reg-reg move (2). */
1156 in SFmode, DFmode and XFmode */
1158 in SFmode, DFmode and XFmode */
1161 in SImode and DImode */
1163 in SImode and DImode */
1166 in SImode, DImode and TImode */
1168 in SImode, DImode and TImode */
1173 /* New AMD processors never drop prefetches; if they cannot be performed
1174 immediately, they are queued. We set number of simultaneous prefetches
1175 to a large constant to reflect this (it probably is not a good idea not
1176 to limit number of prefetches at all, as their execution also takes some
1177 time). */
1187 bdver3_memcpy,
1188 bdver3_memset,
1200 };
1202 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1203 very small blocks it is better to use loop. For large blocks, libcall
1204 can do nontemporary accesses and beat inline considerably. */
1237 in QImode, HImode and SImode.
1238 Relative to reg-reg move (2). */
1242 in SFmode, DFmode and XFmode */
1244 in SFmode, DFmode and XFmode */
1247 in SImode and DImode */
1249 in SImode and DImode */
1252 in SImode, DImode and TImode */
1254 in SImode, DImode and TImode */
1259 /* New AMD processors never drop prefetches; if they cannot be performed
1260 immediately, they are queued. We set number of simultaneous prefetches
1261 to a large constant to reflect this (it probably is not a good idea not
1262 to limit number of prefetches at all, as their execution also takes some
1263 time). */
1273 bdver4_memcpy,
1274 bdver4_memset,
1286 };
1288 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1289 very small blocks it is better to use loop. For large blocks, libcall can
1290 do nontemporary accesses and beat inline considerably. */
1323 in QImode, HImode and SImode.
1324 Relative to reg-reg move (2). */
1328 in SFmode, DFmode and XFmode */
1330 in SFmode, DFmode and XFmode */
1333 in SImode and DImode */
1335 in SImode and DImode */
1338 in SImode, DImode and TImode */
1340 in SImode, DImode and TImode */
1342 /* On K8:
1343 MOVD reg64, xmmreg Double FSTORE 4
1344 MOVD reg32, xmmreg Double FSTORE 4
1345 On AMDFAM10:
1346 MOVD reg64, xmmreg Double FADD 3
1347 1/1 1/1
1348 MOVD reg32, xmmreg Double FADD 3
1349 1/1 1/1 */
1362 btver1_memcpy,
1363 btver1_memset,
1375 };
1409 in QImode, HImode and SImode.
1410 Relative to reg-reg move (2). */
1414 in SFmode, DFmode and XFmode */
1416 in SFmode, DFmode and XFmode */
1419 in SImode and DImode */
1421 in SImode and DImode */
1424 in SImode, DImode and TImode */
1426 in SImode, DImode and TImode */
1428 /* On K8:
1429 MOVD reg64, xmmreg Double FSTORE 4
1430 MOVD reg32, xmmreg Double FSTORE 4
1431 On AMDFAM10:
1432 MOVD reg64, xmmreg Double FADD 3
1433 1/1 1/1
1434 MOVD reg32, xmmreg Double FADD 3
1435 1/1 1/1 */
1447 btver2_memcpy,
1448 btver2_memset,
1460 };
1464 DUMMY_STRINGOP_ALGS};
1468 DUMMY_STRINGOP_ALGS};
1470 static const
1493 in QImode, HImode and SImode.
1494 Relative to reg-reg move (2). */
1498 in SFmode, DFmode and XFmode */
1500 in SFmode, DFmode and XFmode */
1503 in SImode and DImode */
1505 in SImode and DImode */
1508 in SImode, DImode and TImode */
1510 in SImode, DImode and TImode */
1523 pentium4_memcpy,
1524 pentium4_memset,
1536 };
1549 static const
1572 in QImode, HImode and SImode.
1573 Relative to reg-reg move (2). */
1577 in SFmode, DFmode and XFmode */
1579 in SFmode, DFmode and XFmode */
1582 in SImode and DImode */
1584 in SImode and DImode */
1587 in SImode, DImode and TImode */
1589 in SImode, DImode and TImode */
1602 nocona_memcpy,
1603 nocona_memset,
1615 };
1626 static const
1649 in QImode, HImode and SImode.
1650 Relative to reg-reg move (2). */
1654 in SFmode, DFmode and XFmode */
1656 in SFmode, DFmode and XFmode */
1659 in SImode and DImode */
1661 in SImode and DImode */
1664 in SImode, DImode and TImode */
1666 in SImode, DImode and TImode */
1679 atom_memcpy,
1680 atom_memset,
1692 };
1703 static const
1726 in QImode, HImode and SImode.
1727 Relative to reg-reg move (2). */
1731 in SFmode, DFmode and XFmode */
1733 in SFmode, DFmode and XFmode */
1736 in SImode and DImode */
1738 in SImode and DImode */
1741 in SImode, DImode and TImode */
1743 in SImode, DImode and TImode */
1756 slm_memcpy,
1757 slm_memset,
1769 };
1780 static const
1803 in QImode, HImode and SImode.
1804 Relative to reg-reg move (2). */
1808 in SFmode, DFmode and XFmode */
1810 in SFmode, DFmode and XFmode */
1813 in SImode and DImode */
1815 in SImode and DImode */
1818 in SImode, DImode and TImode */
1820 in SImode, DImode and TImode */
1833 intel_memcpy,
1834 intel_memset,
1846 };
1848 /* Generic should produce code tuned for Core-i7 (and newer chips)
1849 and btver1 (and newer chips). */
1861 static const
1864 /* On all chips taken into consideration lea is 2 cycles and more. With
1865 this cost however our current implementation of synth_mult results in
1866 use of unnecessary temporary registers causing regression on several
1867 SPECfp benchmarks. */
1888 in QImode, HImode and SImode.
1889 Relative to reg-reg move (2). */
1893 in SFmode, DFmode and XFmode */
1895 in SFmode, DFmode and XFmode */
1898 in SImode and DImode */
1900 in SImode and DImode */
1903 in SImode, DImode and TImode */
1905 in SImode, DImode and TImode */
1911 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1912 value is increased to perhaps more appropriate value of 5. */
1920 generic_memcpy,
1921 generic_memset,
1933 };
1935 /* core_cost should produce code tuned for Core familly of CPUs. */
1948 static const
1951 /* On all chips taken into consideration lea is 2 cycles and more. With
1952 this cost however our current implementation of synth_mult results in
1953 use of unnecessary temporary registers causing regression on several
1954 SPECfp benchmarks. */
1975 in QImode, HImode and SImode.
1976 Relative to reg-reg move (2). */
1980 in SFmode, DFmode and XFmode */
1982 in SFmode, DFmode and XFmode */
1985 in SImode and DImode */
1987 in SImode and DImode */
1990 in SImode, DImode and TImode */
1992 in SImode, DImode and TImode */
1998 /* FIXME perhaps more appropriate value is 5. */
2006 core_memcpy,
2007 core_memset,
2019 };
2022 /* Set by -mtune. */
2025 /* Set by -mtune or -Os. */
2028 /* Processor feature/optimization bitmasks. */
2029 #define m_386 (1<<PROCESSOR_I386)
2030 #define m_486 (1<<PROCESSOR_I486)
2031 #define m_PENT (1<<PROCESSOR_PENTIUM)
2032 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2033 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2034 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2035 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2036 #define m_CORE2 (1<<PROCESSOR_CORE2)
2037 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2038 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2039 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2040 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2041 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2042 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2043 #define m_INTEL (1<<PROCESSOR_INTEL)
2045 #define m_GEODE (1<<PROCESSOR_GEODE)
2046 #define m_K6 (1<<PROCESSOR_K6)
2047 #define m_K6_GEODE (m_K6 | m_GEODE)
2048 #define m_K8 (1<<PROCESSOR_K8)
2049 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2050 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2051 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2052 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2053 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2054 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2055 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2056 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2057 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2058 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2059 #define m_BTVER (m_BTVER1 | m_BTVER2)
2060 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2062 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2065 #undef DEF_TUNE
2066 #define DEF_TUNE(tune, name, selector) name,
2068 #undef DEF_TUNE
2069 };
2071 /* Feature tests against the various tunings. */
2074 /* Feature tests against the various tunings used to create ix86_tune_features
2075 based on the processor mask. */
2077 #undef DEF_TUNE
2078 #define DEF_TUNE(tune, name, selector) selector,
2080 #undef DEF_TUNE
2081 };
2083 /* Feature tests against the various architecture variations. */
2086 /* Feature tests against the various architecture variations, used to create
2087 ix86_arch_features based on the processor mask. */
2089 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2092 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2095 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2098 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2101 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2103 };
2105 /* In case the average insn count for single function invocation is
2106 lower than this constant, emit fast (but longer) prologue and
2107 epilogue code. */
2108 #define FAST_PROLOGUE_INSN_COUNT 20
2110 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2115 /* Array of the smallest class containing reg number REGNO, indexed by
2116 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2119 {
2120 /* ax, dx, cx, bx */
2122 /* si, di, bp, sp */
2124 /* FP registers */
2127 /* arg pointer */
2128 NON_Q_REGS,
2129 /* flags, fpsr, fpcr, frame */
2131 /* SSE registers */
2134 /* MMX registers */
2137 /* REX registers */
2140 /* SSE REX registers */
2143 /* AVX-512 SSE registers */
2148 /* Mask registers. */
2151 /* MPX bound registers */
2153 };
2155 /* The "default" register map used in 32bit mode. */
2158 {
2170 };
2172 /* The "default" register map used in 64bit mode. */
2175 {
2187 };
2189 /* Define the register numbers to be used in Dwarf debugging information.
2190 The SVR4 reference port C compiler uses the following register numbers
2191 in its Dwarf output code:
2192 0 for %eax (gcc regno = 0)
2193 1 for %ecx (gcc regno = 2)
2194 2 for %edx (gcc regno = 1)
2195 3 for %ebx (gcc regno = 3)
2196 4 for %esp (gcc regno = 7)
2197 5 for %ebp (gcc regno = 6)
2198 6 for %esi (gcc regno = 4)
2199 7 for %edi (gcc regno = 5)
2200 The following three DWARF register numbers are never generated by
2201 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2202 believes these numbers have these meanings.
2203 8 for %eip (no gcc equivalent)
2204 9 for %eflags (gcc regno = 17)
2205 10 for %trapno (no gcc equivalent)
2206 It is not at all clear how we should number the FP stack registers
2207 for the x86 architecture. If the version of SDB on x86/svr4 were
2208 a bit less brain dead with respect to floating-point then we would
2209 have a precedent to follow with respect to DWARF register numbers
2210 for x86 FP registers, but the SDB on x86/svr4 is so completely
2211 broken with respect to FP registers that it is hardly worth thinking
2212 of it as something to strive for compatibility with.
2213 The version of x86/svr4 SDB I have at the moment does (partially)
2214 seem to believe that DWARF register number 11 is associated with
2215 the x86 register %st(0), but that's about all. Higher DWARF
2216 register numbers don't seem to be associated with anything in
2217 particular, and even for DWARF regno 11, SDB only seems to under-
2218 stand that it should say that a variable lives in %st(0) (when
2219 asked via an `=' command) if we said it was in DWARF regno 11,
2220 but SDB still prints garbage when asked for the value of the
2221 variable in question (via a `/' command).
2222 (Also note that the labels SDB prints for various FP stack regs
2223 when doing an `x' command are all wrong.)
2224 Note that these problems generally don't affect the native SVR4
2225 C compiler because it doesn't allow the use of -O with -g and
2226 because when it is *not* optimizing, it allocates a memory
2227 location for each floating-point variable, and the memory
2228 location is what gets described in the DWARF AT_location
2229 attribute for the variable in question.
2230 Regardless of the severe mental illness of the x86/svr4 SDB, we
2231 do something sensible here and we use the following DWARF
2232 register numbers. Note that these are all stack-top-relative
2233 numbers.
2234 11 for %st(0) (gcc regno = 8)
2235 12 for %st(1) (gcc regno = 9)
2236 13 for %st(2) (gcc regno = 10)
2237 14 for %st(3) (gcc regno = 11)
2238 15 for %st(4) (gcc regno = 12)
2239 16 for %st(5) (gcc regno = 13)
2240 17 for %st(6) (gcc regno = 14)
2241 18 for %st(7) (gcc regno = 15)
2242 */
2244 {
2256 };
2258 /* Define parameter passing and return registers. */
2261 {
2263 };
2266 {
2268 };
2271 {
2273 };
2275 /* Additional registers that are clobbered by SYSV calls. */
2278 {
2283 };
2285 /* Define the structure for the machine field in struct function. */
2290 rtx rtl;
2292 };
2294 /* Structure describing stack frame layout.
2295 Stack grows downward:
2297 [arguments]
2298 <- ARG_POINTER
2299 saved pc
2301 saved static chain if ix86_static_chain_on_stack
2303 saved frame pointer if frame_pointer_needed
2304 <- HARD_FRAME_POINTER
2305 [saved regs]
2306 <- regs_save_offset
2307 [padding0]
2309 [saved SSE regs]
2310 <- sse_regs_save_offset
2311 [padding1] |
2312 | <- FRAME_POINTER
2313 [va_arg registers] |
2314 |
2315 [frame] |
2316 |
2317 [padding2] | = to_allocate
2318 <- STACK_POINTER
2319 */
2320 struct ix86_frame
2321 {
2328 /* The offsets relative to ARG_POINTER. */
2329 HOST_WIDE_INT frame_pointer_offset;
2330 HOST_WIDE_INT hard_frame_pointer_offset;
2331 HOST_WIDE_INT stack_pointer_offset;
2332 HOST_WIDE_INT hfp_save_offset;
2333 HOST_WIDE_INT reg_save_offset;
2334 HOST_WIDE_INT sse_reg_save_offset;
2336 /* When save_regs_using_mov is set, emit prologue using
2337 move instead of push instructions. */
2339 };
2341 /* Which cpu are we scheduling for. */
2344 /* Which cpu are we optimizing for. */
2347 /* Which instruction set architecture to use. */
2350 /* True if processor has SSE prefetch instruction. */
2353 /* -mstackrealign option */
2370 /* Preferred alignment for stack boundary in bits. */
2373 /* Alignment for incoming stack boundary in bits specified at
2374 command line. */
2377 /* Default alignment for incoming stack boundary in bits. */
2380 /* Alignment for incoming stack boundary in bits. */
2383 /* Calling abi specific va_list type nodes. */
2387 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2391 /* Fence to use after loop using movnt. */
2392 tree x86_mfence;
2394 /* Register class used for passing given 64bit part of the argument.
2395 These represent classes as documented by the PS ABI, with the exception
2396 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2397 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2399 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2400 whenever possible (upper half does contain padding). */
2401 enum x86_64_reg_class
2402 {
2403 X86_64_NO_CLASS,
2404 X86_64_INTEGER_CLASS,
2405 X86_64_INTEGERSI_CLASS,
2406 X86_64_SSE_CLASS,
2407 X86_64_SSESF_CLASS,
2408 X86_64_SSEDF_CLASS,
2409 X86_64_SSEUP_CLASS,
2410 X86_64_X87_CLASS,
2411 X86_64_X87UP_CLASS,
2412 X86_64_COMPLEX_X87_CLASS,
2413 X86_64_MEMORY_CLASS
2414 };
2416 #define MAX_CLASSES 8
2418 /* Table of constants used by fldpi, fldln2, etc.... */
2422 \f
2427 const_tree);
2439 enum ix86_function_specific_strings
2440 {
2441 IX86_FUNCTION_SPECIFIC_ARCH,
2442 IX86_FUNCTION_SPECIFIC_TUNE,
2443 IX86_FUNCTION_SPECIFIC_MAX
2444 };
2465 \f
2466 #ifndef SUBTARGET32_DEFAULT_CPU
2468 #endif
2470 /* Whether -mtune= or -march= were specified */
2474 /* Vectorization library interface and handlers. */
2480 /* Processor target table, indexed by processor number */
2481 struct ptt
2482 {
2490 };
2492 /* This table must be in sync with enum processor_type in i386.h. */
2494 {
2520 };
2521 \f
2522 static unsigned int
2524 {
2527 /* vzeroupper instructions are inserted immediately after reload to
2528 account for possible spills from 256bit registers. The pass
2529 reuses mode switching infrastructure by re-running mode insertion
2530 pass, so disable entities that have already been processed. */
2536 /* Call optimize_mode_switching. */
2539 }
2544 {
2554 };
2557 {
2561 {}
2563 /* opt_pass methods: */
2565 {
2567 }
2570 {
2572 }
2578 rtl_opt_pass *
2580 {
2582 }
2584 /* Return true if a red-zone is in use. */
2588 {
2590 }
2591 \f
2592 /* Return a string that documents the current -m options. The caller is
2593 responsible for freeing the string. */
2599 {
2600 struct ix86_target_opts
2601 {
2604 };
2606 /* This table is ordered so that options like -msse4.2 that imply
2607 preceding options while match those first. */
2609 {
2662 };
2664 /* Flag options. */
2666 {
2695 };
2712 /* Add -march= option. */
2714 {
2717 }
2719 /* Add -mtune= option. */
2721 {
2724 }
2726 /* Add -m32/-m64/-mx32. */
2728 {
2731 else
2733 isa &= ~ (OPTION_MASK_ISA_64BIT
2734 | OPTION_MASK_ABI_64
2736 }
2737 else
2741 /* Pick out the options in isa options. */
2743 {
2745 {
2748 }
2749 }
2752 {
2755 isa);
2756 }
2758 /* Add flag options. */
2760 {
2762 {
2765 }
2766 }
2769 {
2772 }
2774 /* Add -fpmath= option. */
2776 {
2779 {
2794 }
2795 }
2797 /* Any options? */
2803 /* Size the string. */
2807 {
2812 }
2814 /* Build the string. */
2819 {
2826 {
2828 line_len++;
2831 {
2835 }
2836 }
2840 {
2844 }
2845 }
2851 }
2853 /* Return true, if profiling code should be emitted before
2854 prologue. Otherwise it returns false.
2855 Note: For x86 with "hotfix" it is sorried. */
2856 static bool
2858 {
2860 }
2862 /* Function that is callable from the debugger to print the current
2863 options. */
2864 void ATTRIBUTE_UNUSED
2866 {
2872 {
2875 }
2876 else
2880 }
2883 #define DEF_ENUM
2884 #define DEF_ALG(alg, name) #name,
2886 #undef DEF_ENUM
2887 #undef DEF_ALG
2888 };
2890 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2891 The string is of the following form (or comma separated list of it):
2893 strategy_alg:max_size:[align|noalign]
2895 where the full size range for the strategy is either [0, max_size] or
2896 [min_size, max_size], in which min_size is the max_size + 1 of the
2897 preceding range. The last size range must have max_size == -1.
2899 Examples:
2901 1.
2902 -mmemcpy-strategy=libcall:-1:noalign
2904 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2907 2.
2908 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2910 This is to tell the compiler to use the following strategy for memset
2911 1) when the expected size is between [1, 16], use rep_8byte strategy;
2912 2) when the size is between [17, 2048], use vector_loop;
2913 3) when the size is > 2048, use libcall. */
2915 struct stringop_size_range
2916 {
2918 stringop_alg alg;
2920 };
2922 static void
2924 {
2932 else
2937 do
2938 {
2948 {
2952 }
2955 {
2959 }
2966 {
2968 alg_name,
2971 }
2979 else
2980 {
2984 }
2985 n++;
2987 }
2991 {
2996 }
2999 {
3003 }
3005 /* Now override the default algs array. */
3007 {
3013 }
3014 }
3016 \f
3017 /* parse -mtune-ctrl= option. When DUMP is true,
3018 print the features that are explicitly set. */
3020 static void
3022 {
3030 do
3031 {
3038 {
3039 curr_feature_string++;
3041 }
3043 {
3045 {
3051 }
3052 }
3057 }
3060 }
3062 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3063 processor type. */
3065 static void
3067 {
3072 {
3075 else
3077 }
3080 {
3085 }
3088 }
3091 /* Override various settings based on options. If MAIN_ARGS_P, the
3092 options are from the command line, otherwise they are from
3093 attributes. */
3095 static void
3099 {
3107 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3108 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3109 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3110 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3111 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3112 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3113 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3114 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3115 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3116 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3117 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3118 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3119 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3120 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3121 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3122 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3123 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3124 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3125 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3126 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3127 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3128 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3129 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3130 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3131 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3132 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3133 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3134 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3135 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3136 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3137 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3138 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3139 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3140 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3141 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3142 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3143 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3144 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3145 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3146 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3147 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3148 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3149 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3150 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3151 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3152 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3153 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3154 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3155 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3156 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3157 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3158 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3159 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3160 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3161 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3162 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3163 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3165 #define PTA_CORE2 \
3166 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3167 | PTA_CX16 | PTA_FXSR)
3168 #define PTA_NEHALEM \
3169 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3170 #define PTA_WESTMERE \
3171 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3172 #define PTA_SANDYBRIDGE \
3173 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3174 #define PTA_IVYBRIDGE \
3175 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3176 #define PTA_HASWELL \
3177 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3178 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3179 #define PTA_BROADWELL \
3180 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3181 #define PTA_BONNELL \
3182 (PTA_CORE2 | PTA_MOVBE)
3183 #define PTA_SILVERMONT \
3184 (PTA_WESTMERE | PTA_MOVBE)
3186 /* if this reaches 64, need to widen struct pta flags below */
3188 static struct pta
3189 {
3194 }
3196 {
3230 PTA_SANDYBRIDGE},
3232 PTA_SANDYBRIDGE},
3234 PTA_IVYBRIDGE},
3236 PTA_IVYBRIDGE},
3327 PTA_64BIT
3329 };
3331 /* -mrecip options. */
3332 static struct
3333 {
3336 }
3338 {
3345 };
3349 /* Set up prefix/suffix so the error messages refer to either the command
3350 line argument, or the attribute(target). */
3352 {
3356 }
3357 else
3358 {
3362 }
3364 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3365 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3368 #ifdef TARGET_BI_ARCH
3369 else
3370 {
3371 #if TARGET_BI_ARCH == 1
3372 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3373 is on and OPTION_MASK_ABI_X32 is off. We turn off
3374 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3375 -mx32. */
3378 #else
3379 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3380 on and OPTION_MASK_ABI_64 is off. We turn off
3381 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3382 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3386 #endif
3387 }
3388 #endif
3391 {
3392 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3393 OPTION_MASK_ABI_64 for TARGET_X32. */
3396 }
3399 | OPTION_MASK_ABI_X32
3402 {
3403 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3404 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3407 }
3409 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3410 SUBTARGET_OVERRIDE_OPTIONS;
3411 #endif
3413 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3414 SUBSUBTARGET_OVERRIDE_OPTIONS;
3415 #endif
3417 /* -fPIC is the default for x86_64. */
3421 /* Need to check -mtune=generic first. */
3423 {
3424 /* As special support for cross compilers we read -mtune=native
3425 as -mtune=generic. With native compilers we won't see the
3426 -mtune=native, as it was changed by the driver. */
3428 {
3430 }
3435 }
3436 else
3437 {
3441 {
3442 opts->x_ix86_tune_string
3445 }
3447 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3448 or defaulted. We need to use a sensible tune option. */
3450 {
3452 }
3453 }
3457 {
3458 /* rep; movq isn't available in 32-bit code. */
3461 }
3464 opts->x_ix86_arch_string
3467 else
3471 {
3479 }
3480 else
3487 /* For targets using ms ABI enable ms-extensions, if not
3488 explicit turned off. For non-ms ABI we turn off this
3489 option. */
3494 {
3496 {
3540 {
3543 }
3551 }
3552 }
3553 else
3554 {
3555 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3556 use of rip-relative addressing. This eliminates fixups that
3557 would otherwise be needed if this object is to be placed in a
3558 DLL, and is essentially just as efficient as direct addressing. */
3564 else
3566 }
3568 {
3571 }
3579 {
3582 /* Default cpu tuning to the architecture. */
3760 }
3784 {
3788 {
3790 {
3792 {
3800 }
3801 else
3804 }
3805 }
3806 /* Intel CPUs have always interpreted SSE prefetch instructions as
3807 NOPs; so, we can enable SSE prefetch instructions even when
3808 -mtune (rather than -march) points us to a processor that has them.
3809 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3810 higher processors. */
3815 }
3823 #ifndef USE_IX86_FRAME_POINTER
3824 #define USE_IX86_FRAME_POINTER 0
3825 #endif
3827 #ifndef USE_X86_64_FRAME_POINTER
3828 #define USE_X86_64_FRAME_POINTER 0
3829 #endif
3831 /* Set the default values for switches whose default depends on TARGET_64BIT
3832 in case they weren't overwritten by command line options. */
3834 {
3842 opts->x_flag_unwind_tables
3846 }
3847 else
3848 {
3850 opts->x_flag_omit_frame_pointer
3856 }
3861 else
3864 /* Arrange to set up i386_stack_locals for all functions. */
3867 /* Validate -mregparm= value. */
3869 {
3873 {
3877 }
3878 }
3882 /* Default align_* from the processor table. */
3884 {
3887 }
3889 {
3892 }
3894 {
3896 }
3898 /* Provide default for -mbranch-cost= value. */
3903 {
3904 opts->x_target_flags
3907 /* Enable by default the SSE and MMX builtins. Do allow the user to
3908 explicitly disable any of these. In particular, disabling SSE and
3909 MMX for kernel code is extremely useful. */
3911 opts->x_ix86_isa_flags
3918 }
3919 else
3920 {
3921 opts->x_target_flags
3925 opts->x_ix86_isa_flags
3928 /* i386 ABI does not specify red zone. It still makes sense to use it
3929 when programmer takes care to stack from being destroyed. */
3932 }
3934 /* Keep nonleaf frame pointers. */
3940 /* If we're doing fast math, we don't care about comparison order
3941 wrt NaNs. This lets us use a shorter comparison sequence. */
3945 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3946 since the insns won't need emulation. */
3950 /* Likewise, if the target doesn't have a 387, or we've specified
3951 software floating point, don't use 387 inline intrinsics. */
3955 /* Turn on MMX builtins for -msse. */
3957 opts->x_ix86_isa_flags
3960 /* Enable SSE prefetch. */
3965 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3968 opts->x_ix86_isa_flags
3971 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3974 opts->x_ix86_isa_flags
3977 /* Enable lzcnt instruction for -mabm. */
3979 opts->x_ix86_isa_flags
3982 /* Validate -mpreferred-stack-boundary= value or default it to
3983 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3986 {
3993 {
3997 else
4000 }
4001 else
4002 ix86_preferred_stack_boundary
4004 }
4006 /* Set the default value for -mstackrealign. */
4012 /* Validate -mincoming-stack-boundary= value or default it to
4013 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4016 {
4023 else
4024 {
4025 ix86_user_incoming_stack_boundary
4027 ix86_incoming_stack_boundary
4029 }
4030 }
4032 #ifndef NO_PROFILE_COUNTERS
4035 #endif
4039 /* Accept -msseregparm only if at least SSE support is enabled. */
4045 {
4047 {
4049 {
4052 }
4055 {
4058 }
4059 }
4060 }
4061 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4062 fpmath=387. The second is however default at many targets since the
4063 extra 80bit precision of temporaries is considered to be part of ABI.
4064 Overwrite the default at least for -ffast-math.
4065 TODO: -mfpmath=both seems to produce same performing code with bit
4066 smaller binaries. It is however not clear if register allocation is
4067 ready for this setting.
4068 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4069 codegen. We may switch to 387 with -ffast-math for size optimized
4070 functions. */
4074 else
4077 /* If the i387 is disabled, then do not return values in it. */
4081 /* Use external vectorized library in vectorizing intrinsics. */
4084 {
4095 }
4102 /* If stack probes are required, the space used for large function
4103 arguments on the stack must also be probed, so enable
4104 -maccumulate-outgoing-args so this happens in the prologue. */
4107 {
4112 }
4114 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4115 {
4121 }
4123 /* When scheduling description is not available, disable scheduler pass
4124 so it won't slow down the compilation and make x87 code slower. */
4145 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4147 && HAVE_prefetch
4152 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4153 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4158 {
4161 {
4163 ix86_gen_tls_local_dynamic_base_64
4165 }
4166 else
4167 {
4169 ix86_gen_tls_local_dynamic_base_64
4171 }
4172 }
4173 else
4177 {
4187 }
4188 else
4189 {
4199 }
4201 #ifdef USE_IX86_CLD
4202 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4205 #endif
4208 {
4213 }
4215 {
4219 }
4221 {
4222 #if defined(PROFILE_BEFORE_PROLOGUE)
4224 #else
4226 #endif
4227 }
4229 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4230 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4231 AVX unaligned load/store. */
4233 {
4243 /* Enable 128-bit AVX instruction generation
4244 for the auto-vectorizer. */
4248 }
4251 {
4258 {
4261 {
4263 q++;
4264 }
4265 else
4270 else
4271 {
4274 {
4277 }
4280 {
4284 }
4285 }
4290 else
4292 }
4293 }
4300 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4301 for 64-bit Bionic. */
4306 ? MASK_LONG_DOUBLE_128
4309 /* Only one of them can be active. */
4313 /* Save the initial options in case the user does function specific
4314 options. */
4316 target_option_default_node = target_option_current_node
4319 /* Handle stack protector */
4321 opts->x_ix86_stack_protector_guard
4324 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4326 {
4330 }
4333 {
4337 }
4338 }
4340 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4342 static void
4344 {
4346 struct register_pass_info insert_vzeroupper_info
4349 };
4354 /* This needs to be done at start up. It's convenient to do it here. */
4356 }
4358 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4361 {
4365 }
4367 /* Update register usage after having seen the compiler flags. */
4369 static void
4371 {
4375 /* The PIC register, if it exists, is fixed. */
4380 /* For 32-bit targets, squash the REX registers. */
4382 {
4389 }
4391 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4399 {
4400 /* Set/reset conditionally defined registers from
4401 CALL_USED_REGISTERS initializer. */
4405 /* Calculate registers of CLOBBERED_REGS register set
4406 as call used registers from GENERAL_REGS register set. */
4410 }
4412 /* If MMX is disabled, squash the registers. */
4418 /* If SSE is disabled, squash the registers. */
4424 /* If the FPU is disabled, squash the registers. */
4430 /* If AVX512F is disabled, squash the registers. */
4432 {
4438 }
4440 /* If MPX is disabled, squash the registers. */
4444 }
4446 \f
4447 /* Save the current options */
4449 static void
4452 {
4487 /* The fields are char but the variables are not; make sure the
4488 values fit in the fields. */
4493 }
4495 /* Restore the current options */
4497 static void
4500 {
4506 /* We don't change -fPIC. */
4543 /* Recreate the arch feature tests if the arch changed */
4545 {
4550 }
4552 /* Recreate the tune optimization tests */
4555 }
4557 /* Print the current options */
4559 static void
4562 {
4580 {
4583 }
4584 }
4586 \f
4587 /* Inner function to process the attribute((target(...))), take an argument and
4588 set the current options from the argument. If we have a list, recursively go
4589 over the list. */
4591 static bool
4596 {
4600 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4601 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4602 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4603 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4604 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4606 enum ix86_opt_type
4607 {
4608 ix86_opt_unknown,
4609 ix86_opt_yes,
4610 ix86_opt_no,
4611 ix86_opt_str,
4612 ix86_opt_enum,
4613 ix86_opt_isa
4614 };
4616 static const struct
4617 {
4624 /* isa options */
4677 /* enum options */
4680 /* string options */
4684 /* flag options */
4686 OPT_mcld,
4687 MASK_CLD),
4690 OPT_mfancy_math_387,
4691 MASK_NO_FANCY_MATH_387),
4694 OPT_mieee_fp,
4695 MASK_IEEE_FP),
4698 OPT_minline_all_stringops,
4699 MASK_INLINE_ALL_STRINGOPS),
4702 OPT_minline_stringops_dynamically,
4703 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4706 OPT_mno_align_stringops,
4707 MASK_NO_ALIGN_STRINGOPS),
4710 OPT_mrecip,
4711 MASK_RECIP),
4713 };
4715 /* If this is a list, recurse to get the options. */
4717 {
4724 enum_opts_set))
4728 }
4731 {
4734 }
4736 /* Handle multiple arguments separated by commas. */
4740 {
4754 {
4758 }
4759 else
4760 {
4763 }
4765 /* Recognize no-xxx. */
4767 {
4771 }
4772 else
4775 /* Find the option. */
4779 {
4787 {
4792 }
4793 }
4795 /* Process the option. */
4797 {
4800 }
4803 {
4809 }
4812 {
4818 else
4820 }
4823 {
4825 {
4828 }
4829 else
4831 }
4834 {
4842 global_dc);
4843 else
4844 {
4847 }
4848 }
4850 else
4852 }
4855 }
4857 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4859 tree
4863 {
4878 /* Process each of the options on the chain. */
4883 /* If the changed options are different from the default, rerun
4884 ix86_option_override_internal, and then save the options away.
4885 The string options are are attribute options, and will be undone
4886 when we copy the save structure. */
4892 {
4893 /* If we are using the default tune= or arch=, undo the string assigned,
4894 and use the default. */
4905 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4910 {
4913 }
4915 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4918 /* Add any builtin functions with the new isa if any. */
4921 /* Save the current options unless we are validating options for
4922 #pragma. */
4929 /* Free up memory allocated to hold the strings */
4932 }
4935 }
4937 /* Hook to validate attribute((target("string"))). */
4939 static bool
4942 tree args,
4944 {
4949 /* attribute((target("default"))) does nothing, beyond
4950 affecting multi-versioning. */
4959 /* Get the optimization options of the current function. */
4965 /* Init func_options. */
4973 /* Initialize func_options to the default before its target options can
4974 be set. */
4987 {
4992 }
4995 }
4997 \f
4998 /* Hook to determine if one function can safely inline another. */
5000 static bool
5002 {
5007 /* If callee has no option attributes, then it is ok to inline. */
5011 /* If caller has no option attributes, but callee does then it is not ok to
5012 inline. */
5016 else
5017 {
5021 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5022 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5023 function. */
5028 /* See if we have the same non-isa options. */
5032 /* See if arch, tune, etc. are the same. */
5045 else
5047 }
5050 }
5052 \f
5053 /* Remember the last target of ix86_set_current_function. */
5056 /* Set target globals to default. */
5058 static void
5060 {
5061 tree old_tree = (ix86_previous_fndecl
5066 {
5074 else
5077 }
5078 }
5080 /* Invalidate ix86_previous_fndecl cache. */
5081 void
5083 {
5086 }
5088 /* Establish appropriate back-end context for processing the function
5089 FNDECL. The argument might be NULL to indicate processing at top
5090 level, outside of any function scope. */
5091 static void
5093 {
5094 /* Only change the context if the function changes. This hook is called
5095 several times in the course of compiling a function, and we don't want to
5096 slow things down too much or call target_reinit when it isn't safe. */
5098 {
5099 tree old_tree = (ix86_previous_fndecl
5103 tree new_tree = (fndecl
5108 ;
5111 {
5116 else
5119 }
5124 }
5125 }
5127 \f
5128 /* Return true if this goes in large data/bss. */
5130 static bool
5132 {
5136 /* Functions are never large data. */
5140 /* Automatic variables are never large data. */
5145 {
5151 }
5152 else
5153 {
5156 /* If this is an incomplete type with size 0, then we can't put it
5157 in data because it might be too big when completed. Also,
5158 int_size_in_bytes returns -1 if size can vary or is larger than
5159 an integer in which case also it is safer to assume that it goes in
5160 large data. */
5163 }
5166 }
5168 /* Switch to the appropriate section for output of DECL.
5169 DECL is either a `VAR_DECL' node or a constant of some sort.
5170 RELOC indicates whether forming the initial value of DECL requires
5171 link-time relocations. */
5176 {
5178 {
5182 {
5216 /* We don't split these for medium model. Place them into
5217 default sections and hope for best. */
5219 }
5221 {
5222 /* We might get called with string constants, but get_named_section
5223 doesn't like them as they are not DECLs. Also, we need to set
5224 flags in that case. */
5228 }
5229 }
5231 }
5233 /* Select a set of attributes for section NAME based on the properties
5234 of DECL and whether or not RELOC indicates that DECL's initializer
5235 might contain runtime relocations. */
5237 static unsigned int ATTRIBUTE_UNUSED
5239 {
5253 }
5255 /* Build up a unique section name, expressed as a
5256 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5257 RELOC indicates whether the initial value of EXP requires
5258 link-time relocations. */
5260 static void ATTRIBUTE_UNUSED
5262 {
5264 {
5266 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5270 {
5294 /* We don't split these for medium model. Place them into
5295 default sections and hope for best. */
5297 }
5299 {
5306 /* If we're using one_only, then there needs to be a .gnu.linkonce
5307 prefix to the section name. */
5314 }
5315 }
5317 }
5319 #ifdef COMMON_ASM_OP
5320 /* This says how to output assembler code to declare an
5321 uninitialized external linkage data object.
5323 For medium model x86-64 we need to use .largecomm opcode for
5324 large objects. */
5325 void
5329 {
5333 else
5338 }
5339 #endif
5341 /* Utility function for targets to use in implementing
5342 ASM_OUTPUT_ALIGNED_BSS. */
5344 void
5347 {
5351 else
5354 #ifdef ASM_DECLARE_OBJECT_NAME
5357 #else
5358 /* Standard thing is just output label for the object. */
5362 }
5363 \f
5364 /* Decide whether we must probe the stack before any space allocation
5365 on this target. It's essentially TARGET_STACK_PROBE except when
5366 -fstack-check causes the stack to be already probed differently. */
5368 bool
5370 {
5371 /* Do not probe the stack twice if static stack checking is enabled. */
5376 }
5377 \f
5378 /* Decide whether we can make a sibling call to a function. DECL is the
5379 declaration of the function being targeted by the call and EXP is the
5380 CALL_EXPR representing the call. */
5382 static bool
5384 {
5388 /* If we are generating position-independent code, we cannot sibcall
5389 optimize any indirect call, or a direct call to a global function,
5390 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5392 && !TARGET_64BIT
5393 && flag_pic
5397 /* If we need to align the outgoing stack, then sibcalling would
5398 unalign the stack, which may break the called function. */
5404 {
5407 }
5408 else
5409 {
5410 /* We're looking at the CALL_EXPR, we need the type of the function. */
5415 }
5417 /* Check that the return value locations are the same. Like
5418 if we are returning floats on the 80387 register stack, we cannot
5419 make a sibcall from a function that doesn't return a float to a
5420 function that does or, conversely, from a function that does return
5421 a float to a function that doesn't; the necessary stack adjustment
5422 would not be executed. This is also the place we notice
5423 differences in the return value ABI. Note that it is ok for one
5424 of the functions to have void return type as long as the return
5425 value of the other is passed in a register. */
5430 {
5433 }
5435 ;
5440 {
5441 /* The SYSV ABI has more call-clobbered registers;
5442 disallow sibcalls from MS to SYSV. */
5446 }
5447 else
5448 {
5449 /* If this call is indirect, we'll need to be able to use a
5450 call-clobbered register for the address of the target function.
5451 Make sure that all such registers are not used for passing
5452 parameters. Note that DLLIMPORT functions are indirect. */
5455 {
5457 {
5458 /* ??? Need to count the actual number of registers to be used,
5459 not the possible number of registers. Fix later. */
5461 }
5462 }
5463 }
5465 /* Otherwise okay. That also includes certain types of indirect calls. */
5467 }
5469 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5470 and "sseregparm" calling convention attributes;
5471 arguments as in struct attribute_spec.handler. */
5473 static tree
5475 tree args,
5478 {
5483 {
5485 name);
5488 }
5490 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5492 {
5493 tree cst;
5496 {
5498 }
5501 {
5503 }
5507 {
5510 name);
5512 }
5514 {
5518 }
5521 }
5524 {
5525 /* Do not warn when emulating the MS ABI. */
5530 name);
5533 }
5535 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5537 {
5539 {
5541 }
5543 {
5545 }
5547 {
5549 }
5551 {
5553 }
5554 }
5556 /* Can combine stdcall with fastcall (redundant), regparm and
5557 sseregparm. */
5559 {
5561 {
5563 }
5565 {
5567 }
5569 {
5571 }
5572 }
5574 /* Can combine cdecl with regparm and sseregparm. */
5576 {
5578 {
5580 }
5582 {
5584 }
5586 {
5588 }
5589 }
5591 {
5594 name);
5596 {
5598 }
5600 {
5602 }
5604 {
5606 }
5607 }
5609 /* Can combine sseregparm with all attributes. */
5612 }
5614 /* The transactional memory builtins are implicitly regparm or fastcall
5615 depending on the ABI. Override the generic do-nothing attribute that
5616 these builtins were declared with, and replace it with one of the two
5617 attributes that we expect elsewhere. */
5619 static tree
5622 {
5623 tree alt;
5625 /* In no case do we want to add the placeholder attribute. */
5628 /* The 64-bit ABI is unchanged for transactional memory. */
5632 /* ??? Is there a better way to validate 32-bit windows? We have
5633 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5636 else
5637 {
5640 }
5644 }
5646 /* This function determines from TYPE the calling-convention. */
5648 unsigned int
5650 {
5653 tree attrs;
5660 {
5670 /* Regparam isn't allowed for thiscall and fastcall. */
5672 {
5677 }
5681 }
5688 || is_stdarg
5694 }
5696 /* Return 0 if the attributes for two types are incompatible, 1 if they
5697 are compatible, and 2 if they are nearly compatible (which causes a
5698 warning to be generated). */
5700 static int
5702 {
5718 }
5719 \f
5720 /* Return the regparm value for a function with the indicated TYPE and DECL.
5721 DECL may be NULL when calling function indirectly
5722 or considering a libcall. */
5724 static int
5726 {
5727 tree attr;
5738 {
5741 {
5744 }
5745 }
5751 /* Use register calling convention for local functions when possible. */
5754 /* Caller and callee must agree on the calling convention, so
5755 checking here just optimize means that with
5756 __attribute__((optimize (...))) caller could use regparm convention
5757 and callee not, or vice versa. Instead look at whether the callee
5758 is optimized or not. */
5761 {
5762 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5765 {
5768 /* Make sure no regparm register is taken by a
5769 fixed register variable. */
5774 /* We don't want to use regparm(3) for nested functions as
5775 these use a static chain pointer in the third argument. */
5779 /* In 32-bit mode save a register for the split stack. */
5783 /* Each fixed register usage increases register pressure,
5784 so less registers should be used for argument passing.
5785 This functionality can be overriden by an explicit
5786 regparm value. */
5789 globals++;
5791 local_regparm
5796 }
5797 }
5800 }
5802 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5803 DFmode (2) arguments in SSE registers for a function with the
5804 indicated TYPE and DECL. DECL may be NULL when calling function
5805 indirectly or considering a libcall. Otherwise return 0. */
5807 static int
5809 {
5812 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5813 by the sseregparm attribute. */
5816 {
5818 {
5820 {
5824 else
5827 }
5829 }
5832 }
5834 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5835 (and DFmode for SSE2) arguments in SSE registers. */
5838 {
5839 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5843 }
5846 }
5848 /* Return true if EAX is live at the start of the function. Used by
5849 ix86_expand_prologue to determine if we need special help before
5850 calling allocate_stack_worker. */
5852 static bool
5854 {
5855 /* Cheat. Don't bother working forward from ix86_function_regparm
5856 to the function type to whether an actual argument is located in
5857 eax. Instead just look at cfg info, which is still close enough
5858 to correct at this point. This gives false positives for broken
5859 functions that might use uninitialized data that happens to be
5860 allocated in eax, but who cares? */
5862 }
5864 static bool
5866 {
5867 tree attr;
5870 {
5876 /* For 32-bit MS-ABI the default is to keep aggregate
5877 return pointer. */
5880 }
5882 }
5884 /* Value is the number of bytes of arguments automatically
5885 popped when returning from a subroutine call.
5886 FUNDECL is the declaration node of the function (as a tree),
5887 FUNTYPE is the data type of the function (as a tree),
5888 or for a library call it is an identifier node for the subroutine name.
5889 SIZE is the number of bytes of arguments passed on the stack.
5891 On the 80386, the RTD insn may be used to pop them if the number
5892 of args is fixed, but if the number is variable then the caller
5893 must pop them all. RTD can't be used for library calls now
5894 because the library is compiled with the Unix compiler.
5895 Use of RTD is a selectable option, since it is incompatible with
5896 standard Unix calling sequences. If the option is not selected,
5897 the caller must always pop the args.
5899 The attribute stdcall is equivalent to RTD on a per module basis. */
5901 static int
5903 {
5906 /* None of the 64-bit ABIs pop arguments. */
5917 /* Lose any fake structure return argument if it is passed on the stack. */
5920 {
5924 }
5927 }
5929 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5931 static bool
5933 {
5934 /* Check operand constraints in case hard registers were propagated
5935 into insn pattern. This check prevents combine pass from
5936 generating insn patterns with invalid hard register operands.
5937 These invalid insns can eventually confuse reload to error out
5938 with a spill failure. See also PRs 46829 and 46843. */
5940 {
5949 {
5957 /* For pre-AVX disallow unaligned loads/stores where the
5958 instructions don't support it. */
5962 {
5966 }
5968 /* A unary operator may be accepted by the predicate, but it
5969 is irrelevant for matching constraints. */
5974 {
5982 }
5989 /* Operand has no constraints, anything is OK. */
5994 {
5999 && operands_match_p
6003 {
6006 }
6007 }
6011 }
6012 }
6015 }
6016 \f
6017 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6019 static unsigned HOST_WIDE_INT
6021 {
6025 }
6026 \f
6027 /* Argument support functions. */
6029 /* Return true when register may be used to pass function parameters. */
6030 bool
6032 {
6037 {
6041 else
6047 }
6053 /* TODO: The function should depend on current function ABI but
6054 builtins.c would need updating then. Therefore we use the
6055 default ABI. */
6057 /* RAX is used as hidden argument to va_arg functions. */
6063 else
6070 }
6072 /* Return if we do not know how to pass TYPE solely in registers. */
6074 static bool
6076 {
6080 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6081 The layout_type routine is crafty and tries to trick us into passing
6082 currently unsupported vector types on the stack by using TImode. */
6085 }
6087 /* It returns the size, in bytes, of the area reserved for arguments passed
6088 in registers for the function represented by fndecl dependent to the used
6089 abi format. */
6090 int
6092 {
6096 else
6101 }
6103 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6104 call abi used. */
6105 enum calling_abi
6107 {
6109 {
6112 {
6115 }
6119 }
6121 }
6123 /* We add this as a workaround in order to use libc_has_function
6124 hook in i386.md. */
6125 bool
6127 {
6129 }
6131 static bool
6133 {
6135 {
6139 else
6141 }
6143 }
6145 static enum calling_abi
6147 {
6151 }
6153 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6154 call abi used. */
6155 enum calling_abi
6157 {
6161 }
6163 /* Write the extra assembler code needed to declare a function properly. */
6165 void
6167 tree decl)
6168 {
6172 {
6178 }
6180 #ifdef SUBTARGET_ASM_UNWIND_INIT
6182 #endif
6186 /* Output magic byte marker, if hot-patch attribute is set. */
6188 {
6190 {
6191 /* leaq [%rsp + 0], %rsp */
6194 }
6195 else
6196 {
6197 /* movl.s %edi, %edi
6198 push %ebp
6199 movl.s %esp, %ebp */
6202 }
6203 }
6204 }
6206 /* regclass.c */
6209 /* Implementation of call abi switching target hook. Specific to FNDECL
6210 the specific call register sets are set. See also
6211 ix86_conditional_register_usage for more details. */
6212 void
6214 {
6217 else
6219 }
6221 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6222 expensive re-initialization of init_regs each time we switch function context
6223 since this is needed only during RTL expansion. */
6224 static void
6226 {
6230 }
6232 /* Return 1 if pseudo register should be created and used to hold
6233 GOT address for PIC code. */
6234 static bool
6236 {
6243 }
6245 /* Initialize large model PIC register. */
6247 static void
6249 {
6251 rtx tmp_reg;
6260 label));
6264 }
6266 /* Create and initialize PIC register if required. */
6267 static void
6269 {
6270 edge entry_edge;
6279 {
6282 else
6284 }
6285 else
6286 {
6287 /* If there is future mcount call in the function it is more profitable
6288 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6297 }
6305 }
6307 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6308 for a call to a function whose data type is FNTYPE.
6309 For a library call, FNTYPE is 0. */
6311 void
6315 tree fndecl,
6317 {
6323 {
6326 }
6327 else
6328 {
6331 }
6335 /* Set up the number of registers to use for passing arguments. */
6338 {
6340 ? X86_64_REGPARM_MAX
6342 }
6344 {
6347 {
6349 ? X86_64_SSE_REGPARM_MAX
6351 }
6352 }
6360 /* Because type might mismatch in between caller and callee, we need to
6361 use actual type of function for local calls.
6362 FIXME: cgraph_analyze can be told to actually record if function uses
6363 va_start so for local functions maybe_vaarg can be made aggressive
6364 helping K&R code.
6365 FIXME: once typesytem is fixed, we won't need this code anymore. */
6378 {
6379 /* If there are variable arguments, then we won't pass anything
6380 in registers in 32-bit mode. */
6382 {
6391 }
6393 /* Use ecx and edx registers if function has fastcall attribute,
6394 else look for regparm information. */
6396 {
6399 {
6402 }
6404 {
6407 }
6408 else
6410 }
6412 /* Set up the number of SSE registers used for passing SFmode
6413 and DFmode arguments. Warn for mismatching ABI. */
6415 }
6416 }
6418 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6419 But in the case of vector types, it is some vector mode.
6421 When we have only some of our vector isa extensions enabled, then there
6422 are some modes for which vector_mode_supported_p is false. For these
6423 modes, the generic vector support in gcc will choose some non-vector mode
6424 in order to implement the type. By computing the natural mode, we'll
6425 select the proper ABI location for the operand and not depend on whatever
6426 the middle-end decides to do with these vector types.
6428 The midde-end can't deal with the vector types > 16 bytes. In this
6429 case, we return the original mode and warn ABI change if CUM isn't
6430 NULL.
6432 If INT_RETURN is true, warn ABI change if the vector mode isn't
6433 available for function return value. */
6435 static machine_mode
6438 {
6442 {
6445 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6447 {
6452 else
6455 /* Get the mode which has this inner mode and number of units. */
6459 {
6461 {
6466 {
6470 }
6472 {
6476 }
6479 }
6481 {
6486 {
6490 }
6492 {
6496 }
6499 }
6502 {
6507 {
6511 }
6513 {
6517 }
6518 }
6520 {
6525 {
6529 }
6531 {
6535 }
6536 }
6538 }
6541 }
6542 }
6545 }
6547 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6548 this may not agree with the mode that the type system has chosen for the
6549 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6550 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6552 static rtx
6555 {
6556 rtx tmp;
6560 else
6561 {
6565 }
6568 }
6570 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6571 of this code is to classify each 8bytes of incoming argument by the register
6572 class and assign registers accordingly. */
6574 /* Return the union class of CLASS1 and CLASS2.
6575 See the x86-64 PS ABI for details. */
6577 static enum x86_64_reg_class
6579 {
6580 /* Rule #1: If both classes are equal, this is the resulting class. */
6584 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6585 the other class. */
6591 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6595 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6603 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6604 MEMORY is used. */
6613 /* Rule #6: Otherwise class SSE is used. */
6615 }
6617 /* Classify the argument of type TYPE and mode MODE.
6618 CLASSES will be filled by the register class used to pass each word
6619 of the operand. The number of words is returned. In case the parameter
6620 should be passed in memory, 0 is returned. As a special case for zero
6621 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6623 BIT_OFFSET is used internally for handling records and specifies offset
6624 of the offset in bits modulo 512 to avoid overflow cases.
6626 See the x86-64 PS ABI for details.
6627 */
6629 static int
6632 {
6633 HOST_WIDE_INT bytes =
6635 int words
6638 /* Variable sized entities are always passed/returned in memory. */
6647 {
6649 tree field;
6652 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6659 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6660 signalize memory class, so handle it as special case. */
6662 {
6665 }
6667 /* Classify each field of record and merge classes. */
6669 {
6671 /* And now merge the fields of structure. */
6673 {
6675 {
6681 /* Bitfields are always classified as integer. Handle them
6682 early, since later code would consider them to be
6683 misaligned integers. */
6685 {
6694 }
6695 else
6696 {
6701 /* Flexible array member is ignored. */
6708 {
6712 {
6715 "the ABI of passing struct with"
6716 " a flexible array member has"
6718 }
6720 }
6722 subclasses,
6732 }
6733 }
6734 }
6738 /* Arrays are handled as small records. */
6739 {
6746 /* The partial classes are now full classes. */
6757 }
6760 /* Unions are similar to RECORD_TYPE but offset is always 0.
6761 */
6763 {
6765 {
6773 bit_offset);
6778 }
6779 }
6784 }
6787 {
6788 /* When size > 16 bytes, if the first one isn't
6789 X86_64_SSE_CLASS or any other ones aren't
6790 X86_64_SSEUP_CLASS, everything should be passed in
6791 memory. */
6798 }
6800 /* Final merger cleanup. */
6802 {
6803 /* If one class is MEMORY, everything should be passed in
6804 memory. */
6808 /* The X86_64_SSEUP_CLASS should be always preceded by
6809 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6813 {
6814 /* The first one should never be X86_64_SSEUP_CLASS. */
6817 }
6819 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6820 everything should be passed in memory. */
6823 {
6826 /* The first one should never be X86_64_X87UP_CLASS. */
6829 {
6832 "the ABI of passing union with long double"
6834 }
6836 }
6837 }
6839 }
6841 /* Compute alignment needed. We align all types to natural boundaries with
6842 exception of XFmode that is aligned to 64bits. */
6844 {
6853 /* Misaligned fields are always returned in memory. */
6856 }
6858 /* for V1xx modes, just use the base mode */
6863 /* Classification of atomic types. */
6865 {
6881 {
6884 /* Analyze last 128 bits only. */
6888 {
6891 }
6893 {
6896 }
6898 {
6902 }
6904 {
6907 }
6908 else
6910 }
6917 /* OImode shouldn't be used directly. */
6924 else
6942 else
6943 {
6947 {
6950 "the ABI of passing structure with complex float"
6952 }
6955 }
6964 /* This modes is larger than 16 bytes. */
7022 else
7026 }
7027 }
7029 /* Examine the argument and return set number of register required in each
7030 class. Return true iff parameter should be passed in memory. */
7032 static bool
7035 {
7046 {
7067 }
7070 }
7072 /* Construct container for the argument used by GCC interface. See
7073 FUNCTION_ARG for the detailed description. */
7075 static rtx
7079 {
7080 /* The following variables hold the static issued_error state. */
7085 machine_mode tmpmode;
7094 rtx ret;
7105 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7106 some less clueful developer tries to use floating-point anyway. */
7108 {
7110 {
7112 {
7115 }
7116 }
7118 {
7121 }
7123 }
7125 /* Likewise, error if the ABI requires us to return values in the
7126 x87 registers and the user specified -mno-80387. */
7132 {
7134 {
7137 }
7139 }
7141 /* First construct simple cases. Avoid SCmode, since we want to use
7142 single register to pass this type. */
7145 {
7160 /* Zero sized array, struct or class. */
7164 }
7203 /* Otherwise figure out the entries of the PARALLEL. */
7205 {
7209 {
7214 /* Merge TImodes on aligned occasions here too. */
7216 tmpmode
7220 else
7222 /* We've requested 24 bytes we
7223 don't have mode for. Use DImode. */
7230 intreg++;
7238 sse_regno++;
7246 sse_regno++;
7251 {
7257 {
7259 i++;
7260 }
7261 else
7286 }
7292 sse_regno++;
7296 }
7297 }
7299 /* Empty aligned struct, union or class. */
7307 }
7309 /* Update the data in CUM to advance over an argument of mode MODE
7310 and data type TYPE. (TYPE is null for libcalls where that information
7311 may not be available.)
7313 Return a number of integer regsiters advanced over. */
7315 static int
7318 HOST_WIDE_INT words)
7319 {
7323 {
7330 /* FALLTHRU */
7342 {
7345 }
7349 /* OImode shouldn't be used directly. */
7358 /* FALLTHRU */
7380 {
7385 {
7388 }
7389 }
7399 {
7404 {
7407 }
7408 }
7410 }
7413 }
7415 static int
7418 {
7421 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7428 {
7434 }
7435 else
7436 {
7441 }
7442 }
7444 static int
7446 HOST_WIDE_INT words)
7447 {
7448 /* Otherwise, this should be passed indirect. */
7453 {
7457 }
7459 }
7461 /* Update the data in CUM to advance over an argument of mode MODE and
7462 data type TYPE. (TYPE is null for libcalls where that information
7463 may not be available.) */
7465 static void
7468 {
7475 else
7484 {
7485 /* If we pass bounds in BT then just update remained bounds count. */
7487 {
7490 }
7492 /* Update remained number of bounds to force. */
7499 }
7501 /* The first arg not going to Bounds Tables resets this counter. */
7503 /* For unnamed args we always pass bounds to avoid bounds mess when
7504 passed and received types do not match. If bounds do not follow
7505 unnamed arg, still pretend required number of bounds were passed. */
7507 {
7510 }
7516 else
7519 /* For stdarg we expect bounds to be passed for each value passed
7520 in register. */
7523 /* For pointers passed in memory we expect bounds passed in Bounds
7524 Table. */
7527 }
7529 /* Define where to put the arguments to a function.
7530 Value is zero to push the argument on the stack,
7531 or a hard register in which to store the argument.
7533 MODE is the argument's machine mode.
7534 TYPE is the data type of the argument (as a tree).
7535 This is null for libcalls where that information may
7536 not be available.
7537 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7538 the preceding args and about the function being called.
7539 NAMED is nonzero if this argument is a named parameter
7540 (otherwise it is an extra parameter matching an ellipsis). */
7542 static rtx
7546 {
7547 /* Avoid the AL settings for the Unix64 ABI. */
7552 {
7559 /* FALLTHRU */
7565 {
7568 /* Fastcall allocates the first two DWORD (SImode) or
7569 smaller arguments to ECX and EDX if it isn't an
7570 aggregate type . */
7572 {
7578 /* ECX not EAX is the first allocated register. */
7581 }
7583 }
7592 /* FALLTHRU */
7594 /* In 32bit, we pass TImode in xmm registers. */
7602 {
7606 }
7611 /* OImode and XImode shouldn't be used directly. */
7627 {
7631 }
7641 {
7645 }
7647 }
7650 }
7652 static rtx
7655 {
7656 /* Handle a hidden AL argument containing number of registers
7657 for varargs x86-64 functions. */
7661 ? X86_64_SSE_REGPARM_MAX
7666 {
7682 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7686 }
7692 }
7694 static rtx
7697 HOST_WIDE_INT bytes)
7698 {
7701 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7702 We use value of -2 to specify that current function call is MSABI. */
7706 /* If we've run out of registers, it goes on the stack. */
7712 /* Only floating point modes are passed in anything but integer regs. */
7714 {
7717 else
7718 {
7721 /* Unnamed floating parameters are passed in both the
7722 SSE and integer registers. */
7728 }
7729 }
7730 /* Handle aggregated types passed in register. */
7732 {
7737 }
7740 }
7742 /* Return where to put the arguments to a function.
7743 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7745 MODE is the argument's machine mode. TYPE is the data type of the
7746 argument. It is null for libcalls where that information may not be
7747 available. CUM gives information about the preceding args and about
7748 the function being called. NAMED is nonzero if this argument is a
7749 named parameter (otherwise it is an extra parameter matching an
7750 ellipsis). */
7752 static rtx
7755 {
7759 rtx arg;
7761 /* All pointer bounds argumntas are handled separately here. */
7764 {
7765 /* Return NULL if bounds are forced to go in Bounds Table. */
7768 /* Return the next available bound reg if any. */
7771 /* Return the next special slot number otherwise. */
7772 else
7776 }
7780 else
7784 /* To simplify the code below, represent vector types with a vector mode
7785 even if MMX/SSE are not active. */
7793 else
7797 }
7799 /* A C expression that indicates when an argument must be passed by
7800 reference. If nonzero for an argument, a copy of that argument is
7801 made in memory and a pointer to the argument is passed instead of
7802 the argument itself. The pointer is passed in whatever way is
7803 appropriate for passing a pointer to that type. */
7805 static bool
7808 {
7811 /* See Windows x64 Software Convention. */
7813 {
7816 {
7817 /* Arrays are passed by reference. */
7822 {
7823 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7824 are passed by reference. */
7826 }
7827 }
7829 /* __m128 is passed by reference. */
7835 }
7836 }
7841 }
7843 /* Return true when TYPE should be 128bit aligned for 32bit argument
7844 passing ABI. XXX: This function is obsolete and is only used for
7845 checking psABI compatibility with previous versions of GCC. */
7847 static bool
7849 {
7861 {
7862 /* Walk the aggregates recursively. */
7864 {
7868 {
7869 tree field;
7871 /* Walk all the structure fields. */
7873 {
7877 }
7879 }
7882 /* Just for use if some languages passes arrays by value. */
7889 }
7890 }
7892 }
7894 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7895 XXX: This function is obsolete and is only used for checking psABI
7896 compatibility with previous versions of GCC. */
7898 static unsigned int
7901 {
7902 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7903 natural boundaries. */
7905 {
7906 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7907 make an exception for SSE modes since these require 128bit
7908 alignment.
7910 The handling here differs from field_alignment. ICC aligns MMX
7911 arguments to 4 byte boundaries, while structure fields are aligned
7912 to 8 byte boundaries. */
7914 {
7917 }
7918 else
7919 {
7922 }
7923 }
7927 }
7929 /* Return true when TYPE should be 128bit aligned for 32bit argument
7930 passing ABI. */
7932 static bool
7934 {
7944 {
7945 /* Walk the aggregates recursively. */
7947 {
7951 {
7952 tree field;
7954 /* Walk all the structure fields. */
7956 field;
7958 {
7962 }
7964 }
7967 /* Just for use if some languages passes arrays by value. */
7974 }
7975 }
7976 else
7980 }
7982 /* Gives the alignment boundary, in bits, of an argument with the
7983 specified mode and type. */
7985 static unsigned int
7987 {
7990 {
7991 /* Since the main variant type is used for call, we convert it to
7992 the main variant type. */
7995 }
7996 else
8000 else
8001 {
8006 {
8007 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8009 {
8012 }
8018 }
8021 && !warned
8023 saved_align))
8024 {
8027 "The ABI for passing parameters with %d-byte"
8030 }
8031 }
8034 }
8036 /* Return true if N is a possible register number of function value. */
8038 static bool
8040 {
8042 {
8054 /* Complex values are returned in %st(0)/%st(1) pair. */
8057 /* TODO: The function should depend on current function ABI but
8058 builtins.c would need updating then. Therefore we use the
8059 default ABI. */
8064 /* Complex values are returned in %xmm0/%xmm1 pair. */
8073 }
8076 }
8078 /* Define how to find the value returned by a function.
8079 VALTYPE is the data type of the value (as a tree).
8080 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8081 otherwise, FUNC is 0. */
8083 static rtx
8086 {
8089 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8090 we normally prevent this case when mmx is not available. However
8091 some ABIs may require the result to be returned like DImode. */
8095 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8096 we prevent this case when sse is not available. However some ABIs
8097 may require the result to be returned like integer TImode. */
8102 /* 32-byte vector modes in %ymm0. */
8106 /* 64-byte vector modes in %zmm0. */
8110 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8113 else
8114 /* Most things go in %eax. */
8117 /* Override FP return register with %xmm0 for local functions when
8118 SSE math is enabled or for functions with sseregparm attribute. */
8120 {
8125 }
8127 /* OImode shouldn't be used directly. */
8131 }
8133 static rtx
8135 const_tree valtype)
8136 {
8137 rtx ret;
8139 /* Handle libcalls, which don't provide a type node. */
8141 {
8145 {
8164 }
8167 }
8169 {
8170 /* Pointers are always returned in word_mode. */
8172 }
8178 /* For zero sized structures, construct_container returns NULL, but we
8179 need to keep rest of compiler happy by returning meaningful value. */
8184 }
8186 static rtx
8188 const_tree valtype)
8189 {
8193 {
8195 {
8214 }
8215 }
8217 }
8219 static rtx
8222 {
8237 else
8239 }
8241 static rtx
8243 {
8249 }
8251 /* Return an RTX representing a place where a function returns
8252 or recieves pointer bounds or NULL if no bounds are returned.
8254 VALTYPE is a data type of a value returned by the function.
8256 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8257 or FUNCTION_TYPE of the function.
8259 If OUTGOING is false, return a place in which the caller will
8260 see the return value. Otherwise, return a place where a
8261 function returns a value. */
8263 static rtx
8265 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8267 {
8273 {
8274 bitmap slots;
8276 bitmap_iterator bi;
8284 {
8289 }
8295 }
8296 else
8300 }
8302 /* Pointer function arguments and return values are promoted to
8303 word_mode. */
8305 static machine_mode
8309 {
8311 {
8314 }
8316 for_return);
8317 }
8319 /* Return true if a structure, union or array with MODE containing FIELD
8320 should be accessed using BLKmode. */
8322 static bool
8324 {
8325 /* Union with XFmode must be in BLKmode. */
8329 }
8331 rtx
8333 {
8335 }
8337 /* Return true iff type is returned in memory. */
8339 static bool
8341 {
8342 #ifdef SUBTARGET_RETURN_IN_MEMORY
8344 #else
8346 HOST_WIDE_INT size;
8352 {
8354 {
8357 /* __m128 is returned in xmm0. */
8366 /* Otherwise, the size must be exactly in [1248]. */
8368 }
8369 else
8370 {
8375 }
8376 }
8377 else
8378 {
8388 {
8389 /* User-created vectors small enough to fit in EAX. */
8393 /* Unless ABI prescibes otherwise,
8394 MMX/3dNow values are returned in MM0 if available. */
8399 /* SSE values are returned in XMM0 if available. */
8403 /* AVX values are returned in YMM0 if available. */
8407 /* AVX512F values are returned in ZMM0 if available. */
8410 }
8418 /* OImode shouldn't be used directly. */
8422 }
8423 #endif
8424 }
8426 \f
8427 /* Create the va_list data type. */
8429 /* Returns the calling convention specific va_list date type.
8430 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8432 static tree
8434 {
8437 /* For i386 we use plain pointer to argument area. */
8447 unsigned_type_node);
8450 unsigned_type_node);
8453 ptr_type_node);
8456 ptr_type_node);
8475 /* The correct type is an array type of one element. */
8477 }
8479 /* Setup the builtin va_list data type and for 64-bit the additional
8480 calling convention specific va_list data types. */
8482 static tree
8484 {
8487 /* Initialize abi specific va_list builtin types. */
8489 {
8490 tree t;
8492 {
8497 }
8498 else
8499 {
8504 }
8506 {
8511 }
8512 else
8513 {
8518 }
8519 }
8522 }
8524 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8526 static void
8528 {
8530 alias_set_type set;
8533 /* GPR size of varargs save area. */
8536 else
8539 /* FPR size of varargs save area. We don't need it if we don't pass
8540 anything in SSE registers. */
8543 else
8557 {
8565 }
8568 {
8569 machine_mode smode;
8571 rtx test;
8573 /* Now emit code to save SSE registers. The AX parameter contains number
8574 of SSE parameter registers used to call this function, though all we
8575 actually check here is the zero/non-zero status. */
8580 label));
8582 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8583 we used movdqa (i.e. TImode) instead? Perhaps even better would
8584 be if we could determine the real mode of the data, via a hook
8585 into pass_stdarg. Ignore all that for now. */
8595 {
8604 }
8607 }
8608 }
8610 static void
8612 {
8616 /* Reset to zero, as there might be a sysv vaarg used
8617 before. */
8622 {
8633 }
8634 }
8636 static void
8639 {
8641 CUMULATIVE_ARGS next_cum;
8642 tree fntype;
8644 /* This argument doesn't appear to be used anymore. Which is good,
8645 because the old code here didn't suppress rtl generation. */
8653 /* For varargs, we do not want to skip the dummy va_dcl argument.
8654 For stdargs, we do want to skip the last named argument. */
8662 else
8664 }
8666 static void
8669 tree type,
8672 {
8674 CUMULATIVE_ARGS next_cum;
8675 tree fntype;
8676 rtx save_area;
8681 /* Do nothing if we use plain pointer to argument area. */
8687 /* For varargs, we do not want to skip the dummy va_dcl argument.
8688 For stdargs, we do want to skip the last named argument. */
8702 {
8707 rtx bounds;
8711 else
8712 {
8713 rtx ldx_addr =
8720 }
8726 bnd_reg++;
8727 }
8728 }
8731 /* Checks if TYPE is of kind va_list char *. */
8733 static bool
8735 {
8736 tree canonic;
8738 /* For 32-bit it is always true. */
8744 }
8746 /* Implement va_start. */
8748 static void
8750 {
8754 tree type;
8755 rtx ovf_rtx;
8759 {
8762 /* When we are splitting the stack, we can't refer to the stack
8763 arguments using internal_arg_pointer, because they may be on
8764 the old stack. The split stack prologue will arrange to
8765 leave a pointer to the old stack arguments in a scratch
8766 register, which we here copy to a pseudo-register. The split
8767 stack prologue can't set the pseudo-register directly because
8768 it (the prologue) runs before any registers have been saved. */
8772 {
8773 rtx reg;
8787 }
8788 }
8790 /* Only 64bit target needs something special. */
8792 {
8795 else
8796 {
8806 /* Store zero bounds for va_list. */
8810 next));
8812 }
8814 }
8823 /* The following should be folded into the MEM_REF offset. */
8833 /* Count number of gp and fp argument registers used. */
8839 {
8845 }
8848 {
8854 }
8856 /* Find the overflow area. */
8860 else
8866 /* Store zero bounds for overflow area pointer. */
8875 {
8876 /* Find the register save area.
8877 Prologue of the function save it right above stack frame. */
8883 /* Store zero bounds for save area pointer. */
8890 }
8891 }
8893 /* Implement va_arg. */
8895 static tree
8898 {
8905 rtx container;
8907 tree ptrtype;
8908 machine_mode nat_mode;
8911 /* Only 64bit target needs something special. */
8935 {
8948 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8950 {
8953 }
8961 }
8963 /* Pull the value out of the saved registers. */
8968 {
8982 /* In case we are passing structure, verify that it is consecutive block
8983 on the register save area. If not we need to do moves. */
8985 {
8986 /* Verify that all registers are strictly consecutive */
8988 {
8992 {
8997 }
8998 }
8999 else
9000 {
9004 {
9009 }
9010 }
9011 }
9013 {
9016 }
9017 else
9018 {
9021 }
9023 /* First ensure that we fit completely in registers. */
9025 {
9032 }
9034 {
9042 }
9044 /* Compute index to start of area used for integer regs. */
9046 {
9047 /* int_addr = gpr + sav; */
9050 }
9052 {
9053 /* sse_addr = fpr + sav; */
9056 }
9058 {
9062 /* addr = &temp; */
9067 {
9071 tree piece_type;
9072 tree addr_type;
9073 tree daddr_type;
9082 {
9087 }
9091 else
9098 {
9101 }
9102 else
9103 {
9106 }
9113 {
9118 }
9119 else
9120 {
9121 tree copy
9126 }
9128 }
9129 }
9132 {
9136 }
9139 {
9143 }
9148 }
9150 /* ... otherwise out of the overflow area. */
9152 /* When we align parameter on stack for caller, if the parameter
9153 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9154 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9155 here with caller. */
9160 /* Care for on-stack alignment if needed. */
9163 else
9164 {
9169 }
9186 }
9187 \f
9188 /* Return true if OPNUM's MEM should be matched
9189 in movabs* patterns. */
9191 bool
9193 {
9205 }
9206 \f
9207 /* Initialize the table of extra 80387 mathematical constants. */
9209 static void
9211 {
9213 {
9219 };
9223 {
9225 /* Ensure each constant is rounded to XFmode precision. */
9228 }
9231 }
9233 /* Return non-zero if the constant is something that
9234 can be loaded with a special instruction. */
9236 int
9238 {
9241 REAL_VALUE_TYPE r;
9253 /* For XFmode constants, try to find a special 80387 instruction when
9254 optimizing for size or on those CPUs that benefit from them. */
9257 {
9266 }
9268 /* Load of the constant -0.0 or -1.0 will be split as
9269 fldz;fchs or fld1;fchs sequence. */
9276 }
9278 /* Return the opcode of the special instruction to be used to load
9279 the constant X. */
9283 {
9285 {
9305 }
9306 }
9308 /* Return the CONST_DOUBLE representing the 80387 constant that is
9309 loaded by the specified special instruction. The argument IDX
9310 matches the return value from standard_80387_constant_p. */
9312 rtx
9314 {
9321 {
9332 }
9335 XFmode);
9336 }
9338 /* Return 1 if X is all 0s and 2 if x is all 1s
9339 in supported SSE/AVX vector mode. */
9341 int
9343 {
9350 {
9371 }
9374 }
9376 /* Return the opcode of the special instruction to be used to load
9377 the constant X. */
9381 {
9383 {
9386 {
9413 }
9423 else
9428 }
9430 }
9432 /* Returns true if OP contains a symbol reference */
9434 bool
9436 {
9445 {
9447 {
9453 }
9457 }
9460 }
9462 /* Return true if it is appropriate to emit `ret' instructions in the
9463 body of a function. Do this only if the epilogue is simple, needing a
9464 couple of insns. Prior to reloading, we can't tell how many registers
9465 must be saved, so return false then. Return false if there is no frame
9466 marker to de-allocate. */
9468 bool
9470 {
9476 /* Don't allow more than 32k pop, since that's all we can do
9477 with one instruction. */
9484 }
9485 \f
9486 /* Value should be nonzero if functions must have frame pointers.
9487 Zero means the frame pointer need not be set up (and parms may
9488 be accessed via the stack pointer) in functions that seem suitable. */
9490 static bool
9492 {
9493 /* If we accessed previous frames, then the generated code expects
9494 to be able to access the saved ebp value in our frame. */
9498 /* Several x86 os'es need a frame pointer for other reasons,
9499 usually pertaining to setjmp. */
9503 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9507 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9508 allocation is 4GB. */
9512 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9513 turns off the frame pointer by default. Turn it back on now if
9514 we've not got a leaf function. */
9524 }
9526 /* Record that the current function accesses previous call frames. */
9528 void
9530 {
9532 }
9533 \f
9534 #ifndef USE_HIDDEN_LINKONCE
9535 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9536 # define USE_HIDDEN_LINKONCE 1
9537 # else
9538 # define USE_HIDDEN_LINKONCE 0
9539 # endif
9540 #endif
9544 /* Fills in the label name that should be used for a pc thunk for
9545 the given register. */
9547 static void
9549 {
9554 else
9556 }
9559 /* This function generates code for -fpic that loads %ebx with
9560 the return address of the caller and then returns. */
9562 static void
9564 {
9569 {
9571 tree decl;
9587 #if TARGET_MACHO
9589 {
9598 }
9599 else
9600 #endif
9602 {
9613 }
9614 else
9615 {
9618 }
9624 /* Make sure unwind info is emitted for the thunk if needed. */
9627 /* Pad stack IP move with 4 instructions (two NOPs count
9628 as one instruction). */
9630 {
9635 }
9646 }
9650 }
9652 /* Emit code for the SET_GOT patterns. */
9656 {
9662 {
9663 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9668 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9669 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9670 an unadorned address. */
9675 }
9680 {
9682 /* We don't need a pic base, we're not producing pic. */
9689 }
9690 else
9691 {
9700 #if TARGET_MACHO
9701 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9702 This is what will be referenced by the Mach-O PIC subsystem. */
9706 /* When we are restoring the pic base at the site of a nonlocal label,
9707 and we decided to emit the pic base above, we will still output a
9708 local label used for calculating the correction offset (even though
9709 the offset will be 0 in that case). */
9713 #endif
9714 }
9720 }
9722 /* Generate an "push" pattern for input ARG. */
9724 static rtx
9726 {
9739 stack_pointer_rtx)),
9740 arg);
9741 }
9743 /* Generate an "pop" pattern for input ARG. */
9745 static rtx
9747 {
9752 arg,
9755 stack_pointer_rtx)));
9756 }
9758 /* Return >= 0 if there is an unused call-clobbered register available
9759 for the entire function. */
9761 static unsigned int
9763 {
9770 {
9772 /* Can't use the same register for both PIC and DRAP. */
9775 else
9780 }
9783 }
9785 /* Return TRUE if we need to save REGNO. */
9787 static bool
9789 {
9792 {
9794 {
9795 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9796 _mcount in prologue. */
9799 }
9806 }
9809 {
9812 {
9818 }
9819 }
9830 }
9832 /* Return number of saved general prupose registers. */
9834 static int
9836 {
9842 nregs ++;
9844 }
9846 /* Return number of saved SSE registrers. */
9848 static int
9850 {
9858 nregs ++;
9860 }
9862 /* Given FROM and TO register numbers, say whether this elimination is
9863 allowed. If stack alignment is needed, we can only replace argument
9864 pointer with hard frame pointer, or replace frame pointer with stack
9865 pointer. Otherwise, frame pointer elimination is automatically
9866 handled and all other eliminations are valid. */
9868 static bool
9870 {
9876 else
9878 }
9880 /* Return the offset between two registers, one to be eliminated, and the other
9881 its replacement, at the start of a routine. */
9883 HOST_WIDE_INT
9885 {
9894 else
9895 {
9903 }
9904 }
9906 /* In a dynamically-aligned function, we can't know the offset from
9907 stack pointer to frame pointer, so we must ensure that setjmp
9908 eliminates fp against the hard fp (%ebp) rather than trying to
9909 index from %esp up to the top of the frame across a gap that is
9910 of unknown (at compile-time) size. */
9911 static rtx
9913 {
9915 }
9917 /* When using -fsplit-stack, the allocation routines set a field in
9918 the TCB to the bottom of the stack plus this much space, measured
9919 in bytes. */
9921 #define SPLIT_STACK_AVAILABLE 256
9923 /* Fill structure ix86_frame about frame of currently computed function. */
9925 static void
9927 {
9929 HOST_WIDE_INT offset;
9932 HOST_WIDE_INT to_allocate;
9937 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9938 function prologues and leaf. */
9942 {
9945 }
9946 /* preferred_stack_boundary is never updated for call
9947 expanded from tls descriptor. Update it here. We don't update it in
9948 expand stage because according to the comments before
9949 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9950 away. */
9953 {
9957 }
9966 /* For SEH we have to limit the amount of code movement into the prologue.
9967 At present we do this via a BLOCKAGE, at which point there's very little
9968 scheduling that can be done, which means that there's very little point
9969 in doing anything except PUSHs. */
9973 /* During reload iteration the amount of registers saved can change.
9974 Recompute the value as needed. Do not recompute when amount of registers
9975 didn't change as reload does multiple calls to the function and does not
9976 expect the decision to change within single iteration. */
9979 {
9985 /* The fast prologue uses move instead of push to save registers. This
9986 is significantly longer, but also executes faster as modern hardware
9987 can execute the moves in parallel, but can't do that for push/pop.
9989 Be careful about choosing what prologue to emit: When function takes
9990 many instructions to execute we may use slow version as well as in
9991 case function is known to be outside hot spot (this is known with
9992 feedback only). Weight the size of function by number of registers
9993 to save as it is cheap to use one or two push instructions but very
9994 slow to use many of them. */
9998 || (flag_branch_probabilities
10001 else
10004 }
10006 frame->save_regs_using_mov
10008 /* If static stack checking is enabled and done with probes,
10009 the registers need to be saved before allocating the frame. */
10012 /* Skip return address. */
10015 /* Skip pushed static chain. */
10019 /* Skip saved base pointer. */
10024 /* The traditional frame pointer location is at the top of the frame. */
10027 /* Register save area */
10031 /* On SEH target, registers are pushed just before the frame pointer
10032 location. */
10036 /* Align and set SSE register save area. */
10038 {
10039 /* The only ABI that has saved SSE registers (Win64) also has a
10040 16-byte aligned default stack, and thus we don't need to be
10041 within the re-aligned local stack frame to save them. */
10045 }
10048 /* The re-aligned stack starts here. Values before this point are not
10049 directly comparable with values below this point. In order to make
10050 sure that no value happens to be the same before and after, force
10051 the alignment computation below to add a non-zero value. */
10055 /* Va-arg area */
10059 /* Align start of frame for local function. */
10068 /* Frame pointer points here. */
10073 /* Add outgoing arguments area. Can be skipped if we eliminated
10074 all the function calls as dead code.
10075 Skipping is however impossible when function calls alloca. Alloca
10076 expander assumes that last crtl->outgoing_args_size
10077 of stack frame are unused. */
10081 {
10084 }
10085 else
10088 /* Align stack boundary. Only needed if we're calling another function
10089 or using alloca. */
10094 /* We've reached end of stack frame. */
10097 /* Size prologue needs to allocate. */
10108 {
10114 }
10115 else
10119 /* The SEH frame pointer location is near the bottom of the frame.
10120 This is enforced by the fact that the difference between the
10121 stack pointer and the frame pointer is limited to 240 bytes in
10122 the unwind data structure. */
10124 {
10125 HOST_WIDE_INT diff;
10127 /* If we can leave the frame pointer where it is, do so. Also, returns
10128 the establisher frame for __builtin_frame_address (0). */
10133 {
10134 /* Ideally we'd determine what portion of the local stack frame
10135 (within the constraint of the lowest 240) is most heavily used.
10136 But without that complication, simply bias the frame pointer
10137 by 128 bytes so as to maximize the amount of the local stack
10138 frame that is addressable with 8-bit offsets. */
10140 }
10141 }
10142 }
10144 /* This is semi-inlined memory_address_length, but simplified
10145 since we know that we're always dealing with reg+offset, and
10146 to avoid having to create and discard all that rtl. */
10150 {
10154 {
10155 /* EBP and R13 cannot be encoded without an offset. */
10157 }
10161 /* ESP and R12 must be encoded with a SIB byte. */
10163 len++;
10166 }
10168 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10169 The valid base registers are taken from CFUN->MACHINE->FS. */
10171 static rtx
10173 {
10179 {
10180 /* Choose the base register most likely to allow the most scheduling
10181 opportunities. Generally FP is valid throughout the function,
10182 while DRAP must be reloaded within the epilogue. But choose either
10183 over the SP due to increased encoding size. */
10186 {
10189 }
10191 {
10194 }
10196 {
10199 }
10200 }
10201 else
10202 {
10203 HOST_WIDE_INT toffset;
10206 /* Choose the base register with the smallest address encoding.
10207 With a tie, choose FP > DRAP > SP. */
10209 {
10213 }
10215 {
10219 {
10223 }
10224 }
10226 {
10230 {
10234 }
10235 }
10236 }
10240 }
10242 /* Emit code to save registers in the prologue. */
10244 static void
10246 {
10248 rtx insn;
10252 {
10255 }
10256 }
10258 /* Emit a single register save at CFA - CFA_OFFSET. */
10260 static void
10262 HOST_WIDE_INT cfa_offset)
10263 {
10271 /* For SSE saves, we need to indicate the 128-bit alignment. */
10282 /* When saving registers into a re-aligned local stack frame, avoid
10283 any tricky guessing by dwarf2out. */
10285 {
10289 {
10290 /* A bit of a hack. We force the DRAP register to be saved in
10291 the re-aligned stack frame, which provides us with a copy
10292 of the CFA that will last past the prologue. Install it. */
10298 }
10299 else
10300 {
10301 /* The frame pointer is a stable reference within the
10302 aligned frame. Use it. */
10309 }
10310 }
10312 /* The memory may not be relative to the current CFA register,
10313 which means that we may need to generate a new pattern for
10314 use by the unwind info. */
10316 {
10321 }
10322 }
10324 /* Emit code to save registers using MOV insns.
10325 First register is stored at CFA - CFA_OFFSET. */
10326 static void
10328 {
10333 {
10336 }
10337 }
10339 /* Emit code to save SSE registers using MOV insns.
10340 First register is stored at CFA - CFA_OFFSET. */
10341 static void
10343 {
10348 {
10351 }
10352 }
10356 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10357 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10358 Don't add the note if the previously saved value will be left untouched
10359 within stack red-zone till return, as unwinders can find the same value
10360 in the register and on the stack. */
10362 static void
10364 {
10370 {
10373 }
10374 else
10375 queued_cfa_restores
10377 }
10379 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10381 static void
10383 {
10384 rtx last;
10388 ;
10393 }
10395 /* Expand prologue or epilogue stack adjustment.
10396 The pattern exist to put a dependency on all ebp-based memory accesses.
10397 STYLE should be negative if instructions should be marked as frame related,
10398 zero if %r11 register is live and cannot be freely used and positive
10399 otherwise. */
10401 static void
10404 {
10406 rtx insn;
10413 else
10414 {
10415 rtx tmp;
10416 /* r11 is used by indirect sibcall return as well, set before the
10417 epilogue and used after the epilogue. */
10420 else
10421 {
10425 }
10431 }
10438 {
10439 rtx r;
10449 }
10451 {
10454 {
10458 }
10459 }
10462 {
10467 {
10470 }
10472 {
10475 }
10476 else
10477 {
10478 /* Else there are two possibilities: SP itself, which we set
10479 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10480 taken care of this by hand along the eh_return path. */
10483 }
10487 }
10488 }
10490 /* Find an available register to be used as dynamic realign argument
10491 pointer regsiter. Such a register will be written in prologue and
10492 used in begin of body, so it must not be
10493 1. parameter passing register.
10494 2. GOT pointer.
10495 We reuse static-chain register if it is available. Otherwise, we
10496 use DI for i386 and R13 for x86-64. We chose R13 since it has
10497 shorter encoding.
10499 Return: the regno of chosen register. */
10501 static unsigned int
10503 {
10507 {
10508 /* Use R13 for nested function or function need static chain.
10509 Since function with tail call may use any caller-saved
10510 registers in epilogue, DRAP must not use caller-saved
10511 register in such case. */
10516 }
10517 else
10518 {
10519 /* Use DI for nested function or function need static chain.
10520 Since function with tail call may use any caller-saved
10521 registers in epilogue, DRAP must not use caller-saved
10522 register in such case. */
10526 /* Reuse static chain register if it isn't used for parameter
10527 passing. */
10529 {
10533 }
10535 }
10536 }
10538 /* Return minimum incoming stack alignment. */
10540 static unsigned int
10542 {
10545 /* Prefer the one specified at command line. */
10548 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10549 if -mstackrealign is used, it isn't used for sibcall check and
10550 estimated stack alignment is 128bit. */
10552 && !TARGET_64BIT
10553 && ix86_force_align_arg_pointer
10556 else
10559 /* Incoming stack alignment can be changed on individual functions
10560 via force_align_arg_pointer attribute. We use the smallest
10561 incoming stack boundary. */
10567 /* The incoming stack frame has to be aligned at least at
10568 parm_stack_boundary. */
10572 /* Stack at entrance of main is aligned by runtime. We use the
10573 smallest incoming stack boundary. */
10581 }
10583 /* Update incoming stack boundary and estimated stack alignment. */
10585 static void
10587 {
10588 ix86_incoming_stack_boundary
10591 /* x86_64 vararg needs 16byte stack alignment for register save
10592 area. */
10597 }
10599 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10600 needed or an rtx for DRAP otherwise. */
10602 static rtx
10604 {
10609 {
10610 /* Assign DRAP to vDRAP and returns vDRAP */
10612 rtx drap_vreg;
10613 rtx arg_ptr;
10626 {
10629 }
10631 }
10632 else
10634 }
10636 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10638 static rtx
10640 {
10642 }
10645 rtx reg;
10647 };
10649 /* Return a short-lived scratch register for use on function entry.
10650 In 32-bit mode, it is valid only after the registers are saved
10651 in the prologue. This register must be released by means of
10652 release_scratch_register_on_entry once it is dead. */
10654 static void
10656 {
10662 {
10663 /* We always use R11 in 64-bit mode. */
10665 }
10666 else
10667 {
10669 bool fastcall_p
10671 bool thiscall_p
10675 int drap_regno
10678 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10679 for the static chain register. */
10683 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10684 for the static chain register. */
10689 /* ecx is the static chain register. */
10691 && !static_chain_p
10696 /* esi is the static chain register. */
10702 else
10703 {
10706 }
10707 }
10711 {
10714 }
10715 }
10717 /* Release a scratch register obtained from the preceding function. */
10719 static void
10721 {
10723 {
10727 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10733 }
10734 }
10736 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10738 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10740 static void
10742 {
10743 /* We skip the probe for the first interval + a small dope of 4 words and
10744 probe that many bytes past the specified size to maintain a protection
10745 area at the botton of the stack. */
10749 /* See if we have a constant small number of probes to generate. If so,
10750 that's the easy case. The run-time loop is made up of 11 insns in the
10751 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10752 for n # of intervals. */
10754 {
10758 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10759 values of N from 1 until it exceeds SIZE. If only one probe is
10760 needed, this will not generate any code. Then adjust and probe
10761 to PROBE_INTERVAL + SIZE. */
10763 {
10765 {
10768 }
10769 else
10776 }
10780 else
10788 /* Adjust back to account for the additional first interval. */
10792 }
10794 /* Otherwise, do the same as above, but in a loop. Note that we must be
10795 extra careful with variables wrapping around because we might be at
10796 the very top (or the very bottom) of the address space and we have
10797 to be able to handle this case properly; in particular, we use an
10798 equality test for the loop condition. */
10799 else
10800 {
10801 HOST_WIDE_INT rounded_size;
10807 /* Step 1: round SIZE to the previous multiple of the interval. */
10812 /* Step 2: compute initial and final value of the loop counter. */
10814 /* SP = SP_0 + PROBE_INTERVAL. */
10819 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10823 stack_pointer_rtx)));
10826 /* Step 3: the loop
10828 while (SP != LAST_ADDR)
10829 {
10830 SP = SP + PROBE_INTERVAL
10831 probe at SP
10832 }
10834 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10835 values of N from 1 until it is equal to ROUNDED_SIZE. */
10840 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10841 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10844 {
10849 }
10851 /* Adjust back to account for the additional first interval. */
10857 }
10861 /* Even if the stack pointer isn't the CFA register, we need to correctly
10862 describe the adjustments made to it, in particular differentiate the
10863 frame-related ones from the frame-unrelated ones. */
10865 {
10878 }
10880 /* Make sure nothing is scheduled before we are done. */
10882 }
10884 /* Adjust the stack pointer up to REG while probing it. */
10888 {
10898 /* Jump to END_LAB if SP == LAST_ADDR. */
10906 /* SP = SP + PROBE_INTERVAL. */
10910 /* Probe at SP. */
10921 }
10923 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10924 inclusive. These are offsets from the current stack pointer. */
10926 static void
10928 {
10929 /* See if we have a constant small number of probes to generate. If so,
10930 that's the easy case. The run-time loop is made up of 7 insns in the
10931 generic case while the compile-time loop is made up of n insns for n #
10932 of intervals. */
10934 {
10935 HOST_WIDE_INT i;
10937 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10938 it exceeds SIZE. If only one probe is needed, this will not
10939 generate any code. Then probe at FIRST + SIZE. */
10946 }
10948 /* Otherwise, do the same as above, but in a loop. Note that we must be
10949 extra careful with variables wrapping around because we might be at
10950 the very top (or the very bottom) of the address space and we have
10951 to be able to handle this case properly; in particular, we use an
10952 equality test for the loop condition. */
10953 else
10954 {
10961 /* Step 1: round SIZE to the previous multiple of the interval. */
10966 /* Step 2: compute initial and final value of the loop counter. */
10968 /* TEST_OFFSET = FIRST. */
10971 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10975 /* Step 3: the loop
10977 while (TEST_ADDR != LAST_ADDR)
10978 {
10979 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10980 probe at TEST_ADDR
10981 }
10983 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10984 until it is equal to ROUNDED_SIZE. */
10989 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10990 that SIZE is equal to ROUNDED_SIZE. */
10995 stack_pointer_rtx,
11000 }
11002 /* Make sure nothing is scheduled before we are done. */
11004 }
11006 /* Probe a range of stack addresses from REG to END, inclusive. These are
11007 offsets from the current stack pointer. */
11011 {
11021 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11029 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11033 /* Probe at TEST_ADDR. */
11046 }
11048 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11049 to be generated in correct form. */
11050 static void
11052 {
11053 /* Check if stack realign is really needed after reload, and
11054 stores result in cfun */
11055 unsigned int incoming_stack_boundary
11064 {
11065 /* After stack_realign_needed is finalized, we can't no longer
11066 change it. */
11069 }
11071 /* If the only reason for frame_pointer_needed is that we conservatively
11072 assumed stack realignment might be needed, but in the end nothing that
11073 needed the stack alignment had been spilled, clear frame_pointer_needed
11074 and say we don't need stack realignment. */
11076 && frame_pointer_needed
11078 && flag_omit_frame_pointer
11080 && !ix86_current_function_calls_tls_descriptor
11089 {
11091 basic_block bb;
11098 HARD_FRAME_POINTER_REGNUM);
11100 {
11105 set_up_by_prologue))
11106 {
11110 }
11111 }
11113 /* If drap has been set, but it actually isn't live at the start
11114 of the function, there is no reason to set it up. */
11116 {
11119 {
11122 }
11123 }
11124 else
11139 }
11143 }
11145 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11147 static void
11149 {
11155 {
11158 {
11164 }
11165 }
11166 }
11168 /* Expand the prologue into a bunch of separate insns. */
11170 void
11172 {
11176 HOST_WIDE_INT allocate;
11182 /* DRAP should not coexist with stack_realign_fp */
11187 /* Initialize CFA state for before the prologue. */
11191 /* Track SP offset to the CFA. We continue tracking this after we've
11192 swapped the CFA register away from SP. In the case of re-alignment
11193 this is fudged; we're interested to offsets within the local frame. */
11200 {
11201 /* We should have already generated an error for any use of
11202 ms_hook on a nested function. */
11205 /* Check if profiling is active and we shall use profiling before
11206 prologue variant. If so sorry. */
11211 /* In ix86_asm_output_function_label we emitted:
11212 8b ff movl.s %edi,%edi
11213 55 push %ebp
11214 8b ec movl.s %esp,%ebp
11216 This matches the hookable function prologue in Win32 API
11217 functions in Microsoft Windows XP Service Pack 2 and newer.
11218 Wine uses this to enable Windows apps to hook the Win32 API
11219 functions provided by Wine.
11221 What that means is that we've already set up the frame pointer. */
11225 {
11228 /* We've decided to use the frame pointer already set up.
11229 Describe this to the unwinder by pretending that both
11230 push and mov insns happen right here.
11232 Putting the unwind info here at the end of the ms_hook
11233 is done so that we can make absolutely certain we get
11234 the required byte sequence at the start of the function,
11235 rather than relying on an assembler that can produce
11236 the exact encoding required.
11238 However it does mean (in the unpatched case) that we have
11239 a 1 insn window where the asynchronous unwind info is
11240 incorrect. However, if we placed the unwind info at
11241 its correct location we would have incorrect unwind info
11242 in the patched case. Which is probably all moot since
11243 I don't expect Wine generates dwarf2 unwind info for the
11244 system libraries that use this feature. */
11250 stack_pointer_rtx);
11258 /* Note that gen_push incremented m->fs.cfa_offset, even
11259 though we didn't emit the push insn here. */
11263 }
11264 else
11265 {
11266 /* The frame pointer is not needed so pop %ebp again.
11267 This leaves us with a pristine state. */
11269 }
11270 }
11272 /* The first insn of a function that accepts its static chain on the
11273 stack is to push the register that would be filled in by a direct
11274 call. This insn will be skipped by the trampoline. */
11276 {
11280 /* We don't want to interpret this push insn as a register save,
11281 only as a stack adjustment. The real copy of the register as
11282 a save will be done later, if needed. */
11287 }
11289 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11290 of DRAP is needed and stack realignment is really needed after reload */
11292 {
11295 /* Only need to push parameter pointer reg if it is caller saved. */
11297 {
11298 /* Push arg pointer reg */
11301 }
11303 /* Grab the argument pointer. */
11310 /* Align the stack. */
11312 stack_pointer_rtx,
11316 /* Replicate the return address on the stack so that return
11317 address can be reached via (argp - 1) slot. This is needed
11318 to implement macro RETURN_ADDR_RTX and intrinsic function
11319 expand_builtin_return_addr etc. */
11325 /* For the purposes of frame and register save area addressing,
11326 we've started over with a new frame. */
11329 }
11335 {
11336 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11337 slower on all targets. Also sdb doesn't like it. */
11341 /* Push registers now, before setting the frame pointer
11342 on SEH target. */
11344 && TARGET_SEH
11346 {
11350 }
11353 {
11361 }
11362 }
11365 {
11366 /* If saving registers via PUSH, do so now. */
11368 {
11372 }
11374 /* When using red zone we may start register saving before allocating
11375 the stack frame saving one cycle of the prologue. However, avoid
11376 doing this if we have to probe the stack; at least on x86_64 the
11377 stack probe can turn into a call that clobbers a red zone location. */
11379 && (! TARGET_STACK_PROBE
11381 {
11384 }
11385 }
11388 {
11392 /* The computation of the size of the re-aligned stack frame means
11393 that we must allocate the size of the register save area before
11394 performing the actual alignment. Otherwise we cannot guarantee
11395 that there's enough storage above the realignment point. */
11402 /* Align the stack. */
11404 stack_pointer_rtx,
11407 /* For the purposes of register save area addressing, the stack
11408 pointer is no longer valid. As for the value of sp_offset,
11409 see ix86_compute_frame_layout, which we need to match in order
11410 to pass verification of stack_pointer_offset at the end. */
11413 }
11418 {
11419 /* We start to count from ARG_POINTER. */
11422 /* If it was realigned, take into account the fake frame. */
11424 {
11431 /* This over-estimates by 1 minimal-stack-alignment-unit but
11432 mitigates that by counting in the new return address slot. */
11433 current_function_dynamic_stack_size
11435 }
11438 }
11440 /* On SEH target with very large frame size, allocate an area to save
11441 SSE registers (as the very large allocation won't be described). */
11445 {
11446 HOST_WIDE_INT sse_size =
11451 /* No need to do stack checking as the area will be immediately
11452 written. */
11459 }
11461 /* The stack has already been decremented by the instruction calling us
11462 so probe if the size is non-negative to preserve the protection area. */
11464 {
11465 /* We expect the registers to be saved when probes are used. */
11469 {
11472 {
11475 }
11476 }
11477 else
11478 {
11485 {
11487 {
11490 }
11491 else
11493 }
11494 else
11495 {
11497 {
11501 }
11502 else
11504 }
11505 }
11506 }
11509 ;
11512 {
11516 }
11517 else
11518 {
11530 {
11533 /* Note that SEH directives need to continue tracking the stack
11534 pointer even after the frame pointer has been set up. */
11536 {
11540 }
11541 }
11544 {
11549 {
11553 }
11554 }
11559 /* Use the fact that AX still contains ALLOCATE. */
11561 ? gen_pro_epilogue_adjust_stack_di_sub
11568 {
11576 }
11579 /* Use stack_pointer_rtx for relative addressing so that code
11580 works for realigned stack, too. */
11582 {
11589 }
11591 {
11596 }
11597 }
11600 /* If we havn't already set up the frame pointer, do so now. */
11602 {
11614 }
11621 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11622 in PROLOGUE. */
11624 {
11630 /* Deleting already emmitted SET_GOT if exist and allocated to
11631 REAL_PIC_OFFSET_TABLE_REGNUM. */
11633 }
11636 {
11637 /* vDRAP is setup but after reload it turns out stack realign
11638 isn't necessary, here we will emit prologue to setup DRAP
11639 without stack realign adjustment */
11642 }
11644 /* Prevent instructions from being scheduled into register save push
11645 sequence when access to the redzone area is done through frame pointer.
11646 The offset between the frame pointer and the stack pointer is calculated
11647 relative to the value of the stack pointer at the end of the function
11648 prologue, and moving instructions that access redzone area via frame
11649 pointer inside push sequence violates this assumption. */
11653 /* Emit cld instruction if stringops are used in the function. */
11657 /* SEH requires that the prologue end within 256 bytes of the start of
11658 the function. Prevent instruction schedules that would extend that.
11659 Further, prevent alloca modifications to the stack pointer from being
11660 combined with prologue modifications. */
11663 }
11665 /* Emit code to restore REG using a POP insn. */
11667 static void
11669 {
11678 {
11679 /* Previously we'd represented the CFA as an expression
11680 like *(%ebp - 8). We've just popped that value from
11681 the stack, which means we need to reset the CFA to
11682 the drap register. This will remain until we restore
11683 the stack pointer. */
11687 /* This means that the DRAP register is valid for addressing too. */
11690 }
11693 {
11700 }
11702 /* When the frame pointer is the CFA, and we pop it, we are
11703 swapping back to the stack pointer as the CFA. This happens
11704 for stack frames that don't allocate other data, so we assume
11705 the stack pointer is now pointing at the return address, i.e.
11706 the function entry state, which makes the offset be 1 word. */
11708 {
11711 {
11719 }
11720 }
11721 }
11723 /* Emit code to restore saved registers using POP insns. */
11725 static void
11727 {
11733 }
11735 /* Emit code and notes for the LEAVE instruction. */
11737 static void
11739 {
11751 {
11759 }
11762 }
11764 /* Emit code to restore saved registers using MOV insns.
11765 First register is restored from CFA - CFA_OFFSET. */
11766 static void
11769 {
11775 {
11784 {
11785 /* Previously we'd represented the CFA as an expression
11786 like *(%ebp - 8). We've just popped that value from
11787 the stack, which means we need to reset the CFA to
11788 the drap register. This will remain until we restore
11789 the stack pointer. */
11793 /* This means that the DRAP register is valid for addressing. */
11795 }
11796 else
11800 }
11801 }
11803 /* Emit code to restore saved registers using MOV insns.
11804 First register is restored from CFA - CFA_OFFSET. */
11805 static void
11808 {
11813 {
11815 rtx mem;
11825 }
11826 }
11828 /* Restore function stack, frame, and registers. */
11830 void
11832 {
11848 /* The FP must be valid if the frame pointer is present. */
11853 /* We must have *some* valid pointer to the stack frame. */
11856 /* The DRAP is never valid at this point. */
11859 /* See the comment about red zone and frame
11860 pointer usage in ix86_expand_prologue. */
11867 /* Determine the CFA offset of the end of the red-zone. */
11870 {
11871 /* The red-zone begins below the return address. */
11874 /* When the register save area is in the aligned portion of
11875 the stack, determine the maximum runtime displacement that
11876 matches up with the aligned frame. */
11880 }
11882 /* Special care must be taken for the normal return case of a function
11883 using eh_return: the eax and edx registers are marked as saved, but
11884 not restored along this path. Adjust the save location to match. */
11888 /* EH_RETURN requires the use of moves to function properly. */
11891 /* SEH requires the use of pops to identify the epilogue. */
11894 /* If we're only restoring one register and sp is not valid then
11895 using a move instruction to restore the register since it's
11896 less work than reloading sp and popping the register. */
11909 && TARGET_USE_LEAVE
11913 else
11917 {
11918 /* Ensure that the entire register save area is addressable via
11919 the stack pointer, if we will restore via sp. */
11924 {
11928 style,
11930 }
11931 }
11933 /* If there are any SSE registers to restore, then we have to do it
11934 via moves, since there's obviously no pop for SSE regs. */
11940 {
11941 rtx t;
11946 /* eh_return epilogues need %ecx added to the stack pointer. */
11948 {
11951 /* Stack align doesn't work with eh_return. */
11953 /* Neither does regparm nested functions. */
11957 {
11965 /* Note that we use SA as a temporary CFA, as the return
11966 address is at the proper place relative to it. We
11967 pretend this happens at the FP restore insn because
11968 prior to this insn the FP would be stored at the wrong
11969 offset relative to SA, and after this insn we have no
11970 other reasonable register to use for the CFA. We don't
11971 bother resetting the CFA to the SP for the duration of
11972 the return insn. */
11985 }
11986 else
11987 {
11995 {
11999 UNITS_PER_WORD));
12001 }
12002 }
12005 }
12006 }
12007 else
12008 {
12009 /* SEH requires that the function end with (1) a stack adjustment
12010 if necessary, (2) a sequence of pops, and (3) a return or
12011 jump instruction. Prevent insns from the function body from
12012 being scheduled into this sequence. */
12014 {
12015 /* Prevent a catch region from being adjacent to the standard
12016 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12017 several other flags that would be interesting to test are
12018 not yet set up. */
12021 else
12023 }
12025 /* First step is to deallocate the stack frame so that we can
12026 pop the registers. Also do it on SEH target for very large
12027 frame as the emitted instructions aren't allowed by the ABI in
12028 epilogues. */
12030 || (TARGET_SEH
12033 {
12038 }
12040 {
12044 style,
12046 }
12049 }
12051 /* If we used a stack pointer and haven't already got rid of it,
12052 then do so now. */
12054 {
12055 /* If the stack pointer is valid and pointing at the frame
12056 pointer store address, then we only need a pop. */
12059 /* Leave results in shorter dependency chains on CPUs that are
12060 able to grok it fast. */
12065 else
12066 {
12068 hard_frame_pointer_rtx,
12071 }
12072 }
12075 {
12077 rtx insn;
12103 }
12105 /* At this point the stack pointer must be valid, and we must have
12106 restored all of the registers. We may not have deallocated the
12107 entire stack frame. We've delayed this until now because it may
12108 be possible to merge the local stack deallocation with the
12109 deallocation forced by ix86_static_chain_on_stack. */
12114 {
12118 }
12119 else
12122 /* Sibcall epilogues don't want a return instruction. */
12124 {
12127 }
12130 {
12133 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12134 address, do explicit add, and jump indirectly to the caller. */
12137 {
12139 rtx insn;
12141 /* There is no "pascal" calling convention in any 64bit ABI. */
12158 }
12159 else
12161 }
12162 else
12165 /* Restore the state back to the state from the prologue,
12166 so that it's correct for the next epilogue. */
12168 }
12170 /* Reset from the function's potential modifications. */
12172 static void
12174 {
12178 #if TARGET_MACHO
12179 /* Mach-O doesn't support labels at the end of objects, so if
12180 it looks like we might want one, insert a NOP. */
12181 {
12187 {
12188 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12189 notes only, instead set their CODE_LABEL_NUMBER to -1,
12190 otherwise there would be code generation differences
12191 in between -g and -g0. */
12195 }
12205 }
12206 #endif
12208 }
12210 /* Return a scratch register to use in the split stack prologue. The
12211 split stack prologue is used for -fsplit-stack. It is the first
12212 instructions in the function, even before the regular prologue.
12213 The scratch register can be any caller-saved register which is not
12214 used for parameters or for the static chain. */
12216 static unsigned int
12218 {
12221 else
12222 {
12235 {
12237 {
12241 }
12243 }
12245 {
12249 }
12251 {
12254 else
12255 {
12257 {
12261 }
12263 }
12264 }
12265 else
12266 {
12267 /* FIXME: We could make this work by pushing a register
12268 around the addition and comparison. */
12271 }
12272 }
12273 }
12275 /* A SYMBOL_REF for the function which allocates new stackspace for
12276 -fsplit-stack. */
12280 /* A SYMBOL_REF for the more stack function when using the large
12281 model. */
12285 /* Handle -fsplit-stack. These are the first instructions in the
12286 function, even before the regular prologue. */
12288 void
12290 {
12292 HOST_WIDE_INT allocate;
12298 rtx fn;
12306 /* This is the label we will branch to if we have enough stack
12307 space. We expect the basic block reordering pass to reverse this
12308 branch if optimizing, so that we branch in the unlikely case. */
12311 /* We need to compare the stack pointer minus the frame size with
12312 the stack boundary in the TCB. The stack boundary always gives
12313 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12314 can compare directly. Otherwise we need to do an addition. */
12317 UNSPEC_STACK_CHECK);
12322 else
12323 {
12325 rtx offset;
12327 /* We need a scratch register to hold the stack pointer minus
12328 the required frame size. Since this is the very start of the
12329 function, the scratch register can be any caller-saved
12330 register which is not used for parameters. */
12337 {
12338 /* We don't use ix86_gen_add3 in this case because it will
12339 want to split to lea, but when not optimizing the insn
12340 will not be split after this point. */
12343 offset)));
12344 }
12345 else
12346 {
12349 stack_pointer_rtx));
12350 }
12352 }
12358 /* Mark the jump as very likely to be taken. */
12363 {
12366 }
12369 /* Get more stack space. We pass in the desired stack space and the
12370 size of the arguments to copy to the new stack. In 32-bit mode
12371 we push the parameters; __morestack will return on a new stack
12372 anyhow. In 64-bit mode we pass the parameters in r10 and
12373 r11. */
12378 {
12384 /* If this function uses a static chain, it will be in %r10.
12385 Preserve it across the call to __morestack. */
12387 {
12388 rtx rax;
12393 }
12397 {
12398 HOST_WIDE_INT argval;
12401 /* When using the large model we need to load the address
12402 into a register, and we've run out of registers. So we
12403 switch to a different calling convention, and we call a
12404 different function: __morestack_large. We pass the
12405 argument size in the upper 32 bits of r10 and pass the
12406 frame size in the lower 32 bits. */
12411 {
12412 split_stack_fn_large =
12415 }
12417 {
12419 rtx x;
12428 UNSPEC_GOT);
12434 }
12435 else
12442 }
12443 else
12444 {
12448 }
12451 }
12452 else
12453 {
12456 }
12462 /* In order to make call/return prediction work right, we now need
12463 to execute a return instruction. See
12464 libgcc/config/i386/morestack.S for the details on how this works.
12466 For flow purposes gcc must not see this as a return
12467 instruction--we need control flow to continue at the subsequent
12468 label. Therefore, we use an unspec. */
12472 /* If we are in 64-bit mode and this function uses a static chain,
12473 we saved %r10 in %rax before calling _morestack. */
12478 /* If this function calls va_start, we need to store a pointer to
12479 the arguments on the old stack, because they may not have been
12480 all copied to the new stack. At this point the old stack can be
12481 found at the frame pointer value used by __morestack, because
12482 __morestack has set that up before calling back to us. Here we
12483 store that pointer in a scratch register, and in
12484 ix86_expand_prologue we store the scratch register in a stack
12485 slot. */
12487 {
12489 rtx frame_reg;
12496 /* 64-bit:
12497 fp -> old fp value
12498 return address within this function
12499 return address of caller of this function
12500 stack arguments
12501 So we add three words to get to the stack arguments.
12503 32-bit:
12504 fp -> old fp value
12505 return address within this function
12506 first argument to __morestack
12507 second argument to __morestack
12508 return address of caller of this function
12509 stack arguments
12510 So we add five words to get to the stack arguments.
12511 */
12522 }
12527 /* If this function calls va_start, we now have to set the scratch
12528 register for the case where we do not call __morestack. In this
12529 case we need to set it based on the stack pointer. */
12531 {
12538 }
12539 }
12541 /* We may have to tell the dataflow pass that the split stack prologue
12542 is initializing a scratch register. */
12544 static void
12546 {
12548 {
12551 }
12552 }
12553 \f
12554 /* Extract the parts of an RTL expression that is a valid memory address
12555 for an instruction. Return 0 if the structure of the address is
12556 grossly off. Return -1 if the address contains ASHIFT, so it is not
12557 strictly valid, but still used for computing length of lea instruction. */
12559 int
12561 {
12566 rtx tmp;
12570 /* Allow zero-extended SImode addresses,
12571 they will be emitted with addr32 prefix. */
12573 {
12576 {
12580 }
12583 {
12590 }
12591 }
12593 /* Allow SImode subregs of DImode addresses,
12594 they will be emitted with addr32 prefix. */
12596 {
12599 {
12603 }
12604 }
12609 {
12612 else
12614 }
12616 {
12621 do
12622 {
12627 }
12634 {
12637 {
12662 /* FALLTHRU */
12666 && TARGET_TLS_DIRECT_SEG_REFS
12669 else
12676 /* FALLTHRU */
12683 else
12698 }
12699 }
12700 }
12702 {
12705 }
12707 {
12708 /* We're called for lea too, which implements ashift on occasion. */
12718 }
12719 else
12723 {
12725 ;
12728 ;
12729 else
12731 }
12733 /* Extract the integral value of scale. */
12735 {
12739 }
12744 /* Avoid useless 0 displacement. */
12748 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12753 {
12756 }
12758 /* Special case: %ebp cannot be encoded as a base without a displacement.
12759 Similarly %r13. */
12761 && base_reg
12770 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12771 Avoid this by transforming to [%esi+0].
12772 Reload calls address legitimization without cfun defined, so we need
12773 to test cfun for being non-NULL. */
12779 /* Special case: encode reg+reg instead of reg*2. */
12783 /* Special case: scaling cannot be encoded without base or displacement. */
12794 }
12795 \f
12796 /* Return cost of the memory address x.
12797 For i386, it is better to use a complex address than let gcc copy
12798 the address into a reg and make a new pseudo. But not if the address
12799 requires to two regs - that would mean more pseudos with longer
12800 lifetimes. */
12801 static int
12803 {
12815 /* Attempt to minimize number of registers in the address. */
12821 cost++;
12823 /* When address base or index is "pic_offset_table_rtx" we don't increase
12824 address cost. When a memopt with "pic_offset_table_rtx" is not invariant
12825 itself it most likely means that base or index is not invariant.
12826 Therefore only "pic_offset_table_rtx" could be hoisted out, which is not
12827 profitable for x86. */
12829 && (!pic_offset_table_rtx
12833 && (!pic_offset_table_rtx
12837 cost++;
12839 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12840 since it's predecode logic can't detect the length of instructions
12841 and it degenerates to vector decoded. Increase cost of such
12842 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12843 to split such addresses or even refuse such addresses at all.
12845 Following addressing modes are affected:
12846 [base+scale*index]
12847 [scale*index+disp]
12848 [base+index]
12850 The first and last case may be avoidable by explicitly coding the zero in
12851 memory address, but I don't have AMD-K6 machine handy to check this
12852 theory. */
12861 }
12862 \f
12863 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12864 this is used for to form addresses to local data when -fPIC is in
12865 use. */
12867 static bool
12869 {
12872 }
12874 /* Determine if a given RTX is a valid constant. We already know this
12875 satisfies CONSTANT_P. */
12877 static bool
12879 {
12880 /* Pointer bounds constants are not valid. */
12885 {
12890 {
12894 }
12899 /* Only some unspecs are valid as "constants". */
12902 {
12918 }
12920 /* We must have drilled down to a symbol. */
12925 /* FALLTHRU */
12928 /* TLS symbols are never valid. */
12932 /* DLLIMPORT symbols are never valid. */
12937 #if TARGET_MACHO
12938 /* mdynamic-no-pic */
12941 #endif
12957 }
12959 /* Otherwise we handle everything else in the move patterns. */
12961 }
12963 /* Determine if it's legal to put X into the constant pool. This
12964 is not possible for the address of thread-local symbols, which
12965 is checked above. */
12967 static bool
12969 {
12970 /* We can always put integral constants and vectors in memory. */
12972 {
12980 }
12982 }
12984 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12985 otherwise zero. */
12987 static bool
12989 {
12995 }
12998 /* Nonzero if the constant value X is a legitimate general operand
12999 when generating PIC code. It is given that flag_pic is on and
13000 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
13002 bool
13004 {
13005 rtx inner;
13008 {
13015 /* Only some unspecs are valid as "constants". */
13018 {
13031 }
13032 /* FALLTHRU */
13040 }
13041 }
13043 /* Determine if a given CONST RTX is a valid memory displacement
13044 in PIC mode. */
13046 bool
13048 {
13051 /* In 64bit mode we can allow direct addresses of symbols and labels
13052 when they are not dynamic symbols. */
13054 {
13058 {
13082 /* FALLTHRU */
13085 /* TLS references should always be enclosed in UNSPEC.
13086 The dllimported symbol needs always to be resolved. */
13092 {
13100 /* Function-symbols need to be resolved only for
13101 large-model.
13102 For the small-model we don't need to resolve anything
13103 here. */
13108 /* Non-external symbols don't need to be resolved for
13109 large, and medium-model. */
13114 }
13123 }
13124 }
13130 {
13131 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13132 of GOT tables. We should not need these anyway. */
13144 }
13148 {
13153 }
13162 {
13166 /* We need to check for both symbols and labels because VxWorks loads
13167 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13168 details. */
13172 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13173 While ABI specify also 32bit relocation but we don't produce it in
13174 small PIC model at all. */
13196 }
13199 }
13201 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13202 replace the input X, or the original X if no replacement is called for.
13203 The output parameter *WIN is 1 if the calling macro should goto WIN,
13204 0 if it should not. */
13206 bool
13209 {
13210 /* Reload can generate:
13212 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13213 (reg:DI 97))
13214 (reg:DI 2 cx))
13216 This RTX is rejected from ix86_legitimate_address_p due to
13217 non-strictness of base register 97. Following this rejection,
13218 reload pushes all three components into separate registers,
13219 creating invalid memory address RTX.
13221 Following code reloads only the invalid part of the
13222 memory address RTX. */
13228 {
13234 {
13239 }
13243 {
13248 }
13252 }
13255 }
13257 /* Determine if op is suitable RTX for an address register.
13258 Return naked register if a register or a register subreg is
13259 found, otherwise return NULL_RTX. */
13261 static rtx
13263 {
13266 /* Only SImode or DImode registers can form the address. */
13273 {
13281 /* Don't allow SUBREGs that span more than a word. It can
13282 lead to spill failures when the register is one word out
13283 of a two word structure. */
13287 /* Allow only SUBREGs of non-eliminable hard registers. */
13290 }
13292 /* Op is not a register. */
13294 }
13296 /* Recognizes RTL expressions that are valid memory addresses for an
13297 instruction. The MODE argument is the machine mode for the MEM
13298 expression that wants to use this address.
13300 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13301 convert common non-canonical forms to canonical form so that they will
13302 be recognized. */
13304 static bool
13306 {
13309 HOST_WIDE_INT scale;
13313 /* Decomposition failed. */
13322 /* Validate base register. */
13324 {
13332 /* Base is not valid. */
13334 }
13336 /* Validate index register. */
13338 {
13346 /* Index is not valid. */
13348 }
13350 /* Index and base should have the same mode. */
13355 /* Address override works only on the (%reg) part of %fs:(%reg). */
13361 /* Validate scale factor. */
13363 {
13365 /* Scale without index. */
13369 /* Scale is not a valid multiplier. */
13371 }
13373 /* Validate displacement. */
13375 {
13380 {
13381 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13382 used. While ABI specify also 32bit relocations, we don't produce
13383 them at all and use IP relative instead. */
13390 /* 64bit address unspec. */
13410 /* Invalid address unspec. */
13412 }
13415 && (flag_pic
13416 || (TARGET_MACHO
13417 #if TARGET_MACHO
13418 && MACHOPIC_INDIRECT
13420 #endif
13421 )))
13422 {
13424 is_legitimate_pic:
13426 {
13427 /* foo@dtpoff(%rX) is ok. */
13434 /* Non-constant pic memory reference. */
13436 }
13439 /* Displacement is an invalid pic construct. */
13441 #if TARGET_MACHO
13444 /* displacment must be referenced via non_lazy_pointer */
13446 #endif
13448 /* This code used to verify that a symbolic pic displacement
13449 includes the pic_offset_table_rtx register.
13451 While this is good idea, unfortunately these constructs may
13452 be created by "adds using lea" optimization for incorrect
13453 code like:
13455 int a;
13456 int foo(int i)
13457 {
13458 return *(&a+i);
13459 }
13461 This code is nonsensical, but results in addressing
13462 GOT table with pic_offset_table_rtx base. We can't
13463 just refuse it easily, since it gets matched by
13464 "addsi3" pattern, that later gets split to lea in the
13465 case output register differs from input. While this
13466 can be handled by separate addsi pattern for this case
13467 that never results in lea, this seems to be easier and
13468 correct fix for crash to disable this test. */
13469 }
13476 /* Displacement is not constant. */
13480 /* Displacement is out of range. */
13482 /* In x32 mode, constant addresses are sign extended to 64bit, so
13483 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13488 }
13490 /* Everything looks valid. */
13492 }
13494 /* Determine if a given RTX is a valid constant address. */
13496 bool
13498 {
13500 }
13501 \f
13502 /* Return a unique alias set for the GOT. */
13504 static alias_set_type
13506 {
13511 }
13513 /* Set regs_ever_live for PIC base address register
13514 to true if required. */
13515 static void
13517 {
13520 }
13522 /* Return a legitimate reference for ORIG (an address) using the
13523 register REG. If REG is 0, a new pseudo is generated.
13525 There are two types of references that must be handled:
13527 1. Global data references must load the address from the GOT, via
13528 the PIC reg. An insn is emitted to do this load, and the reg is
13529 returned.
13531 2. Static data references, constant pool addresses, and code labels
13532 compute the address as an offset from the GOT, whose base is in
13533 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13534 differentiate them from global data objects. The returned
13535 address is the PIC reg + an unspec constant.
13537 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13538 reg also appears in the address. */
13540 static rtx
13542 {
13546 #if TARGET_MACHO
13548 {
13551 /* Use the generic Mach-O PIC machinery. */
13553 }
13554 #endif
13557 {
13561 }
13567 {
13568 rtx tmpreg;
13569 /* This symbol may be referenced via a displacement from the PIC
13570 base address (@GOTOFF). */
13576 {
13578 UNSPEC_GOTOFF);
13580 }
13581 else
13586 else
13591 {
13595 }
13596 else
13598 }
13600 {
13601 /* This symbol may be referenced via a displacement from the PIC
13602 base address (@GOTOFF). */
13608 {
13610 UNSPEC_GOTOFF);
13612 }
13613 else
13619 {
13622 }
13623 }
13625 /* We can't use @GOTOFF for text labels on VxWorks;
13626 see gotoff_operand. */
13628 {
13633 /* For x64 PE-COFF there is no GOT table. So we use address
13634 directly. */
13636 {
13644 }
13646 {
13654 /* Use directly gen_movsi, otherwise the address is loaded
13655 into register for CSE. We don't want to CSE this addresses,
13656 instead we CSE addresses from the GOT table, so skip this. */
13659 }
13660 else
13661 {
13662 /* This symbol must be referenced via a load from the
13663 Global Offset Table (@GOT). */
13678 }
13679 }
13680 else
13681 {
13684 {
13686 {
13689 }
13690 else
13692 }
13694 {
13697 /* We must match stuff we generate before. Assume the only
13698 unspecs that can get here are ours. Not that we could do
13699 anything with them anyway.... */
13705 }
13707 {
13710 /* Check first to see if this is a constant offset from a @GOTOFF
13711 symbol reference. */
13714 {
13716 {
13719 UNSPEC_GOTOFF);
13725 {
13728 }
13729 }
13730 else
13731 {
13734 {
13738 }
13739 }
13740 }
13741 else
13742 {
13745 new_rtx
13749 {
13752 {
13755 new_rtx
13757 }
13758 else
13760 }
13761 else
13762 {
13765 {
13768 }
13770 }
13771 }
13772 }
13773 }
13775 }
13776 \f
13777 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13779 static rtx
13781 {
13785 {
13790 }
13796 }
13798 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13802 static rtx
13804 {
13806 {
13812 }
13815 {
13817 UNSPEC_PLTOFF);
13820 }
13823 }
13825 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13829 rtx
13831 {
13833 {
13834 ix86_tls_module_base_symbol
13839 }
13842 }
13844 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13845 false if we expect this to be used for a memory address and true if
13846 we expect to load the address into a register. */
13848 static rtx
13850 {
13856 /* Fall back to global dynamic model if tool chain cannot support local
13857 dynamic. */
13864 {
13869 {
13872 else
13873 {
13876 }
13877 }
13880 {
13883 else
13893 }
13894 else
13895 {
13899 {
13904 emit_call_insn
13914 }
13915 else
13917 }
13924 {
13927 else
13928 {
13931 }
13932 }
13935 {
13940 else
13946 }
13947 else
13948 {
13952 {
13955 rtx eqv;
13958 emit_call_insn
13963 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13964 share the LD_BASE result with other LD model accesses. */
13966 UNSPEC_TLS_LD_BASE);
13970 }
13971 else
13973 }
13981 {
13988 }
13993 {
13995 {
13996 /* The Sun linker took the AMD64 TLS spec literally
13997 and can only handle %rax as destination of the
13998 initial executable code sequence. */
14003 }
14005 /* Generate DImode references to avoid %fs:(%reg32)
14006 problems and linker IE->LE relaxation bug. */
14010 }
14012 {
14016 }
14018 {
14022 }
14023 else
14024 {
14027 }
14037 {
14042 }
14043 else
14044 {
14048 }
14058 {
14062 }
14063 else
14064 {
14068 }
14073 }
14076 }
14078 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14079 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14080 unique refptr-DECL symbol corresponding to symbol DECL. */
14083 {
14087 {
14089 }
14091 static void
14093 {
14099 else
14101 }
14102 };
14106 static tree
14108 {
14114 tree to;
14115 rtx rtl;
14142 else
14155 {
14157 #ifdef SUB_TARGET_RECORD_STUB
14159 #endif
14160 }
14169 }
14171 /* Expand SYMBOL into its corresponding far-addresse symbol.
14172 WANT_REG is true if we require the result be a register. */
14174 static rtx
14176 {
14177 tree imp_decl;
14178 rtx x;
14187 }
14189 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14190 true if we require the result be a register. */
14192 static rtx
14194 {
14195 tree imp_decl;
14196 rtx x;
14205 }
14207 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14208 is true if we require the result be a register. */
14210 static rtx
14212 {
14217 {
14224 {
14227 }
14228 }
14244 {
14247 }
14249 }
14251 /* Try machine-dependent ways of modifying an illegitimate address
14252 to be legitimate. If we find one, return the new, valid address.
14253 This macro is used in only one place: `memory_address' in explow.c.
14255 OLDX is the address as it was before break_out_memory_refs was called.
14256 In some cases it is useful to look at this to decide what needs to be done.
14258 It is always safe for this macro to do nothing. It exists to recognize
14259 opportunities to optimize the output.
14261 For the 80386, we handle X+REG by loading X into a register R and
14262 using R+REG. R will go in a general reg and indexing will be used.
14263 However, if REG is a broken-out memory address or multiplication,
14264 nothing needs to be done because REG can certainly go in a general reg.
14266 When -fpic is used, special handling is needed for symbolic references.
14267 See comments by legitimize_pic_address in i386.c for details. */
14269 static rtx
14271 {
14282 {
14286 }
14289 {
14293 }
14298 #if TARGET_MACHO
14301 #endif
14303 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14307 {
14312 }
14315 {
14316 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14321 {
14327 }
14332 {
14338 }
14340 /* Put multiply first if it isn't already. */
14342 {
14347 }
14349 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14350 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14351 created by virtual register instantiation, register elimination, and
14352 similar optimizations. */
14354 {
14360 }
14362 /* Canonicalize
14363 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14364 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14369 {
14370 rtx constant;
14374 {
14377 }
14379 {
14382 }
14383 else
14387 {
14394 }
14395 }
14401 {
14404 }
14407 {
14410 }
14418 {
14421 }
14427 {
14431 {
14434 }
14438 }
14441 {
14445 {
14448 }
14452 }
14453 }
14456 }
14457 \f
14458 /* Print an integer constant expression in assembler syntax. Addition
14459 and subtraction are the only arithmetic that may appear in these
14460 expressions. FILE is the stdio stream to write to, X is the rtx, and
14461 CODE is the operand print code from the output string. */
14463 static void
14465 {
14469 {
14478 else
14479 {
14482 /* Mark the decl as referenced so that cgraph will
14483 output the function. */
14487 #if TARGET_MACHO
14491 #endif
14493 }
14501 /* FALLTHRU */
14512 /* This used to output parentheses around the expression,
14513 but that does not work on the 386 (either ATT or BSD assembler). */
14519 {
14520 /* We can use %d if the number is <32 bits and positive. */
14525 else
14527 }
14528 else
14529 /* We can't handle floating point constants;
14530 TARGET_PRINT_OPERAND must handle them. */
14535 /* Some assemblers need integer constants to appear first. */
14537 {
14541 }
14542 else
14543 {
14548 }
14563 {
14567 }
14572 {
14591 /* FIXME: This might be @TPOFF in Sun ld too. */
14600 else
14610 else
14616 #if TARGET_MACHO
14621 #endif
14625 }
14630 }
14631 }
14633 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14634 We need to emit DTP-relative relocations. */
14636 static void ATTRIBUTE_UNUSED
14638 {
14643 {
14651 }
14652 }
14654 /* Return true if X is a representation of the PIC register. This copes
14655 with calls from ix86_find_base_term, where the register might have
14656 been replaced by a cselib value. */
14658 static bool
14660 {
14667 {
14675 }
14676 else
14678 }
14680 /* Helper function for ix86_delegitimize_address.
14681 Attempt to delegitimize TLS local-exec accesses. */
14683 static rtx
14685 {
14710 {
14715 }
14721 }
14723 /* In the name of slightly smaller debug output, and to cater to
14724 general assembler lossage, recognize PIC+GOTOFF and turn it back
14725 into a direct symbol reference.
14727 On Darwin, this is necessary to avoid a crash, because Darwin
14728 has a different PIC label for each routine but the DWARF debugging
14729 information is not associated with any particular routine, so it's
14730 necessary to remove references to the PIC label from RTL stored by
14731 the DWARF output code. */
14733 static rtx
14735 {
14737 /* addend is NULL or some rtx if x is something+GOTOFF where
14738 something doesn't include the PIC register. */
14740 /* reg_addend is NULL or a multiple of some register. */
14742 /* const_addend is NULL or a const_int. */
14744 /* This is the result, or NULL. */
14753 {
14760 {
14766 }
14773 {
14776 {
14781 }
14783 }
14788 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14789 and -mcmodel=medium -fpic. */
14790 }
14797 /* %ebx + GOT/GOTOFF */
14798 ;
14800 {
14801 /* %ebx + %reg * scale + GOT/GOTOFF */
14807 else
14808 {
14811 }
14812 }
14813 else
14819 {
14822 }
14843 {
14844 /* If the rest of original X doesn't involve the PIC register, add
14845 addend and subtract pic_offset_table_rtx. This can happen e.g.
14846 for code like:
14847 leal (%ebx, %ecx, 4), %ecx
14848 ...
14849 movl foo@GOTOFF(%ecx), %edx
14850 in which case we return (%ecx - %ebx) + foo
14851 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14852 and reload has completed. */
14856 pic_offset_table_rtx),
14857 result);
14859 {
14863 }
14864 else
14866 }
14868 {
14872 }
14874 }
14876 /* If X is a machine specific address (i.e. a symbol or label being
14877 referenced as a displacement from the GOT implemented using an
14878 UNSPEC), then return the base term. Otherwise return X. */
14880 rtx
14882 {
14883 rtx term;
14886 {
14900 }
14903 }
14904 \f
14905 static void
14908 {
14912 {
14915 }
14920 {
14923 {
14942 }
14946 {
14965 }
14972 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14973 Those same assemblers have the same but opposite lossage on cmov. */
14976 else
14981 {
14994 }
15001 else
15006 {
15019 }
15026 else
15036 else
15047 }
15049 }
15051 /* Print the name of register X to FILE based on its machine mode and number.
15052 If CODE is 'w', pretend the mode is HImode.
15053 If CODE is 'b', pretend the mode is QImode.
15054 If CODE is 'k', pretend the mode is SImode.
15055 If CODE is 'q', pretend the mode is DImode.
15056 If CODE is 'x', pretend the mode is V4SFmode.
15057 If CODE is 't', pretend the mode is V8SFmode.
15058 If CODE is 'g', pretend the mode is V16SFmode.
15059 If CODE is 'h', pretend the reg is the 'high' byte register.
15060 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15061 If CODE is 'd', duplicate the operand for AVX instruction.
15062 */
15064 void
15066 {
15075 {
15079 }
15106 else
15109 /* Irritatingly, AMD extended registers use different naming convention
15110 from the normal registers: "r%d[bwd]" */
15112 {
15117 {
15131 /* no suffix */
15136 }
15138 }
15142 {
15145 {
15148 }
15149 /* FALLTHRU */
15155 /* FALLTHRU */
15158 normal:
15173 {
15178 }
15181 {
15186 }
15190 }
15194 {
15197 else
15199 }
15200 }
15202 /* Meaning of CODE:
15203 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15204 C -- print opcode suffix for set/cmov insn.
15205 c -- like C, but print reversed condition
15206 F,f -- likewise, but for floating-point.
15207 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15208 otherwise nothing
15209 R -- print embeded rounding and sae.
15210 r -- print only sae.
15211 z -- print the opcode suffix for the size of the current operand.
15212 Z -- likewise, with special suffixes for x87 instructions.
15213 * -- print a star (in certain assembler syntax)
15214 A -- print an absolute memory reference.
15215 E -- print address with DImode register names if TARGET_64BIT.
15216 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15217 s -- print a shift double count, followed by the assemblers argument
15218 delimiter.
15219 b -- print the QImode name of the register for the indicated operand.
15220 %b0 would print %al if operands[0] is reg 0.
15221 w -- likewise, print the HImode name of the register.
15222 k -- likewise, print the SImode name of the register.
15223 q -- likewise, print the DImode name of the register.
15224 x -- likewise, print the V4SFmode name of the register.
15225 t -- likewise, print the V8SFmode name of the register.
15226 g -- likewise, print the V16SFmode name of the register.
15227 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15228 y -- print "st(0)" instead of "st" as a register.
15229 d -- print duplicated register operand for AVX instruction.
15230 D -- print condition for SSE cmp instruction.
15231 P -- if PIC, print an @PLT suffix.
15232 p -- print raw symbol name.
15233 X -- don't print any sort of PIC '@' suffix for a symbol.
15234 & -- print some in-use local-dynamic symbol name.
15235 H -- print a memory address offset by 8; used for sse high-parts
15236 Y -- print condition for XOP pcom* instruction.
15237 + -- print a branch hint as 'cs' or 'ds' prefix
15238 ; -- print a semicolon (after prefixes due to bug in older gas).
15239 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15240 @ -- print a segment register of thread base pointer load
15241 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15242 ! -- print MPX prefix for jxx/call/ret instructions if required.
15243 */
15245 void
15247 {
15249 {
15251 {
15254 {
15260 /* Intel syntax. For absolute addresses, registers should not
15261 be surrounded by braces. */
15263 {
15268 }
15273 }
15279 /* Wrap address in an UNSPEC to declare special handling. */
15317 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15322 {
15336 output_operand_lossage
15339 }
15342 #endif
15347 {
15348 /* Opcodes don't get size suffixes if using Intel opcodes. */
15353 {
15371 output_operand_lossage
15374 }
15375 }
15378 warning
15380 /* FALLTHRU */
15383 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15388 {
15390 {
15392 #ifdef HAVE_AS_IX86_FILDS
15394 #endif
15402 #ifdef HAVE_AS_IX86_FILDQ
15404 #else
15406 #endif
15411 }
15412 }
15414 {
15415 /* 387 opcodes don't get size suffixes
15416 if the operands are registers. */
15421 {
15437 }
15438 }
15439 else
15440 {
15441 output_operand_lossage
15444 }
15446 output_operand_lossage
15467 {
15470 }
15475 {
15526 }
15530 /* Little bit of braindamage here. The SSE compare instructions
15531 does use completely different names for the comparisons that the
15532 fp conditional moves. */
15534 {
15537 {
15540 }
15546 {
15549 }
15555 {
15558 }
15567 {
15570 }
15576 {
15579 }
15585 {
15588 }
15599 }
15604 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15607 #endif
15612 {
15616 }
15620 file);
15625 {
15629 }
15630 /* It doesn't actually matter what mode we use here, as we're
15631 only going to use this for printing. */
15633 /* Output 'qword ptr' for intel assembler dialect. */
15642 #ifdef HAVE_AS_IX86_HLE
15644 #else
15646 #endif
15648 #ifdef HAVE_AS_IX86_HLE
15650 #else
15652 #endif
15653 /* We do not want to print value of the operand. */
15682 {
15697 }
15710 {
15715 else
15718 }
15721 {
15722 rtx x;
15731 {
15736 {
15738 bool cputaken
15741 /* Emit hints only in the case default branch prediction
15742 heuristics would fail. */
15744 {
15745 /* We use 3e (DS) prefix for taken branches and
15746 2e (CS) prefix for not taken branches. */
15749 else
15751 }
15752 }
15753 }
15755 }
15758 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15760 #endif
15767 /* The kernel uses a different segment register for performance
15768 reasons; a system call would not have to trash the userspace
15769 segment register, which would be expensive. */
15772 else
15792 }
15793 }
15799 {
15800 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15803 {
15806 {
15815 else
15822 }
15824 /* Check for explicit size override (codes 'b', 'w', 'k',
15825 'q' and 'x') */
15839 }
15842 /* Avoid (%rip) for call operands. */
15848 else
15850 }
15853 {
15854 REAL_VALUE_TYPE r;
15862 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15866 else
15868 }
15871 {
15872 REAL_VALUE_TYPE r;
15881 }
15883 /* These float cases don't actually occur as immediate operands. */
15885 {
15890 }
15892 else
15893 {
15894 /* We have patterns that allow zero sets of memory, for instance.
15895 In 64-bit mode, we should probably support all 8-byte vectors,
15896 since we can in fact encode that into an immediate. */
15898 {
15901 }
15904 {
15906 {
15909 }
15912 {
15915 else
15917 }
15918 }
15923 else
15925 }
15926 }
15928 static bool
15930 {
15933 }
15934 \f
15935 /* Print a memory operand whose address is ADDR. */
15937 static void
15939 {
15948 {
15955 }
15957 {
15961 }
15963 {
15967 {
15970 }
15973 }
15975 {
15980 }
15981 else
15992 {
16003 }
16005 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16007 {
16019 }
16021 {
16022 /* Displacement only requires special attention. */
16025 {
16029 }
16032 else
16034 }
16035 else
16036 {
16037 /* Print SImode register names to force addr32 prefix. */
16039 {
16040 #ifdef ENABLE_CHECKING
16043 {
16054 }
16055 #endif
16058 }
16060 && TARGET_X32
16061 && disp
16064 {
16065 /* X32 runs in 64-bit mode, where displacement, DISP, in
16066 address DISP(%r64), is encoded as 32-bit immediate sign-
16067 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16068 address is %r64 + 0xffffffffbffffd00. When %r64 <
16069 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16070 which is invalid for x32. The correct address is %r64
16071 - 0x40000300 == 0xf7ffdd64. To properly encode
16072 -0x40000300(%r64) for x32, we zero-extend negative
16073 displacement by forcing addr32 prefix which truncates
16074 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16075 zero-extend all negative displacements, including -1(%rsp).
16076 However, for small negative displacements, sign-extension
16077 won't cause overflow. We only zero-extend negative
16078 displacements if they < -16*1024*1024, which is also used
16079 to check legitimate address displacements for PIC. */
16081 }
16084 {
16086 {
16091 else
16093 }
16099 {
16104 }
16106 }
16107 else
16108 {
16112 {
16113 /* Pull out the offset of a symbol; print any symbol itself. */
16117 {
16121 }
16129 else
16131 }
16135 {
16138 {
16142 }
16143 }
16146 else
16150 {
16155 }
16157 }
16158 }
16159 }
16161 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16163 static bool
16165 {
16166 rtx op;
16173 {
16176 /* FIXME: This might be @TPOFF in Sun ld. */
16187 else
16199 else
16206 #if TARGET_MACHO
16212 #endif
16215 {
16220 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16222 #else
16224 #endif
16227 }
16232 }
16235 }
16236 \f
16237 /* Split one or more double-mode RTL references into pairs of half-mode
16238 references. The RTL can be REG, offsettable MEM, integer constant, or
16239 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16240 split and "num" is its length. lo_half and hi_half are output arrays
16241 that parallel "operands". */
16243 void
16246 {
16247 machine_mode half_mode;
16251 {
16260 }
16265 {
16268 /* simplify_subreg refuse to split volatile memory addresses,
16269 but we still have to handle it. */
16271 {
16274 }
16275 else
16276 {
16283 }
16284 }
16285 }
16286 \f
16287 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16288 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16289 is the expression of the binary operation. The output may either be
16290 emitted here, or returned to the caller, like all output_* functions.
16292 There is no guarantee that the operands are the same mode, as they
16293 might be within FLOAT or FLOAT_EXTEND expressions. */
16295 #ifndef SYSV386_COMPAT
16296 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16297 wants to fix the assemblers because that causes incompatibility
16298 with gcc. No-one wants to fix gcc because that causes
16299 incompatibility with assemblers... You can use the option of
16300 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16301 #define SYSV386_COMPAT 1
16302 #endif
16306 {
16312 #ifdef ENABLE_CHECKING
16313 /* Even if we do not want to check the inputs, this documents input
16314 constraints. Which helps in understanding the following code. */
16324 else
16326 #endif
16329 {
16334 else
16343 else
16352 else
16361 else
16368 }
16371 {
16373 {
16377 else
16379 }
16380 else
16381 {
16385 else
16387 }
16389 }
16393 {
16397 {
16401 }
16403 /* know operands[0] == operands[1]. */
16406 {
16409 }
16412 {
16414 /* How is it that we are storing to a dead operand[2]?
16415 Well, presumably operands[1] is dead too. We can't
16416 store the result to st(0) as st(0) gets popped on this
16417 instruction. Instead store to operands[2] (which I
16418 think has to be st(1)). st(1) will be popped later.
16419 gcc <= 2.8.1 didn't have this check and generated
16420 assembly code that the Unixware assembler rejected. */
16422 else
16425 }
16429 else
16436 {
16439 }
16442 {
16445 }
16448 {
16449 #if SYSV386_COMPAT
16450 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16451 derived assemblers, confusingly reverse the direction of
16452 the operation for fsub{r} and fdiv{r} when the
16453 destination register is not st(0). The Intel assembler
16454 doesn't have this brain damage. Read !SYSV386_COMPAT to
16455 figure out what the hardware really does. */
16458 else
16460 #else
16462 /* As above for fmul/fadd, we can't store to st(0). */
16464 else
16466 #endif
16468 }
16471 {
16472 #if SYSV386_COMPAT
16475 else
16477 #else
16480 else
16482 #endif
16484 }
16487 {
16490 else
16493 }
16495 {
16496 #if SYSV386_COMPAT
16498 #else
16500 #endif
16501 }
16502 else
16503 {
16504 #if SYSV386_COMPAT
16506 #else
16508 #endif
16509 }
16514 }
16518 }
16520 /* Check if a 256bit AVX register is referenced inside of EXP. */
16522 static bool
16524 {
16530 }
16532 /* Return needed mode for entity in optimize_mode_switching pass. */
16534 static int
16536 {
16538 {
16539 rtx link;
16541 /* Needed mode is set to AVX_U128_CLEAN if there are
16542 no 256bit modes used in function arguments. */
16544 link;
16546 {
16548 {
16553 }
16554 }
16557 }
16559 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16560 changes state only when a 256bit register is written to, but we need
16561 to prevent the compiler from moving optimal insertion point above
16562 eventual read from 256bit register. */
16569 }
16571 /* Return mode that i387 must be switched into
16572 prior to the execution of insn. */
16574 static int
16576 {
16579 /* The mode UNINITIALIZED is used to store control word after a
16580 function call or ASM pattern. The mode ANY specify that function
16581 has no requirements on the control word and make no changes in the
16582 bits we are interested in. */
16596 {
16619 }
16622 }
16624 /* Return mode that entity must be switched into
16625 prior to the execution of insn. */
16627 static int
16629 {
16631 {
16641 }
16643 }
16645 /* Check if a 256bit AVX register is referenced in stores. */
16647 static void
16649 {
16651 {
16654 }
16655 }
16657 /* Calculate mode of upper 128bit AVX registers after the insn. */
16659 static int
16661 {
16668 /* We know that state is clean after CALL insn if there are no
16669 256bit registers used in the function return register. */
16671 {
16676 }
16678 /* Otherwise, return current mode. Remember that if insn
16679 references AVX 256bit registers, the mode was already changed
16680 to DIRTY from MODE_NEEDED. */
16682 }
16684 /* Return the mode that an insn results in. */
16686 int
16688 {
16690 {
16700 }
16701 }
16703 static int
16705 {
16706 tree arg;
16708 /* Entry mode is set to AVX_U128_DIRTY if there are
16709 256bit modes used in function arguments. */
16712 {
16717 }
16720 }
16722 /* Return a mode that ENTITY is assumed to be
16723 switched to at function entry. */
16725 static int
16727 {
16729 {
16739 }
16740 }
16742 static int
16744 {
16747 /* Exit mode is set to AVX_U128_DIRTY if there are
16748 256bit modes used in the function return register. */
16753 }
16755 /* Return a mode that ENTITY is assumed to be
16756 switched to at function exit. */
16758 static int
16760 {
16762 {
16772 }
16773 }
16775 static int
16777 {
16779 }
16781 /* Output code to initialize control word copies used by trunc?f?i and
16782 rounding patterns. CURRENT_MODE is set to current control word,
16783 while NEW_MODE is set to new control word. */
16785 static void
16787 {
16789 rtx new_mode;
16800 {
16802 {
16804 /* round toward zero (truncate) */
16810 /* round down toward -oo */
16817 /* round up toward +oo */
16824 /* mask precision exception for nearbyint() */
16831 }
16832 }
16833 else
16834 {
16836 {
16838 /* round toward zero (truncate) */
16844 /* round down toward -oo */
16850 /* round up toward +oo */
16856 /* mask precision exception for nearbyint() */
16863 }
16864 }
16870 }
16872 /* Emit vzeroupper. */
16874 void
16876 {
16879 /* Cancel automatic vzeroupper insertion if there are
16880 live call-saved SSE registers at the insertion point. */
16892 }
16894 /* Generate one or more insns to set ENTITY to MODE. */
16896 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16897 is the set of hard registers live at the point where the insn(s)
16898 are to be inserted. */
16900 static void
16902 HARD_REG_SET regs_live)
16903 {
16905 {
16920 }
16921 }
16923 /* Output code for INSN to convert a float to a signed int. OPERANDS
16924 are the insn operands. The output may be [HSD]Imode and the input
16925 operand may be [SDX]Fmode. */
16929 {
16934 /* Jump through a hoop or two for DImode, since the hardware has no
16935 non-popping instruction. We used to do this a different way, but
16936 that was somewhat fragile and broke with post-reload splitters. */
16946 else
16947 {
16952 else
16956 }
16959 }
16961 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16962 have the values zero or one, indicates the ffreep insn's operand
16963 from the OPERANDS array. */
16967 {
16969 #ifdef HAVE_AS_IX86_FFREEP
16971 #else
16972 {
16982 }
16983 #endif
16986 }
16989 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16990 should be used. UNORDERED_P is true when fucom should be used. */
16994 {
17000 {
17003 }
17004 else
17005 {
17008 }
17011 {
17015 else
17017 else
17020 else
17022 }
17029 {
17031 {
17034 }
17035 else
17037 }
17040 && stack_top_dies
17043 {
17044 /* If both the top of the 387 stack dies, and the other operand
17045 is also a stack register that dies, then this must be a
17046 `fcompp' float compare */
17049 {
17050 /* There is no double popping fcomi variant. Fortunately,
17051 eflags is immune from the fstp's cc clobbering. */
17054 else
17057 }
17058 else
17059 {
17062 else
17064 }
17065 }
17066 else
17067 {
17068 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17071 {
17079 NULL,
17080 NULL,
17087 NULL,
17088 NULL,
17089 NULL,
17090 NULL
17091 };
17106 }
17107 }
17109 void
17111 {
17114 #ifdef ASM_QUAD
17117 #else
17119 #endif
17122 }
17124 void
17126 {
17129 #ifdef ASM_QUAD
17132 #else
17134 #endif
17135 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17141 #if TARGET_MACHO
17143 {
17147 }
17148 #endif
17149 else
17152 }
17153 \f
17154 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17155 for the target. */
17157 void
17159 {
17160 rtx tmp;
17162 /* We play register width games, which are only valid after reload. */
17165 /* Avoid HImode and its attendant prefix byte. */
17171 {
17174 }
17177 }
17179 /* X is an unchanging MEM. If it is a constant pool reference, return
17180 the constant pool rtx, else NULL. */
17182 rtx
17184 {
17191 }
17193 void
17195 {
17203 {
17204 rtx tmp;
17208 {
17214 }
17217 }
17221 {
17224 rtx tmp;
17229 else
17233 {
17240 }
17241 }
17245 {
17247 {
17248 #if TARGET_MACHO
17249 /* dynamic-no-pic */
17251 {
17252 rtx temp = ((reload_in_progress
17260 }
17262 {
17266 }
17269 else
17270 {
17278 }
17279 /* dynamic-no-pic */
17280 #endif
17281 }
17282 else
17283 {
17287 {
17293 }
17294 }
17295 }
17296 else
17297 {
17308 /* Force large constants in 64bit compilation into register
17309 to get them CSEed. */
17321 {
17322 /* If we are loading a floating point constant to a register,
17323 force the value to memory now, since we'll get better code
17324 out the back end. */
17328 {
17333 }
17334 }
17335 }
17338 }
17340 void
17342 {
17349 /* Force constants other than zero into memory. We do not know how
17350 the instructions used to build constants modify the upper 64 bits
17351 of the register, once we have that information we may be able
17352 to handle some of them more efficiently. */
17361 /* We need to check memory alignment for SSE mode since attribute
17362 can make operands unaligned. */
17367 {
17370 /* ix86_expand_vector_move_misalign() does not like constants ... */
17376 /* ... nor both arguments in memory. */
17384 }
17386 /* Make operand1 a register if it isn't already. */
17390 {
17393 }
17396 }
17398 /* Split 32-byte AVX unaligned load and store if needed. */
17400 static void
17402 {
17403 rtx m;
17407 machine_mode mode;
17410 {
17431 }
17434 {
17436 {
17443 }
17444 /* Normal *mov<mode>_internal pattern will handle
17445 unaligned loads just fine if misaligned_operand
17446 is true, and without the UNSPEC it can be combined
17447 with arithmetic instructions. */
17450 else
17452 }
17454 {
17456 {
17461 }
17462 else
17464 }
17465 else
17467 }
17469 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17470 straight to ix86_expand_vector_move. */
17471 /* Code generation for scalar reg-reg moves of single and double precision data:
17472 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17473 movaps reg, reg
17474 else
17475 movss reg, reg
17476 if (x86_sse_partial_reg_dependency == true)
17477 movapd reg, reg
17478 else
17479 movsd reg, reg
17481 Code generation for scalar loads of double precision data:
17482 if (x86_sse_split_regs == true)
17483 movlpd mem, reg (gas syntax)
17484 else
17485 movsd mem, reg
17487 Code generation for unaligned packed loads of single precision data
17488 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17489 if (x86_sse_unaligned_move_optimal)
17490 movups mem, reg
17492 if (x86_sse_partial_reg_dependency == true)
17493 {
17494 xorps reg, reg
17495 movlps mem, reg
17496 movhps mem+8, reg
17497 }
17498 else
17499 {
17500 movlps mem, reg
17501 movhps mem+8, reg
17502 }
17504 Code generation for unaligned packed loads of double precision data
17505 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17506 if (x86_sse_unaligned_move_optimal)
17507 movupd mem, reg
17509 if (x86_sse_split_regs == true)
17510 {
17511 movlpd mem, reg
17512 movhpd mem+8, reg
17513 }
17514 else
17515 {
17516 movsd mem, reg
17517 movhpd mem+8, reg
17518 }
17519 */
17521 void
17523 {
17532 {
17534 {
17538 {
17540 {
17543 }
17544 else
17546 }
17548 /* FALLTHRU */
17552 {
17567 }
17573 else
17581 }
17584 }
17588 {
17590 {
17594 {
17596 {
17599 }
17600 else
17602 }
17604 /* FALLTHRU */
17614 }
17617 }
17620 {
17621 /* Normal *mov<mode>_internal pattern will handle
17622 unaligned loads just fine if misaligned_operand
17623 is true, and without the UNSPEC it can be combined
17624 with arithmetic instructions. */
17630 /* ??? If we have typed data, then it would appear that using
17631 movdqu is the only way to get unaligned data loaded with
17632 integer type. */
17634 {
17636 {
17639 }
17641 /* We will eventually emit movups based on insn attributes. */
17645 }
17647 {
17648 rtx zero;
17651 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17652 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17654 {
17655 /* We will eventually emit movups based on insn attributes. */
17658 }
17660 /* When SSE registers are split into halves, we can avoid
17661 writing to the top half twice. */
17663 {
17666 }
17667 else
17668 {
17669 /* ??? Not sure about the best option for the Intel chips.
17670 The following would seem to satisfy; the register is
17671 entirely cleared, breaking the dependency chain. We
17672 then store to the upper half, with a dependency depth
17673 of one. A rumor has it that Intel recommends two movsd
17674 followed by an unpacklpd, but this is unconfirmed. And
17675 given that the dependency depth of the unpacklpd would
17676 still be one, I'm not sure why this would be better. */
17678 }
17684 }
17685 else
17686 {
17687 rtx t;
17690 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17691 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17693 {
17695 {
17698 }
17705 }
17709 else
17714 else
17723 }
17724 }
17726 {
17728 {
17731 /* We will eventually emit movups based on insn attributes. */
17733 }
17735 {
17737 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17738 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17740 /* We will eventually emit movups based on insn attributes. */
17742 else
17743 {
17748 }
17749 }
17750 else
17751 {
17756 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17757 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17759 {
17762 }
17763 else
17764 {
17769 }
17770 }
17771 }
17772 else
17774 }
17776 /* Helper function of ix86_fixup_binary_operands to canonicalize
17777 operand order. Returns true if the operands should be swapped. */
17779 static bool
17781 rtx operands[])
17782 {
17787 /* If the operation is not commutative, we can't do anything. */
17791 /* Highest priority is that src1 should match dst. */
17797 /* Next highest priority is that immediate constants come second. */
17803 /* Lowest priority is that memory references should come second. */
17810 }
17813 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17814 destination to use for the operation. If different from the true
17815 destination in operands[0], a copy operation will be required. */
17817 rtx
17819 rtx operands[])
17820 {
17825 /* Canonicalize operand order. */
17827 {
17828 /* It is invalid to swap operands of different modes. */
17832 }
17834 /* Both source operands cannot be in memory. */
17836 {
17837 /* Optimization: Only read from memory once. */
17839 {
17842 }
17845 else
17847 }
17849 /* If the destination is memory, and we do not have matching source
17850 operands, do things in registers. */
17854 /* Source 1 cannot be a constant. */
17858 /* Source 1 cannot be a non-matching memory. */
17862 /* Improve address combine. */
17871 }
17873 /* Similarly, but assume that the destination has already been
17874 set up properly. */
17876 void
17879 {
17882 }
17884 /* Attempt to expand a binary operator. Make the expansion closer to the
17885 actual machine, then just general_operand, which will allow 3 separate
17886 memory references (one output, two input) in a single insn. */
17888 void
17890 rtx operands[])
17891 {
17898 /* Emit the instruction. */
17902 {
17903 /* Reload doesn't know about the flags register, and doesn't know that
17904 it doesn't want to clobber it. We can only do this with PLUS. */
17907 }
17911 {
17912 /* This is going to be an LEA; avoid splitting it later. */
17914 }
17915 else
17916 {
17919 }
17921 /* Fix up the destination if needed. */
17924 }
17926 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17927 the given OPERANDS. */
17929 void
17931 rtx operands[])
17932 {
17935 {
17938 }
17940 {
17943 }
17944 /* Optimize (__m128i) d | (__m128i) e and similar code
17945 when d and e are float vectors into float vector logical
17946 insn. In C/C++ without using intrinsics there is no other way
17947 to express vector logical operation on float vectors than
17948 to cast them temporarily to integer vectors. */
17950 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17959 {
17960 rtx dst;
17962 {
17971 {
17974 }
17975 else
17976 {
17981 }
17992 }
17993 }
18002 }
18004 /* Return TRUE or FALSE depending on whether the binary operator meets the
18005 appropriate constraints. */
18007 bool
18010 {
18015 /* Both source operands cannot be in memory. */
18019 /* Canonicalize operand order for commutative operators. */
18023 /* If the destination is memory, we must have a matching source operand. */
18027 /* Source 1 cannot be a constant. */
18031 /* Source 1 cannot be a non-matching memory. */
18033 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18041 }
18043 /* Attempt to expand a unary operator. Make the expansion closer to the
18044 actual machine, then just general_operand, which will allow 2 separate
18045 memory references (one output, one input) in a single insn. */
18047 void
18049 rtx operands[])
18050 {
18057 /* If the destination is memory, and we do not have matching source
18058 operands, do things in registers. */
18061 {
18064 else
18066 }
18068 /* When source operand is memory, destination must match. */
18072 /* Emit the instruction. */
18076 {
18077 /* Reload doesn't know about the flags register, and doesn't know that
18078 it doesn't want to clobber it. */
18081 }
18082 else
18083 {
18086 }
18088 /* Fix up the destination if needed. */
18091 }
18093 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18094 divisor are within the range [0-255]. */
18096 void
18099 {
18108 {
18121 }
18128 /* Use 8bit unsigned divimod if dividend and divisor are within
18129 the range [0-255]. */
18138 pc_rtx);
18143 /* Generate original signed/unsigned divimod. */
18148 /* Branch to the end. */
18152 /* Generate 8bit unsigned divide. */
18154 /* Don't use operands[0] for result of 8bit divide since not all
18155 registers support QImode ZERO_EXTRACT. */
18162 {
18165 }
18166 else
18167 {
18170 }
18172 /* Extract remainder from AH. */
18176 else
18177 {
18178 /* Need a new scratch register since the old one has result
18179 of 8bit divide. */
18183 }
18186 /* Zero extend quotient from AL. */
18192 }
18194 #define LEA_MAX_STALL (3)
18195 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18197 /* Increase given DISTANCE in half-cycles according to
18198 dependencies between PREV and NEXT instructions.
18199 Add 1 half-cycle if there is no dependency and
18200 go to next cycle if there is some dependecy. */
18202 static unsigned int
18204 {
18220 }
18222 /* Function checks if instruction INSN defines register number
18223 REGNO1 or REGNO2. */
18225 static bool
18227 rtx insn)
18228 {
18229 df_ref def;
18239 }
18241 /* Function checks if instruction INSN uses register number
18242 REGNO as a part of address expression. */
18244 static bool
18246 {
18247 df_ref use;
18254 }
18256 /* Search backward for non-agu definition of register number REGNO1
18257 or register number REGNO2 in basic block starting from instruction
18258 START up to head of basic block or instruction INSN.
18260 Function puts true value into *FOUND var if definition was found
18261 and false otherwise.
18263 Distance in half-cycles between START and found instruction or head
18264 of BB is added to DISTANCE and returned. */
18266 static int
18270 {
18280 {
18282 {
18285 {
18288 {
18291 }
18292 }
18295 }
18300 }
18303 }
18305 /* Search backward for non-agu definition of register number REGNO1
18306 or register number REGNO2 in INSN's basic block until
18307 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18308 2. Reach neighbour BBs boundary, or
18309 3. Reach agu definition.
18310 Returns the distance between the non-agu definition point and INSN.
18311 If no definition point, returns -1. */
18313 static int
18316 {
18327 {
18328 edge e;
18329 edge_iterator ei;
18334 {
18337 }
18343 else
18344 {
18349 {
18350 int bb_dist
18356 {
18363 }
18364 }
18367 }
18368 }
18370 /* get_attr_type may modify recog data. We want to make sure
18371 that recog data is valid for instruction INSN, on which
18372 distance_non_agu_define is called. INSN is unchanged here. */
18379 }
18381 /* Return the distance in half-cycles between INSN and the next
18382 insn that uses register number REGNO in memory address added
18383 to DISTANCE. Return -1 if REGNO0 is set.
18385 Put true value into *FOUND if register usage was found and
18386 false otherwise.
18387 Put true value into *REDEFINED if register redefinition was
18388 found and false otherwise. */
18390 static int
18394 {
18403 {
18406 /* If insn and start belong to the same bb, set prev to insn,
18407 so the call to increase_distance will increase the distance
18408 between insns by 1. */
18410 }
18415 {
18417 {
18420 {
18421 /* Return DISTANCE if OP0 is used in memory
18422 address in NEXT. */
18425 }
18428 {
18429 /* Return -1 if OP0 is set in NEXT. */
18432 }
18435 }
18441 }
18444 }
18446 /* Return the distance between INSN and the next insn that uses
18447 register number REGNO0 in memory address. Return -1 if no such
18448 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18450 static int
18452 {
18464 {
18465 edge e;
18466 edge_iterator ei;
18471 {
18474 }
18480 else
18481 {
18487 {
18488 int bb_dist
18493 {
18500 }
18501 }
18504 }
18505 }
18511 }
18513 /* Define this macro to tune LEA priority vs ADD, it take effect when
18514 there is a dilemma of choicing LEA or ADD
18515 Negative value: ADD is more preferred than LEA
18516 Zero: Netrual
18517 Positive value: LEA is more preferred than ADD*/
18518 #define IX86_LEA_PRIORITY 0
18520 /* Return true if usage of lea INSN has performance advantage
18521 over a sequence of instructions. Instructions sequence has
18522 SPLIT_COST cycles higher latency than lea latency. */
18524 static bool
18527 {
18530 /* For Silvermont if using a 2-source or 3-source LEA for
18531 non-destructive destination purposes, or due to wanting
18532 ability to use SCALE, the use of LEA is justified. */
18534 {
18542 }
18548 {
18549 /* If there is no non AGU operand definition, no AGU
18550 operand usage and split cost is 0 then both lea
18551 and non lea variants have same priority. Currently
18552 we prefer lea for 64 bit code and non lea on 32 bit
18553 code. */
18556 else
18558 }
18560 /* With longer definitions distance lea is more preferable.
18561 Here we change it to take into account splitting cost and
18562 lea priority. */
18565 /* If there is no use in memory addess then we just check
18566 that split cost exceeds AGU stall. */
18570 /* If this insn has both backward non-agu dependence and forward
18571 agu dependence, the one with short distance takes effect. */
18573 }
18575 /* Return true if it is legal to clobber flags by INSN and
18576 false otherwise. */
18578 static bool
18580 {
18582 df_ref use;
18583 bitmap live;
18586 {
18588 {
18595 }
18601 }
18605 }
18607 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18608 move and add to avoid AGU stalls. */
18610 bool
18612 {
18615 /* Check if we need to optimize. */
18619 /* Check it is correct to split here. */
18627 /* We need to split only adds with non destructive
18628 destination operand. */
18631 else
18633 }
18635 /* Return true if we should emit lea instruction instead of mov
18636 instruction. */
18638 bool
18640 {
18643 /* Check if we need to optimize. */
18647 /* Use lea for reg to reg moves only. */
18655 }
18657 /* Return true if we need to split lea into a sequence of
18658 instructions to avoid AGU stalls. */
18660 bool
18662 {
18668 /* Check we need to optimize. */
18672 /* The "at least two components" test below might not catch simple
18673 move or zero extension insns if parts.base is non-NULL and parts.disp
18674 is const0_rtx as the only components in the address, e.g. if the
18675 register is %rbp or %r13. As this test is much cheaper and moves or
18676 zero extensions are the common case, do this check first. */
18682 /* Check if it is OK to split here. */
18689 /* There should be at least two components in the address. */
18694 /* We should not split into add if non legitimate pic
18695 operand is used as displacement. */
18710 /* Compute how many cycles we will add to execution time
18711 if split lea into a sequence of instructions. */
18713 {
18714 /* Have to use mov instruction if non desctructive
18715 destination form is used. */
18719 /* Have to add index to base if both exist. */
18723 /* Have to use shift and adds if scale is 2 or greater. */
18725 {
18730 else
18732 }
18734 /* Have to use add instruction with immediate if
18735 disp is non zero. */
18739 /* Subtract the price of lea. */
18741 }
18745 }
18747 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18748 matches destination. RTX includes clobber of FLAGS_REG. */
18750 static void
18753 {
18760 }
18762 /* Return true if regno1 def is nearest to the insn. */
18764 static bool
18766 {
18773 {
18775 {
18778 }
18784 }
18786 /* None of the regs is defined in the bb. */
18788 }
18790 /* Split lea instructions into a sequence of instructions
18791 which are executed on ALU to avoid AGU stalls.
18792 It is assumed that it is allowed to clobber flags register
18793 at lea position. */
18795 void
18797 {
18813 {
18816 }
18819 {
18822 }
18828 {
18829 /* Case r1 = r1 + ... */
18831 {
18832 /* If we have a case r1 = r1 + C * r2 then we
18833 should use multiplication which is very
18834 expensive. Assume cost model is wrong if we
18835 have such case here. */
18840 }
18841 else
18842 {
18843 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18847 /* Use shift for scaling. */
18856 }
18857 }
18859 {
18862 }
18863 else
18864 {
18866 {
18869 }
18871 {
18874 }
18875 else
18876 {
18881 else
18882 {
18883 rtx tmp1;
18885 /* Find better operand for SET instruction, depending
18886 on which definition is farther from the insn. */
18889 else
18899 }
18902 }
18906 }
18907 }
18909 /* Return true if it is ok to optimize an ADD operation to LEA
18910 operation to avoid flag register consumation. For most processors,
18911 ADD is faster than LEA. For the processors like BONNELL, if the
18912 destination register of LEA holds an actual address which will be
18913 used soon, LEA is better and otherwise ADD is better. */
18915 bool
18917 {
18922 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18930 }
18932 /* Return true if destination reg of SET_BODY is shift count of
18933 USE_BODY. */
18935 static bool
18937 {
18938 rtx set_dest;
18939 rtx shift_rtx;
18942 /* Retrieve destination of SET_BODY. */
18944 {
18953 use_body))
18958 }
18960 /* Retrieve shift count of USE_BODY. */
18962 {
18974 }
18982 {
18985 /* Return true if shift count is dest of SET_BODY. */
18987 {
18988 /* Add check since it can be invoked before register
18989 allocation in pre-reload schedule. */
18995 }
18996 }
18999 }
19001 /* Return true if destination reg of SET_INSN is shift count of
19002 USE_INSN. */
19004 bool
19006 {
19009 }
19011 /* Return TRUE or FALSE depending on whether the unary operator meets the
19012 appropriate constraints. */
19014 bool
19016 machine_mode,
19018 {
19019 /* If one of operands is memory, source and destination must match. */
19025 }
19027 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19028 are ok, keeping in mind the possible movddup alternative. */
19030 bool
19032 {
19038 }
19040 /* Post-reload splitter for converting an SF or DFmode value in an
19041 SSE register into an unsigned SImode. */
19043 void
19045 {
19046 machine_mode vecmode;
19056 /* Load up the value into the low element. We must ensure that the other
19057 elements are valid floats -- zero is the easiest such value. */
19059 {
19062 else
19064 }
19065 else
19066 {
19071 else
19073 }
19093 else
19098 }
19100 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19101 Expects the 64-bit DImode to be supplied in a pair of integral
19102 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19103 -mfpmath=sse, !optimize_size only. */
19105 void
19107 {
19111 rtx x;
19117 {
19120 }
19121 else
19122 {
19126 }
19134 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19137 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19138 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19139 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19140 (0x1.0p84 + double(fp_value_hi_xmm)).
19141 Note these exponents differ by 32. */
19145 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19146 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19155 /* Add the upper and lower DFmode values together. */
19158 else
19159 {
19163 }
19166 }
19168 /* Not used, but eases macroization of patterns. */
19169 void
19171 {
19173 }
19175 /* Convert an unsigned SImode value into a DFmode. Only currently used
19176 for SSE, but applicable anywhere. */
19178 void
19180 {
19181 REAL_VALUE_TYPE TWO31r;
19196 }
19198 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19199 32-bit mode; otherwise we have a direct convert instruction. */
19201 void
19203 {
19204 REAL_VALUE_TYPE TWO32r;
19222 }
19224 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19225 For x86_32, -mfpmath=sse, !optimize_size only. */
19226 void
19228 {
19229 REAL_VALUE_TYPE ONE16r;
19248 }
19250 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19251 a vector of unsigned ints VAL to vector of floats TARGET. */
19253 void
19255 {
19257 REAL_VALUE_TYPE TWO16r;
19264 else
19269 OPTAB_DIRECT);
19280 OPTAB_DIRECT);
19282 OPTAB_DIRECT);
19285 }
19287 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19288 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19289 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19290 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19292 rtx
19294 {
19295 REAL_VALUE_TYPE TWO31r;
19310 {
19316 }
19325 OPTAB_DIRECT);
19326 else
19327 {
19333 OPTAB_DIRECT);
19334 }
19337 }
19339 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19340 then replicate the value for all elements of the vector
19341 register. */
19343 rtx
19345 {
19347 rtvec v;
19348 machine_mode scalar_mode;
19351 {
19384 }
19385 }
19387 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19388 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19389 for an SSE register. If VECT is true, then replicate the mask for
19390 all elements of the vector register. If INVERT is true, then create
19391 a mask excluding the sign bit. */
19393 rtx
19395 {
19399 rtx v;
19400 rtx mask;
19402 /* Find the sign bit, sign extended to 2*HWI. */
19404 {
19428 else
19436 {
19439 }
19440 else
19441 {
19442 rtvec vec;
19448 {
19451 }
19452 else
19462 }
19467 }
19472 /* Force this value into the low part of a fp vector constant. */
19481 }
19483 /* Generate code for floating point ABS or NEG. */
19485 void
19487 rtx operands[])
19488 {
19499 {
19505 }
19507 /* NEG and ABS performed with SSE use bitwise mask operations.
19508 Create the appropriate mask now. */
19511 else
19521 {
19523 rtvec par;
19528 else
19529 {
19532 }
19534 }
19535 else
19537 }
19539 /* Expand a copysign operation. Special case operand 0 being a constant. */
19541 void
19543 {
19557 else
19561 {
19568 {
19571 else
19572 {
19576 }
19577 }
19587 else
19591 }
19592 else
19593 {
19603 else
19607 }
19608 }
19610 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19611 be a constant, and so has already been expanded into a vector constant. */
19613 void
19615 {
19631 {
19634 }
19635 }
19637 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19638 so we have to do two masks. */
19640 void
19642 {
19657 {
19658 /* Shouldn't happen often (it's useless, obviously), but when it does
19659 we'd generate incorrect code if we continue below. */
19662 }
19665 {
19676 }
19677 else
19678 {
19680 {
19682 }
19684 {
19688 }
19692 {
19695 }
19697 {
19702 }
19704 }
19708 }
19710 /* Return TRUE or FALSE depending on whether the first SET in INSN
19711 has source and destination with matching CC modes, and that the
19712 CC mode is at least as constrained as REQ_MODE. */
19714 bool
19716 {
19717 rtx set;
19718 machine_mode set_mode;
19728 {
19738 /* FALLTHRU */
19742 /* FALLTHRU */
19746 /* FALLTHRU */
19760 }
19763 }
19765 /* Generate insn patterns to do an integer compare of OPERANDS. */
19767 static rtx
19769 {
19770 machine_mode cmpmode;
19776 /* This is very simple, but making the interface the same as in the
19777 FP case makes the rest of the code easier. */
19781 /* Return the test that should be put into the flags user, i.e.
19782 the bcc, scc, or cmov instruction. */
19784 }
19786 /* Figure out whether to use ordered or unordered fp comparisons.
19787 Return the appropriate mode to use. */
19789 machine_mode
19791 {
19792 /* ??? In order to make all comparisons reversible, we do all comparisons
19793 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19794 all forms trapping and nontrapping comparisons, we can make inequality
19795 comparisons trapping again, since it results in better code when using
19796 FCOM based compares. */
19798 }
19800 machine_mode
19802 {
19806 {
19809 }
19812 {
19813 /* Only zero flag is needed. */
19817 /* Codes needing carry flag. */
19820 /* Detect overflow checks. They need just the carry flag. */
19824 else
19829 /* Codes possibly doable only with sign flag when
19830 comparing against zero. */
19835 else
19836 /* For other cases Carry flag is not required. */
19838 /* Codes doable only with sign flag when comparing
19839 against zero, but we miss jump instruction for it
19840 so we need to use relational tests against overflow
19841 that thus needs to be zero. */
19846 else
19848 /* strcmp pattern do (use flags) and combine may ask us for proper
19849 mode. */
19854 }
19855 }
19857 /* Return the fixed registers used for condition codes. */
19859 static bool
19861 {
19865 }
19867 /* If two condition code modes are compatible, return a condition code
19868 mode which is compatible with both. Otherwise, return
19869 VOIDmode. */
19871 static machine_mode
19873 {
19890 {
19904 {
19918 }
19922 /* These are only compatible with themselves, which we already
19923 checked above. */
19925 }
19926 }
19929 /* Return a comparison we can do and that it is equivalent to
19930 swap_condition (code) apart possibly from orderedness.
19931 But, never change orderedness if TARGET_IEEE_FP, returning
19932 UNKNOWN in that case if necessary. */
19934 static enum rtx_code
19936 {
19938 {
19949 }
19950 }
19952 /* Return cost of comparison CODE using the best strategy for performance.
19953 All following functions do use number of instructions as a cost metrics.
19954 In future this should be tweaked to compute bytes for optimize_size and
19955 take into account performance of various instructions on various CPUs. */
19957 static int
19959 {
19962 /* The cost of code using bit-twiddling on %ah. */
19964 {
19987 }
19990 {
19997 }
19998 }
20000 /* Return strategy to use for floating-point. We assume that fcomi is always
20001 preferrable where available, since that is also true when looking at size
20002 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20004 enum ix86_fpcmp_strategy
20006 {
20007 /* Do fcomi/sahf based test when profitable. */
20016 }
20018 /* Swap, force into registers, or otherwise massage the two operands
20019 to a fp comparison. The operands are updated in place; the new
20020 comparison code is returned. */
20022 static enum rtx_code
20024 {
20030 /* All of the unordered compare instructions only work on registers.
20031 The same is true of the fcomi compare instructions. The XFmode
20032 compare instructions require registers except when comparing
20033 against zero or when converting operand 1 from fixed point to
20034 floating point. */
20043 {
20046 }
20047 else
20048 {
20049 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20050 things around if they appear profitable, otherwise force op0
20051 into a register. */
20057 {
20060 {
20063 }
20064 }
20070 {
20075 {
20078 }
20079 else
20081 }
20082 }
20084 /* Try to rearrange the comparison to make it cheaper. */
20088 {
20093 }
20098 }
20100 /* Convert comparison codes we use to represent FP comparison to integer
20101 code that will result in proper branch. Return UNKNOWN if no such code
20102 is available. */
20104 enum rtx_code
20106 {
20108 {
20131 }
20132 }
20134 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20136 static rtx
20138 {
20145 /* Do fcomi/sahf based test when profitable. */
20147 {
20152 tmp);
20160 tmp);
20169 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20176 /* In the unordered case, we have to check C2 for NaN's, which
20177 doesn't happen to work out to anything nice combination-wise.
20178 So do some bit twiddling on the value we've got in AH to come
20179 up with an appropriate set of condition codes. */
20183 {
20187 {
20190 }
20191 else
20192 {
20198 }
20203 {
20208 }
20209 else
20210 {
20213 }
20218 {
20221 }
20222 else
20223 {
20227 }
20232 {
20238 }
20239 else
20240 {
20243 }
20248 {
20253 }
20254 else
20255 {
20258 }
20263 {
20268 }
20269 else
20270 {
20273 }
20287 }
20292 }
20294 /* Return the test that should be put into the flags user, i.e.
20295 the bcc, scc, or cmov instruction. */
20298 const0_rtx);
20299 }
20301 static rtx
20303 {
20304 rtx ret;
20310 {
20313 }
20314 else
20318 }
20320 void
20322 {
20324 rtx tmp;
20327 {
20334 simple:
20338 pc_rtx);
20346 /* Expand DImode branch into multiple compare+branch. */
20347 {
20351 machine_mode submode;
20354 {
20357 }
20364 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20365 avoid two branches. This costs one extra insn, so disable when
20366 optimizing for size. */
20371 {
20389 }
20391 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20392 op1 is a constant and the low word is zero, then we can just
20393 examine the high word. Similarly for low word -1 and
20394 less-or-equal-than or greater-than. */
20398 {
20401 {
20404 }
20408 {
20411 }
20415 }
20417 /* Otherwise, we need two or three jumps. */
20426 {
20440 }
20442 /*
20443 * a < b =>
20444 * if (hi(a) < hi(b)) goto true;
20445 * if (hi(a) > hi(b)) goto false;
20446 * if (lo(a) < lo(b)) goto true;
20447 * false:
20448 */
20460 }
20465 }
20466 }
20468 /* Split branch based on floating point condition. */
20469 void
20472 {
20473 rtx condition;
20474 rtx i;
20477 {
20482 }
20485 tmp);
20493 }
20495 void
20497 {
20498 rtx ret;
20505 }
20507 /* Expand comparison setting or clearing carry flag. Return true when
20508 successful and set pop for the operation. */
20509 static bool
20511 {
20512 machine_mode mode =
20515 /* Do not handle double-mode compares that go through special path. */
20520 {
20521 rtx compare_op;
20526 /* Shortcut: following common codes never translate
20527 into carry flag compares. */
20532 /* These comparisons require zero flag; swap operands so they won't. */
20535 {
20538 }
20540 /* Try to expand the comparison and verify that we end up with
20541 carry flag based comparison. This fails to be true only when
20542 we decide to expand comparison using arithmetic that is not
20543 too common scenario. */
20552 else
20561 }
20567 {
20572 /* Convert a==0 into (unsigned)a<1. */
20581 /* Convert a>b into b<a or a>=b-1. */
20585 {
20587 /* Bail out on overflow. We still can swap operands but that
20588 would force loading of the constant into register. */
20593 }
20594 else
20595 {
20598 }
20601 /* Convert a>=0 into (unsigned)a<0x80000000. */
20619 }
20620 /* Swapping operands may cause constant to appear as first operand. */
20622 {
20626 }
20630 }
20632 bool
20634 {
20637 rtx compare_op;
20659 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20660 HImode insns, we'd be swallowed in word prefix ops. */
20666 {
20670 HOST_WIDE_INT diff;
20673 /* Sign bit compares are better done using shifts than we do by using
20674 sbb. */
20677 {
20678 /* Detect overlap between destination and compare sources. */
20682 {
20683 rtx flags;
20692 {
20694 compare_code
20696 }
20698 /* To simplify rest of code, restrict to the GEU case. */
20700 {
20706 }
20707 else
20708 {
20711 reverse_condition_maybe_unordered
20713 else
20716 }
20725 else
20728 }
20729 else
20730 {
20733 else
20734 {
20739 }
20741 }
20744 {
20745 /*
20746 * cmpl op0,op1
20747 * sbbl dest,dest
20748 * [addl dest, ct]
20749 *
20750 * Size 5 - 8.
20751 */
20756 }
20758 {
20759 /*
20760 * cmpl op0,op1
20761 * sbbl dest,dest
20762 * orl $ct, dest
20763 *
20764 * Size 8.
20765 */
20769 }
20771 {
20772 /*
20773 * cmpl op0,op1
20774 * sbbl dest,dest
20775 * notl dest
20776 * [addl dest, cf]
20777 *
20778 * Size 8 - 11.
20779 */
20785 }
20786 else
20787 {
20788 /*
20789 * cmpl op0,op1
20790 * sbbl dest,dest
20791 * [notl dest]
20792 * andl cf - ct, dest
20793 * [addl dest, ct]
20794 *
20795 * Size 8 - 11.
20796 */
20799 {
20803 }
20813 }
20819 }
20822 {
20829 {
20832 /* We may be reversing unordered compare to normal compare, that
20833 is not valid in general (we may convert non-trapping condition
20834 to trapping one), however on i386 we currently emit all
20835 comparisons unordered. */
20838 }
20839 else
20840 {
20843 }
20844 }
20849 {
20854 {
20859 }
20860 }
20862 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20866 {
20867 /* If lea code below could be used, only optimize
20868 if it results in a 2 insn sequence. */
20874 {
20875 /*
20876 * notl op1 (if necessary)
20877 * sarl $31, op1
20878 * orl cf, op1
20879 */
20881 {
20885 }
20896 }
20897 }
20905 {
20906 /*
20907 * xorl dest,dest
20908 * cmpl op1,op2
20909 * setcc dest
20910 * lea cf(dest*(ct-cf)),dest
20911 *
20912 * Size 14.
20913 *
20914 * This also catches the degenerate setcc-only case.
20915 */
20917 rtx tmp;
20923 /* On x86_64 the lea instruction operates on Pmode, so we need
20924 to get arithmetics done in proper mode to match. */
20927 else
20928 {
20929 rtx out1;
20932 nops++;
20934 {
20936 nops++;
20937 }
20938 }
20940 {
20942 nops++;
20943 }
20945 {
20948 else
20950 }
20955 }
20957 /*
20958 * General case: Jumpful:
20959 * xorl dest,dest cmpl op1, op2
20960 * cmpl op1, op2 movl ct, dest
20961 * setcc dest jcc 1f
20962 * decl dest movl cf, dest
20963 * andl (cf-ct),dest 1:
20964 * addl ct,dest
20965 *
20966 * Size 20. Size 14.
20967 *
20968 * This is reasonably steep, but branch mispredict costs are
20969 * high on modern cpus, so consider failing only if optimizing
20970 * for space.
20971 */
20976 {
20978 {
20985 {
20988 /* We may be reversing unordered compare to normal compare,
20989 that is not valid in general (we may convert non-trapping
20990 condition to trapping one), however on i386 we currently
20991 emit all comparisons unordered. */
20993 }
20994 else
20995 {
20999 }
21000 }
21003 {
21004 /* notl op1 (if needed)
21005 sarl $31, op1
21006 andl (cf-ct), op1
21007 addl ct, op1
21009 For x < 0 (resp. x <= -1) there will be no notl,
21010 so if possible swap the constants to get rid of the
21011 complement.
21012 True/false will be -1/0 while code below (store flag
21013 followed by decrement) is 0/-1, so the constants need
21014 to be exchanged once more. */
21017 {
21020 }
21021 else
21025 }
21026 else
21027 {
21031 constm1_rtx,
21033 }
21045 }
21046 }
21049 {
21050 /* Try a few things more with specific constants and a variable. */
21052 optab op;
21058 /* If one of the two operands is an interesting constant, load a
21059 constant with the above and mask it in with a logical operation. */
21062 {
21068 else
21070 }
21072 {
21078 else
21080 }
21081 else
21088 /* Recurse to get the constant loaded. */
21092 /* Mask in the interesting variable. */
21094 OPTAB_WIDEN);
21099 }
21101 /*
21102 * For comparison with above,
21103 *
21104 * movl cf,dest
21105 * movl ct,tmp
21106 * cmpl op1,op2
21107 * cmovcc tmp,dest
21108 *
21109 * Size 15.
21110 */
21132 }
21134 /* Swap, force into registers, or otherwise massage the two operands
21135 to an sse comparison with a mask result. Thus we differ a bit from
21136 ix86_prepare_fp_compare_args which expects to produce a flags result.
21138 The DEST operand exists to help determine whether to commute commutative
21139 operators. The POP0/POP1 operands are updated in place. The new
21140 comparison code is returned, or UNKNOWN if not implementable. */
21142 static enum rtx_code
21145 {
21147 {
21150 /* AVX supports all the needed comparisons. */
21153 /* We have no LTGT as an operator. We could implement it with
21154 NE & ORDERED, but this requires an extra temporary. It's
21155 not clear that it's worth it. */
21162 /* These are supported directly. */
21169 /* AVX has 3 operand comparisons, no need to swap anything. */
21172 /* For commutative operators, try to canonicalize the destination
21173 operand to be first in the comparison - this helps reload to
21174 avoid extra moves. */
21177 /* FALLTHRU */
21183 /* These are not supported directly before AVX, and furthermore
21184 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21185 comparison operands to transform into something that is
21186 supported. */
21193 }
21196 }
21198 /* Detect conditional moves that exactly match min/max operational
21199 semantics. Note that this is IEEE safe, as long as we don't
21200 interchange the operands.
21202 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21203 and TRUE if the operation is successful and instructions are emitted. */
21205 static bool
21208 {
21209 machine_mode mode;
21211 rtx tmp;
21214 ;
21217 else
21224 else
21229 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21230 but MODE may be a vector mode and thus not appropriate. */
21232 {
21234 rtvec v;
21239 }
21240 else
21241 {
21244 }
21248 }
21250 /* Expand an sse vector comparison. Return the register with the result. */
21252 static rtx
21255 {
21259 /* In general case result of comparison can differ from operands' type. */
21260 machine_mode cmp_mode;
21262 /* In AVX512F the result of comparison is an integer mask. */
21264 rtx x;
21267 {
21272 }
21273 else
21286 /* Compare patterns for int modes are unspec in AVX512F only. */
21288 {
21292 {
21301 }
21304 {
21307 }
21308 }
21312 {
21315 }
21316 else
21320 }
21322 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21323 operations. This is used for both scalar and vector conditional moves. */
21325 static void
21327 {
21331 /* In AVX512F the result of comparison is an integer mask. */
21339 {
21341 }
21344 {
21348 }
21351 {
21356 }
21359 {
21363 }
21366 {
21374 op_true,
21375 op_false)));
21376 }
21377 else
21378 {
21388 {
21402 {
21409 }
21424 {
21431 }
21455 }
21458 {
21462 }
21463 else
21464 {
21470 else
21482 }
21483 }
21484 }
21486 /* Expand a floating-point conditional move. Return true if successful. */
21488 bool
21490 {
21498 {
21499 machine_mode cmode;
21501 /* Since we've no cmove for sse registers, don't force bad register
21502 allocation just to gain access to it. Deny movcc when the
21503 comparison mode doesn't match the move mode. */
21522 }
21529 /* The floating point conditional move instructions don't directly
21530 support conditions resulting from a signed integer comparison. */
21534 {
21539 }
21546 }
21548 /* Expand a floating-point vector conditional move; a vcond operation
21549 rather than a movcc operation. */
21551 bool
21553 {
21555 rtx cmp;
21560 {
21561 rtx temp;
21563 {
21580 }
21582 OPTAB_DIRECT);
21585 }
21595 }
21597 /* Expand a signed/unsigned integral vector conditional move. */
21599 bool
21601 {
21611 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21612 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21621 {
21625 {
21631 }
21634 {
21640 }
21641 }
21650 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21654 ;
21655 else
21656 {
21657 /* Canonicalize the comparison to EQ, GT, GTU. */
21659 {
21676 /* FALLTHRU */
21686 }
21688 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21690 {
21692 {
21694 /* SSE4.1 supports EQ. */
21701 /* SSE4.2 supports GT/GTU. */
21708 }
21709 }
21711 /* Unsigned parallel compare is not supported by the hardware.
21712 Play some tricks to turn this into a signed comparison
21713 against 0. */
21715 {
21719 {
21726 {
21731 {
21740 }
21741 /* Subtract (-(INT MAX) - 1) from both operands to make
21742 them signed. */
21753 }
21762 /* Perform a parallel unsigned saturating subtraction. */
21775 }
21776 }
21777 }
21779 /* Allow the comparison to be done in one mode, but the movcc to
21780 happen in another mode. */
21782 {
21785 }
21786 else
21787 {
21793 }
21798 }
21800 /* AVX512F does support 64-byte integer vector operations,
21801 thus the longest vector we are faced with is V64QImode. */
21802 #define MAX_VECT_LEN 64
21804 struct expand_vec_perm_d
21805 {
21808 machine_mode vmode;
21812 };
21814 static bool
21817 {
21818 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21819 expander, so args are either in d, or in op0, op1 etc. */
21825 {
21852 {
21855 }
21859 {
21862 }
21866 {
21869 }
21885 {
21888 }
21892 {
21895 }
21899 {
21902 }
21906 }
21911 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21912 expander, so args are either in d, or in op0, op1 etc. */
21914 {
21922 }
21926 }
21928 /* Expand a variable vector permutation. */
21930 void
21932 {
21943 /* Number of elements in the vector. */
21952 {
21954 {
21955 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21956 an constant shuffle operand. With a tiny bit of effort we can
21957 use VPERMD instead. A re-interpretation stall for V4DFmode is
21958 unfortunate but there's no avoiding it.
21959 Similarly for V16HImode we don't have instructions for variable
21960 shuffling, while for V32QImode we can use after preparing suitable
21961 masks vpshufb; vpshufb; vpermq; vpor. */
21964 {
21968 }
21969 else
21970 {
21974 }
21977 /* Replicate the low bits of the V4DImode mask into V8SImode:
21978 mask = { A B C D }
21979 t1 = { A A B B C C D D }. */
21987 else
21990 /* Multiply the shuffle indicies by two. */
21992 OPTAB_DIRECT);
21994 /* Add one to the odd shuffle indicies:
21995 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21997 {
22000 }
22004 OPTAB_DIRECT);
22006 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22011 }
22014 {
22016 /* The VPERMD and VPERMPS instructions already properly ignore
22017 the high bits of the shuffle elements. No need for us to
22018 perform an AND ourselves. */
22020 {
22025 }
22026 else
22027 {
22033 }
22040 else
22041 {
22047 }
22051 /* By combining the two 128-bit input vectors into one 256-bit
22052 input vector, we can use VPERMD and VPERMPS for the full
22053 two-operand shuffle. */
22085 /* From mask create two adjusted masks, which contain the same
22086 bits as mask in the low 7 bits of each vector element.
22087 The first mask will have the most significant bit clear
22088 if it requests element from the same 128-bit lane
22089 and MSB set if it requests element from the other 128-bit lane.
22090 The second mask will have the opposite values of the MSB,
22091 and additionally will have its 128-bit lanes swapped.
22092 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22093 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22094 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22095 stands for other 12 bytes. */
22096 /* The bit whether element is from the same lane or the other
22097 lane is bit 4, so shift it up by 3 to the MSB position. */
22101 /* Clear MSB bits from the mask just in case it had them set. */
22103 /* After this t1 will have MSB set for elements from other lane. */
22105 /* Clear bits other than MSB. */
22107 /* Or in the lower bits from mask into t3. */
22109 /* And invert MSB bits in t1, so MSB is set for elements from the same
22110 lane. */
22112 /* Swap 128-bit lanes in t3. */
22117 /* And or in the lower bits from mask into t1. */
22120 {
22121 /* Each of these shuffles will put 0s in places where
22122 element from the other 128-bit lane is needed, otherwise
22123 will shuffle in the requested value. */
22127 /* For t3 the 128-bit lanes are swapped again. */
22132 /* And oring both together leads to the result. */
22139 }
22142 /* Similarly to the above one_operand_shuffle code,
22143 just for repeated twice for each operand. merge_two:
22144 code will merge the two results together. */
22168 }
22169 }
22172 {
22173 /* The XOP VPPERM insn supports three inputs. By ignoring the
22174 one_operand_shuffle special case, we avoid creating another
22175 set of constant vectors in memory. */
22178 /* mask = mask & {2*w-1, ...} */
22180 }
22181 else
22182 {
22183 /* mask = mask & {w-1, ...} */
22185 }
22193 /* For non-QImode operations, convert the word permutation control
22194 into a byte permutation control. */
22196 {
22201 /* Convert mask to vector of chars. */
22204 /* Replicate each of the input bytes into byte positions:
22205 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22206 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22207 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22214 else
22217 /* Convert it into the byte positions by doing
22218 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22224 }
22226 /* The actual shuffle operations all operate on V16QImode. */
22231 {
22238 }
22240 {
22247 }
22248 else
22249 {
22253 /* Shuffle the two input vectors independently. */
22259 merge_two:
22260 /* Then merge them together. The key is whether any given control
22261 element contained a bit set that indicates the second word. */
22265 {
22266 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22267 more shuffle to convert the V2DI input mask into a V4SI
22268 input mask. At which point the masking that expand_int_vcond
22269 will work as desired. */
22277 }
22299 }
22300 }
22302 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22303 true if we should do zero extension, else sign extension. HIGH_P is
22304 true if we want the N/2 high elements, else the low elements. */
22306 void
22308 {
22310 rtx tmp;
22313 {
22319 {
22323 else
22326 extract
22332 else
22335 extract
22341 else
22344 extract
22350 else
22353 extract
22359 else
22362 extract
22368 else
22371 extract
22377 else
22383 else
22389 else
22394 }
22397 {
22400 }
22402 {
22403 /* Shift higher 8 bytes to lower 8 bytes. */
22408 }
22409 else
22413 }
22414 else
22415 {
22419 {
22423 else
22429 else
22435 else
22440 }
22444 else
22451 }
22452 }
22454 /* Expand conditional increment or decrement using adb/sbb instructions.
22455 The default case using setcc followed by the conditional move can be
22456 done by generic code. */
22457 bool
22459 {
22461 rtx flags;
22463 rtx compare_op;
22466 machine_mode mode;
22481 {
22484 }
22487 {
22491 reverse_condition_maybe_unordered
22493 else
22495 }
22499 /* Construct either adc or sbb insn. */
22501 {
22503 {
22518 }
22519 }
22520 else
22521 {
22523 {
22538 }
22539 }
22543 }
22546 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22547 but works for floating pointer parameters and nonoffsetable memories.
22548 For pushes, it returns just stack offsets; the values will be saved
22549 in the right order. Maximally three parts are generated. */
22551 static int
22553 {
22558 else
22564 /* Optimize constant pool reference to immediates. This is used by fp
22565 moves, that force all constants to memory to allow combining. */
22567 {
22571 }
22574 {
22575 /* The only non-offsetable memories we handle are pushes. */
22584 }
22587 {
22589 /* Caution: if we looked through a constant pool memory above,
22590 the operand may actually have a different mode now. That's
22591 ok, since we want to pun this all the way back to an integer. */
22595 }
22598 {
22601 else
22602 {
22606 {
22610 }
22612 {
22617 }
22619 {
22620 REAL_VALUE_TYPE r;
22625 {
22632 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22633 long double may not be 80-bit. */
22642 }
22645 }
22646 else
22648 }
22649 }
22650 else
22651 {
22655 {
22658 {
22662 }
22664 {
22668 }
22670 {
22671 REAL_VALUE_TYPE r;
22677 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22680 = gen_int_mode
22683 DImode);
22684 else
22691 = gen_int_mode
22694 DImode);
22695 else
22697 }
22698 else
22700 }
22701 }
22704 }
22706 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22707 Return false when normal moves are needed; true when all required
22708 insns have been emitted. Operands 2-4 contain the input values
22709 int the correct order; operands 5-7 contain the output values. */
22711 void
22713 {
22721 /* The DFmode expanders may ask us to move double.
22722 For 64bit target this is single move. By hiding the fact
22723 here we simplify i386.md splitters. */
22725 {
22726 /* Optimize constant pool reference to immediates. This is used by
22727 fp moves, that force all constants to memory to allow combining. */
22734 {
22737 }
22738 else
22743 }
22745 /* The only non-offsettable memory we handle is push. */
22748 else
22755 /* When emitting push, take care for source operands on the stack. */
22758 {
22761 /* Compensate for the stack decrement by 4. */
22766 /* src_base refers to the stack pointer and is
22767 automatically decreased by emitted push. */
22771 }
22773 /* We need to do copy in the right order in case an address register
22774 of the source overlaps the destination. */
22776 {
22777 rtx tmp;
22780 {
22784 collisions++;
22785 }
22787 /* Collision in the middle part can be handled by reordering. */
22789 {
22792 }
22796 {
22798 {
22801 }
22802 else
22803 {
22806 }
22807 }
22809 /* If there are more collisions, we can't handle it by reordering.
22810 Do an lea to the last part and use only one colliding move. */
22812 {
22813 rtx base;
22819 /* Handle the case when the last part isn't valid for lea.
22820 Happens in 64-bit mode storing the 12-byte XFmode. */
22827 {
22830 }
22831 }
22832 }
22835 {
22837 {
22839 {
22844 }
22846 {
22849 }
22850 }
22851 else
22852 {
22853 /* In 64bit mode we don't have 32bit push available. In case this is
22854 register, it is OK - we will just use larger counterpart. We also
22855 retype memory - these comes from attempt to avoid REX prefix on
22856 moving of second half of TFmode value. */
22858 {
22860 {
22871 }
22875 }
22876 }
22880 }
22882 /* Choose correct order to not overwrite the source before it is copied. */
22892 {
22894 {
22897 }
22898 }
22899 else
22900 {
22902 {
22905 }
22906 }
22908 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22910 {
22919 }
22925 }
22927 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22928 left shift by a constant, either using a single shift or
22929 a sequence of add instructions. */
22931 static void
22933 {
22939 {
22943 }
22944 else
22945 {
22948 }
22949 }
22951 void
22953 {
22962 {
22967 {
22973 }
22974 else
22975 {
22983 }
22985 }
22992 {
22993 /* Assuming we've chosen a QImode capable registers, then 1 << N
22994 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22996 {
23012 }
23014 /* Otherwise, we can get the same results by manually performing
23015 a bit extract operation on bit 5/6, and then performing the two
23016 shifts. The two methods of getting 0/1 into low/high are exactly
23017 the same size. Avoiding the shift in the bit extract case helps
23018 pentium4 a bit; no one else seems to care much either way. */
23019 else
23020 {
23021 machine_mode half_mode;
23025 HOST_WIDE_INT bits;
23026 rtx x;
23029 {
23035 }
23036 else
23037 {
23043 }
23047 else
23055 }
23060 }
23063 {
23064 /* For -1 << N, we can avoid the shld instruction, because we
23065 know that we're shifting 0...31/63 ones into a -1. */
23069 else
23071 }
23072 else
23073 {
23081 }
23086 {
23092 }
23093 else
23094 {
23099 }
23100 }
23102 void
23104 {
23114 {
23119 {
23125 }
23127 {
23136 }
23137 else
23138 {
23146 }
23147 }
23148 else
23149 {
23161 {
23169 scratch));
23170 }
23171 else
23172 {
23177 }
23178 }
23179 }
23181 void
23183 {
23193 {
23198 {
23205 }
23206 else
23207 {
23215 }
23216 }
23217 else
23218 {
23230 {
23236 scratch));
23237 }
23238 else
23239 {
23244 }
23245 }
23246 }
23248 /* Predict just emitted jump instruction to be taken with probability PROB. */
23249 static void
23251 {
23255 }
23257 /* Helper function for the string operations below. Dest VARIABLE whether
23258 it is aligned to VALUE bytes. If true, jump to the label. */
23261 {
23266 else
23272 else
23275 }
23277 /* Adjust COUNTER by the VALUE. */
23278 static void
23280 {
23285 }
23287 /* Zero extend possibly SImode EXP to Pmode register. */
23288 rtx
23290 {
23292 }
23294 /* Divide COUNTREG by SCALE. */
23295 static rtx
23297 {
23298 rtx sc;
23310 }
23312 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23313 DImode for constant loop counts. */
23315 static machine_mode
23317 {
23325 }
23327 /* Copy the address to a Pmode register. This is used for x32 to
23328 truncate DImode TLS address to a SImode register. */
23330 static rtx
23332 {
23335 else
23336 {
23339 }
23340 }
23342 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23343 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23344 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23345 memory by VALUE (supposed to be in MODE).
23347 The size is rounded down to whole number of chunk size moved at once.
23348 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23351 static void
23356 {
23363 rtx size;
23372 /* Those two should combine. */
23374 {
23378 }
23385 /* This assert could be relaxed - in this case we'll need to compute
23386 smallest power of two, containing in PIECE_SIZE_N and pass it to
23387 offset_address. */
23393 {
23397 /* When unrolling for chips that reorder memory reads and writes,
23398 we can save registers by using single temporary.
23399 Also using 4 temporaries is overkill in 32bit mode. */
23401 {
23403 {
23405 {
23406 destmem =
23408 srcmem =
23410 }
23412 }
23413 }
23414 else
23415 {
23419 {
23422 {
23423 srcmem =
23425 }
23427 }
23429 {
23431 {
23432 destmem =
23434 }
23436 }
23437 }
23438 }
23439 else
23441 {
23443 destmem =
23446 }
23456 {
23462 else
23464 }
23465 else
23473 {
23478 }
23480 }
23482 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23483 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23484 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23485 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23486 ORIG_VALUE is the original value passed to memset to fill the memory with.
23487 Other arguments have same meaning as for previous function. */
23489 static void
23492 rtx count,
23494 {
23495 rtx destexp;
23496 rtx srcexp;
23497 rtx countreg;
23498 HOST_WIDE_INT rounded_count;
23500 /* If possible, it is shorter to use rep movs.
23501 TODO: Maybe it is better to move this logic to decide_alg. */
23512 {
23516 }
23517 else
23520 {
23525 }
23530 {
23533 }
23534 else
23535 {
23539 {
23543 }
23544 else
23547 {
23552 }
23553 else
23554 {
23557 }
23560 }
23561 }
23563 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23564 DESTMEM.
23565 SRC is passed by pointer to be updated on return.
23566 Return value is updated DST. */
23567 static rtx
23569 HOST_WIDE_INT size_to_move)
23570 {
23573 machine_mode move_mode;
23576 /* Find the widest mode in which we could perform moves.
23577 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23578 it until move of such size is supported. */
23583 {
23587 }
23589 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23590 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23592 {
23597 {
23601 }
23602 }
23608 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23612 {
23613 /* We move from memory to memory, so we'll need to do it via
23614 a temporary register. */
23625 piece_size);
23627 piece_size);
23628 }
23630 /* Update DST and SRC rtx. */
23633 }
23635 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23636 static void
23639 {
23642 {
23647 /* For now MAX_SIZE should be a power of 2. This assert could be
23648 relaxed, but it'll require a bit more complicated epilogue
23649 expanding. */
23652 {
23655 }
23657 }
23659 {
23665 }
23667 /* When there are stringops, we can cheaply increase dest and src pointers.
23668 Otherwise we save code size by maintaining offset (zero is readily
23669 available from preceding rep operation) and using x86 addressing modes.
23670 */
23672 {
23674 {
23681 }
23683 {
23690 }
23692 {
23699 }
23700 }
23701 else
23702 {
23704 rtx tmp;
23707 {
23718 }
23720 {
23733 }
23735 {
23744 }
23745 }
23746 }
23748 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23749 with value PROMOTED_VAL.
23750 SRC is passed by pointer to be updated on return.
23751 Return value is updated DST. */
23752 static rtx
23754 HOST_WIDE_INT size_to_move)
23755 {
23758 machine_mode move_mode;
23761 /* Find the widest mode in which we could perform moves.
23762 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23763 it until move of such size is supported. */
23768 {
23771 }
23778 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23782 {
23784 {
23787 piece_size);
23789 }
23797 piece_size);
23798 }
23800 /* Update DST rtx. */
23802 }
23803 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23804 static void
23807 {
23808 count =
23814 }
23816 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23817 static void
23820 {
23821 rtx dest;
23824 {
23829 /* For now MAX_SIZE should be a power of 2. This assert could be
23830 relaxed, but it'll require a bit more complicated epilogue
23831 expanding. */
23834 {
23836 {
23839 else
23841 }
23842 }
23844 }
23846 {
23849 }
23851 {
23854 {
23859 }
23860 else
23861 {
23870 }
23873 }
23875 {
23878 {
23881 }
23882 else
23883 {
23888 }
23891 }
23893 {
23899 }
23901 {
23907 }
23909 {
23915 }
23916 }
23918 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23919 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23920 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23921 ignored.
23922 Return value is updated DESTMEM. */
23923 static rtx
23928 {
23931 {
23933 {
23936 {
23939 else
23941 }
23942 else
23948 }
23949 }
23951 }
23953 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23954 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23955 and jump to DONE_LABEL. */
23956 static void
23962 {
23965 rtx modesize;
23968 /* If we do not have vector value to copy, we must reduce size. */
23970 {
23972 {
23977 }
23978 else
23980 }
23981 else
23982 {
23983 /* Choose appropriate vector mode. */
23989 }
23994 {
23997 else
23998 {
24001 }
24003 }
24009 {
24013 }
24015 {
24018 else
24019 {
24022 }
24024 }
24030 }
24032 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24033 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24034 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24035 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24036 DONE_LABEL is a label after the whole copying sequence. The label is created
24037 on demand if *DONE_LABEL is NULL.
24038 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24039 bounds after the initial copies.
24041 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24042 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24043 we will dispatch to a library call for large blocks.
24045 In pseudocode we do:
24047 if (COUNT < SIZE)
24048 {
24049 Assume that SIZE is 4. Bigger sizes are handled analogously
24050 if (COUNT & 4)
24051 {
24052 copy 4 bytes from SRCPTR to DESTPTR
24053 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24054 goto done_label
24055 }
24056 if (!COUNT)
24057 goto done_label;
24058 copy 1 byte from SRCPTR to DESTPTR
24059 if (COUNT & 2)
24060 {
24061 copy 2 bytes from SRCPTR to DESTPTR
24062 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24063 }
24064 }
24065 else
24066 {
24067 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24068 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24070 OLD_DESPTR = DESTPTR;
24071 Align DESTPTR up to DESIRED_ALIGN
24072 SRCPTR += DESTPTR - OLD_DESTPTR
24073 COUNT -= DEST_PTR - OLD_DESTPTR
24074 if (DYNAMIC_CHECK)
24075 Round COUNT down to multiple of SIZE
24076 << optional caller supplied zero size guard is here >>
24077 << optional caller suppplied dynamic check is here >>
24078 << caller supplied main copy loop is here >>
24079 }
24080 done_label:
24081 */
24082 static void
24085 machine_mode mode,
24095 {
24098 rtx modesize;
24100 rtx mode_value;
24102 /* Chose proper value to copy. */
24105 else
24109 /* See if block is big or small, handle small blocks. */
24111 {
24122 /* Handle sizes > 3. */
24129 /* Nothing to copy? Jump to DONE_LABEL if so */
24133 /* Do a byte copy. */
24137 else
24138 {
24141 }
24143 /* Handle sizes 2 and 3. */
24150 else
24151 {
24156 }
24162 }
24163 else
24167 /* Start memcpy for COUNT >= SIZE. */
24169 {
24172 }
24174 /* Copy first desired_align bytes. */
24180 {
24183 else
24184 {
24187 }
24190 }
24193 /* Copy last SIZE bytes. */
24200 else
24201 {
24207 }
24209 {
24213 else
24214 {
24217 }
24218 }
24220 /* Align destination. */
24222 {
24226 /* Align destptr up, place it to new register. */
24233 /* See how many bytes we skipped. */
24237 /* Adjust srcptr and count. */
24243 /* We copied at most size + prolog_size. */
24246 else
24249 /* Our loops always round down the bock size, but for dispatch to library
24250 we need precise value. */
24254 }
24255 else
24256 {
24258 /* Decrease count, so we won't end up copying last word twice. */
24262 else
24266 }
24267 }
24270 /* This function is like the previous one, except here we know how many bytes
24271 need to be copied. That allows us to update alignment not only of DST, which
24272 is returned, but also of SRC, which is passed as a pointer for that
24273 reason. */
24274 static rtx
24279 {
24287 {
24291 }
24296 {
24298 {
24300 {
24303 else
24305 }
24306 else
24309 }
24310 }
24317 {
24323 {
24326 {
24330 }
24335 }
24339 }
24342 }
24344 /* Return true if ALG can be used in current context.
24345 Assume we expand memset if MEMSET is true. */
24346 static bool
24348 {
24353 /* Algorithms using the rep prefix want at least edi and ecx;
24354 additionally, memset wants eax and memcpy wants esi. Don't
24355 consider such algorithms if the user has appropriated those
24356 registers for their own purposes. */
24363 }
24365 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24366 static enum stringop_alg
24370 {
24381 /* Even if the string operation call is cold, we still might spend a lot
24382 of time processing large blocks. */
24388 else
24394 else
24397 /* See maximal size for user defined algorithm. */
24399 {
24406 }
24408 /* If expected size is not known but max size is small enough
24409 so inline version is a win, set expected size into
24410 the range. */
24415 /* If user specified the algorithm, honnor it if possible. */
24419 /* rep; movq or rep; movl is the smallest variant. */
24421 {
24426 else
24429 }
24430 /* Very tiny blocks are best handled via the loop, REP is expensive to
24431 setup. */
24435 {
24439 {
24440 /* We get here if the algorithms that were not libcall-based
24441 were rep-prefix based and we are unable to use rep prefixes
24442 based on global register usage. Break out of the loop and
24443 use the heuristic below. */
24447 {
24451 {
24454 }
24455 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24456 last non-libcall inline algorithm. */
24458 {
24459 /* When the current size is best to be copied by a libcall,
24460 but we are still forced to inline, run the heuristic below
24461 that will pick code for medium sized blocks. */
24463 {
24466 }
24469 }
24471 {
24474 }
24475 }
24476 }
24477 }
24478 /* When asked to inline the call anyway, try to pick meaningful choice.
24479 We look for maximal size of block that is faster to copy by hand and
24480 take blocks of at most of that size guessing that average size will
24481 be roughly half of the block.
24483 If this turns out to be bad, we might simply specify the preferred
24484 choice in ix86_costs. */
24488 {
24491 /* If there aren't any usable algorithms, then recursing on
24492 smaller sizes isn't going to find anything. Just return the
24493 simple byte-at-a-time copy loop. */
24495 {
24496 /* Pick something reasonable. */
24500 }
24510 }
24513 }
24515 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24516 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24517 static int
24521 machine_mode move_mode)
24522 {
24533 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24534 copying whole cacheline at once. */
24547 }
24550 /* Helper function for memcpy. For QImode value 0xXY produce
24551 0xXYXYXYXY of wide specified by MODE. This is essentially
24552 a * 0x10101010, but we can do slightly better than
24553 synth_mult by unwinding the sequence by hand on CPUs with
24554 slow multiply. */
24555 static rtx
24557 {
24559 rtx tmp;
24566 {
24574 }
24583 nops--;
24588 {
24592 OPTAB_DIRECT);
24593 }
24594 else
24595 {
24601 else
24603 else
24604 {
24607 reg =
24609 }
24619 }
24620 }
24622 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24623 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24624 alignment from ALIGN to DESIRED_ALIGN. */
24625 static rtx
24628 {
24629 rtx promoted_val;
24638 else
24642 }
24644 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24645 operations when profitable. The code depends upon architecture, block size
24646 and alignment, but always has one of the following overall structures:
24648 Aligned move sequence:
24650 1) Prologue guard: Conditional that jumps up to epilogues for small
24651 blocks that can be handled by epilogue alone. This is faster
24652 but also needed for correctness, since prologue assume the block
24653 is larger than the desired alignment.
24655 Optional dynamic check for size and libcall for large
24656 blocks is emitted here too, with -minline-stringops-dynamically.
24658 2) Prologue: copy first few bytes in order to get destination
24659 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24660 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24661 copied. We emit either a jump tree on power of two sized
24662 blocks, or a byte loop.
24664 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24665 with specified algorithm.
24667 4) Epilogue: code copying tail of the block that is too small to be
24668 handled by main body (or up to size guarded by prologue guard).
24670 Misaligned move sequence
24672 1) missaligned move prologue/epilogue containing:
24673 a) Prologue handling small memory blocks and jumping to done_label
24674 (skipped if blocks are known to be large enough)
24675 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24676 needed by single possibly misaligned move
24677 (skipped if alignment is not needed)
24678 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24680 2) Zero size guard dispatching to done_label, if needed
24682 3) dispatch to library call, if needed,
24684 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24685 with specified algorithm. */
24686 bool
24692 {
24693 rtx destreg;
24696 rtx tmp;
24712 /* TODO: Once value ranges are available, fill in proper data. */
24720 /* i386 can do misaligned access on reasonably increased cost. */
24724 /* ALIGN is the minimum of destination and source alignment, but we care here
24725 just about destination alignment. */
24731 {
24734 /* When COUNT is 0, there is nothing to do. */
24737 }
24738 else
24739 {
24748 }
24750 /* Make sure we don't need to care about overflow later on. */
24754 /* Step 0: Decide on preferred algorithm, desired alignment and
24755 size of chunks to be copied by main loop. */
24757 issetmem,
24764 /* For now vector-version of memset is generated only for memory zeroing, as
24765 creating of promoted vector value is very cheap in this case. */
24778 {
24797 /* Find the widest supported mode. */
24803 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24804 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24806 {
24811 }
24823 }
24831 /* Step 1: Prologue guard. */
24833 /* Alignment code needs count to be in register. */
24835 {
24838 {
24839 align_bytes
24843 else
24845 }
24848 }
24851 /* Misaligned move sequences handle both prologue and epilogue at once.
24852 Default code generation results in a smaller code for large alignments
24853 and also avoids redundant job when sizes are known precisely. */
24854 misaligned_prologue_used
24855 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24861 /* Do the cheap promotion to allow better CSE across the
24862 main loop and epilogue (ie one load of the big constant in the
24863 front of all code.
24864 For now the misaligned move sequences do not have fast path
24865 without broadcasting. */
24867 {
24869 {
24875 }
24876 else
24877 {
24880 }
24881 }
24882 /* Misaligned move sequences handles both prologues and epilogues at once.
24883 Default code generation results in smaller code for large alignments and
24884 also avoids redundant job when sizes are known precisely. */
24886 {
24887 /* Misaligned move prologue handled small blocks by itself. */
24888 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24893 desired_align < align
24902 {
24903 /* It is possible that we copied enough so the main loop will not
24904 execute. */
24914 else
24916 }
24917 }
24918 /* Ensure that alignment prologue won't copy past end of block. */
24920 {
24922 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24923 Make sure it is power of 2. */
24926 /* To improve performance of small blocks, we jump around the VAL
24927 promoting mode. This mean that if the promoted VAL is not constant,
24928 we might not use it in the epilogue and have to use byte
24929 loop variant. */
24934 {
24935 /* If main algorithm works on QImode, no epilogue is needed.
24936 For small sizes just don't align anything. */
24939 else
24941 }
24944 {
24951 else
24953 }
24954 }
24956 /* Emit code to decide on runtime whether library call or inline should be
24957 used. */
24959 {
24961 {
24963 {
24967 }
24968 }
24969 else
24970 {
24980 else
24984 }
24985 }
24987 /* Step 2: Alignment prologue. */
24988 /* Do the expensive promotion once we branched off the small blocks. */
24994 {
24996 {
24997 /* Except for the first move in prologue, we no longer know
24998 constant offset in aliasing info. It don't seems to worth
24999 the pain to maintain it for the first move, so throw away
25000 the info early. */
25007 issetmem);
25008 /* At most desired_align - align bytes are copied. */
25011 else
25013 }
25014 else
25015 {
25016 /* If we know how many bytes need to be stored before dst is
25017 sufficiently aligned, maintain aliasing info accurately. */
25019 srcreg,
25020 promoted_val,
25021 vec_promoted_val,
25022 desired_align,
25023 align_bytes,
25024 issetmem);
25031 }
25033 && !min_size
25038 {
25039 /* It is possible that we copied enough so the main loop will not
25040 execute. */
25050 else
25052 }
25053 }
25055 {
25062 }
25066 /* Step 3: Main loop. */
25069 {
25092 }
25093 /* Adjust properly the offset of src and dest memory for aliasing. */
25095 {
25101 }
25102 else
25103 {
25107 }
25109 /* Step 4: Epilogue to copy the remaining bytes. */
25110 epilogue:
25112 {
25113 /* When the main loop is done, COUNT_EXP might hold original count,
25114 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25115 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25116 bytes. Compensate if needed. */
25119 {
25120 tmp =
25123 OPTAB_DIRECT);
25126 }
25129 }
25132 {
25135 epilogue_size_needed);
25136 else
25137 {
25141 epilogue_size_needed);
25142 else
25144 epilogue_size_needed);
25145 }
25146 }
25150 }
25153 /* Expand the appropriate insns for doing strlen if not just doing
25154 repnz; scasb
25156 out = result, initialized with the start address
25157 align_rtx = alignment of the address.
25158 scratch = scratch register, initialized with the startaddress when
25159 not aligned, otherwise undefined
25161 This is just the body. It needs the initializations mentioned above and
25162 some address computing at the end. These things are done in i386.md. */
25164 static void
25166 {
25168 rtx tmp;
25173 rtx mem;
25176 rtx cmp;
25182 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25184 /* Is there a known alignment and is it less than 4? */
25186 {
25189 /* Is there a known alignment and is it not 2? */
25191 {
25195 /* Leave just the 3 lower bits. */
25205 }
25206 else
25207 {
25208 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25209 check if is aligned to 4 - byte. */
25216 }
25220 /* Now compare the bytes. */
25222 /* Compare the first n unaligned byte on a byte per byte basis. */
25226 /* Increment the address. */
25229 /* Not needed with an alignment of 2 */
25231 {
25235 end_0_label);
25240 }
25243 end_0_label);
25246 }
25248 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25249 align this loop. It gives only huge programs, but does not help to
25250 speed up. */
25257 /* This formula yields a nonzero result iff one of the bytes is zero.
25258 This saves three branches inside loop and many cycles. */
25266 align_4_label);
25269 {
25275 /* If zero is not in the first two bytes, move two bytes forward. */
25281 reg,
25282 tmpreg)));
25283 /* Emit lea manually to avoid clobbering of flags. */
25291 reg2,
25292 out)));
25293 }
25294 else
25295 {
25297 /* Is zero in the first two bytes? */
25304 pc_rtx);
25308 /* Not in the first two. Move two bytes forward. */
25314 }
25316 /* Avoid branch in fixing the byte. */
25324 }
25326 /* Expand strlen. */
25328 bool
25330 {
25333 /* The generic case of strlen expander is long. Avoid it's
25334 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25337 && !TARGET_INLINE_ALL_STRINGOPS
25347 {
25348 /* Well it seems that some optimizer does not combine a call like
25349 foo(strlen(bar), strlen(bar));
25350 when the move and the subtraction is done here. It does calculate
25351 the length just once when these instructions are done inside of
25352 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25353 often used and I use one fewer register for the lifetime of
25354 output_strlen_unroll() this is better. */
25360 /* strlensi_unroll_1 returns the address of the zero at the end of
25361 the string, like memchr(), so compute the length by subtracting
25362 the start address. */
25364 }
25365 else
25366 {
25367 rtx unspec;
25369 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25382 /* If .md starts supporting :P, this can be done in .md. */
25388 }
25390 }
25392 /* For given symbol (function) construct code to compute address of it's PLT
25393 entry in large x86-64 PIC model. */
25394 static rtx
25396 {
25409 }
25411 rtx
25413 rtx callarg2,
25415 {
25425 {
25426 #if TARGET_MACHO
25429 #endif
25430 }
25431 else
25432 {
25433 /* Static functions and indirect calls don't need the pic register. */
25435 && (!TARGET_64BIT
25440 {
25444 pic_offset_table_rtx);
25445 }
25446 }
25449 {
25453 }
25456 && !TARGET_PECOFF
25464 {
25467 }
25472 {
25473 /* We should add bounds as destination register in case
25474 pointer with bounds may be returned. */
25476 {
25481 }
25484 }
25488 {
25492 }
25496 {
25497 int const cregs_size
25502 {
25507 }
25508 }
25517 }
25519 /* Output the assembly for a call instruction. */
25523 {
25529 {
25532 /* SEH epilogue detection requires the indirect branch case
25533 to include REX.W. */
25536 else
25541 }
25543 /* SEH unwinding can require an extra nop to be emitted in several
25544 circumstances. Determine if we have one of those. */
25546 {
25550 {
25551 /* If we get to another real insn, we don't need the nop. */
25555 /* If we get to the epilogue note, prevent a catch region from
25556 being adjacent to the standard epilogue sequence. If non-
25557 call-exceptions, we'll have done this during epilogue emission. */
25559 && !flag_non_call_exceptions
25561 {
25564 }
25565 }
25567 /* If we didn't find a real insn following the call, prevent the
25568 unwinder from looking into the next function. */
25571 }
25575 else
25584 }
25585 \f
25586 /* Clear stack slot assignments remembered from previous functions.
25587 This is called from INIT_EXPANDERS once before RTL is emitted for each
25588 function. */
25592 {
25600 }
25602 /* Return a MEM corresponding to a stack slot with mode MODE.
25603 Allocate a new slot if necessary.
25605 The RTL for a function can have several slots available: N is
25606 which slot to use. */
25608 rtx
25610 {
25627 }
25629 static void
25631 {
25637 }
25638 \f
25639 /* Check whether x86 address PARTS is a pc-relative address. */
25641 static bool
25643 {
25651 {
25653 {
25670 }
25671 }
25673 }
25675 /* Calculate the length of the memory address in the instruction encoding.
25676 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25677 or other prefixes. We never generate addr32 prefix for LEA insn. */
25679 int
25681 {
25698 /* If this is not LEA instruction, add the length of addr32 prefix. */
25703 len++;
25717 /* Rule of thumb:
25718 - esp as the base always wants an index,
25719 - ebp as the base always wants a displacement,
25720 - r12 as the base always wants an index,
25721 - r13 as the base always wants a displacement. */
25723 /* Register Indirect. */
25725 {
25726 /* esp (for its index) and ebp (for its displacement) need
25727 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25728 code. */
25735 len++;
25736 }
25738 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25739 is not disp32, but disp32(%rip), so for disp32
25740 SIB byte is needed, unless print_operand_address
25741 optimizes it into disp32(%rip) or (%rip) is implied
25742 by UNSPEC. */
25744 {
25747 len++;
25748 }
25749 else
25750 {
25751 /* Find the length of the displacement constant. */
25753 {
25756 else
25758 }
25759 /* ebp always wants a displacement. Similarly r13. */
25761 len++;
25763 /* An index requires the two-byte modrm form.... */
25765 /* ...like esp (or r12), which always wants an index. */
25769 len++;
25770 }
25773 }
25775 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25776 is set, expect that insn have 8bit immediate alternative. */
25777 int
25779 {
25785 {
25790 {
25793 {
25805 }
25807 {
25810 }
25811 }
25813 {
25823 /* Immediates for DImode instructions are encoded
25824 as 32bit sign extended values. */
25830 }
25831 }
25833 }
25835 /* Compute default value for "length_address" attribute. */
25836 int
25838 {
25842 {
25853 }
25858 {
25861 {
25866 constraints++;
25869 ;
25870 /* Skip ignored operands. */
25873 }
25875 }
25877 }
25879 /* Compute default value for "length_vex" attribute. It includes
25880 2 or 3 byte VEX prefix and 1 opcode byte. */
25882 int
25885 {
25888 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25889 byte VEX prefix. */
25893 /* We can always use 2 byte VEX prefix in 32bit. */
25901 {
25902 /* REX.W bit uses 3 byte VEX prefix. */
25906 }
25907 else
25908 {
25909 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25913 }
25916 }
25917 \f
25918 /* Return the maximum number of instructions a cpu can issue. */
25920 static int
25922 {
25924 {
25955 }
25956 }
25958 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25959 by DEP_INSN and nothing set by DEP_INSN. */
25961 static bool
25963 {
25966 /* Simplify the test for uninteresting insns. */
25974 {
25977 }
25982 {
25985 }
25986 else
25992 /* This test is true if the dependent insn reads the flags but
25993 not any other potentially set register. */
26001 }
26003 /* Return true iff USE_INSN has a memory address with operands set by
26004 SET_INSN. */
26006 bool
26008 {
26013 {
26016 }
26018 }
26020 /* Helper function for exact_store_load_dependency.
26021 Return true if addr is found in insn. */
26022 static bool
26024 {
26031 {
26037 CASE_CONST_ANY:
26046 }
26050 {
26052 {
26062 }
26063 }
26065 }
26067 /* Return true if there exists exact dependency for store & load, i.e.
26068 the same memory address is used in them. */
26069 static bool
26071 {
26085 }
26087 static int
26089 {
26095 /* Anti and output dependencies have zero cost on all CPUs. */
26101 /* If we can't recognize the insns, we can't really do anything. */
26109 {
26111 /* Address Generation Interlock adds a cycle of latency. */
26113 {
26124 }
26128 /* ??? Compares pair with jump/setcc. */
26132 /* Floating point stores require value to be ready one cycle earlier. */
26140 /* INT->FP conversion is expensive. */
26144 /* There is one cycle extra latency between an FP op and a store. */
26154 /* Show ability of reorder buffer to hide latency of load by executing
26155 in parallel with previous instruction in case
26156 previous instruction is not needed to compute the address. */
26159 {
26160 /* Claim moves to take one cycle, as core can issue one load
26161 at time and the next load can start cycle later. */
26166 cost--;
26167 }
26171 /* The esp dependency is resolved before
26172 the instruction is really finished. */
26177 /* INT->FP conversion is expensive. */
26183 /* Show ability of reorder buffer to hide latency of load by executing
26184 in parallel with previous instruction in case
26185 previous instruction is not needed to compute the address. */
26188 {
26189 /* Claim moves to take one cycle, as core can issue one load
26190 at time and the next load can start cycle later. */
26196 else
26198 }
26209 /* Stack engine allows to execute push&pop instructions in parall. */
26213 /* FALLTHRU */
26219 /* Show ability of reorder buffer to hide latency of load by executing
26220 in parallel with previous instruction in case
26221 previous instruction is not needed to compute the address. */
26224 {
26228 /* Because of the difference between the length of integer and
26229 floating unit pipeline preparation stages, the memory operands
26230 for floating point are cheaper.
26232 ??? For Athlon it the difference is most probably 2. */
26235 else
26240 else
26242 }
26249 /* Stack engine allows to execute push&pop instructions in parall. */
26256 /* Show ability of reorder buffer to hide latency of load by executing
26257 in parallel with previous instruction in case
26258 previous instruction is not needed to compute the address. */
26261 {
26264 else
26266 }
26274 /* Increase cost of integer loads. */
26277 {
26280 {
26283 else
26284 {
26285 /* Increase cost of ld/st for short int types only
26286 because of store forwarding issue. */
26290 {
26291 /* Increase cost of store/load insn if exact
26292 dependence exists and it is load insn. */
26297 }
26298 }
26299 }
26300 }
26304 }
26307 }
26309 /* How many alternative schedules to try. This should be as wide as the
26310 scheduling freedom in the DFA, but no wider. Making this value too
26311 large results extra work for the scheduler. */
26313 static int
26315 {
26317 {
26329 /* We use lookahead value 4 for BD both before and after reload
26330 schedules. Plan is to have value 8 included for O3. */
26340 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26341 as many instructions can be executed on a cycle, i.e.,
26342 issue_rate. I wonder why tuning for many CPUs does not do this. */
26345 /* Don't use lookahead for pre-reload schedule to save compile time. */
26350 }
26351 }
26353 /* Return true if target platform supports macro-fusion. */
26355 static bool
26357 {
26359 }
26361 /* Check whether current microarchitecture support macro fusion
26362 for insn pair "CONDGEN + CONDJMP". Refer to
26363 "Intel Architectures Optimization Reference Manual". */
26365 static bool
26367 {
26388 {
26393 {
26397 else
26399 }
26400 }
26407 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26408 supported. */
26415 /* No fusion for RIP-relative address. */
26422 ix86_address parts;
26428 }
26433 /* Check whether conditional jump use Sign or Overflow Flags. */
26441 /* Return true for TYPE_TEST and TYPE_ICMP. */
26446 /* The following is the case that macro-fusion for alu + jmp. */
26450 /* No fusion for alu op with memory destination operand. */
26455 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26456 supported. */
26465 }
26467 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26468 execution. It is applied if
26469 (1) IMUL instruction is on the top of list;
26470 (2) There exists the only producer of independent IMUL instruction in
26471 ready list.
26472 Return index of IMUL producer if it was found and -1 otherwise. */
26473 static int
26475 {
26478 sd_iterator_def sd_it;
26479 dep_t dep;
26486 /* Check that IMUL instruction is on the top of ready list. */
26495 /* Search for producer of independent IMUL instruction. */
26497 {
26501 /* Skip IMUL instruction. */
26511 {
26512 rtx con;
26523 {
26524 sd_iterator_def sd_it1;
26525 dep_t dep1;
26526 /* Check if there is no other dependee for IMUL. */
26529 {
26530 rtx pro;
26536 }
26539 }
26540 }
26543 }
26545 }
26547 /* Try to find the best candidate on the top of ready list if two insns
26548 have the same priority - candidate is best if its dependees were
26549 scheduled earlier. Applied for Silvermont only.
26550 Return true if top 2 insns must be interchanged. */
26551 static bool
26553 {
26556 rtx set;
26557 sd_iterator_def sd_it;
26558 dep_t dep;
26561 #define INSN_TICK(INSN) (HID (INSN)->tick)
26582 {
26585 /* Determine winner more precise. */
26587 {
26588 rtx pro;
26594 }
26596 {
26597 rtx pro;
26603 }
26606 {
26607 /* Determine winner - load must win. */
26613 }
26615 }
26617 #undef INSN_TICK
26618 }
26620 /* Perform possible reodering of ready list for Atom/Silvermont only.
26621 Return issue rate. */
26622 static int
26625 {
26632 /* Set up issue rate. */
26635 /* Do reodering for BONNELL/SILVERMONT only. */
26639 /* Nothing to do if ready list contains only 1 instruction. */
26643 /* Do reodering for post-reload scheduler only. */
26648 {
26653 /* Put IMUL producer (ready[index]) at the top of ready list. */
26659 }
26661 {
26665 /* Swap 2 top elements of ready list. */
26669 }
26671 }
26673 static bool
26676 /* Returns true if lhs of insn is HW function argument register and set up
26677 is_spilled to true if it is likely spilled HW register. */
26678 static bool
26680 {
26681 rtx dst;
26685 /* Call instructions are not movable, ignore it. */
26696 {
26697 /* Is it likely spilled HW register? */
26702 }
26704 }
26706 /* Add output dependencies for chain of function adjacent arguments if only
26707 there is a move to likely spilled HW register. Return first argument
26708 if at least one dependence was added or NULL otherwise. */
26711 {
26719 /* Find nearest to call argument passing instruction. */
26721 {
26730 }
26734 {
26741 {
26744 }
26746 {
26747 /* Add output depdendence between two function arguments if chain
26748 of output arguments contains likely spilled HW registers. */
26752 }
26753 else
26755 }
26759 }
26761 /* Add output or anti dependency from insn to first_arg to restrict its code
26762 motion. */
26763 static void
26765 {
26766 rtx set;
26767 rtx tmp;
26774 {
26775 /* Add output dependency to the first function argument. */
26778 }
26779 /* Add anti dependency. */
26781 }
26783 /* Avoid cross block motion of function argument through adding dependency
26784 from the first non-jump instruction in bb. */
26785 static void
26787 {
26791 {
26793 {
26796 {
26799 }
26800 }
26804 }
26805 }
26807 /* Hook for pre-reload schedule - avoid motion of function arguments
26808 passed in likely spilled HW registers. */
26809 static void
26811 {
26820 {
26823 {
26824 /* Add dependee for first argument to predecessors if only
26825 region contains more than one block. */
26829 /* Skip trivial regions and region head blocks that can have
26830 predecessors outside of region. */
26832 {
26833 edge e;
26834 edge_iterator ei;
26836 /* Regions are SCCs with the exception of selective
26837 scheduling with pipelining of outer blocks enabled.
26838 So also check that immediate predecessors of a non-head
26839 block are in the same region. */
26841 {
26842 /* Avoid creating of loop-carried dependencies through
26843 using topological ordering in the region. */
26847 }
26848 }
26852 }
26853 }
26856 }
26858 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26859 HW registers to maximum, to schedule them at soon as possible. These are
26860 moves from function argument registers at the top of the function entry
26861 and moves from function return value registers after call. */
26862 static int
26864 {
26865 rtx set;
26875 {
26882 }
26885 }
26887 /* Model decoder of Core 2/i7.
26888 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26889 track the instruction fetch block boundaries and make sure that long
26890 (9+ bytes) instructions are assigned to D0. */
26892 /* Maximum length of an insn that can be handled by
26893 a secondary decoder unit. '8' for Core 2/i7. */
26896 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26897 '16' for Core 2/i7. */
26900 /* Maximum number of instructions decoder can handle per cycle.
26901 '6' for Core 2/i7. */
26905 ix86_first_cycle_multipass_data_t;
26907 const_ix86_first_cycle_multipass_data_t;
26909 /* A variable to store target state across calls to max_issue within
26910 one cycle. */
26914 /* Initialize DATA. */
26915 static void
26917 {
26918 ix86_first_cycle_multipass_data_t data
26925 }
26927 /* Advancing the cycle; reset ifetch block counts. */
26928 static void
26930 {
26937 }
26941 /* Filter out insns from ready_try that the core will not be able to issue
26942 on current cycle due to decoder. */
26943 static void
26944 core2i7_first_cycle_multipass_filter_ready_try
26947 {
26949 {
26960 (!first_cycle_insn_p
26962 /* ... or it would not fit into the ifetch block ... */
26964 /* ... or the decoder is full already ... */
26966 /* ... mask the insn out. */
26967 {
26972 }
26973 }
26974 }
26976 /* Prepare for a new round of multipass lookahead scheduling. */
26977 static void
26981 {
26982 ix86_first_cycle_multipass_data_t data
26984 const_ix86_first_cycle_multipass_data_t prev_data
26987 /* Restore the state from the end of the previous round. */
26991 /* Filter instructions that cannot be issued on current cycle due to
26992 decoder restrictions. */
26994 first_cycle_insn_p);
26995 }
26997 /* INSN is being issued in current solution. Account for its impact on
26998 the decoder model. */
26999 static void
27003 {
27004 ix86_first_cycle_multipass_data_t data
27006 const_ix86_first_cycle_multipass_data_t prev_data
27016 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27018 {
27021 }
27023 {
27027 }
27030 /* Filter out insns from ready_try that the core will not be able to issue
27031 on current cycle due to decoder. */
27034 }
27036 /* Revert the effect on ready_try. */
27037 static void
27041 {
27042 const_ix86_first_cycle_multipass_data_t data
27045 sbitmap_iterator sbi;
27049 {
27051 }
27052 }
27054 /* Save the result of multipass lookahead scheduling for the next round. */
27055 static void
27057 {
27058 const_ix86_first_cycle_multipass_data_t data
27060 ix86_first_cycle_multipass_data_t next_data
27064 {
27067 }
27068 }
27070 /* Deallocate target data. */
27071 static void
27073 {
27074 ix86_first_cycle_multipass_data_t data
27078 {
27082 }
27083 }
27085 /* Prepare for scheduling pass. */
27086 static void
27088 {
27089 /* Install scheduling hooks for current CPU. Some of these hooks are used
27090 in time-critical parts of the scheduler, so we only set them up when
27091 they are actually used. */
27093 {
27098 /* Do not perform multipass scheduling for pre-reload schedule
27099 to save compile time. */
27101 {
27117 /* Set decoder parameters. */
27122 }
27123 /* ... Fall through ... */
27133 }
27134 }
27136 \f
27137 /* Compute the alignment given to a constant that is being placed in memory.
27138 EXP is the constant and ALIGN is the alignment that the object would
27139 ordinarily have.
27140 The value of this function is used instead of that alignment to align
27141 the object. */
27143 int
27145 {
27148 {
27153 }
27159 }
27161 /* Compute the alignment for a static variable.
27162 TYPE is the data type, and ALIGN is the alignment that
27163 the object would ordinarily have. The value of this function is used
27164 instead of that alignment to align the object. */
27166 int
27168 {
27169 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27170 for symbols from other compilation units or symbols that don't need
27171 to bind locally. In order to preserve some ABI compatibility with
27172 those compilers, ensure we don't decrease alignment from what we
27173 used to assume. */
27175 int max_align_compat
27178 /* A data structure, equal or greater than the size of a cache line
27179 (64 bytes in the Pentium 4 and other recent Intel processors, including
27180 processors based on Intel Core microarchitecture) should be aligned
27181 so that its base address is a multiple of a cache line size. */
27183 int max_align
27193 {
27200 }
27202 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27203 to 16byte boundary. */
27205 {
27212 }
27218 {
27223 }
27225 {
27232 }
27237 {
27242 }
27245 {
27250 }
27253 }
27255 /* Compute the alignment for a local variable or a stack slot. EXP is
27256 the data type or decl itself, MODE is the widest mode available and
27257 ALIGN is the alignment that the object would ordinarily have. The
27258 value of this macro is used instead of that alignment to align the
27259 object. */
27261 unsigned int
27264 {
27268 {
27271 }
27272 else
27273 {
27276 }
27278 /* Don't do dynamic stack realignment for long long objects with
27279 -mpreferred-stack-boundary=2. */
27288 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27289 register in MODE. We will return the largest alignment of XF
27290 and DF. */
27292 {
27296 }
27298 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27299 to 16byte boundary. Exact wording is:
27301 An array uses the same alignment as its elements, except that a local or
27302 global array variable of length at least 16 bytes or
27303 a C99 variable-length array variable always has alignment of at least 16 bytes.
27305 This was added to allow use of aligned SSE instructions at arrays. This
27306 rule is meant for static storage (where compiler can not do the analysis
27307 by itself). We follow it for automatic variables only when convenient.
27308 We fully control everything in the function compiled and functions from
27309 other unit can not rely on the alignment.
27311 Exclude va_list type. It is the common case of local array where
27312 we can not benefit from the alignment.
27314 TODO: Probably one should optimize for size only when var is not escaping. */
27317 {
27327 }
27329 {
27334 }
27336 {
27342 }
27347 {
27352 }
27355 {
27361 }
27363 }
27365 /* Compute the minimum required alignment for dynamic stack realignment
27366 purposes for a local variable, parameter or a stack slot. EXP is
27367 the data type or decl itself, MODE is its mode and ALIGN is the
27368 alignment that the object would ordinarily have. */
27370 unsigned int
27373 {
27377 {
27380 }
27381 else
27382 {
27385 }
27390 /* Don't do dynamic stack realignment for long long objects with
27391 -mpreferred-stack-boundary=2. */
27398 }
27399 \f
27400 /* Find a location for the static chain incoming to a nested function.
27401 This is a register, unless all free registers are used by arguments. */
27403 static rtx
27405 {
27408 /* While this function won't be called by the middle-end when a static
27409 chain isn't needed, it's also used throughout the backend so it's
27410 easiest to keep this check centralized. */
27415 {
27416 /* We always use R10 in 64-bit mode. */
27418 }
27419 else
27420 {
27424 /* By default in 32-bit mode we use ECX to pass the static chain. */
27428 {
27431 }
27432 else
27433 {
27436 }
27440 {
27441 /* Fastcall functions use ecx/edx for arguments, which leaves
27442 us with EAX for the static chain.
27443 Thiscall functions use ecx for arguments, which also
27444 leaves us with EAX for the static chain. */
27446 }
27448 {
27449 /* Thiscall functions use ecx for arguments, which leaves
27450 us with EAX and EDX for the static chain.
27451 We are using for abi-compatibility EAX. */
27453 }
27455 {
27456 /* For regparm 3, we have no free call-clobbered registers in
27457 which to store the static chain. In order to implement this,
27458 we have the trampoline push the static chain to the stack.
27459 However, we can't push a value below the return address when
27460 we call the nested function directly, so we have to use an
27461 alternate entry point. For this we use ESI, and have the
27462 alternate entry point push ESI, so that things appear the
27463 same once we're executing the nested function. */
27465 {
27471 }
27473 }
27474 }
27477 }
27479 /* Emit RTL insns to initialize the variable parts of a trampoline.
27480 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27481 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27482 to be passed to the target function. */
27484 static void
27486 {
27494 {
27497 /* Load the function address to r11. Try to load address using
27498 the shorter movl instead of movabs. We may want to support
27499 movq for kernel mode, but kernel does not use trampolines at
27500 the moment. FNADDR is a 32bit address and may not be in
27501 DImode when ptr_mode == SImode. Always use movl in this
27502 case. */
27505 {
27514 }
27515 else
27516 {
27523 }
27525 /* Load static chain using movabs to r10. Use the shorter movl
27526 instead of movabs when ptr_mode == SImode. */
27528 {
27531 }
27532 else
27533 {
27536 }
27545 /* Jump to r11; the last (unused) byte is a nop, only there to
27546 pad the write out to a single 32-bit store. */
27550 }
27551 else
27552 {
27555 /* Depending on the static chain location, either load a register
27556 with a constant, or push the constant to the stack. All of the
27557 instructions are the same size. */
27560 {
27562 {
27569 }
27570 }
27571 else
27586 /* Compute offset from the end of the jmp to the target function.
27587 In the case in which the trampoline stores the static chain on
27588 the stack, we need to skip the first insn which pushes the
27589 (call-saved) register static chain; this push is 1 byte. */
27596 }
27600 #ifdef HAVE_ENABLE_EXECUTE_STACK
27601 #ifdef CHECK_EXECUTE_STACK_ENABLED
27603 #endif
27606 #endif
27607 }
27608 \f
27609 /* The following file contains several enumerations and data structures
27610 built from the definitions in i386-builtin-types.def. */
27614 /* Table for the ix86 builtin non-function types. */
27617 /* Retrieve an element from the above table, building some of
27618 the types lazily. */
27620 static tree
27622 {
27634 {
27635 machine_mode mode;
27642 }
27643 else
27644 {
27650 else
27658 }
27662 }
27664 /* Table for the ix86 builtin function types. */
27667 /* Retrieve an element from the above table, building some of
27668 the types lazily. */
27670 static tree
27672 {
27673 tree type;
27682 {
27690 {
27693 }
27696 }
27697 else
27698 {
27704 }
27708 }
27711 /* Codes for all the SSE/MMX builtins. */
27712 enum ix86_builtins
27713 {
27714 IX86_BUILTIN_ADDPS,
27715 IX86_BUILTIN_ADDSS,
27716 IX86_BUILTIN_DIVPS,
27717 IX86_BUILTIN_DIVSS,
27718 IX86_BUILTIN_MULPS,
27719 IX86_BUILTIN_MULSS,
27720 IX86_BUILTIN_SUBPS,
27721 IX86_BUILTIN_SUBSS,
27723 IX86_BUILTIN_CMPEQPS,
27724 IX86_BUILTIN_CMPLTPS,
27725 IX86_BUILTIN_CMPLEPS,
27726 IX86_BUILTIN_CMPGTPS,
27727 IX86_BUILTIN_CMPGEPS,
27728 IX86_BUILTIN_CMPNEQPS,
27729 IX86_BUILTIN_CMPNLTPS,
27730 IX86_BUILTIN_CMPNLEPS,
27731 IX86_BUILTIN_CMPNGTPS,
27732 IX86_BUILTIN_CMPNGEPS,
27733 IX86_BUILTIN_CMPORDPS,
27734 IX86_BUILTIN_CMPUNORDPS,
27735 IX86_BUILTIN_CMPEQSS,
27736 IX86_BUILTIN_CMPLTSS,
27737 IX86_BUILTIN_CMPLESS,
27738 IX86_BUILTIN_CMPNEQSS,
27739 IX86_BUILTIN_CMPNLTSS,
27740 IX86_BUILTIN_CMPNLESS,
27741 IX86_BUILTIN_CMPORDSS,
27742 IX86_BUILTIN_CMPUNORDSS,
27744 IX86_BUILTIN_COMIEQSS,
27745 IX86_BUILTIN_COMILTSS,
27746 IX86_BUILTIN_COMILESS,
27747 IX86_BUILTIN_COMIGTSS,
27748 IX86_BUILTIN_COMIGESS,
27749 IX86_BUILTIN_COMINEQSS,
27750 IX86_BUILTIN_UCOMIEQSS,
27751 IX86_BUILTIN_UCOMILTSS,
27752 IX86_BUILTIN_UCOMILESS,
27753 IX86_BUILTIN_UCOMIGTSS,
27754 IX86_BUILTIN_UCOMIGESS,
27755 IX86_BUILTIN_UCOMINEQSS,
27757 IX86_BUILTIN_CVTPI2PS,
27758 IX86_BUILTIN_CVTPS2PI,
27759 IX86_BUILTIN_CVTSI2SS,
27760 IX86_BUILTIN_CVTSI642SS,
27761 IX86_BUILTIN_CVTSS2SI,
27762 IX86_BUILTIN_CVTSS2SI64,
27763 IX86_BUILTIN_CVTTPS2PI,
27764 IX86_BUILTIN_CVTTSS2SI,
27765 IX86_BUILTIN_CVTTSS2SI64,
27767 IX86_BUILTIN_MAXPS,
27768 IX86_BUILTIN_MAXSS,
27769 IX86_BUILTIN_MINPS,
27770 IX86_BUILTIN_MINSS,
27772 IX86_BUILTIN_LOADUPS,
27773 IX86_BUILTIN_STOREUPS,
27774 IX86_BUILTIN_MOVSS,
27776 IX86_BUILTIN_MOVHLPS,
27777 IX86_BUILTIN_MOVLHPS,
27778 IX86_BUILTIN_LOADHPS,
27779 IX86_BUILTIN_LOADLPS,
27780 IX86_BUILTIN_STOREHPS,
27781 IX86_BUILTIN_STORELPS,
27783 IX86_BUILTIN_MASKMOVQ,
27784 IX86_BUILTIN_MOVMSKPS,
27785 IX86_BUILTIN_PMOVMSKB,
27787 IX86_BUILTIN_MOVNTPS,
27788 IX86_BUILTIN_MOVNTQ,
27790 IX86_BUILTIN_LOADDQU,
27791 IX86_BUILTIN_STOREDQU,
27793 IX86_BUILTIN_PACKSSWB,
27794 IX86_BUILTIN_PACKSSDW,
27795 IX86_BUILTIN_PACKUSWB,
27797 IX86_BUILTIN_PADDB,
27798 IX86_BUILTIN_PADDW,
27799 IX86_BUILTIN_PADDD,
27800 IX86_BUILTIN_PADDQ,
27801 IX86_BUILTIN_PADDSB,
27802 IX86_BUILTIN_PADDSW,
27803 IX86_BUILTIN_PADDUSB,
27804 IX86_BUILTIN_PADDUSW,
27805 IX86_BUILTIN_PSUBB,
27806 IX86_BUILTIN_PSUBW,
27807 IX86_BUILTIN_PSUBD,
27808 IX86_BUILTIN_PSUBQ,
27809 IX86_BUILTIN_PSUBSB,
27810 IX86_BUILTIN_PSUBSW,
27811 IX86_BUILTIN_PSUBUSB,
27812 IX86_BUILTIN_PSUBUSW,
27814 IX86_BUILTIN_PAND,
27815 IX86_BUILTIN_PANDN,
27816 IX86_BUILTIN_POR,
27817 IX86_BUILTIN_PXOR,
27819 IX86_BUILTIN_PAVGB,
27820 IX86_BUILTIN_PAVGW,
27822 IX86_BUILTIN_PCMPEQB,
27823 IX86_BUILTIN_PCMPEQW,
27824 IX86_BUILTIN_PCMPEQD,
27825 IX86_BUILTIN_PCMPGTB,
27826 IX86_BUILTIN_PCMPGTW,
27827 IX86_BUILTIN_PCMPGTD,
27829 IX86_BUILTIN_PMADDWD,
27831 IX86_BUILTIN_PMAXSW,
27832 IX86_BUILTIN_PMAXUB,
27833 IX86_BUILTIN_PMINSW,
27834 IX86_BUILTIN_PMINUB,
27836 IX86_BUILTIN_PMULHUW,
27837 IX86_BUILTIN_PMULHW,
27838 IX86_BUILTIN_PMULLW,
27840 IX86_BUILTIN_PSADBW,
27841 IX86_BUILTIN_PSHUFW,
27843 IX86_BUILTIN_PSLLW,
27844 IX86_BUILTIN_PSLLD,
27845 IX86_BUILTIN_PSLLQ,
27846 IX86_BUILTIN_PSRAW,
27847 IX86_BUILTIN_PSRAD,
27848 IX86_BUILTIN_PSRLW,
27849 IX86_BUILTIN_PSRLD,
27850 IX86_BUILTIN_PSRLQ,
27851 IX86_BUILTIN_PSLLWI,
27852 IX86_BUILTIN_PSLLDI,
27853 IX86_BUILTIN_PSLLQI,
27854 IX86_BUILTIN_PSRAWI,
27855 IX86_BUILTIN_PSRADI,
27856 IX86_BUILTIN_PSRLWI,
27857 IX86_BUILTIN_PSRLDI,
27858 IX86_BUILTIN_PSRLQI,
27860 IX86_BUILTIN_PUNPCKHBW,
27861 IX86_BUILTIN_PUNPCKHWD,
27862 IX86_BUILTIN_PUNPCKHDQ,
27863 IX86_BUILTIN_PUNPCKLBW,
27864 IX86_BUILTIN_PUNPCKLWD,
27865 IX86_BUILTIN_PUNPCKLDQ,
27867 IX86_BUILTIN_SHUFPS,
27869 IX86_BUILTIN_RCPPS,
27870 IX86_BUILTIN_RCPSS,
27871 IX86_BUILTIN_RSQRTPS,
27872 IX86_BUILTIN_RSQRTPS_NR,
27873 IX86_BUILTIN_RSQRTSS,
27874 IX86_BUILTIN_RSQRTF,
27875 IX86_BUILTIN_SQRTPS,
27876 IX86_BUILTIN_SQRTPS_NR,
27877 IX86_BUILTIN_SQRTSS,
27879 IX86_BUILTIN_UNPCKHPS,
27880 IX86_BUILTIN_UNPCKLPS,
27882 IX86_BUILTIN_ANDPS,
27883 IX86_BUILTIN_ANDNPS,
27884 IX86_BUILTIN_ORPS,
27885 IX86_BUILTIN_XORPS,
27887 IX86_BUILTIN_EMMS,
27888 IX86_BUILTIN_LDMXCSR,
27889 IX86_BUILTIN_STMXCSR,
27890 IX86_BUILTIN_SFENCE,
27892 IX86_BUILTIN_FXSAVE,
27893 IX86_BUILTIN_FXRSTOR,
27894 IX86_BUILTIN_FXSAVE64,
27895 IX86_BUILTIN_FXRSTOR64,
27897 IX86_BUILTIN_XSAVE,
27898 IX86_BUILTIN_XRSTOR,
27899 IX86_BUILTIN_XSAVE64,
27900 IX86_BUILTIN_XRSTOR64,
27902 IX86_BUILTIN_XSAVEOPT,
27903 IX86_BUILTIN_XSAVEOPT64,
27905 IX86_BUILTIN_XSAVEC,
27906 IX86_BUILTIN_XSAVEC64,
27908 IX86_BUILTIN_XSAVES,
27909 IX86_BUILTIN_XRSTORS,
27910 IX86_BUILTIN_XSAVES64,
27911 IX86_BUILTIN_XRSTORS64,
27913 /* 3DNow! Original */
27914 IX86_BUILTIN_FEMMS,
27915 IX86_BUILTIN_PAVGUSB,
27916 IX86_BUILTIN_PF2ID,
27917 IX86_BUILTIN_PFACC,
27918 IX86_BUILTIN_PFADD,
27919 IX86_BUILTIN_PFCMPEQ,
27920 IX86_BUILTIN_PFCMPGE,
27921 IX86_BUILTIN_PFCMPGT,
27922 IX86_BUILTIN_PFMAX,
27923 IX86_BUILTIN_PFMIN,
27924 IX86_BUILTIN_PFMUL,
27925 IX86_BUILTIN_PFRCP,
27926 IX86_BUILTIN_PFRCPIT1,
27927 IX86_BUILTIN_PFRCPIT2,
27928 IX86_BUILTIN_PFRSQIT1,
27929 IX86_BUILTIN_PFRSQRT,
27930 IX86_BUILTIN_PFSUB,
27931 IX86_BUILTIN_PFSUBR,
27932 IX86_BUILTIN_PI2FD,
27933 IX86_BUILTIN_PMULHRW,
27935 /* 3DNow! Athlon Extensions */
27936 IX86_BUILTIN_PF2IW,
27937 IX86_BUILTIN_PFNACC,
27938 IX86_BUILTIN_PFPNACC,
27939 IX86_BUILTIN_PI2FW,
27940 IX86_BUILTIN_PSWAPDSI,
27941 IX86_BUILTIN_PSWAPDSF,
27943 /* SSE2 */
27944 IX86_BUILTIN_ADDPD,
27945 IX86_BUILTIN_ADDSD,
27946 IX86_BUILTIN_DIVPD,
27947 IX86_BUILTIN_DIVSD,
27948 IX86_BUILTIN_MULPD,
27949 IX86_BUILTIN_MULSD,
27950 IX86_BUILTIN_SUBPD,
27951 IX86_BUILTIN_SUBSD,
27953 IX86_BUILTIN_CMPEQPD,
27954 IX86_BUILTIN_CMPLTPD,
27955 IX86_BUILTIN_CMPLEPD,
27956 IX86_BUILTIN_CMPGTPD,
27957 IX86_BUILTIN_CMPGEPD,
27958 IX86_BUILTIN_CMPNEQPD,
27959 IX86_BUILTIN_CMPNLTPD,
27960 IX86_BUILTIN_CMPNLEPD,
27961 IX86_BUILTIN_CMPNGTPD,
27962 IX86_BUILTIN_CMPNGEPD,
27963 IX86_BUILTIN_CMPORDPD,
27964 IX86_BUILTIN_CMPUNORDPD,
27965 IX86_BUILTIN_CMPEQSD,
27966 IX86_BUILTIN_CMPLTSD,
27967 IX86_BUILTIN_CMPLESD,
27968 IX86_BUILTIN_CMPNEQSD,
27969 IX86_BUILTIN_CMPNLTSD,
27970 IX86_BUILTIN_CMPNLESD,
27971 IX86_BUILTIN_CMPORDSD,
27972 IX86_BUILTIN_CMPUNORDSD,
27974 IX86_BUILTIN_COMIEQSD,
27975 IX86_BUILTIN_COMILTSD,
27976 IX86_BUILTIN_COMILESD,
27977 IX86_BUILTIN_COMIGTSD,
27978 IX86_BUILTIN_COMIGESD,
27979 IX86_BUILTIN_COMINEQSD,
27980 IX86_BUILTIN_UCOMIEQSD,
27981 IX86_BUILTIN_UCOMILTSD,
27982 IX86_BUILTIN_UCOMILESD,
27983 IX86_BUILTIN_UCOMIGTSD,
27984 IX86_BUILTIN_UCOMIGESD,
27985 IX86_BUILTIN_UCOMINEQSD,
27987 IX86_BUILTIN_MAXPD,
27988 IX86_BUILTIN_MAXSD,
27989 IX86_BUILTIN_MINPD,
27990 IX86_BUILTIN_MINSD,
27992 IX86_BUILTIN_ANDPD,
27993 IX86_BUILTIN_ANDNPD,
27994 IX86_BUILTIN_ORPD,
27995 IX86_BUILTIN_XORPD,
27997 IX86_BUILTIN_SQRTPD,
27998 IX86_BUILTIN_SQRTSD,
28000 IX86_BUILTIN_UNPCKHPD,
28001 IX86_BUILTIN_UNPCKLPD,
28003 IX86_BUILTIN_SHUFPD,
28005 IX86_BUILTIN_LOADUPD,
28006 IX86_BUILTIN_STOREUPD,
28007 IX86_BUILTIN_MOVSD,
28009 IX86_BUILTIN_LOADHPD,
28010 IX86_BUILTIN_LOADLPD,
28012 IX86_BUILTIN_CVTDQ2PD,
28013 IX86_BUILTIN_CVTDQ2PS,
28015 IX86_BUILTIN_CVTPD2DQ,
28016 IX86_BUILTIN_CVTPD2PI,
28017 IX86_BUILTIN_CVTPD2PS,
28018 IX86_BUILTIN_CVTTPD2DQ,
28019 IX86_BUILTIN_CVTTPD2PI,
28021 IX86_BUILTIN_CVTPI2PD,
28022 IX86_BUILTIN_CVTSI2SD,
28023 IX86_BUILTIN_CVTSI642SD,
28025 IX86_BUILTIN_CVTSD2SI,
28026 IX86_BUILTIN_CVTSD2SI64,
28027 IX86_BUILTIN_CVTSD2SS,
28028 IX86_BUILTIN_CVTSS2SD,
28029 IX86_BUILTIN_CVTTSD2SI,
28030 IX86_BUILTIN_CVTTSD2SI64,
28032 IX86_BUILTIN_CVTPS2DQ,
28033 IX86_BUILTIN_CVTPS2PD,
28034 IX86_BUILTIN_CVTTPS2DQ,
28036 IX86_BUILTIN_MOVNTI,
28037 IX86_BUILTIN_MOVNTI64,
28038 IX86_BUILTIN_MOVNTPD,
28039 IX86_BUILTIN_MOVNTDQ,
28041 IX86_BUILTIN_MOVQ128,
28043 /* SSE2 MMX */
28044 IX86_BUILTIN_MASKMOVDQU,
28045 IX86_BUILTIN_MOVMSKPD,
28046 IX86_BUILTIN_PMOVMSKB128,
28048 IX86_BUILTIN_PACKSSWB128,
28049 IX86_BUILTIN_PACKSSDW128,
28050 IX86_BUILTIN_PACKUSWB128,
28052 IX86_BUILTIN_PADDB128,
28053 IX86_BUILTIN_PADDW128,
28054 IX86_BUILTIN_PADDD128,
28055 IX86_BUILTIN_PADDQ128,
28056 IX86_BUILTIN_PADDSB128,
28057 IX86_BUILTIN_PADDSW128,
28058 IX86_BUILTIN_PADDUSB128,
28059 IX86_BUILTIN_PADDUSW128,
28060 IX86_BUILTIN_PSUBB128,
28061 IX86_BUILTIN_PSUBW128,
28062 IX86_BUILTIN_PSUBD128,
28063 IX86_BUILTIN_PSUBQ128,
28064 IX86_BUILTIN_PSUBSB128,
28065 IX86_BUILTIN_PSUBSW128,
28066 IX86_BUILTIN_PSUBUSB128,
28067 IX86_BUILTIN_PSUBUSW128,
28069 IX86_BUILTIN_PAND128,
28070 IX86_BUILTIN_PANDN128,
28071 IX86_BUILTIN_POR128,
28072 IX86_BUILTIN_PXOR128,
28074 IX86_BUILTIN_PAVGB128,
28075 IX86_BUILTIN_PAVGW128,
28077 IX86_BUILTIN_PCMPEQB128,
28078 IX86_BUILTIN_PCMPEQW128,
28079 IX86_BUILTIN_PCMPEQD128,
28080 IX86_BUILTIN_PCMPGTB128,
28081 IX86_BUILTIN_PCMPGTW128,
28082 IX86_BUILTIN_PCMPGTD128,
28084 IX86_BUILTIN_PMADDWD128,
28086 IX86_BUILTIN_PMAXSW128,
28087 IX86_BUILTIN_PMAXUB128,
28088 IX86_BUILTIN_PMINSW128,
28089 IX86_BUILTIN_PMINUB128,
28091 IX86_BUILTIN_PMULUDQ,
28092 IX86_BUILTIN_PMULUDQ128,
28093 IX86_BUILTIN_PMULHUW128,
28094 IX86_BUILTIN_PMULHW128,
28095 IX86_BUILTIN_PMULLW128,
28097 IX86_BUILTIN_PSADBW128,
28098 IX86_BUILTIN_PSHUFHW,
28099 IX86_BUILTIN_PSHUFLW,
28100 IX86_BUILTIN_PSHUFD,
28102 IX86_BUILTIN_PSLLDQI128,
28103 IX86_BUILTIN_PSLLWI128,
28104 IX86_BUILTIN_PSLLDI128,
28105 IX86_BUILTIN_PSLLQI128,
28106 IX86_BUILTIN_PSRAWI128,
28107 IX86_BUILTIN_PSRADI128,
28108 IX86_BUILTIN_PSRLDQI128,
28109 IX86_BUILTIN_PSRLWI128,
28110 IX86_BUILTIN_PSRLDI128,
28111 IX86_BUILTIN_PSRLQI128,
28113 IX86_BUILTIN_PSLLDQ128,
28114 IX86_BUILTIN_PSLLW128,
28115 IX86_BUILTIN_PSLLD128,
28116 IX86_BUILTIN_PSLLQ128,
28117 IX86_BUILTIN_PSRAW128,
28118 IX86_BUILTIN_PSRAD128,
28119 IX86_BUILTIN_PSRLW128,
28120 IX86_BUILTIN_PSRLD128,
28121 IX86_BUILTIN_PSRLQ128,
28123 IX86_BUILTIN_PUNPCKHBW128,
28124 IX86_BUILTIN_PUNPCKHWD128,
28125 IX86_BUILTIN_PUNPCKHDQ128,
28126 IX86_BUILTIN_PUNPCKHQDQ128,
28127 IX86_BUILTIN_PUNPCKLBW128,
28128 IX86_BUILTIN_PUNPCKLWD128,
28129 IX86_BUILTIN_PUNPCKLDQ128,
28130 IX86_BUILTIN_PUNPCKLQDQ128,
28132 IX86_BUILTIN_CLFLUSH,
28133 IX86_BUILTIN_MFENCE,
28134 IX86_BUILTIN_LFENCE,
28135 IX86_BUILTIN_PAUSE,
28137 IX86_BUILTIN_FNSTENV,
28138 IX86_BUILTIN_FLDENV,
28139 IX86_BUILTIN_FNSTSW,
28140 IX86_BUILTIN_FNCLEX,
28142 IX86_BUILTIN_BSRSI,
28143 IX86_BUILTIN_BSRDI,
28144 IX86_BUILTIN_RDPMC,
28145 IX86_BUILTIN_RDTSC,
28146 IX86_BUILTIN_RDTSCP,
28147 IX86_BUILTIN_ROLQI,
28148 IX86_BUILTIN_ROLHI,
28149 IX86_BUILTIN_RORQI,
28150 IX86_BUILTIN_RORHI,
28152 /* SSE3. */
28153 IX86_BUILTIN_ADDSUBPS,
28154 IX86_BUILTIN_HADDPS,
28155 IX86_BUILTIN_HSUBPS,
28156 IX86_BUILTIN_MOVSHDUP,
28157 IX86_BUILTIN_MOVSLDUP,
28158 IX86_BUILTIN_ADDSUBPD,
28159 IX86_BUILTIN_HADDPD,
28160 IX86_BUILTIN_HSUBPD,
28161 IX86_BUILTIN_LDDQU,
28163 IX86_BUILTIN_MONITOR,
28164 IX86_BUILTIN_MWAIT,
28166 /* SSSE3. */
28167 IX86_BUILTIN_PHADDW,
28168 IX86_BUILTIN_PHADDD,
28169 IX86_BUILTIN_PHADDSW,
28170 IX86_BUILTIN_PHSUBW,
28171 IX86_BUILTIN_PHSUBD,
28172 IX86_BUILTIN_PHSUBSW,
28173 IX86_BUILTIN_PMADDUBSW,
28174 IX86_BUILTIN_PMULHRSW,
28175 IX86_BUILTIN_PSHUFB,
28176 IX86_BUILTIN_PSIGNB,
28177 IX86_BUILTIN_PSIGNW,
28178 IX86_BUILTIN_PSIGND,
28179 IX86_BUILTIN_PALIGNR,
28180 IX86_BUILTIN_PABSB,
28181 IX86_BUILTIN_PABSW,
28182 IX86_BUILTIN_PABSD,
28184 IX86_BUILTIN_PHADDW128,
28185 IX86_BUILTIN_PHADDD128,
28186 IX86_BUILTIN_PHADDSW128,
28187 IX86_BUILTIN_PHSUBW128,
28188 IX86_BUILTIN_PHSUBD128,
28189 IX86_BUILTIN_PHSUBSW128,
28190 IX86_BUILTIN_PMADDUBSW128,
28191 IX86_BUILTIN_PMULHRSW128,
28192 IX86_BUILTIN_PSHUFB128,
28193 IX86_BUILTIN_PSIGNB128,
28194 IX86_BUILTIN_PSIGNW128,
28195 IX86_BUILTIN_PSIGND128,
28196 IX86_BUILTIN_PALIGNR128,
28197 IX86_BUILTIN_PABSB128,
28198 IX86_BUILTIN_PABSW128,
28199 IX86_BUILTIN_PABSD128,
28201 /* AMDFAM10 - SSE4A New Instructions. */
28202 IX86_BUILTIN_MOVNTSD,
28203 IX86_BUILTIN_MOVNTSS,
28204 IX86_BUILTIN_EXTRQI,
28205 IX86_BUILTIN_EXTRQ,
28206 IX86_BUILTIN_INSERTQI,
28207 IX86_BUILTIN_INSERTQ,
28209 /* SSE4.1. */
28210 IX86_BUILTIN_BLENDPD,
28211 IX86_BUILTIN_BLENDPS,
28212 IX86_BUILTIN_BLENDVPD,
28213 IX86_BUILTIN_BLENDVPS,
28214 IX86_BUILTIN_PBLENDVB128,
28215 IX86_BUILTIN_PBLENDW128,
28217 IX86_BUILTIN_DPPD,
28218 IX86_BUILTIN_DPPS,
28220 IX86_BUILTIN_INSERTPS128,
28222 IX86_BUILTIN_MOVNTDQA,
28223 IX86_BUILTIN_MPSADBW128,
28224 IX86_BUILTIN_PACKUSDW128,
28225 IX86_BUILTIN_PCMPEQQ,
28226 IX86_BUILTIN_PHMINPOSUW128,
28228 IX86_BUILTIN_PMAXSB128,
28229 IX86_BUILTIN_PMAXSD128,
28230 IX86_BUILTIN_PMAXUD128,
28231 IX86_BUILTIN_PMAXUW128,
28233 IX86_BUILTIN_PMINSB128,
28234 IX86_BUILTIN_PMINSD128,
28235 IX86_BUILTIN_PMINUD128,
28236 IX86_BUILTIN_PMINUW128,
28238 IX86_BUILTIN_PMOVSXBW128,
28239 IX86_BUILTIN_PMOVSXBD128,
28240 IX86_BUILTIN_PMOVSXBQ128,
28241 IX86_BUILTIN_PMOVSXWD128,
28242 IX86_BUILTIN_PMOVSXWQ128,
28243 IX86_BUILTIN_PMOVSXDQ128,
28245 IX86_BUILTIN_PMOVZXBW128,
28246 IX86_BUILTIN_PMOVZXBD128,
28247 IX86_BUILTIN_PMOVZXBQ128,
28248 IX86_BUILTIN_PMOVZXWD128,
28249 IX86_BUILTIN_PMOVZXWQ128,
28250 IX86_BUILTIN_PMOVZXDQ128,
28252 IX86_BUILTIN_PMULDQ128,
28253 IX86_BUILTIN_PMULLD128,
28255 IX86_BUILTIN_ROUNDSD,
28256 IX86_BUILTIN_ROUNDSS,
28258 IX86_BUILTIN_ROUNDPD,
28259 IX86_BUILTIN_ROUNDPS,
28261 IX86_BUILTIN_FLOORPD,
28262 IX86_BUILTIN_CEILPD,
28263 IX86_BUILTIN_TRUNCPD,
28264 IX86_BUILTIN_RINTPD,
28265 IX86_BUILTIN_ROUNDPD_AZ,
28267 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28268 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28269 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28271 IX86_BUILTIN_FLOORPS,
28272 IX86_BUILTIN_CEILPS,
28273 IX86_BUILTIN_TRUNCPS,
28274 IX86_BUILTIN_RINTPS,
28275 IX86_BUILTIN_ROUNDPS_AZ,
28277 IX86_BUILTIN_FLOORPS_SFIX,
28278 IX86_BUILTIN_CEILPS_SFIX,
28279 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28281 IX86_BUILTIN_PTESTZ,
28282 IX86_BUILTIN_PTESTC,
28283 IX86_BUILTIN_PTESTNZC,
28285 IX86_BUILTIN_VEC_INIT_V2SI,
28286 IX86_BUILTIN_VEC_INIT_V4HI,
28287 IX86_BUILTIN_VEC_INIT_V8QI,
28288 IX86_BUILTIN_VEC_EXT_V2DF,
28289 IX86_BUILTIN_VEC_EXT_V2DI,
28290 IX86_BUILTIN_VEC_EXT_V4SF,
28291 IX86_BUILTIN_VEC_EXT_V4SI,
28292 IX86_BUILTIN_VEC_EXT_V8HI,
28293 IX86_BUILTIN_VEC_EXT_V2SI,
28294 IX86_BUILTIN_VEC_EXT_V4HI,
28295 IX86_BUILTIN_VEC_EXT_V16QI,
28296 IX86_BUILTIN_VEC_SET_V2DI,
28297 IX86_BUILTIN_VEC_SET_V4SF,
28298 IX86_BUILTIN_VEC_SET_V4SI,
28299 IX86_BUILTIN_VEC_SET_V8HI,
28300 IX86_BUILTIN_VEC_SET_V4HI,
28301 IX86_BUILTIN_VEC_SET_V16QI,
28303 IX86_BUILTIN_VEC_PACK_SFIX,
28304 IX86_BUILTIN_VEC_PACK_SFIX256,
28306 /* SSE4.2. */
28307 IX86_BUILTIN_CRC32QI,
28308 IX86_BUILTIN_CRC32HI,
28309 IX86_BUILTIN_CRC32SI,
28310 IX86_BUILTIN_CRC32DI,
28312 IX86_BUILTIN_PCMPESTRI128,
28313 IX86_BUILTIN_PCMPESTRM128,
28314 IX86_BUILTIN_PCMPESTRA128,
28315 IX86_BUILTIN_PCMPESTRC128,
28316 IX86_BUILTIN_PCMPESTRO128,
28317 IX86_BUILTIN_PCMPESTRS128,
28318 IX86_BUILTIN_PCMPESTRZ128,
28319 IX86_BUILTIN_PCMPISTRI128,
28320 IX86_BUILTIN_PCMPISTRM128,
28321 IX86_BUILTIN_PCMPISTRA128,
28322 IX86_BUILTIN_PCMPISTRC128,
28323 IX86_BUILTIN_PCMPISTRO128,
28324 IX86_BUILTIN_PCMPISTRS128,
28325 IX86_BUILTIN_PCMPISTRZ128,
28327 IX86_BUILTIN_PCMPGTQ,
28329 /* AES instructions */
28330 IX86_BUILTIN_AESENC128,
28331 IX86_BUILTIN_AESENCLAST128,
28332 IX86_BUILTIN_AESDEC128,
28333 IX86_BUILTIN_AESDECLAST128,
28334 IX86_BUILTIN_AESIMC128,
28335 IX86_BUILTIN_AESKEYGENASSIST128,
28337 /* PCLMUL instruction */
28338 IX86_BUILTIN_PCLMULQDQ128,
28340 /* AVX */
28341 IX86_BUILTIN_ADDPD256,
28342 IX86_BUILTIN_ADDPS256,
28343 IX86_BUILTIN_ADDSUBPD256,
28344 IX86_BUILTIN_ADDSUBPS256,
28345 IX86_BUILTIN_ANDPD256,
28346 IX86_BUILTIN_ANDPS256,
28347 IX86_BUILTIN_ANDNPD256,
28348 IX86_BUILTIN_ANDNPS256,
28349 IX86_BUILTIN_BLENDPD256,
28350 IX86_BUILTIN_BLENDPS256,
28351 IX86_BUILTIN_BLENDVPD256,
28352 IX86_BUILTIN_BLENDVPS256,
28353 IX86_BUILTIN_DIVPD256,
28354 IX86_BUILTIN_DIVPS256,
28355 IX86_BUILTIN_DPPS256,
28356 IX86_BUILTIN_HADDPD256,
28357 IX86_BUILTIN_HADDPS256,
28358 IX86_BUILTIN_HSUBPD256,
28359 IX86_BUILTIN_HSUBPS256,
28360 IX86_BUILTIN_MAXPD256,
28361 IX86_BUILTIN_MAXPS256,
28362 IX86_BUILTIN_MINPD256,
28363 IX86_BUILTIN_MINPS256,
28364 IX86_BUILTIN_MULPD256,
28365 IX86_BUILTIN_MULPS256,
28366 IX86_BUILTIN_ORPD256,
28367 IX86_BUILTIN_ORPS256,
28368 IX86_BUILTIN_SHUFPD256,
28369 IX86_BUILTIN_SHUFPS256,
28370 IX86_BUILTIN_SUBPD256,
28371 IX86_BUILTIN_SUBPS256,
28372 IX86_BUILTIN_XORPD256,
28373 IX86_BUILTIN_XORPS256,
28374 IX86_BUILTIN_CMPSD,
28375 IX86_BUILTIN_CMPSS,
28376 IX86_BUILTIN_CMPPD,
28377 IX86_BUILTIN_CMPPS,
28378 IX86_BUILTIN_CMPPD256,
28379 IX86_BUILTIN_CMPPS256,
28380 IX86_BUILTIN_CVTDQ2PD256,
28381 IX86_BUILTIN_CVTDQ2PS256,
28382 IX86_BUILTIN_CVTPD2PS256,
28383 IX86_BUILTIN_CVTPS2DQ256,
28384 IX86_BUILTIN_CVTPS2PD256,
28385 IX86_BUILTIN_CVTTPD2DQ256,
28386 IX86_BUILTIN_CVTPD2DQ256,
28387 IX86_BUILTIN_CVTTPS2DQ256,
28388 IX86_BUILTIN_EXTRACTF128PD256,
28389 IX86_BUILTIN_EXTRACTF128PS256,
28390 IX86_BUILTIN_EXTRACTF128SI256,
28391 IX86_BUILTIN_VZEROALL,
28392 IX86_BUILTIN_VZEROUPPER,
28393 IX86_BUILTIN_VPERMILVARPD,
28394 IX86_BUILTIN_VPERMILVARPS,
28395 IX86_BUILTIN_VPERMILVARPD256,
28396 IX86_BUILTIN_VPERMILVARPS256,
28397 IX86_BUILTIN_VPERMILPD,
28398 IX86_BUILTIN_VPERMILPS,
28399 IX86_BUILTIN_VPERMILPD256,
28400 IX86_BUILTIN_VPERMILPS256,
28401 IX86_BUILTIN_VPERMIL2PD,
28402 IX86_BUILTIN_VPERMIL2PS,
28403 IX86_BUILTIN_VPERMIL2PD256,
28404 IX86_BUILTIN_VPERMIL2PS256,
28405 IX86_BUILTIN_VPERM2F128PD256,
28406 IX86_BUILTIN_VPERM2F128PS256,
28407 IX86_BUILTIN_VPERM2F128SI256,
28408 IX86_BUILTIN_VBROADCASTSS,
28409 IX86_BUILTIN_VBROADCASTSD256,
28410 IX86_BUILTIN_VBROADCASTSS256,
28411 IX86_BUILTIN_VBROADCASTPD256,
28412 IX86_BUILTIN_VBROADCASTPS256,
28413 IX86_BUILTIN_VINSERTF128PD256,
28414 IX86_BUILTIN_VINSERTF128PS256,
28415 IX86_BUILTIN_VINSERTF128SI256,
28416 IX86_BUILTIN_LOADUPD256,
28417 IX86_BUILTIN_LOADUPS256,
28418 IX86_BUILTIN_STOREUPD256,
28419 IX86_BUILTIN_STOREUPS256,
28420 IX86_BUILTIN_LDDQU256,
28421 IX86_BUILTIN_MOVNTDQ256,
28422 IX86_BUILTIN_MOVNTPD256,
28423 IX86_BUILTIN_MOVNTPS256,
28424 IX86_BUILTIN_LOADDQU256,
28425 IX86_BUILTIN_STOREDQU256,
28426 IX86_BUILTIN_MASKLOADPD,
28427 IX86_BUILTIN_MASKLOADPS,
28428 IX86_BUILTIN_MASKSTOREPD,
28429 IX86_BUILTIN_MASKSTOREPS,
28430 IX86_BUILTIN_MASKLOADPD256,
28431 IX86_BUILTIN_MASKLOADPS256,
28432 IX86_BUILTIN_MASKSTOREPD256,
28433 IX86_BUILTIN_MASKSTOREPS256,
28434 IX86_BUILTIN_MOVSHDUP256,
28435 IX86_BUILTIN_MOVSLDUP256,
28436 IX86_BUILTIN_MOVDDUP256,
28438 IX86_BUILTIN_SQRTPD256,
28439 IX86_BUILTIN_SQRTPS256,
28440 IX86_BUILTIN_SQRTPS_NR256,
28441 IX86_BUILTIN_RSQRTPS256,
28442 IX86_BUILTIN_RSQRTPS_NR256,
28444 IX86_BUILTIN_RCPPS256,
28446 IX86_BUILTIN_ROUNDPD256,
28447 IX86_BUILTIN_ROUNDPS256,
28449 IX86_BUILTIN_FLOORPD256,
28450 IX86_BUILTIN_CEILPD256,
28451 IX86_BUILTIN_TRUNCPD256,
28452 IX86_BUILTIN_RINTPD256,
28453 IX86_BUILTIN_ROUNDPD_AZ256,
28455 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28456 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28457 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28459 IX86_BUILTIN_FLOORPS256,
28460 IX86_BUILTIN_CEILPS256,
28461 IX86_BUILTIN_TRUNCPS256,
28462 IX86_BUILTIN_RINTPS256,
28463 IX86_BUILTIN_ROUNDPS_AZ256,
28465 IX86_BUILTIN_FLOORPS_SFIX256,
28466 IX86_BUILTIN_CEILPS_SFIX256,
28467 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28469 IX86_BUILTIN_UNPCKHPD256,
28470 IX86_BUILTIN_UNPCKLPD256,
28471 IX86_BUILTIN_UNPCKHPS256,
28472 IX86_BUILTIN_UNPCKLPS256,
28474 IX86_BUILTIN_SI256_SI,
28475 IX86_BUILTIN_PS256_PS,
28476 IX86_BUILTIN_PD256_PD,
28477 IX86_BUILTIN_SI_SI256,
28478 IX86_BUILTIN_PS_PS256,
28479 IX86_BUILTIN_PD_PD256,
28481 IX86_BUILTIN_VTESTZPD,
28482 IX86_BUILTIN_VTESTCPD,
28483 IX86_BUILTIN_VTESTNZCPD,
28484 IX86_BUILTIN_VTESTZPS,
28485 IX86_BUILTIN_VTESTCPS,
28486 IX86_BUILTIN_VTESTNZCPS,
28487 IX86_BUILTIN_VTESTZPD256,
28488 IX86_BUILTIN_VTESTCPD256,
28489 IX86_BUILTIN_VTESTNZCPD256,
28490 IX86_BUILTIN_VTESTZPS256,
28491 IX86_BUILTIN_VTESTCPS256,
28492 IX86_BUILTIN_VTESTNZCPS256,
28493 IX86_BUILTIN_PTESTZ256,
28494 IX86_BUILTIN_PTESTC256,
28495 IX86_BUILTIN_PTESTNZC256,
28497 IX86_BUILTIN_MOVMSKPD256,
28498 IX86_BUILTIN_MOVMSKPS256,
28500 /* AVX2 */
28501 IX86_BUILTIN_MPSADBW256,
28502 IX86_BUILTIN_PABSB256,
28503 IX86_BUILTIN_PABSW256,
28504 IX86_BUILTIN_PABSD256,
28505 IX86_BUILTIN_PACKSSDW256,
28506 IX86_BUILTIN_PACKSSWB256,
28507 IX86_BUILTIN_PACKUSDW256,
28508 IX86_BUILTIN_PACKUSWB256,
28509 IX86_BUILTIN_PADDB256,
28510 IX86_BUILTIN_PADDW256,
28511 IX86_BUILTIN_PADDD256,
28512 IX86_BUILTIN_PADDQ256,
28513 IX86_BUILTIN_PADDSB256,
28514 IX86_BUILTIN_PADDSW256,
28515 IX86_BUILTIN_PADDUSB256,
28516 IX86_BUILTIN_PADDUSW256,
28517 IX86_BUILTIN_PALIGNR256,
28518 IX86_BUILTIN_AND256I,
28519 IX86_BUILTIN_ANDNOT256I,
28520 IX86_BUILTIN_PAVGB256,
28521 IX86_BUILTIN_PAVGW256,
28522 IX86_BUILTIN_PBLENDVB256,
28523 IX86_BUILTIN_PBLENDVW256,
28524 IX86_BUILTIN_PCMPEQB256,
28525 IX86_BUILTIN_PCMPEQW256,
28526 IX86_BUILTIN_PCMPEQD256,
28527 IX86_BUILTIN_PCMPEQQ256,
28528 IX86_BUILTIN_PCMPGTB256,
28529 IX86_BUILTIN_PCMPGTW256,
28530 IX86_BUILTIN_PCMPGTD256,
28531 IX86_BUILTIN_PCMPGTQ256,
28532 IX86_BUILTIN_PHADDW256,
28533 IX86_BUILTIN_PHADDD256,
28534 IX86_BUILTIN_PHADDSW256,
28535 IX86_BUILTIN_PHSUBW256,
28536 IX86_BUILTIN_PHSUBD256,
28537 IX86_BUILTIN_PHSUBSW256,
28538 IX86_BUILTIN_PMADDUBSW256,
28539 IX86_BUILTIN_PMADDWD256,
28540 IX86_BUILTIN_PMAXSB256,
28541 IX86_BUILTIN_PMAXSW256,
28542 IX86_BUILTIN_PMAXSD256,
28543 IX86_BUILTIN_PMAXUB256,
28544 IX86_BUILTIN_PMAXUW256,
28545 IX86_BUILTIN_PMAXUD256,
28546 IX86_BUILTIN_PMINSB256,
28547 IX86_BUILTIN_PMINSW256,
28548 IX86_BUILTIN_PMINSD256,
28549 IX86_BUILTIN_PMINUB256,
28550 IX86_BUILTIN_PMINUW256,
28551 IX86_BUILTIN_PMINUD256,
28552 IX86_BUILTIN_PMOVMSKB256,
28553 IX86_BUILTIN_PMOVSXBW256,
28554 IX86_BUILTIN_PMOVSXBD256,
28555 IX86_BUILTIN_PMOVSXBQ256,
28556 IX86_BUILTIN_PMOVSXWD256,
28557 IX86_BUILTIN_PMOVSXWQ256,
28558 IX86_BUILTIN_PMOVSXDQ256,
28559 IX86_BUILTIN_PMOVZXBW256,
28560 IX86_BUILTIN_PMOVZXBD256,
28561 IX86_BUILTIN_PMOVZXBQ256,
28562 IX86_BUILTIN_PMOVZXWD256,
28563 IX86_BUILTIN_PMOVZXWQ256,
28564 IX86_BUILTIN_PMOVZXDQ256,
28565 IX86_BUILTIN_PMULDQ256,
28566 IX86_BUILTIN_PMULHRSW256,
28567 IX86_BUILTIN_PMULHUW256,
28568 IX86_BUILTIN_PMULHW256,
28569 IX86_BUILTIN_PMULLW256,
28570 IX86_BUILTIN_PMULLD256,
28571 IX86_BUILTIN_PMULUDQ256,
28572 IX86_BUILTIN_POR256,
28573 IX86_BUILTIN_PSADBW256,
28574 IX86_BUILTIN_PSHUFB256,
28575 IX86_BUILTIN_PSHUFD256,
28576 IX86_BUILTIN_PSHUFHW256,
28577 IX86_BUILTIN_PSHUFLW256,
28578 IX86_BUILTIN_PSIGNB256,
28579 IX86_BUILTIN_PSIGNW256,
28580 IX86_BUILTIN_PSIGND256,
28581 IX86_BUILTIN_PSLLDQI256,
28582 IX86_BUILTIN_PSLLWI256,
28583 IX86_BUILTIN_PSLLW256,
28584 IX86_BUILTIN_PSLLDI256,
28585 IX86_BUILTIN_PSLLD256,
28586 IX86_BUILTIN_PSLLQI256,
28587 IX86_BUILTIN_PSLLQ256,
28588 IX86_BUILTIN_PSRAWI256,
28589 IX86_BUILTIN_PSRAW256,
28590 IX86_BUILTIN_PSRADI256,
28591 IX86_BUILTIN_PSRAD256,
28592 IX86_BUILTIN_PSRLDQI256,
28593 IX86_BUILTIN_PSRLWI256,
28594 IX86_BUILTIN_PSRLW256,
28595 IX86_BUILTIN_PSRLDI256,
28596 IX86_BUILTIN_PSRLD256,
28597 IX86_BUILTIN_PSRLQI256,
28598 IX86_BUILTIN_PSRLQ256,
28599 IX86_BUILTIN_PSUBB256,
28600 IX86_BUILTIN_PSUBW256,
28601 IX86_BUILTIN_PSUBD256,
28602 IX86_BUILTIN_PSUBQ256,
28603 IX86_BUILTIN_PSUBSB256,
28604 IX86_BUILTIN_PSUBSW256,
28605 IX86_BUILTIN_PSUBUSB256,
28606 IX86_BUILTIN_PSUBUSW256,
28607 IX86_BUILTIN_PUNPCKHBW256,
28608 IX86_BUILTIN_PUNPCKHWD256,
28609 IX86_BUILTIN_PUNPCKHDQ256,
28610 IX86_BUILTIN_PUNPCKHQDQ256,
28611 IX86_BUILTIN_PUNPCKLBW256,
28612 IX86_BUILTIN_PUNPCKLWD256,
28613 IX86_BUILTIN_PUNPCKLDQ256,
28614 IX86_BUILTIN_PUNPCKLQDQ256,
28615 IX86_BUILTIN_PXOR256,
28616 IX86_BUILTIN_MOVNTDQA256,
28617 IX86_BUILTIN_VBROADCASTSS_PS,
28618 IX86_BUILTIN_VBROADCASTSS_PS256,
28619 IX86_BUILTIN_VBROADCASTSD_PD256,
28620 IX86_BUILTIN_VBROADCASTSI256,
28621 IX86_BUILTIN_PBLENDD256,
28622 IX86_BUILTIN_PBLENDD128,
28623 IX86_BUILTIN_PBROADCASTB256,
28624 IX86_BUILTIN_PBROADCASTW256,
28625 IX86_BUILTIN_PBROADCASTD256,
28626 IX86_BUILTIN_PBROADCASTQ256,
28627 IX86_BUILTIN_PBROADCASTB128,
28628 IX86_BUILTIN_PBROADCASTW128,
28629 IX86_BUILTIN_PBROADCASTD128,
28630 IX86_BUILTIN_PBROADCASTQ128,
28631 IX86_BUILTIN_VPERMVARSI256,
28632 IX86_BUILTIN_VPERMDF256,
28633 IX86_BUILTIN_VPERMVARSF256,
28634 IX86_BUILTIN_VPERMDI256,
28635 IX86_BUILTIN_VPERMTI256,
28636 IX86_BUILTIN_VEXTRACT128I256,
28637 IX86_BUILTIN_VINSERT128I256,
28638 IX86_BUILTIN_MASKLOADD,
28639 IX86_BUILTIN_MASKLOADQ,
28640 IX86_BUILTIN_MASKLOADD256,
28641 IX86_BUILTIN_MASKLOADQ256,
28642 IX86_BUILTIN_MASKSTORED,
28643 IX86_BUILTIN_MASKSTOREQ,
28644 IX86_BUILTIN_MASKSTORED256,
28645 IX86_BUILTIN_MASKSTOREQ256,
28646 IX86_BUILTIN_PSLLVV4DI,
28647 IX86_BUILTIN_PSLLVV2DI,
28648 IX86_BUILTIN_PSLLVV8SI,
28649 IX86_BUILTIN_PSLLVV4SI,
28650 IX86_BUILTIN_PSRAVV8SI,
28651 IX86_BUILTIN_PSRAVV4SI,
28652 IX86_BUILTIN_PSRLVV4DI,
28653 IX86_BUILTIN_PSRLVV2DI,
28654 IX86_BUILTIN_PSRLVV8SI,
28655 IX86_BUILTIN_PSRLVV4SI,
28657 IX86_BUILTIN_GATHERSIV2DF,
28658 IX86_BUILTIN_GATHERSIV4DF,
28659 IX86_BUILTIN_GATHERDIV2DF,
28660 IX86_BUILTIN_GATHERDIV4DF,
28661 IX86_BUILTIN_GATHERSIV4SF,
28662 IX86_BUILTIN_GATHERSIV8SF,
28663 IX86_BUILTIN_GATHERDIV4SF,
28664 IX86_BUILTIN_GATHERDIV8SF,
28665 IX86_BUILTIN_GATHERSIV2DI,
28666 IX86_BUILTIN_GATHERSIV4DI,
28667 IX86_BUILTIN_GATHERDIV2DI,
28668 IX86_BUILTIN_GATHERDIV4DI,
28669 IX86_BUILTIN_GATHERSIV4SI,
28670 IX86_BUILTIN_GATHERSIV8SI,
28671 IX86_BUILTIN_GATHERDIV4SI,
28672 IX86_BUILTIN_GATHERDIV8SI,
28674 /* AVX512F */
28675 IX86_BUILTIN_SI512_SI256,
28676 IX86_BUILTIN_PD512_PD256,
28677 IX86_BUILTIN_PS512_PS256,
28678 IX86_BUILTIN_SI512_SI,
28679 IX86_BUILTIN_PD512_PD,
28680 IX86_BUILTIN_PS512_PS,
28681 IX86_BUILTIN_ADDPD512,
28682 IX86_BUILTIN_ADDPS512,
28683 IX86_BUILTIN_ADDSD_ROUND,
28684 IX86_BUILTIN_ADDSS_ROUND,
28685 IX86_BUILTIN_ALIGND512,
28686 IX86_BUILTIN_ALIGNQ512,
28687 IX86_BUILTIN_BLENDMD512,
28688 IX86_BUILTIN_BLENDMPD512,
28689 IX86_BUILTIN_BLENDMPS512,
28690 IX86_BUILTIN_BLENDMQ512,
28691 IX86_BUILTIN_BROADCASTF32X4_512,
28692 IX86_BUILTIN_BROADCASTF64X4_512,
28693 IX86_BUILTIN_BROADCASTI32X4_512,
28694 IX86_BUILTIN_BROADCASTI64X4_512,
28695 IX86_BUILTIN_BROADCASTSD512,
28696 IX86_BUILTIN_BROADCASTSS512,
28697 IX86_BUILTIN_CMPD512,
28698 IX86_BUILTIN_CMPPD512,
28699 IX86_BUILTIN_CMPPS512,
28700 IX86_BUILTIN_CMPQ512,
28701 IX86_BUILTIN_CMPSD_MASK,
28702 IX86_BUILTIN_CMPSS_MASK,
28703 IX86_BUILTIN_COMIDF,
28704 IX86_BUILTIN_COMISF,
28705 IX86_BUILTIN_COMPRESSPD512,
28706 IX86_BUILTIN_COMPRESSPDSTORE512,
28707 IX86_BUILTIN_COMPRESSPS512,
28708 IX86_BUILTIN_COMPRESSPSSTORE512,
28709 IX86_BUILTIN_CVTDQ2PD512,
28710 IX86_BUILTIN_CVTDQ2PS512,
28711 IX86_BUILTIN_CVTPD2DQ512,
28712 IX86_BUILTIN_CVTPD2PS512,
28713 IX86_BUILTIN_CVTPD2UDQ512,
28714 IX86_BUILTIN_CVTPH2PS512,
28715 IX86_BUILTIN_CVTPS2DQ512,
28716 IX86_BUILTIN_CVTPS2PD512,
28717 IX86_BUILTIN_CVTPS2PH512,
28718 IX86_BUILTIN_CVTPS2UDQ512,
28719 IX86_BUILTIN_CVTSD2SS_ROUND,
28720 IX86_BUILTIN_CVTSI2SD64,
28721 IX86_BUILTIN_CVTSI2SS32,
28722 IX86_BUILTIN_CVTSI2SS64,
28723 IX86_BUILTIN_CVTSS2SD_ROUND,
28724 IX86_BUILTIN_CVTTPD2DQ512,
28725 IX86_BUILTIN_CVTTPD2UDQ512,
28726 IX86_BUILTIN_CVTTPS2DQ512,
28727 IX86_BUILTIN_CVTTPS2UDQ512,
28728 IX86_BUILTIN_CVTUDQ2PD512,
28729 IX86_BUILTIN_CVTUDQ2PS512,
28730 IX86_BUILTIN_CVTUSI2SD32,
28731 IX86_BUILTIN_CVTUSI2SD64,
28732 IX86_BUILTIN_CVTUSI2SS32,
28733 IX86_BUILTIN_CVTUSI2SS64,
28734 IX86_BUILTIN_DIVPD512,
28735 IX86_BUILTIN_DIVPS512,
28736 IX86_BUILTIN_DIVSD_ROUND,
28737 IX86_BUILTIN_DIVSS_ROUND,
28738 IX86_BUILTIN_EXPANDPD512,
28739 IX86_BUILTIN_EXPANDPD512Z,
28740 IX86_BUILTIN_EXPANDPDLOAD512,
28741 IX86_BUILTIN_EXPANDPDLOAD512Z,
28742 IX86_BUILTIN_EXPANDPS512,
28743 IX86_BUILTIN_EXPANDPS512Z,
28744 IX86_BUILTIN_EXPANDPSLOAD512,
28745 IX86_BUILTIN_EXPANDPSLOAD512Z,
28746 IX86_BUILTIN_EXTRACTF32X4,
28747 IX86_BUILTIN_EXTRACTF64X4,
28748 IX86_BUILTIN_EXTRACTI32X4,
28749 IX86_BUILTIN_EXTRACTI64X4,
28750 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28751 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28752 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28753 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28754 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28755 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28756 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28757 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28758 IX86_BUILTIN_GETEXPPD512,
28759 IX86_BUILTIN_GETEXPPS512,
28760 IX86_BUILTIN_GETEXPSD128,
28761 IX86_BUILTIN_GETEXPSS128,
28762 IX86_BUILTIN_GETMANTPD512,
28763 IX86_BUILTIN_GETMANTPS512,
28764 IX86_BUILTIN_GETMANTSD128,
28765 IX86_BUILTIN_GETMANTSS128,
28766 IX86_BUILTIN_INSERTF32X4,
28767 IX86_BUILTIN_INSERTF64X4,
28768 IX86_BUILTIN_INSERTI32X4,
28769 IX86_BUILTIN_INSERTI64X4,
28770 IX86_BUILTIN_LOADAPD512,
28771 IX86_BUILTIN_LOADAPS512,
28772 IX86_BUILTIN_LOADDQUDI512,
28773 IX86_BUILTIN_LOADDQUSI512,
28774 IX86_BUILTIN_LOADUPD512,
28775 IX86_BUILTIN_LOADUPS512,
28776 IX86_BUILTIN_MAXPD512,
28777 IX86_BUILTIN_MAXPS512,
28778 IX86_BUILTIN_MAXSD_ROUND,
28779 IX86_BUILTIN_MAXSS_ROUND,
28780 IX86_BUILTIN_MINPD512,
28781 IX86_BUILTIN_MINPS512,
28782 IX86_BUILTIN_MINSD_ROUND,
28783 IX86_BUILTIN_MINSS_ROUND,
28784 IX86_BUILTIN_MOVAPD512,
28785 IX86_BUILTIN_MOVAPS512,
28786 IX86_BUILTIN_MOVDDUP512,
28787 IX86_BUILTIN_MOVDQA32LOAD512,
28788 IX86_BUILTIN_MOVDQA32STORE512,
28789 IX86_BUILTIN_MOVDQA32_512,
28790 IX86_BUILTIN_MOVDQA64LOAD512,
28791 IX86_BUILTIN_MOVDQA64STORE512,
28792 IX86_BUILTIN_MOVDQA64_512,
28793 IX86_BUILTIN_MOVNTDQ512,
28794 IX86_BUILTIN_MOVNTDQA512,
28795 IX86_BUILTIN_MOVNTPD512,
28796 IX86_BUILTIN_MOVNTPS512,
28797 IX86_BUILTIN_MOVSHDUP512,
28798 IX86_BUILTIN_MOVSLDUP512,
28799 IX86_BUILTIN_MULPD512,
28800 IX86_BUILTIN_MULPS512,
28801 IX86_BUILTIN_MULSD_ROUND,
28802 IX86_BUILTIN_MULSS_ROUND,
28803 IX86_BUILTIN_PABSD512,
28804 IX86_BUILTIN_PABSQ512,
28805 IX86_BUILTIN_PADDD512,
28806 IX86_BUILTIN_PADDQ512,
28807 IX86_BUILTIN_PANDD512,
28808 IX86_BUILTIN_PANDND512,
28809 IX86_BUILTIN_PANDNQ512,
28810 IX86_BUILTIN_PANDQ512,
28811 IX86_BUILTIN_PBROADCASTD512,
28812 IX86_BUILTIN_PBROADCASTD512_GPR,
28813 IX86_BUILTIN_PBROADCASTMB512,
28814 IX86_BUILTIN_PBROADCASTMW512,
28815 IX86_BUILTIN_PBROADCASTQ512,
28816 IX86_BUILTIN_PBROADCASTQ512_GPR,
28817 IX86_BUILTIN_PBROADCASTQ512_MEM,
28818 IX86_BUILTIN_PCMPEQD512_MASK,
28819 IX86_BUILTIN_PCMPEQQ512_MASK,
28820 IX86_BUILTIN_PCMPGTD512_MASK,
28821 IX86_BUILTIN_PCMPGTQ512_MASK,
28822 IX86_BUILTIN_PCOMPRESSD512,
28823 IX86_BUILTIN_PCOMPRESSDSTORE512,
28824 IX86_BUILTIN_PCOMPRESSQ512,
28825 IX86_BUILTIN_PCOMPRESSQSTORE512,
28826 IX86_BUILTIN_PEXPANDD512,
28827 IX86_BUILTIN_PEXPANDD512Z,
28828 IX86_BUILTIN_PEXPANDDLOAD512,
28829 IX86_BUILTIN_PEXPANDDLOAD512Z,
28830 IX86_BUILTIN_PEXPANDQ512,
28831 IX86_BUILTIN_PEXPANDQ512Z,
28832 IX86_BUILTIN_PEXPANDQLOAD512,
28833 IX86_BUILTIN_PEXPANDQLOAD512Z,
28834 IX86_BUILTIN_PMAXSD512,
28835 IX86_BUILTIN_PMAXSQ512,
28836 IX86_BUILTIN_PMAXUD512,
28837 IX86_BUILTIN_PMAXUQ512,
28838 IX86_BUILTIN_PMINSD512,
28839 IX86_BUILTIN_PMINSQ512,
28840 IX86_BUILTIN_PMINUD512,
28841 IX86_BUILTIN_PMINUQ512,
28842 IX86_BUILTIN_PMOVDB512,
28843 IX86_BUILTIN_PMOVDB512_MEM,
28844 IX86_BUILTIN_PMOVDW512,
28845 IX86_BUILTIN_PMOVDW512_MEM,
28846 IX86_BUILTIN_PMOVQB512,
28847 IX86_BUILTIN_PMOVQB512_MEM,
28848 IX86_BUILTIN_PMOVQD512,
28849 IX86_BUILTIN_PMOVQD512_MEM,
28850 IX86_BUILTIN_PMOVQW512,
28851 IX86_BUILTIN_PMOVQW512_MEM,
28852 IX86_BUILTIN_PMOVSDB512,
28853 IX86_BUILTIN_PMOVSDB512_MEM,
28854 IX86_BUILTIN_PMOVSDW512,
28855 IX86_BUILTIN_PMOVSDW512_MEM,
28856 IX86_BUILTIN_PMOVSQB512,
28857 IX86_BUILTIN_PMOVSQB512_MEM,
28858 IX86_BUILTIN_PMOVSQD512,
28859 IX86_BUILTIN_PMOVSQD512_MEM,
28860 IX86_BUILTIN_PMOVSQW512,
28861 IX86_BUILTIN_PMOVSQW512_MEM,
28862 IX86_BUILTIN_PMOVSXBD512,
28863 IX86_BUILTIN_PMOVSXBQ512,
28864 IX86_BUILTIN_PMOVSXDQ512,
28865 IX86_BUILTIN_PMOVSXWD512,
28866 IX86_BUILTIN_PMOVSXWQ512,
28867 IX86_BUILTIN_PMOVUSDB512,
28868 IX86_BUILTIN_PMOVUSDB512_MEM,
28869 IX86_BUILTIN_PMOVUSDW512,
28870 IX86_BUILTIN_PMOVUSDW512_MEM,
28871 IX86_BUILTIN_PMOVUSQB512,
28872 IX86_BUILTIN_PMOVUSQB512_MEM,
28873 IX86_BUILTIN_PMOVUSQD512,
28874 IX86_BUILTIN_PMOVUSQD512_MEM,
28875 IX86_BUILTIN_PMOVUSQW512,
28876 IX86_BUILTIN_PMOVUSQW512_MEM,
28877 IX86_BUILTIN_PMOVZXBD512,
28878 IX86_BUILTIN_PMOVZXBQ512,
28879 IX86_BUILTIN_PMOVZXDQ512,
28880 IX86_BUILTIN_PMOVZXWD512,
28881 IX86_BUILTIN_PMOVZXWQ512,
28882 IX86_BUILTIN_PMULDQ512,
28883 IX86_BUILTIN_PMULLD512,
28884 IX86_BUILTIN_PMULUDQ512,
28885 IX86_BUILTIN_PORD512,
28886 IX86_BUILTIN_PORQ512,
28887 IX86_BUILTIN_PROLD512,
28888 IX86_BUILTIN_PROLQ512,
28889 IX86_BUILTIN_PROLVD512,
28890 IX86_BUILTIN_PROLVQ512,
28891 IX86_BUILTIN_PRORD512,
28892 IX86_BUILTIN_PRORQ512,
28893 IX86_BUILTIN_PRORVD512,
28894 IX86_BUILTIN_PRORVQ512,
28895 IX86_BUILTIN_PSHUFD512,
28896 IX86_BUILTIN_PSLLD512,
28897 IX86_BUILTIN_PSLLDI512,
28898 IX86_BUILTIN_PSLLQ512,
28899 IX86_BUILTIN_PSLLQI512,
28900 IX86_BUILTIN_PSLLVV16SI,
28901 IX86_BUILTIN_PSLLVV8DI,
28902 IX86_BUILTIN_PSRAD512,
28903 IX86_BUILTIN_PSRADI512,
28904 IX86_BUILTIN_PSRAQ512,
28905 IX86_BUILTIN_PSRAQI512,
28906 IX86_BUILTIN_PSRAVV16SI,
28907 IX86_BUILTIN_PSRAVV8DI,
28908 IX86_BUILTIN_PSRLD512,
28909 IX86_BUILTIN_PSRLDI512,
28910 IX86_BUILTIN_PSRLQ512,
28911 IX86_BUILTIN_PSRLQI512,
28912 IX86_BUILTIN_PSRLVV16SI,
28913 IX86_BUILTIN_PSRLVV8DI,
28914 IX86_BUILTIN_PSUBD512,
28915 IX86_BUILTIN_PSUBQ512,
28916 IX86_BUILTIN_PTESTMD512,
28917 IX86_BUILTIN_PTESTMQ512,
28918 IX86_BUILTIN_PTESTNMD512,
28919 IX86_BUILTIN_PTESTNMQ512,
28920 IX86_BUILTIN_PUNPCKHDQ512,
28921 IX86_BUILTIN_PUNPCKHQDQ512,
28922 IX86_BUILTIN_PUNPCKLDQ512,
28923 IX86_BUILTIN_PUNPCKLQDQ512,
28924 IX86_BUILTIN_PXORD512,
28925 IX86_BUILTIN_PXORQ512,
28926 IX86_BUILTIN_RCP14PD512,
28927 IX86_BUILTIN_RCP14PS512,
28928 IX86_BUILTIN_RCP14SD,
28929 IX86_BUILTIN_RCP14SS,
28930 IX86_BUILTIN_RNDSCALEPD,
28931 IX86_BUILTIN_RNDSCALEPS,
28932 IX86_BUILTIN_RNDSCALESD,
28933 IX86_BUILTIN_RNDSCALESS,
28934 IX86_BUILTIN_RSQRT14PD512,
28935 IX86_BUILTIN_RSQRT14PS512,
28936 IX86_BUILTIN_RSQRT14SD,
28937 IX86_BUILTIN_RSQRT14SS,
28938 IX86_BUILTIN_SCALEFPD512,
28939 IX86_BUILTIN_SCALEFPS512,
28940 IX86_BUILTIN_SCALEFSD,
28941 IX86_BUILTIN_SCALEFSS,
28942 IX86_BUILTIN_SHUFPD512,
28943 IX86_BUILTIN_SHUFPS512,
28944 IX86_BUILTIN_SHUF_F32x4,
28945 IX86_BUILTIN_SHUF_F64x2,
28946 IX86_BUILTIN_SHUF_I32x4,
28947 IX86_BUILTIN_SHUF_I64x2,
28948 IX86_BUILTIN_SQRTPD512,
28949 IX86_BUILTIN_SQRTPD512_MASK,
28950 IX86_BUILTIN_SQRTPS512_MASK,
28951 IX86_BUILTIN_SQRTPS_NR512,
28952 IX86_BUILTIN_SQRTSD_ROUND,
28953 IX86_BUILTIN_SQRTSS_ROUND,
28954 IX86_BUILTIN_STOREAPD512,
28955 IX86_BUILTIN_STOREAPS512,
28956 IX86_BUILTIN_STOREDQUDI512,
28957 IX86_BUILTIN_STOREDQUSI512,
28958 IX86_BUILTIN_STOREUPD512,
28959 IX86_BUILTIN_STOREUPS512,
28960 IX86_BUILTIN_SUBPD512,
28961 IX86_BUILTIN_SUBPS512,
28962 IX86_BUILTIN_SUBSD_ROUND,
28963 IX86_BUILTIN_SUBSS_ROUND,
28964 IX86_BUILTIN_UCMPD512,
28965 IX86_BUILTIN_UCMPQ512,
28966 IX86_BUILTIN_UNPCKHPD512,
28967 IX86_BUILTIN_UNPCKHPS512,
28968 IX86_BUILTIN_UNPCKLPD512,
28969 IX86_BUILTIN_UNPCKLPS512,
28970 IX86_BUILTIN_VCVTSD2SI32,
28971 IX86_BUILTIN_VCVTSD2SI64,
28972 IX86_BUILTIN_VCVTSD2USI32,
28973 IX86_BUILTIN_VCVTSD2USI64,
28974 IX86_BUILTIN_VCVTSS2SI32,
28975 IX86_BUILTIN_VCVTSS2SI64,
28976 IX86_BUILTIN_VCVTSS2USI32,
28977 IX86_BUILTIN_VCVTSS2USI64,
28978 IX86_BUILTIN_VCVTTSD2SI32,
28979 IX86_BUILTIN_VCVTTSD2SI64,
28980 IX86_BUILTIN_VCVTTSD2USI32,
28981 IX86_BUILTIN_VCVTTSD2USI64,
28982 IX86_BUILTIN_VCVTTSS2SI32,
28983 IX86_BUILTIN_VCVTTSS2SI64,
28984 IX86_BUILTIN_VCVTTSS2USI32,
28985 IX86_BUILTIN_VCVTTSS2USI64,
28986 IX86_BUILTIN_VFMADDPD512_MASK,
28987 IX86_BUILTIN_VFMADDPD512_MASK3,
28988 IX86_BUILTIN_VFMADDPD512_MASKZ,
28989 IX86_BUILTIN_VFMADDPS512_MASK,
28990 IX86_BUILTIN_VFMADDPS512_MASK3,
28991 IX86_BUILTIN_VFMADDPS512_MASKZ,
28992 IX86_BUILTIN_VFMADDSD3_ROUND,
28993 IX86_BUILTIN_VFMADDSS3_ROUND,
28994 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28995 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28996 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28997 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28998 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28999 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29000 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29001 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29002 IX86_BUILTIN_VFMSUBPD512_MASK3,
29003 IX86_BUILTIN_VFMSUBPS512_MASK3,
29004 IX86_BUILTIN_VFMSUBSD3_MASK3,
29005 IX86_BUILTIN_VFMSUBSS3_MASK3,
29006 IX86_BUILTIN_VFNMADDPD512_MASK,
29007 IX86_BUILTIN_VFNMADDPS512_MASK,
29008 IX86_BUILTIN_VFNMSUBPD512_MASK,
29009 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29010 IX86_BUILTIN_VFNMSUBPS512_MASK,
29011 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29012 IX86_BUILTIN_VPCLZCNTD512,
29013 IX86_BUILTIN_VPCLZCNTQ512,
29014 IX86_BUILTIN_VPCONFLICTD512,
29015 IX86_BUILTIN_VPCONFLICTQ512,
29016 IX86_BUILTIN_VPERMDF512,
29017 IX86_BUILTIN_VPERMDI512,
29018 IX86_BUILTIN_VPERMI2VARD512,
29019 IX86_BUILTIN_VPERMI2VARPD512,
29020 IX86_BUILTIN_VPERMI2VARPS512,
29021 IX86_BUILTIN_VPERMI2VARQ512,
29022 IX86_BUILTIN_VPERMILPD512,
29023 IX86_BUILTIN_VPERMILPS512,
29024 IX86_BUILTIN_VPERMILVARPD512,
29025 IX86_BUILTIN_VPERMILVARPS512,
29026 IX86_BUILTIN_VPERMT2VARD512,
29027 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29028 IX86_BUILTIN_VPERMT2VARPD512,
29029 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29030 IX86_BUILTIN_VPERMT2VARPS512,
29031 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29032 IX86_BUILTIN_VPERMT2VARQ512,
29033 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29034 IX86_BUILTIN_VPERMVARDF512,
29035 IX86_BUILTIN_VPERMVARDI512,
29036 IX86_BUILTIN_VPERMVARSF512,
29037 IX86_BUILTIN_VPERMVARSI512,
29038 IX86_BUILTIN_VTERNLOGD512_MASK,
29039 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29040 IX86_BUILTIN_VTERNLOGQ512_MASK,
29041 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29043 /* Mask arithmetic operations */
29044 IX86_BUILTIN_KAND16,
29045 IX86_BUILTIN_KANDN16,
29046 IX86_BUILTIN_KNOT16,
29047 IX86_BUILTIN_KOR16,
29048 IX86_BUILTIN_KORTESTC16,
29049 IX86_BUILTIN_KORTESTZ16,
29050 IX86_BUILTIN_KUNPCKBW,
29051 IX86_BUILTIN_KXNOR16,
29052 IX86_BUILTIN_KXOR16,
29053 IX86_BUILTIN_KMOV16,
29055 /* AVX512VL. */
29056 IX86_BUILTIN_PMOVUSQD256_MEM,
29057 IX86_BUILTIN_PMOVUSQD128_MEM,
29058 IX86_BUILTIN_PMOVSQD256_MEM,
29059 IX86_BUILTIN_PMOVSQD128_MEM,
29060 IX86_BUILTIN_PMOVQD256_MEM,
29061 IX86_BUILTIN_PMOVQD128_MEM,
29062 IX86_BUILTIN_PMOVUSQW256_MEM,
29063 IX86_BUILTIN_PMOVUSQW128_MEM,
29064 IX86_BUILTIN_PMOVSQW256_MEM,
29065 IX86_BUILTIN_PMOVSQW128_MEM,
29066 IX86_BUILTIN_PMOVQW256_MEM,
29067 IX86_BUILTIN_PMOVQW128_MEM,
29068 IX86_BUILTIN_PMOVUSQB256_MEM,
29069 IX86_BUILTIN_PMOVUSQB128_MEM,
29070 IX86_BUILTIN_PMOVSQB256_MEM,
29071 IX86_BUILTIN_PMOVSQB128_MEM,
29072 IX86_BUILTIN_PMOVQB256_MEM,
29073 IX86_BUILTIN_PMOVQB128_MEM,
29074 IX86_BUILTIN_PMOVUSDW256_MEM,
29075 IX86_BUILTIN_PMOVUSDW128_MEM,
29076 IX86_BUILTIN_PMOVSDW256_MEM,
29077 IX86_BUILTIN_PMOVSDW128_MEM,
29078 IX86_BUILTIN_PMOVDW256_MEM,
29079 IX86_BUILTIN_PMOVDW128_MEM,
29080 IX86_BUILTIN_PMOVUSDB256_MEM,
29081 IX86_BUILTIN_PMOVUSDB128_MEM,
29082 IX86_BUILTIN_PMOVSDB256_MEM,
29083 IX86_BUILTIN_PMOVSDB128_MEM,
29084 IX86_BUILTIN_PMOVDB256_MEM,
29085 IX86_BUILTIN_PMOVDB128_MEM,
29086 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29087 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29088 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29089 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29090 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29091 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29092 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29093 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29094 IX86_BUILTIN_LOADAPD256_MASK,
29095 IX86_BUILTIN_LOADAPD128_MASK,
29096 IX86_BUILTIN_LOADAPS256_MASK,
29097 IX86_BUILTIN_LOADAPS128_MASK,
29098 IX86_BUILTIN_STOREAPD256_MASK,
29099 IX86_BUILTIN_STOREAPD128_MASK,
29100 IX86_BUILTIN_STOREAPS256_MASK,
29101 IX86_BUILTIN_STOREAPS128_MASK,
29102 IX86_BUILTIN_LOADUPD256_MASK,
29103 IX86_BUILTIN_LOADUPD128_MASK,
29104 IX86_BUILTIN_LOADUPS256_MASK,
29105 IX86_BUILTIN_LOADUPS128_MASK,
29106 IX86_BUILTIN_STOREUPD256_MASK,
29107 IX86_BUILTIN_STOREUPD128_MASK,
29108 IX86_BUILTIN_STOREUPS256_MASK,
29109 IX86_BUILTIN_STOREUPS128_MASK,
29110 IX86_BUILTIN_LOADDQUDI256_MASK,
29111 IX86_BUILTIN_LOADDQUDI128_MASK,
29112 IX86_BUILTIN_LOADDQUSI256_MASK,
29113 IX86_BUILTIN_LOADDQUSI128_MASK,
29114 IX86_BUILTIN_LOADDQUHI256_MASK,
29115 IX86_BUILTIN_LOADDQUHI128_MASK,
29116 IX86_BUILTIN_LOADDQUQI256_MASK,
29117 IX86_BUILTIN_LOADDQUQI128_MASK,
29118 IX86_BUILTIN_STOREDQUDI256_MASK,
29119 IX86_BUILTIN_STOREDQUDI128_MASK,
29120 IX86_BUILTIN_STOREDQUSI256_MASK,
29121 IX86_BUILTIN_STOREDQUSI128_MASK,
29122 IX86_BUILTIN_STOREDQUHI256_MASK,
29123 IX86_BUILTIN_STOREDQUHI128_MASK,
29124 IX86_BUILTIN_STOREDQUQI256_MASK,
29125 IX86_BUILTIN_STOREDQUQI128_MASK,
29126 IX86_BUILTIN_COMPRESSPDSTORE256,
29127 IX86_BUILTIN_COMPRESSPDSTORE128,
29128 IX86_BUILTIN_COMPRESSPSSTORE256,
29129 IX86_BUILTIN_COMPRESSPSSTORE128,
29130 IX86_BUILTIN_PCOMPRESSQSTORE256,
29131 IX86_BUILTIN_PCOMPRESSQSTORE128,
29132 IX86_BUILTIN_PCOMPRESSDSTORE256,
29133 IX86_BUILTIN_PCOMPRESSDSTORE128,
29134 IX86_BUILTIN_EXPANDPDLOAD256,
29135 IX86_BUILTIN_EXPANDPDLOAD128,
29136 IX86_BUILTIN_EXPANDPSLOAD256,
29137 IX86_BUILTIN_EXPANDPSLOAD128,
29138 IX86_BUILTIN_PEXPANDQLOAD256,
29139 IX86_BUILTIN_PEXPANDQLOAD128,
29140 IX86_BUILTIN_PEXPANDDLOAD256,
29141 IX86_BUILTIN_PEXPANDDLOAD128,
29142 IX86_BUILTIN_EXPANDPDLOAD256Z,
29143 IX86_BUILTIN_EXPANDPDLOAD128Z,
29144 IX86_BUILTIN_EXPANDPSLOAD256Z,
29145 IX86_BUILTIN_EXPANDPSLOAD128Z,
29146 IX86_BUILTIN_PEXPANDQLOAD256Z,
29147 IX86_BUILTIN_PEXPANDQLOAD128Z,
29148 IX86_BUILTIN_PEXPANDDLOAD256Z,
29149 IX86_BUILTIN_PEXPANDDLOAD128Z,
29150 IX86_BUILTIN_PALIGNR256_MASK,
29151 IX86_BUILTIN_PALIGNR128_MASK,
29152 IX86_BUILTIN_MOVDQA64_256_MASK,
29153 IX86_BUILTIN_MOVDQA64_128_MASK,
29154 IX86_BUILTIN_MOVDQA32_256_MASK,
29155 IX86_BUILTIN_MOVDQA32_128_MASK,
29156 IX86_BUILTIN_MOVAPD256_MASK,
29157 IX86_BUILTIN_MOVAPD128_MASK,
29158 IX86_BUILTIN_MOVAPS256_MASK,
29159 IX86_BUILTIN_MOVAPS128_MASK,
29160 IX86_BUILTIN_MOVDQUHI256_MASK,
29161 IX86_BUILTIN_MOVDQUHI128_MASK,
29162 IX86_BUILTIN_MOVDQUQI256_MASK,
29163 IX86_BUILTIN_MOVDQUQI128_MASK,
29164 IX86_BUILTIN_MINPS128_MASK,
29165 IX86_BUILTIN_MAXPS128_MASK,
29166 IX86_BUILTIN_MINPD128_MASK,
29167 IX86_BUILTIN_MAXPD128_MASK,
29168 IX86_BUILTIN_MAXPD256_MASK,
29169 IX86_BUILTIN_MAXPS256_MASK,
29170 IX86_BUILTIN_MINPD256_MASK,
29171 IX86_BUILTIN_MINPS256_MASK,
29172 IX86_BUILTIN_MULPS128_MASK,
29173 IX86_BUILTIN_DIVPS128_MASK,
29174 IX86_BUILTIN_MULPD128_MASK,
29175 IX86_BUILTIN_DIVPD128_MASK,
29176 IX86_BUILTIN_DIVPD256_MASK,
29177 IX86_BUILTIN_DIVPS256_MASK,
29178 IX86_BUILTIN_MULPD256_MASK,
29179 IX86_BUILTIN_MULPS256_MASK,
29180 IX86_BUILTIN_ADDPD128_MASK,
29181 IX86_BUILTIN_ADDPD256_MASK,
29182 IX86_BUILTIN_ADDPS128_MASK,
29183 IX86_BUILTIN_ADDPS256_MASK,
29184 IX86_BUILTIN_SUBPD128_MASK,
29185 IX86_BUILTIN_SUBPD256_MASK,
29186 IX86_BUILTIN_SUBPS128_MASK,
29187 IX86_BUILTIN_SUBPS256_MASK,
29188 IX86_BUILTIN_XORPD256_MASK,
29189 IX86_BUILTIN_XORPD128_MASK,
29190 IX86_BUILTIN_XORPS256_MASK,
29191 IX86_BUILTIN_XORPS128_MASK,
29192 IX86_BUILTIN_ORPD256_MASK,
29193 IX86_BUILTIN_ORPD128_MASK,
29194 IX86_BUILTIN_ORPS256_MASK,
29195 IX86_BUILTIN_ORPS128_MASK,
29196 IX86_BUILTIN_BROADCASTF32x2_256,
29197 IX86_BUILTIN_BROADCASTI32x2_256,
29198 IX86_BUILTIN_BROADCASTI32x2_128,
29199 IX86_BUILTIN_BROADCASTF64X2_256,
29200 IX86_BUILTIN_BROADCASTI64X2_256,
29201 IX86_BUILTIN_BROADCASTF32X4_256,
29202 IX86_BUILTIN_BROADCASTI32X4_256,
29203 IX86_BUILTIN_EXTRACTF32X4_256,
29204 IX86_BUILTIN_EXTRACTI32X4_256,
29205 IX86_BUILTIN_DBPSADBW256,
29206 IX86_BUILTIN_DBPSADBW128,
29207 IX86_BUILTIN_CVTTPD2QQ256,
29208 IX86_BUILTIN_CVTTPD2QQ128,
29209 IX86_BUILTIN_CVTTPD2UQQ256,
29210 IX86_BUILTIN_CVTTPD2UQQ128,
29211 IX86_BUILTIN_CVTPD2QQ256,
29212 IX86_BUILTIN_CVTPD2QQ128,
29213 IX86_BUILTIN_CVTPD2UQQ256,
29214 IX86_BUILTIN_CVTPD2UQQ128,
29215 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29216 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29217 IX86_BUILTIN_CVTTPS2QQ256,
29218 IX86_BUILTIN_CVTTPS2QQ128,
29219 IX86_BUILTIN_CVTTPS2UQQ256,
29220 IX86_BUILTIN_CVTTPS2UQQ128,
29221 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29222 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29223 IX86_BUILTIN_CVTTPS2UDQ256,
29224 IX86_BUILTIN_CVTTPS2UDQ128,
29225 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29226 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29227 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29228 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29229 IX86_BUILTIN_CVTPD2DQ256_MASK,
29230 IX86_BUILTIN_CVTPD2DQ128_MASK,
29231 IX86_BUILTIN_CVTDQ2PD256_MASK,
29232 IX86_BUILTIN_CVTDQ2PD128_MASK,
29233 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29234 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29235 IX86_BUILTIN_CVTDQ2PS256_MASK,
29236 IX86_BUILTIN_CVTDQ2PS128_MASK,
29237 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29238 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29239 IX86_BUILTIN_CVTPS2PD256_MASK,
29240 IX86_BUILTIN_CVTPS2PD128_MASK,
29241 IX86_BUILTIN_PBROADCASTB256_MASK,
29242 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29243 IX86_BUILTIN_PBROADCASTB128_MASK,
29244 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29245 IX86_BUILTIN_PBROADCASTW256_MASK,
29246 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29247 IX86_BUILTIN_PBROADCASTW128_MASK,
29248 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29249 IX86_BUILTIN_PBROADCASTD256_MASK,
29250 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29251 IX86_BUILTIN_PBROADCASTD128_MASK,
29252 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29253 IX86_BUILTIN_PBROADCASTQ256_MASK,
29254 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29255 IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
29256 IX86_BUILTIN_PBROADCASTQ128_MASK,
29257 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29258 IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
29259 IX86_BUILTIN_BROADCASTSS256,
29260 IX86_BUILTIN_BROADCASTSS128,
29261 IX86_BUILTIN_BROADCASTSD256,
29262 IX86_BUILTIN_EXTRACTF64X2_256,
29263 IX86_BUILTIN_EXTRACTI64X2_256,
29264 IX86_BUILTIN_INSERTF32X4_256,
29265 IX86_BUILTIN_INSERTI32X4_256,
29266 IX86_BUILTIN_PMOVSXBW256_MASK,
29267 IX86_BUILTIN_PMOVSXBW128_MASK,
29268 IX86_BUILTIN_PMOVSXBD256_MASK,
29269 IX86_BUILTIN_PMOVSXBD128_MASK,
29270 IX86_BUILTIN_PMOVSXBQ256_MASK,
29271 IX86_BUILTIN_PMOVSXBQ128_MASK,
29272 IX86_BUILTIN_PMOVSXWD256_MASK,
29273 IX86_BUILTIN_PMOVSXWD128_MASK,
29274 IX86_BUILTIN_PMOVSXWQ256_MASK,
29275 IX86_BUILTIN_PMOVSXWQ128_MASK,
29276 IX86_BUILTIN_PMOVSXDQ256_MASK,
29277 IX86_BUILTIN_PMOVSXDQ128_MASK,
29278 IX86_BUILTIN_PMOVZXBW256_MASK,
29279 IX86_BUILTIN_PMOVZXBW128_MASK,
29280 IX86_BUILTIN_PMOVZXBD256_MASK,
29281 IX86_BUILTIN_PMOVZXBD128_MASK,
29282 IX86_BUILTIN_PMOVZXBQ256_MASK,
29283 IX86_BUILTIN_PMOVZXBQ128_MASK,
29284 IX86_BUILTIN_PMOVZXWD256_MASK,
29285 IX86_BUILTIN_PMOVZXWD128_MASK,
29286 IX86_BUILTIN_PMOVZXWQ256_MASK,
29287 IX86_BUILTIN_PMOVZXWQ128_MASK,
29288 IX86_BUILTIN_PMOVZXDQ256_MASK,
29289 IX86_BUILTIN_PMOVZXDQ128_MASK,
29290 IX86_BUILTIN_REDUCEPD256_MASK,
29291 IX86_BUILTIN_REDUCEPD128_MASK,
29292 IX86_BUILTIN_REDUCEPS256_MASK,
29293 IX86_BUILTIN_REDUCEPS128_MASK,
29294 IX86_BUILTIN_REDUCESD_MASK,
29295 IX86_BUILTIN_REDUCESS_MASK,
29296 IX86_BUILTIN_VPERMVARHI256_MASK,
29297 IX86_BUILTIN_VPERMVARHI128_MASK,
29298 IX86_BUILTIN_VPERMT2VARHI256,
29299 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29300 IX86_BUILTIN_VPERMT2VARHI128,
29301 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29302 IX86_BUILTIN_VPERMI2VARHI256,
29303 IX86_BUILTIN_VPERMI2VARHI128,
29304 IX86_BUILTIN_RCP14PD256,
29305 IX86_BUILTIN_RCP14PD128,
29306 IX86_BUILTIN_RCP14PS256,
29307 IX86_BUILTIN_RCP14PS128,
29308 IX86_BUILTIN_RSQRT14PD256_MASK,
29309 IX86_BUILTIN_RSQRT14PD128_MASK,
29310 IX86_BUILTIN_RSQRT14PS256_MASK,
29311 IX86_BUILTIN_RSQRT14PS128_MASK,
29312 IX86_BUILTIN_SQRTPD256_MASK,
29313 IX86_BUILTIN_SQRTPD128_MASK,
29314 IX86_BUILTIN_SQRTPS256_MASK,
29315 IX86_BUILTIN_SQRTPS128_MASK,
29316 IX86_BUILTIN_PADDB128_MASK,
29317 IX86_BUILTIN_PADDW128_MASK,
29318 IX86_BUILTIN_PADDD128_MASK,
29319 IX86_BUILTIN_PADDQ128_MASK,
29320 IX86_BUILTIN_PSUBB128_MASK,
29321 IX86_BUILTIN_PSUBW128_MASK,
29322 IX86_BUILTIN_PSUBD128_MASK,
29323 IX86_BUILTIN_PSUBQ128_MASK,
29324 IX86_BUILTIN_PADDSB128_MASK,
29325 IX86_BUILTIN_PADDSW128_MASK,
29326 IX86_BUILTIN_PSUBSB128_MASK,
29327 IX86_BUILTIN_PSUBSW128_MASK,
29328 IX86_BUILTIN_PADDUSB128_MASK,
29329 IX86_BUILTIN_PADDUSW128_MASK,
29330 IX86_BUILTIN_PSUBUSB128_MASK,
29331 IX86_BUILTIN_PSUBUSW128_MASK,
29332 IX86_BUILTIN_PADDB256_MASK,
29333 IX86_BUILTIN_PADDW256_MASK,
29334 IX86_BUILTIN_PADDD256_MASK,
29335 IX86_BUILTIN_PADDQ256_MASK,
29336 IX86_BUILTIN_PADDSB256_MASK,
29337 IX86_BUILTIN_PADDSW256_MASK,
29338 IX86_BUILTIN_PADDUSB256_MASK,
29339 IX86_BUILTIN_PADDUSW256_MASK,
29340 IX86_BUILTIN_PSUBB256_MASK,
29341 IX86_BUILTIN_PSUBW256_MASK,
29342 IX86_BUILTIN_PSUBD256_MASK,
29343 IX86_BUILTIN_PSUBQ256_MASK,
29344 IX86_BUILTIN_PSUBSB256_MASK,
29345 IX86_BUILTIN_PSUBSW256_MASK,
29346 IX86_BUILTIN_PSUBUSB256_MASK,
29347 IX86_BUILTIN_PSUBUSW256_MASK,
29348 IX86_BUILTIN_SHUF_F64x2_256,
29349 IX86_BUILTIN_SHUF_I64x2_256,
29350 IX86_BUILTIN_SHUF_I32x4_256,
29351 IX86_BUILTIN_SHUF_F32x4_256,
29352 IX86_BUILTIN_PMOVWB128,
29353 IX86_BUILTIN_PMOVWB256,
29354 IX86_BUILTIN_PMOVSWB128,
29355 IX86_BUILTIN_PMOVSWB256,
29356 IX86_BUILTIN_PMOVUSWB128,
29357 IX86_BUILTIN_PMOVUSWB256,
29358 IX86_BUILTIN_PMOVDB128,
29359 IX86_BUILTIN_PMOVDB256,
29360 IX86_BUILTIN_PMOVSDB128,
29361 IX86_BUILTIN_PMOVSDB256,
29362 IX86_BUILTIN_PMOVUSDB128,
29363 IX86_BUILTIN_PMOVUSDB256,
29364 IX86_BUILTIN_PMOVDW128,
29365 IX86_BUILTIN_PMOVDW256,
29366 IX86_BUILTIN_PMOVSDW128,
29367 IX86_BUILTIN_PMOVSDW256,
29368 IX86_BUILTIN_PMOVUSDW128,
29369 IX86_BUILTIN_PMOVUSDW256,
29370 IX86_BUILTIN_PMOVQB128,
29371 IX86_BUILTIN_PMOVQB256,
29372 IX86_BUILTIN_PMOVSQB128,
29373 IX86_BUILTIN_PMOVSQB256,
29374 IX86_BUILTIN_PMOVUSQB128,
29375 IX86_BUILTIN_PMOVUSQB256,
29376 IX86_BUILTIN_PMOVQW128,
29377 IX86_BUILTIN_PMOVQW256,
29378 IX86_BUILTIN_PMOVSQW128,
29379 IX86_BUILTIN_PMOVSQW256,
29380 IX86_BUILTIN_PMOVUSQW128,
29381 IX86_BUILTIN_PMOVUSQW256,
29382 IX86_BUILTIN_PMOVQD128,
29383 IX86_BUILTIN_PMOVQD256,
29384 IX86_BUILTIN_PMOVSQD128,
29385 IX86_BUILTIN_PMOVSQD256,
29386 IX86_BUILTIN_PMOVUSQD128,
29387 IX86_BUILTIN_PMOVUSQD256,
29388 IX86_BUILTIN_RANGEPD256,
29389 IX86_BUILTIN_RANGEPD128,
29390 IX86_BUILTIN_RANGEPS256,
29391 IX86_BUILTIN_RANGEPS128,
29392 IX86_BUILTIN_GETEXPPS256,
29393 IX86_BUILTIN_GETEXPPD256,
29394 IX86_BUILTIN_GETEXPPS128,
29395 IX86_BUILTIN_GETEXPPD128,
29396 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29397 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29398 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29399 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29400 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29401 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29402 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29403 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29404 IX86_BUILTIN_PABSQ256,
29405 IX86_BUILTIN_PABSQ128,
29406 IX86_BUILTIN_PABSD256_MASK,
29407 IX86_BUILTIN_PABSD128_MASK,
29408 IX86_BUILTIN_PMULHRSW256_MASK,
29409 IX86_BUILTIN_PMULHRSW128_MASK,
29410 IX86_BUILTIN_PMULHUW128_MASK,
29411 IX86_BUILTIN_PMULHUW256_MASK,
29412 IX86_BUILTIN_PMULHW256_MASK,
29413 IX86_BUILTIN_PMULHW128_MASK,
29414 IX86_BUILTIN_PMULLW256_MASK,
29415 IX86_BUILTIN_PMULLW128_MASK,
29416 IX86_BUILTIN_PMULLQ256,
29417 IX86_BUILTIN_PMULLQ128,
29418 IX86_BUILTIN_ANDPD256_MASK,
29419 IX86_BUILTIN_ANDPD128_MASK,
29420 IX86_BUILTIN_ANDPS256_MASK,
29421 IX86_BUILTIN_ANDPS128_MASK,
29422 IX86_BUILTIN_ANDNPD256_MASK,
29423 IX86_BUILTIN_ANDNPD128_MASK,
29424 IX86_BUILTIN_ANDNPS256_MASK,
29425 IX86_BUILTIN_ANDNPS128_MASK,
29426 IX86_BUILTIN_PSLLWI128_MASK,
29427 IX86_BUILTIN_PSLLDI128_MASK,
29428 IX86_BUILTIN_PSLLQI128_MASK,
29429 IX86_BUILTIN_PSLLW128_MASK,
29430 IX86_BUILTIN_PSLLD128_MASK,
29431 IX86_BUILTIN_PSLLQ128_MASK,
29432 IX86_BUILTIN_PSLLWI256_MASK ,
29433 IX86_BUILTIN_PSLLW256_MASK,
29434 IX86_BUILTIN_PSLLDI256_MASK,
29435 IX86_BUILTIN_PSLLD256_MASK,
29436 IX86_BUILTIN_PSLLQI256_MASK,
29437 IX86_BUILTIN_PSLLQ256_MASK,
29438 IX86_BUILTIN_PSRADI128_MASK,
29439 IX86_BUILTIN_PSRAD128_MASK,
29440 IX86_BUILTIN_PSRADI256_MASK,
29441 IX86_BUILTIN_PSRAD256_MASK,
29442 IX86_BUILTIN_PSRAQI128_MASK,
29443 IX86_BUILTIN_PSRAQ128_MASK,
29444 IX86_BUILTIN_PSRAQI256_MASK,
29445 IX86_BUILTIN_PSRAQ256_MASK,
29446 IX86_BUILTIN_PANDD256,
29447 IX86_BUILTIN_PANDD128,
29448 IX86_BUILTIN_PSRLDI128_MASK,
29449 IX86_BUILTIN_PSRLD128_MASK,
29450 IX86_BUILTIN_PSRLDI256_MASK,
29451 IX86_BUILTIN_PSRLD256_MASK,
29452 IX86_BUILTIN_PSRLQI128_MASK,
29453 IX86_BUILTIN_PSRLQ128_MASK,
29454 IX86_BUILTIN_PSRLQI256_MASK,
29455 IX86_BUILTIN_PSRLQ256_MASK,
29456 IX86_BUILTIN_PANDQ256,
29457 IX86_BUILTIN_PANDQ128,
29458 IX86_BUILTIN_PANDND256,
29459 IX86_BUILTIN_PANDND128,
29460 IX86_BUILTIN_PANDNQ256,
29461 IX86_BUILTIN_PANDNQ128,
29462 IX86_BUILTIN_PORD256,
29463 IX86_BUILTIN_PORD128,
29464 IX86_BUILTIN_PORQ256,
29465 IX86_BUILTIN_PORQ128,
29466 IX86_BUILTIN_PXORD256,
29467 IX86_BUILTIN_PXORD128,
29468 IX86_BUILTIN_PXORQ256,
29469 IX86_BUILTIN_PXORQ128,
29470 IX86_BUILTIN_PACKSSWB256_MASK,
29471 IX86_BUILTIN_PACKSSWB128_MASK,
29472 IX86_BUILTIN_PACKUSWB256_MASK,
29473 IX86_BUILTIN_PACKUSWB128_MASK,
29474 IX86_BUILTIN_RNDSCALEPS256,
29475 IX86_BUILTIN_RNDSCALEPD256,
29476 IX86_BUILTIN_RNDSCALEPS128,
29477 IX86_BUILTIN_RNDSCALEPD128,
29478 IX86_BUILTIN_VTERNLOGQ256_MASK,
29479 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29480 IX86_BUILTIN_VTERNLOGD256_MASK,
29481 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29482 IX86_BUILTIN_VTERNLOGQ128_MASK,
29483 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29484 IX86_BUILTIN_VTERNLOGD128_MASK,
29485 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29486 IX86_BUILTIN_SCALEFPD256,
29487 IX86_BUILTIN_SCALEFPS256,
29488 IX86_BUILTIN_SCALEFPD128,
29489 IX86_BUILTIN_SCALEFPS128,
29490 IX86_BUILTIN_VFMADDPD256_MASK,
29491 IX86_BUILTIN_VFMADDPD256_MASK3,
29492 IX86_BUILTIN_VFMADDPD256_MASKZ,
29493 IX86_BUILTIN_VFMADDPD128_MASK,
29494 IX86_BUILTIN_VFMADDPD128_MASK3,
29495 IX86_BUILTIN_VFMADDPD128_MASKZ,
29496 IX86_BUILTIN_VFMADDPS256_MASK,
29497 IX86_BUILTIN_VFMADDPS256_MASK3,
29498 IX86_BUILTIN_VFMADDPS256_MASKZ,
29499 IX86_BUILTIN_VFMADDPS128_MASK,
29500 IX86_BUILTIN_VFMADDPS128_MASK3,
29501 IX86_BUILTIN_VFMADDPS128_MASKZ,
29502 IX86_BUILTIN_VFMSUBPD256_MASK3,
29503 IX86_BUILTIN_VFMSUBPD128_MASK3,
29504 IX86_BUILTIN_VFMSUBPS256_MASK3,
29505 IX86_BUILTIN_VFMSUBPS128_MASK3,
29506 IX86_BUILTIN_VFNMADDPD256_MASK,
29507 IX86_BUILTIN_VFNMADDPD128_MASK,
29508 IX86_BUILTIN_VFNMADDPS256_MASK,
29509 IX86_BUILTIN_VFNMADDPS128_MASK,
29510 IX86_BUILTIN_VFNMSUBPD256_MASK,
29511 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29512 IX86_BUILTIN_VFNMSUBPD128_MASK,
29513 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29514 IX86_BUILTIN_VFNMSUBPS256_MASK,
29515 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29516 IX86_BUILTIN_VFNMSUBPS128_MASK,
29517 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29518 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29519 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29520 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29521 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29522 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29523 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29524 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29525 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29526 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29527 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29528 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29529 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29530 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29531 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29532 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29533 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29534 IX86_BUILTIN_INSERTF64X2_256,
29535 IX86_BUILTIN_INSERTI64X2_256,
29536 IX86_BUILTIN_PSRAVV16HI,
29537 IX86_BUILTIN_PSRAVV8HI,
29538 IX86_BUILTIN_PMADDUBSW256_MASK,
29539 IX86_BUILTIN_PMADDUBSW128_MASK,
29540 IX86_BUILTIN_PMADDWD256_MASK,
29541 IX86_BUILTIN_PMADDWD128_MASK,
29542 IX86_BUILTIN_PSRLVV16HI,
29543 IX86_BUILTIN_PSRLVV8HI,
29544 IX86_BUILTIN_CVTPS2DQ256_MASK,
29545 IX86_BUILTIN_CVTPS2DQ128_MASK,
29546 IX86_BUILTIN_CVTPS2UDQ256,
29547 IX86_BUILTIN_CVTPS2UDQ128,
29548 IX86_BUILTIN_CVTPS2QQ256,
29549 IX86_BUILTIN_CVTPS2QQ128,
29550 IX86_BUILTIN_CVTPS2UQQ256,
29551 IX86_BUILTIN_CVTPS2UQQ128,
29552 IX86_BUILTIN_GETMANTPS256,
29553 IX86_BUILTIN_GETMANTPS128,
29554 IX86_BUILTIN_GETMANTPD256,
29555 IX86_BUILTIN_GETMANTPD128,
29556 IX86_BUILTIN_MOVDDUP256_MASK,
29557 IX86_BUILTIN_MOVDDUP128_MASK,
29558 IX86_BUILTIN_MOVSHDUP256_MASK,
29559 IX86_BUILTIN_MOVSHDUP128_MASK,
29560 IX86_BUILTIN_MOVSLDUP256_MASK,
29561 IX86_BUILTIN_MOVSLDUP128_MASK,
29562 IX86_BUILTIN_CVTQQ2PS256,
29563 IX86_BUILTIN_CVTQQ2PS128,
29564 IX86_BUILTIN_CVTUQQ2PS256,
29565 IX86_BUILTIN_CVTUQQ2PS128,
29566 IX86_BUILTIN_CVTQQ2PD256,
29567 IX86_BUILTIN_CVTQQ2PD128,
29568 IX86_BUILTIN_CVTUQQ2PD256,
29569 IX86_BUILTIN_CVTUQQ2PD128,
29570 IX86_BUILTIN_VPERMT2VARQ256,
29571 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29572 IX86_BUILTIN_VPERMT2VARD256,
29573 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29574 IX86_BUILTIN_VPERMI2VARQ256,
29575 IX86_BUILTIN_VPERMI2VARD256,
29576 IX86_BUILTIN_VPERMT2VARPD256,
29577 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29578 IX86_BUILTIN_VPERMT2VARPS256,
29579 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29580 IX86_BUILTIN_VPERMI2VARPD256,
29581 IX86_BUILTIN_VPERMI2VARPS256,
29582 IX86_BUILTIN_VPERMT2VARQ128,
29583 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29584 IX86_BUILTIN_VPERMT2VARD128,
29585 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29586 IX86_BUILTIN_VPERMI2VARQ128,
29587 IX86_BUILTIN_VPERMI2VARD128,
29588 IX86_BUILTIN_VPERMT2VARPD128,
29589 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29590 IX86_BUILTIN_VPERMT2VARPS128,
29591 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29592 IX86_BUILTIN_VPERMI2VARPD128,
29593 IX86_BUILTIN_VPERMI2VARPS128,
29594 IX86_BUILTIN_PSHUFB256_MASK,
29595 IX86_BUILTIN_PSHUFB128_MASK,
29596 IX86_BUILTIN_PSHUFHW256_MASK,
29597 IX86_BUILTIN_PSHUFHW128_MASK,
29598 IX86_BUILTIN_PSHUFLW256_MASK,
29599 IX86_BUILTIN_PSHUFLW128_MASK,
29600 IX86_BUILTIN_PSHUFD256_MASK,
29601 IX86_BUILTIN_PSHUFD128_MASK,
29602 IX86_BUILTIN_SHUFPD256_MASK,
29603 IX86_BUILTIN_SHUFPD128_MASK,
29604 IX86_BUILTIN_SHUFPS256_MASK,
29605 IX86_BUILTIN_SHUFPS128_MASK,
29606 IX86_BUILTIN_PROLVQ256,
29607 IX86_BUILTIN_PROLVQ128,
29608 IX86_BUILTIN_PROLQ256,
29609 IX86_BUILTIN_PROLQ128,
29610 IX86_BUILTIN_PRORVQ256,
29611 IX86_BUILTIN_PRORVQ128,
29612 IX86_BUILTIN_PRORQ256,
29613 IX86_BUILTIN_PRORQ128,
29614 IX86_BUILTIN_PSRAVQ128,
29615 IX86_BUILTIN_PSRAVQ256,
29616 IX86_BUILTIN_PSLLVV4DI_MASK,
29617 IX86_BUILTIN_PSLLVV2DI_MASK,
29618 IX86_BUILTIN_PSLLVV8SI_MASK,
29619 IX86_BUILTIN_PSLLVV4SI_MASK,
29620 IX86_BUILTIN_PSRAVV8SI_MASK,
29621 IX86_BUILTIN_PSRAVV4SI_MASK,
29622 IX86_BUILTIN_PSRLVV4DI_MASK,
29623 IX86_BUILTIN_PSRLVV2DI_MASK,
29624 IX86_BUILTIN_PSRLVV8SI_MASK,
29625 IX86_BUILTIN_PSRLVV4SI_MASK,
29626 IX86_BUILTIN_PSRAWI256_MASK,
29627 IX86_BUILTIN_PSRAW256_MASK,
29628 IX86_BUILTIN_PSRAWI128_MASK,
29629 IX86_BUILTIN_PSRAW128_MASK,
29630 IX86_BUILTIN_PSRLWI256_MASK,
29631 IX86_BUILTIN_PSRLW256_MASK,
29632 IX86_BUILTIN_PSRLWI128_MASK,
29633 IX86_BUILTIN_PSRLW128_MASK,
29634 IX86_BUILTIN_PRORVD256,
29635 IX86_BUILTIN_PROLVD256,
29636 IX86_BUILTIN_PRORD256,
29637 IX86_BUILTIN_PROLD256,
29638 IX86_BUILTIN_PRORVD128,
29639 IX86_BUILTIN_PROLVD128,
29640 IX86_BUILTIN_PRORD128,
29641 IX86_BUILTIN_PROLD128,
29642 IX86_BUILTIN_FPCLASSPD256,
29643 IX86_BUILTIN_FPCLASSPD128,
29644 IX86_BUILTIN_FPCLASSSD,
29645 IX86_BUILTIN_FPCLASSPS256,
29646 IX86_BUILTIN_FPCLASSPS128,
29647 IX86_BUILTIN_FPCLASSSS,
29648 IX86_BUILTIN_CVTB2MASK128,
29649 IX86_BUILTIN_CVTB2MASK256,
29650 IX86_BUILTIN_CVTW2MASK128,
29651 IX86_BUILTIN_CVTW2MASK256,
29652 IX86_BUILTIN_CVTD2MASK128,
29653 IX86_BUILTIN_CVTD2MASK256,
29654 IX86_BUILTIN_CVTQ2MASK128,
29655 IX86_BUILTIN_CVTQ2MASK256,
29656 IX86_BUILTIN_CVTMASK2B128,
29657 IX86_BUILTIN_CVTMASK2B256,
29658 IX86_BUILTIN_CVTMASK2W128,
29659 IX86_BUILTIN_CVTMASK2W256,
29660 IX86_BUILTIN_CVTMASK2D128,
29661 IX86_BUILTIN_CVTMASK2D256,
29662 IX86_BUILTIN_CVTMASK2Q128,
29663 IX86_BUILTIN_CVTMASK2Q256,
29664 IX86_BUILTIN_PCMPEQB128_MASK,
29665 IX86_BUILTIN_PCMPEQB256_MASK,
29666 IX86_BUILTIN_PCMPEQW128_MASK,
29667 IX86_BUILTIN_PCMPEQW256_MASK,
29668 IX86_BUILTIN_PCMPEQD128_MASK,
29669 IX86_BUILTIN_PCMPEQD256_MASK,
29670 IX86_BUILTIN_PCMPEQQ128_MASK,
29671 IX86_BUILTIN_PCMPEQQ256_MASK,
29672 IX86_BUILTIN_PCMPGTB128_MASK,
29673 IX86_BUILTIN_PCMPGTB256_MASK,
29674 IX86_BUILTIN_PCMPGTW128_MASK,
29675 IX86_BUILTIN_PCMPGTW256_MASK,
29676 IX86_BUILTIN_PCMPGTD128_MASK,
29677 IX86_BUILTIN_PCMPGTD256_MASK,
29678 IX86_BUILTIN_PCMPGTQ128_MASK,
29679 IX86_BUILTIN_PCMPGTQ256_MASK,
29680 IX86_BUILTIN_PTESTMB128,
29681 IX86_BUILTIN_PTESTMB256,
29682 IX86_BUILTIN_PTESTMW128,
29683 IX86_BUILTIN_PTESTMW256,
29684 IX86_BUILTIN_PTESTMD128,
29685 IX86_BUILTIN_PTESTMD256,
29686 IX86_BUILTIN_PTESTMQ128,
29687 IX86_BUILTIN_PTESTMQ256,
29688 IX86_BUILTIN_PTESTNMB128,
29689 IX86_BUILTIN_PTESTNMB256,
29690 IX86_BUILTIN_PTESTNMW128,
29691 IX86_BUILTIN_PTESTNMW256,
29692 IX86_BUILTIN_PTESTNMD128,
29693 IX86_BUILTIN_PTESTNMD256,
29694 IX86_BUILTIN_PTESTNMQ128,
29695 IX86_BUILTIN_PTESTNMQ256,
29696 IX86_BUILTIN_PBROADCASTMB128,
29697 IX86_BUILTIN_PBROADCASTMB256,
29698 IX86_BUILTIN_PBROADCASTMW128,
29699 IX86_BUILTIN_PBROADCASTMW256,
29700 IX86_BUILTIN_COMPRESSPD256,
29701 IX86_BUILTIN_COMPRESSPD128,
29702 IX86_BUILTIN_COMPRESSPS256,
29703 IX86_BUILTIN_COMPRESSPS128,
29704 IX86_BUILTIN_PCOMPRESSQ256,
29705 IX86_BUILTIN_PCOMPRESSQ128,
29706 IX86_BUILTIN_PCOMPRESSD256,
29707 IX86_BUILTIN_PCOMPRESSD128,
29708 IX86_BUILTIN_EXPANDPD256,
29709 IX86_BUILTIN_EXPANDPD128,
29710 IX86_BUILTIN_EXPANDPS256,
29711 IX86_BUILTIN_EXPANDPS128,
29712 IX86_BUILTIN_PEXPANDQ256,
29713 IX86_BUILTIN_PEXPANDQ128,
29714 IX86_BUILTIN_PEXPANDD256,
29715 IX86_BUILTIN_PEXPANDD128,
29716 IX86_BUILTIN_EXPANDPD256Z,
29717 IX86_BUILTIN_EXPANDPD128Z,
29718 IX86_BUILTIN_EXPANDPS256Z,
29719 IX86_BUILTIN_EXPANDPS128Z,
29720 IX86_BUILTIN_PEXPANDQ256Z,
29721 IX86_BUILTIN_PEXPANDQ128Z,
29722 IX86_BUILTIN_PEXPANDD256Z,
29723 IX86_BUILTIN_PEXPANDD128Z,
29724 IX86_BUILTIN_PMAXSD256_MASK,
29725 IX86_BUILTIN_PMINSD256_MASK,
29726 IX86_BUILTIN_PMAXUD256_MASK,
29727 IX86_BUILTIN_PMINUD256_MASK,
29728 IX86_BUILTIN_PMAXSD128_MASK,
29729 IX86_BUILTIN_PMINSD128_MASK,
29730 IX86_BUILTIN_PMAXUD128_MASK,
29731 IX86_BUILTIN_PMINUD128_MASK,
29732 IX86_BUILTIN_PMAXSQ256_MASK,
29733 IX86_BUILTIN_PMINSQ256_MASK,
29734 IX86_BUILTIN_PMAXUQ256_MASK,
29735 IX86_BUILTIN_PMINUQ256_MASK,
29736 IX86_BUILTIN_PMAXSQ128_MASK,
29737 IX86_BUILTIN_PMINSQ128_MASK,
29738 IX86_BUILTIN_PMAXUQ128_MASK,
29739 IX86_BUILTIN_PMINUQ128_MASK,
29740 IX86_BUILTIN_PMINSB256_MASK,
29741 IX86_BUILTIN_PMINUB256_MASK,
29742 IX86_BUILTIN_PMAXSB256_MASK,
29743 IX86_BUILTIN_PMAXUB256_MASK,
29744 IX86_BUILTIN_PMINSB128_MASK,
29745 IX86_BUILTIN_PMINUB128_MASK,
29746 IX86_BUILTIN_PMAXSB128_MASK,
29747 IX86_BUILTIN_PMAXUB128_MASK,
29748 IX86_BUILTIN_PMINSW256_MASK,
29749 IX86_BUILTIN_PMINUW256_MASK,
29750 IX86_BUILTIN_PMAXSW256_MASK,
29751 IX86_BUILTIN_PMAXUW256_MASK,
29752 IX86_BUILTIN_PMINSW128_MASK,
29753 IX86_BUILTIN_PMINUW128_MASK,
29754 IX86_BUILTIN_PMAXSW128_MASK,
29755 IX86_BUILTIN_PMAXUW128_MASK,
29756 IX86_BUILTIN_VPCONFLICTQ256,
29757 IX86_BUILTIN_VPCONFLICTD256,
29758 IX86_BUILTIN_VPCLZCNTQ256,
29759 IX86_BUILTIN_VPCLZCNTD256,
29760 IX86_BUILTIN_UNPCKHPD256_MASK,
29761 IX86_BUILTIN_UNPCKHPD128_MASK,
29762 IX86_BUILTIN_UNPCKHPS256_MASK,
29763 IX86_BUILTIN_UNPCKHPS128_MASK,
29764 IX86_BUILTIN_UNPCKLPD256_MASK,
29765 IX86_BUILTIN_UNPCKLPD128_MASK,
29766 IX86_BUILTIN_UNPCKLPS256_MASK,
29767 IX86_BUILTIN_VPCONFLICTQ128,
29768 IX86_BUILTIN_VPCONFLICTD128,
29769 IX86_BUILTIN_VPCLZCNTQ128,
29770 IX86_BUILTIN_VPCLZCNTD128,
29771 IX86_BUILTIN_UNPCKLPS128_MASK,
29772 IX86_BUILTIN_ALIGND256,
29773 IX86_BUILTIN_ALIGNQ256,
29774 IX86_BUILTIN_ALIGND128,
29775 IX86_BUILTIN_ALIGNQ128,
29776 IX86_BUILTIN_CVTPS2PH256_MASK,
29777 IX86_BUILTIN_CVTPS2PH_MASK,
29778 IX86_BUILTIN_CVTPH2PS_MASK,
29779 IX86_BUILTIN_CVTPH2PS256_MASK,
29780 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29781 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29782 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29783 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29784 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29785 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29786 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29787 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29788 IX86_BUILTIN_PUNPCKHBW128_MASK,
29789 IX86_BUILTIN_PUNPCKHBW256_MASK,
29790 IX86_BUILTIN_PUNPCKHWD128_MASK,
29791 IX86_BUILTIN_PUNPCKHWD256_MASK,
29792 IX86_BUILTIN_PUNPCKLBW128_MASK,
29793 IX86_BUILTIN_PUNPCKLBW256_MASK,
29794 IX86_BUILTIN_PUNPCKLWD128_MASK,
29795 IX86_BUILTIN_PUNPCKLWD256_MASK,
29796 IX86_BUILTIN_PSLLVV16HI,
29797 IX86_BUILTIN_PSLLVV8HI,
29798 IX86_BUILTIN_PACKSSDW256_MASK,
29799 IX86_BUILTIN_PACKSSDW128_MASK,
29800 IX86_BUILTIN_PACKUSDW256_MASK,
29801 IX86_BUILTIN_PACKUSDW128_MASK,
29802 IX86_BUILTIN_PAVGB256_MASK,
29803 IX86_BUILTIN_PAVGW256_MASK,
29804 IX86_BUILTIN_PAVGB128_MASK,
29805 IX86_BUILTIN_PAVGW128_MASK,
29806 IX86_BUILTIN_VPERMVARSF256_MASK,
29807 IX86_BUILTIN_VPERMVARDF256_MASK,
29808 IX86_BUILTIN_VPERMDF256_MASK,
29809 IX86_BUILTIN_PABSB256_MASK,
29810 IX86_BUILTIN_PABSB128_MASK,
29811 IX86_BUILTIN_PABSW256_MASK,
29812 IX86_BUILTIN_PABSW128_MASK,
29813 IX86_BUILTIN_VPERMILVARPD_MASK,
29814 IX86_BUILTIN_VPERMILVARPS_MASK,
29815 IX86_BUILTIN_VPERMILVARPD256_MASK,
29816 IX86_BUILTIN_VPERMILVARPS256_MASK,
29817 IX86_BUILTIN_VPERMILPD_MASK,
29818 IX86_BUILTIN_VPERMILPS_MASK,
29819 IX86_BUILTIN_VPERMILPD256_MASK,
29820 IX86_BUILTIN_VPERMILPS256_MASK,
29821 IX86_BUILTIN_BLENDMQ256,
29822 IX86_BUILTIN_BLENDMD256,
29823 IX86_BUILTIN_BLENDMPD256,
29824 IX86_BUILTIN_BLENDMPS256,
29825 IX86_BUILTIN_BLENDMQ128,
29826 IX86_BUILTIN_BLENDMD128,
29827 IX86_BUILTIN_BLENDMPD128,
29828 IX86_BUILTIN_BLENDMPS128,
29829 IX86_BUILTIN_BLENDMW256,
29830 IX86_BUILTIN_BLENDMB256,
29831 IX86_BUILTIN_BLENDMW128,
29832 IX86_BUILTIN_BLENDMB128,
29833 IX86_BUILTIN_PMULLD256_MASK,
29834 IX86_BUILTIN_PMULLD128_MASK,
29835 IX86_BUILTIN_PMULUDQ256_MASK,
29836 IX86_BUILTIN_PMULDQ256_MASK,
29837 IX86_BUILTIN_PMULDQ128_MASK,
29838 IX86_BUILTIN_PMULUDQ128_MASK,
29839 IX86_BUILTIN_CVTPD2PS256_MASK,
29840 IX86_BUILTIN_CVTPD2PS_MASK,
29841 IX86_BUILTIN_VPERMVARSI256_MASK,
29842 IX86_BUILTIN_VPERMVARDI256_MASK,
29843 IX86_BUILTIN_VPERMDI256_MASK,
29844 IX86_BUILTIN_CMPQ256,
29845 IX86_BUILTIN_CMPD256,
29846 IX86_BUILTIN_UCMPQ256,
29847 IX86_BUILTIN_UCMPD256,
29848 IX86_BUILTIN_CMPB256,
29849 IX86_BUILTIN_CMPW256,
29850 IX86_BUILTIN_UCMPB256,
29851 IX86_BUILTIN_UCMPW256,
29852 IX86_BUILTIN_CMPPD256_MASK,
29853 IX86_BUILTIN_CMPPS256_MASK,
29854 IX86_BUILTIN_CMPQ128,
29855 IX86_BUILTIN_CMPD128,
29856 IX86_BUILTIN_UCMPQ128,
29857 IX86_BUILTIN_UCMPD128,
29858 IX86_BUILTIN_CMPB128,
29859 IX86_BUILTIN_CMPW128,
29860 IX86_BUILTIN_UCMPB128,
29861 IX86_BUILTIN_UCMPW128,
29862 IX86_BUILTIN_CMPPD128_MASK,
29863 IX86_BUILTIN_CMPPS128_MASK,
29865 IX86_BUILTIN_GATHER3SIV8SF,
29866 IX86_BUILTIN_GATHER3SIV4SF,
29867 IX86_BUILTIN_GATHER3SIV4DF,
29868 IX86_BUILTIN_GATHER3SIV2DF,
29869 IX86_BUILTIN_GATHER3DIV8SF,
29870 IX86_BUILTIN_GATHER3DIV4SF,
29871 IX86_BUILTIN_GATHER3DIV4DF,
29872 IX86_BUILTIN_GATHER3DIV2DF,
29873 IX86_BUILTIN_GATHER3SIV8SI,
29874 IX86_BUILTIN_GATHER3SIV4SI,
29875 IX86_BUILTIN_GATHER3SIV4DI,
29876 IX86_BUILTIN_GATHER3SIV2DI,
29877 IX86_BUILTIN_GATHER3DIV8SI,
29878 IX86_BUILTIN_GATHER3DIV4SI,
29879 IX86_BUILTIN_GATHER3DIV4DI,
29880 IX86_BUILTIN_GATHER3DIV2DI,
29881 IX86_BUILTIN_SCATTERSIV8SF,
29882 IX86_BUILTIN_SCATTERSIV4SF,
29883 IX86_BUILTIN_SCATTERSIV4DF,
29884 IX86_BUILTIN_SCATTERSIV2DF,
29885 IX86_BUILTIN_SCATTERDIV8SF,
29886 IX86_BUILTIN_SCATTERDIV4SF,
29887 IX86_BUILTIN_SCATTERDIV4DF,
29888 IX86_BUILTIN_SCATTERDIV2DF,
29889 IX86_BUILTIN_SCATTERSIV8SI,
29890 IX86_BUILTIN_SCATTERSIV4SI,
29891 IX86_BUILTIN_SCATTERSIV4DI,
29892 IX86_BUILTIN_SCATTERSIV2DI,
29893 IX86_BUILTIN_SCATTERDIV8SI,
29894 IX86_BUILTIN_SCATTERDIV4SI,
29895 IX86_BUILTIN_SCATTERDIV4DI,
29896 IX86_BUILTIN_SCATTERDIV2DI,
29898 /* AVX512DQ. */
29899 IX86_BUILTIN_RANGESD128,
29900 IX86_BUILTIN_RANGESS128,
29901 IX86_BUILTIN_KUNPCKWD,
29902 IX86_BUILTIN_KUNPCKDQ,
29903 IX86_BUILTIN_BROADCASTF32x2_512,
29904 IX86_BUILTIN_BROADCASTI32x2_512,
29905 IX86_BUILTIN_BROADCASTF64X2_512,
29906 IX86_BUILTIN_BROADCASTI64X2_512,
29907 IX86_BUILTIN_BROADCASTF32X8_512,
29908 IX86_BUILTIN_BROADCASTI32X8_512,
29909 IX86_BUILTIN_EXTRACTF64X2_512,
29910 IX86_BUILTIN_EXTRACTF32X8,
29911 IX86_BUILTIN_EXTRACTI64X2_512,
29912 IX86_BUILTIN_EXTRACTI32X8,
29913 IX86_BUILTIN_REDUCEPD512_MASK,
29914 IX86_BUILTIN_REDUCEPS512_MASK,
29915 IX86_BUILTIN_PMULLQ512,
29916 IX86_BUILTIN_XORPD512,
29917 IX86_BUILTIN_XORPS512,
29918 IX86_BUILTIN_ORPD512,
29919 IX86_BUILTIN_ORPS512,
29920 IX86_BUILTIN_ANDPD512,
29921 IX86_BUILTIN_ANDPS512,
29922 IX86_BUILTIN_ANDNPD512,
29923 IX86_BUILTIN_ANDNPS512,
29924 IX86_BUILTIN_INSERTF32X8,
29925 IX86_BUILTIN_INSERTI32X8,
29926 IX86_BUILTIN_INSERTF64X2_512,
29927 IX86_BUILTIN_INSERTI64X2_512,
29928 IX86_BUILTIN_FPCLASSPD512,
29929 IX86_BUILTIN_FPCLASSPS512,
29930 IX86_BUILTIN_CVTD2MASK512,
29931 IX86_BUILTIN_CVTQ2MASK512,
29932 IX86_BUILTIN_CVTMASK2D512,
29933 IX86_BUILTIN_CVTMASK2Q512,
29934 IX86_BUILTIN_CVTPD2QQ512,
29935 IX86_BUILTIN_CVTPS2QQ512,
29936 IX86_BUILTIN_CVTPD2UQQ512,
29937 IX86_BUILTIN_CVTPS2UQQ512,
29938 IX86_BUILTIN_CVTQQ2PS512,
29939 IX86_BUILTIN_CVTUQQ2PS512,
29940 IX86_BUILTIN_CVTQQ2PD512,
29941 IX86_BUILTIN_CVTUQQ2PD512,
29942 IX86_BUILTIN_CVTTPS2QQ512,
29943 IX86_BUILTIN_CVTTPS2UQQ512,
29944 IX86_BUILTIN_CVTTPD2QQ512,
29945 IX86_BUILTIN_CVTTPD2UQQ512,
29946 IX86_BUILTIN_RANGEPS512,
29947 IX86_BUILTIN_RANGEPD512,
29949 /* AVX512BW. */
29950 IX86_BUILTIN_PACKUSDW512,
29951 IX86_BUILTIN_PACKSSDW512,
29952 IX86_BUILTIN_LOADDQUHI512_MASK,
29953 IX86_BUILTIN_LOADDQUQI512_MASK,
29954 IX86_BUILTIN_PSLLDQ512,
29955 IX86_BUILTIN_PSRLDQ512,
29956 IX86_BUILTIN_STOREDQUHI512_MASK,
29957 IX86_BUILTIN_STOREDQUQI512_MASK,
29958 IX86_BUILTIN_PALIGNR512,
29959 IX86_BUILTIN_PALIGNR512_MASK,
29960 IX86_BUILTIN_MOVDQUHI512_MASK,
29961 IX86_BUILTIN_MOVDQUQI512_MASK,
29962 IX86_BUILTIN_PSADBW512,
29963 IX86_BUILTIN_DBPSADBW512,
29964 IX86_BUILTIN_PBROADCASTB512,
29965 IX86_BUILTIN_PBROADCASTB512_GPR,
29966 IX86_BUILTIN_PBROADCASTW512,
29967 IX86_BUILTIN_PBROADCASTW512_GPR,
29968 IX86_BUILTIN_PMOVSXBW512_MASK,
29969 IX86_BUILTIN_PMOVZXBW512_MASK,
29970 IX86_BUILTIN_VPERMVARHI512_MASK,
29971 IX86_BUILTIN_VPERMT2VARHI512,
29972 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
29973 IX86_BUILTIN_VPERMI2VARHI512,
29974 IX86_BUILTIN_PAVGB512,
29975 IX86_BUILTIN_PAVGW512,
29976 IX86_BUILTIN_PADDB512,
29977 IX86_BUILTIN_PSUBB512,
29978 IX86_BUILTIN_PSUBSB512,
29979 IX86_BUILTIN_PADDSB512,
29980 IX86_BUILTIN_PSUBUSB512,
29981 IX86_BUILTIN_PADDUSB512,
29982 IX86_BUILTIN_PSUBW512,
29983 IX86_BUILTIN_PADDW512,
29984 IX86_BUILTIN_PSUBSW512,
29985 IX86_BUILTIN_PADDSW512,
29986 IX86_BUILTIN_PSUBUSW512,
29987 IX86_BUILTIN_PADDUSW512,
29988 IX86_BUILTIN_PMAXUW512,
29989 IX86_BUILTIN_PMAXSW512,
29990 IX86_BUILTIN_PMINUW512,
29991 IX86_BUILTIN_PMINSW512,
29992 IX86_BUILTIN_PMAXUB512,
29993 IX86_BUILTIN_PMAXSB512,
29994 IX86_BUILTIN_PMINUB512,
29995 IX86_BUILTIN_PMINSB512,
29996 IX86_BUILTIN_PMOVWB512,
29997 IX86_BUILTIN_PMOVSWB512,
29998 IX86_BUILTIN_PMOVUSWB512,
29999 IX86_BUILTIN_PMULHRSW512_MASK,
30000 IX86_BUILTIN_PMULHUW512_MASK,
30001 IX86_BUILTIN_PMULHW512_MASK,
30002 IX86_BUILTIN_PMULLW512_MASK,
30003 IX86_BUILTIN_PSLLWI512_MASK,
30004 IX86_BUILTIN_PSLLW512_MASK,
30005 IX86_BUILTIN_PACKSSWB512,
30006 IX86_BUILTIN_PACKUSWB512,
30007 IX86_BUILTIN_PSRAVV32HI,
30008 IX86_BUILTIN_PMADDUBSW512_MASK,
30009 IX86_BUILTIN_PMADDWD512_MASK,
30010 IX86_BUILTIN_PSRLVV32HI,
30011 IX86_BUILTIN_PUNPCKHBW512,
30012 IX86_BUILTIN_PUNPCKHWD512,
30013 IX86_BUILTIN_PUNPCKLBW512,
30014 IX86_BUILTIN_PUNPCKLWD512,
30015 IX86_BUILTIN_PSHUFB512,
30016 IX86_BUILTIN_PSHUFHW512,
30017 IX86_BUILTIN_PSHUFLW512,
30018 IX86_BUILTIN_PSRAWI512,
30019 IX86_BUILTIN_PSRAW512,
30020 IX86_BUILTIN_PSRLWI512,
30021 IX86_BUILTIN_PSRLW512,
30022 IX86_BUILTIN_CVTB2MASK512,
30023 IX86_BUILTIN_CVTW2MASK512,
30024 IX86_BUILTIN_CVTMASK2B512,
30025 IX86_BUILTIN_CVTMASK2W512,
30026 IX86_BUILTIN_PCMPEQB512_MASK,
30027 IX86_BUILTIN_PCMPEQW512_MASK,
30028 IX86_BUILTIN_PCMPGTB512_MASK,
30029 IX86_BUILTIN_PCMPGTW512_MASK,
30030 IX86_BUILTIN_PTESTMB512,
30031 IX86_BUILTIN_PTESTMW512,
30032 IX86_BUILTIN_PTESTNMB512,
30033 IX86_BUILTIN_PTESTNMW512,
30034 IX86_BUILTIN_PSLLVV32HI,
30035 IX86_BUILTIN_PABSB512,
30036 IX86_BUILTIN_PABSW512,
30037 IX86_BUILTIN_BLENDMW512,
30038 IX86_BUILTIN_BLENDMB512,
30039 IX86_BUILTIN_CMPB512,
30040 IX86_BUILTIN_CMPW512,
30041 IX86_BUILTIN_UCMPB512,
30042 IX86_BUILTIN_UCMPW512,
30044 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30045 where all operands are 32-byte or 64-byte wide respectively. */
30046 IX86_BUILTIN_GATHERALTSIV4DF,
30047 IX86_BUILTIN_GATHERALTDIV8SF,
30048 IX86_BUILTIN_GATHERALTSIV4DI,
30049 IX86_BUILTIN_GATHERALTDIV8SI,
30050 IX86_BUILTIN_GATHER3ALTDIV16SF,
30051 IX86_BUILTIN_GATHER3ALTDIV16SI,
30052 IX86_BUILTIN_GATHER3ALTSIV4DF,
30053 IX86_BUILTIN_GATHER3ALTDIV8SF,
30054 IX86_BUILTIN_GATHER3ALTSIV4DI,
30055 IX86_BUILTIN_GATHER3ALTDIV8SI,
30056 IX86_BUILTIN_GATHER3ALTSIV8DF,
30057 IX86_BUILTIN_GATHER3ALTSIV8DI,
30058 IX86_BUILTIN_GATHER3DIV16SF,
30059 IX86_BUILTIN_GATHER3DIV16SI,
30060 IX86_BUILTIN_GATHER3DIV8DF,
30061 IX86_BUILTIN_GATHER3DIV8DI,
30062 IX86_BUILTIN_GATHER3SIV16SF,
30063 IX86_BUILTIN_GATHER3SIV16SI,
30064 IX86_BUILTIN_GATHER3SIV8DF,
30065 IX86_BUILTIN_GATHER3SIV8DI,
30066 IX86_BUILTIN_SCATTERDIV16SF,
30067 IX86_BUILTIN_SCATTERDIV16SI,
30068 IX86_BUILTIN_SCATTERDIV8DF,
30069 IX86_BUILTIN_SCATTERDIV8DI,
30070 IX86_BUILTIN_SCATTERSIV16SF,
30071 IX86_BUILTIN_SCATTERSIV16SI,
30072 IX86_BUILTIN_SCATTERSIV8DF,
30073 IX86_BUILTIN_SCATTERSIV8DI,
30075 /* AVX512PF */
30076 IX86_BUILTIN_GATHERPFQPD,
30077 IX86_BUILTIN_GATHERPFDPS,
30078 IX86_BUILTIN_GATHERPFDPD,
30079 IX86_BUILTIN_GATHERPFQPS,
30080 IX86_BUILTIN_SCATTERPFDPD,
30081 IX86_BUILTIN_SCATTERPFDPS,
30082 IX86_BUILTIN_SCATTERPFQPD,
30083 IX86_BUILTIN_SCATTERPFQPS,
30085 /* AVX-512ER */
30086 IX86_BUILTIN_EXP2PD_MASK,
30087 IX86_BUILTIN_EXP2PS_MASK,
30088 IX86_BUILTIN_EXP2PS,
30089 IX86_BUILTIN_RCP28PD,
30090 IX86_BUILTIN_RCP28PS,
30091 IX86_BUILTIN_RCP28SD,
30092 IX86_BUILTIN_RCP28SS,
30093 IX86_BUILTIN_RSQRT28PD,
30094 IX86_BUILTIN_RSQRT28PS,
30095 IX86_BUILTIN_RSQRT28SD,
30096 IX86_BUILTIN_RSQRT28SS,
30098 /* AVX-512IFMA */
30099 IX86_BUILTIN_VPMADD52LUQ512,
30100 IX86_BUILTIN_VPMADD52HUQ512,
30101 IX86_BUILTIN_VPMADD52LUQ256,
30102 IX86_BUILTIN_VPMADD52HUQ256,
30103 IX86_BUILTIN_VPMADD52LUQ128,
30104 IX86_BUILTIN_VPMADD52HUQ128,
30105 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30106 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30107 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30108 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30109 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30110 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30112 /* AVX-512VBMI */
30113 IX86_BUILTIN_VPMULTISHIFTQB512,
30114 IX86_BUILTIN_VPMULTISHIFTQB256,
30115 IX86_BUILTIN_VPMULTISHIFTQB128,
30116 IX86_BUILTIN_VPERMVARQI512_MASK,
30117 IX86_BUILTIN_VPERMT2VARQI512,
30118 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30119 IX86_BUILTIN_VPERMI2VARQI512,
30120 IX86_BUILTIN_VPERMVARQI256_MASK,
30121 IX86_BUILTIN_VPERMVARQI128_MASK,
30122 IX86_BUILTIN_VPERMT2VARQI256,
30123 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30124 IX86_BUILTIN_VPERMT2VARQI128,
30125 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30126 IX86_BUILTIN_VPERMI2VARQI256,
30127 IX86_BUILTIN_VPERMI2VARQI128,
30129 /* SHA builtins. */
30130 IX86_BUILTIN_SHA1MSG1,
30131 IX86_BUILTIN_SHA1MSG2,
30132 IX86_BUILTIN_SHA1NEXTE,
30133 IX86_BUILTIN_SHA1RNDS4,
30134 IX86_BUILTIN_SHA256MSG1,
30135 IX86_BUILTIN_SHA256MSG2,
30136 IX86_BUILTIN_SHA256RNDS2,
30138 /* CLWB instructions. */
30139 IX86_BUILTIN_CLWB,
30141 /* PCOMMIT instructions. */
30142 IX86_BUILTIN_PCOMMIT,
30144 /* CLFLUSHOPT instructions. */
30145 IX86_BUILTIN_CLFLUSHOPT,
30147 /* TFmode support builtins. */
30148 IX86_BUILTIN_INFQ,
30149 IX86_BUILTIN_HUGE_VALQ,
30150 IX86_BUILTIN_FABSQ,
30151 IX86_BUILTIN_COPYSIGNQ,
30153 /* Vectorizer support builtins. */
30154 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30155 IX86_BUILTIN_CPYSGNPS,
30156 IX86_BUILTIN_CPYSGNPD,
30157 IX86_BUILTIN_CPYSGNPS256,
30158 IX86_BUILTIN_CPYSGNPS512,
30159 IX86_BUILTIN_CPYSGNPD256,
30160 IX86_BUILTIN_CPYSGNPD512,
30161 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30162 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30165 /* FMA4 instructions. */
30166 IX86_BUILTIN_VFMADDSS,
30167 IX86_BUILTIN_VFMADDSD,
30168 IX86_BUILTIN_VFMADDPS,
30169 IX86_BUILTIN_VFMADDPD,
30170 IX86_BUILTIN_VFMADDPS256,
30171 IX86_BUILTIN_VFMADDPD256,
30172 IX86_BUILTIN_VFMADDSUBPS,
30173 IX86_BUILTIN_VFMADDSUBPD,
30174 IX86_BUILTIN_VFMADDSUBPS256,
30175 IX86_BUILTIN_VFMADDSUBPD256,
30177 /* FMA3 instructions. */
30178 IX86_BUILTIN_VFMADDSS3,
30179 IX86_BUILTIN_VFMADDSD3,
30181 /* XOP instructions. */
30182 IX86_BUILTIN_VPCMOV,
30183 IX86_BUILTIN_VPCMOV_V2DI,
30184 IX86_BUILTIN_VPCMOV_V4SI,
30185 IX86_BUILTIN_VPCMOV_V8HI,
30186 IX86_BUILTIN_VPCMOV_V16QI,
30187 IX86_BUILTIN_VPCMOV_V4SF,
30188 IX86_BUILTIN_VPCMOV_V2DF,
30189 IX86_BUILTIN_VPCMOV256,
30190 IX86_BUILTIN_VPCMOV_V4DI256,
30191 IX86_BUILTIN_VPCMOV_V8SI256,
30192 IX86_BUILTIN_VPCMOV_V16HI256,
30193 IX86_BUILTIN_VPCMOV_V32QI256,
30194 IX86_BUILTIN_VPCMOV_V8SF256,
30195 IX86_BUILTIN_VPCMOV_V4DF256,
30197 IX86_BUILTIN_VPPERM,
30199 IX86_BUILTIN_VPMACSSWW,
30200 IX86_BUILTIN_VPMACSWW,
30201 IX86_BUILTIN_VPMACSSWD,
30202 IX86_BUILTIN_VPMACSWD,
30203 IX86_BUILTIN_VPMACSSDD,
30204 IX86_BUILTIN_VPMACSDD,
30205 IX86_BUILTIN_VPMACSSDQL,
30206 IX86_BUILTIN_VPMACSSDQH,
30207 IX86_BUILTIN_VPMACSDQL,
30208 IX86_BUILTIN_VPMACSDQH,
30209 IX86_BUILTIN_VPMADCSSWD,
30210 IX86_BUILTIN_VPMADCSWD,
30212 IX86_BUILTIN_VPHADDBW,
30213 IX86_BUILTIN_VPHADDBD,
30214 IX86_BUILTIN_VPHADDBQ,
30215 IX86_BUILTIN_VPHADDWD,
30216 IX86_BUILTIN_VPHADDWQ,
30217 IX86_BUILTIN_VPHADDDQ,
30218 IX86_BUILTIN_VPHADDUBW,
30219 IX86_BUILTIN_VPHADDUBD,
30220 IX86_BUILTIN_VPHADDUBQ,
30221 IX86_BUILTIN_VPHADDUWD,
30222 IX86_BUILTIN_VPHADDUWQ,
30223 IX86_BUILTIN_VPHADDUDQ,
30224 IX86_BUILTIN_VPHSUBBW,
30225 IX86_BUILTIN_VPHSUBWD,
30226 IX86_BUILTIN_VPHSUBDQ,
30228 IX86_BUILTIN_VPROTB,
30229 IX86_BUILTIN_VPROTW,
30230 IX86_BUILTIN_VPROTD,
30231 IX86_BUILTIN_VPROTQ,
30232 IX86_BUILTIN_VPROTB_IMM,
30233 IX86_BUILTIN_VPROTW_IMM,
30234 IX86_BUILTIN_VPROTD_IMM,
30235 IX86_BUILTIN_VPROTQ_IMM,
30237 IX86_BUILTIN_VPSHLB,
30238 IX86_BUILTIN_VPSHLW,
30239 IX86_BUILTIN_VPSHLD,
30240 IX86_BUILTIN_VPSHLQ,
30241 IX86_BUILTIN_VPSHAB,
30242 IX86_BUILTIN_VPSHAW,
30243 IX86_BUILTIN_VPSHAD,
30244 IX86_BUILTIN_VPSHAQ,
30246 IX86_BUILTIN_VFRCZSS,
30247 IX86_BUILTIN_VFRCZSD,
30248 IX86_BUILTIN_VFRCZPS,
30249 IX86_BUILTIN_VFRCZPD,
30250 IX86_BUILTIN_VFRCZPS256,
30251 IX86_BUILTIN_VFRCZPD256,
30253 IX86_BUILTIN_VPCOMEQUB,
30254 IX86_BUILTIN_VPCOMNEUB,
30255 IX86_BUILTIN_VPCOMLTUB,
30256 IX86_BUILTIN_VPCOMLEUB,
30257 IX86_BUILTIN_VPCOMGTUB,
30258 IX86_BUILTIN_VPCOMGEUB,
30259 IX86_BUILTIN_VPCOMFALSEUB,
30260 IX86_BUILTIN_VPCOMTRUEUB,
30262 IX86_BUILTIN_VPCOMEQUW,
30263 IX86_BUILTIN_VPCOMNEUW,
30264 IX86_BUILTIN_VPCOMLTUW,
30265 IX86_BUILTIN_VPCOMLEUW,
30266 IX86_BUILTIN_VPCOMGTUW,
30267 IX86_BUILTIN_VPCOMGEUW,
30268 IX86_BUILTIN_VPCOMFALSEUW,
30269 IX86_BUILTIN_VPCOMTRUEUW,
30271 IX86_BUILTIN_VPCOMEQUD,
30272 IX86_BUILTIN_VPCOMNEUD,
30273 IX86_BUILTIN_VPCOMLTUD,
30274 IX86_BUILTIN_VPCOMLEUD,
30275 IX86_BUILTIN_VPCOMGTUD,
30276 IX86_BUILTIN_VPCOMGEUD,
30277 IX86_BUILTIN_VPCOMFALSEUD,
30278 IX86_BUILTIN_VPCOMTRUEUD,
30280 IX86_BUILTIN_VPCOMEQUQ,
30281 IX86_BUILTIN_VPCOMNEUQ,
30282 IX86_BUILTIN_VPCOMLTUQ,
30283 IX86_BUILTIN_VPCOMLEUQ,
30284 IX86_BUILTIN_VPCOMGTUQ,
30285 IX86_BUILTIN_VPCOMGEUQ,
30286 IX86_BUILTIN_VPCOMFALSEUQ,
30287 IX86_BUILTIN_VPCOMTRUEUQ,
30289 IX86_BUILTIN_VPCOMEQB,
30290 IX86_BUILTIN_VPCOMNEB,
30291 IX86_BUILTIN_VPCOMLTB,
30292 IX86_BUILTIN_VPCOMLEB,
30293 IX86_BUILTIN_VPCOMGTB,
30294 IX86_BUILTIN_VPCOMGEB,
30295 IX86_BUILTIN_VPCOMFALSEB,
30296 IX86_BUILTIN_VPCOMTRUEB,
30298 IX86_BUILTIN_VPCOMEQW,
30299 IX86_BUILTIN_VPCOMNEW,
30300 IX86_BUILTIN_VPCOMLTW,
30301 IX86_BUILTIN_VPCOMLEW,
30302 IX86_BUILTIN_VPCOMGTW,
30303 IX86_BUILTIN_VPCOMGEW,
30304 IX86_BUILTIN_VPCOMFALSEW,
30305 IX86_BUILTIN_VPCOMTRUEW,
30307 IX86_BUILTIN_VPCOMEQD,
30308 IX86_BUILTIN_VPCOMNED,
30309 IX86_BUILTIN_VPCOMLTD,
30310 IX86_BUILTIN_VPCOMLED,
30311 IX86_BUILTIN_VPCOMGTD,
30312 IX86_BUILTIN_VPCOMGED,
30313 IX86_BUILTIN_VPCOMFALSED,
30314 IX86_BUILTIN_VPCOMTRUED,
30316 IX86_BUILTIN_VPCOMEQQ,
30317 IX86_BUILTIN_VPCOMNEQ,
30318 IX86_BUILTIN_VPCOMLTQ,
30319 IX86_BUILTIN_VPCOMLEQ,
30320 IX86_BUILTIN_VPCOMGTQ,
30321 IX86_BUILTIN_VPCOMGEQ,
30322 IX86_BUILTIN_VPCOMFALSEQ,
30323 IX86_BUILTIN_VPCOMTRUEQ,
30325 /* LWP instructions. */
30326 IX86_BUILTIN_LLWPCB,
30327 IX86_BUILTIN_SLWPCB,
30328 IX86_BUILTIN_LWPVAL32,
30329 IX86_BUILTIN_LWPVAL64,
30330 IX86_BUILTIN_LWPINS32,
30331 IX86_BUILTIN_LWPINS64,
30333 IX86_BUILTIN_CLZS,
30335 /* RTM */
30336 IX86_BUILTIN_XBEGIN,
30337 IX86_BUILTIN_XEND,
30338 IX86_BUILTIN_XABORT,
30339 IX86_BUILTIN_XTEST,
30341 /* MPX */
30342 IX86_BUILTIN_BNDMK,
30343 IX86_BUILTIN_BNDSTX,
30344 IX86_BUILTIN_BNDLDX,
30345 IX86_BUILTIN_BNDCL,
30346 IX86_BUILTIN_BNDCU,
30347 IX86_BUILTIN_BNDRET,
30348 IX86_BUILTIN_BNDNARROW,
30349 IX86_BUILTIN_BNDINT,
30350 IX86_BUILTIN_SIZEOF,
30351 IX86_BUILTIN_BNDLOWER,
30352 IX86_BUILTIN_BNDUPPER,
30354 /* BMI instructions. */
30355 IX86_BUILTIN_BEXTR32,
30356 IX86_BUILTIN_BEXTR64,
30357 IX86_BUILTIN_CTZS,
30359 /* TBM instructions. */
30360 IX86_BUILTIN_BEXTRI32,
30361 IX86_BUILTIN_BEXTRI64,
30363 /* BMI2 instructions. */
30364 IX86_BUILTIN_BZHI32,
30365 IX86_BUILTIN_BZHI64,
30366 IX86_BUILTIN_PDEP32,
30367 IX86_BUILTIN_PDEP64,
30368 IX86_BUILTIN_PEXT32,
30369 IX86_BUILTIN_PEXT64,
30371 /* ADX instructions. */
30372 IX86_BUILTIN_ADDCARRYX32,
30373 IX86_BUILTIN_ADDCARRYX64,
30375 /* SBB instructions. */
30376 IX86_BUILTIN_SBB32,
30377 IX86_BUILTIN_SBB64,
30379 /* FSGSBASE instructions. */
30380 IX86_BUILTIN_RDFSBASE32,
30381 IX86_BUILTIN_RDFSBASE64,
30382 IX86_BUILTIN_RDGSBASE32,
30383 IX86_BUILTIN_RDGSBASE64,
30384 IX86_BUILTIN_WRFSBASE32,
30385 IX86_BUILTIN_WRFSBASE64,
30386 IX86_BUILTIN_WRGSBASE32,
30387 IX86_BUILTIN_WRGSBASE64,
30389 /* RDRND instructions. */
30390 IX86_BUILTIN_RDRAND16_STEP,
30391 IX86_BUILTIN_RDRAND32_STEP,
30392 IX86_BUILTIN_RDRAND64_STEP,
30394 /* RDSEED instructions. */
30395 IX86_BUILTIN_RDSEED16_STEP,
30396 IX86_BUILTIN_RDSEED32_STEP,
30397 IX86_BUILTIN_RDSEED64_STEP,
30399 /* F16C instructions. */
30400 IX86_BUILTIN_CVTPH2PS,
30401 IX86_BUILTIN_CVTPH2PS256,
30402 IX86_BUILTIN_CVTPS2PH,
30403 IX86_BUILTIN_CVTPS2PH256,
30405 /* CFString built-in for darwin */
30406 IX86_BUILTIN_CFSTRING,
30408 /* Builtins to get CPU type and supported features. */
30409 IX86_BUILTIN_CPU_INIT,
30410 IX86_BUILTIN_CPU_IS,
30411 IX86_BUILTIN_CPU_SUPPORTS,
30413 /* Read/write FLAGS register built-ins. */
30414 IX86_BUILTIN_READ_FLAGS,
30415 IX86_BUILTIN_WRITE_FLAGS,
30417 IX86_BUILTIN_MAX
30418 };
30420 /* Table for the ix86 builtin decls. */
30423 /* Table of all of the builtin functions that are possible with different ISA's
30424 but are waiting to be built until a function is declared to use that
30425 ISA. */
30434 };
30439 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30440 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30441 function decl in the ix86_builtins array. Returns the function decl or
30442 NULL_TREE, if the builtin was not added.
30444 If the front end has a special hook for builtin functions, delay adding
30445 builtin functions that aren't in the current ISA until the ISA is changed
30446 with function specific optimization. Doing so, can save about 300K for the
30447 default compiler. When the builtin is expanded, check at that time whether
30448 it is valid.
30450 If the front end doesn't have a special hook, record all builtins, even if
30451 it isn't an instruction set in the current ISA in case the user uses
30452 function specific options for a different ISA, so that we don't get scope
30453 errors if a builtin is added in the middle of a function scope. */
30459 {
30463 {
30472 {
30478 }
30479 else
30480 {
30488 }
30489 }
30492 }
30494 /* Like def_builtin, but also marks the function decl "const". */
30499 {
30503 else
30507 }
30509 /* Add any new builtin functions for a given ISA that may not have been
30510 declared. This saves a bit of space compared to adding all of the
30511 declarations to the tree, even if we didn't use them. */
30513 static void
30515 {
30519 {
30522 {
30525 /* Don't define the builtin again. */
30531 NULL_TREE);
30538 NULL_TREE);
30541 }
30542 }
30543 }
30545 /* Bits for builtin_description.flag. */
30547 /* Set when we don't support the comparison natively, and should
30548 swap_comparison in order to support it. */
30549 #define BUILTIN_DESC_SWAP_OPERANDS 1
30551 struct builtin_description
30552 {
30559 };
30562 {
30563 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30564 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30565 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30566 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30567 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30568 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30569 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30570 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30571 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30572 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30573 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30574 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30577 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30581 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30587 };
30590 {
30591 /* SSE4.2 */
30592 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30593 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30594 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30595 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30596 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30597 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30598 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30599 };
30602 {
30603 /* SSE4.2 */
30604 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30605 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30606 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30607 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30608 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30609 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30610 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30611 };
30613 /* Special builtins with variable number of arguments. */
30615 {
30616 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30617 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30618 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30620 /* 80387 (for use internally for atomic compound assignment). */
30621 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30622 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30623 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30624 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30626 /* MMX */
30627 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30629 /* 3DNow! */
30630 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30632 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30633 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30634 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30635 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30636 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30637 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30638 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30639 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30640 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30642 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30643 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30644 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30645 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30646 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30647 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30648 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30649 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30651 /* SSE */
30652 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30653 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30654 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30656 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30657 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30658 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30659 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30661 /* SSE or 3DNow!A */
30662 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30663 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30665 /* SSE2 */
30666 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30667 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30668 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30669 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30670 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30671 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30672 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30673 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30674 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30675 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30677 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30678 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30680 /* SSE3 */
30681 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30683 /* SSE4.1 */
30684 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30686 /* SSE4A */
30687 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30688 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30690 /* AVX */
30691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30694 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30695 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30696 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30721 /* AVX2 */
30722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30730 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30732 /* AVX512F */
30733 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30734 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30735 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30736 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30737 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30738 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30739 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30740 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30741 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30742 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30743 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30744 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30745 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30746 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30747 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30748 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30749 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30750 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30751 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30752 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30753 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30754 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30755 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30756 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30757 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30758 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30759 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30760 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30781 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30782 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30783 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30784 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30785 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30786 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30788 /* FSGSBASE */
30789 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30790 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30791 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30792 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30793 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30794 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30795 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30796 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30798 /* RTM */
30799 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30800 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30801 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30803 /* AVX512BW */
30804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30809 /* AVX512VL */
30810 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30811 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30812 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30813 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30816 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30817 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30818 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30819 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30824 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30825 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30847 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30848 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30849 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30905 /* PCOMMIT. */
30906 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
30907 };
30909 /* Builtins with variable number of arguments. */
30911 {
30912 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30913 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30914 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30915 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30916 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30917 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30918 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30920 /* MMX */
30921 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30922 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30923 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30924 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30925 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30926 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30928 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30929 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30930 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30931 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30932 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30933 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30934 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30935 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30937 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30938 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30940 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30941 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30942 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30943 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30945 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30946 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30947 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30948 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30949 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30950 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30952 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30953 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30954 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30955 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30956 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
30957 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
30959 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30960 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
30961 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30963 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
30965 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30966 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30967 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30974 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30979 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30982 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30984 /* 3DNow! */
30985 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30986 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30987 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30988 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30990 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30991 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30992 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30993 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30994 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30995 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30996 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30997 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30998 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30999 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31000 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31001 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31002 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31003 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31004 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31006 /* 3DNow!A */
31007 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31008 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31009 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31010 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31011 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31012 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31014 /* SSE */
31015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31017 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31019 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31023 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31026 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31030 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31031 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31032 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31033 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31034 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31035 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31036 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31037 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31039 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31040 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31041 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31042 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31043 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31044 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31045 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31046 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31047 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31048 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31049 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31050 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31051 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31052 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31053 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31054 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31055 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31056 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31057 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31058 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31060 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31061 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31062 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31065 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31066 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31067 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31068 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31070 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31072 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31075 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31076 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31078 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31080 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31082 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31088 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31089 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31091 /* SSE MMX or 3Dnow!A */
31092 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31093 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31094 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31096 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31097 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31098 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31099 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31101 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31102 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31104 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31106 /* SSE2 */
31107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31113 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31116 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31125 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31126 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31129 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31130 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31132 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31133 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31134 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31135 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31139 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31152 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31163 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31167 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31169 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31170 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31172 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31175 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31176 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31178 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31180 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31181 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31182 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31183 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31184 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31185 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31186 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31187 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31199 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31201 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31203 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31204 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31216 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31217 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31218 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31221 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31222 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31223 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31224 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31225 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31226 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31227 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31228 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31234 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31238 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31243 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31247 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31248 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31249 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31250 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31251 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31252 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31253 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31255 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31256 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31257 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31258 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31259 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31260 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31261 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31263 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31264 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31265 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31266 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31276 /* SSE2 MMX */
31277 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31278 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31280 /* SSE3 */
31281 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31282 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31284 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31285 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31286 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31287 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31288 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31289 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31291 /* SSSE3 */
31292 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31293 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31294 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31295 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31296 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31297 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31299 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31300 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31301 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31302 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31303 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31304 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31305 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31306 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31307 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31308 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31309 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31310 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31311 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31312 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31313 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31314 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31315 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31316 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31317 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31318 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31319 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31320 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31321 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31322 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31324 /* SSSE3. */
31325 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31326 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31328 /* SSE4.1 */
31329 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31330 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31331 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31332 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31333 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31334 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31335 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31336 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31337 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31338 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31340 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31341 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31342 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31343 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31344 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31345 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31346 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31347 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31348 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31349 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31350 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31351 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31352 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31354 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31355 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31356 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31357 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31358 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31359 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31360 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31361 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31362 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31363 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31364 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31365 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31367 /* SSE4.1 */
31368 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31369 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31370 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31371 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31373 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31374 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31375 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31376 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31378 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31379 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31381 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31382 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31384 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31385 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31386 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31387 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31389 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31390 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31392 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31393 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31395 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31396 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31397 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31399 /* SSE4.2 */
31400 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31401 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31402 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31403 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31404 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31406 /* SSE4A */
31407 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31408 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31409 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31410 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31412 /* AES */
31413 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31414 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31416 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31417 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31418 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31419 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31421 /* PCLMUL */
31422 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31424 /* AVX */
31425 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31426 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31429 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31430 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31433 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31439 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31440 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31441 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31442 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31443 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31444 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31445 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31446 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31447 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31448 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31449 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31450 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31452 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31453 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31454 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31455 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31457 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31458 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31460 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31461 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31462 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31463 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31467 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31468 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31470 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31471 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31472 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31473 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31474 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31475 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31476 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31477 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31478 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31479 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31480 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31481 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31482 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31483 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31484 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31485 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31487 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31488 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31489 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31490 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31492 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31493 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31494 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31496 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31497 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31498 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31500 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31512 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31513 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31526 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31527 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31537 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31538 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31539 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31560 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31561 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31563 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31565 /* AVX2 */
31566 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31567 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31568 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31569 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31570 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31571 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31572 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31573 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31574 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31575 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31576 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31577 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31578 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31579 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31580 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31581 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31582 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31583 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31584 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31585 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31586 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31587 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31588 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31589 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31590 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31591 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31592 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31593 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31594 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31595 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31596 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31597 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31598 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31599 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31600 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31601 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31602 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31603 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31604 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31605 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31606 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31607 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31608 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31609 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31610 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31611 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31612 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31613 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31614 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31615 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31616 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31617 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31618 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31619 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31620 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31621 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31622 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31623 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31624 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31625 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31626 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31627 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31628 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31629 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31630 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31631 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31632 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31633 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31634 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31635 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31636 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31637 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31642 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31643 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31644 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31647 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31648 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31649 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31650 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31651 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31652 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31653 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31654 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31655 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31656 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31658 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31659 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31660 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31661 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31662 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31663 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31664 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31665 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31666 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31667 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31680 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31682 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31683 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31701 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31713 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31715 /* BMI */
31716 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31717 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31718 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31720 /* TBM */
31721 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31722 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31724 /* F16C */
31725 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31726 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31727 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31728 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31730 /* BMI2 */
31731 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31732 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31733 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31734 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31735 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31736 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31738 /* AVX512F */
31739 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31740 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31741 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31742 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31743 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31744 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31745 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31746 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31747 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31748 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31749 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31750 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31751 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31752 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31753 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31754 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31755 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31756 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31757 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31758 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31759 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31760 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31794 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31795 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31797 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31798 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31906 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31907 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31908 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31909 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31941 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31946 /* Mask arithmetic operations */
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
31958 /* SHA */
31959 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
31967 /* AVX512VL. */
31968 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
31969 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
31970 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
31971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
31973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31978 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
31979 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
31980 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
31981 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31982 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31983 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31984 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31985 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31988 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31989 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31990 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31991 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31992 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31993 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31994 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31995 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32006 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32007 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32008 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32009 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32010 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32011 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32012 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32013 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32014 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32015 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32016 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32017 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32018 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32023 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32024 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32025 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32026 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32027 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32028 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32029 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32030 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32031 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32032 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32035 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32036 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32037 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32038 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32043 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32044 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32045 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32059 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32060 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32061 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32062 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32063 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32064 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32065 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32066 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32072 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32073 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32075 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32076 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32080 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32081 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32084 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32085 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32096 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32097 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32099 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32100 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32101 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32102 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32103 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32105 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32106 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32108 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32109 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32110 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32111 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32112 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32113 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32114 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32115 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32116 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32117 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32118 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32119 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32120 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32121 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32134 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32135 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32136 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32137 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32138 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32139 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32142 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32143 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32144 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32145 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32146 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32147 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32148 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32149 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32150 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32151 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32154 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32155 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32156 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32157 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32158 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32159 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32162 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32163 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32164 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32165 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32170 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32171 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32172 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32173 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32174 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32175 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32206 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32207 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32208 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32209 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32226 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32227 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32228 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32229 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32230 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32231 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32232 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32233 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32234 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32235 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32236 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32237 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32238 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32239 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32240 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32241 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32242 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32243 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32244 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32247 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32250 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32251 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32288 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32289 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32290 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32291 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32304 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32311 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32312 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32313 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32314 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32315 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32316 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32352 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32353 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32354 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32355 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32356 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32357 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32358 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32359 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32360 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32361 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32366 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32367 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32368 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32369 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32380 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32381 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32382 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32383 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32384 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32385 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32386 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32387 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32412 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32413 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32414 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32415 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32416 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32417 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32441 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32444 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32445 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32446 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32447 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32448 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32449 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32450 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32451 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32460 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32461 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32462 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32463 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32464 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32465 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32466 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32467 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32468 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32469 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32470 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32471 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32472 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32473 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32474 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32475 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32476 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32477 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32478 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32479 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32480 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32481 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32482 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32483 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32492 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32493 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32498 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32506 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32507 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32508 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32509 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32514 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32515 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32516 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32517 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32549 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32558 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32559 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32560 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32561 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32562 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32563 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32564 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32565 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32566 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32567 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32568 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32569 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32570 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32571 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32572 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32574 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32575 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32576 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32577 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32583 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32585 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32586 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32587 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32588 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32606 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32607 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32608 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32609 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32610 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32611 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32612 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32613 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32614 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32615 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32616 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32617 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32618 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32619 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32620 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32621 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32622 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32623 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32627 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32628 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32629 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32630 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32641 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32642 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32643 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32644 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32645 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32646 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32648 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32649 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32650 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32666 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32667 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32668 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32669 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32676 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32677 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32678 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32679 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32683 /* AVX512DQ. */
32684 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32685 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32686 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32687 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32688 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32689 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32690 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32691 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32692 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32693 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32694 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32695 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32696 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32697 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32698 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32699 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32700 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32701 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32702 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32703 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32704 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32705 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32706 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32707 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32708 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32709 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32710 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32711 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32712 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32713 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32714 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32716 /* AVX512BW. */
32717 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32718 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32719 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32720 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32721 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32722 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32723 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32724 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32725 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32726 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32727 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32728 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32729 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32730 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32731 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32732 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32733 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32734 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32735 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32736 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32737 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32738 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32739 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32740 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32741 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32742 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32743 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32744 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32745 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32746 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32747 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32748 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32749 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32750 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32751 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32752 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32753 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32754 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32755 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32756 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32757 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32758 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32759 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32760 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32761 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32762 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32763 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32764 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32765 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32766 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32767 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32768 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32769 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32770 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32771 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32772 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32773 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32774 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32775 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32776 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32777 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32778 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32779 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32780 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32781 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32782 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32783 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32784 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32785 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32786 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32787 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32788 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32789 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32790 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32791 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32792 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32793 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32794 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32795 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32796 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32797 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32798 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32799 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32800 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32801 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32802 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32803 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32809 /* AVX512IFMA */
32810 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32811 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32812 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32813 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32814 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32815 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32816 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32817 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32818 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32819 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32820 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32821 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32823 /* AVX512VBMI */
32824 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32825 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32826 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32827 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32828 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32829 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32830 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32831 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32832 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32833 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32834 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32835 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32836 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32837 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32838 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32839 };
32841 /* Builtins with rounding support. */
32843 {
32844 /* AVX512F */
32845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32864 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32866 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32873 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32875 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32925 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32927 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32929 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32931 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32933 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32935 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32937 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32939 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
32947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
32948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32965 /* AVX512ER */
32966 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32967 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32968 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32969 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32970 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32971 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32972 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32973 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32974 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32975 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32977 /* AVX512DQ. */
32978 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32979 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32980 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32981 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32982 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32983 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32984 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32985 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32986 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32987 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32988 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32989 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32990 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32991 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32992 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
32993 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
32994 };
32996 /* Bultins for MPX. */
32998 {
32999 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33000 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33001 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33002 };
33004 /* Const builtins for MPX. */
33006 {
33007 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33008 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33009 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33010 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33011 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33012 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33013 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33014 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33015 };
33017 /* FMA4 and XOP. */
33018 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33019 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33020 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33021 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33022 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33023 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33024 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33025 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33026 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33027 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33028 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33029 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33030 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33031 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33032 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33033 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33034 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33035 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33036 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33037 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33038 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33039 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33040 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33041 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33042 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33043 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33044 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33045 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33046 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33047 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33048 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33049 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33050 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33051 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33052 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33053 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33054 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33055 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33056 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33057 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33058 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33059 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33060 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33061 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33062 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33063 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33064 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33065 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33066 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33067 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33068 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33069 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33072 {
33113 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33114 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33115 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33116 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33117 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33118 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33119 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33121 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33122 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33123 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33124 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33125 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33126 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33127 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33129 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33131 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33132 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33133 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33134 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33135 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33136 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33137 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33138 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33139 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33140 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33141 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33142 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33144 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33145 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33146 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33147 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33148 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33149 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33150 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33151 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33152 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33153 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33154 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33155 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33156 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33157 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33158 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33159 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33161 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33162 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33163 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33164 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33165 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33166 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33168 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33169 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33170 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33171 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33172 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33173 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33174 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33175 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33176 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33177 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33178 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33179 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33180 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33181 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33182 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33184 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33185 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33186 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33187 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33188 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33189 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33190 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33192 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33193 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33194 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33195 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33197 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33200 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33202 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33203 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33204 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33208 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33211 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33212 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33213 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33216 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33217 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33218 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33224 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33226 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33229 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33232 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33234 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33236 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33240 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33241 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33242 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33243 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33248 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33250 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33252 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33266 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33271 };
33272 \f
33273 /* TM vector builtins. */
33275 /* Reuse the existing x86-specific `struct builtin_description' cause
33276 we're lazy. Add casts to make them fit. */
33278 {
33279 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33280 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33281 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33282 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33283 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33284 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33285 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33287 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33288 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33289 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33290 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33291 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33292 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33293 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33295 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33296 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33297 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33298 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33299 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33300 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33301 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33303 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33304 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33305 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33306 };
33308 /* TM callbacks. */
33310 /* Return the builtin decl needed to load a vector of TYPE. */
33312 static tree
33314 {
33316 {
33318 {
33325 }
33326 }
33328 }
33330 /* Return the builtin decl needed to store a vector of TYPE. */
33332 static tree
33334 {
33336 {
33338 {
33345 }
33346 }
33348 }
33349 \f
33350 /* Initialize the transactional memory vector load/store builtins. */
33352 static void
33354 {
33358 tree decl;
33365 /* If there are no builtins defined, we must be compiling in a
33366 language without trans-mem support. */
33370 /* Use whatever attributes a normal TM load has. */
33374 /* Use whatever attributes a normal TM store has. */
33378 /* Use whatever attributes a normal TM log has. */
33386 {
33390 {
33398 {
33401 }
33403 {
33406 }
33407 else
33408 {
33411 }
33413 /* The builtin without the prefix for
33414 calling it directly. */
33416 attrs);
33417 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33418 set the TYPE_ATTRIBUTES. */
33422 }
33423 }
33424 }
33426 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33427 in the current target ISA to allow the user to compile particular modules
33428 with different target specific options that differ from the command line
33429 options. */
33430 static void
33432 {
33437 /* Add all special builtins with variable number of operands. */
33441 {
33447 }
33449 /* Add all builtins with variable number of operands. */
33453 {
33459 }
33461 /* Add all builtins with rounding. */
33465 {
33471 }
33473 /* pcmpestr[im] insns. */
33477 {
33480 else
33483 }
33485 /* pcmpistr[im] insns. */
33489 {
33492 else
33495 }
33497 /* comi/ucomi insns. */
33499 {
33502 else
33505 }
33507 /* SSE */
33513 /* SSE or 3DNow!A */
33516 IX86_BUILTIN_MASKMOVQ);
33518 /* SSE2 */
33527 /* SSE3. */
33533 /* AES */
33547 /* PCLMUL */
33551 /* RDRND */
33558 IX86_BUILTIN_RDRAND64_STEP);
33560 /* AVX2 */
33562 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33563 IX86_BUILTIN_GATHERSIV2DF);
33566 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33567 IX86_BUILTIN_GATHERSIV4DF);
33570 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33571 IX86_BUILTIN_GATHERDIV2DF);
33574 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33575 IX86_BUILTIN_GATHERDIV4DF);
33578 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33579 IX86_BUILTIN_GATHERSIV4SF);
33582 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33583 IX86_BUILTIN_GATHERSIV8SF);
33586 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33587 IX86_BUILTIN_GATHERDIV4SF);
33590 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33591 IX86_BUILTIN_GATHERDIV8SF);
33594 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33595 IX86_BUILTIN_GATHERSIV2DI);
33598 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33599 IX86_BUILTIN_GATHERSIV4DI);
33602 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33603 IX86_BUILTIN_GATHERDIV2DI);
33606 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33607 IX86_BUILTIN_GATHERDIV4DI);
33610 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33611 IX86_BUILTIN_GATHERSIV4SI);
33614 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33615 IX86_BUILTIN_GATHERSIV8SI);
33618 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33619 IX86_BUILTIN_GATHERDIV4SI);
33622 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33623 IX86_BUILTIN_GATHERDIV8SI);
33626 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33627 IX86_BUILTIN_GATHERALTSIV4DF);
33630 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33631 IX86_BUILTIN_GATHERALTDIV8SF);
33634 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33635 IX86_BUILTIN_GATHERALTSIV4DI);
33638 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33639 IX86_BUILTIN_GATHERALTDIV8SI);
33641 /* AVX512F */
33643 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33644 IX86_BUILTIN_GATHER3SIV16SF);
33647 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33648 IX86_BUILTIN_GATHER3SIV8DF);
33651 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33652 IX86_BUILTIN_GATHER3DIV16SF);
33655 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33656 IX86_BUILTIN_GATHER3DIV8DF);
33659 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33660 IX86_BUILTIN_GATHER3SIV16SI);
33663 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33664 IX86_BUILTIN_GATHER3SIV8DI);
33667 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33668 IX86_BUILTIN_GATHER3DIV16SI);
33671 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33672 IX86_BUILTIN_GATHER3DIV8DI);
33675 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33676 IX86_BUILTIN_GATHER3ALTSIV8DF);
33679 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33680 IX86_BUILTIN_GATHER3ALTDIV16SF);
33683 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33684 IX86_BUILTIN_GATHER3ALTSIV8DI);
33687 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33688 IX86_BUILTIN_GATHER3ALTDIV16SI);
33691 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33692 IX86_BUILTIN_SCATTERSIV16SF);
33695 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33696 IX86_BUILTIN_SCATTERSIV8DF);
33699 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33700 IX86_BUILTIN_SCATTERDIV16SF);
33703 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33704 IX86_BUILTIN_SCATTERDIV8DF);
33707 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33708 IX86_BUILTIN_SCATTERSIV16SI);
33711 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33712 IX86_BUILTIN_SCATTERSIV8DI);
33715 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33716 IX86_BUILTIN_SCATTERDIV16SI);
33719 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33720 IX86_BUILTIN_SCATTERDIV8DI);
33722 /* AVX512VL */
33724 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33725 IX86_BUILTIN_GATHER3SIV2DF);
33728 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33729 IX86_BUILTIN_GATHER3SIV4DF);
33732 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33733 IX86_BUILTIN_GATHER3DIV2DF);
33736 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33737 IX86_BUILTIN_GATHER3DIV4DF);
33740 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33741 IX86_BUILTIN_GATHER3SIV4SF);
33744 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33745 IX86_BUILTIN_GATHER3SIV8SF);
33748 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33749 IX86_BUILTIN_GATHER3DIV4SF);
33752 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33753 IX86_BUILTIN_GATHER3DIV8SF);
33756 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33757 IX86_BUILTIN_GATHER3SIV2DI);
33760 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33761 IX86_BUILTIN_GATHER3SIV4DI);
33764 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33765 IX86_BUILTIN_GATHER3DIV2DI);
33768 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33769 IX86_BUILTIN_GATHER3DIV4DI);
33772 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33773 IX86_BUILTIN_GATHER3SIV4SI);
33776 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33777 IX86_BUILTIN_GATHER3SIV8SI);
33780 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33781 IX86_BUILTIN_GATHER3DIV4SI);
33784 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33785 IX86_BUILTIN_GATHER3DIV8SI);
33788 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33789 IX86_BUILTIN_GATHER3ALTSIV4DF);
33792 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33793 IX86_BUILTIN_GATHER3ALTDIV8SF);
33796 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33797 IX86_BUILTIN_GATHER3ALTSIV4DI);
33800 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33801 IX86_BUILTIN_GATHER3ALTDIV8SI);
33804 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33805 IX86_BUILTIN_SCATTERSIV8SF);
33808 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33809 IX86_BUILTIN_SCATTERSIV4SF);
33812 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33813 IX86_BUILTIN_SCATTERSIV4DF);
33816 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33817 IX86_BUILTIN_SCATTERSIV2DF);
33820 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33821 IX86_BUILTIN_SCATTERDIV8SF);
33824 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33825 IX86_BUILTIN_SCATTERDIV4SF);
33828 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33829 IX86_BUILTIN_SCATTERDIV4DF);
33832 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33833 IX86_BUILTIN_SCATTERDIV2DF);
33836 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33837 IX86_BUILTIN_SCATTERSIV8SI);
33840 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33841 IX86_BUILTIN_SCATTERSIV4SI);
33844 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33845 IX86_BUILTIN_SCATTERSIV4DI);
33848 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33849 IX86_BUILTIN_SCATTERSIV2DI);
33852 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33853 IX86_BUILTIN_SCATTERDIV8SI);
33856 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33857 IX86_BUILTIN_SCATTERDIV4SI);
33860 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33861 IX86_BUILTIN_SCATTERDIV4DI);
33864 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33865 IX86_BUILTIN_SCATTERDIV2DI);
33867 /* AVX512PF */
33869 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33870 IX86_BUILTIN_GATHERPFDPD);
33872 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33873 IX86_BUILTIN_GATHERPFDPS);
33875 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33876 IX86_BUILTIN_GATHERPFQPD);
33878 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33879 IX86_BUILTIN_GATHERPFQPS);
33881 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33882 IX86_BUILTIN_SCATTERPFDPD);
33884 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33885 IX86_BUILTIN_SCATTERPFDPS);
33887 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33888 IX86_BUILTIN_SCATTERPFQPD);
33890 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33891 IX86_BUILTIN_SCATTERPFQPS);
33893 /* SHA */
33909 /* RTM. */
33913 /* MMX access to the vec_init patterns. */
33918 V4HI_FTYPE_HI_HI_HI_HI,
33919 IX86_BUILTIN_VEC_INIT_V4HI);
33922 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33923 IX86_BUILTIN_VEC_INIT_V8QI);
33925 /* Access to the vec_extract patterns. */
33947 /* Access to the vec_set patterns. */
33968 /* RDSEED */
33977 /* ADCX */
33982 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33983 IX86_BUILTIN_ADDCARRYX64);
33985 /* SBB */
33990 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33991 IX86_BUILTIN_SBB64);
33993 /* Read/write FLAGS. */
34003 /* CLFLUSHOPT. */
34007 /* CLWB. */
34011 /* Add FMA4 multi-arg argument instructions */
34013 {
34019 }
34020 }
34022 static void
34024 {
34027 tree decl;
34033 {
34040 /* With no leaf and nothrow flags for MPX builtins
34041 abnormal edges may follow its call when setjmp
34042 presents in the function. Since we may have a lot
34043 of MPX builtins calls it causes lots of useless
34044 edges and enormous PHI nodes. To avoid this we mark
34045 MPX builtins as leaf and nothrow. */
34047 {
34049 NULL_TREE);
34051 }
34052 else
34053 {
34056 }
34057 }
34062 {
34070 {
34072 NULL_TREE);
34074 }
34075 else
34076 {
34079 }
34080 }
34081 }
34083 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34084 to return a pointer to VERSION_DECL if the outcome of the expression
34085 formed by PREDICATE_CHAIN is true. This function will be called during
34086 version dispatch to decide which function version to execute. It returns
34087 the basic block at the end, to which more conditions can be added. */
34089 static basic_block
34092 {
34093 gimple return_stmt;
34095 gimple convert_stmt;
34096 gimple call_cond_stmt;
34097 gimple if_else_stmt;
34103 gimple_seq gseq;
34120 {
34128 }
34131 {
34146 else
34147 {
34148 gimple assign_stmt;
34149 /* Use MIN_EXPR to check if any integer is zero?.
34150 and_expr_var = min_expr <cond_var, and_expr_var> */
34158 }
34159 }
34162 integer_zero_node,
34192 }
34194 /* This parses the attribute arguments to target in DECL and determines
34195 the right builtin to use to match the platform specification.
34196 It returns the priority value for this version decl. If PREDICATE_LIST
34197 is not NULL, it stores the list of cpu features that need to be checked
34198 before dispatching this function. */
34200 static unsigned int
34202 {
34203 tree attrs;
34205 tree target_node;
34212 /* Priority of i386 features, greater value is higher priority. This is
34213 used to decide the order in which function dispatch must happen. For
34214 instance, a version specialized for SSE4.2 should be checked for dispatch
34215 before a version for SSE3, as SSE4.2 implies SSE3. */
34216 enum feature_priority
34217 {
34219 P_MMX,
34220 P_SSE,
34221 P_SSE2,
34222 P_SSE3,
34223 P_SSSE3,
34224 P_PROC_SSSE3,
34225 P_SSE4_A,
34226 P_PROC_SSE4_A,
34227 P_SSE4_1,
34228 P_SSE4_2,
34229 P_PROC_SSE4_2,
34230 P_POPCNT,
34231 P_AVX,
34232 P_PROC_AVX,
34233 P_FMA4,
34234 P_XOP,
34235 P_PROC_XOP,
34236 P_FMA,
34237 P_PROC_FMA,
34238 P_AVX2,
34239 P_PROC_AVX2,
34240 P_AVX512F
34241 };
34245 /* These are the target attribute strings for which a dispatcher is
34246 available, from fold_builtin_cpu. */
34248 static struct _feature_list
34249 {
34252 }
34254 {
34270 };
34273 static unsigned int NUM_FEATURES
34289 /* Return priority zero for default function. */
34293 /* Handle arch= if specified. For priority, set it to be 1 more than
34294 the best instruction set the processor can handle. For instance, if
34295 there is a version for atom and a version for ssse3 (the highest ISA
34296 priority for atom), the atom version must be checked for dispatch
34297 before the ssse3 version. */
34299 {
34309 {
34311 {
34319 else
34320 /* We translate "arch=corei7" and "arch=nehalem" to
34321 "corei7" so that it will be mapped to M_INTEL_COREI7
34322 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34329 else
34336 else
34376 }
34377 }
34382 {
34386 }
34389 {
34391 /* For a C string literal the length includes the trailing NULL. */
34394 predicate_chain);
34395 }
34396 }
34398 /* Process feature name. */
34405 {
34406 /* Do not process "arch=" */
34408 {
34411 }
34413 {
34415 {
34417 {
34422 predicate_chain);
34423 }
34424 /* Find the maximum priority feature. */
34429 }
34430 }
34432 {
34436 }
34438 }
34442 {
34445 attrs_str);
34447 }
34449 {
34452 }
34455 }
34457 /* This compares the priority of target features in function DECL1
34458 and DECL2. It returns positive value if DECL1 is higher priority,
34459 negative value if DECL2 is higher priority and 0 if they are the
34460 same. */
34462 static int
34464 {
34469 }
34471 /* V1 and V2 point to function versions with different priorities
34472 based on the target ISA. This function compares their priorities. */
34474 static int
34476 {
34478 {
34479 tree version_decl;
34480 tree predicate_chain;
34487 }
34489 /* This function generates the dispatch function for
34490 multi-versioned functions. DISPATCH_DECL is the function which will
34491 contain the dispatch logic. FNDECLS are the function choices for
34492 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34493 in DISPATCH_DECL in which the dispatch code is generated. */
34495 static int
34499 {
34500 tree default_decl;
34501 gimple ifunc_cpu_init_stmt;
34502 gimple_seq gseq;
34504 tree ele;
34510 struct _function_version_info
34511 {
34512 tree version_decl;
34513 tree predicate_chain;
34521 /*fndecls_p is actually a vector. */
34524 /* At least one more version other than the default. */
34531 /* The first version in the vector is the default decl. */
34537 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34538 constructors, so explicity call __builtin_cpu_init here. */
34549 {
34553 /* Get attribute string, parse it and find the right predicate decl.
34554 The predicate function could be a lengthy combination of many
34555 features, like arch-type and various isa-variants. */
34566 actual_versions++;
34567 }
34569 /* Sort the versions according to descending order of dispatch priority. The
34570 priority is based on the ISA. This is not a perfect solution. There
34571 could still be ambiguity. If more than one function version is suitable
34572 to execute, which one should be dispatched? In future, allow the user
34573 to specify a dispatch priority next to the version. */
34583 /* dispatch default version at the end. */
34589 }
34591 /* Comparator function to be used in qsort routine to sort attribute
34592 specification strings to "target". */
34594 static int
34596 {
34600 }
34602 /* ARGLIST is the argument to target attribute. This function tokenizes
34603 the comma separated arguments, sorts them and returns a string which
34604 is a unique identifier for the comma separated arguments. It also
34605 replaces non-identifier characters "=,-" with "_". */
34609 {
34610 tree arg;
34619 {
34624 argnum++;
34627 argnum++;
34628 }
34633 {
34639 }
34641 /* Replace "=,-" with "_". */
34654 {
34656 i++;
34658 }
34665 {
34670 }
34675 }
34677 /* This function changes the assembler name for functions that are
34678 versions. If DECL is a function version and has a "target"
34679 attribute, it appends the attribute string to its assembler name. */
34681 static tree
34683 {
34684 tree version_attr;
34692 "Function versions cannot be marked as gnu_inline,"
34701 /* target attribute string cannot be NULL. */
34705 version_string
34716 /* Allow assembler name to be modified if already set. */
34724 }
34726 /* This function returns true if FN1 and FN2 are versions of the same function,
34727 that is, the target strings of the function decls are different. This assumes
34728 that FN1 and FN2 have the same signature. */
34730 static bool
34732 {
34744 /* At least one function decl should have the target attribute specified. */
34748 /* Diagnose missing target attribute if one of the decls is already
34749 multi-versioned. */
34751 {
34753 {
34755 {
34760 }
34763 fn2);
34766 /* Prevent diagnosing of the same error multiple times. */
34771 }
34773 }
34778 /* The sorted target strings must be different for fn1 and fn2
34779 to be versions. */
34782 else
34789 }
34791 static tree
34793 {
34794 /* For function version, add the target suffix to the assembler name. */
34798 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34800 #endif
34803 }
34805 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34806 is true, append the full path name of the source file. */
34810 {
34818 /* Get a unique name that can be used globally without any chances
34819 of collision at link time. */
34829 /* Use '.' to concatenate names as it is demangler friendly. */
34832 suffix);
34833 else
34837 }
34839 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34841 /* Make a dispatcher declaration for the multi-versioned function DECL.
34842 Calls to DECL function will be replaced with calls to the dispatcher
34843 by the front-end. Return the decl created. */
34845 static tree
34847 {
34848 tree func_decl;
34868 /* Mark this func as external, the resolver will flip it again if
34869 it gets generated. */
34871 /* This will be of type IFUNCs have to be externally visible. */
34875 }
34877 #endif
34879 /* Returns true if decl is multi-versioned and DECL is the default function,
34880 that is it is not tagged with target specific optimization. */
34882 static bool
34884 {
34893 }
34895 /* Make a dispatcher declaration for the multi-versioned function DECL.
34896 Calls to DECL function will be replaced with calls to the dispatcher
34897 by the front-end. Returns the decl of the dispatcher function. */
34899 static tree
34901 {
34923 /* Find the default version and make it the first node. */
34925 /* Go to the beginning of the chain. */
34930 {
34935 }
34937 /* If there is no default node, just return NULL. */
34941 /* Make default info the first node. */
34943 {
34950 }
34954 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34956 {
34961 /* Right now, the dispatching is done via ifunc. */
34967 dispatcher_version_info
34972 /* Set the dispatcher for all the versions. */
34975 {
34978 }
34979 }
34980 else
34981 #endif
34982 {
34984 "multiversioning needs ifunc which is not supported "
34986 }
34989 }
34991 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
34992 it to CHAIN. */
34994 static tree
34996 {
34997 tree attr_name;
34998 tree attr_arg_name;
34999 tree attr_args;
35000 tree attr;
35007 }
35009 /* Make the resolver function decl to dispatch the versions of
35010 a multi-versioned function, DEFAULT_DECL. Create an
35011 empty basic block in the resolver and store the pointer in
35012 EMPTY_BB. Return the decl of the resolver function. */
35014 static tree
35018 {
35023 /* IFUNC's have to be globally visible. So, if the default_decl is
35024 not, then the name of the IFUNC should be made unique. */
35028 /* Append the filename to the resolver function if the versions are
35029 not externally visible. This is because the resolver function has
35030 to be externally visible for the loader to find it. So, appending
35031 the filename will prevent conflicts with a resolver function from
35032 another module which is based on the same version name. */
35035 /* The resolver function should return a (void *). */
35046 /* IFUNC resolvers have to be externally visible. */
35050 /* Resolver is not external, body is generated. */
35060 {
35061 /* In this case, each translation unit with a call to this
35062 versioned function will put out a resolver. Ensure it
35063 is comdat to keep just one copy. */
35066 }
35067 /* Build result decl and add to function_decl. */
35083 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35087 /* Create the alias for dispatch to resolver here. */
35088 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35092 }
35094 /* Generate the dispatching code body to dispatch multi-versioned function
35095 DECL. The target hook is called to process the "target" attributes and
35096 provide the code to dispatch the right function at run-time. NODE points
35097 to the dispatcher decl whose body will be created. */
35099 static tree
35101 {
35102 tree resolver_decl;
35103 basic_block empty_bb;
35104 tree default_ver_decl;
35120 /* The first version in the chain corresponds to the default version. */
35123 /* node is going to be an alias, so remove the finalized bit. */
35137 {
35139 /* Check for virtual functions here again, as by this time it should
35140 have been determined if this function needs a vtable index or
35141 not. This happens for methods in derived classes that override
35142 virtual methods in base classes but are not explicitly marked as
35143 virtual. */
35148 }
35154 }
35155 /* This builds the processor_model struct type defined in
35156 libgcc/config/i386/cpuinfo.c */
35158 static tree
35160 {
35167 /* The first 3 fields are unsigned int. */
35169 {
35175 }
35177 /* The last field is an array of unsigned integers of size one. */
35188 }
35190 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35192 static tree
35194 {
35195 tree new_decl;
35198 VAR_DECL,
35200 type);
35213 }
35215 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35216 into an integer defined in libgcc/config/i386/cpuinfo.c */
35218 static tree
35220 {
35226 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35227 enum processor_features
35228 {
35230 F_MMX,
35231 F_POPCNT,
35232 F_SSE,
35233 F_SSE2,
35234 F_SSE3,
35235 F_SSSE3,
35236 F_SSE4_1,
35237 F_SSE4_2,
35238 F_AVX,
35239 F_AVX2,
35240 F_SSE4_A,
35241 F_FMA4,
35242 F_XOP,
35243 F_FMA,
35244 F_AVX512F,
35245 F_MAX
35246 };
35248 /* These are the values for vendor types and cpu types and subtypes
35249 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35250 the corresponding start value. */
35251 enum processor_model
35252 {
35254 M_AMD,
35255 M_CPU_TYPE_START,
35256 M_INTEL_BONNELL,
35257 M_INTEL_CORE2,
35258 M_INTEL_COREI7,
35259 M_AMDFAM10H,
35260 M_AMDFAM15H,
35261 M_INTEL_SILVERMONT,
35262 M_AMD_BTVER1,
35263 M_AMD_BTVER2,
35264 M_CPU_SUBTYPE_START,
35265 M_INTEL_COREI7_NEHALEM,
35266 M_INTEL_COREI7_WESTMERE,
35267 M_INTEL_COREI7_SANDYBRIDGE,
35268 M_AMDFAM10H_BARCELONA,
35269 M_AMDFAM10H_SHANGHAI,
35270 M_AMDFAM10H_ISTANBUL,
35271 M_AMDFAM15H_BDVER1,
35272 M_AMDFAM15H_BDVER2,
35273 M_AMDFAM15H_BDVER3,
35274 M_AMDFAM15H_BDVER4,
35275 M_INTEL_COREI7_IVYBRIDGE,
35276 M_INTEL_COREI7_HASWELL
35277 };
35279 static struct _arch_names_table
35280 {
35283 }
35285 {
35310 };
35312 static struct _isa_names_table
35313 {
35316 }
35318 {
35335 };
35349 {
35350 /* *args must be a expr that can contain other EXPRS leading to a
35351 STRING_CST. */
35353 {
35356 }
35358 }
35363 {
35364 tree ref;
35365 tree field;
35366 tree final;
35369 unsigned int NUM_ARCH_NAMES
35378 {
35382 }
35387 /* CPU types are stored in the next field. */
35390 {
35393 }
35395 /* CPU subtypes are stored in the next field. */
35397 {
35400 }
35402 /* Get the appropriate field in __cpu_model. */
35406 /* Check the value. */
35410 }
35412 {
35413 tree ref;
35414 tree array_elt;
35415 tree field;
35416 tree final;
35419 unsigned int NUM_ISA_NAMES
35428 {
35432 }
35435 /* Get the last field, which is __cpu_features. */
35439 /* Get the appropriate field: __cpu_model.__cpu_features */
35443 /* Access the 0th element of __cpu_features array. */
35448 /* Return __cpu_model.__cpu_features[0] & field_val */
35452 }
35454 }
35456 static tree
35459 {
35461 {
35466 {
35469 }
35470 }
35472 #ifdef SUBTARGET_FOLD_BUILTIN
35474 #endif
35477 }
35479 /* Make builtins to detect cpu type and features supported. NAME is
35480 the builtin name, CODE is the builtin code, and FTYPE is the function
35481 type of the builtin. */
35483 static void
35486 {
35487 tree decl;
35488 tree type;
35496 }
35498 /* Make builtins to get CPU type and features supported. The created
35499 builtins are :
35501 __builtin_cpu_init (), to detect cpu type and features,
35502 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35503 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35504 */
35506 static void
35508 {
35515 }
35517 /* Internal method for ix86_init_builtins. */
35519 static void
35521 {
35533 sysv_va_ref =
35536 fnvoid_va_end_ms =
35538 fnvoid_va_start_ms =
35540 fnvoid_va_end_sysv =
35542 fnvoid_va_start_sysv =
35544 NULL_TREE);
35545 fnvoid_va_copy_ms =
35547 NULL_TREE);
35548 fnvoid_va_copy_sysv =
35564 }
35566 static void
35568 {
35571 /* The __float80 type. */
35574 {
35575 /* The __float80 type. */
35580 }
35583 /* The __float128 type. */
35589 /* This macro is built by i386-builtin-types.awk. */
35590 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35591 }
35593 static void
35595 {
35596 tree t;
35600 /* Builtins to get CPU type and features. */
35603 /* TFmode support builtins. */
35609 /* We will expand them to normal call if SSE isn't available since
35610 they are used by libgcc. */
35630 #ifdef SUBTARGET_INIT_BUILTINS
35631 SUBTARGET_INIT_BUILTINS;
35632 #endif
35633 }
35635 /* Return the ix86 builtin for CODE. */
35637 static tree
35639 {
35644 }
35646 /* Errors in the source file can cause expand_expr to return const0_rtx
35647 where we expect a vector. To avoid crashing, use one of the vector
35648 clear instructions. */
35649 static rtx
35651 {
35655 }
35657 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35659 static rtx
35661 {
35662 rtx pat;
35682 {
35686 }
35700 }
35702 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35704 static rtx
35708 {
35709 rtx pat;
35717 rtx op;
35718 machine_mode mode;
35724 {
35804 }
35814 {
35821 {
35823 {
35826 {
35844 xop_rotl:
35846 {
35849 gcc_checking_assert
35851 }
35852 else
35853 {
35854 gcc_checking_assert
35865 }
35869 }
35870 }
35871 }
35872 else
35873 {
35874 non_constant:
35878 /* If we aren't optimizing, only allow one memory operand to be
35879 generated. */
35881 num_memory++;
35889 }
35893 }
35896 {
35907 else
35908 {
35914 }
35927 }
35934 }
35936 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
35937 insns with vec_merge. */
35939 static rtx
35941 rtx target)
35942 {
35943 rtx pat;
35970 }
35972 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
35974 static rtx
35977 {
35978 rtx pat;
35983 rtx op2;
35994 /* Swap operands if we have a comparison that isn't available in
35995 hardware. */
35997 {
36002 }
36022 }
36024 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36026 static rtx
36028 rtx target)
36029 {
36030 rtx pat;
36044 /* Swap operands if we have a comparison that isn't available in
36045 hardware. */
36068 const0_rtx)));
36071 }
36073 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36075 static rtx
36077 rtx target)
36078 {
36079 rtx pat;
36104 }
36106 static rtx
36109 {
36110 rtx pat;
36115 rtx op2;
36142 }
36144 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36146 static rtx
36148 rtx target)
36149 {
36150 rtx pat;
36183 const0_rtx)));
36186 }
36188 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36190 static rtx
36193 {
36194 rtx pat;
36232 {
36235 }
36238 {
36247 }
36249 {
36258 }
36259 else
36260 {
36267 }
36275 {
36280 emit_insn
36284 FLAGS_REG),
36285 const0_rtx)));
36287 }
36288 else
36290 }
36293 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36295 static rtx
36298 {
36299 rtx pat;
36327 {
36330 }
36333 {
36342 }
36344 {
36353 }
36354 else
36355 {
36362 }
36370 {
36375 emit_insn
36379 FLAGS_REG),
36380 const0_rtx)));
36382 }
36383 else
36385 }
36387 /* Subroutine of ix86_expand_builtin to take care of insns with
36388 variable number of operands. */
36390 static rtx
36393 {
36399 struct
36400 {
36401 rtx op;
36402 machine_mode mode;
36413 {
37123 }
37128 {
37131 }
37134 {
37141 }
37142 else
37143 {
37146 }
37149 {
37156 {
37157 /* SIMD shift insns take either an 8-bit immediate or
37158 register as count. But builtin functions take int as
37159 count. If count doesn't match, we put it in register. */
37161 {
37165 }
37166 }
37169 {
37172 {
37281 {
37285 {
37288 }
37294 }
37296 }
37297 }
37298 else
37299 {
37303 /* If we aren't optimizing, only allow one memory operand to
37304 be generated. */
37306 num_memory++;
37309 {
37312 }
37313 else
37314 {
37317 }
37318 }
37322 }
37325 {
37350 }
37357 }
37359 /* Transform pattern of following layout:
37360 (parallel [
37361 set (A B)
37362 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37363 ])
37364 into:
37365 (set (A B))
37367 Or:
37368 (parallel [ A B
37369 ...
37370 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37371 ...
37372 ])
37373 into:
37374 (parallel [ A B ... ]) */
37376 static rtx
37378 {
37385 {
37394 }
37395 else
37396 {
37402 {
37407 }
37409 /* No more than 1 occurence was removed. */
37413 }
37414 }
37416 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37417 with rounding. */
37418 static rtx
37421 {
37438 /* See avxintrin.h for values. */
37440 {
37444 };
37446 {
37451 };
37454 {
37457 }
37459 {
37462 }
37465 {
37468 }
37491 ? CODE_FOR_sse_ucomi_round
37498 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37500 {
37506 }
37507 else
37508 {
37511 }
37517 set_dst,
37518 const0_rtx)));
37521 }
37523 static rtx
37526 {
37527 rtx pat;
37529 struct
37530 {
37531 rtx op;
37532 machine_mode mode;
37541 {
37624 }
37634 {
37641 {
37643 {
37645 {
37661 }
37662 }
37663 }
37665 {
37667 {
37670 }
37672 /* If there is no rounding use normal version of the pattern. */
37675 }
37676 else
37677 {
37682 {
37685 }
37686 else
37687 {
37690 }
37691 }
37695 }
37698 {
37723 }
37733 }
37735 /* Subroutine of ix86_expand_builtin to take care of special insns
37736 with variable number of operands. */
37738 static rtx
37741 {
37742 tree arg;
37746 struct
37747 {
37748 rtx op;
37749 machine_mode mode;
37758 {
37798 {
37806 }
37825 /* Reserve memory operand for target. */
37828 {
37829 /* These builtins and instructions require the memory
37830 to be properly aligned. */
37849 }
37878 {
37879 /* These builtins and instructions require the memory
37880 to be properly aligned. */
37897 }
37898 /* FALLTHRU */
37936 /* Reserve memory operand for target. */
37963 {
37964 /* These builtins and instructions require the memory
37965 to be properly aligned. */
37988 }
38001 }
38006 {
38011 {
38014 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38015 on it. Try to improve it using get_pointer_alignment,
38016 and if the special builtin is one that requires strict
38017 mode alignment, also from it's GET_MODE_ALIGNMENT.
38018 Failure to do so could lead to ix86_legitimate_combined_insn
38019 rejecting all changes to such insns. */
38025 }
38026 else
38029 }
38030 else
38031 {
38038 }
38041 {
38050 {
38052 {
38058 else
38061 }
38062 }
38063 else
38064 {
38066 {
38067 /* This must be the memory operand. */
38070 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38071 on it. Try to improve it using get_pointer_alignment,
38072 and if the special builtin is one that requires strict
38073 mode alignment, also from it's GET_MODE_ALIGNMENT.
38074 Failure to do so could lead to ix86_legitimate_combined_insn
38075 rejecting all changes to such insns. */
38081 }
38082 else
38083 {
38084 /* This must be register. */
38090 else
38091 {
38094 }
38095 }
38096 }
38100 }
38103 {
38118 }
38124 }
38126 /* Return the integer constant in ARG. Constrain it to be in the range
38127 of the subparts of VEC_TYPE; issue an error if not. */
38129 static int
38131 {
38136 {
38139 }
38142 }
38144 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38145 ix86_expand_vector_init. We DO have language-level syntax for this, in
38146 the form of (type){ init-list }. Except that since we can't place emms
38147 instructions from inside the compiler, we can't allow the use of MMX
38148 registers unless the user explicitly asks for it. So we do *not* define
38149 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38150 we have builtins invoked by mmintrin.h that gives us license to emit
38151 these sorts of instructions. */
38153 static rtx
38155 {
38165 {
38168 }
38175 }
38177 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38178 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38179 had a language-level syntax for referencing vector elements. */
38181 static rtx
38183 {
38187 rtx op0;
38207 }
38209 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38210 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38211 a language-level syntax for referencing vector elements. */
38213 static rtx
38215 {
38239 /* OP0 is the source of these builtin functions and shouldn't be
38240 modified. Create a copy, use it and return it as target. */
38246 }
38248 /* Emit conditional move of SRC to DST with condition
38249 OP1 CODE OP2. */
38250 static void
38252 {
38253 rtx t;
38256 {
38261 }
38262 else
38263 {
38269 }
38270 }
38272 /* Choose max of DST and SRC and put it to DST. */
38273 static void
38275 {
38277 }
38279 /* Expand an expression EXP that calls a built-in function,
38280 with result going to TARGET if that's convenient
38281 (and in mode MODE if that's convenient).
38282 SUBTARGET may be used as the target for computing one of EXP's operands.
38283 IGNORE is nonzero if the value is to be ignored. */
38285 static rtx
38288 {
38298 /* For CPU builtins that can be folded, fold first and expand the fold. */
38300 {
38302 {
38303 /* Make it call __cpu_indicator_init in libgcc. */
38309 }
38312 {
38317 }
38318 }
38320 /* Determine whether the builtin function is available under the current ISA.
38321 Originally the builtin was not created if it wasn't applicable to the
38322 current ISA based on the command line switches. With function specific
38323 options, we need to check in the context of the function making the call
38324 whether it is supported. */
38327 {
38333 else
38334 {
38338 }
38340 }
38343 {
38361 /* Builtin arg1 is size of block but instruction op1 should
38362 be (size - 1). */
38453 /* If no bounds were specified for returned value,
38454 then use INIT bounds. It usually happens when
38455 some built-in function is expanded. */
38457 {
38466 }
38472 {
38475 /* Return value and lb. */
38477 /* Bounds. */
38479 /* Size. */
38486 /* Size was passed but we need to use (size - 1) as for bndmk. */
38490 /* Add LB to size and inverse to get UB. */
38500 /* We need to move bounds to memory before any computations. */
38503 else
38504 {
38507 }
38509 /* Generate mem expression to be used for access to LB and UB. */
38515 /* Compute LB. */
38520 /* Compute UB. UB is stored in 1's complement form. Therefore
38521 we also use max here. */
38530 }
38533 {
38551 /* Put first bounds to temporaries. */
38555 {
38559 }
38560 else
38561 {
38565 }
38567 /* Put second bounds to temporaries. */
38571 {
38575 }
38576 else
38577 {
38581 }
38583 /* Compute LB. */
38587 /* Compute UB. UB is stored in 1's complement form. Therefore
38588 we also use max here. */
38595 }
38598 {
38599 tree name;
38600 rtx symbol;
38618 }
38621 {
38632 /* We need to move bounds to memory first. */
38635 else
38636 {
38639 }
38641 /* Generate mem expression to access LB and load it. */
38646 }
38649 {
38660 /* We need to move bounds to memory first. */
38663 else
38664 {
38667 }
38669 /* Generate mem expression to access UB. */
38672 /* We need to inverse all bits of UB. */
38679 }
38684 ? CODE_FOR_mmx_maskmovq
38686 /* Note the arg order is different from the operand order. */
38807 {
38808 REAL_VALUE_TYPE inf;
38809 rtx tmp;
38821 }
38831 {
38837 insn = (TARGET_64BIT
38841 }
38843 {
38844 insn = (TARGET_64BIT
38848 }
38849 else
38850 {
38853 insn = (TARGET_64BIT
38861 {
38864 }
38866 }
38869 {
38870 /* mode is VOIDmode if __builtin_rd* has been called
38871 without lhs. */
38875 }
38878 {
38883 }
38896 {
38917 }
38923 {
38926 }
38952 {
38955 }
38961 {
38965 {
39004 }
39009 }
39010 else
39011 {
39013 {
39034 }
39036 }
39066 ? CODE_FOR_tbm_bextri_si
39069 {
39072 }
39073 else
39074 {
39083 }
39099 rdrand_step:
39106 {
39109 }
39115 /* Emit SImode conditional move. */
39117 {
39120 }
39123 else
39131 const0_rtx);
39150 rdseed_step:
39157 {
39160 }
39166 const0_rtx);
39195 addcarryx:
39203 /* Generate CF from input operand. */
39208 /* Gen ADCX instruction to compute X+Y+CF. */
39223 /* Store the result. */
39226 {
39229 }
39232 /* Return current CF value. */
39274 kortest:
39288 /* Emit kortest. */
39290 /* And use setcc to return result from flags. */
39548 gather_gen:
39549 rtx half;
39562 /* Note the arg order is different from the operand order. */
39573 else
39577 {
39601 else
39608 {
39613 }
39622 else
39629 {
39634 }
39638 }
39640 /* Force memory operand only with base register here. But we
39641 don't want to do it on memory operand for other builtin
39642 functions. */
39652 {
39655 }
39656 else
39657 {
39660 }
39662 {
39665 }
39667 /* Optimize. If mask is known to have all high bits set,
39668 replace op0 with pc_rtx to signal that the instruction
39669 overwrites the whole destination and doesn't use its
39670 previous contents. */
39672 {
39674 {
39677 }
39679 {
39682 {
39686 negative++;
39689 negative++;
39690 }
39693 }
39696 {
39697 /* Recognize also when mask is like:
39698 __v2df src = _mm_setzero_pd ();
39699 __v2df mask = _mm_cmpeq_pd (src, src);
39700 or
39701 __v8sf src = _mm256_setzero_ps ();
39702 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39703 as that is a cheaper way to load all ones into
39704 a register than having to load a constant from
39705 memory. */
39708 {
39713 {
39720 /* FALLTHRU */
39730 }
39731 }
39732 }
39733 }
39741 {
39767 }
39770 scatter_gen:
39786 /* Force memory operand only with base register here. But we
39787 don't want to do it on memory operand for other builtin
39788 functions. */
39795 {
39798 }
39799 else
39800 {
39803 }
39812 {
39815 }
39824 vec_prefetch_gen:
39842 {
39845 }
39847 {
39850 }
39855 /* Force memory operand only with base register here. But we
39856 don't want to do it on memory operand for other builtin
39857 functions. */
39864 {
39867 }
39870 {
39873 }
39889 {
39892 }
39898 }
39911 {
39915 /* Emit a normal call if SSE isn't available. */
39919 }
39948 }
39950 /* This returns the target-specific builtin with code CODE if
39951 current_function_decl has visibility on this builtin, which is checked
39952 using isa flags. Returns NULL_TREE otherwise. */
39955 {
39959 /* Determine the isa flags of current_function_decl. */
39971 else
39973 }
39975 /* Return function decl for target specific builtin
39976 for given MPX builtin passed i FCODE. */
39977 static tree
39979 {
39981 {
40017 }
40020 }
40022 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40024 Return an address to be used to load/store bounds for pointer
40025 passed in SLOT.
40027 SLOT_NO is an integer constant holding number of a target
40028 dependent special slot to be used in case SLOT is not a memory.
40030 SPECIAL_BASE is a pointer to be used as a base of fake address
40031 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40032 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40034 static rtx
40036 {
40039 /* NULL slot means we pass bounds for pointer not passed to the
40040 function at all. Register slot means we pass pointer in a
40041 register. In both these cases bounds are passed via Bounds
40042 Table. Since we do not have actual pointer stored in memory,
40043 we have to use fake addresses to access Bounds Table. We
40044 start with (special_base - sizeof (void*)) and decrease this
40045 address by pointer size to get addresses for other slots. */
40047 {
40051 }
40052 /* If pointer is passed in a memory then its address is used to
40053 access Bounds Table. */
40055 {
40059 }
40060 else
40064 }
40066 /* Expand pass uses this hook to load bounds for function parameter
40067 PTR passed in SLOT in case its bounds are not passed in a register.
40069 If SLOT is a memory, then bounds are loaded as for regular pointer
40070 loaded from memory. PTR may be NULL in case SLOT is a memory.
40071 In such case value of PTR (if required) may be loaded from SLOT.
40073 If SLOT is NULL or a register then SLOT_NO is an integer constant
40074 holding number of the target dependent special slot which should be
40075 used to obtain bounds.
40077 Return loaded bounds. */
40079 static rtx
40081 {
40083 rtx addr;
40085 /* Get address to be used to access Bounds Table. Special slots start
40086 at the location of return address of the current function. */
40089 /* Load pointer value from a memory if we don't have it. */
40091 {
40094 }
40101 }
40103 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40104 passed in SLOT in case BOUNDS are not passed in a register.
40106 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40107 stored in memory. PTR may be NULL in case SLOT is a memory.
40108 In such case value of PTR (if required) may be loaded from SLOT.
40110 If SLOT is NULL or a register then SLOT_NO is an integer constant
40111 holding number of the target dependent special slot which should be
40112 used to store BOUNDS. */
40114 static void
40116 {
40117 rtx addr;
40119 /* Get address to be used to access Bounds Table. Special slots start
40120 at the location of return address of a called function. */
40123 /* Load pointer value from a memory if we don't have it. */
40125 {
40128 }
40137 }
40139 /* Load and return bounds returned by function in SLOT. */
40141 static rtx
40143 {
40144 rtx res;
40151 }
40153 /* Store BOUNDS returned by function into SLOT. */
40155 static void
40157 {
40160 }
40162 /* Returns a function decl for a vectorized version of the builtin function
40163 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40164 if it is not available. */
40166 static tree
40168 tree type_in)
40169 {
40185 {
40188 {
40195 }
40200 {
40203 }
40208 {
40215 }
40221 /* The round insn does not trap on denormals. */
40226 {
40233 }
40239 /* The round insn does not trap on denormals. */
40244 {
40249 }
40255 /* The round insn does not trap on denormals. */
40260 {
40267 }
40273 /* The round insn does not trap on denormals. */
40278 {
40283 }
40290 {
40295 }
40302 {
40307 }
40313 /* The round insn does not trap on denormals. */
40318 {
40325 }
40331 /* The round insn does not trap on denormals. */
40336 {
40341 }
40346 {
40353 }
40358 {
40365 }
40369 /* The round insn does not trap on denormals. */
40374 {
40379 }
40383 /* The round insn does not trap on denormals. */
40388 {
40393 }
40397 /* The round insn does not trap on denormals. */
40402 {
40407 }
40411 /* The round insn does not trap on denormals. */
40416 {
40421 }
40425 /* The round insn does not trap on denormals. */
40430 {
40435 }
40439 /* The round insn does not trap on denormals. */
40444 {
40449 }
40453 /* The round insn does not trap on denormals. */
40458 {
40463 }
40467 /* The round insn does not trap on denormals. */
40472 {
40477 }
40481 /* The round insn does not trap on denormals. */
40486 {
40491 }
40495 /* The round insn does not trap on denormals. */
40500 {
40505 }
40510 {
40515 }
40520 {
40525 }
40530 }
40532 /* Dispatch to a handler for a vectorization library. */
40535 type_in);
40538 }
40540 /* Handler for an SVML-style interface to
40541 a library with vectorized intrinsics. */
40543 static tree
40545 {
40553 /* The SVML is suitable for unsafe math only. */
40566 {
40613 }
40622 {
40625 }
40626 else
40629 /* Convert to uppercase. */
40634 args;
40636 arity++;
40640 else
40643 /* Build a function declaration for the vectorized function. */
40652 }
40654 /* Handler for an ACML-style interface to
40655 a library with vectorized intrinsics. */
40657 static tree
40659 {
40667 /* The ACML is 64bits only and suitable for unsafe math only as
40668 it does not correctly support parts of IEEE with the required
40669 precision such as denormals. */
40683 {
40713 }
40720 args;
40722 arity++;
40726 else
40729 /* Build a function declaration for the vectorized function. */
40738 }
40740 /* Returns a decl of a function that implements gather load with
40741 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40742 Return NULL_TREE if it is not available. */
40744 static tree
40747 {
40763 /* v*gather* insn sign extends index to pointer mode. */
40775 {
40779 else
40785 else
40791 else
40797 else
40803 else
40809 else
40815 else
40821 else
40827 else
40833 else
40839 else
40845 else
40850 }
40853 }
40855 /* Returns a code for a target-specific builtin that implements
40856 reciprocal of the function, or NULL_TREE if not available. */
40858 static tree
40860 {
40867 /* Machine dependent builtins. */
40869 {
40870 /* Vectorized version of sqrt to rsqrt conversion. */
40879 }
40880 else
40881 /* Normal builtins. */
40883 {
40884 /* Sqrt to rsqrt conversion. */
40890 }
40891 }
40892 \f
40893 /* Helper for avx_vpermilps256_operand et al. This is also used by
40894 the expansion functions to turn the parallel back into a mask.
40895 The return value is 0 for no match and the imm8+1 for a match. */
40897 int
40899 {
40907 /* Validate that all of the elements are constants, and not totally
40908 out of range. Copy the data into an integral array to make the
40909 subsequent checks easier. */
40911 {
40921 }
40924 {
40926 /* In the 512-bit DFmode case, we can only move elements within
40927 a 128-bit lane. First fill the second part of the mask,
40928 then fallthru. */
40930 {
40934 }
40936 {
40940 }
40941 /* FALLTHRU */
40944 /* In the 256-bit DFmode case, we can only move elements within
40945 a 128-bit lane. */
40947 {
40951 }
40953 {
40957 }
40961 /* In 512 bit SFmode case, permutation in the upper 256 bits
40962 must mirror the permutation in the lower 256-bits. */
40966 /* FALLTHRU */
40969 /* In 256 bit SFmode case, we have full freedom of
40970 movement within the low 128-bit lane, but the high 128-bit
40971 lane must mirror the exact same pattern. */
40976 /* FALLTHRU */
40980 /* In the 128-bit case, we've full freedom in the placement of
40981 the elements from the source operand. */
40988 }
40990 /* Make sure success has a non-zero value by adding one. */
40992 }
40994 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
40995 the expansion functions to turn the parallel back into a mask.
40996 The return value is 0 for no match and the imm8+1 for a match. */
40998 int
41000 {
41008 /* Validate that all of the elements are constants, and not totally
41009 out of range. Copy the data into an integral array to make the
41010 subsequent checks easier. */
41012 {
41022 }
41024 /* Validate that the halves of the permute are halves. */
41032 /* Reconstruct the mask. */
41034 {
41040 }
41042 /* Make sure success has a non-zero value by adding one. */
41044 }
41045 \f
41046 /* Return a register priority for hard reg REGNO. */
41047 static int
41049 {
41050 /* ebp and r13 as the base always wants a displacement, r12 as the
41051 base always wants an index. So discourage their usage in an
41052 address. */
41057 /* New x86-64 int registers result in bigger code size. Discourage
41058 them. */
41061 /* New x86-64 SSE registers result in bigger code size. Discourage
41062 them. */
41065 /* Usage of AX register results in smaller code. Prefer it. */
41069 }
41071 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41073 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41074 QImode must go into class Q_REGS.
41075 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41076 movdf to do mem-to-mem moves through integer regs. */
41078 static reg_class_t
41080 {
41083 /* We're only allowed to return a subclass of CLASS. Many of the
41084 following checks fail for NO_REGS, so eliminate that early. */
41088 /* All classes can load zeros. */
41092 /* Force constants into memory if we are loading a (nonzero) constant into
41093 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41094 instructions to load from a constant. */
41101 /* Prefer SSE regs only, if we can use them for math. */
41105 /* Floating-point constants need more complex checks. */
41107 {
41108 /* General regs can load everything. */
41112 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41113 zero above. We only want to wind up preferring 80387 registers if
41114 we plan on doing computation with them. */
41117 {
41118 /* Limit class to non-sse. */
41127 }
41130 }
41132 /* Generally when we see PLUS here, it's the function invariant
41133 (plus soft-fp const_int). Which can only be computed into general
41134 regs. */
41138 /* QImode constants are easy to load, but non-constant QImode data
41139 must go into Q_REGS. */
41141 {
41147 }
41150 }
41152 /* Discourage putting floating-point values in SSE registers unless
41153 SSE math is being used, and likewise for the 387 registers. */
41154 static reg_class_t
41156 {
41159 /* Restrict the output reload class to the register bank that we are doing
41160 math on. If we would like not to return a subset of CLASS, reject this
41161 alternative: if reload cannot do this, it will still use its choice. */
41167 {
41172 else
41174 }
41177 }
41179 static reg_class_t
41182 {
41183 /* Double-word spills from general registers to non-offsettable memory
41184 references (zero-extended addresses) require special handling. */
41190 {
41192 ? CODE_FOR_reload_noff_load
41194 /* Add the cost of moving address to a temporary. */
41198 }
41200 /* QImode spills from non-QI registers require
41201 intermediate register on 32bit targets. */
41207 {
41212 else
41218 /* Return Q_REGS if the operand is in memory. */
41221 }
41223 /* This condition handles corner case where an expression involving
41224 pointers gets vectorized. We're trying to use the address of a
41225 stack slot as a vector initializer.
41227 (set (reg:V2DI 74 [ vect_cst_.2 ])
41228 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41230 Eventually frame gets turned into sp+offset like this:
41232 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41233 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41234 (const_int 392 [0x188]))))
41236 That later gets turned into:
41238 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41239 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41240 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41242 We'll have the following reload recorded:
41244 Reload 0: reload_in (DI) =
41245 (plus:DI (reg/f:DI 7 sp)
41246 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41247 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41248 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41249 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41250 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41251 reload_reg_rtx: (reg:V2DI 22 xmm1)
41253 Which isn't going to work since SSE instructions can't handle scalar
41254 additions. Returning GENERAL_REGS forces the addition into integer
41255 register and reload can handle subsequent reloads without problems. */
41263 }
41265 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41267 static bool
41269 {
41271 {
41287 }
41290 }
41292 /* If we are copying between general and FP registers, we need a memory
41293 location. The same is true for SSE and MMX registers.
41295 To optimize register_move_cost performance, allow inline variant.
41297 The macro can't work reliably when one of the CLASSES is class containing
41298 registers from multiple units (SSE, MMX, integer). We avoid this by never
41299 combining those units in single alternative in the machine description.
41300 Ensure that this constraint holds to avoid unexpected surprises.
41302 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41303 enforce these sanity checks. */
41308 {
41317 {
41320 }
41325 /* Between mask and general, we have moves no larger than word size. */
41330 /* ??? This is a lie. We do have moves between mmx/general, and for
41331 mmx/sse2. But by saying we need secondary memory we discourage the
41332 register allocator from using the mmx registers unless needed. */
41337 {
41338 /* SSE1 doesn't have any direct moves from other classes. */
41342 /* If the target says that inter-unit moves are more expensive
41343 than moving through memory, then don't generate them. */
41348 /* Between SSE and general, we have moves no larger than word size. */
41351 }
41354 }
41356 bool
41359 {
41361 }
41363 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41365 On the 80386, this is the size of MODE in words,
41366 except in the FP regs, where a single reg is always enough. */
41368 static unsigned char
41370 {
41372 {
41377 else
41379 }
41380 else
41381 {
41384 else
41386 }
41387 }
41389 /* Return true if the registers in CLASS cannot represent the change from
41390 modes FROM to TO. */
41392 bool
41395 {
41399 /* x87 registers can't do subreg at all, as all values are reformatted
41400 to extended precision. */
41405 {
41406 /* Vector registers do not support QI or HImode loads. If we don't
41407 disallow a change to these modes, reload will assume it's ok to
41408 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41409 the vec_dupv4hi pattern. */
41412 }
41415 }
41417 /* Return the cost of moving data of mode M between a
41418 register and memory. A value of 2 is the default; this cost is
41419 relative to those in `REGISTER_MOVE_COST'.
41421 This function is used extensively by register_move_cost that is used to
41422 build tables at startup. Make it inline in this case.
41423 When IN is 2, return maximum of in and out move cost.
41425 If moving between registers and memory is more expensive than
41426 between two registers, you should define this macro to express the
41427 relative cost.
41429 Model also increased moving costs of QImode registers in non
41430 Q_REGS classes.
41431 */
41435 {
41438 {
41441 {
41453 }
41457 }
41459 {
41462 {
41474 }
41478 }
41480 {
41483 {
41492 }
41496 }
41498 {
41501 {
41507 else
41512 }
41513 else
41514 {
41519 else
41521 }
41528 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41535 else
41539 }
41540 }
41542 static int
41545 {
41547 }
41550 /* Return the cost of moving data from a register in class CLASS1 to
41551 one in class CLASS2.
41553 It is not required that the cost always equal 2 when FROM is the same as TO;
41554 on some machines it is expensive to move between registers if they are not
41555 general registers. */
41557 static int
41559 reg_class_t class2_i)
41560 {
41564 /* In case we require secondary memory, compute cost of the store followed
41565 by load. In order to avoid bad register allocation choices, we need
41566 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41569 {
41575 /* In case of copying from general_purpose_register we may emit multiple
41576 stores followed by single load causing memory size mismatch stall.
41577 Count this as arbitrarily high cost of 20. */
41582 /* In the case of FP/MMX moves, the registers actually overlap, and we
41583 have to switch modes in order to treat them differently. */
41589 }
41591 /* Moves between SSE/MMX and integer unit are expensive. */
41595 /* ??? By keeping returned value relatively high, we limit the number
41596 of moves between integer and MMX/SSE registers for all targets.
41597 Additionally, high value prevents problem with x86_modes_tieable_p(),
41598 where integer modes in MMX/SSE registers are not tieable
41599 because of missing QImode and HImode moves to, from or between
41600 MMX/SSE registers. */
41610 }
41612 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41613 MODE. */
41615 bool
41617 {
41618 /* Flags and only flags can only hold CCmode values. */
41634 {
41635 /* We implement the move patterns for all vector modes into and
41636 out of SSE registers, even when no operation instructions
41637 are available. */
41639 /* For AVX-512 we allow, regardless of regno:
41640 - XI mode
41641 - any of 512-bit wide vector mode
41642 - any scalar mode. */
41649 /* TODO check for QI/HI scalars. */
41650 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41658 /* xmm16-xmm31 are only available for AVX-512. */
41662 /* OImode and AVX modes are available only when AVX is enabled. */
41669 }
41671 {
41672 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41673 so if the register is available at all, then we can move data of
41674 the given mode into or out of it. */
41677 }
41680 {
41681 /* Take care for QImode values - they can be in non-QI regs,
41682 but then they do cause partial register stalls. */
41687 /* LRA checks if the hard register is OK for the given mode.
41688 QImode values can live in non-QI regs, so we allow all
41689 registers here. */
41693 }
41694 /* We handle both integer and floats in the general purpose registers. */
41701 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41702 on to use that value in smaller contexts, this can easily force a
41703 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41704 supporting DImode, allow it. */
41709 }
41711 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41712 tieable integer mode. */
41714 static bool
41716 {
41718 {
41731 }
41732 }
41734 /* Return true if MODE1 is accessible in a register that can hold MODE2
41735 without copying. That is, all register classes that can hold MODE2
41736 can also hold MODE1. */
41738 bool
41740 {
41748 /* MODE2 being XFmode implies fp stack or general regs, which means we
41749 can tie any smaller floating point modes to it. Note that we do not
41750 tie this with TFmode. */
41754 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41755 that we can tie it with SFmode. */
41759 /* If MODE2 is only appropriate for an SSE register, then tie with
41760 any other mode acceptable to SSE registers. */
41770 /* If MODE2 is appropriate for an MMX register, then tie
41771 with any other mode acceptable to MMX registers. */
41778 }
41780 /* Return the cost of moving between two registers of mode MODE. */
41782 static int
41784 {
41788 {
41820 }
41822 /* Return the cost of moving between two registers of mode MODE,
41823 assuming that the move will be in pieces of at most UNITS bytes. */
41825 }
41827 /* Compute a (partial) cost for rtx X. Return true if the complete
41828 cost has been computed, and false if subexpressions should be
41829 scanned. In either case, *TOTAL contains the cost result. */
41831 static bool
41834 {
41835 rtx mask;
41842 {
41846 {
41849 }
41861 && !(TARGET_64BIT
41866 else
41872 {
41875 }
41877 {
41887 }
41889 {
41892 {
41901 }
41902 }
41903 /* Fall back to (MEM (SYMBOL_REF)), since that's where
41904 it'll probably end up. Add a penalty for size. */
41911 /* The zero extensions is often completely free on x86_64, so make
41912 it as cheap as possible. */
41918 else
41930 {
41933 {
41936 }
41939 {
41942 }
41943 }
41944 /* FALLTHRU */
41951 {
41952 /* ??? Should be SSE vector operation cost. */
41953 /* At least for published AMD latencies, this really is the same
41954 as the latency for a simple fpu operation like fabs. */
41955 /* V*QImode is emulated with 1-11 insns. */
41957 {
41960 {
41961 /* For XOP we use vpshab, which requires a broadcast of the
41962 value to the variable shift insn. For constants this
41963 means a V16Q const in mem; even when we can perform the
41964 shift with one insn set the cost to prefer paddb. */
41966 {
41971 }
41973 }
41977 }
41978 else
41980 }
41982 {
41984 {
41987 else
41989 }
41990 else
41991 {
41994 else
41996 }
41997 }
41998 else
41999 {
42004 {
42005 /* Return the cost after shift-and truncation. */
42008 }
42009 else
42011 }
42015 {
42016 rtx sub;
42021 /* ??? SSE scalar/vector cost should be used here. */
42022 /* ??? Bald assumption that fma has the same cost as fmul. */
42026 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42037 }
42041 {
42042 /* ??? SSE scalar cost should be used here. */
42045 }
42047 {
42050 }
42052 {
42053 /* ??? SSE vector cost should be used here. */
42056 }
42058 {
42059 /* V*QImode is emulated with 7-13 insns. */
42061 {
42068 }
42069 /* V*DImode is emulated with 5-8 insns. */
42071 {
42074 else
42076 }
42077 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42078 insns, including two PMULUDQ. */
42081 else
42084 }
42085 else
42086 {
42091 {
42094 nbits++;
42095 }
42096 else
42097 /* This is arbitrary. */
42100 /* Compute costs correctly for widening multiplication. */
42104 {
42111 {
42115 else
42117 }
42121 }
42129 }
42136 /* ??? SSE cost should be used here. */
42141 /* ??? SSE vector cost should be used here. */
42143 else
42150 {
42155 {
42158 {
42166 }
42167 }
42170 {
42173 {
42179 }
42180 }
42182 {
42190 }
42191 }
42192 /* FALLTHRU */
42196 {
42197 /* ??? SSE cost should be used here. */
42200 }
42202 {
42205 }
42207 {
42208 /* ??? SSE vector cost should be used here. */
42211 }
42212 /* FALLTHRU */
42219 {
42226 }
42227 /* FALLTHRU */
42231 {
42232 /* ??? SSE cost should be used here. */
42235 }
42237 {
42240 }
42242 {
42243 /* ??? SSE vector cost should be used here. */
42246 }
42247 /* FALLTHRU */
42251 {
42252 /* ??? Should be SSE vector operation cost. */
42253 /* At least for published AMD latencies, this really is the same
42254 as the latency for a simple fpu operation like fabs. */
42256 }
42259 else
42268 {
42269 /* This kind of construct is implemented using test[bwl].
42270 Treat it as if we had an AND. */
42275 }
42285 /* ??? SSE cost should be used here. */
42290 /* ??? SSE vector cost should be used here. */
42296 /* ??? SSE cost should be used here. */
42301 /* ??? SSE vector cost should be used here. */
42313 /* ??? Assume all of these vector manipulation patterns are
42314 recognizable. In which case they all pretty much have the
42315 same cost. */
42320 /* This is masked instruction, assume the same cost,
42321 as nonmasked variant. */
42324 else
42330 }
42331 }
42333 #if TARGET_MACHO
42337 /* Given a symbol name and its associated stub, write out the
42338 definition of the stub. */
42340 void
42342 {
42347 /* For 64-bit we shouldn't get here. */
42350 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42367 else
42374 {
42376 }
42378 {
42379 /* PIC stub. */
42380 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42386 }
42387 else
42390 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42391 it needs no stub-binding-helper. */
42398 {
42401 }
42402 else
42407 /* N.B. Keep the correspondence of these
42408 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42409 old-pic/new-pic/non-pic stubs; altering this will break
42410 compatibility with existing dylibs. */
42412 {
42413 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42415 }
42416 else
42417 /* 16-byte -mdynamic-no-pic stub. */
42423 }
42426 /* Order the registers for register allocator. */
42428 void
42430 {
42434 /* First allocate the local general purpose registers. */
42439 /* Global general purpose registers. */
42444 /* x87 registers come first in case we are doing FP math
42445 using them. */
42450 /* SSE registers. */
42456 /* Extended REX SSE registers. */
42460 /* Mask register. */
42464 /* MPX bound registers. */
42468 /* x87 registers. */
42476 /* Initialize the rest of array as we do not allocate some registers
42477 at all. */
42480 }
42482 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42483 in struct attribute_spec handler. */
42484 static tree
42486 tree args,
42489 {
42494 {
42496 name);
42499 }
42501 {
42503 name);
42506 }
42508 {
42509 tree cst;
42513 {
42516 name);
42518 }
42521 {
42524 name);
42526 }
42529 }
42532 }
42534 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42535 struct attribute_spec.handler. */
42536 static tree
42539 {
42544 {
42546 name);
42549 }
42551 /* Can combine regparm with all attributes but fastcall. */
42553 {
42555 {
42557 }
42560 }
42562 {
42564 {
42566 }
42569 }
42572 }
42574 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42575 struct attribute_spec.handler. */
42576 static tree
42579 {
42582 {
42585 }
42586 else
42590 {
42592 name);
42594 }
42600 {
42602 name);
42604 }
42607 }
42609 static tree
42612 {
42614 {
42616 name);
42618 }
42620 }
42622 static bool
42624 {
42628 }
42630 /* Returns an expression indicating where the this parameter is
42631 located on entry to the FUNCTION. */
42633 static rtx
42635 {
42641 {
42646 else
42649 }
42654 {
42661 {
42666 }
42667 else
42668 {
42671 {
42677 }
42678 }
42680 }
42684 }
42686 /* Determine whether x86_output_mi_thunk can succeed. */
42688 static bool
42690 const_tree function)
42691 {
42692 /* 64-bit can handle anything. */
42696 /* For 32-bit, everything's fine if we have one free register. */
42700 /* Need a free register for vcall_offset. */
42704 /* Need a free register for GOT references. */
42708 /* Otherwise ok. */
42710 }
42712 /* Output the assembler code for a thunk function. THUNK_DECL is the
42713 declaration for the thunk function itself, FUNCTION is the decl for
42714 the target function. DELTA is an immediate constant offset to be
42715 added to THIS. If VCALL_OFFSET is nonzero, the word at
42716 *(*this + vcall_offset) should be added to THIS. */
42718 static void
42721 {
42729 else
42730 {
42736 else
42738 }
42742 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42743 pull it in now and let DELTA benefit. */
42747 {
42748 /* Put the this parameter into %eax. */
42751 }
42752 else
42755 /* Adjust the this parameter by a fixed constant. */
42757 {
42762 {
42764 {
42768 }
42769 }
42772 }
42774 /* Adjust the this parameter by a value stored in the vtable. */
42776 {
42786 /* Adjust the this parameter. */
42790 {
42794 }
42801 vcall_mem));
42802 else
42804 }
42806 /* If necessary, drop THIS back to its stack slot. */
42812 {
42815 ;
42816 else
42817 {
42821 }
42822 }
42823 else
42824 {
42826 ;
42827 #if TARGET_MACHO
42829 {
42832 }
42834 else
42835 {
42843 }
42844 }
42846 /* Our sibling call patterns do not allow memories, because we have no
42847 predicate that can distinguish between frame and non-frame memory.
42848 For our purposes here, we can get away with (ab)using a jump pattern,
42849 because we're going to do no optimization. */
42851 {
42853 {
42859 }
42860 else
42862 }
42863 else
42864 {
42866 {
42867 // CM_LARGE_PIC always uses pseudo PIC register which is
42868 // uninitialized. Since FUNCTION is local and calling it
42869 // doesn't go through PLT, we use scratch register %r11 as
42870 // PIC register and initialize it here.
42875 }
42878 {
42884 }
42890 }
42893 /* Emit just enough of rest_of_compilation to get the insns emitted.
42894 Note that use_thunk calls assemble_start_function et al. */
42900 }
42902 static void
42904 {
42908 #if TARGET_MACHO
42910 #endif
42917 }
42919 int
42921 {
42922 machine_mode mode;
42933 }
42935 /* Print call to TARGET to FILE. */
42937 static void
42939 {
42942 else
42944 }
42946 /* Output assembler code to FILE to increment profiler label # LABELNO
42947 for profiling a function entry. */
42948 void
42950 {
42954 {
42955 #ifndef NO_PROFILE_COUNTERS
42957 #endif
42961 else
42963 }
42965 {
42966 #ifndef NO_PROFILE_COUNTERS
42969 #endif
42971 }
42972 else
42973 {
42974 #ifndef NO_PROFILE_COUNTERS
42977 #endif
42979 }
42982 {
42986 }
42987 }
42989 /* We don't have exact information about the insn sizes, but we may assume
42990 quite safely that we are informed about all 1 byte insns and memory
42991 address sizes. This is enough to eliminate unnecessary padding in
42992 99% of cases. */
42994 static int
42996 {
43002 /* Discard alignments we've emit and jump instructions. */
43007 /* Important case - calls are always 5 bytes.
43008 It is common to have many calls in the row. */
43017 /* For normal instructions we rely on get_attr_length being exact,
43018 with a few exceptions. */
43020 {
43024 {
43034 /* Otherwise trust get_attr_length. */
43036 }
43041 }
43044 else
43046 }
43048 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43050 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43051 window. */
43053 static void
43055 {
43060 /* Look for all minimal intervals of instructions containing 4 jumps.
43061 The intervals are bounded by START and INSN. NBYTES is the total
43062 size of instructions in the interval including INSN and not including
43063 START. When the NBYTES is smaller than 16 bytes, it is possible
43064 that the end of START and INSN ends up in the same 16byte page.
43066 The smallest offset in the page INSN can start is the case where START
43067 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43068 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43070 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43071 have to, control transfer to label(s) can be performed through other
43072 means, and also we estimate minimum length of all asm stmts as 0. */
43074 {
43078 {
43084 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43085 already in the current 16 byte page, because otherwise
43086 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43087 bytes to reach 16 byte boundary. */
43095 {
43097 {
43102 else
43105 }
43106 }
43108 }
43117 njumps++;
43118 else
43122 {
43127 else
43130 }
43137 {
43144 }
43145 }
43146 }
43147 #endif
43149 /* AMD Athlon works faster
43150 when RET is not destination of conditional jump or directly preceded
43151 by other jump instruction. We avoid the penalty by inserting NOP just
43152 before the RET instructions in such cases. */
43153 static void
43155 {
43156 edge e;
43157 edge_iterator ei;
43160 {
43173 {
43174 edge e;
43175 edge_iterator ei;
43180 {
43183 }
43184 }
43186 {
43192 /* Empty functions get branch mispredict even when
43193 the jump destination is not visible to us. */
43196 }
43198 {
43201 }
43202 }
43203 }
43205 /* Count the minimum number of instructions in BB. Return 4 if the
43206 number of instructions >= 4. */
43208 static int
43210 {
43214 /* Count number of instructions in this block. Return 4 if the number
43215 of instructions >= 4. */
43217 {
43218 /* Only happen in exit blocks. */
43226 {
43227 insn_count++;
43230 }
43231 }
43234 }
43237 /* Count the minimum number of instructions in code path in BB.
43238 Return 4 if the number of instructions >= 4. */
43240 static int
43242 {
43243 edge e;
43244 edge_iterator ei;
43247 /* Only bother counting instructions along paths with no
43248 more than 2 basic blocks between entry and exit. Given
43249 that BB has an edge to exit, determine if a predecessor
43250 of BB has an edge from entry. If so, compute the number
43251 of instructions in the predecessor block. If there
43252 happen to be multiple such blocks, compute the minimum. */
43255 {
43256 edge prev_e;
43257 edge_iterator prev_ei;
43260 {
43263 }
43265 {
43267 {
43272 }
43273 }
43274 }
43280 }
43282 /* Pad short function to 4 instructions. */
43284 static void
43286 {
43287 edge e;
43288 edge_iterator ei;
43291 {
43294 {
43297 /* Pad short function. */
43299 {
43302 /* Find epilogue. */
43311 /* Two NOPs count as one instruction. */
43314 }
43315 }
43316 }
43317 }
43319 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43320 the epilogue, the Windows system unwinder will apply epilogue logic and
43321 produce incorrect offsets. This can be avoided by adding a nop between
43322 the last insn that can throw and the first insn of the epilogue. */
43324 static void
43326 {
43327 edge e;
43328 edge_iterator ei;
43331 {
43334 /* Find the beginning of the epilogue. */
43341 /* We only care about preceding insns that can throw. */
43346 /* Do not separate calls from their debug information. */
43352 else
43356 }
43357 }
43359 /* Implement machine specific optimizations. We implement padding of returns
43360 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43361 static void
43363 {
43364 /* We are freeing block_for_insn in the toplev to keep compatibility
43365 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43372 {
43377 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43380 #endif
43381 }
43382 }
43384 /* Return nonzero when QImode register that must be represented via REX prefix
43385 is used. */
43386 bool
43388 {
43396 }
43398 /* Return true when INSN mentions register that must be encoded using REX
43399 prefix. */
43400 bool
43402 {
43405 {
43410 }
43412 }
43414 /* If profitable, negate (without causing overflow) integer constant
43415 of mode MODE at location LOC. Return true in this case. */
43416 bool
43418 {
43419 HOST_WIDE_INT val;
43425 {
43427 /* DImode x86_64 constants must fit in 32 bits. */
43440 }
43442 /* Avoid overflows. */
43448 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43449 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43452 {
43455 }
43458 }
43460 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43461 optabs would emit if we didn't have TFmode patterns. */
43463 void
43465 {
43500 }
43501 \f
43507 /* Get a vector mode of the same size as the original but with elements
43508 twice as wide. This is only guaranteed to apply to integral vectors. */
43512 {
43513 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43518 }
43520 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43521 fill target with val via vec_duplicate. */
43523 static bool
43525 {
43528 rtx dup;
43530 /* First attempt to recognize VAL as-is. */
43534 {
43536 /* If that fails, force VAL into a register. */
43547 }
43549 }
43551 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43552 with all elements equal to VAR. Return true if successful. */
43554 static bool
43557 {
43561 {
43566 /* FALLTHRU */
43586 {
43587 rtx x;
43594 }
43607 {
43611 permute:
43619 /* Extend to SImode using a paradoxical SUBREG. */
43623 /* Insert the SImode value as low element of a V4SImode vector. */
43632 }
43643 widen:
43644 /* Replicate the value once into the next wider mode and recurse. */
43645 {
43647 rtx x;
43664 }
43670 else
43671 {
43680 }
43687 else
43688 {
43697 }
43702 }
43703 }
43705 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43706 whose ONE_VAR element is VAR, and other elements are zero. Return true
43707 if successful. */
43709 static bool
43712 {
43713 machine_mode vsimode;
43714 rtx new_target;
43719 {
43721 /* For SSE4.1, we normally use vector set. But if the second
43722 element is zero and inter-unit moves are OK, we use movq
43723 instead. */
43725 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43747 /* Use ix86_expand_vector_set in 64bit mode only. */
43752 }
43755 {
43760 }
43763 {
43768 /* FALLTHRU */
43783 else
43790 {
43791 /* We need to shuffle the value to the correct position, so
43792 create a new pseudo to store the intermediate result. */
43794 /* With SSE2, we can use the integer shuffle insns. */
43796 {
43798 const1_rtx,
43805 }
43807 /* Otherwise convert the intermediate result to V4SFmode and
43808 use the SSE1 shuffle instructions. */
43810 {
43813 }
43814 else
43818 const1_rtx,
43827 }
43842 widen:
43846 /* Zero extend the variable element to SImode and recurse. */
43859 }
43860 }
43862 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43863 consisting of the values in VALS. It is known that all elements
43864 except ONE_VAR are constants. Return true if successful. */
43866 static bool
43869 {
43871 machine_mode wmode;
43879 {
43884 /* For the two element vectors, it's just as easy to use
43885 the general case. */
43889 /* Use ix86_expand_vector_set in 64bit mode only. */
43911 widen:
43912 /* There's no way to set one QImode entry easily. Combine
43913 the variable value with its adjacent constant value, and
43914 promote to an HImode set. */
43917 {
43922 }
43923 else
43924 {
43927 }
43941 }
43946 }
43948 /* A subroutine of ix86_expand_vector_init_general. Use vector
43949 concatenate to handle the most general case: all values variable,
43950 and none identical. */
43952 static void
43955 {
43958 rtvec v;
43962 {
43965 {
44010 }
44023 {
44038 }
44043 {
44062 }
44067 {
44080 }
44083 half:
44084 /* FIXME: We process inputs backward to help RA. PR 36222. */
44088 {
44093 }
44097 {
44101 {
44105 }
44108 {
44112 }
44115 }
44117 {
44120 {
44124 }
44127 }
44128 else
44134 }
44135 }
44137 /* A subroutine of ix86_expand_vector_init_general. Use vector
44138 interleave to handle the most general case: all values variable,
44139 and none identical. */
44141 static void
44144 {
44153 {
44174 }
44177 {
44178 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44182 /* Insert the SImode value as low element of V4SImode vector. */
44186 op0),
44188 const1_rtx);
44191 /* Cast the V4SImode vector back to a vector in orignal mode. */
44195 /* Load even elements into the second position. */
44199 const1_rtx));
44201 /* Cast vector to FIRST_IMODE vector. */
44204 }
44206 /* Interleave low FIRST_IMODE vectors. */
44208 {
44212 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44215 }
44217 /* Interleave low SECOND_IMODE vectors. */
44219 {
44222 {
44227 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44228 vector. */
44231 }
44234 /* FALLTHRU */
44241 /* Cast the SECOND_IMODE vector back to a vector on original
44242 mode. */
44249 }
44250 }
44252 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44253 all values variable, and none identical. */
44255 static void
44258 {
44265 {
44270 /* FALLTHRU */
44298 half:
44322 quarter:
44351 /* FALLTHRU */
44357 /* Don't use ix86_expand_vector_init_interleave if we can't
44358 move from GPR to SSE register directly. */
44374 }
44376 {
44378 machine_mode inner_mode;
44388 {
44392 {
44398 else
44399 {
44404 }
44405 }
44408 }
44413 {
44419 }
44421 {
44427 }
44428 else
44430 }
44431 }
44433 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44434 instructions unless MMX_OK is true. */
44436 void
44438 {
44445 rtx x;
44448 {
44458 }
44460 /* Constants are best loaded from the constant pool. */
44462 {
44465 }
44467 /* If all values are identical, broadcast the value. */
44473 /* Values where only one field is non-constant are best loaded from
44474 the pool and overwritten via move later. */
44476 {
44480 one_var))
44485 }
44488 }
44490 void
44492 {
44495 machine_mode half_mode;
44497 rtx tmp;
44499 = {
44506 };
44508 = {
44515 };
44519 {
44523 {
44528 else
44532 }
44544 else
44550 {
44553 /* For the two element vectors, we implement a VEC_CONCAT with
44554 the extraction of the other element. */
44561 else
44566 }
44575 {
44581 /* tmp = target = A B C D */
44583 /* target = A A B B */
44585 /* target = X A B B */
44587 /* target = A X C D */
44594 /* tmp = target = A B C D */
44596 /* tmp = X B C D */
44598 /* target = A B X D */
44605 /* tmp = target = A B C D */
44607 /* tmp = X B C D */
44609 /* target = A B X D */
44617 }
44625 /* Element 0 handled by vec_merge below. */
44627 {
44630 }
44633 {
44634 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44635 store into element 0, then shuffle them back. */
44652 }
44653 else
44654 {
44655 /* For SSE1, we have to reuse the V4SF code. */
44659 }
44712 half:
44713 /* Compute offset. */
44719 /* Extract the half. */
44723 /* Put val in tmp at elt. */
44726 /* Put it back. */
44732 {
44739 }
44740 else
44744 {
44751 }
44752 else
44756 {
44763 }
44764 else
44768 {
44775 }
44776 else
44780 {
44787 }
44788 else
44792 {
44799 }
44800 else
44805 }
44808 {
44812 }
44813 else
44814 {
44823 }
44824 }
44826 void
44828 {
44832 rtx tmp;
44835 {
44840 /* FALLTHRU */
44853 {
44873 }
44885 {
44887 {
44907 }
44911 }
44912 else
44913 {
44914 /* For SSE1, we have to reuse the V4SF code. */
44918 }
44934 {
44938 else
44942 }
44947 {
44951 else
44955 }
44960 {
44964 else
44968 }
44973 {
44977 else
44981 }
44986 {
44990 else
44994 }
44999 {
45003 else
45007 }
45012 {
45016 else
45020 }
45025 {
45029 else
45033 }
45040 else
45049 else
45058 else
45067 else
45073 /* ??? Could extract the appropriate HImode element and shift. */
45076 }
45079 {
45083 /* Let the rtl optimizers know about the zero extension performed. */
45085 {
45088 }
45091 }
45092 else
45093 {
45100 }
45101 }
45103 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45104 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45105 The upper bits of DEST are undefined, though they shouldn't cause
45106 exceptions (some bits from src or all zeros are ok). */
45108 static void
45110 {
45113 {
45117 else
45135 else
45142 else
45150 {
45155 const1_rtx);
45156 }
45157 else
45158 {
45162 }
45184 else
45206 }
45210 }
45212 /* Expand a vector reduction. FN is the binary pattern to reduce;
45213 DEST is the destination; IN is the input vector. */
45215 void
45217 {
45222 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45226 {
45229 }
45234 {
45239 else
45243 }
45244 }
45245 \f
45246 /* Target hook for scalar_mode_supported_p. */
45247 static bool
45249 {
45254 else
45256 }
45258 /* Implements target hook vector_mode_supported_p. */
45259 static bool
45261 {
45275 }
45277 /* Implement target hook libgcc_floating_mode_supported_p. */
45278 static bool
45280 {
45282 {
45289 #ifdef IX86_NO_LIBGCC_TFMODE
45291 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45293 #else
45295 #endif
45299 }
45300 }
45302 /* Target hook for c_mode_for_suffix. */
45303 static machine_mode
45305 {
45312 }
45314 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45316 We do this in the new i386 backend to maintain source compatibility
45317 with the old cc0-based compiler. */
45319 static tree
45321 {
45323 clobbers);
45325 clobbers);
45327 }
45329 /* Implements target vector targetm.asm.encode_section_info. */
45331 static void ATTRIBUTE_UNUSED
45333 {
45338 }
45340 /* Worker function for REVERSE_CONDITION. */
45342 enum rtx_code
45344 {
45348 }
45350 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45351 to OPERANDS[0]. */
45355 {
45357 {
45360 {
45364 }
45368 }
45370 {
45374 else
45375 {
45376 /* There is no non-popping store to memory for XFmode.
45377 So if we need one, follow the store with a load. */
45380 else
45382 }
45383 }
45384 else
45386 }
45388 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45389 FP status register is set. */
45391 void
45393 {
45395 rtx temp;
45400 {
45405 }
45406 else
45407 {
45412 }
45416 pc_rtx);
45421 }
45423 /* Output code to perform a log1p XFmode calculation. */
45426 {
45432 rtx test;
45438 XFmode));
45452 }
45454 /* Emit code for round calculation. */
45456 {
45463 rtx insn;
45468 {
45480 }
45483 {
45504 }
45512 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45514 /* scratch = fxam(op1) */
45517 UNSPEC_FXAM)));
45518 /* e1 = fabs(op1) */
45521 /* e2 = e1 + 0.5 */
45526 /* res = floor(e2) */
45528 {
45533 }
45534 else
45538 {
45541 {
45548 UNSPEC_TRUNC_NOOP)));
45549 }
45565 }
45567 /* flags = signbit(a) */
45570 /* if (flags) then res = -res */
45574 pc_rtx);
45585 }
45587 /* Output code to perform a Newton-Rhapson approximation of a single precision
45588 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45591 {
45599 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45603 /* x0 = rcp(b) estimate */
45607 UNSPEC_RCP14)));
45608 else
45611 UNSPEC_RCP)));
45613 /* e0 = x0 * b */
45617 /* e0 = x0 * e0 */
45621 /* e1 = x0 + x0 */
45625 /* x1 = e1 - e0 */
45629 /* res = a * x1 */
45632 }
45634 /* Output code to perform a Newton-Rhapson approximation of a
45635 single precision floating point [reciprocal] square root. */
45639 {
45641 REAL_VALUE_TYPE r;
45658 {
45661 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45664 }
45666 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45667 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45671 /* x0 = rsqrt(a) estimate */
45674 unspec)));
45676 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45678 {
45686 /* Handle masked compare. */
45688 {
45690 /* Imm value 0x4 corresponds to not-equal comparison. */
45693 }
45694 else
45695 {
45701 }
45702 }
45704 /* e0 = x0 * a */
45707 /* e1 = e0 * x0 */
45711 /* e2 = e1 - 3. */
45718 /* e3 = -.5 * x0 */
45721 else
45722 /* e3 = -.5 * e0 */
45725 /* ret = e2 * e3 */
45728 }
45730 #ifdef TARGET_SOLARIS
45731 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45733 static void
45735 tree decl)
45736 {
45737 /* With Binutils 2.15, the "@unwind" marker must be specified on
45738 every occurrence of the ".eh_frame" section, not just the first
45739 one. */
45742 {
45746 }
45748 #ifndef USE_GAS
45750 {
45753 }
45754 #endif
45757 }
45760 /* Return the mangling of TYPE if it is an extended fundamental type. */
45764 {
45772 {
45774 /* __float128 is "g". */
45777 /* "long double" or __float80 is "e". */
45781 }
45782 }
45784 /* For 32-bit code we can save PIC register setup by using
45785 __stack_chk_fail_local hidden function instead of calling
45786 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45787 register, so it is better to call __stack_chk_fail directly. */
45789 static tree ATTRIBUTE_UNUSED
45791 {
45792 return TARGET_64BIT
45795 }
45797 /* Select a format to encode pointers in exception handling data. CODE
45798 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45799 true if the symbol may be affected by dynamic relocations.
45801 ??? All x86 object file formats are capable of representing this.
45802 After all, the relocation needed is the same as for the call insn.
45803 Whether or not a particular assembler allows us to enter such, I
45804 guess we'll have to see. */
45805 int
45807 {
45809 {
45816 }
45821 }
45822 \f
45823 /* Expand copysign from SIGN to the positive value ABS_VALUE
45824 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45825 the sign-bit. */
45826 static void
45828 {
45832 {
45833 machine_mode vmode;
45839 else
45844 {
45845 /* We need to generate a scalar mode mask in this case. */
45850 }
45851 }
45852 else
45858 }
45860 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45861 mask for masking out the sign-bit is stored in *SMASK, if that is
45862 non-null. */
45863 static rtx
45865 {
45874 else
45878 {
45879 /* We need to generate a scalar mode mask in this case. */
45884 }
45892 }
45894 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
45895 swapping the operands if SWAP_OPERANDS is true. The expanded
45896 code is a forward jump to a newly created label in case the
45897 comparison is true. The generated label rtx is returned. */
45901 {
45904 rtx tmp;
45920 }
45922 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
45923 using comparison code CODE. Operands are swapped for the comparison if
45924 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
45925 static rtx
45928 {
45941 }
45943 /* Generate and return a rtx of mode MODE for 2**n where n is the number
45944 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
45945 static rtx
45947 {
45948 REAL_VALUE_TYPE TWO52r;
45949 rtx TWO52;
45956 }
45958 /* Expand SSE sequence for computing lround from OP1 storing
45959 into OP0. */
45960 void
45962 {
45963 /* C code for the stuff we're doing below:
45964 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
45965 return (long)tmp;
45966 */
45970 rtx adj;
45972 /* load nextafter (0.5, 0.0) */
45977 /* adj = copysign (0.5, op1) */
45981 /* adj = op1 + adj */
45984 /* op0 = (imode)adj */
45986 }
45988 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
45989 into OPERAND0. */
45990 void
45992 {
45993 /* C code for the stuff we're doing below (for do_floor):
45994 xi = (long)op1;
45995 xi -= (double)xi > op1 ? 1 : 0;
45996 return xi;
45997 */
46003 /* reg = (long)op1 */
46007 /* freg = (double)reg */
46011 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46022 }
46024 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46025 result in OPERAND0. */
46026 void
46028 {
46029 /* C code for the stuff we're doing below:
46030 xa = fabs (operand1);
46031 if (!isless (xa, 2**52))
46032 return operand1;
46033 xa = xa + 2**52 - 2**52;
46034 return copysign (xa, operand1);
46035 */
46043 /* xa = abs (operand1) */
46046 /* if (!isless (xa, TWO52)) goto label; */
46059 }
46061 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46062 into OPERAND0. */
46063 void
46065 {
46066 /* C code for the stuff we expand below.
46067 double xa = fabs (x), x2;
46068 if (!isless (xa, TWO52))
46069 return x;
46070 xa = xa + TWO52 - TWO52;
46071 x2 = copysign (xa, x);
46072 Compensate. Floor:
46073 if (x2 > x)
46074 x2 -= 1;
46075 Compensate. Ceil:
46076 if (x2 < x)
46077 x2 -= -1;
46078 return x2;
46079 */
46086 /* Temporary for holding the result, initialized to the input
46087 operand to ease control flow. */
46091 /* xa = abs (operand1) */
46094 /* if (!isless (xa, TWO52)) goto label; */
46097 /* xa = xa + TWO52 - TWO52; */
46101 /* xa = copysign (xa, operand1) */
46104 /* generate 1.0 or -1.0 */
46109 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46113 /* We always need to subtract here to preserve signed zero. */
46122 }
46124 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46125 into OPERAND0. */
46126 void
46128 {
46129 /* C code for the stuff we expand below.
46130 double xa = fabs (x), x2;
46131 if (!isless (xa, TWO52))
46132 return x;
46133 x2 = (double)(long)x;
46134 Compensate. Floor:
46135 if (x2 > x)
46136 x2 -= 1;
46137 Compensate. Ceil:
46138 if (x2 < x)
46139 x2 += 1;
46140 if (HONOR_SIGNED_ZEROS (mode))
46141 return copysign (x2, x);
46142 return x2;
46143 */
46150 /* Temporary for holding the result, initialized to the input
46151 operand to ease control flow. */
46155 /* xa = abs (operand1) */
46158 /* if (!isless (xa, TWO52)) goto label; */
46161 /* xa = (double)(long)x */
46166 /* generate 1.0 */
46169 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46184 }
46186 /* Expand SSE sequence for computing round from OPERAND1 storing
46187 into OPERAND0. Sequence that works without relying on DImode truncation
46188 via cvttsd2siq that is only available on 64bit targets. */
46189 void
46191 {
46192 /* C code for the stuff we expand below.
46193 double xa = fabs (x), xa2, x2;
46194 if (!isless (xa, TWO52))
46195 return x;
46196 Using the absolute value and copying back sign makes
46197 -0.0 -> -0.0 correct.
46198 xa2 = xa + TWO52 - TWO52;
46199 Compensate.
46200 dxa = xa2 - xa;
46201 if (dxa <= -0.5)
46202 xa2 += 1;
46203 else if (dxa > 0.5)
46204 xa2 -= 1;
46205 x2 = copysign (xa2, x);
46206 return x2;
46207 */
46214 /* Temporary for holding the result, initialized to the input
46215 operand to ease control flow. */
46219 /* xa = abs (operand1) */
46222 /* if (!isless (xa, TWO52)) goto label; */
46225 /* xa2 = xa + TWO52 - TWO52; */
46229 /* dxa = xa2 - xa; */
46232 /* generate 0.5, 1.0 and -0.5 */
46238 /* Compensate. */
46240 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46245 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46251 /* res = copysign (xa2, operand1) */
46258 }
46260 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46261 into OPERAND0. */
46262 void
46264 {
46265 /* C code for SSE variant we expand below.
46266 double xa = fabs (x), x2;
46267 if (!isless (xa, TWO52))
46268 return x;
46269 x2 = (double)(long)x;
46270 if (HONOR_SIGNED_ZEROS (mode))
46271 return copysign (x2, x);
46272 return x2;
46273 */
46280 /* Temporary for holding the result, initialized to the input
46281 operand to ease control flow. */
46285 /* xa = abs (operand1) */
46288 /* if (!isless (xa, TWO52)) goto label; */
46291 /* x = (double)(long)x */
46303 }
46305 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46306 into OPERAND0. */
46307 void
46309 {
46314 /* C code for SSE variant we expand below.
46315 double xa = fabs (x), x2;
46316 if (!isless (xa, TWO52))
46317 return x;
46318 xa2 = xa + TWO52 - TWO52;
46319 Compensate:
46320 if (xa2 > xa)
46321 xa2 -= 1.0;
46322 x2 = copysign (xa2, x);
46323 return x2;
46324 */
46328 /* Temporary for holding the result, initialized to the input
46329 operand to ease control flow. */
46333 /* xa = abs (operand1) */
46336 /* if (!isless (xa, TWO52)) goto label; */
46339 /* res = xa + TWO52 - TWO52; */
46344 /* generate 1.0 */
46347 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46355 /* res = copysign (res, operand1) */
46362 }
46364 /* Expand SSE sequence for computing round from OPERAND1 storing
46365 into OPERAND0. */
46366 void
46368 {
46369 /* C code for the stuff we're doing below:
46370 double xa = fabs (x);
46371 if (!isless (xa, TWO52))
46372 return x;
46373 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46374 return copysign (xa, x);
46375 */
46382 /* Temporary for holding the result, initialized to the input
46383 operand to ease control flow. */
46391 /* load nextafter (0.5, 0.0) */
46396 /* xa = xa + 0.5 */
46400 /* xa = (double)(int64_t)xa */
46405 /* res = copysign (xa, operand1) */
46412 }
46414 /* Expand SSE sequence for computing round
46415 from OP1 storing into OP0 using sse4 round insn. */
46416 void
46418 {
46427 {
46438 }
46440 /* round (a) = trunc (a + copysign (0.5, a)) */
46442 /* load nextafter (0.5, 0.0) */
46448 /* e1 = copysign (0.5, op1) */
46452 /* e2 = op1 + e1 */
46455 /* res = trunc (e2) */
46460 }
46461 \f
46463 /* Table of valid machine attributes. */
46465 {
46466 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46467 affects_type_identity } */
46468 /* Stdcall attribute says callee is responsible for popping arguments
46469 if they are not variable. */
46472 /* Fastcall attribute says callee is responsible for popping arguments
46473 if they are not variable. */
46476 /* Thiscall attribute says callee is responsible for popping arguments
46477 if they are not variable. */
46480 /* Cdecl attribute says the callee is a normal C declaration */
46483 /* Regparm attribute specifies how many integer arguments are to be
46484 passed in registers. */
46487 /* Sseregparm attribute says we are using x86_64 calling conventions
46488 for FP arguments. */
46491 /* The transactional memory builtins are implicitly regparm or fastcall
46492 depending on the ABI. Override the generic do-nothing attribute that
46493 these builtins were declared with. */
46496 /* force_align_arg_pointer says this function realigns the stack at entry. */
46499 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46504 #endif
46509 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46510 SUBTARGET_ATTRIBUTE_TABLE,
46511 #endif
46512 /* ms_abi and sysv_abi calling convention function attributes. */
46519 /* End element. */
46521 };
46523 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46524 static int
46527 {
46531 {
46576 }
46577 }
46579 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46580 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46581 insn every time. */
46585 /* Initialize vselect_insn. */
46587 static void
46589 {
46591 rtx x;
46602 }
46604 /* Construct (set target (vec_select op0 (parallel perm))) and
46605 return true if that's a valid instruction in the active ISA. */
46607 static bool
46610 {
46636 }
46638 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46640 static bool
46644 {
46645 machine_mode v2mode;
46646 rtx x;
46661 }
46663 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46664 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46666 static bool
46668 {
46678 ;
46680 ;
46682 ;
46684 ;
46685 else
46688 /* This is a blend, not a permute. Elements must stay in their
46689 respective lanes. */
46691 {
46695 }
46700 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46701 decision should be extracted elsewhere, so that we only try that
46702 sequence once all budget==3 options have been tried. */
46709 {
46739 /* See if bytes move in pairs so we can use pblendw with
46740 an immediate argument, rather than pblendvb with a vector
46741 argument. */
46744 {
46745 use_pblendvb:
46749 finish_pblendvb:
46755 else
46760 }
46765 /* FALLTHRU */
46767 do_subreg:
46774 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46778 /* See if bytes move in quadruplets. If yes, vpblendd
46779 with immediate can be used. */
46784 {
46785 /* See if bytes move the same in both lanes. If yes,
46786 vpblendw with immediate can be used. */
46791 /* Use vpblendw. */
46796 }
46798 /* Use vpblendd. */
46805 /* See if words move in pairs. If yes, vpblendd can be used. */
46810 {
46811 /* See if words move the same in both lanes. If not,
46812 vpblendvb must be used. */
46815 {
46816 /* Use vpblendvb. */
46826 }
46828 /* Use vpblendw. */
46832 }
46834 /* Use vpblendd. */
46841 /* Use vpblendd. */
46849 }
46851 /* This matches five different patterns with the different modes. */
46859 }
46861 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46862 in terms of the variable form of vpermilps.
46864 Note that we will have already failed the immediate input vpermilps,
46865 which requires that the high and low part shuffle be identical; the
46866 variable form doesn't require that. */
46868 static bool
46870 {
46877 /* We can only permute within the 128-bit lane. */
46879 {
46883 }
46889 {
46892 /* Within each 128-bit lane, the elements of op0 are numbered
46893 from 0 and the elements of op1 are numbered from 4. */
46900 }
46907 }
46909 /* Return true if permutation D can be performed as VMODE permutation
46910 instead. */
46912 static bool
46914 {
46929 else
46935 }
46937 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46938 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
46940 static bool
46942 {
46951 {
46953 {
46956 {
46960 /* Use vperm2i128 insn. The pattern uses
46961 V4DImode instead of V2TImode. */
46974 }
46976 }
46977 }
46978 else
46979 {
46981 {
46984 }
46986 {
46990 /* V4DImode should be already handled through
46991 expand_vselect by vpermq instruction. */
46998 {
46999 /* First see if vpermq can be used for
47000 V8SImode/V16HImode/V32QImode. */
47002 {
47010 {
47014 }
47016 }
47018 /* Next see if vpermd can be used. */
47021 }
47022 /* Or if vpermps can be used. */
47027 {
47028 /* vpshufb only works intra lanes, it is not
47029 possible to shuffle bytes in between the lanes. */
47033 }
47034 }
47036 {
47040 /* If vpermq didn't work, vpshufb won't work either. */
47048 {
47049 /* First see if vpermq can be used for
47050 V16SImode/V32HImode/V64QImode. */
47052 {
47060 {
47064 }
47066 }
47068 /* Next see if vpermd can be used. */
47071 }
47072 /* Or if vpermps can be used. */
47076 {
47077 /* vpshufb only works intra lanes, it is not
47078 possible to shuffle bytes in between the lanes. */
47082 }
47083 }
47084 else
47086 }
47097 else
47098 {
47106 else
47110 {
47114 }
47115 }
47126 {
47141 else
47143 }
47144 else
47145 {
47148 }
47153 }
47155 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47156 in a single instruction. */
47158 static bool
47160 {
47164 /* Check plain VEC_SELECT first, because AVX has instructions that could
47165 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47166 input where SEL+CONCAT may not. */
47168 {
47174 {
47180 }
47183 {
47187 }
47189 {
47190 /* Use vpbroadcast{b,w,d}. */
47193 {
47236 /* For other modes prefer other shuffles this function creates. */
47238 }
47240 {
47244 }
47245 }
47250 /* There are plenty of patterns in sse.md that are written for
47251 SEL+CONCAT and are not replicated for a single op. Perhaps
47252 that should be changed, to avoid the nastiness here. */
47254 /* Recognize interleave style patterns, which means incrementing
47255 every other permutation operand. */
47257 {
47260 }
47265 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47267 {
47269 {
47274 }
47279 }
47280 }
47282 /* Finally, try the fully general two operand permute. */
47287 /* Recognize interleave style patterns with reversed operands. */
47289 {
47291 {
47295 else
47298 }
47303 }
47305 /* Try the SSE4.1 blend variable merge instructions. */
47309 /* Try one of the AVX vpermil variable permutations. */
47313 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47314 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47318 /* Try the AVX2 vpalignr instruction. */
47322 /* Try the AVX512F vpermi2 instructions. */
47327 }
47329 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47330 in terms of a pair of pshuflw + pshufhw instructions. */
47332 static bool
47334 {
47342 /* The two permutations only operate in 64-bit lanes. */
47353 /* Emit the pshuflw. */
47360 /* Emit the pshufhw. */
47368 }
47370 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47371 the permutation using the SSSE3 palignr instruction. This succeeds
47372 when all of the elements in PERM fit within one vector and we merely
47373 need to shift them down so that a single vector permutation has a
47374 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47375 the vpalignr instruction itself can perform the requested permutation. */
47377 static bool
47379 {
47386 /* Even with AVX, palignr only operates on 128-bit vectors,
47387 in AVX2 palignr operates on both 128-bit lanes. */
47397 {
47401 {
47404 }
47413 }
47416 {
47425 }
47427 /* Given that we have SSSE3, we know we'll be able to implement the
47428 single operand permutation after the palignr with pshufb for
47429 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47430 first. */
47436 {
47441 }
47445 {
47451 else
47456 }
47462 /* For AVX2, test whether we can permute the result in one instruction. */
47464 {
47469 }
47473 {
47477 }
47478 else
47479 {
47484 shift));
47485 }
47489 /* Test for the degenerate case where the alignment by itself
47490 produces the desired permutation. */
47492 {
47495 }
47501 }
47503 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47504 the permutation using the SSE4_1 pblendv instruction. Potentially
47505 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47507 static bool
47509 {
47515 /* Use the same checks as in expand_vec_perm_blend. */
47519 ;
47521 ;
47523 ;
47524 else
47527 /* Figure out where permutation elements stay not in their
47528 respective lanes. */
47530 {
47534 }
47535 /* We can pblend the part where elements stay not in their
47536 respective lanes only when these elements are all in one
47537 half of a permutation.
47538 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47539 lanes, but both 8 and 9 >= 8
47540 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47541 respective lanes and 8 >= 8, but 2 not. */
47547 /* First we apply one operand permutation to the part where
47548 elements stay not in their respective lanes. */
47552 else
47562 else
47567 /* Next we put permuted elements into their positions. */
47571 else
47581 }
47585 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47586 a two vector permutation into a single vector permutation by using
47587 an interleave operation to merge the vectors. */
47589 static bool
47591 {
47600 {
47603 }
47605 {
47608 /* For 32-byte modes allow even d->one_operand_p.
47609 The lack of cross-lane shuffling in some instructions
47610 might prevent a single insn shuffle. */
47613 /* If expand_vec_perm_interleave3 can expand this into
47614 a 3 insn sequence, give up and let it be expanded as
47615 3 insn sequence. While that is one insn longer,
47616 it doesn't need a memory operand and in the common
47617 case that both interleave low and high permutations
47618 with the same operands are adjacent needs 4 insns
47619 for both after CSE. */
47622 }
47623 else
47626 /* Examine from whence the elements come. */
47635 {
47638 /* Split the two input vectors into 4 halves. */
47644 /* If the elements from the low halves use interleave low, and similarly
47645 for interleave high. If the elements are from mis-matched halves, we
47646 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47648 {
47649 /* punpckl* */
47651 {
47656 }
47659 }
47661 {
47662 /* punpckh* */
47664 {
47669 }
47672 }
47674 {
47675 /* shufps */
47677 {
47682 }
47684 {
47685 /* shufpd */
47690 }
47691 }
47693 {
47694 /* shufps */
47696 {
47701 }
47703 {
47704 /* shufpd */
47709 }
47710 }
47711 else
47713 }
47714 else
47715 {
47720 /* Split the two input vectors into 8 quarters. */
47726 {
47729 }
47732 {
47736 }
47738 {
47741 }
47744 {
47746 {
47747 /* Attempt to increase the likelihood that dfinal
47748 shuffle will be intra-lane. */
47752 }
47754 /* vperm2f128 or vperm2i128. */
47756 {
47761 }
47766 {
47770 {
47773 }
47774 }
47775 }
47780 {
47781 /* vpunpckl* */
47783 {
47792 }
47793 }
47796 {
47797 /* vpunpckh* */
47799 {
47808 }
47809 }
47810 else
47812 }
47814 /* Use the remapping array set up above to move the elements from their
47815 swizzled locations into their final destinations. */
47818 {
47821 /* If same_halves is true, both halves of the remapped vector are the
47822 same. Avoid cross-lane accesses if possible. */
47824 {
47827 }
47828 else
47830 }
47832 {
47835 }
47839 /* Test if the final remap can be done with a single insn. For V4SFmode or
47840 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47853 {
47856 }
47863 }
47865 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47866 a single vector cross-lane permutation into vpermq followed
47867 by any of the single insn permutations. */
47869 static bool
47871 {
47885 {
47888 }
47891 {
47896 }
47909 {
47916 }
47923 {
47928 ;
47931 else
47933 }
47942 }
47944 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
47945 a vector permutation using two instructions, vperm2f128 resp.
47946 vperm2i128 followed by any single in-lane permutation. */
47948 static bool
47950 {
47964 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
47965 immediate. For perm < 16 the second permutation uses
47966 d->op0 as first operand, for perm >= 16 it uses d->op1
47967 as first operand. The second operand is the result of
47968 vperm2[fi]128. */
47970 {
47971 /* Ignore permutations which do not move anything cross-lane. */
47973 {
47974 /* The second shuffle for e.g. V4DFmode has
47975 0123 and ABCD operands.
47976 Ignore AB23, as 23 is already in the second lane
47977 of the first operand. */
47979 /* And 01CD, as 01 is in the first lane of the first
47980 operand. */
47982 /* And 4567, as then the vperm2[fi]128 doesn't change
47983 anything on the original 4567 second operand. */
47985 }
47986 else
47987 {
47988 /* The second shuffle for e.g. V4DFmode has
47989 4567 and ABCD operands.
47990 Ignore AB67, as 67 is already in the second lane
47991 of the first operand. */
47993 /* And 45CD, as 45 is in the first lane of the first
47994 operand. */
47996 /* And 0123, as then the vperm2[fi]128 doesn't change
47997 anything on the original 0123 first operand. */
47999 }
48002 {
48008 else
48010 }
48013 {
48017 }
48018 else
48022 {
48026 /* Found a usable second shuffle. dfirst will be
48027 vperm2f128 on d->op0 and d->op1. */
48039 /* And dsecond is some single insn shuffle, taking
48040 d->op0 and result of vperm2f128 (if perm < 16) or
48041 d->op1 and result of vperm2f128 (otherwise). */
48050 }
48052 /* For one operand, the only useful vperm2f128 permutation is 0x01
48053 aka lanes swap. */
48056 }
48059 }
48061 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48062 a two vector permutation using 2 intra-lane interleave insns
48063 and cross-lane shuffle for 32-byte vectors. */
48065 static bool
48067 {
48074 ;
48076 ;
48077 else
48092 {
48096 else
48102 else
48108 else
48114 else
48120 else
48126 else
48131 }
48135 }
48137 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48138 a single vector permutation using a single intra-lane vector
48139 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48140 the non-swapped and swapped vectors together. */
48142 static bool
48144 {
48152 || TARGET_AVX2
48161 {
48168 }
48203 }
48205 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48206 permutation using two vperm2f128, followed by a vshufpd insn blending
48207 the two vectors together. */
48209 static bool
48211 {
48254 }
48256 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48257 permutation with two pshufb insns and an ior. We should have already
48258 failed all two instruction sequences. */
48260 static bool
48262 {
48276 /* Generate two permutation masks. If the required element is within
48277 the given vector it is shuffled into the proper lane. If the required
48278 element is in the other vector, force a zero into the lane by setting
48279 bit 7 in the permutation mask. */
48282 {
48289 {
48292 }
48293 }
48317 }
48319 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48320 with two vpshufb insns, vpermq and vpor. We should have already failed
48321 all two or three instruction sequences. */
48323 static bool
48325 {
48340 /* Generate two permutation masks. If the required element is within
48341 the same lane, it is shuffled in. If the required element from the
48342 other lane, force a zero by setting bit 7 in the permutation mask.
48343 In the other mask the mask has non-negative elements if element
48344 is requested from the other lane, but also moved to the other lane,
48345 so that the result of vpshufb can have the two V2TImode halves
48346 swapped. */
48349 {
48354 {
48357 }
48358 }
48367 /* Swap the 128-byte lanes of h into hp. */
48371 const1_rtx));
48388 }
48390 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48391 and extract-odd permutations of two V32QImode and V16QImode operand
48392 with two vpshufb insns, vpor and vpermq. We should have already
48393 failed all two or three instruction sequences. */
48395 static bool
48397 {
48416 /* Generate two permutation masks. In the first permutation mask
48417 the first quarter will contain indexes for the first half
48418 of the op0, the second quarter will contain bit 7 set, third quarter
48419 will contain indexes for the second half of the op0 and the
48420 last quarter bit 7 set. In the second permutation mask
48421 the first quarter will contain bit 7 set, the second quarter
48422 indexes for the first half of the op1, the third quarter bit 7 set
48423 and last quarter indexes for the second half of the op1.
48424 I.e. the first mask e.g. for V32QImode extract even will be:
48425 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48426 (all values masked with 0xf except for -128) and second mask
48427 for extract even will be
48428 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48431 {
48437 {
48440 }
48441 }
48460 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48468 }
48470 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48471 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48472 with two "and" and "pack" or two "shift" and "pack" insns. We should
48473 have already failed all two instruction sequences. */
48475 static bool
48477 {
48481 machine_mode half_mode;
48490 {
48492 /* Required for "pack". */
48503 /* No check as all instructions are SSE2. */
48534 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48535 general shuffles. */
48537 }
48539 /* Check that permutation is even or odd. */
48554 {
48561 }
48562 else
48563 {
48570 }
48571 /* In AVX2 for 256 bit case we need to permute pack result. */
48573 {
48579 const0_rtx,
48580 const2_rtx,
48581 const1_rtx,
48584 }
48585 else
48589 }
48591 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48592 and extract-odd permutations. */
48594 static bool
48596 {
48600 {
48607 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48611 /* Now an unpck[lh]pd will produce the result required. */
48614 else
48620 {
48629 /* Shuffle within the 128-bit lanes to produce:
48630 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48634 /* Shuffle the lanes around to produce:
48635 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48639 /* Shuffle within the 128-bit lanes to produce:
48640 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48643 /* Shuffle within the 128-bit lanes to produce:
48644 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48647 /* Shuffle the lanes around to produce:
48648 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48651 }
48658 /* These are always directly implementable by expand_vec_perm_1. */
48666 else
48667 {
48670 /* We need 2*log2(N)-1 operations to achieve odd/even
48671 with interleave. */
48680 else
48683 }
48695 {
48700 else
48705 {
48710 }
48712 }
48720 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48724 /* Now an vpunpck[lh]qdq will produce the result required. */
48727 else
48734 {
48739 else
48744 {
48749 }
48751 }
48762 /* Shuffle the lanes around into
48763 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48771 /* Swap the 2nd and 3rd position in each lane into
48772 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48778 /* Now an vpunpck[lh]qdq will produce
48779 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48783 else
48792 }
48795 }
48797 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48798 extract-even and extract-odd permutations. */
48800 static bool
48802 {
48814 }
48816 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48817 permutations. We assume that expand_vec_perm_1 has already failed. */
48819 static bool
48821 {
48829 {
48832 /* These are special-cased in sse.md so that we can optionally
48833 use the vbroadcast instruction. They expand to two insns
48834 if the input happens to be in a register. */
48841 /* These are always implementable using standard shuffle patterns. */
48846 /* These can be implemented via interleave. We save one insn by
48847 stopping once we have promoted to V4SImode and then use pshufd. */
48850 do
48851 {
48852 rtx dest;
48858 {
48862 }
48869 }
48884 /* For AVX2 broadcasts of the first element vpbroadcast* or
48885 vpermq should be used by expand_vec_perm_1. */
48891 }
48892 }
48894 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48895 broadcast permutations. */
48897 static bool
48899 {
48911 }
48913 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
48914 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
48915 all the shorter instruction sequences. */
48917 static bool
48919 {
48935 /* Generate 4 permutation masks. If the required element is within
48936 the same lane, it is shuffled in. If the required element from the
48937 other lane, force a zero by setting bit 7 in the permutation mask.
48938 In the other mask the mask has non-negative elements if element
48939 is requested from the other lane, but also moved to the other lane,
48940 so that the result of vpshufb can have the two V2TImode halves
48941 swapped. */
48944 {
48949 }
48955 {
48963 }
48966 {
48968 {
48971 }
48978 }
48980 /* Swap the 128-byte lanes of h[X]. */
48982 {
48988 const1_rtx));
48990 }
48993 {
48995 {
48998 }
49004 }
49007 {
49009 {
49013 }
49016 }
49026 }
49028 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49029 With all of the interface bits taken care of, perform the expansion
49030 in D and return true on success. */
49032 static bool
49034 {
49035 /* Try a single instruction expansion. */
49039 /* Try sequences of two instructions. */
49062 /* Try sequences of three instructions. */
49079 /* Try sequences of four instructions. */
49087 /* ??? Look for narrow permutations whose element orderings would
49088 allow the promotion to a wider mode. */
49090 /* ??? Look for sequences of interleave or a wider permute that place
49091 the data into the correct lanes for a half-vector shuffle like
49092 pshuf[lh]w or vpermilps. */
49094 /* ??? Look for sequences of interleave that produce the desired results.
49095 The combinatorics of punpck[lh] get pretty ugly... */
49100 /* Even longer sequences. */
49105 }
49107 /* If a permutation only uses one operand, make it clear. Returns true
49108 if the permutation references both operands. */
49110 static bool
49112 {
49120 {
49126 {
49129 }
49130 /* The elements of PERM do not suggest that only the first operand
49131 is used, but both operands are identical. Allow easier matching
49132 of the permutation by folding the permutation into the single
49133 input vector. */
49134 /* FALLTHRU */
49145 }
49148 }
49150 bool
49152 {
49157 rtx sel;
49174 {
49179 }
49186 /* If the selector says both arguments are needed, but the operands are the
49187 same, the above tried to expand with one_operand_p and flattened selector.
49188 If that didn't work, retry without one_operand_p; we succeeded with that
49189 during testing. */
49191 {
49195 }
49198 }
49200 /* Implement targetm.vectorize.vec_perm_const_ok. */
49202 static bool
49205 {
49214 /* Given sufficient ISA support we can just return true here
49215 for selected vector modes. */
49217 {
49223 /* All implementable with a single vpermi2 insn. */
49228 /* All implementable with a single vpermi2 insn. */
49236 /* All implementable with a single vpermi2 insn. */
49241 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49246 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49253 /* All implementable with a single vpperm insn. */
49256 /* All implementable with 2 pshufb + 1 ior. */
49262 /* All implementable with shufpd or unpck[lh]pd. */
49266 }
49268 /* Extract the values from the vector CST into the permutation
49269 array in D. */
49272 {
49276 }
49278 /* For all elements from second vector, fold the elements to first. */
49283 /* Check whether the mask can be applied to the vector type. */
49286 /* Implementable with shufps or pshufd. */
49290 /* Otherwise we have to go through the motions and see if we can
49291 figure out how to generate the requested permutation. */
49302 }
49304 void
49306 {
49321 /* We'll either be able to implement the permutation directly... */
49325 /* ... or we use the special-case patterns. */
49327 }
49329 static void
49331 {
49346 {
49349 }
49351 /* Note that for AVX this isn't one instruction. */
49354 }
49357 /* Expand a vector operation CODE for a V*QImode in terms of the
49358 same operation on V*HImode. */
49360 void
49362 {
49364 machine_mode himode;
49374 {
49392 }
49396 {
49398 /* Unpack data such that we've got a source byte in each low byte of
49399 each word. We don't care what goes into the high byte of each word.
49400 Rather than trying to get zero in there, most convenient is to let
49401 it be a copy of the low byte. */
49406 /* FALLTHRU */
49418 /* FALLTHRU */
49428 }
49430 /* Perform the operation. */
49437 /* Merge the data back into the right place. */
49447 {
49448 /* For SSE2, we used an full interleave, so the desired
49449 results are in the even elements. */
49452 }
49453 else
49454 {
49455 /* For AVX, the interleave used above was not cross-lane. So the
49456 extraction is evens but with the second and third quarter swapped.
49457 Happily, that is even one insn shorter than even extraction. */
49460 }
49467 }
49469 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49470 if op is CONST_VECTOR with all odd elements equal to their
49471 preceding element. */
49473 static bool
49475 {
49485 }
49487 void
49490 {
49493 rtx x;
49501 /* We only play even/odd games with vectors of SImode. */
49504 /* If we're looking for the odd results, shift those members down to
49505 the even slots. For some cpus this is faster than a PSHUFD. */
49507 {
49508 /* For XOP use vpmacsdqh, but only for smult, as it is only
49509 signed. */
49511 {
49515 }
49526 }
49529 {
49532 else
49534 }
49536 {
49539 else
49541 }
49546 else
49547 {
49550 /* The easiest way to implement this without PMULDQ is to go through
49551 the motions as if we are performing a full 64-bit multiply. With
49552 the exception that we need to do less shuffling of the elements. */
49554 /* Compute the sign-extension, aka highparts, of the two operands. */
49560 /* Multiply LO(A) * HI(B), and vice-versa. */
49566 /* Multiply LO(A) * LO(B). */
49570 /* Combine and shift the highparts into place. */
49575 /* Combine high and low parts. */
49578 }
49580 }
49582 void
49585 {
49591 {
49596 {
49597 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49598 shuffle the elements once so that all elements are in the right
49599 place for immediate use: { A C B D }. */
49604 }
49605 else
49606 {
49607 /* Put the elements into place for the multiply. */
49611 }
49616 /* Shuffle the elements between the lanes. After this we
49617 have { A B E F | C D G H } for each operand. */
49627 /* Shuffle the elements within the lanes. After this we
49628 have { A A B B | C C D D } or { E E F F | G G H H }. */
49669 }
49670 }
49672 void
49674 {
49684 /* Move the results in element 2 down to element 1; we don't care
49685 what goes in elements 2 and 3. Then we can merge the parts
49686 back together with an interleave.
49688 Note that two other sequences were tried:
49689 (1) Use interleaves at the start instead of psrldq, which allows
49690 us to use a single shufps to merge things back at the end.
49691 (2) Use shufps here to combine the two vectors, then pshufd to
49692 put the elements in the correct order.
49693 In both cases the cost of the reformatting stall was too high
49694 and the overall sequence slower. */
49705 }
49707 void
49709 {
49720 {
49721 /* op1: A,B,C,D, op2: E,F,G,H */
49730 /* t1: B,A,D,C */
49737 /* t2: (B*E),(A*F),(D*G),(C*H) */
49740 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49743 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49746 /* Multiply lower parts and add all */
49753 }
49754 else
49755 {
49756 machine_mode nmode;
49760 {
49763 }
49765 {
49768 }
49770 {
49773 }
49774 else
49778 /* Multiply low parts. */
49782 /* Shift input vectors right 32 bits so we can multiply high parts. */
49787 /* Multiply high parts by low parts. */
49793 /* Combine and shift the highparts back. */
49797 /* Combine high and low parts. */
49799 }
49803 }
49805 /* Return 1 if control tansfer instruction INSN
49806 should be encoded with bnd prefix.
49807 If insn is NULL then return 1 when control
49808 transfer instructions should be prefixed with
49809 bnd by default for current function. */
49811 bool
49813 {
49814 /* For call insns check special flag. */
49816 {
49820 }
49822 /* All other insns are prefixed only if function is instrumented. */
49824 }
49826 /* Calculate integer abs() using only SSE2 instructions. */
49828 void
49830 {
49835 {
49836 /* For 32-bit signed integer X, the best way to calculate the absolute
49837 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
49849 /* For 16-bit signed integer X, the best way to calculate the absolute
49850 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
49858 /* For 8-bit signed integer X, the best way to calculate the absolute
49859 value of X is min ((unsigned char) X, (unsigned char) (-X)),
49860 as SSE2 provides the PMINUB insn. */
49870 }
49874 }
49876 /* Expand an insert into a vector register through pinsr insn.
49877 Return true if successful. */
49879 bool
49881 {
49889 {
49892 }
49898 {
49903 {
49910 {
49942 }
49956 }
49960 }
49961 }
49962 \f
49963 /* This function returns the calling abi specific va_list type node.
49964 It returns the FNDECL specific va_list type. */
49966 static tree
49968 {
49975 else
49977 }
49979 /* Returns the canonical va_list type specified by TYPE. If there
49980 is no valid TYPE provided, it return NULL_TREE. */
49982 static tree
49984 {
49987 /* Resolve references and pointers to va_list type. */
49996 {
50001 {
50002 /* If va_list is an array type, the argument may have decayed
50003 to a pointer type, e.g. by being passed to another function.
50004 In that case, unwrap both types so that we can compare the
50005 underlying records. */
50008 {
50011 }
50012 }
50019 {
50020 /* If va_list is an array type, the argument may have decayed
50021 to a pointer type, e.g. by being passed to another function.
50022 In that case, unwrap both types so that we can compare the
50023 underlying records. */
50026 {
50029 }
50030 }
50037 {
50038 /* If va_list is an array type, the argument may have decayed
50039 to a pointer type, e.g. by being passed to another function.
50040 In that case, unwrap both types so that we can compare the
50041 underlying records. */
50044 {
50047 }
50048 }
50052 }
50054 }
50056 /* Iterate through the target-specific builtin types for va_list.
50057 IDX denotes the iterator, *PTREE is set to the result type of
50058 the va_list builtin, and *PNAME to its internal type.
50059 Returns zero if there is no element for this index, otherwise
50060 IDX should be increased upon the next call.
50061 Note, do not iterate a base builtin's name like __builtin_va_list.
50062 Used from c_common_nodes_and_builtins. */
50064 static int
50066 {
50068 {
50070 {
50083 }
50084 }
50087 }
50089 #undef TARGET_SCHED_DISPATCH
50090 #define TARGET_SCHED_DISPATCH has_dispatch
50091 #undef TARGET_SCHED_DISPATCH_DO
50092 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50093 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50094 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50095 #undef TARGET_SCHED_REORDER
50096 #define TARGET_SCHED_REORDER ix86_sched_reorder
50097 #undef TARGET_SCHED_ADJUST_PRIORITY
50098 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50099 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50100 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50101 ix86_dependencies_evaluation_hook
50103 /* The size of the dispatch window is the total number of bytes of
50104 object code allowed in a window. */
50105 #define DISPATCH_WINDOW_SIZE 16
50107 /* Number of dispatch windows considered for scheduling. */
50108 #define MAX_DISPATCH_WINDOWS 3
50110 /* Maximum number of instructions in a window. */
50111 #define MAX_INSN 4
50113 /* Maximum number of immediate operands in a window. */
50114 #define MAX_IMM 4
50116 /* Maximum number of immediate bits allowed in a window. */
50117 #define MAX_IMM_SIZE 128
50119 /* Maximum number of 32 bit immediates allowed in a window. */
50120 #define MAX_IMM_32 4
50122 /* Maximum number of 64 bit immediates allowed in a window. */
50123 #define MAX_IMM_64 2
50125 /* Maximum total of loads or prefetches allowed in a window. */
50126 #define MAX_LOAD 2
50128 /* Maximum total of stores allowed in a window. */
50129 #define MAX_STORE 1
50131 #undef BIG
50132 #define BIG 100
50135 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50138 disp_load,
50139 disp_store,
50140 disp_load_store,
50141 disp_prefetch,
50142 disp_imm,
50143 disp_imm_32,
50144 disp_imm_64,
50145 disp_branch,
50146 disp_cmp,
50147 disp_jcc,
50148 disp_last
50149 };
50151 /* Number of allowable groups in a dispatch window. It is an array
50152 indexed by dispatch_group enum. 100 is used as a big number,
50153 because the number of these kind of operations does not have any
50154 effect in dispatch window, but we need them for other reasons in
50155 the table. */
50158 };
50164 };
50166 /* Instruction path. */
50172 last_path
50173 };
50175 /* sched_insn_info defines a window to the instructions scheduled in
50176 the basic block. It contains a pointer to the insn_info table and
50177 the instruction scheduled.
50179 Windows are allocated for each basic block and are linked
50180 together. */
50182 rtx insn;
50189 /* Linked list of dispatch windows. This is a two way list of
50190 dispatch windows of a basic block. It contains information about
50191 the number of uops in the window and the total number of
50192 instructions and of bytes in the object code for this dispatch
50193 window. */
50211 /* Immediate valuse used in an insn. */
50213 {
50222 /* Get dispatch group of insn. */
50224 static enum dispatch_group
50226 {
50242 }
50244 /* Return true if insn is a compare instruction. */
50246 static bool
50248 {
50256 }
50258 /* Return true if a dispatch violation encountered. */
50260 static bool
50262 {
50266 }
50268 /* Return true if insn is a branch instruction. */
50270 static bool
50272 {
50274 }
50276 /* Return true if insn is a prefetch instruction. */
50278 static bool
50280 {
50282 }
50284 /* This function initializes a dispatch window and the list container holding a
50285 pointer to the window. */
50287 static void
50289 {
50295 else
50313 {
50319 }
50321 }
50323 /* This function allocates and initializes a dispatch window and the
50324 list container holding a pointer to the window. */
50328 {
50333 }
50335 /* This routine initializes the dispatch scheduling information. It
50336 initiates building dispatch scheduler tables and constructs the
50337 first dispatch window. */
50339 static void
50341 {
50342 /* Allocate a dispatch list and a window. */
50347 }
50349 /* This function returns true if a branch is detected. End of a basic block
50350 does not have to be a branch, but here we assume only branches end a
50351 window. */
50353 static bool
50355 {
50357 }
50359 /* This function is called when the end of a window processing is reached. */
50361 static void
50363 {
50366 {
50371 }
50373 }
50375 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50376 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50377 for 48 bytes of instructions. Note that these windows are not dispatch
50378 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50382 {
50384 {
50389 }
50395 }
50397 /* Compute number of immediate operands of an instruction. */
50399 static void
50401 {
50408 {
50415 else
50426 {
50429 }
50434 }
50435 }
50437 /* Return total size of immediate operands of an instruction along with number
50438 of corresponding immediate-operands. It initializes its parameters to zero
50439 befor calling FIND_CONSTANT.
50440 INSN is the input instruction. IMM is the total of immediates.
50441 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50442 bit immediates. */
50444 static int
50446 {
50454 }
50456 /* This function indicates if an operand of an instruction is an
50457 immediate. */
50459 static bool
50461 {
50470 }
50472 /* Return single or double path for instructions. */
50474 static enum insn_path
50476 {
50486 }
50488 /* Return insn dispatch group. */
50490 static enum dispatch_group
50492 {
50510 }
50512 /* Count number of GROUP restricted instructions in a dispatch
50513 window WINDOW_LIST. */
50515 static int
50517 {
50528 {
50547 }
50560 }
50562 /* This function returns true if insn satisfies dispatch rules on the
50563 last window scheduled. */
50565 static bool
50567 {
50575 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50576 instructions should be given the lowest priority in the
50577 scheduling process in Haifa scheduler to make sure they will be
50578 scheduled in the same dispatch window as the reference to them. */
50582 /* Check nonrestricted. */
50586 /* Get last dispatch window. */
50591 {
50596 /* Window 1 is full. Go for next window. */
50598 }
50605 /* See if it fits in the first window. */
50607 {
50608 /* The first widow should have only single and double path
50609 uops. */
50615 }
50617 }
50619 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50620 dispatch window WINDOW_LIST. */
50622 static void
50624 {
50642 /* Initialize window with new instruction. */
50663 {
50666 }
50667 }
50669 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50670 If the total bytes of instructions or the number of instructions in
50671 the window exceed allowable, it allocates a new window. */
50673 static void
50675 {
50698 /* Get the last dispatch window. */
50706 else
50709 /* If current window is full, get a new window.
50710 Window number zero is full, if MAX_INSN uops are scheduled in it.
50711 Window number one is full, if window zero's bytes plus window
50712 one's bytes is 32, or if the bytes of the new instruction added
50713 to the total makes it greater than 48, or it has already MAX_INSN
50714 instructions in it. */
50723 {
50726 }
50729 {
50733 {
50736 }
50737 }
50739 {
50744 {
50747 }
50750 }
50751 else
50755 {
50756 /* End of basic block is reached do end-basic-block process. */
50759 }
50760 }
50762 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50764 DEBUG_FUNCTION static void
50766 {
50772 else
50786 {
50789 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50795 }
50796 }
50798 /* Print to stdout a dispatch window. */
50800 DEBUG_FUNCTION void
50802 {
50804 }
50806 /* Print INSN dispatch information to FILE. */
50808 DEBUG_FUNCTION static void
50810 {
50833 }
50835 /* Print to STDERR the status of the ready list with respect to
50836 dispatch windows. */
50838 DEBUG_FUNCTION void
50840 {
50848 }
50850 /* This routine is the driver of the dispatch scheduler. */
50852 static void
50854 {
50859 }
50861 /* Return TRUE if Dispatch Scheduling is supported. */
50863 static bool
50865 {
50869 {
50885 }
50888 }
50890 /* Implementation of reassociation_width target hook used by
50891 reassoc phase to identify parallelism level in reassociated
50892 tree. Statements tree_code is passed in OPC. Arguments type
50893 is passed in MODE.
50895 Currently parallel reassociation is enabled for Atom
50896 processors only and we set reassociation width to be 2
50897 because Atom may issue up to 2 instructions per cycle.
50899 Return value should be fixed if parallel reassociation is
50900 enabled for other processors. */
50902 static int
50904 {
50907 /* Vector part. */
50909 {
50912 else
50914 }
50916 /* Scalar part. */
50923 }
50925 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
50926 place emms and femms instructions. */
50928 static machine_mode
50930 {
50935 {
50954 else
50966 /* FALLTHRU */
50970 }
50971 }
50973 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
50974 vectors. If AVX512F is enabled then try vectorizing with 512bit,
50975 256bit and 128bit vectors. */
50977 static unsigned int
50979 {
50982 }
50984 \f
50986 /* Return class of registers which could be used for pseudo of MODE
50987 and of class RCLASS for spilling instead of memory. Return NO_REGS
50988 if it is not possible or non-profitable. */
50989 static reg_class_t
50991 {
50997 }
50999 /* Implement targetm.vectorize.init_cost. */
51003 {
51007 }
51009 /* Implement targetm.vectorize.add_stmt_cost. */
51011 static unsigned
51015 {
51022 /* Statements in an inner loop relative to the loop being
51023 vectorized are weighted more heavily. The value here is
51024 arbitrary and could potentially be improved with analysis. */
51030 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51031 for Silvermont as it has out of order integer pipeline and can execute
51032 2 scalar instruction per tick, but has in order SIMD pipeline. */
51035 {
51039 }
51044 }
51046 /* Implement targetm.vectorize.finish_cost. */
51048 static void
51051 {
51056 }
51058 /* Implement targetm.vectorize.destroy_cost_data. */
51060 static void
51062 {
51064 }
51066 /* Validate target specific memory model bits in VAL. */
51068 static unsigned HOST_WIDE_INT
51070 {
51077 {
51081 }
51084 {
51088 }
51090 {
51094 }
51096 }
51098 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51099 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51100 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51101 or number of vecsize_mangle variants that should be emitted. */
51103 static int
51107 {
51114 {
51118 }
51123 {
51130 /* case SCmode: */
51131 /* case DCmode: */
51137 }
51139 tree t;
51143 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51145 {
51152 /* case SCmode: */
51153 /* case DCmode: */
51159 }
51162 {
51163 /* Parse here processor clause. If not present, default to 'b'. */
51165 }
51167 {
51168 /* If the function isn't exported, we can pick up just one ISA
51169 for the clones. */
51174 else
51177 }
51178 else
51179 {
51182 }
51184 {
51197 }
51199 {
51202 else
51207 }
51209 }
51211 /* Add target attribute to SIMD clone NODE if needed. */
51213 static void
51215 {
51219 {
51234 }
51244 }
51246 /* If SIMD clone NODE can't be used in a vectorized loop
51247 in current function, return -1, otherwise return a badness of using it
51248 (0 if it is most desirable from vecsize_mangle point of view, 1
51249 slightly less desirable, etc.). */
51251 static int
51253 {
51255 {
51273 }
51274 }
51276 /* This function adjusts the unroll factor based on
51277 the hardware capabilities. For ex, bdver3 has
51278 a loop buffer which makes unrolling of smaller
51279 loops less important. This function decides the
51280 unroll factor using number of memory references
51281 (value 32 is used) as a heuristic. */
51283 static unsigned
51285 {
51294 /* Count the number of memory references within the loop body.
51295 This value determines the unrolling factor for bdver3 and bdver4
51296 architectures. */
51305 {
51310 else
51312 }
51319 }
51322 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51324 static bool
51326 {
51327 /* For x87 floating point with standard excess precision handling,
51328 there is no adddf3 pattern (since x87 floating point only has
51329 XFmode operations) so the default hook implementation gets this
51330 wrong. */
51332 }
51334 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51336 static void
51338 {
51343 {
51358 hold_fnclex);
51371 }
51373 {
51382 mxcsr_orig_var,
51392 ldmxcsr_hold_call);
51395 else
51400 ldmxcsr_clear_call);
51401 else
51405 stxmcsr_update_call);
51407 {
51413 exceptions_assign);
51414 }
51415 else
51420 ldmxcsr_update_call);
51421 }
51422 tree atomic_feraiseexcept
51427 atomic_feraiseexcept_call);
51428 }
51430 /* Return mode to be used for bounds or VOIDmode
51431 if bounds are not supported. */
51433 static enum machine_mode
51435 {
51436 /* Do not support pointer checker if MPX
51437 is not enabled. */
51439 {
51444 }
51447 }
51449 /* Return constant used to statically initialize constant bounds.
51451 This function is used to create special bound values. For now
51452 only INIT bounds and NONE bounds are expected. More special
51453 values may be added later. */
51455 static tree
51457 {
51463 /* This function is supposed to be used to create INIT and
51464 NONE bounds only. */
51469 }
51471 /* Generate a list of statements STMTS to initialize pointer bounds
51472 variable VAR with bounds LB and UB. Return the number of generated
51473 statements. */
51475 static int
51477 {
51495 }
51497 /* Initialize the GCC target structure. */
51498 #undef TARGET_RETURN_IN_MEMORY
51499 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51501 #undef TARGET_LEGITIMIZE_ADDRESS
51502 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51504 #undef TARGET_ATTRIBUTE_TABLE
51505 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51506 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51507 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51508 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51509 # undef TARGET_MERGE_DECL_ATTRIBUTES
51510 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51511 #endif
51513 #undef TARGET_COMP_TYPE_ATTRIBUTES
51514 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51516 #undef TARGET_INIT_BUILTINS
51517 #define TARGET_INIT_BUILTINS ix86_init_builtins
51518 #undef TARGET_BUILTIN_DECL
51519 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51520 #undef TARGET_EXPAND_BUILTIN
51521 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51523 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51524 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51525 ix86_builtin_vectorized_function
51527 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51528 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51530 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51531 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51533 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51534 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51536 #undef TARGET_BUILTIN_RECIPROCAL
51537 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51539 #undef TARGET_ASM_FUNCTION_EPILOGUE
51540 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51542 #undef TARGET_ENCODE_SECTION_INFO
51543 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51544 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51545 #else
51546 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51547 #endif
51549 #undef TARGET_ASM_OPEN_PAREN
51551 #undef TARGET_ASM_CLOSE_PAREN
51554 #undef TARGET_ASM_BYTE_OP
51555 #define TARGET_ASM_BYTE_OP ASM_BYTE
51557 #undef TARGET_ASM_ALIGNED_HI_OP
51558 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51559 #undef TARGET_ASM_ALIGNED_SI_OP
51560 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51561 #ifdef ASM_QUAD
51562 #undef TARGET_ASM_ALIGNED_DI_OP
51563 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51564 #endif
51566 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51567 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51569 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51570 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51572 #undef TARGET_ASM_UNALIGNED_HI_OP
51573 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51574 #undef TARGET_ASM_UNALIGNED_SI_OP
51575 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51576 #undef TARGET_ASM_UNALIGNED_DI_OP
51577 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51579 #undef TARGET_PRINT_OPERAND
51580 #define TARGET_PRINT_OPERAND ix86_print_operand
51581 #undef TARGET_PRINT_OPERAND_ADDRESS
51582 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51583 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51584 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51585 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51586 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51588 #undef TARGET_SCHED_INIT_GLOBAL
51589 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51590 #undef TARGET_SCHED_ADJUST_COST
51591 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51592 #undef TARGET_SCHED_ISSUE_RATE
51593 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51594 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51595 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51596 ia32_multipass_dfa_lookahead
51597 #undef TARGET_SCHED_MACRO_FUSION_P
51598 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51599 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51600 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51602 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51603 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51605 #undef TARGET_MEMMODEL_CHECK
51606 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51608 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51609 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51611 #ifdef HAVE_AS_TLS
51612 #undef TARGET_HAVE_TLS
51613 #define TARGET_HAVE_TLS true
51614 #endif
51615 #undef TARGET_CANNOT_FORCE_CONST_MEM
51616 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51617 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51618 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51620 #undef TARGET_DELEGITIMIZE_ADDRESS
51621 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51623 #undef TARGET_MS_BITFIELD_LAYOUT_P
51624 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51626 #if TARGET_MACHO
51627 #undef TARGET_BINDS_LOCAL_P
51628 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51629 #endif
51630 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51631 #undef TARGET_BINDS_LOCAL_P
51632 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51633 #endif
51635 #undef TARGET_ASM_OUTPUT_MI_THUNK
51636 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51637 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51638 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51640 #undef TARGET_ASM_FILE_START
51641 #define TARGET_ASM_FILE_START x86_file_start
51643 #undef TARGET_OPTION_OVERRIDE
51644 #define TARGET_OPTION_OVERRIDE ix86_option_override
51646 #undef TARGET_REGISTER_MOVE_COST
51647 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51648 #undef TARGET_MEMORY_MOVE_COST
51649 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51650 #undef TARGET_RTX_COSTS
51651 #define TARGET_RTX_COSTS ix86_rtx_costs
51652 #undef TARGET_ADDRESS_COST
51653 #define TARGET_ADDRESS_COST ix86_address_cost
51655 #undef TARGET_FIXED_CONDITION_CODE_REGS
51656 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51657 #undef TARGET_CC_MODES_COMPATIBLE
51658 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51660 #undef TARGET_MACHINE_DEPENDENT_REORG
51661 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51663 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51664 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51666 #undef TARGET_BUILD_BUILTIN_VA_LIST
51667 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51669 #undef TARGET_FOLD_BUILTIN
51670 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51672 #undef TARGET_COMPARE_VERSION_PRIORITY
51673 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51675 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51676 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51677 ix86_generate_version_dispatcher_body
51679 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51680 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51681 ix86_get_function_versions_dispatcher
51683 #undef TARGET_ENUM_VA_LIST_P
51684 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51686 #undef TARGET_FN_ABI_VA_LIST
51687 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51689 #undef TARGET_CANONICAL_VA_LIST_TYPE
51690 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51692 #undef TARGET_EXPAND_BUILTIN_VA_START
51693 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51695 #undef TARGET_MD_ASM_CLOBBERS
51696 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51698 #undef TARGET_PROMOTE_PROTOTYPES
51699 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51700 #undef TARGET_SETUP_INCOMING_VARARGS
51701 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51702 #undef TARGET_MUST_PASS_IN_STACK
51703 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51704 #undef TARGET_FUNCTION_ARG_ADVANCE
51705 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51706 #undef TARGET_FUNCTION_ARG
51707 #define TARGET_FUNCTION_ARG ix86_function_arg
51708 #undef TARGET_INIT_PIC_REG
51709 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51710 #undef TARGET_USE_PSEUDO_PIC_REG
51711 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51712 #undef TARGET_FUNCTION_ARG_BOUNDARY
51713 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51714 #undef TARGET_PASS_BY_REFERENCE
51715 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51716 #undef TARGET_INTERNAL_ARG_POINTER
51717 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51718 #undef TARGET_UPDATE_STACK_BOUNDARY
51719 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51720 #undef TARGET_GET_DRAP_RTX
51721 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51722 #undef TARGET_STRICT_ARGUMENT_NAMING
51723 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51724 #undef TARGET_STATIC_CHAIN
51725 #define TARGET_STATIC_CHAIN ix86_static_chain
51726 #undef TARGET_TRAMPOLINE_INIT
51727 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51728 #undef TARGET_RETURN_POPS_ARGS
51729 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51731 #undef TARGET_LEGITIMATE_COMBINED_INSN
51732 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51734 #undef TARGET_ASAN_SHADOW_OFFSET
51735 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
51737 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
51738 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
51740 #undef TARGET_SCALAR_MODE_SUPPORTED_P
51741 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
51743 #undef TARGET_VECTOR_MODE_SUPPORTED_P
51744 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
51746 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
51747 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
51748 ix86_libgcc_floating_mode_supported_p
51750 #undef TARGET_C_MODE_FOR_SUFFIX
51751 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
51753 #ifdef HAVE_AS_TLS
51754 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
51755 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
51756 #endif
51758 #ifdef SUBTARGET_INSERT_ATTRIBUTES
51759 #undef TARGET_INSERT_ATTRIBUTES
51760 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
51761 #endif
51763 #undef TARGET_MANGLE_TYPE
51764 #define TARGET_MANGLE_TYPE ix86_mangle_type
51766 #if !TARGET_MACHO
51767 #undef TARGET_STACK_PROTECT_FAIL
51768 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
51769 #endif
51771 #undef TARGET_FUNCTION_VALUE
51772 #define TARGET_FUNCTION_VALUE ix86_function_value
51774 #undef TARGET_FUNCTION_VALUE_REGNO_P
51775 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
51777 #undef TARGET_PROMOTE_FUNCTION_MODE
51778 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
51780 #undef TARGET_MEMBER_TYPE_FORCES_BLK
51781 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
51783 #undef TARGET_INSTANTIATE_DECLS
51784 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
51786 #undef TARGET_SECONDARY_RELOAD
51787 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
51789 #undef TARGET_CLASS_MAX_NREGS
51790 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
51792 #undef TARGET_PREFERRED_RELOAD_CLASS
51793 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
51794 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
51795 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
51796 #undef TARGET_CLASS_LIKELY_SPILLED_P
51797 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
51799 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
51800 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
51801 ix86_builtin_vectorization_cost
51802 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
51803 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
51804 ix86_vectorize_vec_perm_const_ok
51805 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
51806 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
51807 ix86_preferred_simd_mode
51808 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
51809 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
51810 ix86_autovectorize_vector_sizes
51811 #undef TARGET_VECTORIZE_INIT_COST
51812 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
51813 #undef TARGET_VECTORIZE_ADD_STMT_COST
51814 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
51815 #undef TARGET_VECTORIZE_FINISH_COST
51816 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
51817 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
51818 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
51820 #undef TARGET_SET_CURRENT_FUNCTION
51821 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
51823 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
51824 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
51826 #undef TARGET_OPTION_SAVE
51827 #define TARGET_OPTION_SAVE ix86_function_specific_save
51829 #undef TARGET_OPTION_RESTORE
51830 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
51832 #undef TARGET_OPTION_PRINT
51833 #define TARGET_OPTION_PRINT ix86_function_specific_print
51835 #undef TARGET_OPTION_FUNCTION_VERSIONS
51836 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
51838 #undef TARGET_CAN_INLINE_P
51839 #define TARGET_CAN_INLINE_P ix86_can_inline_p
51841 #undef TARGET_EXPAND_TO_RTL_HOOK
51842 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
51844 #undef TARGET_LEGITIMATE_ADDRESS_P
51845 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
51847 #undef TARGET_LRA_P
51848 #define TARGET_LRA_P hook_bool_void_true
51850 #undef TARGET_REGISTER_PRIORITY
51851 #define TARGET_REGISTER_PRIORITY ix86_register_priority
51853 #undef TARGET_REGISTER_USAGE_LEVELING_P
51854 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
51856 #undef TARGET_LEGITIMATE_CONSTANT_P
51857 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
51859 #undef TARGET_FRAME_POINTER_REQUIRED
51860 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
51862 #undef TARGET_CAN_ELIMINATE
51863 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
51865 #undef TARGET_EXTRA_LIVE_ON_ENTRY
51866 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
51868 #undef TARGET_ASM_CODE_END
51869 #define TARGET_ASM_CODE_END ix86_code_end
51871 #undef TARGET_CONDITIONAL_REGISTER_USAGE
51872 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
51874 #if TARGET_MACHO
51875 #undef TARGET_INIT_LIBFUNCS
51876 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
51877 #endif
51879 #undef TARGET_LOOP_UNROLL_ADJUST
51880 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
51882 #undef TARGET_SPILL_CLASS
51883 #define TARGET_SPILL_CLASS ix86_spill_class
51885 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
51886 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
51887 ix86_simd_clone_compute_vecsize_and_simdlen
51889 #undef TARGET_SIMD_CLONE_ADJUST
51890 #define TARGET_SIMD_CLONE_ADJUST \
51891 ix86_simd_clone_adjust
51893 #undef TARGET_SIMD_CLONE_USABLE
51894 #define TARGET_SIMD_CLONE_USABLE \
51895 ix86_simd_clone_usable
51897 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
51898 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
51899 ix86_float_exceptions_rounding_supported_p
51901 #undef TARGET_MODE_EMIT
51902 #define TARGET_MODE_EMIT ix86_emit_mode_set
51904 #undef TARGET_MODE_NEEDED
51905 #define TARGET_MODE_NEEDED ix86_mode_needed
51907 #undef TARGET_MODE_AFTER
51908 #define TARGET_MODE_AFTER ix86_mode_after
51910 #undef TARGET_MODE_ENTRY
51911 #define TARGET_MODE_ENTRY ix86_mode_entry
51913 #undef TARGET_MODE_EXIT
51914 #define TARGET_MODE_EXIT ix86_mode_exit
51916 #undef TARGET_MODE_PRIORITY
51917 #define TARGET_MODE_PRIORITY ix86_mode_priority
51919 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
51920 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
51922 #undef TARGET_LOAD_BOUNDS_FOR_ARG
51923 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
51925 #undef TARGET_STORE_BOUNDS_FOR_ARG
51926 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
51928 #undef TARGET_LOAD_RETURNED_BOUNDS
51929 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
51931 #undef TARGET_STORE_RETURNED_BOUNDS
51932 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
51934 #undef TARGET_CHKP_BOUND_MODE
51935 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
51937 #undef TARGET_BUILTIN_CHKP_FUNCTION
51938 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
51940 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
51941 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
51943 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
51944 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
51946 #undef TARGET_CHKP_INITIALIZE_BOUNDS
51947 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
51949 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
51950 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
51952 #undef TARGET_OFFLOAD_OPTIONS
51953 #define TARGET_OFFLOAD_OPTIONS \
51954 ix86_offload_options
51957 \f