| blob | b86a4777621cccca370f449a580a41a0609d784f |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_LDGP1 1)
30 (UNSPEC_INSXH 2)
31 (UNSPEC_MSKXH 3)
32 (UNSPEC_CVTQL 4)
33 (UNSPEC_CVTLQ 5)
34 (UNSPEC_UMK_LAUM 6)
35 (UNSPEC_UMK_LALM 7)
36 (UNSPEC_UMK_LAL 8)
37 (UNSPEC_UMK_LOAD_CIW 9)
38 (UNSPEC_LDGP2 10)
39 (UNSPEC_LITERAL 11)
40 (UNSPEC_LITUSE 12)
41 (UNSPEC_SIBCALL 13)
42 (UNSPEC_SYMBOL 14)
44 ;; TLS Support
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
47 (UNSPEC_TLSGD 17)
48 (UNSPEC_TLSLDM 18)
49 (UNSPEC_DTPREL 19)
50 (UNSPEC_TPREL 20)
51 (UNSPEC_TP 21)
53 ;; Builtins
54 (UNSPEC_CMPBGE 22)
55 (UNSPEC_ZAP 23)
56 (UNSPEC_AMASK 24)
57 (UNSPEC_IMPLVER 25)
58 (UNSPEC_PERR 26)
59 (UNSPEC_COPYSIGN 27)
61 ;; Atomic operations
62 (UNSPEC_MB 28)
63 (UNSPEC_ATOMIC 31)
64 (UNSPEC_CMPXCHG 32)
65 (UNSPEC_XCHG 33)
66 ])
68 ;; UNSPEC_VOLATILE:
70 (define_constants
71 [(UNSPECV_IMB 0)
72 (UNSPECV_BLOCKAGE 1)
73 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
74 (UNSPECV_LONGJMP 3) ; builtin_longjmp
75 (UNSPECV_TRAPB 4)
76 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
77 (UNSPECV_REALIGN 6)
78 (UNSPECV_EHR 7) ; exception_receiver
79 (UNSPECV_MCOUNT 8)
80 (UNSPECV_FORCE_MOV 9)
81 (UNSPECV_LDGP1 10)
82 (UNSPECV_PLDGP2 11) ; prologue ldgp
83 (UNSPECV_SET_TP 12)
84 (UNSPECV_RPCC 13)
85 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
86 (UNSPECV_LL 15) ; load-locked
87 (UNSPECV_SC 16) ; store-conditional
88 ])
90 ;; Where necessary, the suffixes _le and _be are used to distinguish between
91 ;; little-endian and big-endian patterns.
92 ;;
93 ;; Note that the Unicos/Mk assembler does not support the following
94 ;; opcodes: mov, fmov, nop, fnop, unop.
95 \f
96 ;; Processor type -- this attribute must exactly match the processor_type
97 ;; enumeration in alpha.h.
99 (define_attr "tune" "ev4,ev5,ev6"
100 (const (symbol_ref "alpha_tune")))
102 ;; Define an insn type attribute. This is used in function unit delay
103 ;; computations, among other purposes. For the most part, we use the names
104 ;; defined in the EV4 documentation, but add a few that we have to know about
105 ;; separately.
107 (define_attr "type"
108 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
109 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
110 multi,none"
111 (const_string "iadd"))
113 ;; Describe a user's asm statement.
114 (define_asm_attributes
115 [(set_attr "type" "multi")])
117 ;; Define the operand size an insn operates on. Used primarily by mul
118 ;; and div operations that have size dependent timings.
120 (define_attr "opsize" "si,di,udi"
121 (const_string "di"))
123 ;; The TRAP attribute marks instructions that may generate traps
124 ;; (which are imprecise and may need a trapb if software completion
125 ;; is desired).
127 (define_attr "trap" "no,yes"
128 (const_string "no"))
130 ;; The ROUND_SUFFIX attribute marks which instructions require a
131 ;; rounding-mode suffix. The value NONE indicates no suffix,
132 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
134 (define_attr "round_suffix" "none,normal,c"
135 (const_string "none"))
137 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
138 ;; NONE no suffix
139 ;; SU accepts only /su (cmpt et al)
140 ;; SUI accepts only /sui (cvtqt and cvtqs)
141 ;; V_SV accepts /v and /sv (cvtql only)
142 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
143 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
144 ;;
145 ;; The actual suffix emitted is controlled by alpha_fptm.
147 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
148 (const_string "none"))
150 ;; The length of an instruction sequence in bytes.
152 (define_attr "length" ""
153 (const_int 4))
155 ;; The USEGP attribute marks instructions that have relocations that use
156 ;; the GP.
158 (define_attr "usegp" "no,yes"
159 (cond [(eq_attr "type" "ldsym,jsr")
160 (const_string "yes")
161 (eq_attr "type" "ild,fld,ist,fst")
162 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
163 ]
164 (const_string "no")))
166 ;; The CANNOT_COPY attribute marks instructions with relocations that
167 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
168 ;; since they have to stay in 1-1 correspondence with one another. This
169 ;; also includes jsr insns, since they must stay in correspondence with
170 ;; the immediately following gpdisp instructions.
172 (define_attr "cannot_copy" "false,true"
173 (const_string "false"))
174 \f
175 ;; Include scheduling descriptions.
177 (include "ev4.md")
178 (include "ev5.md")
179 (include "ev6.md")
181 \f
182 ;; Operand and operator predicates and constraints
184 (include "predicates.md")
185 (include "constraints.md")
187 \f
188 ;; First define the arithmetic insns. Note that the 32-bit forms also
189 ;; sign-extend.
191 ;; Handle 32-64 bit extension from memory to a floating point register
192 ;; specially, since this occurs frequently in int->double conversions.
193 ;;
194 ;; Note that while we must retain the =f case in the insn for reload's
195 ;; benefit, it should be eliminated after reload, so we should never emit
196 ;; code for that case. But we don't reject the possibility.
198 (define_expand "extendsidi2"
199 [(set (match_operand:DI 0 "register_operand" "")
200 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
201 ""
202 "")
204 (define_insn "*cvtlq"
205 [(set (match_operand:DI 0 "register_operand" "=f")
206 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
207 UNSPEC_CVTLQ))]
208 ""
209 "cvtlq %1,%0"
210 [(set_attr "type" "fadd")])
212 (define_insn "*extendsidi2_1"
213 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
214 (sign_extend:DI
215 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
216 ""
217 "@
218 addl $31,%1,%0
219 ldl %0,%1
220 lds %0,%1\;cvtlq %0,%0"
221 [(set_attr "type" "iadd,ild,fld")
222 (set_attr "length" "*,*,8")])
224 (define_split
225 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
226 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
227 "reload_completed"
228 [(set (match_dup 2) (match_dup 1))
229 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
230 {
231 operands[1] = adjust_address (operands[1], SFmode, 0);
232 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
233 })
235 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
236 ;; reload when converting fp->int.
238 (define_peephole2
239 [(set (match_operand:SI 0 "hard_int_register_operand" "")
240 (match_operand:SI 1 "memory_operand" ""))
241 (set (match_operand:DI 2 "hard_int_register_operand" "")
242 (sign_extend:DI (match_dup 0)))]
243 "true_regnum (operands[0]) == true_regnum (operands[2])
244 || peep2_reg_dead_p (2, operands[0])"
245 [(set (match_dup 2)
246 (sign_extend:DI (match_dup 1)))]
247 "")
249 ;; Don't say we have addsi3 if optimizing. This generates better code. We
250 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
251 (define_expand "addsi3"
252 [(set (match_operand:SI 0 "register_operand" "")
253 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
254 (match_operand:SI 2 "add_operand" "")))]
255 "! optimize"
256 "")
258 (define_insn "*addsi_internal"
259 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
260 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
261 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
262 ""
263 "@
264 addl %r1,%2,%0
265 subl %r1,%n2,%0
266 lda %0,%2(%r1)
267 ldah %0,%h2(%r1)")
269 (define_split
270 [(set (match_operand:SI 0 "register_operand" "")
271 (plus:SI (match_operand:SI 1 "register_operand" "")
272 (match_operand:SI 2 "const_int_operand" "")))]
273 "! add_operand (operands[2], SImode)"
274 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
275 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
276 {
277 HOST_WIDE_INT val = INTVAL (operands[2]);
278 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
279 HOST_WIDE_INT rest = val - low;
281 operands[3] = GEN_INT (rest);
282 operands[4] = GEN_INT (low);
283 })
285 (define_insn "*addsi_se"
286 [(set (match_operand:DI 0 "register_operand" "=r,r")
287 (sign_extend:DI
288 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
289 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
290 ""
291 "@
292 addl %r1,%2,%0
293 subl %r1,%n2,%0")
295 (define_insn "*addsi_se2"
296 [(set (match_operand:DI 0 "register_operand" "=r,r")
297 (sign_extend:DI
298 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
299 (match_operand:DI 2 "sext_add_operand" "rI,O"))
300 0)))]
301 ""
302 "@
303 addl %r1,%2,%0
304 subl %r1,%n2,%0")
306 (define_split
307 [(set (match_operand:DI 0 "register_operand" "")
308 (sign_extend:DI
309 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
310 (match_operand:SI 2 "const_int_operand" ""))))
311 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
312 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
313 && INTVAL (operands[2]) % 4 == 0"
314 [(set (match_dup 3) (match_dup 4))
315 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
316 (match_dup 5))
317 (match_dup 1))))]
318 {
319 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
320 int mult = 4;
322 if (val % 2 == 0)
323 val /= 2, mult = 8;
325 operands[4] = GEN_INT (val);
326 operands[5] = GEN_INT (mult);
327 })
329 (define_split
330 [(set (match_operand:DI 0 "register_operand" "")
331 (sign_extend:DI
332 (plus:SI (match_operator:SI 1 "comparison_operator"
333 [(match_operand 2 "" "")
334 (match_operand 3 "" "")])
335 (match_operand:SI 4 "add_operand" ""))))
336 (clobber (match_operand:DI 5 "register_operand" ""))]
337 ""
338 [(set (match_dup 5) (match_dup 6))
339 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
340 {
341 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
342 operands[2], operands[3]);
343 operands[7] = gen_lowpart (SImode, operands[5]);
344 })
346 (define_insn "addvsi3"
347 [(set (match_operand:SI 0 "register_operand" "=r,r")
348 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
349 (match_operand:SI 2 "sext_add_operand" "rI,O")))
350 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
351 (sign_extend:DI (match_dup 2)))
352 (sign_extend:DI (plus:SI (match_dup 1)
353 (match_dup 2))))
354 (const_int 0))]
355 ""
356 "@
357 addlv %r1,%2,%0
358 sublv %r1,%n2,%0")
360 (define_expand "adddi3"
361 [(set (match_operand:DI 0 "register_operand" "")
362 (plus:DI (match_operand:DI 1 "register_operand" "")
363 (match_operand:DI 2 "add_operand" "")))]
364 ""
365 "")
367 (define_insn "*adddi_er_lo16_dtp"
368 [(set (match_operand:DI 0 "register_operand" "=r")
369 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
370 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
371 "HAVE_AS_TLS"
372 "lda %0,%2(%1)\t\t!dtprel")
374 (define_insn "*adddi_er_hi32_dtp"
375 [(set (match_operand:DI 0 "register_operand" "=r")
376 (plus:DI (match_operand:DI 1 "register_operand" "r")
377 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
378 "HAVE_AS_TLS"
379 "ldah %0,%2(%1)\t\t!dtprelhi")
381 (define_insn "*adddi_er_lo32_dtp"
382 [(set (match_operand:DI 0 "register_operand" "=r")
383 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
384 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
385 "HAVE_AS_TLS"
386 "lda %0,%2(%1)\t\t!dtprello")
388 (define_insn "*adddi_er_lo16_tp"
389 [(set (match_operand:DI 0 "register_operand" "=r")
390 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
391 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
392 "HAVE_AS_TLS"
393 "lda %0,%2(%1)\t\t!tprel")
395 (define_insn "*adddi_er_hi32_tp"
396 [(set (match_operand:DI 0 "register_operand" "=r")
397 (plus:DI (match_operand:DI 1 "register_operand" "r")
398 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
399 "HAVE_AS_TLS"
400 "ldah %0,%2(%1)\t\t!tprelhi")
402 (define_insn "*adddi_er_lo32_tp"
403 [(set (match_operand:DI 0 "register_operand" "=r")
404 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
405 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
406 "HAVE_AS_TLS"
407 "lda %0,%2(%1)\t\t!tprello")
409 (define_insn "*adddi_er_high_l"
410 [(set (match_operand:DI 0 "register_operand" "=r")
411 (plus:DI (match_operand:DI 1 "register_operand" "r")
412 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
413 "TARGET_EXPLICIT_RELOCS && reload_completed"
414 "ldah %0,%2(%1)\t\t!gprelhigh"
415 [(set_attr "usegp" "yes")])
417 (define_split
418 [(set (match_operand:DI 0 "register_operand" "")
419 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
420 "TARGET_EXPLICIT_RELOCS && reload_completed"
421 [(set (match_dup 0)
422 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
423 "operands[2] = pic_offset_table_rtx;")
425 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
426 ;; With complications like
427 ;;
428 ;; The NT stack unwind code can't handle a subq to adjust the stack
429 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
430 ;; the exception handling code will loop if a subq is used and an
431 ;; exception occurs.
432 ;;
433 ;; The 19980616 change to emit prologues as RTL also confused some
434 ;; versions of GDB, which also interprets prologues. This has been
435 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
436 ;; use lda here.
437 ;;
438 ;; and the fact that the three insns schedule exactly the same, it's
439 ;; just not worth the effort.
441 (define_insn "*adddi_internal"
442 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
443 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
444 (match_operand:DI 2 "add_operand" "r,K,L")))]
445 ""
446 "@
447 addq %1,%2,%0
448 lda %0,%2(%1)
449 ldah %0,%h2(%1)")
451 ;; ??? Allow large constants when basing off the frame pointer or some
452 ;; virtual register that may eliminate to the frame pointer. This is
453 ;; done because register elimination offsets will change the hi/lo split,
454 ;; and if we split before reload, we will require additional instructions.
456 (define_insn "*adddi_fp_hack"
457 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
458 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
459 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
460 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
461 && INTVAL (operands[2]) >= 0
462 /* This is the largest constant an lda+ldah pair can add, minus
463 an upper bound on the displacement between SP and AP during
464 register elimination. See INITIAL_ELIMINATION_OFFSET. */
465 && INTVAL (operands[2])
466 < (0x7fff8000
467 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
468 - ALPHA_ROUND(current_function_outgoing_args_size)
469 - (ALPHA_ROUND (get_frame_size ()
470 + max_reg_num () * UNITS_PER_WORD
471 + current_function_pretend_args_size)
472 - current_function_pretend_args_size))"
473 "@
474 lda %0,%2(%1)
475 ldah %0,%h2(%1)
476 #")
478 ;; Don't do this if we are adjusting SP since we don't want to do it
479 ;; in two steps. Don't split FP sources for the reason listed above.
480 (define_split
481 [(set (match_operand:DI 0 "register_operand" "")
482 (plus:DI (match_operand:DI 1 "register_operand" "")
483 (match_operand:DI 2 "const_int_operand" "")))]
484 "! add_operand (operands[2], DImode)
485 && operands[0] != stack_pointer_rtx
486 && operands[1] != frame_pointer_rtx
487 && operands[1] != arg_pointer_rtx"
488 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
489 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
490 {
491 HOST_WIDE_INT val = INTVAL (operands[2]);
492 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
493 HOST_WIDE_INT rest = val - low;
494 rtx rest_rtx = GEN_INT (rest);
496 operands[4] = GEN_INT (low);
497 if (satisfies_constraint_L (rest_rtx))
498 operands[3] = rest_rtx;
499 else if (! no_new_pseudos)
500 {
501 operands[3] = gen_reg_rtx (DImode);
502 emit_move_insn (operands[3], operands[2]);
503 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
504 DONE;
505 }
506 else
507 FAIL;
508 })
510 (define_insn "*saddl"
511 [(set (match_operand:SI 0 "register_operand" "=r,r")
512 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
513 (match_operand:SI 2 "const48_operand" "I,I"))
514 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
515 ""
516 "@
517 s%2addl %1,%3,%0
518 s%2subl %1,%n3,%0")
520 (define_insn "*saddl_se"
521 [(set (match_operand:DI 0 "register_operand" "=r,r")
522 (sign_extend:DI
523 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
524 (match_operand:SI 2 "const48_operand" "I,I"))
525 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
526 ""
527 "@
528 s%2addl %1,%3,%0
529 s%2subl %1,%n3,%0")
531 (define_split
532 [(set (match_operand:DI 0 "register_operand" "")
533 (sign_extend:DI
534 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
535 [(match_operand 2 "" "")
536 (match_operand 3 "" "")])
537 (match_operand:SI 4 "const48_operand" ""))
538 (match_operand:SI 5 "sext_add_operand" ""))))
539 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
540 ""
541 [(set (match_dup 6) (match_dup 7))
542 (set (match_dup 0)
543 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
544 (match_dup 5))))]
545 {
546 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
547 operands[2], operands[3]);
548 operands[8] = gen_lowpart (SImode, operands[6]);
549 })
551 (define_insn "*saddq"
552 [(set (match_operand:DI 0 "register_operand" "=r,r")
553 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
554 (match_operand:DI 2 "const48_operand" "I,I"))
555 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
556 ""
557 "@
558 s%2addq %1,%3,%0
559 s%2subq %1,%n3,%0")
561 (define_insn "addvdi3"
562 [(set (match_operand:DI 0 "register_operand" "=r,r")
563 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
564 (match_operand:DI 2 "sext_add_operand" "rI,O")))
565 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
566 (sign_extend:TI (match_dup 2)))
567 (sign_extend:TI (plus:DI (match_dup 1)
568 (match_dup 2))))
569 (const_int 0))]
570 ""
571 "@
572 addqv %r1,%2,%0
573 subqv %r1,%n2,%0")
575 (define_insn "negsi2"
576 [(set (match_operand:SI 0 "register_operand" "=r")
577 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
578 ""
579 "subl $31,%1,%0")
581 (define_insn "*negsi_se"
582 [(set (match_operand:DI 0 "register_operand" "=r")
583 (sign_extend:DI (neg:SI
584 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
585 ""
586 "subl $31,%1,%0")
588 (define_insn "negvsi2"
589 [(set (match_operand:SI 0 "register_operand" "=r")
590 (neg:SI (match_operand:SI 1 "register_operand" "r")))
591 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
592 (sign_extend:DI (neg:SI (match_dup 1))))
593 (const_int 0))]
594 ""
595 "sublv $31,%1,%0")
597 (define_insn "negdi2"
598 [(set (match_operand:DI 0 "register_operand" "=r")
599 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
600 ""
601 "subq $31,%1,%0")
603 (define_insn "negvdi2"
604 [(set (match_operand:DI 0 "register_operand" "=r")
605 (neg:DI (match_operand:DI 1 "register_operand" "r")))
606 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
607 (sign_extend:TI (neg:DI (match_dup 1))))
608 (const_int 0))]
609 ""
610 "subqv $31,%1,%0")
612 (define_expand "subsi3"
613 [(set (match_operand:SI 0 "register_operand" "")
614 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
615 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
616 "! optimize"
617 "")
619 (define_insn "*subsi_internal"
620 [(set (match_operand:SI 0 "register_operand" "=r")
621 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
622 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
623 ""
624 "subl %r1,%2,%0")
626 (define_insn "*subsi_se"
627 [(set (match_operand:DI 0 "register_operand" "=r")
628 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
629 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
630 ""
631 "subl %r1,%2,%0")
633 (define_insn "*subsi_se2"
634 [(set (match_operand:DI 0 "register_operand" "=r")
635 (sign_extend:DI
636 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
637 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
638 0)))]
639 ""
640 "subl %r1,%2,%0")
642 (define_insn "subvsi3"
643 [(set (match_operand:SI 0 "register_operand" "=r")
644 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
645 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
646 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
647 (sign_extend:DI (match_dup 2)))
648 (sign_extend:DI (minus:SI (match_dup 1)
649 (match_dup 2))))
650 (const_int 0))]
651 ""
652 "sublv %r1,%2,%0")
654 (define_insn "subdi3"
655 [(set (match_operand:DI 0 "register_operand" "=r")
656 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
657 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
658 ""
659 "subq %r1,%2,%0")
661 (define_insn "*ssubl"
662 [(set (match_operand:SI 0 "register_operand" "=r")
663 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
664 (match_operand:SI 2 "const48_operand" "I"))
665 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
666 ""
667 "s%2subl %1,%3,%0")
669 (define_insn "*ssubl_se"
670 [(set (match_operand:DI 0 "register_operand" "=r")
671 (sign_extend:DI
672 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
673 (match_operand:SI 2 "const48_operand" "I"))
674 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
675 ""
676 "s%2subl %1,%3,%0")
678 (define_insn "*ssubq"
679 [(set (match_operand:DI 0 "register_operand" "=r")
680 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
681 (match_operand:DI 2 "const48_operand" "I"))
682 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
683 ""
684 "s%2subq %1,%3,%0")
686 (define_insn "subvdi3"
687 [(set (match_operand:DI 0 "register_operand" "=r")
688 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
689 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
690 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
691 (sign_extend:TI (match_dup 2)))
692 (sign_extend:TI (minus:DI (match_dup 1)
693 (match_dup 2))))
694 (const_int 0))]
695 ""
696 "subqv %r1,%2,%0")
698 ;; The Unicos/Mk assembler doesn't support mull.
700 (define_insn "mulsi3"
701 [(set (match_operand:SI 0 "register_operand" "=r")
702 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
703 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
704 "!TARGET_ABI_UNICOSMK"
705 "mull %r1,%2,%0"
706 [(set_attr "type" "imul")
707 (set_attr "opsize" "si")])
709 (define_insn "*mulsi_se"
710 [(set (match_operand:DI 0 "register_operand" "=r")
711 (sign_extend:DI
712 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
713 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
714 "!TARGET_ABI_UNICOSMK"
715 "mull %r1,%2,%0"
716 [(set_attr "type" "imul")
717 (set_attr "opsize" "si")])
719 (define_insn "mulvsi3"
720 [(set (match_operand:SI 0 "register_operand" "=r")
721 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
722 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
723 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
724 (sign_extend:DI (match_dup 2)))
725 (sign_extend:DI (mult:SI (match_dup 1)
726 (match_dup 2))))
727 (const_int 0))]
728 "!TARGET_ABI_UNICOSMK"
729 "mullv %r1,%2,%0"
730 [(set_attr "type" "imul")
731 (set_attr "opsize" "si")])
733 (define_insn "muldi3"
734 [(set (match_operand:DI 0 "register_operand" "=r")
735 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
736 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
737 ""
738 "mulq %r1,%2,%0"
739 [(set_attr "type" "imul")])
741 (define_insn "mulvdi3"
742 [(set (match_operand:DI 0 "register_operand" "=r")
743 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
744 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
745 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
746 (sign_extend:TI (match_dup 2)))
747 (sign_extend:TI (mult:DI (match_dup 1)
748 (match_dup 2))))
749 (const_int 0))]
750 ""
751 "mulqv %r1,%2,%0"
752 [(set_attr "type" "imul")])
754 (define_expand "umuldi3_highpart"
755 [(set (match_operand:DI 0 "register_operand" "")
756 (truncate:DI
757 (lshiftrt:TI
758 (mult:TI (zero_extend:TI
759 (match_operand:DI 1 "register_operand" ""))
760 (match_operand:DI 2 "reg_or_8bit_operand" ""))
761 (const_int 64))))]
762 ""
763 {
764 if (REG_P (operands[2]))
765 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
766 })
768 (define_insn "*umuldi3_highpart_reg"
769 [(set (match_operand:DI 0 "register_operand" "=r")
770 (truncate:DI
771 (lshiftrt:TI
772 (mult:TI (zero_extend:TI
773 (match_operand:DI 1 "register_operand" "r"))
774 (zero_extend:TI
775 (match_operand:DI 2 "register_operand" "r")))
776 (const_int 64))))]
777 ""
778 "umulh %1,%2,%0"
779 [(set_attr "type" "imul")
780 (set_attr "opsize" "udi")])
782 (define_insn "*umuldi3_highpart_const"
783 [(set (match_operand:DI 0 "register_operand" "=r")
784 (truncate:DI
785 (lshiftrt:TI
786 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
787 (match_operand:TI 2 "cint8_operand" "I"))
788 (const_int 64))))]
789 ""
790 "umulh %1,%2,%0"
791 [(set_attr "type" "imul")
792 (set_attr "opsize" "udi")])
793 \f
794 ;; The divide and remainder operations take their inputs from r24 and
795 ;; r25, put their output in r27, and clobber r23 and r28 on all
796 ;; systems except Unicos/Mk. On Unicos, the standard library provides
797 ;; subroutines which use the standard calling convention and work on
798 ;; DImode operands.
800 ;; ??? Force sign-extension here because some versions of OSF/1 and
801 ;; Interix/NT don't do the right thing if the inputs are not properly
802 ;; sign-extended. But Linux, for instance, does not have this
803 ;; problem. Is it worth the complication here to eliminate the sign
804 ;; extension?
806 (define_expand "divsi3"
807 [(set (match_dup 3)
808 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
809 (set (match_dup 4)
810 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
811 (parallel [(set (match_dup 5)
812 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
813 (clobber (reg:DI 23))
814 (clobber (reg:DI 28))])
815 (set (match_operand:SI 0 "nonimmediate_operand" "")
816 (subreg:SI (match_dup 5) 0))]
817 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
818 {
819 operands[3] = gen_reg_rtx (DImode);
820 operands[4] = gen_reg_rtx (DImode);
821 operands[5] = gen_reg_rtx (DImode);
822 })
824 (define_expand "udivsi3"
825 [(set (match_dup 3)
826 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
827 (set (match_dup 4)
828 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
829 (parallel [(set (match_dup 5)
830 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
831 (clobber (reg:DI 23))
832 (clobber (reg:DI 28))])
833 (set (match_operand:SI 0 "nonimmediate_operand" "")
834 (subreg:SI (match_dup 5) 0))]
835 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
836 {
837 operands[3] = gen_reg_rtx (DImode);
838 operands[4] = gen_reg_rtx (DImode);
839 operands[5] = gen_reg_rtx (DImode);
840 })
842 (define_expand "modsi3"
843 [(set (match_dup 3)
844 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
845 (set (match_dup 4)
846 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
847 (parallel [(set (match_dup 5)
848 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
849 (clobber (reg:DI 23))
850 (clobber (reg:DI 28))])
851 (set (match_operand:SI 0 "nonimmediate_operand" "")
852 (subreg:SI (match_dup 5) 0))]
853 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
854 {
855 operands[3] = gen_reg_rtx (DImode);
856 operands[4] = gen_reg_rtx (DImode);
857 operands[5] = gen_reg_rtx (DImode);
858 })
860 (define_expand "umodsi3"
861 [(set (match_dup 3)
862 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
863 (set (match_dup 4)
864 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
865 (parallel [(set (match_dup 5)
866 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
867 (clobber (reg:DI 23))
868 (clobber (reg:DI 28))])
869 (set (match_operand:SI 0 "nonimmediate_operand" "")
870 (subreg:SI (match_dup 5) 0))]
871 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
872 {
873 operands[3] = gen_reg_rtx (DImode);
874 operands[4] = gen_reg_rtx (DImode);
875 operands[5] = gen_reg_rtx (DImode);
876 })
878 (define_expand "divdi3"
879 [(parallel [(set (match_operand:DI 0 "register_operand" "")
880 (div:DI (match_operand:DI 1 "register_operand" "")
881 (match_operand:DI 2 "register_operand" "")))
882 (clobber (reg:DI 23))
883 (clobber (reg:DI 28))])]
884 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
885 "")
887 (define_expand "udivdi3"
888 [(parallel [(set (match_operand:DI 0 "register_operand" "")
889 (udiv:DI (match_operand:DI 1 "register_operand" "")
890 (match_operand:DI 2 "register_operand" "")))
891 (clobber (reg:DI 23))
892 (clobber (reg:DI 28))])]
893 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
894 "")
896 (define_expand "moddi3"
897 [(use (match_operand:DI 0 "register_operand" ""))
898 (use (match_operand:DI 1 "register_operand" ""))
899 (use (match_operand:DI 2 "register_operand" ""))]
900 "!TARGET_ABI_OPEN_VMS"
901 {
902 if (TARGET_ABI_UNICOSMK)
903 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
904 else
905 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
906 DONE;
907 })
909 (define_expand "moddi3_dft"
910 [(parallel [(set (match_operand:DI 0 "register_operand" "")
911 (mod:DI (match_operand:DI 1 "register_operand" "")
912 (match_operand:DI 2 "register_operand" "")))
913 (clobber (reg:DI 23))
914 (clobber (reg:DI 28))])]
915 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
916 "")
918 ;; On Unicos/Mk, we do as the system's C compiler does:
919 ;; compute the quotient, multiply and subtract.
921 (define_expand "moddi3_umk"
922 [(use (match_operand:DI 0 "register_operand" ""))
923 (use (match_operand:DI 1 "register_operand" ""))
924 (use (match_operand:DI 2 "register_operand" ""))]
925 "TARGET_ABI_UNICOSMK"
926 {
927 rtx div, mul = gen_reg_rtx (DImode);
929 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
930 NULL_RTX, 0, OPTAB_LIB);
931 div = force_reg (DImode, div);
932 emit_insn (gen_muldi3 (mul, operands[2], div));
933 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
934 DONE;
935 })
937 (define_expand "umoddi3"
938 [(use (match_operand:DI 0 "register_operand" ""))
939 (use (match_operand:DI 1 "register_operand" ""))
940 (use (match_operand:DI 2 "register_operand" ""))]
941 "! TARGET_ABI_OPEN_VMS"
942 {
943 if (TARGET_ABI_UNICOSMK)
944 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
945 else
946 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
947 DONE;
948 })
950 (define_expand "umoddi3_dft"
951 [(parallel [(set (match_operand:DI 0 "register_operand" "")
952 (umod:DI (match_operand:DI 1 "register_operand" "")
953 (match_operand:DI 2 "register_operand" "")))
954 (clobber (reg:DI 23))
955 (clobber (reg:DI 28))])]
956 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
957 "")
959 (define_expand "umoddi3_umk"
960 [(use (match_operand:DI 0 "register_operand" ""))
961 (use (match_operand:DI 1 "register_operand" ""))
962 (use (match_operand:DI 2 "register_operand" ""))]
963 "TARGET_ABI_UNICOSMK"
964 {
965 rtx div, mul = gen_reg_rtx (DImode);
967 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
968 NULL_RTX, 1, OPTAB_LIB);
969 div = force_reg (DImode, div);
970 emit_insn (gen_muldi3 (mul, operands[2], div));
971 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
972 DONE;
973 })
975 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
976 ;; expanded by the assembler.
978 (define_insn_and_split "*divmodsi_internal_er"
979 [(set (match_operand:DI 0 "register_operand" "=c")
980 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
981 [(match_operand:DI 1 "register_operand" "a")
982 (match_operand:DI 2 "register_operand" "b")])))
983 (clobber (reg:DI 23))
984 (clobber (reg:DI 28))]
985 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
986 "#"
987 "&& reload_completed"
988 [(parallel [(set (match_dup 0)
989 (sign_extend:DI (match_dup 3)))
990 (use (match_dup 0))
991 (use (match_dup 4))
992 (clobber (reg:DI 23))
993 (clobber (reg:DI 28))])]
994 {
995 const char *str;
996 switch (GET_CODE (operands[3]))
997 {
998 case DIV:
999 str = "__divl";
1000 break;
1001 case UDIV:
1002 str = "__divlu";
1003 break;
1004 case MOD:
1005 str = "__reml";
1006 break;
1007 case UMOD:
1008 str = "__remlu";
1009 break;
1010 default:
1011 gcc_unreachable ();
1012 }
1013 operands[4] = GEN_INT (alpha_next_sequence_number++);
1014 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1015 gen_rtx_SYMBOL_REF (DImode, str),
1016 operands[4]));
1017 }
1018 [(set_attr "type" "jsr")
1019 (set_attr "length" "8")])
1021 (define_insn "*divmodsi_internal_er_1"
1022 [(set (match_operand:DI 0 "register_operand" "=c")
1023 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1024 [(match_operand:DI 1 "register_operand" "a")
1025 (match_operand:DI 2 "register_operand" "b")])))
1026 (use (match_operand:DI 4 "register_operand" "c"))
1027 (use (match_operand 5 "const_int_operand" ""))
1028 (clobber (reg:DI 23))
1029 (clobber (reg:DI 28))]
1030 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1031 "jsr $23,($27),__%E3%j5"
1032 [(set_attr "type" "jsr")
1033 (set_attr "length" "4")])
1035 (define_insn "*divmodsi_internal"
1036 [(set (match_operand:DI 0 "register_operand" "=c")
1037 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1038 [(match_operand:DI 1 "register_operand" "a")
1039 (match_operand:DI 2 "register_operand" "b")])))
1040 (clobber (reg:DI 23))
1041 (clobber (reg:DI 28))]
1042 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1043 "%E3 %1,%2,%0"
1044 [(set_attr "type" "jsr")
1045 (set_attr "length" "8")])
1047 (define_insn_and_split "*divmoddi_internal_er"
1048 [(set (match_operand:DI 0 "register_operand" "=c")
1049 (match_operator:DI 3 "divmod_operator"
1050 [(match_operand:DI 1 "register_operand" "a")
1051 (match_operand:DI 2 "register_operand" "b")]))
1052 (clobber (reg:DI 23))
1053 (clobber (reg:DI 28))]
1054 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1055 "#"
1056 "&& reload_completed"
1057 [(parallel [(set (match_dup 0) (match_dup 3))
1058 (use (match_dup 0))
1059 (use (match_dup 4))
1060 (clobber (reg:DI 23))
1061 (clobber (reg:DI 28))])]
1062 {
1063 const char *str;
1064 switch (GET_CODE (operands[3]))
1065 {
1066 case DIV:
1067 str = "__divq";
1068 break;
1069 case UDIV:
1070 str = "__divqu";
1071 break;
1072 case MOD:
1073 str = "__remq";
1074 break;
1075 case UMOD:
1076 str = "__remqu";
1077 break;
1078 default:
1079 gcc_unreachable ();
1080 }
1081 operands[4] = GEN_INT (alpha_next_sequence_number++);
1082 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1083 gen_rtx_SYMBOL_REF (DImode, str),
1084 operands[4]));
1085 }
1086 [(set_attr "type" "jsr")
1087 (set_attr "length" "8")])
1089 (define_insn "*divmoddi_internal_er_1"
1090 [(set (match_operand:DI 0 "register_operand" "=c")
1091 (match_operator:DI 3 "divmod_operator"
1092 [(match_operand:DI 1 "register_operand" "a")
1093 (match_operand:DI 2 "register_operand" "b")]))
1094 (use (match_operand:DI 4 "register_operand" "c"))
1095 (use (match_operand 5 "const_int_operand" ""))
1096 (clobber (reg:DI 23))
1097 (clobber (reg:DI 28))]
1098 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1099 "jsr $23,($27),__%E3%j5"
1100 [(set_attr "type" "jsr")
1101 (set_attr "length" "4")])
1103 (define_insn "*divmoddi_internal"
1104 [(set (match_operand:DI 0 "register_operand" "=c")
1105 (match_operator:DI 3 "divmod_operator"
1106 [(match_operand:DI 1 "register_operand" "a")
1107 (match_operand:DI 2 "register_operand" "b")]))
1108 (clobber (reg:DI 23))
1109 (clobber (reg:DI 28))]
1110 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1111 "%E3 %1,%2,%0"
1112 [(set_attr "type" "jsr")
1113 (set_attr "length" "8")])
1114 \f
1115 ;; Next are the basic logical operations. We only expose the DImode operations
1116 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1117 ;; the atomic operation splitters.
1119 (define_insn "*andsi_internal"
1120 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1121 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1122 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1123 ""
1124 "@
1125 and %r1,%2,%0
1126 bic %r1,%N2,%0
1127 zapnot %r1,%m2,%0"
1128 [(set_attr "type" "ilog,ilog,shift")])
1130 (define_insn "anddi3"
1131 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1132 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1133 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1134 ""
1135 "@
1136 and %r1,%2,%0
1137 bic %r1,%N2,%0
1138 zapnot %r1,%m2,%0"
1139 [(set_attr "type" "ilog,ilog,shift")])
1141 ;; There are times when we can split an AND into two AND insns. This occurs
1142 ;; when we can first clear any bytes and then clear anything else. For
1143 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1144 ;; Only do this when running on 64-bit host since the computations are
1145 ;; too messy otherwise.
1147 (define_split
1148 [(set (match_operand:DI 0 "register_operand" "")
1149 (and:DI (match_operand:DI 1 "register_operand" "")
1150 (match_operand:DI 2 "const_int_operand" "")))]
1151 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1152 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1153 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1154 {
1155 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1156 unsigned HOST_WIDE_INT mask2 = mask1;
1157 int i;
1159 /* For each byte that isn't all zeros, make it all ones. */
1160 for (i = 0; i < 64; i += 8)
1161 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1162 mask1 |= (HOST_WIDE_INT) 0xff << i;
1164 /* Now turn on any bits we've just turned off. */
1165 mask2 |= ~ mask1;
1167 operands[3] = GEN_INT (mask1);
1168 operands[4] = GEN_INT (mask2);
1169 })
1171 (define_expand "zero_extendqihi2"
1172 [(set (match_operand:HI 0 "register_operand" "")
1173 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1174 ""
1175 {
1176 if (! TARGET_BWX)
1177 operands[1] = force_reg (QImode, operands[1]);
1178 })
1180 (define_insn "*zero_extendqihi2_bwx"
1181 [(set (match_operand:HI 0 "register_operand" "=r,r")
1182 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1183 "TARGET_BWX"
1184 "@
1185 and %1,0xff,%0
1186 ldbu %0,%1"
1187 [(set_attr "type" "ilog,ild")])
1189 (define_insn "*zero_extendqihi2_nobwx"
1190 [(set (match_operand:HI 0 "register_operand" "=r")
1191 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1192 "! TARGET_BWX"
1193 "and %1,0xff,%0"
1194 [(set_attr "type" "ilog")])
1196 (define_expand "zero_extendqisi2"
1197 [(set (match_operand:SI 0 "register_operand" "")
1198 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1199 ""
1200 {
1201 if (! TARGET_BWX)
1202 operands[1] = force_reg (QImode, operands[1]);
1203 })
1205 (define_insn "*zero_extendqisi2_bwx"
1206 [(set (match_operand:SI 0 "register_operand" "=r,r")
1207 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1208 "TARGET_BWX"
1209 "@
1210 and %1,0xff,%0
1211 ldbu %0,%1"
1212 [(set_attr "type" "ilog,ild")])
1214 (define_insn "*zero_extendqisi2_nobwx"
1215 [(set (match_operand:SI 0 "register_operand" "=r")
1216 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1217 "! TARGET_BWX"
1218 "and %1,0xff,%0"
1219 [(set_attr "type" "ilog")])
1221 (define_expand "zero_extendqidi2"
1222 [(set (match_operand:DI 0 "register_operand" "")
1223 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1224 ""
1225 {
1226 if (! TARGET_BWX)
1227 operands[1] = force_reg (QImode, operands[1]);
1228 })
1230 (define_insn "*zero_extendqidi2_bwx"
1231 [(set (match_operand:DI 0 "register_operand" "=r,r")
1232 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1233 "TARGET_BWX"
1234 "@
1235 and %1,0xff,%0
1236 ldbu %0,%1"
1237 [(set_attr "type" "ilog,ild")])
1239 (define_insn "*zero_extendqidi2_nobwx"
1240 [(set (match_operand:DI 0 "register_operand" "=r")
1241 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1242 "! TARGET_BWX"
1243 "and %1,0xff,%0"
1244 [(set_attr "type" "ilog")])
1246 (define_expand "zero_extendhisi2"
1247 [(set (match_operand:SI 0 "register_operand" "")
1248 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1249 ""
1250 {
1251 if (! TARGET_BWX)
1252 operands[1] = force_reg (HImode, operands[1]);
1253 })
1255 (define_insn "*zero_extendhisi2_bwx"
1256 [(set (match_operand:SI 0 "register_operand" "=r,r")
1257 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1258 "TARGET_BWX"
1259 "@
1260 zapnot %1,3,%0
1261 ldwu %0,%1"
1262 [(set_attr "type" "shift,ild")])
1264 (define_insn "*zero_extendhisi2_nobwx"
1265 [(set (match_operand:SI 0 "register_operand" "=r")
1266 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1267 "! TARGET_BWX"
1268 "zapnot %1,3,%0"
1269 [(set_attr "type" "shift")])
1271 (define_expand "zero_extendhidi2"
1272 [(set (match_operand:DI 0 "register_operand" "")
1273 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1274 ""
1275 {
1276 if (! TARGET_BWX)
1277 operands[1] = force_reg (HImode, operands[1]);
1278 })
1280 (define_insn "*zero_extendhidi2_bwx"
1281 [(set (match_operand:DI 0 "register_operand" "=r,r")
1282 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1283 "TARGET_BWX"
1284 "@
1285 zapnot %1,3,%0
1286 ldwu %0,%1"
1287 [(set_attr "type" "shift,ild")])
1289 (define_insn "*zero_extendhidi2_nobwx"
1290 [(set (match_operand:DI 0 "register_operand" "=r")
1291 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1292 ""
1293 "zapnot %1,3,%0"
1294 [(set_attr "type" "shift")])
1296 (define_insn "zero_extendsidi2"
1297 [(set (match_operand:DI 0 "register_operand" "=r")
1298 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1299 ""
1300 "zapnot %1,15,%0"
1301 [(set_attr "type" "shift")])
1303 (define_insn "*andnotsi3"
1304 [(set (match_operand:SI 0 "register_operand" "=r")
1305 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1306 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1307 ""
1308 "bic %r2,%1,%0"
1309 [(set_attr "type" "ilog")])
1311 (define_insn "andnotdi3"
1312 [(set (match_operand:DI 0 "register_operand" "=r")
1313 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1314 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1315 ""
1316 "bic %r2,%1,%0"
1317 [(set_attr "type" "ilog")])
1319 (define_insn "*iorsi_internal"
1320 [(set (match_operand:SI 0 "register_operand" "=r,r")
1321 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1322 (match_operand:SI 2 "or_operand" "rI,N")))]
1323 ""
1324 "@
1325 bis %r1,%2,%0
1326 ornot %r1,%N2,%0"
1327 [(set_attr "type" "ilog")])
1329 (define_insn "iordi3"
1330 [(set (match_operand:DI 0 "register_operand" "=r,r")
1331 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1332 (match_operand:DI 2 "or_operand" "rI,N")))]
1333 ""
1334 "@
1335 bis %r1,%2,%0
1336 ornot %r1,%N2,%0"
1337 [(set_attr "type" "ilog")])
1339 (define_insn "*one_cmplsi_internal"
1340 [(set (match_operand:SI 0 "register_operand" "=r")
1341 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1342 ""
1343 "ornot $31,%1,%0"
1344 [(set_attr "type" "ilog")])
1346 (define_insn "one_cmpldi2"
1347 [(set (match_operand:DI 0 "register_operand" "=r")
1348 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1349 ""
1350 "ornot $31,%1,%0"
1351 [(set_attr "type" "ilog")])
1353 (define_insn "*iornotsi3"
1354 [(set (match_operand:SI 0 "register_operand" "=r")
1355 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1356 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1357 ""
1358 "ornot %r2,%1,%0"
1359 [(set_attr "type" "ilog")])
1361 (define_insn "*iornotdi3"
1362 [(set (match_operand:DI 0 "register_operand" "=r")
1363 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1364 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1365 ""
1366 "ornot %r2,%1,%0"
1367 [(set_attr "type" "ilog")])
1369 (define_insn "*xorsi_internal"
1370 [(set (match_operand:SI 0 "register_operand" "=r,r")
1371 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1372 (match_operand:SI 2 "or_operand" "rI,N")))]
1373 ""
1374 "@
1375 xor %r1,%2,%0
1376 eqv %r1,%N2,%0"
1377 [(set_attr "type" "ilog")])
1379 (define_insn "xordi3"
1380 [(set (match_operand:DI 0 "register_operand" "=r,r")
1381 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1382 (match_operand:DI 2 "or_operand" "rI,N")))]
1383 ""
1384 "@
1385 xor %r1,%2,%0
1386 eqv %r1,%N2,%0"
1387 [(set_attr "type" "ilog")])
1389 (define_insn "*xornotsi3"
1390 [(set (match_operand:SI 0 "register_operand" "=r")
1391 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1392 (match_operand:SI 2 "register_operand" "rI"))))]
1393 ""
1394 "eqv %r1,%2,%0"
1395 [(set_attr "type" "ilog")])
1397 (define_insn "*xornotdi3"
1398 [(set (match_operand:DI 0 "register_operand" "=r")
1399 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1400 (match_operand:DI 2 "register_operand" "rI"))))]
1401 ""
1402 "eqv %r1,%2,%0"
1403 [(set_attr "type" "ilog")])
1404 \f
1405 ;; Handle FFS and related insns iff we support CIX.
1407 (define_expand "ffsdi2"
1408 [(set (match_dup 2)
1409 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1410 (set (match_dup 3)
1411 (plus:DI (match_dup 2) (const_int 1)))
1412 (set (match_operand:DI 0 "register_operand" "")
1413 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1414 (const_int 0) (match_dup 3)))]
1415 "TARGET_CIX"
1416 {
1417 operands[2] = gen_reg_rtx (DImode);
1418 operands[3] = gen_reg_rtx (DImode);
1419 })
1421 (define_insn "clzdi2"
1422 [(set (match_operand:DI 0 "register_operand" "=r")
1423 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1424 "TARGET_CIX"
1425 "ctlz %1,%0"
1426 [(set_attr "type" "mvi")])
1428 (define_insn "ctzdi2"
1429 [(set (match_operand:DI 0 "register_operand" "=r")
1430 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1431 "TARGET_CIX"
1432 "cttz %1,%0"
1433 [(set_attr "type" "mvi")])
1435 (define_insn "popcountdi2"
1436 [(set (match_operand:DI 0 "register_operand" "=r")
1437 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1438 "TARGET_CIX"
1439 "ctpop %1,%0"
1440 [(set_attr "type" "mvi")])
1442 (define_expand "bswapsi2"
1443 [(set (match_operand:SI 0 "register_operand" "")
1444 (bswap:SI (match_operand:SI 1 "register_operand" "")))]
1445 "!optimize_size"
1446 {
1447 rtx t0, t1;
1449 t0 = gen_reg_rtx (DImode);
1450 t1 = gen_reg_rtx (DImode);
1452 emit_insn (gen_insxh (t0, gen_lowpart (DImode, operands[1]),
1453 GEN_INT (32), GEN_INT (WORDS_BIG_ENDIAN ? 0 : 7)));
1454 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
1455 GEN_INT (24)));
1456 emit_insn (gen_iordi3 (t1, t0, t1));
1457 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1458 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5)));
1459 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa)));
1460 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0),
1461 gen_lowpart (SImode, t1)));
1462 DONE;
1463 })
1465 (define_expand "bswapdi2"
1466 [(set (match_operand:DI 0 "register_operand" "")
1467 (bswap:DI (match_operand:DI 1 "register_operand" "")))]
1468 "!optimize_size"
1469 {
1470 rtx t0, t1;
1472 t0 = gen_reg_rtx (DImode);
1473 t1 = gen_reg_rtx (DImode);
1475 /* This method of shifting and masking is not specific to Alpha, but
1476 is only profitable on Alpha because of our handy byte zap insn. */
1478 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32)));
1479 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32)));
1480 emit_insn (gen_iordi3 (t1, t0, t1));
1482 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1483 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16)));
1484 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc)));
1485 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33)));
1486 emit_insn (gen_iordi3 (t1, t0, t1));
1488 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8)));
1489 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8)));
1490 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa)));
1491 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55)));
1492 emit_insn (gen_iordi3 (operands[0], t0, t1));
1493 DONE;
1494 })
1495 \f
1496 ;; Next come the shifts and the various extract and insert operations.
1498 (define_insn "ashldi3"
1499 [(set (match_operand:DI 0 "register_operand" "=r,r")
1500 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1501 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1502 ""
1503 {
1504 switch (which_alternative)
1505 {
1506 case 0:
1507 if (operands[2] == const1_rtx)
1508 return "addq %r1,%r1,%0";
1509 else
1510 return "s%P2addq %r1,0,%0";
1511 case 1:
1512 return "sll %r1,%2,%0";
1513 default:
1514 gcc_unreachable ();
1515 }
1516 }
1517 [(set_attr "type" "iadd,shift")])
1519 (define_insn "*ashldi_se"
1520 [(set (match_operand:DI 0 "register_operand" "=r")
1521 (sign_extend:DI
1522 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1523 (match_operand:DI 2 "const_int_operand" "P"))
1524 0)))]
1525 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1526 {
1527 if (operands[2] == const1_rtx)
1528 return "addl %r1,%r1,%0";
1529 else
1530 return "s%P2addl %r1,0,%0";
1531 }
1532 [(set_attr "type" "iadd")])
1534 (define_insn "lshrdi3"
1535 [(set (match_operand:DI 0 "register_operand" "=r")
1536 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1537 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1538 ""
1539 "srl %r1,%2,%0"
1540 [(set_attr "type" "shift")])
1542 (define_insn "ashrdi3"
1543 [(set (match_operand:DI 0 "register_operand" "=r")
1544 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1545 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1546 ""
1547 "sra %r1,%2,%0"
1548 [(set_attr "type" "shift")])
1550 (define_expand "extendqihi2"
1551 [(set (match_dup 2)
1552 (ashift:DI (match_operand:QI 1 "some_operand" "")
1553 (const_int 56)))
1554 (set (match_operand:HI 0 "register_operand" "")
1555 (ashiftrt:DI (match_dup 2)
1556 (const_int 56)))]
1557 ""
1558 {
1559 if (TARGET_BWX)
1560 {
1561 emit_insn (gen_extendqihi2x (operands[0],
1562 force_reg (QImode, operands[1])));
1563 DONE;
1564 }
1566 /* If we have an unaligned MEM, extend to DImode (which we do
1567 specially) and then copy to the result. */
1568 if (unaligned_memory_operand (operands[1], HImode))
1569 {
1570 rtx temp = gen_reg_rtx (DImode);
1572 emit_insn (gen_extendqidi2 (temp, operands[1]));
1573 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1574 DONE;
1575 }
1577 operands[0] = gen_lowpart (DImode, operands[0]);
1578 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1579 operands[2] = gen_reg_rtx (DImode);
1580 })
1582 (define_insn "extendqidi2x"
1583 [(set (match_operand:DI 0 "register_operand" "=r")
1584 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1585 "TARGET_BWX"
1586 "sextb %1,%0"
1587 [(set_attr "type" "shift")])
1589 (define_insn "extendhidi2x"
1590 [(set (match_operand:DI 0 "register_operand" "=r")
1591 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1592 "TARGET_BWX"
1593 "sextw %1,%0"
1594 [(set_attr "type" "shift")])
1596 (define_insn "extendqisi2x"
1597 [(set (match_operand:SI 0 "register_operand" "=r")
1598 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1599 "TARGET_BWX"
1600 "sextb %1,%0"
1601 [(set_attr "type" "shift")])
1603 (define_insn "extendhisi2x"
1604 [(set (match_operand:SI 0 "register_operand" "=r")
1605 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1606 "TARGET_BWX"
1607 "sextw %1,%0"
1608 [(set_attr "type" "shift")])
1610 (define_insn "extendqihi2x"
1611 [(set (match_operand:HI 0 "register_operand" "=r")
1612 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1613 "TARGET_BWX"
1614 "sextb %1,%0"
1615 [(set_attr "type" "shift")])
1617 (define_expand "extendqisi2"
1618 [(set (match_dup 2)
1619 (ashift:DI (match_operand:QI 1 "some_operand" "")
1620 (const_int 56)))
1621 (set (match_operand:SI 0 "register_operand" "")
1622 (ashiftrt:DI (match_dup 2)
1623 (const_int 56)))]
1624 ""
1625 {
1626 if (TARGET_BWX)
1627 {
1628 emit_insn (gen_extendqisi2x (operands[0],
1629 force_reg (QImode, operands[1])));
1630 DONE;
1631 }
1633 /* If we have an unaligned MEM, extend to a DImode form of
1634 the result (which we do specially). */
1635 if (unaligned_memory_operand (operands[1], QImode))
1636 {
1637 rtx temp = gen_reg_rtx (DImode);
1639 emit_insn (gen_extendqidi2 (temp, operands[1]));
1640 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1641 DONE;
1642 }
1644 operands[0] = gen_lowpart (DImode, operands[0]);
1645 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1646 operands[2] = gen_reg_rtx (DImode);
1647 })
1649 (define_expand "extendqidi2"
1650 [(set (match_dup 2)
1651 (ashift:DI (match_operand:QI 1 "some_operand" "")
1652 (const_int 56)))
1653 (set (match_operand:DI 0 "register_operand" "")
1654 (ashiftrt:DI (match_dup 2)
1655 (const_int 56)))]
1656 ""
1657 {
1658 if (TARGET_BWX)
1659 {
1660 emit_insn (gen_extendqidi2x (operands[0],
1661 force_reg (QImode, operands[1])));
1662 DONE;
1663 }
1665 if (unaligned_memory_operand (operands[1], QImode))
1666 {
1667 rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
1668 alpha_set_memflags (seq, operands[1]);
1669 emit_insn (seq);
1670 DONE;
1671 }
1673 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1674 operands[2] = gen_reg_rtx (DImode);
1675 })
1677 (define_expand "extendhisi2"
1678 [(set (match_dup 2)
1679 (ashift:DI (match_operand:HI 1 "some_operand" "")
1680 (const_int 48)))
1681 (set (match_operand:SI 0 "register_operand" "")
1682 (ashiftrt:DI (match_dup 2)
1683 (const_int 48)))]
1684 ""
1685 {
1686 if (TARGET_BWX)
1687 {
1688 emit_insn (gen_extendhisi2x (operands[0],
1689 force_reg (HImode, operands[1])));
1690 DONE;
1691 }
1693 /* If we have an unaligned MEM, extend to a DImode form of
1694 the result (which we do specially). */
1695 if (unaligned_memory_operand (operands[1], HImode))
1696 {
1697 rtx temp = gen_reg_rtx (DImode);
1699 emit_insn (gen_extendhidi2 (temp, operands[1]));
1700 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1701 DONE;
1702 }
1704 operands[0] = gen_lowpart (DImode, operands[0]);
1705 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1706 operands[2] = gen_reg_rtx (DImode);
1707 })
1709 (define_expand "extendhidi2"
1710 [(set (match_dup 2)
1711 (ashift:DI (match_operand:HI 1 "some_operand" "")
1712 (const_int 48)))
1713 (set (match_operand:DI 0 "register_operand" "")
1714 (ashiftrt:DI (match_dup 2)
1715 (const_int 48)))]
1716 ""
1717 {
1718 if (TARGET_BWX)
1719 {
1720 emit_insn (gen_extendhidi2x (operands[0],
1721 force_reg (HImode, operands[1])));
1722 DONE;
1723 }
1725 if (unaligned_memory_operand (operands[1], HImode))
1726 {
1727 rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
1729 alpha_set_memflags (seq, operands[1]);
1730 emit_insn (seq);
1731 DONE;
1732 }
1734 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1735 operands[2] = gen_reg_rtx (DImode);
1736 })
1738 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1739 ;; as a pattern saves one instruction. The code is similar to that for
1740 ;; the unaligned loads (see below).
1741 ;;
1742 ;; Operand 1 is the address, operand 0 is the result.
1743 (define_expand "unaligned_extendqidi"
1744 [(use (match_operand:QI 0 "register_operand" ""))
1745 (use (match_operand:DI 1 "address_operand" ""))]
1746 ""
1747 {
1748 operands[0] = gen_lowpart (DImode, operands[0]);
1749 if (WORDS_BIG_ENDIAN)
1750 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1751 else
1752 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1753 DONE;
1754 })
1756 (define_expand "unaligned_extendqidi_le"
1757 [(set (match_dup 3)
1758 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1759 (set (match_dup 4)
1760 (ashift:DI (match_dup 3)
1761 (minus:DI (const_int 64)
1762 (ashift:DI
1763 (and:DI (match_dup 2) (const_int 7))
1764 (const_int 3)))))
1765 (set (match_operand:DI 0 "register_operand" "")
1766 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1767 "! WORDS_BIG_ENDIAN"
1768 {
1769 operands[2] = get_unaligned_offset (operands[1], 1);
1770 operands[3] = gen_reg_rtx (DImode);
1771 operands[4] = gen_reg_rtx (DImode);
1772 })
1774 (define_expand "unaligned_extendqidi_be"
1775 [(set (match_dup 3)
1776 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1777 (set (match_dup 4)
1778 (ashift:DI (match_dup 3)
1779 (ashift:DI
1780 (and:DI
1781 (plus:DI (match_dup 2) (const_int 1))
1782 (const_int 7))
1783 (const_int 3))))
1784 (set (match_operand:DI 0 "register_operand" "")
1785 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1786 "WORDS_BIG_ENDIAN"
1787 {
1788 operands[2] = get_unaligned_offset (operands[1], -1);
1789 operands[3] = gen_reg_rtx (DImode);
1790 operands[4] = gen_reg_rtx (DImode);
1791 })
1793 (define_expand "unaligned_extendhidi"
1794 [(use (match_operand:QI 0 "register_operand" ""))
1795 (use (match_operand:DI 1 "address_operand" ""))]
1796 ""
1797 {
1798 operands[0] = gen_lowpart (DImode, operands[0]);
1799 if (WORDS_BIG_ENDIAN)
1800 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1801 else
1802 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1803 DONE;
1804 })
1806 (define_expand "unaligned_extendhidi_le"
1807 [(set (match_dup 3)
1808 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1809 (set (match_dup 4)
1810 (ashift:DI (match_dup 3)
1811 (minus:DI (const_int 64)
1812 (ashift:DI
1813 (and:DI (match_dup 2) (const_int 7))
1814 (const_int 3)))))
1815 (set (match_operand:DI 0 "register_operand" "")
1816 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1817 "! WORDS_BIG_ENDIAN"
1818 {
1819 operands[2] = get_unaligned_offset (operands[1], 2);
1820 operands[3] = gen_reg_rtx (DImode);
1821 operands[4] = gen_reg_rtx (DImode);
1822 })
1824 (define_expand "unaligned_extendhidi_be"
1825 [(set (match_dup 3)
1826 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1827 (set (match_dup 4)
1828 (ashift:DI (match_dup 3)
1829 (ashift:DI
1830 (and:DI
1831 (plus:DI (match_dup 2) (const_int 1))
1832 (const_int 7))
1833 (const_int 3))))
1834 (set (match_operand:DI 0 "register_operand" "")
1835 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1836 "WORDS_BIG_ENDIAN"
1837 {
1838 operands[2] = get_unaligned_offset (operands[1], -1);
1839 operands[3] = gen_reg_rtx (DImode);
1840 operands[4] = gen_reg_rtx (DImode);
1841 })
1843 (define_insn "*extxl_const"
1844 [(set (match_operand:DI 0 "register_operand" "=r")
1845 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1846 (match_operand:DI 2 "mode_width_operand" "n")
1847 (match_operand:DI 3 "mul8_operand" "I")))]
1848 ""
1849 "ext%M2l %r1,%s3,%0"
1850 [(set_attr "type" "shift")])
1852 (define_insn "extxl_le"
1853 [(set (match_operand:DI 0 "register_operand" "=r")
1854 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1855 (match_operand:DI 2 "mode_width_operand" "n")
1856 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1857 (const_int 3))))]
1858 "! WORDS_BIG_ENDIAN"
1859 "ext%M2l %r1,%3,%0"
1860 [(set_attr "type" "shift")])
1862 (define_insn "extxl_be"
1863 [(set (match_operand:DI 0 "register_operand" "=r")
1864 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1865 (match_operand:DI 2 "mode_width_operand" "n")
1866 (minus:DI
1867 (const_int 56)
1868 (ashift:DI
1869 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1870 (const_int 3)))))]
1871 "WORDS_BIG_ENDIAN"
1872 "ext%M2l %r1,%3,%0"
1873 [(set_attr "type" "shift")])
1875 ;; Combine has some strange notion of preserving existing undefined behavior
1876 ;; in shifts larger than a word size. So capture these patterns that it
1877 ;; should have turned into zero_extracts.
1879 (define_insn "*extxl_1_le"
1880 [(set (match_operand:DI 0 "register_operand" "=r")
1881 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1882 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1883 (const_int 3)))
1884 (match_operand:DI 3 "mode_mask_operand" "n")))]
1885 "! WORDS_BIG_ENDIAN"
1886 "ext%U3l %1,%2,%0"
1887 [(set_attr "type" "shift")])
1889 (define_insn "*extxl_1_be"
1890 [(set (match_operand:DI 0 "register_operand" "=r")
1891 (and:DI (lshiftrt:DI
1892 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1893 (minus:DI (const_int 56)
1894 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1895 (const_int 3))))
1896 (match_operand:DI 3 "mode_mask_operand" "n")))]
1897 "WORDS_BIG_ENDIAN"
1898 "ext%U3l %1,%2,%0"
1899 [(set_attr "type" "shift")])
1901 (define_insn "*extql_2_le"
1902 [(set (match_operand:DI 0 "register_operand" "=r")
1903 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1904 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1905 (const_int 3))))]
1906 "! WORDS_BIG_ENDIAN"
1907 "extql %1,%2,%0"
1908 [(set_attr "type" "shift")])
1910 (define_insn "*extql_2_be"
1911 [(set (match_operand:DI 0 "register_operand" "=r")
1912 (lshiftrt:DI
1913 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1914 (minus:DI (const_int 56)
1915 (ashift:DI
1916 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1917 (const_int 3)))))]
1918 "WORDS_BIG_ENDIAN"
1919 "extql %1,%2,%0"
1920 [(set_attr "type" "shift")])
1922 (define_insn "extqh_le"
1923 [(set (match_operand:DI 0 "register_operand" "=r")
1924 (ashift:DI
1925 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1926 (minus:DI (const_int 64)
1927 (ashift:DI
1928 (and:DI
1929 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1930 (const_int 7))
1931 (const_int 3)))))]
1932 "! WORDS_BIG_ENDIAN"
1933 "extqh %r1,%2,%0"
1934 [(set_attr "type" "shift")])
1936 (define_insn "extqh_be"
1937 [(set (match_operand:DI 0 "register_operand" "=r")
1938 (ashift:DI
1939 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1940 (ashift:DI
1941 (and:DI
1942 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1943 (const_int 1))
1944 (const_int 7))
1945 (const_int 3))))]
1946 "WORDS_BIG_ENDIAN"
1947 "extqh %r1,%2,%0"
1948 [(set_attr "type" "shift")])
1950 (define_insn "extlh_le"
1951 [(set (match_operand:DI 0 "register_operand" "=r")
1952 (ashift:DI
1953 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1954 (const_int 2147483647))
1955 (minus:DI (const_int 64)
1956 (ashift:DI
1957 (and:DI
1958 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1959 (const_int 7))
1960 (const_int 3)))))]
1961 "! WORDS_BIG_ENDIAN"
1962 "extlh %r1,%2,%0"
1963 [(set_attr "type" "shift")])
1965 (define_insn "extlh_be"
1966 [(set (match_operand:DI 0 "register_operand" "=r")
1967 (and:DI
1968 (ashift:DI
1969 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1970 (ashift:DI
1971 (and:DI
1972 (plus:DI
1973 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1974 (const_int 1))
1975 (const_int 7))
1976 (const_int 3)))
1977 (const_int 2147483647)))]
1978 "WORDS_BIG_ENDIAN"
1979 "extlh %r1,%2,%0"
1980 [(set_attr "type" "shift")])
1982 (define_insn "extwh_le"
1983 [(set (match_operand:DI 0 "register_operand" "=r")
1984 (ashift:DI
1985 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1986 (const_int 65535))
1987 (minus:DI (const_int 64)
1988 (ashift:DI
1989 (and:DI
1990 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1991 (const_int 7))
1992 (const_int 3)))))]
1993 "! WORDS_BIG_ENDIAN"
1994 "extwh %r1,%2,%0"
1995 [(set_attr "type" "shift")])
1997 (define_insn "extwh_be"
1998 [(set (match_operand:DI 0 "register_operand" "=r")
1999 (and:DI
2000 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2001 (ashift:DI
2002 (and:DI
2003 (plus:DI
2004 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2005 (const_int 1))
2006 (const_int 7))
2007 (const_int 3)))
2008 (const_int 65535)))]
2009 "WORDS_BIG_ENDIAN"
2010 "extwh %r1,%2,%0"
2011 [(set_attr "type" "shift")])
2013 ;; This converts an extXl into an extXh with an appropriate adjustment
2014 ;; to the address calculation.
2016 ;;(define_split
2017 ;; [(set (match_operand:DI 0 "register_operand" "")
2018 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2019 ;; (match_operand:DI 2 "mode_width_operand" "")
2020 ;; (ashift:DI (match_operand:DI 3 "" "")
2021 ;; (const_int 3)))
2022 ;; (match_operand:DI 4 "const_int_operand" "")))
2023 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2024 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2025 ;; [(set (match_dup 5) (match_dup 6))
2026 ;; (set (match_dup 0)
2027 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2028 ;; (ashift:DI (plus:DI (match_dup 5)
2029 ;; (match_dup 7))
2030 ;; (const_int 3)))
2031 ;; (match_dup 4)))]
2032 ;; "
2033 ;;{
2034 ;; operands[6] = plus_constant (operands[3],
2035 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2036 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2037 ;;}")
2039 (define_insn "*insbl_const"
2040 [(set (match_operand:DI 0 "register_operand" "=r")
2041 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2042 (match_operand:DI 2 "mul8_operand" "I")))]
2043 ""
2044 "insbl %1,%s2,%0"
2045 [(set_attr "type" "shift")])
2047 (define_insn "inswl_const"
2048 [(set (match_operand:DI 0 "register_operand" "=r")
2049 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2050 (match_operand:DI 2 "mul8_operand" "I")))]
2051 ""
2052 "inswl %1,%s2,%0"
2053 [(set_attr "type" "shift")])
2055 (define_insn "*insll_const"
2056 [(set (match_operand:DI 0 "register_operand" "=r")
2057 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2058 (match_operand:DI 2 "mul8_operand" "I")))]
2059 ""
2060 "insll %1,%s2,%0"
2061 [(set_attr "type" "shift")])
2063 (define_insn "insbl_le"
2064 [(set (match_operand:DI 0 "register_operand" "=r")
2065 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2066 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2067 (const_int 3))))]
2068 "! WORDS_BIG_ENDIAN"
2069 "insbl %1,%2,%0"
2070 [(set_attr "type" "shift")])
2072 (define_insn "insbl_be"
2073 [(set (match_operand:DI 0 "register_operand" "=r")
2074 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2075 (minus:DI (const_int 56)
2076 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2077 (const_int 3)))))]
2078 "WORDS_BIG_ENDIAN"
2079 "insbl %1,%2,%0"
2080 [(set_attr "type" "shift")])
2082 (define_insn "inswl_le"
2083 [(set (match_operand:DI 0 "register_operand" "=r")
2084 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2085 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2086 (const_int 3))))]
2087 "! WORDS_BIG_ENDIAN"
2088 "inswl %1,%2,%0"
2089 [(set_attr "type" "shift")])
2091 (define_insn "inswl_be"
2092 [(set (match_operand:DI 0 "register_operand" "=r")
2093 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2094 (minus:DI (const_int 56)
2095 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2096 (const_int 3)))))]
2097 "WORDS_BIG_ENDIAN"
2098 "inswl %1,%2,%0"
2099 [(set_attr "type" "shift")])
2101 (define_insn "insll_le"
2102 [(set (match_operand:DI 0 "register_operand" "=r")
2103 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2104 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2105 (const_int 3))))]
2106 "! WORDS_BIG_ENDIAN"
2107 "insll %1,%2,%0"
2108 [(set_attr "type" "shift")])
2110 (define_insn "insll_be"
2111 [(set (match_operand:DI 0 "register_operand" "=r")
2112 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2113 (minus:DI (const_int 56)
2114 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2115 (const_int 3)))))]
2116 "WORDS_BIG_ENDIAN"
2117 "insll %1,%2,%0"
2118 [(set_attr "type" "shift")])
2120 (define_insn "insql_le"
2121 [(set (match_operand:DI 0 "register_operand" "=r")
2122 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2123 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2124 (const_int 3))))]
2125 "! WORDS_BIG_ENDIAN"
2126 "insql %1,%2,%0"
2127 [(set_attr "type" "shift")])
2129 (define_insn "insql_be"
2130 [(set (match_operand:DI 0 "register_operand" "=r")
2131 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2132 (minus:DI (const_int 56)
2133 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2134 (const_int 3)))))]
2135 "WORDS_BIG_ENDIAN"
2136 "insql %1,%2,%0"
2137 [(set_attr "type" "shift")])
2139 ;; Combine has this sometimes habit of moving the and outside of the
2140 ;; shift, making life more interesting.
2142 (define_insn "*insxl"
2143 [(set (match_operand:DI 0 "register_operand" "=r")
2144 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2145 (match_operand:DI 2 "mul8_operand" "I"))
2146 (match_operand:DI 3 "immediate_operand" "i")))]
2147 "HOST_BITS_PER_WIDE_INT == 64
2148 && GET_CODE (operands[3]) == CONST_INT
2149 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2150 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2151 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2152 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2153 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2154 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2155 {
2156 #if HOST_BITS_PER_WIDE_INT == 64
2157 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2158 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2159 return "insbl %1,%s2,%0";
2160 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2161 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2162 return "inswl %1,%s2,%0";
2163 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2164 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2165 return "insll %1,%s2,%0";
2166 #endif
2167 gcc_unreachable ();
2168 }
2169 [(set_attr "type" "shift")])
2171 ;; We do not include the insXh insns because they are complex to express
2172 ;; and it does not appear that we would ever want to generate them.
2173 ;;
2174 ;; Since we need them for block moves, though, cop out and use unspec.
2176 (define_insn "insxh"
2177 [(set (match_operand:DI 0 "register_operand" "=r")
2178 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2179 (match_operand:DI 2 "mode_width_operand" "n")
2180 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2181 UNSPEC_INSXH))]
2182 ""
2183 "ins%M2h %1,%3,%0"
2184 [(set_attr "type" "shift")])
2186 (define_insn "mskxl_le"
2187 [(set (match_operand:DI 0 "register_operand" "=r")
2188 (and:DI (not:DI (ashift:DI
2189 (match_operand:DI 2 "mode_mask_operand" "n")
2190 (ashift:DI
2191 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2192 (const_int 3))))
2193 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2194 "! WORDS_BIG_ENDIAN"
2195 "msk%U2l %r1,%3,%0"
2196 [(set_attr "type" "shift")])
2198 (define_insn "mskxl_be"
2199 [(set (match_operand:DI 0 "register_operand" "=r")
2200 (and:DI (not:DI (ashift:DI
2201 (match_operand:DI 2 "mode_mask_operand" "n")
2202 (minus:DI (const_int 56)
2203 (ashift:DI
2204 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2205 (const_int 3)))))
2206 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2207 "WORDS_BIG_ENDIAN"
2208 "msk%U2l %r1,%3,%0"
2209 [(set_attr "type" "shift")])
2211 ;; We do not include the mskXh insns because it does not appear we would
2212 ;; ever generate one.
2213 ;;
2214 ;; Again, we do for block moves and we use unspec again.
2216 (define_insn "mskxh"
2217 [(set (match_operand:DI 0 "register_operand" "=r")
2218 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2219 (match_operand:DI 2 "mode_width_operand" "n")
2220 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2221 UNSPEC_MSKXH))]
2222 ""
2223 "msk%M2h %1,%3,%0"
2224 [(set_attr "type" "shift")])
2226 ;; Prefer AND + NE over LSHIFTRT + AND.
2228 (define_insn_and_split "*ze_and_ne"
2229 [(set (match_operand:DI 0 "register_operand" "=r")
2230 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2231 (const_int 1)
2232 (match_operand 2 "const_int_operand" "I")))]
2233 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2234 "#"
2235 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2236 [(set (match_dup 0)
2237 (and:DI (match_dup 1) (match_dup 3)))
2238 (set (match_dup 0)
2239 (ne:DI (match_dup 0) (const_int 0)))]
2240 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2241 \f
2242 ;; Floating-point operations. All the double-precision insns can extend
2243 ;; from single, so indicate that. The exception are the ones that simply
2244 ;; play with the sign bits; it's not clear what to do there.
2246 (define_insn "abssf2"
2247 [(set (match_operand:SF 0 "register_operand" "=f")
2248 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2249 "TARGET_FP"
2250 "cpys $f31,%R1,%0"
2251 [(set_attr "type" "fcpys")])
2253 (define_insn "*nabssf2"
2254 [(set (match_operand:SF 0 "register_operand" "=f")
2255 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2256 "TARGET_FP"
2257 "cpysn $f31,%R1,%0"
2258 [(set_attr "type" "fadd")])
2260 (define_insn "absdf2"
2261 [(set (match_operand:DF 0 "register_operand" "=f")
2262 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2263 "TARGET_FP"
2264 "cpys $f31,%R1,%0"
2265 [(set_attr "type" "fcpys")])
2267 (define_insn "*nabsdf2"
2268 [(set (match_operand:DF 0 "register_operand" "=f")
2269 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2270 "TARGET_FP"
2271 "cpysn $f31,%R1,%0"
2272 [(set_attr "type" "fadd")])
2274 (define_expand "abstf2"
2275 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2276 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2277 (use (match_dup 2))])]
2278 "TARGET_HAS_XFLOATING_LIBS"
2279 {
2280 #if HOST_BITS_PER_WIDE_INT >= 64
2281 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2282 #else
2283 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2284 #endif
2285 })
2287 (define_insn_and_split "*abstf_internal"
2288 [(set (match_operand:TF 0 "register_operand" "=r")
2289 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2290 (use (match_operand:DI 2 "register_operand" "r"))]
2291 "TARGET_HAS_XFLOATING_LIBS"
2292 "#"
2293 "&& reload_completed"
2294 [(const_int 0)]
2295 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2297 (define_insn "negsf2"
2298 [(set (match_operand:SF 0 "register_operand" "=f")
2299 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2300 "TARGET_FP"
2301 "cpysn %R1,%R1,%0"
2302 [(set_attr "type" "fadd")])
2304 (define_insn "negdf2"
2305 [(set (match_operand:DF 0 "register_operand" "=f")
2306 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2307 "TARGET_FP"
2308 "cpysn %R1,%R1,%0"
2309 [(set_attr "type" "fadd")])
2311 (define_expand "negtf2"
2312 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2313 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2314 (use (match_dup 2))])]
2315 "TARGET_HAS_XFLOATING_LIBS"
2316 {
2317 #if HOST_BITS_PER_WIDE_INT >= 64
2318 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2319 #else
2320 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2321 #endif
2322 })
2324 (define_insn_and_split "*negtf_internal"
2325 [(set (match_operand:TF 0 "register_operand" "=r")
2326 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2327 (use (match_operand:DI 2 "register_operand" "r"))]
2328 "TARGET_HAS_XFLOATING_LIBS"
2329 "#"
2330 "&& reload_completed"
2331 [(const_int 0)]
2332 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2334 (define_insn "copysignsf3"
2335 [(set (match_operand:SF 0 "register_operand" "=f")
2336 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2337 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2338 UNSPEC_COPYSIGN))]
2339 "TARGET_FP"
2340 "cpys %R2,%R1,%0"
2341 [(set_attr "type" "fadd")])
2343 (define_insn "*ncopysignsf3"
2344 [(set (match_operand:SF 0 "register_operand" "=f")
2345 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2346 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2347 UNSPEC_COPYSIGN)))]
2348 "TARGET_FP"
2349 "cpysn %R2,%R1,%0"
2350 [(set_attr "type" "fadd")])
2352 (define_insn "copysigndf3"
2353 [(set (match_operand:DF 0 "register_operand" "=f")
2354 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2355 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2356 UNSPEC_COPYSIGN))]
2357 "TARGET_FP"
2358 "cpys %R2,%R1,%0"
2359 [(set_attr "type" "fadd")])
2361 (define_insn "*ncopysigndf3"
2362 [(set (match_operand:DF 0 "register_operand" "=f")
2363 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2364 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2365 UNSPEC_COPYSIGN)))]
2366 "TARGET_FP"
2367 "cpysn %R2,%R1,%0"
2368 [(set_attr "type" "fadd")])
2370 (define_insn "*addsf_ieee"
2371 [(set (match_operand:SF 0 "register_operand" "=&f")
2372 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2373 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2374 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2375 "add%,%/ %R1,%R2,%0"
2376 [(set_attr "type" "fadd")
2377 (set_attr "trap" "yes")
2378 (set_attr "round_suffix" "normal")
2379 (set_attr "trap_suffix" "u_su_sui")])
2381 (define_insn "addsf3"
2382 [(set (match_operand:SF 0 "register_operand" "=f")
2383 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2384 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2385 "TARGET_FP"
2386 "add%,%/ %R1,%R2,%0"
2387 [(set_attr "type" "fadd")
2388 (set_attr "trap" "yes")
2389 (set_attr "round_suffix" "normal")
2390 (set_attr "trap_suffix" "u_su_sui")])
2392 (define_insn "*adddf_ieee"
2393 [(set (match_operand:DF 0 "register_operand" "=&f")
2394 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2395 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2396 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2397 "add%-%/ %R1,%R2,%0"
2398 [(set_attr "type" "fadd")
2399 (set_attr "trap" "yes")
2400 (set_attr "round_suffix" "normal")
2401 (set_attr "trap_suffix" "u_su_sui")])
2403 (define_insn "adddf3"
2404 [(set (match_operand:DF 0 "register_operand" "=f")
2405 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2406 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2407 "TARGET_FP"
2408 "add%-%/ %R1,%R2,%0"
2409 [(set_attr "type" "fadd")
2410 (set_attr "trap" "yes")
2411 (set_attr "round_suffix" "normal")
2412 (set_attr "trap_suffix" "u_su_sui")])
2414 (define_insn "*adddf_ext1"
2415 [(set (match_operand:DF 0 "register_operand" "=f")
2416 (plus:DF (float_extend:DF
2417 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2418 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2419 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2420 "add%-%/ %R1,%R2,%0"
2421 [(set_attr "type" "fadd")
2422 (set_attr "trap" "yes")
2423 (set_attr "round_suffix" "normal")
2424 (set_attr "trap_suffix" "u_su_sui")])
2426 (define_insn "*adddf_ext2"
2427 [(set (match_operand:DF 0 "register_operand" "=f")
2428 (plus:DF (float_extend:DF
2429 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2430 (float_extend:DF
2431 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2432 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2433 "add%-%/ %R1,%R2,%0"
2434 [(set_attr "type" "fadd")
2435 (set_attr "trap" "yes")
2436 (set_attr "round_suffix" "normal")
2437 (set_attr "trap_suffix" "u_su_sui")])
2439 (define_expand "addtf3"
2440 [(use (match_operand 0 "register_operand" ""))
2441 (use (match_operand 1 "general_operand" ""))
2442 (use (match_operand 2 "general_operand" ""))]
2443 "TARGET_HAS_XFLOATING_LIBS"
2444 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2446 ;; Define conversion operators between DFmode and SImode, using the cvtql
2447 ;; instruction. To allow combine et al to do useful things, we keep the
2448 ;; operation as a unit until after reload, at which point we split the
2449 ;; instructions.
2450 ;;
2451 ;; Note that we (attempt to) only consider this optimization when the
2452 ;; ultimate destination is memory. If we will be doing further integer
2453 ;; processing, it is cheaper to do the truncation in the int regs.
2455 (define_insn "*cvtql"
2456 [(set (match_operand:SF 0 "register_operand" "=f")
2457 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2458 UNSPEC_CVTQL))]
2459 "TARGET_FP"
2460 "cvtql%/ %R1,%0"
2461 [(set_attr "type" "fadd")
2462 (set_attr "trap" "yes")
2463 (set_attr "trap_suffix" "v_sv")])
2465 (define_insn_and_split "*fix_truncdfsi_ieee"
2466 [(set (match_operand:SI 0 "memory_operand" "=m")
2467 (subreg:SI
2468 (match_operator:DI 4 "fix_operator"
2469 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2470 (clobber (match_scratch:DI 2 "=&f"))
2471 (clobber (match_scratch:SF 3 "=&f"))]
2472 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2473 "#"
2474 "&& reload_completed"
2475 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2476 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2477 (set (match_dup 5) (match_dup 3))]
2478 {
2479 operands[5] = adjust_address (operands[0], SFmode, 0);
2480 }
2481 [(set_attr "type" "fadd")
2482 (set_attr "trap" "yes")])
2484 (define_insn_and_split "*fix_truncdfsi_internal"
2485 [(set (match_operand:SI 0 "memory_operand" "=m")
2486 (subreg:SI
2487 (match_operator:DI 3 "fix_operator"
2488 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2489 (clobber (match_scratch:DI 2 "=f"))]
2490 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2491 "#"
2492 "&& reload_completed"
2493 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2494 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2495 (set (match_dup 5) (match_dup 4))]
2496 {
2497 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2498 operands[5] = adjust_address (operands[0], SFmode, 0);
2499 }
2500 [(set_attr "type" "fadd")
2501 (set_attr "trap" "yes")])
2503 (define_insn "*fix_truncdfdi_ieee"
2504 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2505 (match_operator:DI 2 "fix_operator"
2506 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2507 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2508 "cvt%-q%/ %R1,%0"
2509 [(set_attr "type" "fadd")
2510 (set_attr "trap" "yes")
2511 (set_attr "round_suffix" "c")
2512 (set_attr "trap_suffix" "v_sv_svi")])
2514 (define_insn "*fix_truncdfdi2"
2515 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2516 (match_operator:DI 2 "fix_operator"
2517 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2518 "TARGET_FP"
2519 "cvt%-q%/ %R1,%0"
2520 [(set_attr "type" "fadd")
2521 (set_attr "trap" "yes")
2522 (set_attr "round_suffix" "c")
2523 (set_attr "trap_suffix" "v_sv_svi")])
2525 (define_expand "fix_truncdfdi2"
2526 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2527 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2528 "TARGET_FP"
2529 "")
2531 (define_expand "fixuns_truncdfdi2"
2532 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2533 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2534 "TARGET_FP"
2535 "")
2537 ;; Likewise between SFmode and SImode.
2539 (define_insn_and_split "*fix_truncsfsi_ieee"
2540 [(set (match_operand:SI 0 "memory_operand" "=m")
2541 (subreg:SI
2542 (match_operator:DI 4 "fix_operator"
2543 [(float_extend:DF
2544 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2545 (clobber (match_scratch:DI 2 "=&f"))
2546 (clobber (match_scratch:SF 3 "=&f"))]
2547 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2548 "#"
2549 "&& reload_completed"
2550 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2551 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2552 (set (match_dup 5) (match_dup 3))]
2553 {
2554 operands[5] = adjust_address (operands[0], SFmode, 0);
2555 }
2556 [(set_attr "type" "fadd")
2557 (set_attr "trap" "yes")])
2559 (define_insn_and_split "*fix_truncsfsi_internal"
2560 [(set (match_operand:SI 0 "memory_operand" "=m")
2561 (subreg:SI
2562 (match_operator:DI 3 "fix_operator"
2563 [(float_extend:DF
2564 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2565 (clobber (match_scratch:DI 2 "=f"))]
2566 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2567 "#"
2568 "&& reload_completed"
2569 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2570 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2571 (set (match_dup 5) (match_dup 4))]
2572 {
2573 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2574 operands[5] = adjust_address (operands[0], SFmode, 0);
2575 }
2576 [(set_attr "type" "fadd")
2577 (set_attr "trap" "yes")])
2579 (define_insn "*fix_truncsfdi_ieee"
2580 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2581 (match_operator:DI 2 "fix_operator"
2582 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2583 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2584 "cvt%-q%/ %R1,%0"
2585 [(set_attr "type" "fadd")
2586 (set_attr "trap" "yes")
2587 (set_attr "round_suffix" "c")
2588 (set_attr "trap_suffix" "v_sv_svi")])
2590 (define_insn "*fix_truncsfdi2"
2591 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2592 (match_operator:DI 2 "fix_operator"
2593 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2594 "TARGET_FP"
2595 "cvt%-q%/ %R1,%0"
2596 [(set_attr "type" "fadd")
2597 (set_attr "trap" "yes")
2598 (set_attr "round_suffix" "c")
2599 (set_attr "trap_suffix" "v_sv_svi")])
2601 (define_expand "fix_truncsfdi2"
2602 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2603 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2604 "TARGET_FP"
2605 "")
2607 (define_expand "fixuns_truncsfdi2"
2608 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2609 (unsigned_fix:DI
2610 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2611 "TARGET_FP"
2612 "")
2614 (define_expand "fix_trunctfdi2"
2615 [(use (match_operand:DI 0 "register_operand" ""))
2616 (use (match_operand:TF 1 "general_operand" ""))]
2617 "TARGET_HAS_XFLOATING_LIBS"
2618 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2620 (define_expand "fixuns_trunctfdi2"
2621 [(use (match_operand:DI 0 "register_operand" ""))
2622 (use (match_operand:TF 1 "general_operand" ""))]
2623 "TARGET_HAS_XFLOATING_LIBS"
2624 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2626 (define_insn "*floatdisf_ieee"
2627 [(set (match_operand:SF 0 "register_operand" "=&f")
2628 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2629 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2630 "cvtq%,%/ %1,%0"
2631 [(set_attr "type" "fadd")
2632 (set_attr "trap" "yes")
2633 (set_attr "round_suffix" "normal")
2634 (set_attr "trap_suffix" "sui")])
2636 (define_insn "floatdisf2"
2637 [(set (match_operand:SF 0 "register_operand" "=f")
2638 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2639 "TARGET_FP"
2640 "cvtq%,%/ %1,%0"
2641 [(set_attr "type" "fadd")
2642 (set_attr "trap" "yes")
2643 (set_attr "round_suffix" "normal")
2644 (set_attr "trap_suffix" "sui")])
2646 (define_insn_and_split "*floatsisf2_ieee"
2647 [(set (match_operand:SF 0 "register_operand" "=&f")
2648 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2649 (clobber (match_scratch:DI 2 "=&f"))
2650 (clobber (match_scratch:SF 3 "=&f"))]
2651 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2652 "#"
2653 "&& reload_completed"
2654 [(set (match_dup 3) (match_dup 1))
2655 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2656 (set (match_dup 0) (float:SF (match_dup 2)))]
2657 {
2658 operands[1] = adjust_address (operands[1], SFmode, 0);
2659 })
2661 (define_insn_and_split "*floatsisf2"
2662 [(set (match_operand:SF 0 "register_operand" "=f")
2663 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2664 "TARGET_FP"
2665 "#"
2666 "&& reload_completed"
2667 [(set (match_dup 0) (match_dup 1))
2668 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2669 (set (match_dup 0) (float:SF (match_dup 2)))]
2670 {
2671 operands[1] = adjust_address (operands[1], SFmode, 0);
2672 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2673 })
2675 (define_insn "*floatdidf_ieee"
2676 [(set (match_operand:DF 0 "register_operand" "=&f")
2677 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2678 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2679 "cvtq%-%/ %1,%0"
2680 [(set_attr "type" "fadd")
2681 (set_attr "trap" "yes")
2682 (set_attr "round_suffix" "normal")
2683 (set_attr "trap_suffix" "sui")])
2685 (define_insn "floatdidf2"
2686 [(set (match_operand:DF 0 "register_operand" "=f")
2687 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2688 "TARGET_FP"
2689 "cvtq%-%/ %1,%0"
2690 [(set_attr "type" "fadd")
2691 (set_attr "trap" "yes")
2692 (set_attr "round_suffix" "normal")
2693 (set_attr "trap_suffix" "sui")])
2695 (define_insn_and_split "*floatsidf2_ieee"
2696 [(set (match_operand:DF 0 "register_operand" "=&f")
2697 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2698 (clobber (match_scratch:DI 2 "=&f"))
2699 (clobber (match_scratch:SF 3 "=&f"))]
2700 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2701 "#"
2702 "&& reload_completed"
2703 [(set (match_dup 3) (match_dup 1))
2704 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2705 (set (match_dup 0) (float:DF (match_dup 2)))]
2706 {
2707 operands[1] = adjust_address (operands[1], SFmode, 0);
2708 })
2710 (define_insn_and_split "*floatsidf2"
2711 [(set (match_operand:DF 0 "register_operand" "=f")
2712 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2713 "TARGET_FP"
2714 "#"
2715 "&& reload_completed"
2716 [(set (match_dup 3) (match_dup 1))
2717 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2718 (set (match_dup 0) (float:DF (match_dup 2)))]
2719 {
2720 operands[1] = adjust_address (operands[1], SFmode, 0);
2721 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2722 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2723 })
2725 (define_expand "floatditf2"
2726 [(use (match_operand:TF 0 "register_operand" ""))
2727 (use (match_operand:DI 1 "general_operand" ""))]
2728 "TARGET_HAS_XFLOATING_LIBS"
2729 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2731 (define_expand "floatunsdisf2"
2732 [(use (match_operand:SF 0 "register_operand" ""))
2733 (use (match_operand:DI 1 "register_operand" ""))]
2734 "TARGET_FP"
2735 "alpha_emit_floatuns (operands); DONE;")
2737 (define_expand "floatunsdidf2"
2738 [(use (match_operand:DF 0 "register_operand" ""))
2739 (use (match_operand:DI 1 "register_operand" ""))]
2740 "TARGET_FP"
2741 "alpha_emit_floatuns (operands); DONE;")
2743 (define_expand "floatunsditf2"
2744 [(use (match_operand:TF 0 "register_operand" ""))
2745 (use (match_operand:DI 1 "general_operand" ""))]
2746 "TARGET_HAS_XFLOATING_LIBS"
2747 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2749 (define_expand "extendsfdf2"
2750 [(set (match_operand:DF 0 "register_operand" "")
2751 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2752 "TARGET_FP"
2753 {
2754 if (alpha_fptm >= ALPHA_FPTM_SU)
2755 operands[1] = force_reg (SFmode, operands[1]);
2756 })
2758 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2759 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2761 (define_insn "*extendsfdf2_ieee"
2762 [(set (match_operand:DF 0 "register_operand" "=&f")
2763 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2764 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2765 "cvtsts %1,%0"
2766 [(set_attr "type" "fadd")
2767 (set_attr "trap" "yes")])
2769 (define_insn "*extendsfdf2_internal"
2770 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2771 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2772 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2773 "@
2774 cpys %1,%1,%0
2775 ld%, %0,%1
2776 st%- %1,%0"
2777 [(set_attr "type" "fcpys,fld,fst")])
2779 ;; Use register_operand for operand 1 to prevent compress_float_constant
2780 ;; from doing something silly. When optimizing we'll put things back
2781 ;; together anyway.
2782 (define_expand "extendsftf2"
2783 [(use (match_operand:TF 0 "register_operand" ""))
2784 (use (match_operand:SF 1 "register_operand" ""))]
2785 "TARGET_HAS_XFLOATING_LIBS"
2786 {
2787 rtx tmp = gen_reg_rtx (DFmode);
2788 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2789 emit_insn (gen_extenddftf2 (operands[0], tmp));
2790 DONE;
2791 })
2793 (define_expand "extenddftf2"
2794 [(use (match_operand:TF 0 "register_operand" ""))
2795 (use (match_operand:DF 1 "register_operand" ""))]
2796 "TARGET_HAS_XFLOATING_LIBS"
2797 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2799 (define_insn "*truncdfsf2_ieee"
2800 [(set (match_operand:SF 0 "register_operand" "=&f")
2801 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2802 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2803 "cvt%-%,%/ %R1,%0"
2804 [(set_attr "type" "fadd")
2805 (set_attr "trap" "yes")
2806 (set_attr "round_suffix" "normal")
2807 (set_attr "trap_suffix" "u_su_sui")])
2809 (define_insn "truncdfsf2"
2810 [(set (match_operand:SF 0 "register_operand" "=f")
2811 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2812 "TARGET_FP"
2813 "cvt%-%,%/ %R1,%0"
2814 [(set_attr "type" "fadd")
2815 (set_attr "trap" "yes")
2816 (set_attr "round_suffix" "normal")
2817 (set_attr "trap_suffix" "u_su_sui")])
2819 (define_expand "trunctfdf2"
2820 [(use (match_operand:DF 0 "register_operand" ""))
2821 (use (match_operand:TF 1 "general_operand" ""))]
2822 "TARGET_HAS_XFLOATING_LIBS"
2823 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2825 (define_expand "trunctfsf2"
2826 [(use (match_operand:SF 0 "register_operand" ""))
2827 (use (match_operand:TF 1 "general_operand" ""))]
2828 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2829 {
2830 rtx tmpf, sticky, arg, lo, hi;
2832 tmpf = gen_reg_rtx (DFmode);
2833 sticky = gen_reg_rtx (DImode);
2834 arg = copy_to_mode_reg (TFmode, operands[1]);
2835 lo = gen_lowpart (DImode, arg);
2836 hi = gen_highpart (DImode, arg);
2838 /* Convert the low word of the TFmode value into a sticky rounding bit,
2839 then or it into the low bit of the high word. This leaves the sticky
2840 bit at bit 48 of the fraction, which is representable in DFmode,
2841 which prevents rounding error in the final conversion to SFmode. */
2843 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2844 gen_rtx_NE (DImode, lo, const0_rtx)));
2845 emit_insn (gen_iordi3 (hi, hi, sticky));
2846 emit_insn (gen_trunctfdf2 (tmpf, arg));
2847 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2848 DONE;
2849 })
2851 (define_insn "*divsf3_ieee"
2852 [(set (match_operand:SF 0 "register_operand" "=&f")
2853 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2854 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2855 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2856 "div%,%/ %R1,%R2,%0"
2857 [(set_attr "type" "fdiv")
2858 (set_attr "opsize" "si")
2859 (set_attr "trap" "yes")
2860 (set_attr "round_suffix" "normal")
2861 (set_attr "trap_suffix" "u_su_sui")])
2863 (define_insn "divsf3"
2864 [(set (match_operand:SF 0 "register_operand" "=f")
2865 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2866 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2867 "TARGET_FP"
2868 "div%,%/ %R1,%R2,%0"
2869 [(set_attr "type" "fdiv")
2870 (set_attr "opsize" "si")
2871 (set_attr "trap" "yes")
2872 (set_attr "round_suffix" "normal")
2873 (set_attr "trap_suffix" "u_su_sui")])
2875 (define_insn "*divdf3_ieee"
2876 [(set (match_operand:DF 0 "register_operand" "=&f")
2877 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2878 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2879 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2880 "div%-%/ %R1,%R2,%0"
2881 [(set_attr "type" "fdiv")
2882 (set_attr "trap" "yes")
2883 (set_attr "round_suffix" "normal")
2884 (set_attr "trap_suffix" "u_su_sui")])
2886 (define_insn "divdf3"
2887 [(set (match_operand:DF 0 "register_operand" "=f")
2888 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2889 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2890 "TARGET_FP"
2891 "div%-%/ %R1,%R2,%0"
2892 [(set_attr "type" "fdiv")
2893 (set_attr "trap" "yes")
2894 (set_attr "round_suffix" "normal")
2895 (set_attr "trap_suffix" "u_su_sui")])
2897 (define_insn "*divdf_ext1"
2898 [(set (match_operand:DF 0 "register_operand" "=f")
2899 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2900 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2901 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2902 "div%-%/ %R1,%R2,%0"
2903 [(set_attr "type" "fdiv")
2904 (set_attr "trap" "yes")
2905 (set_attr "round_suffix" "normal")
2906 (set_attr "trap_suffix" "u_su_sui")])
2908 (define_insn "*divdf_ext2"
2909 [(set (match_operand:DF 0 "register_operand" "=f")
2910 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2911 (float_extend:DF
2912 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2913 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2914 "div%-%/ %R1,%R2,%0"
2915 [(set_attr "type" "fdiv")
2916 (set_attr "trap" "yes")
2917 (set_attr "round_suffix" "normal")
2918 (set_attr "trap_suffix" "u_su_sui")])
2920 (define_insn "*divdf_ext3"
2921 [(set (match_operand:DF 0 "register_operand" "=f")
2922 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2923 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2924 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2925 "div%-%/ %R1,%R2,%0"
2926 [(set_attr "type" "fdiv")
2927 (set_attr "trap" "yes")
2928 (set_attr "round_suffix" "normal")
2929 (set_attr "trap_suffix" "u_su_sui")])
2931 (define_expand "divtf3"
2932 [(use (match_operand 0 "register_operand" ""))
2933 (use (match_operand 1 "general_operand" ""))
2934 (use (match_operand 2 "general_operand" ""))]
2935 "TARGET_HAS_XFLOATING_LIBS"
2936 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2938 (define_insn "*mulsf3_ieee"
2939 [(set (match_operand:SF 0 "register_operand" "=&f")
2940 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2941 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2942 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2943 "mul%,%/ %R1,%R2,%0"
2944 [(set_attr "type" "fmul")
2945 (set_attr "trap" "yes")
2946 (set_attr "round_suffix" "normal")
2947 (set_attr "trap_suffix" "u_su_sui")])
2949 (define_insn "mulsf3"
2950 [(set (match_operand:SF 0 "register_operand" "=f")
2951 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2952 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2953 "TARGET_FP"
2954 "mul%,%/ %R1,%R2,%0"
2955 [(set_attr "type" "fmul")
2956 (set_attr "trap" "yes")
2957 (set_attr "round_suffix" "normal")
2958 (set_attr "trap_suffix" "u_su_sui")])
2960 (define_insn "*muldf3_ieee"
2961 [(set (match_operand:DF 0 "register_operand" "=&f")
2962 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2963 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2964 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2965 "mul%-%/ %R1,%R2,%0"
2966 [(set_attr "type" "fmul")
2967 (set_attr "trap" "yes")
2968 (set_attr "round_suffix" "normal")
2969 (set_attr "trap_suffix" "u_su_sui")])
2971 (define_insn "muldf3"
2972 [(set (match_operand:DF 0 "register_operand" "=f")
2973 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2974 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2975 "TARGET_FP"
2976 "mul%-%/ %R1,%R2,%0"
2977 [(set_attr "type" "fmul")
2978 (set_attr "trap" "yes")
2979 (set_attr "round_suffix" "normal")
2980 (set_attr "trap_suffix" "u_su_sui")])
2982 (define_insn "*muldf_ext1"
2983 [(set (match_operand:DF 0 "register_operand" "=f")
2984 (mult:DF (float_extend:DF
2985 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2986 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2987 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2988 "mul%-%/ %R1,%R2,%0"
2989 [(set_attr "type" "fmul")
2990 (set_attr "trap" "yes")
2991 (set_attr "round_suffix" "normal")
2992 (set_attr "trap_suffix" "u_su_sui")])
2994 (define_insn "*muldf_ext2"
2995 [(set (match_operand:DF 0 "register_operand" "=f")
2996 (mult:DF (float_extend:DF
2997 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2998 (float_extend:DF
2999 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3000 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3001 "mul%-%/ %R1,%R2,%0"
3002 [(set_attr "type" "fmul")
3003 (set_attr "trap" "yes")
3004 (set_attr "round_suffix" "normal")
3005 (set_attr "trap_suffix" "u_su_sui")])
3007 (define_expand "multf3"
3008 [(use (match_operand 0 "register_operand" ""))
3009 (use (match_operand 1 "general_operand" ""))
3010 (use (match_operand 2 "general_operand" ""))]
3011 "TARGET_HAS_XFLOATING_LIBS"
3012 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
3014 (define_insn "*subsf3_ieee"
3015 [(set (match_operand:SF 0 "register_operand" "=&f")
3016 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
3017 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
3018 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3019 "sub%,%/ %R1,%R2,%0"
3020 [(set_attr "type" "fadd")
3021 (set_attr "trap" "yes")
3022 (set_attr "round_suffix" "normal")
3023 (set_attr "trap_suffix" "u_su_sui")])
3025 (define_insn "subsf3"
3026 [(set (match_operand:SF 0 "register_operand" "=f")
3027 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
3028 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
3029 "TARGET_FP"
3030 "sub%,%/ %R1,%R2,%0"
3031 [(set_attr "type" "fadd")
3032 (set_attr "trap" "yes")
3033 (set_attr "round_suffix" "normal")
3034 (set_attr "trap_suffix" "u_su_sui")])
3036 (define_insn "*subdf3_ieee"
3037 [(set (match_operand:DF 0 "register_operand" "=&f")
3038 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3039 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3040 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3041 "sub%-%/ %R1,%R2,%0"
3042 [(set_attr "type" "fadd")
3043 (set_attr "trap" "yes")
3044 (set_attr "round_suffix" "normal")
3045 (set_attr "trap_suffix" "u_su_sui")])
3047 (define_insn "subdf3"
3048 [(set (match_operand:DF 0 "register_operand" "=f")
3049 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3050 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3051 "TARGET_FP"
3052 "sub%-%/ %R1,%R2,%0"
3053 [(set_attr "type" "fadd")
3054 (set_attr "trap" "yes")
3055 (set_attr "round_suffix" "normal")
3056 (set_attr "trap_suffix" "u_su_sui")])
3058 (define_insn "*subdf_ext1"
3059 [(set (match_operand:DF 0 "register_operand" "=f")
3060 (minus:DF (float_extend:DF
3061 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3062 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3063 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3064 "sub%-%/ %R1,%R2,%0"
3065 [(set_attr "type" "fadd")
3066 (set_attr "trap" "yes")
3067 (set_attr "round_suffix" "normal")
3068 (set_attr "trap_suffix" "u_su_sui")])
3070 (define_insn "*subdf_ext2"
3071 [(set (match_operand:DF 0 "register_operand" "=f")
3072 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3073 (float_extend:DF
3074 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3075 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3076 "sub%-%/ %R1,%R2,%0"
3077 [(set_attr "type" "fadd")
3078 (set_attr "trap" "yes")
3079 (set_attr "round_suffix" "normal")
3080 (set_attr "trap_suffix" "u_su_sui")])
3082 (define_insn "*subdf_ext3"
3083 [(set (match_operand:DF 0 "register_operand" "=f")
3084 (minus:DF (float_extend:DF
3085 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3086 (float_extend:DF
3087 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3088 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3089 "sub%-%/ %R1,%R2,%0"
3090 [(set_attr "type" "fadd")
3091 (set_attr "trap" "yes")
3092 (set_attr "round_suffix" "normal")
3093 (set_attr "trap_suffix" "u_su_sui")])
3095 (define_expand "subtf3"
3096 [(use (match_operand 0 "register_operand" ""))
3097 (use (match_operand 1 "general_operand" ""))
3098 (use (match_operand 2 "general_operand" ""))]
3099 "TARGET_HAS_XFLOATING_LIBS"
3100 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3102 (define_insn "*sqrtsf2_ieee"
3103 [(set (match_operand:SF 0 "register_operand" "=&f")
3104 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3105 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3106 "sqrt%,%/ %R1,%0"
3107 [(set_attr "type" "fsqrt")
3108 (set_attr "opsize" "si")
3109 (set_attr "trap" "yes")
3110 (set_attr "round_suffix" "normal")
3111 (set_attr "trap_suffix" "u_su_sui")])
3113 (define_insn "sqrtsf2"
3114 [(set (match_operand:SF 0 "register_operand" "=f")
3115 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3116 "TARGET_FP && TARGET_FIX"
3117 "sqrt%,%/ %R1,%0"
3118 [(set_attr "type" "fsqrt")
3119 (set_attr "opsize" "si")
3120 (set_attr "trap" "yes")
3121 (set_attr "round_suffix" "normal")
3122 (set_attr "trap_suffix" "u_su_sui")])
3124 (define_insn "*sqrtdf2_ieee"
3125 [(set (match_operand:DF 0 "register_operand" "=&f")
3126 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3127 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3128 "sqrt%-%/ %R1,%0"
3129 [(set_attr "type" "fsqrt")
3130 (set_attr "trap" "yes")
3131 (set_attr "round_suffix" "normal")
3132 (set_attr "trap_suffix" "u_su_sui")])
3134 (define_insn "sqrtdf2"
3135 [(set (match_operand:DF 0 "register_operand" "=f")
3136 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3137 "TARGET_FP && TARGET_FIX"
3138 "sqrt%-%/ %R1,%0"
3139 [(set_attr "type" "fsqrt")
3140 (set_attr "trap" "yes")
3141 (set_attr "round_suffix" "normal")
3142 (set_attr "trap_suffix" "u_su_sui")])
3143 \f
3144 ;; Next are all the integer comparisons, and conditional moves and branches
3145 ;; and some of the related define_expand's and define_split's.
3147 (define_insn "*setcc_internal"
3148 [(set (match_operand 0 "register_operand" "=r")
3149 (match_operator 1 "alpha_comparison_operator"
3150 [(match_operand:DI 2 "register_operand" "r")
3151 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3152 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3153 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3154 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3155 "cmp%C1 %2,%3,%0"
3156 [(set_attr "type" "icmp")])
3158 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3159 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3160 ;; from cse on.
3161 (define_insn "*setcc_swapped_internal"
3162 [(set (match_operand 0 "register_operand" "=r")
3163 (match_operator 1 "alpha_swapped_comparison_operator"
3164 [(match_operand:DI 2 "register_operand" "r")
3165 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3166 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3167 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3168 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3169 "cmp%c1 %r3,%2,%0"
3170 [(set_attr "type" "icmp")])
3172 ;; Use match_operator rather than ne directly so that we can match
3173 ;; multiple integer modes.
3174 (define_insn "*setne_internal"
3175 [(set (match_operand 0 "register_operand" "=r")
3176 (match_operator 1 "signed_comparison_operator"
3177 [(match_operand:DI 2 "register_operand" "r")
3178 (const_int 0)]))]
3179 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3180 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3181 && GET_CODE (operands[1]) == NE
3182 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3183 "cmpult $31,%2,%0"
3184 [(set_attr "type" "icmp")])
3186 ;; The mode folding trick can't be used with const_int operands, since
3187 ;; reload needs to know the proper mode.
3188 ;;
3189 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3190 ;; in order to create more pairs of constants. As long as we're allowing
3191 ;; two constants at the same time, and will have to reload one of them...
3193 (define_insn "*movqicc_internal"
3194 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3195 (if_then_else:QI
3196 (match_operator 2 "signed_comparison_operator"
3197 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3198 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3199 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3200 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3201 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3202 "@
3203 cmov%C2 %r3,%1,%0
3204 cmov%D2 %r3,%5,%0
3205 cmov%c2 %r4,%1,%0
3206 cmov%d2 %r4,%5,%0"
3207 [(set_attr "type" "icmov")])
3209 (define_insn "*movhicc_internal"
3210 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3211 (if_then_else:HI
3212 (match_operator 2 "signed_comparison_operator"
3213 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3214 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3215 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3216 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3217 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3218 "@
3219 cmov%C2 %r3,%1,%0
3220 cmov%D2 %r3,%5,%0
3221 cmov%c2 %r4,%1,%0
3222 cmov%d2 %r4,%5,%0"
3223 [(set_attr "type" "icmov")])
3225 (define_insn "*movsicc_internal"
3226 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3227 (if_then_else:SI
3228 (match_operator 2 "signed_comparison_operator"
3229 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3230 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3231 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3232 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3233 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3234 "@
3235 cmov%C2 %r3,%1,%0
3236 cmov%D2 %r3,%5,%0
3237 cmov%c2 %r4,%1,%0
3238 cmov%d2 %r4,%5,%0"
3239 [(set_attr "type" "icmov")])
3241 (define_insn "*movdicc_internal"
3242 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3243 (if_then_else:DI
3244 (match_operator 2 "signed_comparison_operator"
3245 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3246 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3247 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3248 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3249 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3250 "@
3251 cmov%C2 %r3,%1,%0
3252 cmov%D2 %r3,%5,%0
3253 cmov%c2 %r4,%1,%0
3254 cmov%d2 %r4,%5,%0"
3255 [(set_attr "type" "icmov")])
3257 (define_insn "*movqicc_lbc"
3258 [(set (match_operand:QI 0 "register_operand" "=r,r")
3259 (if_then_else:QI
3260 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3261 (const_int 1)
3262 (const_int 0))
3263 (const_int 0))
3264 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3265 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3266 ""
3267 "@
3268 cmovlbc %r2,%1,%0
3269 cmovlbs %r2,%3,%0"
3270 [(set_attr "type" "icmov")])
3272 (define_insn "*movhicc_lbc"
3273 [(set (match_operand:HI 0 "register_operand" "=r,r")
3274 (if_then_else:HI
3275 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3276 (const_int 1)
3277 (const_int 0))
3278 (const_int 0))
3279 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3280 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3281 ""
3282 "@
3283 cmovlbc %r2,%1,%0
3284 cmovlbs %r2,%3,%0"
3285 [(set_attr "type" "icmov")])
3287 (define_insn "*movsicc_lbc"
3288 [(set (match_operand:SI 0 "register_operand" "=r,r")
3289 (if_then_else:SI
3290 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3291 (const_int 1)
3292 (const_int 0))
3293 (const_int 0))
3294 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3295 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3296 ""
3297 "@
3298 cmovlbc %r2,%1,%0
3299 cmovlbs %r2,%3,%0"
3300 [(set_attr "type" "icmov")])
3302 (define_insn "*movdicc_lbc"
3303 [(set (match_operand:DI 0 "register_operand" "=r,r")
3304 (if_then_else:DI
3305 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3306 (const_int 1)
3307 (const_int 0))
3308 (const_int 0))
3309 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3310 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3311 ""
3312 "@
3313 cmovlbc %r2,%1,%0
3314 cmovlbs %r2,%3,%0"
3315 [(set_attr "type" "icmov")])
3317 (define_insn "*movqicc_lbs"
3318 [(set (match_operand:QI 0 "register_operand" "=r,r")
3319 (if_then_else:QI
3320 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3321 (const_int 1)
3322 (const_int 0))
3323 (const_int 0))
3324 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3325 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3326 ""
3327 "@
3328 cmovlbs %r2,%1,%0
3329 cmovlbc %r2,%3,%0"
3330 [(set_attr "type" "icmov")])
3332 (define_insn "*movhicc_lbs"
3333 [(set (match_operand:HI 0 "register_operand" "=r,r")
3334 (if_then_else:HI
3335 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3336 (const_int 1)
3337 (const_int 0))
3338 (const_int 0))
3339 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3340 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3341 ""
3342 "@
3343 cmovlbs %r2,%1,%0
3344 cmovlbc %r2,%3,%0"
3345 [(set_attr "type" "icmov")])
3347 (define_insn "*movsicc_lbs"
3348 [(set (match_operand:SI 0 "register_operand" "=r,r")
3349 (if_then_else:SI
3350 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3351 (const_int 1)
3352 (const_int 0))
3353 (const_int 0))
3354 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3355 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3356 ""
3357 "@
3358 cmovlbs %r2,%1,%0
3359 cmovlbc %r2,%3,%0"
3360 [(set_attr "type" "icmov")])
3362 (define_insn "*movdicc_lbs"
3363 [(set (match_operand:DI 0 "register_operand" "=r,r")
3364 (if_then_else:DI
3365 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3366 (const_int 1)
3367 (const_int 0))
3368 (const_int 0))
3369 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3370 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3371 ""
3372 "@
3373 cmovlbs %r2,%1,%0
3374 cmovlbc %r2,%3,%0"
3375 [(set_attr "type" "icmov")])
3377 ;; For ABS, we have two choices, depending on whether the input and output
3378 ;; registers are the same or not.
3379 (define_expand "absdi2"
3380 [(set (match_operand:DI 0 "register_operand" "")
3381 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3382 ""
3383 {
3384 if (rtx_equal_p (operands[0], operands[1]))
3385 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3386 else
3387 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3388 DONE;
3389 })
3391 (define_expand "absdi2_same"
3392 [(set (match_operand:DI 1 "register_operand" "")
3393 (neg:DI (match_operand:DI 0 "register_operand" "")))
3394 (set (match_dup 0)
3395 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3396 (match_dup 0)
3397 (match_dup 1)))]
3398 ""
3399 "")
3401 (define_expand "absdi2_diff"
3402 [(set (match_operand:DI 0 "register_operand" "")
3403 (neg:DI (match_operand:DI 1 "register_operand" "")))
3404 (set (match_dup 0)
3405 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3406 (match_dup 0)
3407 (match_dup 1)))]
3408 ""
3409 "")
3411 (define_split
3412 [(set (match_operand:DI 0 "register_operand" "")
3413 (abs:DI (match_dup 0)))
3414 (clobber (match_operand:DI 1 "register_operand" ""))]
3415 ""
3416 [(set (match_dup 1) (neg:DI (match_dup 0)))
3417 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3418 (match_dup 0) (match_dup 1)))]
3419 "")
3421 (define_split
3422 [(set (match_operand:DI 0 "register_operand" "")
3423 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3424 "! rtx_equal_p (operands[0], operands[1])"
3425 [(set (match_dup 0) (neg:DI (match_dup 1)))
3426 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3427 (match_dup 0) (match_dup 1)))]
3428 "")
3430 (define_split
3431 [(set (match_operand:DI 0 "register_operand" "")
3432 (neg:DI (abs:DI (match_dup 0))))
3433 (clobber (match_operand:DI 1 "register_operand" ""))]
3434 ""
3435 [(set (match_dup 1) (neg:DI (match_dup 0)))
3436 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3437 (match_dup 0) (match_dup 1)))]
3438 "")
3440 (define_split
3441 [(set (match_operand:DI 0 "register_operand" "")
3442 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3443 "! rtx_equal_p (operands[0], operands[1])"
3444 [(set (match_dup 0) (neg:DI (match_dup 1)))
3445 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3446 (match_dup 0) (match_dup 1)))]
3447 "")
3449 (define_insn "sminqi3"
3450 [(set (match_operand:QI 0 "register_operand" "=r")
3451 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3452 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3453 "TARGET_MAX"
3454 "minsb8 %r1,%2,%0"
3455 [(set_attr "type" "mvi")])
3457 (define_insn "uminqi3"
3458 [(set (match_operand:QI 0 "register_operand" "=r")
3459 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3460 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3461 "TARGET_MAX"
3462 "minub8 %r1,%2,%0"
3463 [(set_attr "type" "mvi")])
3465 (define_insn "smaxqi3"
3466 [(set (match_operand:QI 0 "register_operand" "=r")
3467 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3468 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3469 "TARGET_MAX"
3470 "maxsb8 %r1,%2,%0"
3471 [(set_attr "type" "mvi")])
3473 (define_insn "umaxqi3"
3474 [(set (match_operand:QI 0 "register_operand" "=r")
3475 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3476 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3477 "TARGET_MAX"
3478 "maxub8 %r1,%2,%0"
3479 [(set_attr "type" "mvi")])
3481 (define_insn "sminhi3"
3482 [(set (match_operand:HI 0 "register_operand" "=r")
3483 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3484 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3485 "TARGET_MAX"
3486 "minsw4 %r1,%2,%0"
3487 [(set_attr "type" "mvi")])
3489 (define_insn "uminhi3"
3490 [(set (match_operand:HI 0 "register_operand" "=r")
3491 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3492 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3493 "TARGET_MAX"
3494 "minuw4 %r1,%2,%0"
3495 [(set_attr "type" "mvi")])
3497 (define_insn "smaxhi3"
3498 [(set (match_operand:HI 0 "register_operand" "=r")
3499 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3500 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3501 "TARGET_MAX"
3502 "maxsw4 %r1,%2,%0"
3503 [(set_attr "type" "mvi")])
3505 (define_insn "umaxhi3"
3506 [(set (match_operand:HI 0 "register_operand" "=r")
3507 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3508 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3509 "TARGET_MAX"
3510 "maxuw4 %r1,%2,%0"
3511 [(set_attr "type" "mvi")])
3513 (define_expand "smaxdi3"
3514 [(set (match_dup 3)
3515 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3516 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3517 (set (match_operand:DI 0 "register_operand" "")
3518 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3519 (match_dup 1) (match_dup 2)))]
3520 ""
3521 { operands[3] = gen_reg_rtx (DImode); })
3523 (define_split
3524 [(set (match_operand:DI 0 "register_operand" "")
3525 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3526 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3527 (clobber (match_operand:DI 3 "register_operand" ""))]
3528 "operands[2] != const0_rtx"
3529 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3530 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3531 (match_dup 1) (match_dup 2)))]
3532 "")
3534 (define_insn "*smax_const0"
3535 [(set (match_operand:DI 0 "register_operand" "=r")
3536 (smax:DI (match_operand:DI 1 "register_operand" "0")
3537 (const_int 0)))]
3538 ""
3539 "cmovlt %0,0,%0"
3540 [(set_attr "type" "icmov")])
3542 (define_expand "smindi3"
3543 [(set (match_dup 3)
3544 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3545 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3546 (set (match_operand:DI 0 "register_operand" "")
3547 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3548 (match_dup 1) (match_dup 2)))]
3549 ""
3550 { operands[3] = gen_reg_rtx (DImode); })
3552 (define_split
3553 [(set (match_operand:DI 0 "register_operand" "")
3554 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3555 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3556 (clobber (match_operand:DI 3 "register_operand" ""))]
3557 "operands[2] != const0_rtx"
3558 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3559 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3560 (match_dup 1) (match_dup 2)))]
3561 "")
3563 (define_insn "*smin_const0"
3564 [(set (match_operand:DI 0 "register_operand" "=r")
3565 (smin:DI (match_operand:DI 1 "register_operand" "0")
3566 (const_int 0)))]
3567 ""
3568 "cmovgt %0,0,%0"
3569 [(set_attr "type" "icmov")])
3571 (define_expand "umaxdi3"
3572 [(set (match_dup 3)
3573 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3574 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3575 (set (match_operand:DI 0 "register_operand" "")
3576 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3577 (match_dup 1) (match_dup 2)))]
3578 ""
3579 "operands[3] = gen_reg_rtx (DImode);")
3581 (define_split
3582 [(set (match_operand:DI 0 "register_operand" "")
3583 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3584 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3585 (clobber (match_operand:DI 3 "register_operand" ""))]
3586 "operands[2] != const0_rtx"
3587 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3588 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3589 (match_dup 1) (match_dup 2)))]
3590 "")
3592 (define_expand "umindi3"
3593 [(set (match_dup 3)
3594 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3595 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3596 (set (match_operand:DI 0 "register_operand" "")
3597 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3598 (match_dup 1) (match_dup 2)))]
3599 ""
3600 "operands[3] = gen_reg_rtx (DImode);")
3602 (define_split
3603 [(set (match_operand:DI 0 "register_operand" "")
3604 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3605 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3606 (clobber (match_operand:DI 3 "register_operand" ""))]
3607 "operands[2] != const0_rtx"
3608 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3609 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3610 (match_dup 1) (match_dup 2)))]
3611 "")
3613 (define_insn "*bcc_normal"
3614 [(set (pc)
3615 (if_then_else
3616 (match_operator 1 "signed_comparison_operator"
3617 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3618 (const_int 0)])
3619 (label_ref (match_operand 0 "" ""))
3620 (pc)))]
3621 ""
3622 "b%C1 %r2,%0"
3623 [(set_attr "type" "ibr")])
3625 (define_insn "*bcc_reverse"
3626 [(set (pc)
3627 (if_then_else
3628 (match_operator 1 "signed_comparison_operator"
3629 [(match_operand:DI 2 "register_operand" "r")
3630 (const_int 0)])
3632 (pc)
3633 (label_ref (match_operand 0 "" ""))))]
3634 ""
3635 "b%c1 %2,%0"
3636 [(set_attr "type" "ibr")])
3638 (define_insn "*blbs_normal"
3639 [(set (pc)
3640 (if_then_else
3641 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3642 (const_int 1)
3643 (const_int 0))
3644 (const_int 0))
3645 (label_ref (match_operand 0 "" ""))
3646 (pc)))]
3647 ""
3648 "blbs %r1,%0"
3649 [(set_attr "type" "ibr")])
3651 (define_insn "*blbc_normal"
3652 [(set (pc)
3653 (if_then_else
3654 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3655 (const_int 1)
3656 (const_int 0))
3657 (const_int 0))
3658 (label_ref (match_operand 0 "" ""))
3659 (pc)))]
3660 ""
3661 "blbc %r1,%0"
3662 [(set_attr "type" "ibr")])
3664 (define_split
3665 [(parallel
3666 [(set (pc)
3667 (if_then_else
3668 (match_operator 1 "comparison_operator"
3669 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3670 (const_int 1)
3671 (match_operand:DI 3 "const_int_operand" ""))
3672 (const_int 0)])
3673 (label_ref (match_operand 0 "" ""))
3674 (pc)))
3675 (clobber (match_operand:DI 4 "register_operand" ""))])]
3676 "INTVAL (operands[3]) != 0"
3677 [(set (match_dup 4)
3678 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3679 (set (pc)
3680 (if_then_else (match_op_dup 1
3681 [(zero_extract:DI (match_dup 4)
3682 (const_int 1)
3683 (const_int 0))
3684 (const_int 0)])
3685 (label_ref (match_dup 0))
3686 (pc)))]
3687 "")
3688 \f
3689 ;; The following are the corresponding floating-point insns. Recall
3690 ;; we need to have variants that expand the arguments from SFmode
3691 ;; to DFmode.
3693 (define_insn "*cmpdf_ieee"
3694 [(set (match_operand:DF 0 "register_operand" "=&f")
3695 (match_operator:DF 1 "alpha_fp_comparison_operator"
3696 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3697 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3698 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3699 "cmp%-%C1%/ %R2,%R3,%0"
3700 [(set_attr "type" "fadd")
3701 (set_attr "trap" "yes")
3702 (set_attr "trap_suffix" "su")])
3704 (define_insn "*cmpdf_internal"
3705 [(set (match_operand:DF 0 "register_operand" "=f")
3706 (match_operator:DF 1 "alpha_fp_comparison_operator"
3707 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3708 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3709 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3710 "cmp%-%C1%/ %R2,%R3,%0"
3711 [(set_attr "type" "fadd")
3712 (set_attr "trap" "yes")
3713 (set_attr "trap_suffix" "su")])
3715 (define_insn "*cmpdf_ieee_ext1"
3716 [(set (match_operand:DF 0 "register_operand" "=&f")
3717 (match_operator:DF 1 "alpha_fp_comparison_operator"
3718 [(float_extend:DF
3719 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3720 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3721 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3722 "cmp%-%C1%/ %R2,%R3,%0"
3723 [(set_attr "type" "fadd")
3724 (set_attr "trap" "yes")
3725 (set_attr "trap_suffix" "su")])
3727 (define_insn "*cmpdf_ext1"
3728 [(set (match_operand:DF 0 "register_operand" "=f")
3729 (match_operator:DF 1 "alpha_fp_comparison_operator"
3730 [(float_extend:DF
3731 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3732 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3733 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3734 "cmp%-%C1%/ %R2,%R3,%0"
3735 [(set_attr "type" "fadd")
3736 (set_attr "trap" "yes")
3737 (set_attr "trap_suffix" "su")])
3739 (define_insn "*cmpdf_ieee_ext2"
3740 [(set (match_operand:DF 0 "register_operand" "=&f")
3741 (match_operator:DF 1 "alpha_fp_comparison_operator"
3742 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3743 (float_extend:DF
3744 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3745 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3746 "cmp%-%C1%/ %R2,%R3,%0"
3747 [(set_attr "type" "fadd")
3748 (set_attr "trap" "yes")
3749 (set_attr "trap_suffix" "su")])
3751 (define_insn "*cmpdf_ext2"
3752 [(set (match_operand:DF 0 "register_operand" "=f")
3753 (match_operator:DF 1 "alpha_fp_comparison_operator"
3754 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3755 (float_extend:DF
3756 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3757 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3758 "cmp%-%C1%/ %R2,%R3,%0"
3759 [(set_attr "type" "fadd")
3760 (set_attr "trap" "yes")
3761 (set_attr "trap_suffix" "su")])
3763 (define_insn "*cmpdf_ieee_ext3"
3764 [(set (match_operand:DF 0 "register_operand" "=&f")
3765 (match_operator:DF 1 "alpha_fp_comparison_operator"
3766 [(float_extend:DF
3767 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3768 (float_extend:DF
3769 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3770 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3771 "cmp%-%C1%/ %R2,%R3,%0"
3772 [(set_attr "type" "fadd")
3773 (set_attr "trap" "yes")
3774 (set_attr "trap_suffix" "su")])
3776 (define_insn "*cmpdf_ext3"
3777 [(set (match_operand:DF 0 "register_operand" "=f")
3778 (match_operator:DF 1 "alpha_fp_comparison_operator"
3779 [(float_extend:DF
3780 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3781 (float_extend:DF
3782 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3783 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3784 "cmp%-%C1%/ %R2,%R3,%0"
3785 [(set_attr "type" "fadd")
3786 (set_attr "trap" "yes")
3787 (set_attr "trap_suffix" "su")])
3789 (define_insn "*movdfcc_internal"
3790 [(set (match_operand:DF 0 "register_operand" "=f,f")
3791 (if_then_else:DF
3792 (match_operator 3 "signed_comparison_operator"
3793 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3794 (match_operand:DF 2 "const0_operand" "G,G")])
3795 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3796 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3797 "TARGET_FP"
3798 "@
3799 fcmov%C3 %R4,%R1,%0
3800 fcmov%D3 %R4,%R5,%0"
3801 [(set_attr "type" "fcmov")])
3803 (define_insn "*movsfcc_internal"
3804 [(set (match_operand:SF 0 "register_operand" "=f,f")
3805 (if_then_else:SF
3806 (match_operator 3 "signed_comparison_operator"
3807 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3808 (match_operand:DF 2 "const0_operand" "G,G")])
3809 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3810 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3811 "TARGET_FP"
3812 "@
3813 fcmov%C3 %R4,%R1,%0
3814 fcmov%D3 %R4,%R5,%0"
3815 [(set_attr "type" "fcmov")])
3817 (define_insn "*movdfcc_ext1"
3818 [(set (match_operand:DF 0 "register_operand" "=f,f")
3819 (if_then_else:DF
3820 (match_operator 3 "signed_comparison_operator"
3821 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3822 (match_operand:DF 2 "const0_operand" "G,G")])
3823 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3824 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3825 "TARGET_FP"
3826 "@
3827 fcmov%C3 %R4,%R1,%0
3828 fcmov%D3 %R4,%R5,%0"
3829 [(set_attr "type" "fcmov")])
3831 (define_insn "*movdfcc_ext2"
3832 [(set (match_operand:DF 0 "register_operand" "=f,f")
3833 (if_then_else:DF
3834 (match_operator 3 "signed_comparison_operator"
3835 [(float_extend:DF
3836 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3837 (match_operand:DF 2 "const0_operand" "G,G")])
3838 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3839 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3840 "TARGET_FP"
3841 "@
3842 fcmov%C3 %R4,%R1,%0
3843 fcmov%D3 %R4,%R5,%0"
3844 [(set_attr "type" "fcmov")])
3846 (define_insn "*movdfcc_ext3"
3847 [(set (match_operand:SF 0 "register_operand" "=f,f")
3848 (if_then_else:SF
3849 (match_operator 3 "signed_comparison_operator"
3850 [(float_extend:DF
3851 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3852 (match_operand:DF 2 "const0_operand" "G,G")])
3853 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3854 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3855 "TARGET_FP"
3856 "@
3857 fcmov%C3 %R4,%R1,%0
3858 fcmov%D3 %R4,%R5,%0"
3859 [(set_attr "type" "fcmov")])
3861 (define_insn "*movdfcc_ext4"
3862 [(set (match_operand:DF 0 "register_operand" "=f,f")
3863 (if_then_else:DF
3864 (match_operator 3 "signed_comparison_operator"
3865 [(float_extend:DF
3866 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3867 (match_operand:DF 2 "const0_operand" "G,G")])
3868 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3869 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3870 "TARGET_FP"
3871 "@
3872 fcmov%C3 %R4,%R1,%0
3873 fcmov%D3 %R4,%R5,%0"
3874 [(set_attr "type" "fcmov")])
3876 (define_expand "smaxdf3"
3877 [(set (match_dup 3)
3878 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3879 (match_operand:DF 2 "reg_or_0_operand" "")))
3880 (set (match_operand:DF 0 "register_operand" "")
3881 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3882 (match_dup 1) (match_dup 2)))]
3883 "TARGET_FP"
3884 {
3885 operands[3] = gen_reg_rtx (DFmode);
3886 operands[4] = CONST0_RTX (DFmode);
3887 })
3889 (define_expand "smindf3"
3890 [(set (match_dup 3)
3891 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3892 (match_operand:DF 2 "reg_or_0_operand" "")))
3893 (set (match_operand:DF 0 "register_operand" "")
3894 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3895 (match_dup 1) (match_dup 2)))]
3896 "TARGET_FP"
3897 {
3898 operands[3] = gen_reg_rtx (DFmode);
3899 operands[4] = CONST0_RTX (DFmode);
3900 })
3902 (define_expand "smaxsf3"
3903 [(set (match_dup 3)
3904 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3905 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3906 (set (match_operand:SF 0 "register_operand" "")
3907 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3908 (match_dup 1) (match_dup 2)))]
3909 "TARGET_FP"
3910 {
3911 operands[3] = gen_reg_rtx (DFmode);
3912 operands[4] = CONST0_RTX (DFmode);
3913 })
3915 (define_expand "sminsf3"
3916 [(set (match_dup 3)
3917 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3918 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3919 (set (match_operand:SF 0 "register_operand" "")
3920 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3921 (match_dup 1) (match_dup 2)))]
3922 "TARGET_FP"
3923 {
3924 operands[3] = gen_reg_rtx (DFmode);
3925 operands[4] = CONST0_RTX (DFmode);
3926 })
3928 (define_insn "*fbcc_normal"
3929 [(set (pc)
3930 (if_then_else
3931 (match_operator 1 "signed_comparison_operator"
3932 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3933 (match_operand:DF 3 "const0_operand" "G")])
3934 (label_ref (match_operand 0 "" ""))
3935 (pc)))]
3936 "TARGET_FP"
3937 "fb%C1 %R2,%0"
3938 [(set_attr "type" "fbr")])
3940 (define_insn "*fbcc_ext_normal"
3941 [(set (pc)
3942 (if_then_else
3943 (match_operator 1 "signed_comparison_operator"
3944 [(float_extend:DF
3945 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3946 (match_operand:DF 3 "const0_operand" "G")])
3947 (label_ref (match_operand 0 "" ""))
3948 (pc)))]
3949 "TARGET_FP"
3950 "fb%C1 %R2,%0"
3951 [(set_attr "type" "fbr")])
3952 \f
3953 ;; These are the main define_expand's used to make conditional branches
3954 ;; and compares.
3956 (define_expand "cmpdf"
3957 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3958 (match_operand:DF 1 "reg_or_0_operand" "")))]
3959 "TARGET_FP"
3960 {
3961 alpha_compare.op0 = operands[0];
3962 alpha_compare.op1 = operands[1];
3963 alpha_compare.fp_p = 1;
3964 DONE;
3965 })
3967 (define_expand "cmptf"
3968 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3969 (match_operand:TF 1 "general_operand" "")))]
3970 "TARGET_HAS_XFLOATING_LIBS"
3971 {
3972 alpha_compare.op0 = operands[0];
3973 alpha_compare.op1 = operands[1];
3974 alpha_compare.fp_p = 1;
3975 DONE;
3976 })
3978 (define_expand "cmpdi"
3979 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3980 (match_operand:DI 1 "some_operand" "")))]
3981 ""
3982 {
3983 alpha_compare.op0 = operands[0];
3984 alpha_compare.op1 = operands[1];
3985 alpha_compare.fp_p = 0;
3986 DONE;
3987 })
3989 (define_expand "beq"
3990 [(set (pc)
3991 (if_then_else (match_dup 1)
3992 (label_ref (match_operand 0 "" ""))
3993 (pc)))]
3994 ""
3995 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3997 (define_expand "bne"
3998 [(set (pc)
3999 (if_then_else (match_dup 1)
4000 (label_ref (match_operand 0 "" ""))
4001 (pc)))]
4002 ""
4003 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
4005 (define_expand "blt"
4006 [(set (pc)
4007 (if_then_else (match_dup 1)
4008 (label_ref (match_operand 0 "" ""))
4009 (pc)))]
4010 ""
4011 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
4013 (define_expand "ble"
4014 [(set (pc)
4015 (if_then_else (match_dup 1)
4016 (label_ref (match_operand 0 "" ""))
4017 (pc)))]
4018 ""
4019 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
4021 (define_expand "bgt"
4022 [(set (pc)
4023 (if_then_else (match_dup 1)
4024 (label_ref (match_operand 0 "" ""))
4025 (pc)))]
4026 ""
4027 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
4029 (define_expand "bge"
4030 [(set (pc)
4031 (if_then_else (match_dup 1)
4032 (label_ref (match_operand 0 "" ""))
4033 (pc)))]
4034 ""
4035 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
4037 (define_expand "bltu"
4038 [(set (pc)
4039 (if_then_else (match_dup 1)
4040 (label_ref (match_operand 0 "" ""))
4041 (pc)))]
4042 ""
4043 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4045 (define_expand "bleu"
4046 [(set (pc)
4047 (if_then_else (match_dup 1)
4048 (label_ref (match_operand 0 "" ""))
4049 (pc)))]
4050 ""
4051 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4053 (define_expand "bgtu"
4054 [(set (pc)
4055 (if_then_else (match_dup 1)
4056 (label_ref (match_operand 0 "" ""))
4057 (pc)))]
4058 ""
4059 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4061 (define_expand "bgeu"
4062 [(set (pc)
4063 (if_then_else (match_dup 1)
4064 (label_ref (match_operand 0 "" ""))
4065 (pc)))]
4066 ""
4067 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4069 (define_expand "bunordered"
4070 [(set (pc)
4071 (if_then_else (match_dup 1)
4072 (label_ref (match_operand 0 "" ""))
4073 (pc)))]
4074 ""
4075 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4077 (define_expand "bordered"
4078 [(set (pc)
4079 (if_then_else (match_dup 1)
4080 (label_ref (match_operand 0 "" ""))
4081 (pc)))]
4082 ""
4083 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4085 (define_expand "seq"
4086 [(set (match_operand:DI 0 "register_operand" "")
4087 (match_dup 1))]
4088 ""
4089 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4091 (define_expand "sne"
4092 [(set (match_operand:DI 0 "register_operand" "")
4093 (match_dup 1))]
4094 ""
4095 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4097 (define_expand "slt"
4098 [(set (match_operand:DI 0 "register_operand" "")
4099 (match_dup 1))]
4100 ""
4101 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4103 (define_expand "sle"
4104 [(set (match_operand:DI 0 "register_operand" "")
4105 (match_dup 1))]
4106 ""
4107 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4109 (define_expand "sgt"
4110 [(set (match_operand:DI 0 "register_operand" "")
4111 (match_dup 1))]
4112 ""
4113 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4115 (define_expand "sge"
4116 [(set (match_operand:DI 0 "register_operand" "")
4117 (match_dup 1))]
4118 ""
4119 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4121 (define_expand "sltu"
4122 [(set (match_operand:DI 0 "register_operand" "")
4123 (match_dup 1))]
4124 ""
4125 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4127 (define_expand "sleu"
4128 [(set (match_operand:DI 0 "register_operand" "")
4129 (match_dup 1))]
4130 ""
4131 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4133 (define_expand "sgtu"
4134 [(set (match_operand:DI 0 "register_operand" "")
4135 (match_dup 1))]
4136 ""
4137 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4139 (define_expand "sgeu"
4140 [(set (match_operand:DI 0 "register_operand" "")
4141 (match_dup 1))]
4142 ""
4143 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4145 (define_expand "sunordered"
4146 [(set (match_operand:DI 0 "register_operand" "")
4147 (match_dup 1))]
4148 ""
4149 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4151 (define_expand "sordered"
4152 [(set (match_operand:DI 0 "register_operand" "")
4153 (match_dup 1))]
4154 ""
4155 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4156 \f
4157 ;; These are the main define_expand's used to make conditional moves.
4159 (define_expand "movsicc"
4160 [(set (match_operand:SI 0 "register_operand" "")
4161 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4162 (match_operand:SI 2 "reg_or_8bit_operand" "")
4163 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4164 ""
4165 {
4166 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4167 FAIL;
4168 })
4170 (define_expand "movdicc"
4171 [(set (match_operand:DI 0 "register_operand" "")
4172 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4173 (match_operand:DI 2 "reg_or_8bit_operand" "")
4174 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4175 ""
4176 {
4177 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4178 FAIL;
4179 })
4181 (define_expand "movsfcc"
4182 [(set (match_operand:SF 0 "register_operand" "")
4183 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4184 (match_operand:SF 2 "reg_or_8bit_operand" "")
4185 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4186 ""
4187 {
4188 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4189 FAIL;
4190 })
4192 (define_expand "movdfcc"
4193 [(set (match_operand:DF 0 "register_operand" "")
4194 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4195 (match_operand:DF 2 "reg_or_8bit_operand" "")
4196 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4197 ""
4198 {
4199 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4200 FAIL;
4201 })
4202 \f
4203 ;; These define_split definitions are used in cases when comparisons have
4204 ;; not be stated in the correct way and we need to reverse the second
4205 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4206 ;; comparison that tests the result being reversed. We have one define_split
4207 ;; for each use of a comparison. They do not match valid insns and need
4208 ;; not generate valid insns.
4209 ;;
4210 ;; We can also handle equality comparisons (and inequality comparisons in
4211 ;; cases where the resulting add cannot overflow) by doing an add followed by
4212 ;; a comparison with zero. This is faster since the addition takes one
4213 ;; less cycle than a compare when feeding into a conditional move.
4214 ;; For this case, we also have an SImode pattern since we can merge the add
4215 ;; and sign extend and the order doesn't matter.
4216 ;;
4217 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4218 ;; operation could have been generated.
4220 (define_split
4221 [(set (match_operand:DI 0 "register_operand" "")
4222 (if_then_else:DI
4223 (match_operator 1 "comparison_operator"
4224 [(match_operand:DI 2 "reg_or_0_operand" "")
4225 (match_operand:DI 3 "reg_or_cint_operand" "")])
4226 (match_operand:DI 4 "reg_or_cint_operand" "")
4227 (match_operand:DI 5 "reg_or_cint_operand" "")))
4228 (clobber (match_operand:DI 6 "register_operand" ""))]
4229 "operands[3] != const0_rtx"
4230 [(set (match_dup 6) (match_dup 7))
4231 (set (match_dup 0)
4232 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4233 {
4234 enum rtx_code code = GET_CODE (operands[1]);
4235 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4237 /* If we are comparing for equality with a constant and that constant
4238 appears in the arm when the register equals the constant, use the
4239 register since that is more likely to match (and to produce better code
4240 if both would). */
4242 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4243 && rtx_equal_p (operands[4], operands[3]))
4244 operands[4] = operands[2];
4246 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4247 && rtx_equal_p (operands[5], operands[3]))
4248 operands[5] = operands[2];
4250 if (code == NE || code == EQ
4251 || (extended_count (operands[2], DImode, unsignedp) >= 1
4252 && extended_count (operands[3], DImode, unsignedp) >= 1))
4253 {
4254 if (GET_CODE (operands[3]) == CONST_INT)
4255 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4256 GEN_INT (- INTVAL (operands[3])));
4257 else
4258 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4260 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4261 }
4263 else if (code == EQ || code == LE || code == LT
4264 || code == LEU || code == LTU)
4265 {
4266 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4267 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4268 }
4269 else
4270 {
4271 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4272 operands[2], operands[3]);
4273 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4274 }
4275 })
4277 (define_split
4278 [(set (match_operand:DI 0 "register_operand" "")
4279 (if_then_else:DI
4280 (match_operator 1 "comparison_operator"
4281 [(match_operand:SI 2 "reg_or_0_operand" "")
4282 (match_operand:SI 3 "reg_or_cint_operand" "")])
4283 (match_operand:DI 4 "reg_or_8bit_operand" "")
4284 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4285 (clobber (match_operand:DI 6 "register_operand" ""))]
4286 "operands[3] != const0_rtx
4287 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4288 [(set (match_dup 6) (match_dup 7))
4289 (set (match_dup 0)
4290 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4291 {
4292 enum rtx_code code = GET_CODE (operands[1]);
4293 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4294 rtx tem;
4296 if ((code != NE && code != EQ
4297 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4298 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4299 FAIL;
4301 if (GET_CODE (operands[3]) == CONST_INT)
4302 tem = gen_rtx_PLUS (SImode, operands[2],
4303 GEN_INT (- INTVAL (operands[3])));
4304 else
4305 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4307 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4308 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4309 operands[6], const0_rtx);
4310 })
4312 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4314 (define_split
4315 [(set (match_operand 0 "register_operand" "")
4316 (if_then_else (match_operator 1 "signed_comparison_operator"
4317 [(match_operand:DI 2 "reg_or_0_operand" "")
4318 (const_int 0)])
4319 (match_operand 3 "const_int_operand" "")
4320 (match_operand 4 "const_int_operand" "")))]
4321 ""
4322 [(const_int 0)]
4323 {
4324 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4325 operands[2], operands[3], operands[4]))
4326 DONE;
4327 else
4328 FAIL;
4329 })
4331 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4332 ;; Oh well, we match it in movcc, so it must be partially our fault.
4333 (define_split
4334 [(set (match_operand 0 "register_operand" "")
4335 (if_then_else (match_operator 1 "signed_comparison_operator"
4336 [(const_int 0)
4337 (match_operand:DI 2 "reg_or_0_operand" "")])
4338 (match_operand 3 "const_int_operand" "")
4339 (match_operand 4 "const_int_operand" "")))]
4340 ""
4341 [(const_int 0)]
4342 {
4343 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4344 operands[0], operands[2], operands[3],
4345 operands[4]))
4346 DONE;
4347 else
4348 FAIL;
4349 })
4351 (define_insn_and_split "*cmp_sadd_di"
4352 [(set (match_operand:DI 0 "register_operand" "=r")
4353 (plus:DI (if_then_else:DI
4354 (match_operator 1 "alpha_zero_comparison_operator"
4355 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4356 (const_int 0)])
4357 (match_operand:DI 3 "const48_operand" "I")
4358 (const_int 0))
4359 (match_operand:DI 4 "sext_add_operand" "rIO")))
4360 (clobber (match_scratch:DI 5 "=r"))]
4361 ""
4362 "#"
4363 "! no_new_pseudos || reload_completed"
4364 [(set (match_dup 5)
4365 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4366 (set (match_dup 0)
4367 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4368 (match_dup 4)))]
4369 {
4370 if (! no_new_pseudos)
4371 operands[5] = gen_reg_rtx (DImode);
4372 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4373 operands[5] = operands[0];
4374 })
4376 (define_insn_and_split "*cmp_sadd_si"
4377 [(set (match_operand:SI 0 "register_operand" "=r")
4378 (plus:SI (if_then_else:SI
4379 (match_operator 1 "alpha_zero_comparison_operator"
4380 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4381 (const_int 0)])
4382 (match_operand:SI 3 "const48_operand" "I")
4383 (const_int 0))
4384 (match_operand:SI 4 "sext_add_operand" "rIO")))
4385 (clobber (match_scratch:SI 5 "=r"))]
4386 ""
4387 "#"
4388 "! no_new_pseudos || reload_completed"
4389 [(set (match_dup 5)
4390 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4391 (set (match_dup 0)
4392 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4393 (match_dup 4)))]
4394 {
4395 if (! no_new_pseudos)
4396 operands[5] = gen_reg_rtx (DImode);
4397 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4398 operands[5] = operands[0];
4399 })
4401 (define_insn_and_split "*cmp_sadd_sidi"
4402 [(set (match_operand:DI 0 "register_operand" "=r")
4403 (sign_extend:DI
4404 (plus:SI (if_then_else:SI
4405 (match_operator 1 "alpha_zero_comparison_operator"
4406 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4407 (const_int 0)])
4408 (match_operand:SI 3 "const48_operand" "I")
4409 (const_int 0))
4410 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4411 (clobber (match_scratch:SI 5 "=r"))]
4412 ""
4413 "#"
4414 "! no_new_pseudos || reload_completed"
4415 [(set (match_dup 5)
4416 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4417 (set (match_dup 0)
4418 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4419 (match_dup 4))))]
4420 {
4421 if (! no_new_pseudos)
4422 operands[5] = gen_reg_rtx (DImode);
4423 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4424 operands[5] = operands[0];
4425 })
4427 (define_insn_and_split "*cmp_ssub_di"
4428 [(set (match_operand:DI 0 "register_operand" "=r")
4429 (minus:DI (if_then_else:DI
4430 (match_operator 1 "alpha_zero_comparison_operator"
4431 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4432 (const_int 0)])
4433 (match_operand:DI 3 "const48_operand" "I")
4434 (const_int 0))
4435 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4436 (clobber (match_scratch:DI 5 "=r"))]
4437 ""
4438 "#"
4439 "! no_new_pseudos || reload_completed"
4440 [(set (match_dup 5)
4441 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4442 (set (match_dup 0)
4443 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4444 (match_dup 4)))]
4445 {
4446 if (! no_new_pseudos)
4447 operands[5] = gen_reg_rtx (DImode);
4448 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4449 operands[5] = operands[0];
4450 })
4452 (define_insn_and_split "*cmp_ssub_si"
4453 [(set (match_operand:SI 0 "register_operand" "=r")
4454 (minus:SI (if_then_else:SI
4455 (match_operator 1 "alpha_zero_comparison_operator"
4456 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4457 (const_int 0)])
4458 (match_operand:SI 3 "const48_operand" "I")
4459 (const_int 0))
4460 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4461 (clobber (match_scratch:SI 5 "=r"))]
4462 ""
4463 "#"
4464 "! no_new_pseudos || reload_completed"
4465 [(set (match_dup 5)
4466 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4467 (set (match_dup 0)
4468 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4469 (match_dup 4)))]
4470 {
4471 if (! no_new_pseudos)
4472 operands[5] = gen_reg_rtx (DImode);
4473 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4474 operands[5] = operands[0];
4475 })
4477 (define_insn_and_split "*cmp_ssub_sidi"
4478 [(set (match_operand:DI 0 "register_operand" "=r")
4479 (sign_extend:DI
4480 (minus:SI (if_then_else:SI
4481 (match_operator 1 "alpha_zero_comparison_operator"
4482 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4483 (const_int 0)])
4484 (match_operand:SI 3 "const48_operand" "I")
4485 (const_int 0))
4486 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4487 (clobber (match_scratch:SI 5 "=r"))]
4488 ""
4489 "#"
4490 "! no_new_pseudos || reload_completed"
4491 [(set (match_dup 5)
4492 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4493 (set (match_dup 0)
4494 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4495 (match_dup 4))))]
4496 {
4497 if (! no_new_pseudos)
4498 operands[5] = gen_reg_rtx (DImode);
4499 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4500 operands[5] = operands[0];
4501 })
4502 \f
4503 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4504 ;; work differently, so we have different patterns for each.
4506 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4507 ;; call. The CIW contains information about arguments passed in registers
4508 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4509 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4510 ;; in the presence of inlining since the CIWs for calls performed by the
4511 ;; inlined function must be stored in the SSIB of the function it is inlined
4512 ;; into as well. We encode the CIW in an unspec and append it to the list
4513 ;; of the CIWs for the current function only when the instruction for loading
4514 ;; $25 is generated.
4516 (define_expand "call"
4517 [(use (match_operand:DI 0 "" ""))
4518 (use (match_operand 1 "" ""))
4519 (use (match_operand 2 "" ""))
4520 (use (match_operand 3 "" ""))]
4521 ""
4522 {
4523 if (TARGET_ABI_WINDOWS_NT)
4524 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4525 else if (TARGET_ABI_OPEN_VMS)
4526 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4527 else if (TARGET_ABI_UNICOSMK)
4528 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4529 else
4530 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4531 DONE;
4532 })
4534 (define_expand "sibcall"
4535 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4536 (match_operand 1 "" ""))
4537 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4538 "TARGET_ABI_OSF"
4539 {
4540 gcc_assert (GET_CODE (operands[0]) == MEM);
4541 operands[0] = XEXP (operands[0], 0);
4542 })
4544 (define_expand "call_osf"
4545 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4546 (match_operand 1 "" ""))
4547 (use (reg:DI 29))
4548 (clobber (reg:DI 26))])]
4549 ""
4550 {
4551 gcc_assert (GET_CODE (operands[0]) == MEM);
4553 operands[0] = XEXP (operands[0], 0);
4554 if (! call_operand (operands[0], Pmode))
4555 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4556 })
4558 (define_expand "call_nt"
4559 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4560 (match_operand 1 "" ""))
4561 (clobber (reg:DI 26))])]
4562 ""
4563 {
4564 gcc_assert (GET_CODE (operands[0]) == MEM);
4566 operands[0] = XEXP (operands[0], 0);
4567 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4568 operands[0] = force_reg (DImode, operands[0]);
4569 })
4571 ;; Calls on Unicos/Mk are always indirect.
4572 ;; op 0: symbol ref for called function
4573 ;; op 1: CIW for $25 represented by an unspec
4575 (define_expand "call_umk"
4576 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4577 (match_operand 1 "" ""))
4578 (use (reg:DI 25))
4579 (clobber (reg:DI 26))])]
4580 ""
4581 {
4582 gcc_assert (GET_CODE (operands[0]) == MEM);
4584 /* Always load the address of the called function into a register;
4585 load the CIW in $25. */
4587 operands[0] = XEXP (operands[0], 0);
4588 if (GET_CODE (operands[0]) != REG)
4589 operands[0] = force_reg (DImode, operands[0]);
4591 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4592 })
4594 ;;
4595 ;; call openvms/alpha
4596 ;; op 0: symbol ref for called function
4597 ;; op 1: next_arg_reg (argument information value for R25)
4598 ;;
4599 (define_expand "call_vms"
4600 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4601 (match_operand 1 "" ""))
4602 (use (match_dup 2))
4603 (use (reg:DI 25))
4604 (use (reg:DI 26))
4605 (clobber (reg:DI 27))])]
4606 ""
4607 {
4608 gcc_assert (GET_CODE (operands[0]) == MEM);
4610 operands[0] = XEXP (operands[0], 0);
4612 /* Always load AI with argument information, then handle symbolic and
4613 indirect call differently. Load RA and set operands[2] to PV in
4614 both cases. */
4616 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4617 if (GET_CODE (operands[0]) == SYMBOL_REF)
4618 {
4619 alpha_need_linkage (XSTR (operands[0], 0), 0);
4621 operands[2] = const0_rtx;
4622 }
4623 else
4624 {
4625 emit_move_insn (gen_rtx_REG (Pmode, 26),
4626 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4627 operands[2] = operands[0];
4628 }
4630 })
4632 (define_expand "call_value"
4633 [(use (match_operand 0 "" ""))
4634 (use (match_operand:DI 1 "" ""))
4635 (use (match_operand 2 "" ""))
4636 (use (match_operand 3 "" ""))
4637 (use (match_operand 4 "" ""))]
4638 ""
4639 {
4640 if (TARGET_ABI_WINDOWS_NT)
4641 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4642 else if (TARGET_ABI_OPEN_VMS)
4643 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4644 operands[3]));
4645 else if (TARGET_ABI_UNICOSMK)
4646 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4647 operands[3]));
4648 else
4649 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4650 operands[2]));
4651 DONE;
4652 })
4654 (define_expand "sibcall_value"
4655 [(parallel [(set (match_operand 0 "" "")
4656 (call (mem:DI (match_operand 1 "" ""))
4657 (match_operand 2 "" "")))
4658 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4659 "TARGET_ABI_OSF"
4660 {
4661 gcc_assert (GET_CODE (operands[1]) == MEM);
4662 operands[1] = XEXP (operands[1], 0);
4663 })
4665 (define_expand "call_value_osf"
4666 [(parallel [(set (match_operand 0 "" "")
4667 (call (mem:DI (match_operand 1 "" ""))
4668 (match_operand 2 "" "")))
4669 (use (reg:DI 29))
4670 (clobber (reg:DI 26))])]
4671 ""
4672 {
4673 gcc_assert (GET_CODE (operands[1]) == MEM);
4675 operands[1] = XEXP (operands[1], 0);
4676 if (! call_operand (operands[1], Pmode))
4677 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4678 })
4680 (define_expand "call_value_nt"
4681 [(parallel [(set (match_operand 0 "" "")
4682 (call (mem:DI (match_operand 1 "" ""))
4683 (match_operand 2 "" "")))
4684 (clobber (reg:DI 26))])]
4685 ""
4686 {
4687 gcc_assert (GET_CODE (operands[1]) == MEM);
4689 operands[1] = XEXP (operands[1], 0);
4690 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4691 operands[1] = force_reg (DImode, operands[1]);
4692 })
4694 (define_expand "call_value_vms"
4695 [(parallel [(set (match_operand 0 "" "")
4696 (call (mem:DI (match_operand:DI 1 "" ""))
4697 (match_operand 2 "" "")))
4698 (use (match_dup 3))
4699 (use (reg:DI 25))
4700 (use (reg:DI 26))
4701 (clobber (reg:DI 27))])]
4702 ""
4703 {
4704 gcc_assert (GET_CODE (operands[1]) == MEM);
4706 operands[1] = XEXP (operands[1], 0);
4708 /* Always load AI with argument information, then handle symbolic and
4709 indirect call differently. Load RA and set operands[3] to PV in
4710 both cases. */
4712 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4713 if (GET_CODE (operands[1]) == SYMBOL_REF)
4714 {
4715 alpha_need_linkage (XSTR (operands[1], 0), 0);
4717 operands[3] = const0_rtx;
4718 }
4719 else
4720 {
4721 emit_move_insn (gen_rtx_REG (Pmode, 26),
4722 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4723 operands[3] = operands[1];
4724 }
4725 })
4727 (define_expand "call_value_umk"
4728 [(parallel [(set (match_operand 0 "" "")
4729 (call (mem:DI (match_operand 1 "" ""))
4730 (match_operand 2 "" "")))
4731 (use (reg:DI 25))
4732 (clobber (reg:DI 26))])]
4733 ""
4734 {
4735 gcc_assert (GET_CODE (operands[1]) == MEM);
4737 operands[1] = XEXP (operands[1], 0);
4738 if (GET_CODE (operands[1]) != REG)
4739 operands[1] = force_reg (DImode, operands[1]);
4741 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4742 })
4744 (define_insn "*call_osf_1_er_noreturn"
4745 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4746 (match_operand 1 "" ""))
4747 (use (reg:DI 29))
4748 (clobber (reg:DI 26))]
4749 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4750 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4751 "@
4752 jsr $26,($27),0
4753 bsr $26,%0\t\t!samegp
4754 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
4755 [(set_attr "type" "jsr")
4756 (set_attr "length" "*,*,8")])
4758 (define_insn "*call_osf_1_er"
4759 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4760 (match_operand 1 "" ""))
4761 (use (reg:DI 29))
4762 (clobber (reg:DI 26))]
4763 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4764 "@
4765 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4766 bsr $26,%0\t\t!samegp
4767 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4768 [(set_attr "type" "jsr")
4769 (set_attr "length" "12,*,16")])
4771 ;; We must use peep2 instead of a split because we need accurate life
4772 ;; information for $gp. Consider the case of { bar(); while (1); }.
4773 (define_peephole2
4774 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4775 (match_operand 1 "" ""))
4776 (use (reg:DI 29))
4777 (clobber (reg:DI 26))])]
4778 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4779 && ! samegp_function_operand (operands[0], Pmode)
4780 && (peep2_regno_dead_p (1, 29)
4781 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4782 [(parallel [(call (mem:DI (match_dup 2))
4783 (match_dup 1))
4784 (use (reg:DI 29))
4785 (use (match_dup 0))
4786 (use (match_dup 3))
4787 (clobber (reg:DI 26))])]
4788 {
4789 if (CONSTANT_P (operands[0]))
4790 {
4791 operands[2] = gen_rtx_REG (Pmode, 27);
4792 operands[3] = GEN_INT (alpha_next_sequence_number++);
4793 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4794 operands[0], operands[3]));
4795 }
4796 else
4797 {
4798 operands[2] = operands[0];
4799 operands[0] = const0_rtx;
4800 operands[3] = const0_rtx;
4801 }
4802 })
4804 (define_peephole2
4805 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4806 (match_operand 1 "" ""))
4807 (use (reg:DI 29))
4808 (clobber (reg:DI 26))])]
4809 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4810 && ! samegp_function_operand (operands[0], Pmode)
4811 && ! (peep2_regno_dead_p (1, 29)
4812 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4813 [(parallel [(call (mem:DI (match_dup 2))
4814 (match_dup 1))
4815 (set (match_dup 5)
4816 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1))
4817 (use (match_dup 0))
4818 (use (match_dup 4))
4819 (clobber (reg:DI 26))])
4820 (set (match_dup 5)
4821 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))]
4822 {
4823 if (CONSTANT_P (operands[0]))
4824 {
4825 operands[2] = gen_rtx_REG (Pmode, 27);
4826 operands[4] = GEN_INT (alpha_next_sequence_number++);
4827 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4828 operands[0], operands[4]));
4829 }
4830 else
4831 {
4832 operands[2] = operands[0];
4833 operands[0] = const0_rtx;
4834 operands[4] = const0_rtx;
4835 }
4836 operands[3] = GEN_INT (alpha_next_sequence_number++);
4837 operands[5] = pic_offset_table_rtx;
4838 })
4840 (define_insn "*call_osf_2_er_nogp"
4841 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4842 (match_operand 1 "" ""))
4843 (use (reg:DI 29))
4844 (use (match_operand 2 "" ""))
4845 (use (match_operand 3 "const_int_operand" ""))
4846 (clobber (reg:DI 26))]
4847 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4848 "jsr $26,(%0),%2%J3"
4849 [(set_attr "type" "jsr")])
4851 (define_insn "*call_osf_2_er"
4852 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4853 (match_operand 1 "" ""))
4854 (set (reg:DI 29)
4855 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand" "")]
4856 UNSPEC_LDGP1))
4857 (use (match_operand 2 "" ""))
4858 (use (match_operand 3 "const_int_operand" ""))
4859 (clobber (reg:DI 26))]
4860 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4861 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
4862 [(set_attr "type" "jsr")
4863 (set_attr "cannot_copy" "true")
4864 (set_attr "length" "8")])
4866 (define_insn "*call_osf_1_noreturn"
4867 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4868 (match_operand 1 "" ""))
4869 (use (reg:DI 29))
4870 (clobber (reg:DI 26))]
4871 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4872 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4873 "@
4874 jsr $26,($27),0
4875 bsr $26,$%0..ng
4876 jsr $26,%0"
4877 [(set_attr "type" "jsr")
4878 (set_attr "length" "*,*,8")])
4880 (define_insn "*call_osf_1"
4881 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4882 (match_operand 1 "" ""))
4883 (use (reg:DI 29))
4884 (clobber (reg:DI 26))]
4885 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4886 "@
4887 jsr $26,($27),0\;ldgp $29,0($26)
4888 bsr $26,$%0..ng
4889 jsr $26,%0\;ldgp $29,0($26)"
4890 [(set_attr "type" "jsr")
4891 (set_attr "length" "12,*,16")])
4893 (define_insn "*sibcall_osf_1_er"
4894 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4895 (match_operand 1 "" ""))
4896 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4897 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4898 "@
4899 br $31,%0\t\t!samegp
4900 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4901 [(set_attr "type" "jsr")
4902 (set_attr "length" "*,8")])
4904 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4905 ;; doesn't do what we want.
4906 (define_insn "*sibcall_osf_1"
4907 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4908 (match_operand 1 "" ""))
4909 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4910 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4911 "@
4912 br $31,$%0..ng
4913 lda $27,%0\;jmp $31,($27),%0"
4914 [(set_attr "type" "jsr")
4915 (set_attr "length" "*,8")])
4917 (define_insn "*call_nt_1"
4918 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4919 (match_operand 1 "" ""))
4920 (clobber (reg:DI 26))]
4921 "TARGET_ABI_WINDOWS_NT"
4922 "@
4923 jsr $26,(%0)
4924 bsr $26,%0
4925 jsr $26,%0"
4926 [(set_attr "type" "jsr")
4927 (set_attr "length" "*,*,12")])
4929 ; GAS relies on the order and position of instructions output below in order
4930 ; to generate relocs for VMS link to potentially optimize the call.
4931 ; Please do not molest.
4932 (define_insn "*call_vms_1"
4933 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4934 (match_operand 1 "" ""))
4935 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4936 (use (reg:DI 25))
4937 (use (reg:DI 26))
4938 (clobber (reg:DI 27))]
4939 "TARGET_ABI_OPEN_VMS"
4940 {
4941 switch (which_alternative)
4942 {
4943 case 0:
4944 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4945 case 1:
4946 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4947 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4948 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4949 default:
4950 gcc_unreachable ();
4951 }
4952 }
4953 [(set_attr "type" "jsr")
4954 (set_attr "length" "12,16")])
4956 (define_insn "*call_umk_1"
4957 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4958 (match_operand 1 "" ""))
4959 (use (reg:DI 25))
4960 (clobber (reg:DI 26))]
4961 "TARGET_ABI_UNICOSMK"
4962 "jsr $26,(%0)"
4963 [(set_attr "type" "jsr")])
4965 ;; Call subroutine returning any type.
4967 (define_expand "untyped_call"
4968 [(parallel [(call (match_operand 0 "" "")
4969 (const_int 0))
4970 (match_operand 1 "" "")
4971 (match_operand 2 "" "")])]
4972 ""
4973 {
4974 int i;
4976 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4978 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4979 {
4980 rtx set = XVECEXP (operands[2], 0, i);
4981 emit_move_insn (SET_DEST (set), SET_SRC (set));
4982 }
4984 /* The optimizer does not know that the call sets the function value
4985 registers we stored in the result block. We avoid problems by
4986 claiming that all hard registers are used and clobbered at this
4987 point. */
4988 emit_insn (gen_blockage ());
4990 DONE;
4991 })
4993 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4994 ;; all of memory. This blocks insns from being moved across this point.
4996 (define_insn "blockage"
4997 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4998 ""
4999 ""
5000 [(set_attr "length" "0")
5001 (set_attr "type" "none")])
5003 (define_insn "jump"
5004 [(set (pc)
5005 (label_ref (match_operand 0 "" "")))]
5006 ""
5007 "br $31,%l0"
5008 [(set_attr "type" "ibr")])
5010 (define_expand "return"
5011 [(return)]
5012 "direct_return ()"
5013 "")
5015 (define_insn "*return_internal"
5016 [(return)]
5017 "reload_completed"
5018 "ret $31,($26),1"
5019 [(set_attr "type" "ibr")])
5021 (define_insn "indirect_jump"
5022 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5023 ""
5024 "jmp $31,(%0),0"
5025 [(set_attr "type" "ibr")])
5027 (define_expand "tablejump"
5028 [(parallel [(set (pc)
5029 (match_operand 0 "register_operand" ""))
5030 (use (label_ref:DI (match_operand 1 "" "")))])]
5031 ""
5032 {
5033 if (TARGET_ABI_WINDOWS_NT)
5034 {
5035 rtx dest = gen_reg_rtx (DImode);
5036 emit_insn (gen_extendsidi2 (dest, operands[0]));
5037 operands[0] = dest;
5038 }
5039 else if (TARGET_ABI_OSF)
5040 {
5041 rtx dest = gen_reg_rtx (DImode);
5042 emit_insn (gen_extendsidi2 (dest, operands[0]));
5043 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5044 operands[0] = dest;
5045 }
5046 })
5048 (define_insn "*tablejump_osf_nt_internal"
5049 [(set (pc)
5050 (match_operand:DI 0 "register_operand" "r"))
5051 (use (label_ref:DI (match_operand 1 "" "")))]
5052 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5053 && alpha_tablejump_addr_vec (insn)"
5054 {
5055 operands[2] = alpha_tablejump_best_label (insn);
5056 return "jmp $31,(%0),%2";
5057 }
5058 [(set_attr "type" "ibr")])
5060 (define_insn "*tablejump_internal"
5061 [(set (pc)
5062 (match_operand:DI 0 "register_operand" "r"))
5063 (use (label_ref (match_operand 1 "" "")))]
5064 ""
5065 "jmp $31,(%0),0"
5066 [(set_attr "type" "ibr")])
5068 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5069 ;; want to have to include pal.h in our .s file.
5070 (define_insn "imb"
5071 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5072 ""
5073 "call_pal 0x86"
5074 [(set_attr "type" "callpal")])
5076 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5077 ;; NT does not document anything at 0x81 -- presumably it would generate
5078 ;; the equivalent of SIGILL, but this isn't that important.
5079 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5080 (define_insn "trap"
5081 [(trap_if (const_int 1) (const_int 0))]
5082 "!TARGET_ABI_WINDOWS_NT"
5083 "call_pal 0x81"
5084 [(set_attr "type" "callpal")])
5086 ;; For userland, we load the thread pointer from the TCB.
5087 ;; For the kernel, we load the per-cpu private value.
5089 (define_insn "load_tp"
5090 [(set (match_operand:DI 0 "register_operand" "=v")
5091 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5092 "TARGET_ABI_OSF"
5093 {
5094 if (TARGET_TLS_KERNEL)
5095 return "call_pal 0x32";
5096 else
5097 return "call_pal 0x9e";
5098 }
5099 [(set_attr "type" "callpal")])
5101 ;; For completeness, and possibly a __builtin function, here's how to
5102 ;; set the thread pointer. Since we don't describe enough of this
5103 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5104 ;; not much point in creating an R16_REG register class.
5106 (define_expand "set_tp"
5107 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5108 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5109 "TARGET_ABI_OSF"
5110 "")
5112 (define_insn "*set_tp"
5113 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5114 "TARGET_ABI_OSF"
5115 {
5116 if (TARGET_TLS_KERNEL)
5117 return "call_pal 0x31";
5118 else
5119 return "call_pal 0x9f";
5120 }
5121 [(set_attr "type" "callpal")])
5122 \f
5123 ;; Finally, we have the basic data motion insns. The byte and word insns
5124 ;; are done via define_expand. Start with the floating-point insns, since
5125 ;; they are simpler.
5127 (define_insn "*movsf_nofix"
5128 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5129 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5130 "TARGET_FPREGS && ! TARGET_FIX
5131 && (register_operand (operands[0], SFmode)
5132 || reg_or_0_operand (operands[1], SFmode))"
5133 "@
5134 cpys %R1,%R1,%0
5135 ld%, %0,%1
5136 bis $31,%r1,%0
5137 ldl %0,%1
5138 st%, %R1,%0
5139 stl %r1,%0"
5140 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5142 (define_insn "*movsf_fix"
5143 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5144 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5145 "TARGET_FPREGS && TARGET_FIX
5146 && (register_operand (operands[0], SFmode)
5147 || reg_or_0_operand (operands[1], SFmode))"
5148 "@
5149 cpys %R1,%R1,%0
5150 ld%, %0,%1
5151 bis $31,%r1,%0
5152 ldl %0,%1
5153 st%, %R1,%0
5154 stl %r1,%0
5155 itofs %1,%0
5156 ftois %1,%0"
5157 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5159 (define_insn "*movsf_nofp"
5160 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5161 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5162 "! TARGET_FPREGS
5163 && (register_operand (operands[0], SFmode)
5164 || reg_or_0_operand (operands[1], SFmode))"
5165 "@
5166 bis $31,%r1,%0
5167 ldl %0,%1
5168 stl %r1,%0"
5169 [(set_attr "type" "ilog,ild,ist")])
5171 (define_insn "*movdf_nofix"
5172 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5173 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5174 "TARGET_FPREGS && ! TARGET_FIX
5175 && (register_operand (operands[0], DFmode)
5176 || reg_or_0_operand (operands[1], DFmode))"
5177 "@
5178 cpys %R1,%R1,%0
5179 ld%- %0,%1
5180 bis $31,%r1,%0
5181 ldq %0,%1
5182 st%- %R1,%0
5183 stq %r1,%0"
5184 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5186 (define_insn "*movdf_fix"
5187 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5188 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5189 "TARGET_FPREGS && TARGET_FIX
5190 && (register_operand (operands[0], DFmode)
5191 || reg_or_0_operand (operands[1], DFmode))"
5192 "@
5193 cpys %R1,%R1,%0
5194 ld%- %0,%1
5195 bis $31,%r1,%0
5196 ldq %0,%1
5197 st%- %R1,%0
5198 stq %r1,%0
5199 itoft %1,%0
5200 ftoit %1,%0"
5201 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5203 (define_insn "*movdf_nofp"
5204 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5205 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5206 "! TARGET_FPREGS
5207 && (register_operand (operands[0], DFmode)
5208 || reg_or_0_operand (operands[1], DFmode))"
5209 "@
5210 bis $31,%r1,%0
5211 ldq %0,%1
5212 stq %r1,%0"
5213 [(set_attr "type" "ilog,ild,ist")])
5215 ;; Subregs suck for register allocation. Pretend we can move TFmode
5216 ;; data between general registers until after reload.
5218 (define_insn_and_split "*movtf_internal"
5219 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5220 (match_operand:TF 1 "input_operand" "roG,rG"))]
5221 "register_operand (operands[0], TFmode)
5222 || reg_or_0_operand (operands[1], TFmode)"
5223 "#"
5224 "reload_completed"
5225 [(set (match_dup 0) (match_dup 2))
5226 (set (match_dup 1) (match_dup 3))]
5227 {
5228 alpha_split_tmode_pair (operands, TFmode, true);
5229 })
5231 (define_expand "movsf"
5232 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5233 (match_operand:SF 1 "general_operand" ""))]
5234 ""
5235 {
5236 if (GET_CODE (operands[0]) == MEM
5237 && ! reg_or_0_operand (operands[1], SFmode))
5238 operands[1] = force_reg (SFmode, operands[1]);
5239 })
5241 (define_expand "movdf"
5242 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5243 (match_operand:DF 1 "general_operand" ""))]
5244 ""
5245 {
5246 if (GET_CODE (operands[0]) == MEM
5247 && ! reg_or_0_operand (operands[1], DFmode))
5248 operands[1] = force_reg (DFmode, operands[1]);
5249 })
5251 (define_expand "movtf"
5252 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5253 (match_operand:TF 1 "general_operand" ""))]
5254 ""
5255 {
5256 if (GET_CODE (operands[0]) == MEM
5257 && ! reg_or_0_operand (operands[1], TFmode))
5258 operands[1] = force_reg (TFmode, operands[1]);
5259 })
5261 (define_insn "*movsi"
5262 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5263 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5264 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5265 && (register_operand (operands[0], SImode)
5266 || reg_or_0_operand (operands[1], SImode))"
5267 "@
5268 bis $31,%r1,%0
5269 lda %0,%1($31)
5270 ldah %0,%h1($31)
5271 #
5272 ldl %0,%1
5273 stl %r1,%0"
5274 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5276 (define_insn "*movsi_nt_vms"
5277 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5278 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5279 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5280 && (register_operand (operands[0], SImode)
5281 || reg_or_0_operand (operands[1], SImode))"
5282 "@
5283 bis $31,%1,%0
5284 lda %0,%1
5285 ldah %0,%h1
5286 lda %0,%1
5287 #
5288 ldl %0,%1
5289 stl %r1,%0"
5290 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5292 (define_insn "*movhi_nobwx"
5293 [(set (match_operand:HI 0 "register_operand" "=r,r")
5294 (match_operand:HI 1 "input_operand" "rJ,n"))]
5295 "! TARGET_BWX
5296 && (register_operand (operands[0], HImode)
5297 || register_operand (operands[1], HImode))"
5298 "@
5299 bis $31,%r1,%0
5300 lda %0,%L1($31)"
5301 [(set_attr "type" "ilog,iadd")])
5303 (define_insn "*movhi_bwx"
5304 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5305 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5306 "TARGET_BWX
5307 && (register_operand (operands[0], HImode)
5308 || reg_or_0_operand (operands[1], HImode))"
5309 "@
5310 bis $31,%r1,%0
5311 lda %0,%L1($31)
5312 ldwu %0,%1
5313 stw %r1,%0"
5314 [(set_attr "type" "ilog,iadd,ild,ist")])
5316 (define_insn "*movqi_nobwx"
5317 [(set (match_operand:QI 0 "register_operand" "=r,r")
5318 (match_operand:QI 1 "input_operand" "rJ,n"))]
5319 "! TARGET_BWX
5320 && (register_operand (operands[0], QImode)
5321 || register_operand (operands[1], QImode))"
5322 "@
5323 bis $31,%r1,%0
5324 lda %0,%L1($31)"
5325 [(set_attr "type" "ilog,iadd")])
5327 (define_insn "*movqi_bwx"
5328 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5329 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5330 "TARGET_BWX
5331 && (register_operand (operands[0], QImode)
5332 || reg_or_0_operand (operands[1], QImode))"
5333 "@
5334 bis $31,%r1,%0
5335 lda %0,%L1($31)
5336 ldbu %0,%1
5337 stb %r1,%0"
5338 [(set_attr "type" "ilog,iadd,ild,ist")])
5340 ;; We do two major things here: handle mem->mem and construct long
5341 ;; constants.
5343 (define_expand "movsi"
5344 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5345 (match_operand:SI 1 "general_operand" ""))]
5346 ""
5347 {
5348 if (alpha_expand_mov (SImode, operands))
5349 DONE;
5350 })
5352 ;; Split a load of a large constant into the appropriate two-insn
5353 ;; sequence.
5355 (define_split
5356 [(set (match_operand:SI 0 "register_operand" "")
5357 (match_operand:SI 1 "non_add_const_operand" ""))]
5358 ""
5359 [(const_int 0)]
5360 {
5361 if (alpha_split_const_mov (SImode, operands))
5362 DONE;
5363 else
5364 FAIL;
5365 })
5367 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5368 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5369 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5370 ;; notes and update LABEL_NUSES because this is not done automatically.
5371 ;; Labels may be incorrectly deleted if we don't do this.
5372 ;;
5373 ;; Describing what the individual instructions do correctly is too complicated
5374 ;; so use UNSPECs for each of the three parts of an address.
5376 (define_split
5377 [(set (match_operand:DI 0 "register_operand" "")
5378 (match_operand:DI 1 "symbolic_operand" ""))]
5379 "TARGET_ABI_UNICOSMK && reload_completed"
5380 [(const_int 0)]
5381 {
5382 rtx insn1, insn2, insn3;
5384 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5385 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5386 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5387 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5388 set_unique_reg_note (insn3, REG_EQUAL, operands[1]);
5390 if (GET_CODE (operands[1]) == LABEL_REF)
5391 {
5392 rtx label;
5394 label = XEXP (operands[1], 0);
5395 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5396 REG_NOTES (insn1));
5397 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5398 REG_NOTES (insn2));
5399 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5400 REG_NOTES (insn3));
5401 LABEL_NUSES (label) += 3;
5402 }
5403 DONE;
5404 })
5406 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5408 (define_insn "umk_laum"
5409 [(set (match_operand:DI 0 "register_operand" "=r")
5410 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5411 UNSPEC_UMK_LAUM))]
5412 "TARGET_ABI_UNICOSMK"
5413 "laum %r0,%t1($31)"
5414 [(set_attr "type" "iadd")])
5416 (define_insn "umk_lalm"
5417 [(set (match_operand:DI 0 "register_operand" "=r")
5418 (plus:DI (match_operand:DI 1 "register_operand" "r")
5419 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5420 UNSPEC_UMK_LALM)))]
5421 "TARGET_ABI_UNICOSMK"
5422 "lalm %r0,%t2(%r1)"
5423 [(set_attr "type" "iadd")])
5425 (define_insn "umk_lal"
5426 [(set (match_operand:DI 0 "register_operand" "=r")
5427 (plus:DI (match_operand:DI 1 "register_operand" "r")
5428 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5429 UNSPEC_UMK_LAL)))]
5430 "TARGET_ABI_UNICOSMK"
5431 "lal %r0,%t2(%r1)"
5432 [(set_attr "type" "iadd")])
5434 ;; Add a new call information word to the current function's list of CIWs
5435 ;; and load its index into $25. Doing it here ensures that the CIW will be
5436 ;; associated with the correct function even in the presence of inlining.
5438 (define_insn "*umk_load_ciw"
5439 [(set (reg:DI 25)
5440 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5441 "TARGET_ABI_UNICOSMK"
5442 {
5443 operands[0] = unicosmk_add_call_info_word (operands[0]);
5444 return "lda $25,%0";
5445 }
5446 [(set_attr "type" "iadd")])
5448 (define_insn "*movdi_er_low_l"
5449 [(set (match_operand:DI 0 "register_operand" "=r")
5450 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5451 (match_operand:DI 2 "local_symbolic_operand" "")))]
5452 "TARGET_EXPLICIT_RELOCS"
5453 {
5454 if (true_regnum (operands[1]) == 29)
5455 return "lda %0,%2(%1)\t\t!gprel";
5456 else
5457 return "lda %0,%2(%1)\t\t!gprellow";
5458 }
5459 [(set_attr "usegp" "yes")])
5461 (define_split
5462 [(set (match_operand:DI 0 "register_operand" "")
5463 (match_operand:DI 1 "small_symbolic_operand" ""))]
5464 "TARGET_EXPLICIT_RELOCS && reload_completed"
5465 [(set (match_dup 0)
5466 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5467 "operands[2] = pic_offset_table_rtx;")
5469 (define_split
5470 [(set (match_operand:DI 0 "register_operand" "")
5471 (match_operand:DI 1 "local_symbolic_operand" ""))]
5472 "TARGET_EXPLICIT_RELOCS && reload_completed"
5473 [(set (match_dup 0)
5474 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5475 (set (match_dup 0)
5476 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5477 "operands[2] = pic_offset_table_rtx;")
5479 (define_split
5480 [(match_operand 0 "some_small_symbolic_operand" "")]
5481 ""
5482 [(match_dup 0)]
5483 "operands[0] = split_small_symbolic_operand (operands[0]);")
5485 ;; Accepts any symbolic, not just global, since function calls that
5486 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5487 (define_insn "movdi_er_high_g"
5488 [(set (match_operand:DI 0 "register_operand" "=r")
5489 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5490 (match_operand:DI 2 "symbolic_operand" "")
5491 (match_operand 3 "const_int_operand" "")]
5492 UNSPEC_LITERAL))]
5493 "TARGET_EXPLICIT_RELOCS"
5494 {
5495 if (INTVAL (operands[3]) == 0)
5496 return "ldq %0,%2(%1)\t\t!literal";
5497 else
5498 return "ldq %0,%2(%1)\t\t!literal!%3";
5499 }
5500 [(set_attr "type" "ldsym")])
5502 (define_split
5503 [(set (match_operand:DI 0 "register_operand" "")
5504 (match_operand:DI 1 "global_symbolic_operand" ""))]
5505 "TARGET_EXPLICIT_RELOCS && reload_completed"
5506 [(set (match_dup 0)
5507 (unspec:DI [(match_dup 2)
5508 (match_dup 1)
5509 (const_int 0)] UNSPEC_LITERAL))]
5510 "operands[2] = pic_offset_table_rtx;")
5512 (define_insn "movdi_er_tlsgd"
5513 [(set (match_operand:DI 0 "register_operand" "=r")
5514 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5515 (match_operand:DI 2 "symbolic_operand" "")
5516 (match_operand 3 "const_int_operand" "")]
5517 UNSPEC_TLSGD))]
5518 "HAVE_AS_TLS"
5519 {
5520 if (INTVAL (operands[3]) == 0)
5521 return "lda %0,%2(%1)\t\t!tlsgd";
5522 else
5523 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5524 })
5526 (define_insn "movdi_er_tlsldm"
5527 [(set (match_operand:DI 0 "register_operand" "=r")
5528 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5529 (match_operand 2 "const_int_operand" "")]
5530 UNSPEC_TLSLDM))]
5531 "HAVE_AS_TLS"
5532 {
5533 if (INTVAL (operands[2]) == 0)
5534 return "lda %0,%&(%1)\t\t!tlsldm";
5535 else
5536 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5537 })
5539 (define_insn "*movdi_er_gotdtp"
5540 [(set (match_operand:DI 0 "register_operand" "=r")
5541 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5542 (match_operand:DI 2 "symbolic_operand" "")]
5543 UNSPEC_DTPREL))]
5544 "HAVE_AS_TLS"
5545 "ldq %0,%2(%1)\t\t!gotdtprel"
5546 [(set_attr "type" "ild")
5547 (set_attr "usegp" "yes")])
5549 (define_split
5550 [(set (match_operand:DI 0 "register_operand" "")
5551 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5552 "HAVE_AS_TLS && reload_completed"
5553 [(set (match_dup 0)
5554 (unspec:DI [(match_dup 2)
5555 (match_dup 1)] UNSPEC_DTPREL))]
5556 {
5557 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5558 operands[2] = pic_offset_table_rtx;
5559 })
5561 (define_insn "*movdi_er_gottp"
5562 [(set (match_operand:DI 0 "register_operand" "=r")
5563 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5564 (match_operand:DI 2 "symbolic_operand" "")]
5565 UNSPEC_TPREL))]
5566 "HAVE_AS_TLS"
5567 "ldq %0,%2(%1)\t\t!gottprel"
5568 [(set_attr "type" "ild")
5569 (set_attr "usegp" "yes")])
5571 (define_split
5572 [(set (match_operand:DI 0 "register_operand" "")
5573 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5574 "HAVE_AS_TLS && reload_completed"
5575 [(set (match_dup 0)
5576 (unspec:DI [(match_dup 2)
5577 (match_dup 1)] UNSPEC_TPREL))]
5578 {
5579 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5580 operands[2] = pic_offset_table_rtx;
5581 })
5583 (define_insn "*movdi_er_nofix"
5584 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5585 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5586 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5587 && (register_operand (operands[0], DImode)
5588 || reg_or_0_operand (operands[1], DImode))"
5589 "@
5590 mov %r1,%0
5591 lda %0,%1($31)
5592 ldah %0,%h1($31)
5593 #
5594 #
5595 #
5596 ldq%A1 %0,%1
5597 stq%A0 %r1,%0
5598 fmov %R1,%0
5599 ldt %0,%1
5600 stt %R1,%0"
5601 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5602 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5604 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5605 ;; have been split up by the rules above but we shouldn't reject the
5606 ;; possibility of them getting through.
5608 (define_insn "*movdi_nofix"
5609 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5610 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5611 "! TARGET_FIX
5612 && (register_operand (operands[0], DImode)
5613 || reg_or_0_operand (operands[1], DImode))"
5614 "@
5615 bis $31,%r1,%0
5616 lda %0,%1($31)
5617 ldah %0,%h1($31)
5618 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5619 lda %0,%1
5620 #
5621 ldq%A1 %0,%1
5622 stq%A0 %r1,%0
5623 cpys %R1,%R1,%0
5624 ldt %0,%1
5625 stt %R1,%0"
5626 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5627 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5629 (define_insn "*movdi_er_fix"
5630 [(set (match_operand:DI 0 "nonimmediate_operand"
5631 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5632 (match_operand:DI 1 "input_operand"
5633 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5634 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5635 && (register_operand (operands[0], DImode)
5636 || reg_or_0_operand (operands[1], DImode))"
5637 "@
5638 mov %r1,%0
5639 lda %0,%1($31)
5640 ldah %0,%h1($31)
5641 #
5642 #
5643 #
5644 ldq%A1 %0,%1
5645 stq%A0 %r1,%0
5646 fmov %R1,%0
5647 ldt %0,%1
5648 stt %R1,%0
5649 ftoit %1,%0
5650 itoft %1,%0"
5651 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5652 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5654 (define_insn "*movdi_fix"
5655 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5656 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5657 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5658 && (register_operand (operands[0], DImode)
5659 || reg_or_0_operand (operands[1], DImode))"
5660 "@
5661 bis $31,%r1,%0
5662 lda %0,%1($31)
5663 ldah %0,%h1($31)
5664 lda %0,%1
5665 #
5666 ldq%A1 %0,%1
5667 stq%A0 %r1,%0
5668 cpys %R1,%R1,%0
5669 ldt %0,%1
5670 stt %R1,%0
5671 ftoit %1,%0
5672 itoft %1,%0"
5673 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5675 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5676 ;; often appears dead to the life analysis code, at which point we
5677 ;; die for emitting dead prologue instructions. Force this live.
5679 (define_insn "force_movdi"
5680 [(set (match_operand:DI 0 "register_operand" "=r")
5681 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5682 UNSPECV_FORCE_MOV))]
5683 ""
5684 "mov %1,%0"
5685 [(set_attr "type" "ilog")])
5687 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5688 ;; memory, and construct long 32-bit constants.
5690 (define_expand "movdi"
5691 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5692 (match_operand:DI 1 "general_operand" ""))]
5693 ""
5694 {
5695 if (alpha_expand_mov (DImode, operands))
5696 DONE;
5697 })
5699 ;; Split a load of a large constant into the appropriate two-insn
5700 ;; sequence.
5702 (define_split
5703 [(set (match_operand:DI 0 "register_operand" "")
5704 (match_operand:DI 1 "non_add_const_operand" ""))]
5705 ""
5706 [(const_int 0)]
5707 {
5708 if (alpha_split_const_mov (DImode, operands))
5709 DONE;
5710 else
5711 FAIL;
5712 })
5714 ;; We need to prevent reload from splitting TImode moves, because it
5715 ;; might decide to overwrite a pointer with the value it points to.
5716 ;; In that case we have to do the loads in the appropriate order so
5717 ;; that the pointer is not destroyed too early.
5719 (define_insn_and_split "*movti_internal"
5720 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
5721 (match_operand:TI 1 "input_operand" "roJ,rJ"))]
5722 "(register_operand (operands[0], TImode)
5723 /* Prevent rematerialization of constants. */
5724 && ! CONSTANT_P (operands[1]))
5725 || reg_or_0_operand (operands[1], TImode)"
5726 "#"
5727 "reload_completed"
5728 [(set (match_dup 0) (match_dup 2))
5729 (set (match_dup 1) (match_dup 3))]
5730 {
5731 alpha_split_tmode_pair (operands, TImode, true);
5732 })
5734 (define_expand "movti"
5735 [(set (match_operand:TI 0 "nonimmediate_operand" "")
5736 (match_operand:TI 1 "general_operand" ""))]
5737 ""
5738 {
5739 if (GET_CODE (operands[0]) == MEM
5740 && ! reg_or_0_operand (operands[1], TImode))
5741 operands[1] = force_reg (TImode, operands[1]);
5743 if (operands[1] == const0_rtx)
5744 ;
5745 /* We must put 64-bit constants in memory. We could keep the
5746 32-bit constants in TImode and rely on the splitter, but
5747 this doesn't seem to be worth the pain. */
5748 else if (GET_CODE (operands[1]) == CONST_INT
5749 || GET_CODE (operands[1]) == CONST_DOUBLE)
5750 {
5751 rtx in[2], out[2], target;
5753 gcc_assert (!no_new_pseudos);
5755 split_double (operands[1], &in[0], &in[1]);
5757 if (in[0] == const0_rtx)
5758 out[0] = const0_rtx;
5759 else
5760 {
5761 out[0] = gen_reg_rtx (DImode);
5762 emit_insn (gen_movdi (out[0], in[0]));
5763 }
5765 if (in[1] == const0_rtx)
5766 out[1] = const0_rtx;
5767 else
5768 {
5769 out[1] = gen_reg_rtx (DImode);
5770 emit_insn (gen_movdi (out[1], in[1]));
5771 }
5773 if (GET_CODE (operands[0]) != REG)
5774 target = gen_reg_rtx (TImode);
5775 else
5776 target = operands[0];
5778 emit_insn (gen_movdi (gen_rtx_SUBREG (DImode, target, 0), out[0]));
5779 emit_insn (gen_movdi (gen_rtx_SUBREG (DImode, target, 8), out[1]));
5781 if (target != operands[0])
5782 emit_insn (gen_rtx_SET (VOIDmode, operands[0], target));
5784 DONE;
5785 }
5786 })
5788 ;; These are the partial-word cases.
5789 ;;
5790 ;; First we have the code to load an aligned word. Operand 0 is the register
5791 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5792 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5793 ;; number of bits within the word that the value is. Operand 3 is an SImode
5794 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5795 ;; same register. It is allowed to conflict with operand 1 as well.
5797 (define_expand "aligned_loadqi"
5798 [(set (match_operand:SI 3 "register_operand" "")
5799 (match_operand:SI 1 "memory_operand" ""))
5800 (set (match_operand:DI 0 "register_operand" "")
5801 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5802 (const_int 8)
5803 (match_operand:DI 2 "const_int_operand" "")))]
5805 ""
5806 "")
5808 (define_expand "aligned_loadhi"
5809 [(set (match_operand:SI 3 "register_operand" "")
5810 (match_operand:SI 1 "memory_operand" ""))
5811 (set (match_operand:DI 0 "register_operand" "")
5812 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5813 (const_int 16)
5814 (match_operand:DI 2 "const_int_operand" "")))]
5816 ""
5817 "")
5819 ;; Similar for unaligned loads, where we use the sequence from the
5820 ;; Alpha Architecture manual. We have to distinguish between little-endian
5821 ;; and big-endian systems as the sequences are different.
5822 ;;
5823 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5824 ;; operand 3 can overlap the input and output registers.
5826 (define_expand "unaligned_loadqi"
5827 [(use (match_operand:DI 0 "register_operand" ""))
5828 (use (match_operand:DI 1 "address_operand" ""))
5829 (use (match_operand:DI 2 "register_operand" ""))
5830 (use (match_operand:DI 3 "register_operand" ""))]
5831 ""
5832 {
5833 if (WORDS_BIG_ENDIAN)
5834 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5835 operands[2], operands[3]));
5836 else
5837 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5838 operands[2], operands[3]));
5839 DONE;
5840 })
5842 (define_expand "unaligned_loadqi_le"
5843 [(set (match_operand:DI 2 "register_operand" "")
5844 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5845 (const_int -8))))
5846 (set (match_operand:DI 3 "register_operand" "")
5847 (match_dup 1))
5848 (set (match_operand:DI 0 "register_operand" "")
5849 (zero_extract:DI (match_dup 2)
5850 (const_int 8)
5851 (ashift:DI (match_dup 3) (const_int 3))))]
5852 "! WORDS_BIG_ENDIAN"
5853 "")
5855 (define_expand "unaligned_loadqi_be"
5856 [(set (match_operand:DI 2 "register_operand" "")
5857 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5858 (const_int -8))))
5859 (set (match_operand:DI 3 "register_operand" "")
5860 (match_dup 1))
5861 (set (match_operand:DI 0 "register_operand" "")
5862 (zero_extract:DI (match_dup 2)
5863 (const_int 8)
5864 (minus:DI
5865 (const_int 56)
5866 (ashift:DI (match_dup 3) (const_int 3)))))]
5867 "WORDS_BIG_ENDIAN"
5868 "")
5870 (define_expand "unaligned_loadhi"
5871 [(use (match_operand:DI 0 "register_operand" ""))
5872 (use (match_operand:DI 1 "address_operand" ""))
5873 (use (match_operand:DI 2 "register_operand" ""))
5874 (use (match_operand:DI 3 "register_operand" ""))]
5875 ""
5876 {
5877 if (WORDS_BIG_ENDIAN)
5878 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5879 operands[2], operands[3]));
5880 else
5881 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5882 operands[2], operands[3]));
5883 DONE;
5884 })
5886 (define_expand "unaligned_loadhi_le"
5887 [(set (match_operand:DI 2 "register_operand" "")
5888 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5889 (const_int -8))))
5890 (set (match_operand:DI 3 "register_operand" "")
5891 (match_dup 1))
5892 (set (match_operand:DI 0 "register_operand" "")
5893 (zero_extract:DI (match_dup 2)
5894 (const_int 16)
5895 (ashift:DI (match_dup 3) (const_int 3))))]
5896 "! WORDS_BIG_ENDIAN"
5897 "")
5899 (define_expand "unaligned_loadhi_be"
5900 [(set (match_operand:DI 2 "register_operand" "")
5901 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5902 (const_int -8))))
5903 (set (match_operand:DI 3 "register_operand" "")
5904 (plus:DI (match_dup 1) (const_int 1)))
5905 (set (match_operand:DI 0 "register_operand" "")
5906 (zero_extract:DI (match_dup 2)
5907 (const_int 16)
5908 (minus:DI
5909 (const_int 56)
5910 (ashift:DI (match_dup 3) (const_int 3)))))]
5911 "WORDS_BIG_ENDIAN"
5912 "")
5914 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5915 ;; aligned SImode MEM. Operand 1 is the register containing the
5916 ;; byte or word to store. Operand 2 is the number of bits within the word that
5917 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5919 (define_expand "aligned_store"
5920 [(set (match_operand:SI 3 "register_operand" "")
5921 (match_operand:SI 0 "memory_operand" ""))
5922 (set (subreg:DI (match_dup 3) 0)
5923 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5924 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5925 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5926 (match_operand:DI 2 "const_int_operand" "")))
5927 (set (subreg:DI (match_dup 4) 0)
5928 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5929 (set (match_dup 0) (match_dup 4))]
5930 ""
5931 {
5932 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5933 << INTVAL (operands[2])));
5934 })
5936 ;; For the unaligned byte and halfword cases, we use code similar to that
5937 ;; in the ;; Architecture book, but reordered to lower the number of registers
5938 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5939 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5940 ;; be the same temporary, if desired. If the address is in a register,
5941 ;; operand 2 can be that register.
5943 (define_expand "unaligned_storeqi"
5944 [(use (match_operand:DI 0 "address_operand" ""))
5945 (use (match_operand:QI 1 "register_operand" ""))
5946 (use (match_operand:DI 2 "register_operand" ""))
5947 (use (match_operand:DI 3 "register_operand" ""))
5948 (use (match_operand:DI 4 "register_operand" ""))]
5949 ""
5950 {
5951 if (WORDS_BIG_ENDIAN)
5952 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5953 operands[2], operands[3],
5954 operands[4]));
5955 else
5956 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5957 operands[2], operands[3],
5958 operands[4]));
5959 DONE;
5960 })
5962 (define_expand "unaligned_storeqi_le"
5963 [(set (match_operand:DI 3 "register_operand" "")
5964 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5965 (const_int -8))))
5966 (set (match_operand:DI 2 "register_operand" "")
5967 (match_dup 0))
5968 (set (match_dup 3)
5969 (and:DI (not:DI (ashift:DI (const_int 255)
5970 (ashift:DI (match_dup 2) (const_int 3))))
5971 (match_dup 3)))
5972 (set (match_operand:DI 4 "register_operand" "")
5973 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5974 (ashift:DI (match_dup 2) (const_int 3))))
5975 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5976 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5977 (match_dup 4))]
5978 "! WORDS_BIG_ENDIAN"
5979 "")
5981 (define_expand "unaligned_storeqi_be"
5982 [(set (match_operand:DI 3 "register_operand" "")
5983 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5984 (const_int -8))))
5985 (set (match_operand:DI 2 "register_operand" "")
5986 (match_dup 0))
5987 (set (match_dup 3)
5988 (and:DI (not:DI (ashift:DI (const_int 255)
5989 (minus:DI (const_int 56)
5990 (ashift:DI (match_dup 2) (const_int 3)))))
5991 (match_dup 3)))
5992 (set (match_operand:DI 4 "register_operand" "")
5993 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5994 (minus:DI (const_int 56)
5995 (ashift:DI (match_dup 2) (const_int 3)))))
5996 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5997 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5998 (match_dup 4))]
5999 "WORDS_BIG_ENDIAN"
6000 "")
6002 (define_expand "unaligned_storehi"
6003 [(use (match_operand:DI 0 "address_operand" ""))
6004 (use (match_operand:HI 1 "register_operand" ""))
6005 (use (match_operand:DI 2 "register_operand" ""))
6006 (use (match_operand:DI 3 "register_operand" ""))
6007 (use (match_operand:DI 4 "register_operand" ""))]
6008 ""
6009 {
6010 if (WORDS_BIG_ENDIAN)
6011 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
6012 operands[2], operands[3],
6013 operands[4]));
6014 else
6015 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
6016 operands[2], operands[3],
6017 operands[4]));
6018 DONE;
6019 })
6021 (define_expand "unaligned_storehi_le"
6022 [(set (match_operand:DI 3 "register_operand" "")
6023 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
6024 (const_int -8))))
6025 (set (match_operand:DI 2 "register_operand" "")
6026 (match_dup 0))
6027 (set (match_dup 3)
6028 (and:DI (not:DI (ashift:DI (const_int 65535)
6029 (ashift:DI (match_dup 2) (const_int 3))))
6030 (match_dup 3)))
6031 (set (match_operand:DI 4 "register_operand" "")
6032 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6033 (ashift:DI (match_dup 2) (const_int 3))))
6034 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6035 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6036 (match_dup 4))]
6037 "! WORDS_BIG_ENDIAN"
6038 "")
6040 (define_expand "unaligned_storehi_be"
6041 [(set (match_operand:DI 3 "register_operand" "")
6042 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
6043 (const_int -8))))
6044 (set (match_operand:DI 2 "register_operand" "")
6045 (plus:DI (match_dup 0) (const_int 1)))
6046 (set (match_dup 3)
6047 (and:DI (not:DI (ashift:DI
6048 (const_int 65535)
6049 (minus:DI (const_int 56)
6050 (ashift:DI (match_dup 2) (const_int 3)))))
6051 (match_dup 3)))
6052 (set (match_operand:DI 4 "register_operand" "")
6053 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6054 (minus:DI (const_int 56)
6055 (ashift:DI (match_dup 2) (const_int 3)))))
6056 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6057 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6058 (match_dup 4))]
6059 "WORDS_BIG_ENDIAN"
6060 "")
6061 \f
6062 ;; Here are the define_expand's for QI and HI moves that use the above
6063 ;; patterns. We have the normal sets, plus the ones that need scratch
6064 ;; registers for reload.
6066 (define_expand "movqi"
6067 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6068 (match_operand:QI 1 "general_operand" ""))]
6069 ""
6070 {
6071 if (TARGET_BWX
6072 ? alpha_expand_mov (QImode, operands)
6073 : alpha_expand_mov_nobwx (QImode, operands))
6074 DONE;
6075 })
6077 (define_expand "movhi"
6078 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6079 (match_operand:HI 1 "general_operand" ""))]
6080 ""
6081 {
6082 if (TARGET_BWX
6083 ? alpha_expand_mov (HImode, operands)
6084 : alpha_expand_mov_nobwx (HImode, operands))
6085 DONE;
6086 })
6088 ;; Here are the versions for reload. Note that in the unaligned cases
6089 ;; we know that the operand must not be a pseudo-register because stack
6090 ;; slots are always aligned references.
6092 (define_expand "reload_inqi"
6093 [(parallel [(match_operand:QI 0 "register_operand" "=r")
6094 (match_operand:QI 1 "any_memory_operand" "m")
6095 (match_operand:TI 2 "register_operand" "=&r")])]
6096 "! TARGET_BWX"
6097 {
6098 rtx scratch, seq;
6100 if (aligned_memory_operand (operands[1], QImode))
6101 {
6102 seq = gen_reload_inqi_help (operands[0], operands[1],
6103 gen_rtx_REG (SImode, REGNO (operands[2])));
6104 }
6105 else
6106 {
6107 rtx addr;
6109 /* It is possible that one of the registers we got for operands[2]
6110 might coincide with that of operands[0] (which is why we made
6111 it TImode). Pick the other one to use as our scratch. */
6112 if (REGNO (operands[0]) == REGNO (operands[2]))
6113 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6114 else
6115 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6117 addr = get_unaligned_address (operands[1]);
6118 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6119 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
6120 alpha_set_memflags (seq, operands[1]);
6121 }
6122 emit_insn (seq);
6123 DONE;
6124 })
6126 (define_expand "reload_inhi"
6127 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6128 (match_operand:HI 1 "any_memory_operand" "m")
6129 (match_operand:TI 2 "register_operand" "=&r")])]
6130 "! TARGET_BWX"
6131 {
6132 rtx scratch, seq;
6134 if (aligned_memory_operand (operands[1], HImode))
6135 {
6136 seq = gen_reload_inhi_help (operands[0], operands[1],
6137 gen_rtx_REG (SImode, REGNO (operands[2])));
6138 }
6139 else
6140 {
6141 rtx addr;
6143 /* It is possible that one of the registers we got for operands[2]
6144 might coincide with that of operands[0] (which is why we made
6145 it TImode). Pick the other one to use as our scratch. */
6146 if (REGNO (operands[0]) == REGNO (operands[2]))
6147 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6148 else
6149 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6151 addr = get_unaligned_address (operands[1]);
6152 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6153 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
6154 alpha_set_memflags (seq, operands[1]);
6155 }
6156 emit_insn (seq);
6157 DONE;
6158 })
6160 (define_expand "reload_outqi"
6161 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6162 (match_operand:QI 1 "register_operand" "r")
6163 (match_operand:TI 2 "register_operand" "=&r")])]
6164 "! TARGET_BWX"
6165 {
6166 if (aligned_memory_operand (operands[0], QImode))
6167 {
6168 emit_insn (gen_reload_outqi_help
6169 (operands[0], operands[1],
6170 gen_rtx_REG (SImode, REGNO (operands[2])),
6171 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6172 }
6173 else
6174 {
6175 rtx addr = get_unaligned_address (operands[0]);
6176 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6177 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6178 rtx scratch3 = scratch1;
6179 rtx seq;
6181 if (GET_CODE (addr) == REG)
6182 scratch1 = addr;
6184 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6185 scratch2, scratch3);
6186 alpha_set_memflags (seq, operands[0]);
6187 emit_insn (seq);
6188 }
6189 DONE;
6190 })
6192 (define_expand "reload_outhi"
6193 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6194 (match_operand:HI 1 "register_operand" "r")
6195 (match_operand:TI 2 "register_operand" "=&r")])]
6196 "! TARGET_BWX"
6197 {
6198 if (aligned_memory_operand (operands[0], HImode))
6199 {
6200 emit_insn (gen_reload_outhi_help
6201 (operands[0], operands[1],
6202 gen_rtx_REG (SImode, REGNO (operands[2])),
6203 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6204 }
6205 else
6206 {
6207 rtx addr = get_unaligned_address (operands[0]);
6208 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6209 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6210 rtx scratch3 = scratch1;
6211 rtx seq;
6213 if (GET_CODE (addr) == REG)
6214 scratch1 = addr;
6216 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6217 scratch2, scratch3);
6218 alpha_set_memflags (seq, operands[0]);
6219 emit_insn (seq);
6220 }
6221 DONE;
6222 })
6224 ;; Helpers for the above. The way reload is structured, we can't
6225 ;; always get a proper address for a stack slot during reload_foo
6226 ;; expansion, so we must delay our address manipulations until after.
6228 (define_insn_and_split "reload_inqi_help"
6229 [(set (match_operand:QI 0 "register_operand" "=r")
6230 (match_operand:QI 1 "memory_operand" "m"))
6231 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6232 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6233 "#"
6234 "! TARGET_BWX && reload_completed"
6235 [(const_int 0)]
6236 {
6237 rtx aligned_mem, bitnum;
6238 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6239 operands[0] = gen_lowpart (DImode, operands[0]);
6240 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6241 operands[2]));
6242 DONE;
6243 })
6245 (define_insn_and_split "reload_inhi_help"
6246 [(set (match_operand:HI 0 "register_operand" "=r")
6247 (match_operand:HI 1 "memory_operand" "m"))
6248 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6249 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6250 "#"
6251 "! TARGET_BWX && reload_completed"
6252 [(const_int 0)]
6253 {
6254 rtx aligned_mem, bitnum;
6255 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6256 operands[0] = gen_lowpart (DImode, operands[0]);
6257 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6258 operands[2]));
6259 DONE;
6260 })
6262 (define_insn_and_split "reload_outqi_help"
6263 [(set (match_operand:QI 0 "memory_operand" "=m")
6264 (match_operand:QI 1 "register_operand" "r"))
6265 (clobber (match_operand:SI 2 "register_operand" "=r"))
6266 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6267 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6268 "#"
6269 "! TARGET_BWX && reload_completed"
6270 [(const_int 0)]
6271 {
6272 rtx aligned_mem, bitnum;
6273 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6274 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6275 operands[2], operands[3]));
6276 DONE;
6277 })
6279 (define_insn_and_split "reload_outhi_help"
6280 [(set (match_operand:HI 0 "memory_operand" "=m")
6281 (match_operand:HI 1 "register_operand" "r"))
6282 (clobber (match_operand:SI 2 "register_operand" "=r"))
6283 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6284 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6285 "#"
6286 "! TARGET_BWX && reload_completed"
6287 [(const_int 0)]
6288 {
6289 rtx aligned_mem, bitnum;
6290 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6291 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6292 operands[2], operands[3]));
6293 DONE;
6294 })
6295 \f
6296 ;; Vector operations
6298 (define_mode_macro VEC [V8QI V4HI V2SI])
6300 (define_expand "mov<mode>"
6301 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6302 (match_operand:VEC 1 "general_operand" ""))]
6303 ""
6304 {
6305 if (alpha_expand_mov (<MODE>mode, operands))
6306 DONE;
6307 })
6309 (define_split
6310 [(set (match_operand:VEC 0 "register_operand" "")
6311 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6312 ""
6313 [(const_int 0)]
6314 {
6315 if (alpha_split_const_mov (<MODE>mode, operands))
6316 DONE;
6317 else
6318 FAIL;
6319 })
6322 (define_expand "movmisalign<mode>"
6323 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6324 (match_operand:VEC 1 "general_operand" ""))]
6325 ""
6326 {
6327 alpha_expand_movmisalign (<MODE>mode, operands);
6328 DONE;
6329 })
6331 (define_insn "*mov<mode>_fix"
6332 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6333 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6334 "TARGET_FIX
6335 && (register_operand (operands[0], <MODE>mode)
6336 || reg_or_0_operand (operands[1], <MODE>mode))"
6337 "@
6338 bis $31,%r1,%0
6339 #
6340 ldq %0,%1
6341 stq %r1,%0
6342 cpys %R1,%R1,%0
6343 ldt %0,%1
6344 stt %R1,%0
6345 ftoit %1,%0
6346 itoft %1,%0"
6347 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6349 (define_insn "*mov<mode>_nofix"
6350 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6351 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6352 "! TARGET_FIX
6353 && (register_operand (operands[0], <MODE>mode)
6354 || reg_or_0_operand (operands[1], <MODE>mode))"
6355 "@
6356 bis $31,%r1,%0
6357 #
6358 ldq %0,%1
6359 stq %r1,%0
6360 cpys %R1,%R1,%0
6361 ldt %0,%1
6362 stt %R1,%0"
6363 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6365 (define_insn "uminv8qi3"
6366 [(set (match_operand:V8QI 0 "register_operand" "=r")
6367 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6368 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6369 "TARGET_MAX"
6370 "minub8 %r1,%r2,%0"
6371 [(set_attr "type" "mvi")])
6373 (define_insn "sminv8qi3"
6374 [(set (match_operand:V8QI 0 "register_operand" "=r")
6375 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6376 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6377 "TARGET_MAX"
6378 "minsb8 %r1,%r2,%0"
6379 [(set_attr "type" "mvi")])
6381 (define_insn "uminv4hi3"
6382 [(set (match_operand:V4HI 0 "register_operand" "=r")
6383 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6384 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6385 "TARGET_MAX"
6386 "minuw4 %r1,%r2,%0"
6387 [(set_attr "type" "mvi")])
6389 (define_insn "sminv4hi3"
6390 [(set (match_operand:V4HI 0 "register_operand" "=r")
6391 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6392 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6393 "TARGET_MAX"
6394 "minsw4 %r1,%r2,%0"
6395 [(set_attr "type" "mvi")])
6397 (define_insn "umaxv8qi3"
6398 [(set (match_operand:V8QI 0 "register_operand" "=r")
6399 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6400 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6401 "TARGET_MAX"
6402 "maxub8 %r1,%r2,%0"
6403 [(set_attr "type" "mvi")])
6405 (define_insn "smaxv8qi3"
6406 [(set (match_operand:V8QI 0 "register_operand" "=r")
6407 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6408 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6409 "TARGET_MAX"
6410 "maxsb8 %r1,%r2,%0"
6411 [(set_attr "type" "mvi")])
6413 (define_insn "umaxv4hi3"
6414 [(set (match_operand:V4HI 0 "register_operand" "=r")
6415 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6416 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6417 "TARGET_MAX"
6418 "maxuw4 %r1,%r2,%0"
6419 [(set_attr "type" "mvi")])
6421 (define_insn "smaxv4hi3"
6422 [(set (match_operand:V4HI 0 "register_operand" "=r")
6423 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6424 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6425 "TARGET_MAX"
6426 "maxsw4 %r1,%r2,%0"
6427 [(set_attr "type" "mvi")])
6429 (define_insn "one_cmpl<mode>2"
6430 [(set (match_operand:VEC 0 "register_operand" "=r")
6431 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6432 ""
6433 "ornot $31,%1,%0"
6434 [(set_attr "type" "ilog")])
6436 (define_insn "and<mode>3"
6437 [(set (match_operand:VEC 0 "register_operand" "=r")
6438 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6439 (match_operand:VEC 2 "register_operand" "r")))]
6440 ""
6441 "and %1,%2,%0"
6442 [(set_attr "type" "ilog")])
6444 (define_insn "*andnot<mode>3"
6445 [(set (match_operand:VEC 0 "register_operand" "=r")
6446 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6447 (match_operand:VEC 2 "register_operand" "r")))]
6448 ""
6449 "bic %2,%1,%0"
6450 [(set_attr "type" "ilog")])
6452 (define_insn "ior<mode>3"
6453 [(set (match_operand:VEC 0 "register_operand" "=r")
6454 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6455 (match_operand:VEC 2 "register_operand" "r")))]
6456 ""
6457 "bis %1,%2,%0"
6458 [(set_attr "type" "ilog")])
6460 (define_insn "*iornot<mode>3"
6461 [(set (match_operand:VEC 0 "register_operand" "=r")
6462 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6463 (match_operand:VEC 2 "register_operand" "r")))]
6464 ""
6465 "ornot %2,%1,%0"
6466 [(set_attr "type" "ilog")])
6468 (define_insn "xor<mode>3"
6469 [(set (match_operand:VEC 0 "register_operand" "=r")
6470 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6471 (match_operand:VEC 2 "register_operand" "r")))]
6472 ""
6473 "xor %1,%2,%0"
6474 [(set_attr "type" "ilog")])
6476 (define_insn "*xornot<mode>3"
6477 [(set (match_operand:VEC 0 "register_operand" "=r")
6478 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6479 (match_operand:VEC 2 "register_operand" "r"))))]
6480 ""
6481 "eqv %1,%2,%0"
6482 [(set_attr "type" "ilog")])
6484 (define_expand "vec_shl_<mode>"
6485 [(set (match_operand:VEC 0 "register_operand" "")
6486 (ashift:DI (match_operand:VEC 1 "register_operand" "")
6487 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6488 ""
6489 {
6490 operands[0] = gen_lowpart (DImode, operands[0]);
6491 operands[1] = gen_lowpart (DImode, operands[1]);
6492 })
6494 (define_expand "vec_shr_<mode>"
6495 [(set (match_operand:VEC 0 "register_operand" "")
6496 (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
6497 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6498 ""
6499 {
6500 operands[0] = gen_lowpart (DImode, operands[0]);
6501 operands[1] = gen_lowpart (DImode, operands[1]);
6502 })
6503 \f
6504 ;; Bit field extract patterns which use ext[wlq][lh]
6506 (define_expand "extv"
6507 [(set (match_operand:DI 0 "register_operand" "")
6508 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6509 (match_operand:DI 2 "immediate_operand" "")
6510 (match_operand:DI 3 "immediate_operand" "")))]
6511 ""
6512 {
6513 int ofs;
6515 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6516 if (INTVAL (operands[3]) % 8 != 0
6517 || (INTVAL (operands[2]) != 16
6518 && INTVAL (operands[2]) != 32
6519 && INTVAL (operands[2]) != 64))
6520 FAIL;
6522 /* From mips.md: extract_bit_field doesn't verify that our source
6523 matches the predicate, so we force it to be a MEM here. */
6524 if (GET_CODE (operands[1]) != MEM)
6525 FAIL;
6527 /* The bit number is relative to the mode of operand 1 which is
6528 usually QImode (this might actually be a bug in expmed.c). Note
6529 that the bit number is negative in big-endian mode in this case.
6530 We have to convert that to the offset. */
6531 if (WORDS_BIG_ENDIAN)
6532 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6533 - INTVAL (operands[2]) - INTVAL (operands[3]);
6534 else
6535 ofs = INTVAL (operands[3]);
6537 ofs = ofs / 8;
6539 alpha_expand_unaligned_load (operands[0], operands[1],
6540 INTVAL (operands[2]) / 8,
6541 ofs, 1);
6542 DONE;
6543 })
6545 (define_expand "extzv"
6546 [(set (match_operand:DI 0 "register_operand" "")
6547 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6548 (match_operand:DI 2 "immediate_operand" "")
6549 (match_operand:DI 3 "immediate_operand" "")))]
6550 ""
6551 {
6552 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6553 if (INTVAL (operands[3]) % 8 != 0
6554 || (INTVAL (operands[2]) != 8
6555 && INTVAL (operands[2]) != 16
6556 && INTVAL (operands[2]) != 32
6557 && INTVAL (operands[2]) != 64))
6558 FAIL;
6560 if (GET_CODE (operands[1]) == MEM)
6561 {
6562 int ofs;
6564 /* Fail 8-bit fields, falling back on a simple byte load. */
6565 if (INTVAL (operands[2]) == 8)
6566 FAIL;
6568 /* The bit number is relative to the mode of operand 1 which is
6569 usually QImode (this might actually be a bug in expmed.c). Note
6570 that the bit number is negative in big-endian mode in this case.
6571 We have to convert that to the offset. */
6572 if (WORDS_BIG_ENDIAN)
6573 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6574 - INTVAL (operands[2]) - INTVAL (operands[3]);
6575 else
6576 ofs = INTVAL (operands[3]);
6578 ofs = ofs / 8;
6580 alpha_expand_unaligned_load (operands[0], operands[1],
6581 INTVAL (operands[2]) / 8,
6582 ofs, 0);
6583 DONE;
6584 }
6585 })
6587 (define_expand "insv"
6588 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6589 (match_operand:DI 1 "immediate_operand" "")
6590 (match_operand:DI 2 "immediate_operand" ""))
6591 (match_operand:DI 3 "register_operand" ""))]
6592 ""
6593 {
6594 int ofs;
6596 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6597 if (INTVAL (operands[2]) % 8 != 0
6598 || (INTVAL (operands[1]) != 16
6599 && INTVAL (operands[1]) != 32
6600 && INTVAL (operands[1]) != 64))
6601 FAIL;
6603 /* From mips.md: store_bit_field doesn't verify that our source
6604 matches the predicate, so we force it to be a MEM here. */
6605 if (GET_CODE (operands[0]) != MEM)
6606 FAIL;
6608 /* The bit number is relative to the mode of operand 1 which is
6609 usually QImode (this might actually be a bug in expmed.c). Note
6610 that the bit number is negative in big-endian mode in this case.
6611 We have to convert that to the offset. */
6612 if (WORDS_BIG_ENDIAN)
6613 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6614 - INTVAL (operands[1]) - INTVAL (operands[2]);
6615 else
6616 ofs = INTVAL (operands[2]);
6618 ofs = ofs / 8;
6620 alpha_expand_unaligned_store (operands[0], operands[3],
6621 INTVAL (operands[1]) / 8, ofs);
6622 DONE;
6623 })
6625 ;; Block move/clear, see alpha.c for more details.
6626 ;; Argument 0 is the destination
6627 ;; Argument 1 is the source
6628 ;; Argument 2 is the length
6629 ;; Argument 3 is the alignment
6631 (define_expand "movmemqi"
6632 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6633 (match_operand:BLK 1 "memory_operand" ""))
6634 (use (match_operand:DI 2 "immediate_operand" ""))
6635 (use (match_operand:DI 3 "immediate_operand" ""))])]
6636 ""
6637 {
6638 if (alpha_expand_block_move (operands))
6639 DONE;
6640 else
6641 FAIL;
6642 })
6644 (define_expand "movmemdi"
6645 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6646 (match_operand:BLK 1 "memory_operand" ""))
6647 (use (match_operand:DI 2 "immediate_operand" ""))
6648 (use (match_operand:DI 3 "immediate_operand" ""))
6649 (use (match_dup 4))
6650 (clobber (reg:DI 25))
6651 (clobber (reg:DI 16))
6652 (clobber (reg:DI 17))
6653 (clobber (reg:DI 18))
6654 (clobber (reg:DI 19))
6655 (clobber (reg:DI 20))
6656 (clobber (reg:DI 26))
6657 (clobber (reg:DI 27))])]
6658 "TARGET_ABI_OPEN_VMS"
6659 {
6660 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6661 alpha_need_linkage (XSTR (operands[4], 0), 0);
6662 })
6664 (define_insn "*movmemdi_1"
6665 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6666 (match_operand:BLK 1 "memory_operand" "m,m"))
6667 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6668 (use (match_operand:DI 3 "immediate_operand" ""))
6669 (use (match_operand:DI 4 "call_operand" "i,i"))
6670 (clobber (reg:DI 25))
6671 (clobber (reg:DI 16))
6672 (clobber (reg:DI 17))
6673 (clobber (reg:DI 18))
6674 (clobber (reg:DI 19))
6675 (clobber (reg:DI 20))
6676 (clobber (reg:DI 26))
6677 (clobber (reg:DI 27))]
6678 "TARGET_ABI_OPEN_VMS"
6679 {
6680 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6681 switch (which_alternative)
6682 {
6683 case 0:
6684 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6685 case 1:
6686 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6687 default:
6688 gcc_unreachable ();
6689 }
6690 }
6691 [(set_attr "type" "multi")
6692 (set_attr "length" "28")])
6694 (define_expand "setmemqi"
6695 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6696 (match_operand 2 "const_int_operand" ""))
6697 (use (match_operand:DI 1 "immediate_operand" ""))
6698 (use (match_operand:DI 3 "immediate_operand" ""))])]
6699 ""
6700 {
6701 /* If value to set is not zero, use the library routine. */
6702 if (operands[2] != const0_rtx)
6703 FAIL;
6705 if (alpha_expand_block_clear (operands))
6706 DONE;
6707 else
6708 FAIL;
6709 })
6711 (define_expand "setmemdi"
6712 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6713 (match_operand 2 "const_int_operand" ""))
6714 (use (match_operand:DI 1 "immediate_operand" ""))
6715 (use (match_operand:DI 3 "immediate_operand" ""))
6716 (use (match_dup 4))
6717 (clobber (reg:DI 25))
6718 (clobber (reg:DI 16))
6719 (clobber (reg:DI 17))
6720 (clobber (reg:DI 26))
6721 (clobber (reg:DI 27))])]
6722 "TARGET_ABI_OPEN_VMS"
6723 {
6724 /* If value to set is not zero, use the library routine. */
6725 if (operands[2] != const0_rtx)
6726 FAIL;
6728 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6729 alpha_need_linkage (XSTR (operands[4], 0), 0);
6730 })
6732 (define_insn "*clrmemdi_1"
6733 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6734 (const_int 0))
6735 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6736 (use (match_operand:DI 2 "immediate_operand" ""))
6737 (use (match_operand:DI 3 "call_operand" "i,i"))
6738 (clobber (reg:DI 25))
6739 (clobber (reg:DI 16))
6740 (clobber (reg:DI 17))
6741 (clobber (reg:DI 26))
6742 (clobber (reg:DI 27))]
6743 "TARGET_ABI_OPEN_VMS"
6744 {
6745 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6746 switch (which_alternative)
6747 {
6748 case 0:
6749 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6750 case 1:
6751 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6752 default:
6753 gcc_unreachable ();
6754 }
6755 }
6756 [(set_attr "type" "multi")
6757 (set_attr "length" "24")])
6759 \f
6760 ;; Subroutine of stack space allocation. Perform a stack probe.
6761 (define_expand "probe_stack"
6762 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6763 ""
6764 {
6765 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6766 INTVAL (operands[0])));
6767 MEM_VOLATILE_P (operands[1]) = 1;
6769 operands[0] = const0_rtx;
6770 })
6772 ;; This is how we allocate stack space. If we are allocating a
6773 ;; constant amount of space and we know it is less than 4096
6774 ;; bytes, we need do nothing.
6775 ;;
6776 ;; If it is more than 4096 bytes, we need to probe the stack
6777 ;; periodically.
6778 (define_expand "allocate_stack"
6779 [(set (reg:DI 30)
6780 (plus:DI (reg:DI 30)
6781 (match_operand:DI 1 "reg_or_cint_operand" "")))
6782 (set (match_operand:DI 0 "register_operand" "=r")
6783 (match_dup 2))]
6784 ""
6785 {
6786 if (GET_CODE (operands[1]) == CONST_INT
6787 && INTVAL (operands[1]) < 32768)
6788 {
6789 if (INTVAL (operands[1]) >= 4096)
6790 {
6791 /* We do this the same way as in the prologue and generate explicit
6792 probes. Then we update the stack by the constant. */
6794 int probed = 4096;
6796 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6797 while (probed + 8192 < INTVAL (operands[1]))
6798 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6800 if (probed + 4096 < INTVAL (operands[1]))
6801 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6802 }
6804 operands[1] = GEN_INT (- INTVAL (operands[1]));
6805 operands[2] = virtual_stack_dynamic_rtx;
6806 }
6807 else
6808 {
6809 rtx out_label = 0;
6810 rtx loop_label = gen_label_rtx ();
6811 rtx want = gen_reg_rtx (Pmode);
6812 rtx tmp = gen_reg_rtx (Pmode);
6813 rtx memref;
6815 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6816 force_reg (Pmode, operands[1])));
6817 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6819 if (GET_CODE (operands[1]) != CONST_INT)
6820 {
6821 out_label = gen_label_rtx ();
6822 emit_insn (gen_cmpdi (want, tmp));
6823 emit_jump_insn (gen_bgeu (out_label));
6824 }
6826 emit_label (loop_label);
6827 memref = gen_rtx_MEM (DImode, tmp);
6828 MEM_VOLATILE_P (memref) = 1;
6829 emit_move_insn (memref, const0_rtx);
6830 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6831 emit_insn (gen_cmpdi (tmp, want));
6832 emit_jump_insn (gen_bgtu (loop_label));
6834 memref = gen_rtx_MEM (DImode, want);
6835 MEM_VOLATILE_P (memref) = 1;
6836 emit_move_insn (memref, const0_rtx);
6838 if (out_label)
6839 emit_label (out_label);
6841 emit_move_insn (stack_pointer_rtx, want);
6842 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6843 DONE;
6844 }
6845 })
6847 ;; This is used by alpha_expand_prolog to do the same thing as above,
6848 ;; except we cannot at that time generate new basic blocks, so we hide
6849 ;; the loop in this one insn.
6851 (define_insn "prologue_stack_probe_loop"
6852 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6853 (match_operand:DI 1 "register_operand" "r")]
6854 UNSPECV_PSPL)]
6855 ""
6856 {
6857 operands[2] = gen_label_rtx ();
6858 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6859 CODE_LABEL_NUMBER (operands[2]));
6861 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6862 }
6863 [(set_attr "length" "16")
6864 (set_attr "type" "multi")])
6866 (define_expand "prologue"
6867 [(clobber (const_int 0))]
6868 ""
6869 {
6870 alpha_expand_prologue ();
6871 DONE;
6872 })
6874 ;; These take care of emitting the ldgp insn in the prologue. This will be
6875 ;; an lda/ldah pair and we want to align them properly. So we have two
6876 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6877 ;; and the second of which emits nothing. However, both are marked as type
6878 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6879 ;; with them.
6881 (define_expand "prologue_ldgp"
6882 [(set (match_dup 0)
6883 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6884 (set (match_dup 0)
6885 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6886 ""
6887 {
6888 operands[0] = pic_offset_table_rtx;
6889 operands[1] = gen_rtx_REG (Pmode, 27);
6890 operands[2] = (TARGET_EXPLICIT_RELOCS
6891 ? GEN_INT (alpha_next_sequence_number++)
6892 : const0_rtx);
6893 })
6895 (define_insn "*ldgp_er_1"
6896 [(set (match_operand:DI 0 "register_operand" "=r")
6897 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6898 (match_operand 2 "const_int_operand" "")]
6899 UNSPECV_LDGP1))]
6900 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6901 "ldah %0,0(%1)\t\t!gpdisp!%2"
6902 [(set_attr "cannot_copy" "true")])
6904 (define_insn "*ldgp_er_2"
6905 [(set (match_operand:DI 0 "register_operand" "=r")
6906 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6907 (match_operand 2 "const_int_operand" "")]
6908 UNSPEC_LDGP2))]
6909 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6910 "lda %0,0(%1)\t\t!gpdisp!%2"
6911 [(set_attr "cannot_copy" "true")])
6913 (define_insn "*prologue_ldgp_er_2"
6914 [(set (match_operand:DI 0 "register_operand" "=r")
6915 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6916 (match_operand 2 "const_int_operand" "")]
6917 UNSPECV_PLDGP2))]
6918 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6919 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6920 [(set_attr "cannot_copy" "true")])
6922 (define_insn "*prologue_ldgp_1"
6923 [(set (match_operand:DI 0 "register_operand" "=r")
6924 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6925 (match_operand 2 "const_int_operand" "")]
6926 UNSPECV_LDGP1))]
6927 ""
6928 "ldgp %0,0(%1)\n$%~..ng:"
6929 [(set_attr "cannot_copy" "true")])
6931 (define_insn "*prologue_ldgp_2"
6932 [(set (match_operand:DI 0 "register_operand" "=r")
6933 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6934 (match_operand 2 "const_int_operand" "")]
6935 UNSPECV_PLDGP2))]
6936 ""
6937 "")
6939 ;; The _mcount profiling hook has special calling conventions, and
6940 ;; does not clobber all the registers that a normal call would. So
6941 ;; hide the fact this is a call at all.
6943 (define_insn "prologue_mcount"
6944 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6945 ""
6946 {
6947 if (TARGET_EXPLICIT_RELOCS)
6948 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6949 cannot be called via the PLT. */
6950 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6951 else
6952 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6953 }
6954 [(set_attr "type" "multi")
6955 (set_attr "length" "8")])
6957 (define_insn "init_fp"
6958 [(set (match_operand:DI 0 "register_operand" "=r")
6959 (match_operand:DI 1 "register_operand" "r"))
6960 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6961 ""
6962 "bis $31,%1,%0")
6964 (define_expand "epilogue"
6965 [(return)]
6966 ""
6967 {
6968 alpha_expand_epilogue ();
6969 })
6971 (define_expand "sibcall_epilogue"
6972 [(return)]
6973 "TARGET_ABI_OSF"
6974 {
6975 alpha_expand_epilogue ();
6976 DONE;
6977 })
6979 (define_expand "builtin_longjmp"
6980 [(use (match_operand:DI 0 "register_operand" "r"))]
6981 "TARGET_ABI_OSF"
6982 {
6983 /* The elements of the buffer are, in order: */
6984 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6985 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6986 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6987 rtx pv = gen_rtx_REG (Pmode, 27);
6989 /* This bit is the same as expand_builtin_longjmp. */
6990 emit_move_insn (hard_frame_pointer_rtx, fp);
6991 emit_move_insn (pv, lab);
6992 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6993 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6994 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6996 /* Load the label we are jumping through into $27 so that we know
6997 where to look for it when we get back to setjmp's function for
6998 restoring the gp. */
6999 emit_jump_insn (gen_builtin_longjmp_internal (pv));
7000 emit_barrier ();
7001 DONE;
7002 })
7004 ;; This is effectively a copy of indirect_jump, but constrained such
7005 ;; that register renaming cannot foil our cunning plan with $27.
7006 (define_insn "builtin_longjmp_internal"
7007 [(set (pc)
7008 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
7009 UNSPECV_LONGJMP))]
7010 ""
7011 "jmp $31,(%0),0"
7012 [(set_attr "type" "ibr")])
7014 (define_expand "builtin_setjmp_receiver"
7015 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
7016 "TARGET_ABI_OSF"
7017 "")
7019 (define_insn_and_split "*builtin_setjmp_receiver_1"
7020 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
7021 "TARGET_ABI_OSF"
7022 {
7023 if (TARGET_EXPLICIT_RELOCS)
7024 return "#";
7025 else
7026 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
7027 }
7028 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
7029 [(set (match_dup 1)
7030 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
7031 (set (match_dup 1)
7032 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
7033 {
7034 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
7035 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
7036 UNSPECV_SETJMPR_ER));
7037 operands[1] = pic_offset_table_rtx;
7038 operands[2] = gen_rtx_REG (Pmode, 27);
7039 operands[3] = GEN_INT (alpha_next_sequence_number++);
7040 }
7041 [(set_attr "length" "12")
7042 (set_attr "type" "multi")])
7044 (define_insn "*builtin_setjmp_receiver_er_sl_1"
7045 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7046 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
7047 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
7049 (define_insn "*builtin_setjmp_receiver_er_1"
7050 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7051 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
7052 "br $27,$LSJ%=\n$LSJ%=:"
7053 [(set_attr "type" "ibr")])
7055 (define_expand "exception_receiver"
7056 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
7057 "TARGET_ABI_OSF"
7058 {
7059 if (TARGET_LD_BUGGY_LDGP)
7060 operands[0] = alpha_gp_save_rtx ();
7061 else
7062 operands[0] = const0_rtx;
7063 })
7065 (define_insn "*exception_receiver_2"
7066 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
7067 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
7068 "ldq $29,%0"
7069 [(set_attr "type" "ild")])
7071 (define_insn_and_split "*exception_receiver_1"
7072 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
7073 "TARGET_ABI_OSF"
7074 {
7075 if (TARGET_EXPLICIT_RELOCS)
7076 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
7077 else
7078 return "ldgp $29,0($26)";
7079 }
7080 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
7081 [(set (match_dup 0)
7082 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
7083 (set (match_dup 0)
7084 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
7085 {
7086 operands[0] = pic_offset_table_rtx;
7087 operands[1] = gen_rtx_REG (Pmode, 26);
7088 operands[2] = GEN_INT (alpha_next_sequence_number++);
7089 }
7090 [(set_attr "length" "8")
7091 (set_attr "type" "multi")])
7093 (define_expand "nonlocal_goto_receiver"
7094 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7095 (set (reg:DI 27) (mem:DI (reg:DI 29)))
7096 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7097 (use (reg:DI 27))]
7098 "TARGET_ABI_OPEN_VMS"
7099 "")
7101 (define_insn "arg_home"
7102 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7103 (use (reg:DI 1))
7104 (use (reg:DI 25))
7105 (use (reg:DI 16))
7106 (use (reg:DI 17))
7107 (use (reg:DI 18))
7108 (use (reg:DI 19))
7109 (use (reg:DI 20))
7110 (use (reg:DI 21))
7111 (use (reg:DI 48))
7112 (use (reg:DI 49))
7113 (use (reg:DI 50))
7114 (use (reg:DI 51))
7115 (use (reg:DI 52))
7116 (use (reg:DI 53))
7117 (clobber (mem:BLK (const_int 0)))
7118 (clobber (reg:DI 24))
7119 (clobber (reg:DI 25))
7120 (clobber (reg:DI 0))]
7121 "TARGET_ABI_OPEN_VMS"
7122 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7123 [(set_attr "length" "16")
7124 (set_attr "type" "multi")])
7126 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7128 (define_expand "umk_mismatch_args"
7129 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7130 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7131 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7132 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7133 (const_int 8))
7134 (match_dup 2)))
7135 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7136 "TARGET_ABI_UNICOSMK"
7137 {
7138 operands[1] = gen_reg_rtx (DImode);
7139 operands[2] = gen_reg_rtx (DImode);
7140 operands[3] = gen_reg_rtx (DImode);
7141 })
7143 (define_insn "arg_home_umk"
7144 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7145 (use (reg:DI 1))
7146 (use (reg:DI 2))
7147 (use (reg:DI 16))
7148 (use (reg:DI 17))
7149 (use (reg:DI 18))
7150 (use (reg:DI 19))
7151 (use (reg:DI 20))
7152 (use (reg:DI 21))
7153 (use (reg:DI 48))
7154 (use (reg:DI 49))
7155 (use (reg:DI 50))
7156 (use (reg:DI 51))
7157 (use (reg:DI 52))
7158 (use (reg:DI 53))
7159 (clobber (mem:BLK (const_int 0)))
7160 (parallel [
7161 (clobber (reg:DI 22))
7162 (clobber (reg:DI 23))
7163 (clobber (reg:DI 24))
7164 (clobber (reg:DI 0))
7165 (clobber (reg:DI 1))
7166 (clobber (reg:DI 2))
7167 (clobber (reg:DI 3))
7168 (clobber (reg:DI 4))
7169 (clobber (reg:DI 5))
7170 (clobber (reg:DI 6))
7171 (clobber (reg:DI 7))
7172 (clobber (reg:DI 8))])]
7173 "TARGET_ABI_UNICOSMK"
7174 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7175 [(set_attr "length" "16")
7176 (set_attr "type" "multi")])
7178 ;; Prefetch data.
7179 ;;
7180 ;; On EV4, these instructions are nops -- no load occurs.
7181 ;;
7182 ;; On EV5, these instructions act as a normal load, and thus can trap
7183 ;; if the address is invalid. The OS may (or may not) handle this in
7184 ;; the entMM fault handler and suppress the fault. If so, then this
7185 ;; has the effect of a read prefetch instruction.
7186 ;;
7187 ;; On EV6, these become official prefetch instructions.
7189 (define_insn "prefetch"
7190 [(prefetch (match_operand:DI 0 "address_operand" "p")
7191 (match_operand:DI 1 "const_int_operand" "n")
7192 (match_operand:DI 2 "const_int_operand" "n"))]
7193 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7194 {
7195 /* Interpret "no temporal locality" as this data should be evicted once
7196 it is used. The "evict next" alternatives load the data into the cache
7197 and leave the LRU eviction counter pointing to that block. */
7198 static const char * const alt[2][2] = {
7199 {
7200 "ldq $31,%a0", /* read, evict next */
7201 "ldl $31,%a0", /* read, evict last */
7202 },
7203 {
7204 "ldt $f31,%a0", /* write, evict next */
7205 "lds $f31,%a0", /* write, evict last */
7206 }
7207 };
7209 bool write = INTVAL (operands[1]) != 0;
7210 bool lru = INTVAL (operands[2]) != 0;
7212 return alt[write][lru];
7213 }
7214 [(set_attr "type" "ild")])
7216 ;; Close the trap shadow of preceding instructions. This is generated
7217 ;; by alpha_reorg.
7219 (define_insn "trapb"
7220 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7221 ""
7222 "trapb"
7223 [(set_attr "type" "misc")])
7225 ;; No-op instructions used by machine-dependent reorg to preserve
7226 ;; alignment for instruction issue.
7227 ;; The Unicos/Mk assembler does not support these opcodes.
7229 (define_insn "nop"
7230 [(const_int 0)]
7231 ""
7232 "bis $31,$31,$31"
7233 [(set_attr "type" "ilog")])
7235 (define_insn "fnop"
7236 [(const_int 1)]
7237 "TARGET_FP"
7238 "cpys $f31,$f31,$f31"
7239 [(set_attr "type" "fcpys")])
7241 (define_insn "unop"
7242 [(const_int 2)]
7243 ""
7244 "ldq_u $31,0($30)")
7246 ;; On Unicos/Mk we use a macro for aligning code.
7248 (define_insn "realign"
7249 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7250 UNSPECV_REALIGN)]
7251 ""
7252 {
7253 if (TARGET_ABI_UNICOSMK)
7254 return "gcc@code@align %0";
7255 else
7256 return ".align %0 #realign";
7257 })
7258 \f
7259 ;; Instructions to be emitted from __builtins.
7261 (define_insn "builtin_cmpbge"
7262 [(set (match_operand:DI 0 "register_operand" "=r")
7263 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7264 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7265 UNSPEC_CMPBGE))]
7266 ""
7267 "cmpbge %r1,%2,%0"
7268 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7269 ;; actually differentiate between ILOG and ICMP in the schedule.
7270 [(set_attr "type" "icmp")])
7272 (define_expand "builtin_extbl"
7273 [(match_operand:DI 0 "register_operand" "")
7274 (match_operand:DI 1 "reg_or_0_operand" "")
7275 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7276 ""
7277 {
7278 rtx (*gen) (rtx, rtx, rtx, rtx);
7279 if (WORDS_BIG_ENDIAN)
7280 gen = gen_extxl_be;
7281 else
7282 gen = gen_extxl_le;
7283 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7284 DONE;
7285 })
7287 (define_expand "builtin_extwl"
7288 [(match_operand:DI 0 "register_operand" "")
7289 (match_operand:DI 1 "reg_or_0_operand" "")
7290 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7291 ""
7292 {
7293 rtx (*gen) (rtx, rtx, rtx, rtx);
7294 if (WORDS_BIG_ENDIAN)
7295 gen = gen_extxl_be;
7296 else
7297 gen = gen_extxl_le;
7298 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7299 DONE;
7300 })
7302 (define_expand "builtin_extll"
7303 [(match_operand:DI 0 "register_operand" "")
7304 (match_operand:DI 1 "reg_or_0_operand" "")
7305 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7306 ""
7307 {
7308 rtx (*gen) (rtx, rtx, rtx, rtx);
7309 if (WORDS_BIG_ENDIAN)
7310 gen = gen_extxl_be;
7311 else
7312 gen = gen_extxl_le;
7313 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7314 DONE;
7315 })
7317 (define_expand "builtin_extql"
7318 [(match_operand:DI 0 "register_operand" "")
7319 (match_operand:DI 1 "reg_or_0_operand" "")
7320 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7321 ""
7322 {
7323 rtx (*gen) (rtx, rtx, rtx, rtx);
7324 if (WORDS_BIG_ENDIAN)
7325 gen = gen_extxl_be;
7326 else
7327 gen = gen_extxl_le;
7328 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7329 DONE;
7330 })
7332 (define_expand "builtin_extwh"
7333 [(match_operand:DI 0 "register_operand" "")
7334 (match_operand:DI 1 "reg_or_0_operand" "")
7335 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7336 ""
7337 {
7338 rtx (*gen) (rtx, rtx, rtx);
7339 if (WORDS_BIG_ENDIAN)
7340 gen = gen_extwh_be;
7341 else
7342 gen = gen_extwh_le;
7343 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7344 DONE;
7345 })
7347 (define_expand "builtin_extlh"
7348 [(match_operand:DI 0 "register_operand" "")
7349 (match_operand:DI 1 "reg_or_0_operand" "")
7350 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7351 ""
7352 {
7353 rtx (*gen) (rtx, rtx, rtx);
7354 if (WORDS_BIG_ENDIAN)
7355 gen = gen_extlh_be;
7356 else
7357 gen = gen_extlh_le;
7358 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7359 DONE;
7360 })
7362 (define_expand "builtin_extqh"
7363 [(match_operand:DI 0 "register_operand" "")
7364 (match_operand:DI 1 "reg_or_0_operand" "")
7365 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7366 ""
7367 {
7368 rtx (*gen) (rtx, rtx, rtx);
7369 if (WORDS_BIG_ENDIAN)
7370 gen = gen_extqh_be;
7371 else
7372 gen = gen_extqh_le;
7373 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7374 DONE;
7375 })
7377 (define_expand "builtin_insbl"
7378 [(match_operand:DI 0 "register_operand" "")
7379 (match_operand:DI 1 "register_operand" "")
7380 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7381 ""
7382 {
7383 rtx (*gen) (rtx, rtx, rtx);
7384 if (WORDS_BIG_ENDIAN)
7385 gen = gen_insbl_be;
7386 else
7387 gen = gen_insbl_le;
7388 operands[1] = gen_lowpart (QImode, operands[1]);
7389 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7390 DONE;
7391 })
7393 (define_expand "builtin_inswl"
7394 [(match_operand:DI 0 "register_operand" "")
7395 (match_operand:DI 1 "register_operand" "")
7396 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7397 ""
7398 {
7399 rtx (*gen) (rtx, rtx, rtx);
7400 if (WORDS_BIG_ENDIAN)
7401 gen = gen_inswl_be;
7402 else
7403 gen = gen_inswl_le;
7404 operands[1] = gen_lowpart (HImode, operands[1]);
7405 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7406 DONE;
7407 })
7409 (define_expand "builtin_insll"
7410 [(match_operand:DI 0 "register_operand" "")
7411 (match_operand:DI 1 "register_operand" "")
7412 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7413 ""
7414 {
7415 rtx (*gen) (rtx, rtx, rtx);
7416 if (WORDS_BIG_ENDIAN)
7417 gen = gen_insll_be;
7418 else
7419 gen = gen_insll_le;
7420 operands[1] = gen_lowpart (SImode, operands[1]);
7421 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7422 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7423 DONE;
7424 })
7426 (define_expand "builtin_insql"
7427 [(match_operand:DI 0 "register_operand" "")
7428 (match_operand:DI 1 "reg_or_0_operand" "")
7429 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7430 ""
7431 {
7432 rtx (*gen) (rtx, rtx, rtx);
7433 if (WORDS_BIG_ENDIAN)
7434 gen = gen_insql_be;
7435 else
7436 gen = gen_insql_le;
7437 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7438 DONE;
7439 })
7441 (define_expand "builtin_inswh"
7442 [(match_operand:DI 0 "register_operand" "")
7443 (match_operand:DI 1 "register_operand" "")
7444 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7445 ""
7446 {
7447 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7448 DONE;
7449 })
7451 (define_expand "builtin_inslh"
7452 [(match_operand:DI 0 "register_operand" "")
7453 (match_operand:DI 1 "register_operand" "")
7454 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7455 ""
7456 {
7457 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7458 DONE;
7459 })
7461 (define_expand "builtin_insqh"
7462 [(match_operand:DI 0 "register_operand" "")
7463 (match_operand:DI 1 "register_operand" "")
7464 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7465 ""
7466 {
7467 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7468 DONE;
7469 })
7471 (define_expand "builtin_mskbl"
7472 [(match_operand:DI 0 "register_operand" "")
7473 (match_operand:DI 1 "reg_or_0_operand" "")
7474 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7475 ""
7476 {
7477 rtx (*gen) (rtx, rtx, rtx, rtx);
7478 rtx mask;
7479 if (WORDS_BIG_ENDIAN)
7480 gen = gen_mskxl_be;
7481 else
7482 gen = gen_mskxl_le;
7483 mask = GEN_INT (0xff);
7484 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7485 DONE;
7486 })
7488 (define_expand "builtin_mskwl"
7489 [(match_operand:DI 0 "register_operand" "")
7490 (match_operand:DI 1 "reg_or_0_operand" "")
7491 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7492 ""
7493 {
7494 rtx (*gen) (rtx, rtx, rtx, rtx);
7495 rtx mask;
7496 if (WORDS_BIG_ENDIAN)
7497 gen = gen_mskxl_be;
7498 else
7499 gen = gen_mskxl_le;
7500 mask = GEN_INT (0xffff);
7501 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7502 DONE;
7503 })
7505 (define_expand "builtin_mskll"
7506 [(match_operand:DI 0 "register_operand" "")
7507 (match_operand:DI 1 "reg_or_0_operand" "")
7508 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7509 ""
7510 {
7511 rtx (*gen) (rtx, rtx, rtx, rtx);
7512 rtx mask;
7513 if (WORDS_BIG_ENDIAN)
7514 gen = gen_mskxl_be;
7515 else
7516 gen = gen_mskxl_le;
7517 mask = immed_double_const (0xffffffff, 0, DImode);
7518 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7519 DONE;
7520 })
7522 (define_expand "builtin_mskql"
7523 [(match_operand:DI 0 "register_operand" "")
7524 (match_operand:DI 1 "reg_or_0_operand" "")
7525 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7526 ""
7527 {
7528 rtx (*gen) (rtx, rtx, rtx, rtx);
7529 rtx mask;
7530 if (WORDS_BIG_ENDIAN)
7531 gen = gen_mskxl_be;
7532 else
7533 gen = gen_mskxl_le;
7534 mask = constm1_rtx;
7535 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7536 DONE;
7537 })
7539 (define_expand "builtin_mskwh"
7540 [(match_operand:DI 0 "register_operand" "")
7541 (match_operand:DI 1 "register_operand" "")
7542 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7543 ""
7544 {
7545 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7546 DONE;
7547 })
7549 (define_expand "builtin_msklh"
7550 [(match_operand:DI 0 "register_operand" "")
7551 (match_operand:DI 1 "register_operand" "")
7552 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7553 ""
7554 {
7555 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7556 DONE;
7557 })
7559 (define_expand "builtin_mskqh"
7560 [(match_operand:DI 0 "register_operand" "")
7561 (match_operand:DI 1 "register_operand" "")
7562 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7563 ""
7564 {
7565 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7566 DONE;
7567 })
7569 (define_expand "builtin_zap"
7570 [(set (match_operand:DI 0 "register_operand" "")
7571 (and:DI (unspec:DI
7572 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7573 UNSPEC_ZAP)
7574 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7575 ""
7576 {
7577 if (GET_CODE (operands[2]) == CONST_INT)
7578 {
7579 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7581 if (mask == const0_rtx)
7582 {
7583 emit_move_insn (operands[0], const0_rtx);
7584 DONE;
7585 }
7586 if (mask == constm1_rtx)
7587 {
7588 emit_move_insn (operands[0], operands[1]);
7589 DONE;
7590 }
7592 operands[1] = force_reg (DImode, operands[1]);
7593 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7594 DONE;
7595 }
7597 operands[1] = force_reg (DImode, operands[1]);
7598 operands[2] = gen_lowpart (QImode, operands[2]);
7599 })
7601 (define_insn "*builtin_zap_1"
7602 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7603 (and:DI (unspec:DI
7604 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7605 UNSPEC_ZAP)
7606 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7607 ""
7608 "@
7609 #
7610 #
7611 bis $31,$31,%0
7612 zap %r1,%2,%0"
7613 [(set_attr "type" "shift,shift,ilog,shift")])
7615 (define_split
7616 [(set (match_operand:DI 0 "register_operand" "")
7617 (and:DI (unspec:DI
7618 [(match_operand:QI 2 "const_int_operand" "")]
7619 UNSPEC_ZAP)
7620 (match_operand:DI 1 "const_int_operand" "")))]
7621 ""
7622 [(const_int 0)]
7623 {
7624 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7625 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7626 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7627 else
7628 {
7629 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7630 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7631 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7632 c_hi & CONST_DOUBLE_HIGH (mask),
7633 DImode);
7634 }
7635 emit_move_insn (operands[0], operands[1]);
7636 DONE;
7637 })
7639 (define_split
7640 [(set (match_operand:DI 0 "register_operand" "")
7641 (and:DI (unspec:DI
7642 [(match_operand:QI 2 "const_int_operand" "")]
7643 UNSPEC_ZAP)
7644 (match_operand:DI 1 "register_operand" "")))]
7645 ""
7646 [(set (match_dup 0)
7647 (and:DI (match_dup 1) (match_dup 2)))]
7648 {
7649 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7650 if (operands[2] == const0_rtx)
7651 {
7652 emit_move_insn (operands[0], const0_rtx);
7653 DONE;
7654 }
7655 if (operands[2] == constm1_rtx)
7656 {
7657 emit_move_insn (operands[0], operands[1]);
7658 DONE;
7659 }
7660 })
7662 (define_expand "builtin_zapnot"
7663 [(set (match_operand:DI 0 "register_operand" "")
7664 (and:DI (unspec:DI
7665 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7666 UNSPEC_ZAP)
7667 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7668 ""
7669 {
7670 if (GET_CODE (operands[2]) == CONST_INT)
7671 {
7672 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7674 if (mask == const0_rtx)
7675 {
7676 emit_move_insn (operands[0], const0_rtx);
7677 DONE;
7678 }
7679 if (mask == constm1_rtx)
7680 {
7681 emit_move_insn (operands[0], operands[1]);
7682 DONE;
7683 }
7685 operands[1] = force_reg (DImode, operands[1]);
7686 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7687 DONE;
7688 }
7690 operands[1] = force_reg (DImode, operands[1]);
7691 operands[2] = gen_lowpart (QImode, operands[2]);
7692 })
7694 (define_insn "*builtin_zapnot_1"
7695 [(set (match_operand:DI 0 "register_operand" "=r")
7696 (and:DI (unspec:DI
7697 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7698 UNSPEC_ZAP)
7699 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7700 ""
7701 "zapnot %r1,%2,%0"
7702 [(set_attr "type" "shift")])
7704 (define_insn "builtin_amask"
7705 [(set (match_operand:DI 0 "register_operand" "=r")
7706 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7707 UNSPEC_AMASK))]
7708 ""
7709 "amask %1,%0"
7710 [(set_attr "type" "ilog")])
7712 (define_insn "builtin_implver"
7713 [(set (match_operand:DI 0 "register_operand" "=r")
7714 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7715 ""
7716 "implver %0"
7717 [(set_attr "type" "ilog")])
7719 (define_insn "builtin_rpcc"
7720 [(set (match_operand:DI 0 "register_operand" "=r")
7721 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7722 ""
7723 "rpcc %0"
7724 [(set_attr "type" "ilog")])
7726 (define_expand "builtin_minub8"
7727 [(match_operand:DI 0 "register_operand" "")
7728 (match_operand:DI 1 "reg_or_0_operand" "")
7729 (match_operand:DI 2 "reg_or_0_operand" "")]
7730 "TARGET_MAX"
7731 {
7732 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7733 operands[1], operands[2]);
7734 DONE;
7735 })
7737 (define_expand "builtin_minsb8"
7738 [(match_operand:DI 0 "register_operand" "")
7739 (match_operand:DI 1 "reg_or_0_operand" "")
7740 (match_operand:DI 2 "reg_or_0_operand" "")]
7741 "TARGET_MAX"
7742 {
7743 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7744 operands[1], operands[2]);
7745 DONE;
7746 })
7748 (define_expand "builtin_minuw4"
7749 [(match_operand:DI 0 "register_operand" "")
7750 (match_operand:DI 1 "reg_or_0_operand" "")
7751 (match_operand:DI 2 "reg_or_0_operand" "")]
7752 "TARGET_MAX"
7753 {
7754 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7755 operands[1], operands[2]);
7756 DONE;
7757 })
7759 (define_expand "builtin_minsw4"
7760 [(match_operand:DI 0 "register_operand" "")
7761 (match_operand:DI 1 "reg_or_0_operand" "")
7762 (match_operand:DI 2 "reg_or_0_operand" "")]
7763 "TARGET_MAX"
7764 {
7765 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7766 operands[1], operands[2]);
7767 DONE;
7768 })
7770 (define_expand "builtin_maxub8"
7771 [(match_operand:DI 0 "register_operand" "")
7772 (match_operand:DI 1 "reg_or_0_operand" "")
7773 (match_operand:DI 2 "reg_or_0_operand" "")]
7774 "TARGET_MAX"
7775 {
7776 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7777 operands[1], operands[2]);
7778 DONE;
7779 })
7781 (define_expand "builtin_maxsb8"
7782 [(match_operand:DI 0 "register_operand" "")
7783 (match_operand:DI 1 "reg_or_0_operand" "")
7784 (match_operand:DI 2 "reg_or_0_operand" "")]
7785 "TARGET_MAX"
7786 {
7787 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7788 operands[1], operands[2]);
7789 DONE;
7790 })
7792 (define_expand "builtin_maxuw4"
7793 [(match_operand:DI 0 "register_operand" "")
7794 (match_operand:DI 1 "reg_or_0_operand" "")
7795 (match_operand:DI 2 "reg_or_0_operand" "")]
7796 "TARGET_MAX"
7797 {
7798 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7799 operands[1], operands[2]);
7800 DONE;
7801 })
7803 (define_expand "builtin_maxsw4"
7804 [(match_operand:DI 0 "register_operand" "")
7805 (match_operand:DI 1 "reg_or_0_operand" "")
7806 (match_operand:DI 2 "reg_or_0_operand" "")]
7807 "TARGET_MAX"
7808 {
7809 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7810 operands[1], operands[2]);
7811 DONE;
7812 })
7814 (define_insn "builtin_perr"
7815 [(set (match_operand:DI 0 "register_operand" "=r")
7816 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7817 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7818 UNSPEC_PERR))]
7819 "TARGET_MAX"
7820 "perr %r1,%r2,%0"
7821 [(set_attr "type" "mvi")])
7823 (define_expand "builtin_pklb"
7824 [(set (match_operand:DI 0 "register_operand" "")
7825 (vec_concat:V8QI
7826 (vec_concat:V4QI
7827 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7828 (match_dup 2))
7829 (match_dup 3)))]
7830 "TARGET_MAX"
7831 {
7832 operands[0] = gen_lowpart (V8QImode, operands[0]);
7833 operands[1] = gen_lowpart (V2SImode, operands[1]);
7834 operands[2] = CONST0_RTX (V2QImode);
7835 operands[3] = CONST0_RTX (V4QImode);
7836 })
7838 (define_insn "*pklb"
7839 [(set (match_operand:V8QI 0 "register_operand" "=r")
7840 (vec_concat:V8QI
7841 (vec_concat:V4QI
7842 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7843 (match_operand:V2QI 2 "const0_operand" ""))
7844 (match_operand:V4QI 3 "const0_operand" "")))]
7845 "TARGET_MAX"
7846 "pklb %r1,%0"
7847 [(set_attr "type" "mvi")])
7849 (define_expand "builtin_pkwb"
7850 [(set (match_operand:DI 0 "register_operand" "")
7851 (vec_concat:V8QI
7852 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7853 (match_dup 2)))]
7854 "TARGET_MAX"
7855 {
7856 operands[0] = gen_lowpart (V8QImode, operands[0]);
7857 operands[1] = gen_lowpart (V4HImode, operands[1]);
7858 operands[2] = CONST0_RTX (V4QImode);
7859 })
7861 (define_insn "*pkwb"
7862 [(set (match_operand:V8QI 0 "register_operand" "=r")
7863 (vec_concat:V8QI
7864 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7865 (match_operand:V4QI 2 "const0_operand" "")))]
7866 "TARGET_MAX"
7867 "pkwb %r1,%0"
7868 [(set_attr "type" "mvi")])
7870 (define_expand "builtin_unpkbl"
7871 [(set (match_operand:DI 0 "register_operand" "")
7872 (zero_extend:V2SI
7873 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7874 (parallel [(const_int 0) (const_int 1)]))))]
7875 "TARGET_MAX"
7876 {
7877 operands[0] = gen_lowpart (V2SImode, operands[0]);
7878 operands[1] = gen_lowpart (V8QImode, operands[1]);
7879 })
7881 (define_insn "*unpkbl"
7882 [(set (match_operand:V2SI 0 "register_operand" "=r")
7883 (zero_extend:V2SI
7884 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7885 (parallel [(const_int 0) (const_int 1)]))))]
7886 "TARGET_MAX"
7887 "unpkbl %r1,%0"
7888 [(set_attr "type" "mvi")])
7890 (define_expand "builtin_unpkbw"
7891 [(set (match_operand:DI 0 "register_operand" "")
7892 (zero_extend:V4HI
7893 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7894 (parallel [(const_int 0)
7895 (const_int 1)
7896 (const_int 2)
7897 (const_int 3)]))))]
7898 "TARGET_MAX"
7899 {
7900 operands[0] = gen_lowpart (V4HImode, operands[0]);
7901 operands[1] = gen_lowpart (V8QImode, operands[1]);
7902 })
7904 (define_insn "*unpkbw"
7905 [(set (match_operand:V4HI 0 "register_operand" "=r")
7906 (zero_extend:V4HI
7907 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7908 (parallel [(const_int 0)
7909 (const_int 1)
7910 (const_int 2)
7911 (const_int 3)]))))]
7912 "TARGET_MAX"
7913 "unpkbw %r1,%0"
7914 [(set_attr "type" "mvi")])
7915 \f
7916 (include "sync.md")
7917 \f
7918 ;; The call patterns are at the end of the file because their
7919 ;; wildcard operand0 interferes with nice recognition.
7921 (define_insn "*call_value_osf_1_er_noreturn"
7922 [(set (match_operand 0 "" "")
7923 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7924 (match_operand 2 "" "")))
7925 (use (reg:DI 29))
7926 (clobber (reg:DI 26))]
7927 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7928 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7929 "@
7930 jsr $26,($27),0
7931 bsr $26,%1\t\t!samegp
7932 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#"
7933 [(set_attr "type" "jsr")
7934 (set_attr "length" "*,*,8")])
7936 (define_insn "*call_value_osf_1_er"
7937 [(set (match_operand 0 "" "")
7938 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7939 (match_operand 2 "" "")))
7940 (use (reg:DI 29))
7941 (clobber (reg:DI 26))]
7942 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7943 "@
7944 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7945 bsr $26,%1\t\t!samegp
7946 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7947 [(set_attr "type" "jsr")
7948 (set_attr "length" "12,*,16")])
7950 ;; We must use peep2 instead of a split because we need accurate life
7951 ;; information for $gp. Consider the case of { bar(); while (1); }.
7952 (define_peephole2
7953 [(parallel [(set (match_operand 0 "" "")
7954 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7955 (match_operand 2 "" "")))
7956 (use (reg:DI 29))
7957 (clobber (reg:DI 26))])]
7958 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7959 && ! samegp_function_operand (operands[1], Pmode)
7960 && (peep2_regno_dead_p (1, 29)
7961 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7962 [(parallel [(set (match_dup 0)
7963 (call (mem:DI (match_dup 3))
7964 (match_dup 2)))
7965 (use (reg:DI 29))
7966 (use (match_dup 1))
7967 (use (match_dup 4))
7968 (clobber (reg:DI 26))])]
7969 {
7970 if (CONSTANT_P (operands[1]))
7971 {
7972 operands[3] = gen_rtx_REG (Pmode, 27);
7973 operands[4] = GEN_INT (alpha_next_sequence_number++);
7974 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7975 operands[1], operands[4]));
7976 }
7977 else
7978 {
7979 operands[3] = operands[1];
7980 operands[1] = const0_rtx;
7981 operands[4] = const0_rtx;
7982 }
7983 })
7985 (define_peephole2
7986 [(parallel [(set (match_operand 0 "" "")
7987 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7988 (match_operand 2 "" "")))
7989 (use (reg:DI 29))
7990 (clobber (reg:DI 26))])]
7991 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7992 && ! samegp_function_operand (operands[1], Pmode)
7993 && ! (peep2_regno_dead_p (1, 29)
7994 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7995 [(parallel [(set (match_dup 0)
7996 (call (mem:DI (match_dup 3))
7997 (match_dup 2)))
7998 (set (match_dup 6)
7999 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1))
8000 (use (match_dup 1))
8001 (use (match_dup 5))
8002 (clobber (reg:DI 26))])
8003 (set (match_dup 6)
8004 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))]
8005 {
8006 if (CONSTANT_P (operands[1]))
8007 {
8008 operands[3] = gen_rtx_REG (Pmode, 27);
8009 operands[5] = GEN_INT (alpha_next_sequence_number++);
8010 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
8011 operands[1], operands[5]));
8012 }
8013 else
8014 {
8015 operands[3] = operands[1];
8016 operands[1] = const0_rtx;
8017 operands[5] = const0_rtx;
8018 }
8019 operands[4] = GEN_INT (alpha_next_sequence_number++);
8020 operands[6] = pic_offset_table_rtx;
8021 })
8023 (define_insn "*call_value_osf_2_er_nogp"
8024 [(set (match_operand 0 "" "")
8025 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
8026 (match_operand 2 "" "")))
8027 (use (reg:DI 29))
8028 (use (match_operand 3 "" ""))
8029 (use (match_operand 4 "" ""))
8030 (clobber (reg:DI 26))]
8031 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8032 "jsr $26,(%1),%3%J4"
8033 [(set_attr "type" "jsr")])
8035 (define_insn "*call_value_osf_2_er"
8036 [(set (match_operand 0 "" "")
8037 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
8038 (match_operand 2 "" "")))
8039 (set (reg:DI 29)
8040 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand" "")]
8041 UNSPEC_LDGP1))
8042 (use (match_operand 3 "" ""))
8043 (use (match_operand 4 "" ""))
8044 (clobber (reg:DI 26))]
8045 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8046 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
8047 [(set_attr "type" "jsr")
8048 (set_attr "cannot_copy" "true")
8049 (set_attr "length" "8")])
8051 (define_insn "*call_value_osf_1_noreturn"
8052 [(set (match_operand 0 "" "")
8053 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8054 (match_operand 2 "" "")))
8055 (use (reg:DI 29))
8056 (clobber (reg:DI 26))]
8057 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
8058 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8059 "@
8060 jsr $26,($27),0
8061 bsr $26,$%1..ng
8062 jsr $26,%1"
8063 [(set_attr "type" "jsr")
8064 (set_attr "length" "*,*,8")])
8066 (define_insn_and_split "call_value_osf_tlsgd"
8067 [(set (match_operand 0 "" "")
8068 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8069 (const_int 0)))
8070 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
8071 (use (reg:DI 29))
8072 (clobber (reg:DI 26))]
8073 "HAVE_AS_TLS"
8074 "#"
8075 "&& reload_completed"
8076 [(set (match_dup 3)
8077 (unspec:DI [(match_dup 5)
8078 (match_dup 1)
8079 (match_dup 2)] UNSPEC_LITERAL))
8080 (parallel [(set (match_dup 0)
8081 (call (mem:DI (match_dup 3))
8082 (const_int 0)))
8083 (set (match_dup 5)
8084 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
8085 (use (match_dup 1))
8086 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))
8087 (clobber (reg:DI 26))])
8088 (set (match_dup 5)
8089 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8090 {
8091 operands[3] = gen_rtx_REG (Pmode, 27);
8092 operands[4] = GEN_INT (alpha_next_sequence_number++);
8093 operands[5] = pic_offset_table_rtx;
8094 }
8095 [(set_attr "type" "multi")])
8097 (define_insn_and_split "call_value_osf_tlsldm"
8098 [(set (match_operand 0 "" "")
8099 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8100 (const_int 0)))
8101 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
8102 (use (reg:DI 29))
8103 (clobber (reg:DI 26))]
8104 "HAVE_AS_TLS"
8105 "#"
8106 "&& reload_completed"
8107 [(set (match_dup 3)
8108 (unspec:DI [(match_dup 5)
8109 (match_dup 1)
8110 (match_dup 2)] UNSPEC_LITERAL))
8111 (parallel [(set (match_dup 0)
8112 (call (mem:DI (match_dup 3))
8113 (const_int 0)))
8114 (set (match_dup 5)
8115 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
8116 (use (match_dup 1))
8117 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))
8118 (clobber (reg:DI 26))])
8119 (set (match_dup 5)
8120 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8121 {
8122 operands[3] = gen_rtx_REG (Pmode, 27);
8123 operands[4] = GEN_INT (alpha_next_sequence_number++);
8124 operands[5] = pic_offset_table_rtx;
8125 }
8126 [(set_attr "type" "multi")])
8128 (define_insn "*call_value_osf_1"
8129 [(set (match_operand 0 "" "")
8130 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8131 (match_operand 2 "" "")))
8132 (use (reg:DI 29))
8133 (clobber (reg:DI 26))]
8134 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8135 "@
8136 jsr $26,($27),0\;ldgp $29,0($26)
8137 bsr $26,$%1..ng
8138 jsr $26,%1\;ldgp $29,0($26)"
8139 [(set_attr "type" "jsr")
8140 (set_attr "length" "12,*,16")])
8142 (define_insn "*sibcall_value_osf_1_er"
8143 [(set (match_operand 0 "" "")
8144 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8145 (match_operand 2 "" "")))
8146 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8147 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8148 "@
8149 br $31,%1\t\t!samegp
8150 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8151 [(set_attr "type" "jsr")
8152 (set_attr "length" "*,8")])
8154 (define_insn "*sibcall_value_osf_1"
8155 [(set (match_operand 0 "" "")
8156 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8157 (match_operand 2 "" "")))
8158 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8159 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8160 "@
8161 br $31,$%1..ng
8162 lda $27,%1\;jmp $31,($27),%1"
8163 [(set_attr "type" "jsr")
8164 (set_attr "length" "*,8")])
8166 (define_insn "*call_value_nt_1"
8167 [(set (match_operand 0 "" "")
8168 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8169 (match_operand 2 "" "")))
8170 (clobber (reg:DI 26))]
8171 "TARGET_ABI_WINDOWS_NT"
8172 "@
8173 jsr $26,(%1)
8174 bsr $26,%1
8175 jsr $26,%1"
8176 [(set_attr "type" "jsr")
8177 (set_attr "length" "*,*,12")])
8179 ; GAS relies on the order and position of instructions output below in order
8180 ; to generate relocs for VMS link to potentially optimize the call.
8181 ; Please do not molest.
8182 (define_insn "*call_value_vms_1"
8183 [(set (match_operand 0 "" "")
8184 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8185 (match_operand 2 "" "")))
8186 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8187 (use (reg:DI 25))
8188 (use (reg:DI 26))
8189 (clobber (reg:DI 27))]
8190 "TARGET_ABI_OPEN_VMS"
8191 {
8192 switch (which_alternative)
8193 {
8194 case 0:
8195 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8196 case 1:
8197 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8198 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8199 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8200 default:
8201 gcc_unreachable ();
8202 }
8203 }
8204 [(set_attr "type" "jsr")
8205 (set_attr "length" "12,16")])
8207 (define_insn "*call_value_umk"
8208 [(set (match_operand 0 "" "")
8209 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8210 (match_operand 2 "" "")))
8211 (use (reg:DI 25))
8212 (clobber (reg:DI 26))]
8213 "TARGET_ABI_UNICOSMK"
8214 "jsr $26,(%1)"
8215 [(set_attr "type" "jsr")])