1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
31 #include "insn-config.h"
37 static void store_fixed_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
38 unsigned HOST_WIDE_INT
,
39 unsigned HOST_WIDE_INT
, rtx
));
40 static void store_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
, rtx
));
42 static rtx extract_fixed_bit_field
PARAMS ((enum machine_mode
, rtx
,
43 unsigned HOST_WIDE_INT
,
44 unsigned HOST_WIDE_INT
,
45 unsigned HOST_WIDE_INT
,
47 static rtx mask_rtx
PARAMS ((enum machine_mode
, int,
49 static rtx lshift_value
PARAMS ((enum machine_mode
, rtx
,
51 static rtx extract_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, int));
53 static void do_cmp_and_jump
PARAMS ((rtx
, rtx
, enum rtx_code
,
54 enum machine_mode
, rtx
));
56 /* Non-zero means divides or modulus operations are relatively cheap for
57 powers of two, so don't use branches; emit the operation instead.
58 Usually, this will mean that the MD file will emit non-branch
61 static int sdiv_pow2_cheap
, smod_pow2_cheap
;
63 #ifndef SLOW_UNALIGNED_ACCESS
64 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
67 /* For compilers that support multiple targets with different word sizes,
68 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
69 is the H8/300(H) compiler. */
71 #ifndef MAX_BITS_PER_WORD
72 #define MAX_BITS_PER_WORD BITS_PER_WORD
75 /* Reduce conditional compilation elsewhere. */
78 #define CODE_FOR_insv CODE_FOR_nothing
79 #define gen_insv(a,b,c,d) NULL_RTX
83 #define CODE_FOR_extv CODE_FOR_nothing
84 #define gen_extv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extzv CODE_FOR_nothing
89 #define gen_extzv(a,b,c,d) NULL_RTX
92 /* Cost of various pieces of RTL. Note that some of these are indexed by
93 shift count and some by mode. */
94 static int add_cost
, negate_cost
, zero_cost
;
95 static int shift_cost
[MAX_BITS_PER_WORD
];
96 static int shiftadd_cost
[MAX_BITS_PER_WORD
];
97 static int shiftsub_cost
[MAX_BITS_PER_WORD
];
98 static int mul_cost
[NUM_MACHINE_MODES
];
99 static int div_cost
[NUM_MACHINE_MODES
];
100 static int mul_widen_cost
[NUM_MACHINE_MODES
];
101 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
106 /* This is "some random pseudo register" for purposes of calling recog
107 to see what insns exist. */
108 rtx reg
= gen_rtx_REG (word_mode
, 10000);
109 rtx shift_insn
, shiftadd_insn
, shiftsub_insn
;
112 enum machine_mode mode
, wider_mode
;
116 reg
= gen_rtx_REG (word_mode
, 10000);
118 zero_cost
= rtx_cost (const0_rtx
, 0);
119 add_cost
= rtx_cost (gen_rtx_PLUS (word_mode
, reg
, reg
), SET
);
121 shift_insn
= emit_insn (gen_rtx_SET (VOIDmode
, reg
,
122 gen_rtx_ASHIFT (word_mode
, reg
,
126 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
127 gen_rtx_PLUS (word_mode
,
128 gen_rtx_MULT (word_mode
,
133 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
134 gen_rtx_MINUS (word_mode
,
135 gen_rtx_MULT (word_mode
,
142 shiftadd_cost
[0] = shiftsub_cost
[0] = add_cost
;
144 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
146 shift_cost
[m
] = shiftadd_cost
[m
] = shiftsub_cost
[m
] = 32000;
148 XEXP (SET_SRC (PATTERN (shift_insn
)), 1) = GEN_INT (m
);
149 if (recog (PATTERN (shift_insn
), shift_insn
, &dummy
) >= 0)
150 shift_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shift_insn
)), SET
);
152 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn
)), 0), 1)
153 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
154 if (recog (PATTERN (shiftadd_insn
), shiftadd_insn
, &dummy
) >= 0)
155 shiftadd_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn
)), SET
);
157 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn
)), 0), 1)
158 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
159 if (recog (PATTERN (shiftsub_insn
), shiftsub_insn
, &dummy
) >= 0)
160 shiftsub_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn
)), SET
);
163 negate_cost
= rtx_cost (gen_rtx_NEG (word_mode
, reg
), SET
);
166 = (rtx_cost (gen_rtx_DIV (word_mode
, reg
, GEN_INT (32)), SET
)
169 = (rtx_cost (gen_rtx_MOD (word_mode
, reg
, GEN_INT (32)), SET
)
172 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
174 mode
= GET_MODE_WIDER_MODE (mode
))
176 reg
= gen_rtx_REG (mode
, 10000);
177 div_cost
[(int) mode
] = rtx_cost (gen_rtx_UDIV (mode
, reg
, reg
), SET
);
178 mul_cost
[(int) mode
] = rtx_cost (gen_rtx_MULT (mode
, reg
, reg
), SET
);
179 wider_mode
= GET_MODE_WIDER_MODE (mode
);
180 if (wider_mode
!= VOIDmode
)
182 mul_widen_cost
[(int) wider_mode
]
183 = rtx_cost (gen_rtx_MULT (wider_mode
,
184 gen_rtx_ZERO_EXTEND (wider_mode
, reg
),
185 gen_rtx_ZERO_EXTEND (wider_mode
, reg
)),
187 mul_highpart_cost
[(int) mode
]
188 = rtx_cost (gen_rtx_TRUNCATE
190 gen_rtx_LSHIFTRT (wider_mode
,
191 gen_rtx_MULT (wider_mode
,
196 GEN_INT (GET_MODE_BITSIZE (mode
)))),
204 /* Return an rtx representing minus the value of X.
205 MODE is the intended mode of the result,
206 useful if X is a CONST_INT. */
210 enum machine_mode mode
;
213 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
216 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
221 /* Report on the availability of insv/extv/extzv and the desired mode
222 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
223 is false; else the mode of the specified operand. If OPNO is -1,
224 all the caller cares about is whether the insn is available. */
226 mode_for_extraction (pattern
, opno
)
227 enum extraction_pattern pattern
;
230 const struct insn_data
*data
;
237 data
= &insn_data
[CODE_FOR_insv
];
240 return MAX_MACHINE_MODE
;
245 data
= &insn_data
[CODE_FOR_extv
];
248 return MAX_MACHINE_MODE
;
253 data
= &insn_data
[CODE_FOR_extzv
];
256 return MAX_MACHINE_MODE
;
265 /* Everyone who uses this function used to follow it with
266 if (result == VOIDmode) result = word_mode; */
267 if (data
->operand
[opno
].mode
== VOIDmode
)
269 return data
->operand
[opno
].mode
;
273 /* Generate code to store value from rtx VALUE
274 into a bit-field within structure STR_RTX
275 containing BITSIZE bits starting at bit BITNUM.
276 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
277 ALIGN is the alignment that STR_RTX is known to have.
278 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
280 /* ??? Note that there are two different ideas here for how
281 to determine the size to count bits within, for a register.
282 One is BITS_PER_WORD, and the other is the size of operand 3
285 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
286 else, we use the mode of operand 3. */
289 store_bit_field (str_rtx
, bitsize
, bitnum
, fieldmode
, value
, total_size
)
291 unsigned HOST_WIDE_INT bitsize
;
292 unsigned HOST_WIDE_INT bitnum
;
293 enum machine_mode fieldmode
;
295 HOST_WIDE_INT total_size
;
298 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
299 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
300 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
304 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
306 /* Discount the part of the structure before the desired byte.
307 We need to know how many bytes are safe to reference after it. */
309 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
310 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
312 while (GET_CODE (op0
) == SUBREG
)
314 /* The following line once was done only if WORDS_BIG_ENDIAN,
315 but I think that is a mistake. WORDS_BIG_ENDIAN is
316 meaningful at a much higher level; when structures are copied
317 between memory and regs, the higher-numbered regs
318 always get higher addresses. */
319 offset
+= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
);
320 /* We used to adjust BITPOS here, but now we do the whole adjustment
321 right after the loop. */
322 op0
= SUBREG_REG (op0
);
325 value
= protect_from_queue (value
, 0);
329 int old_generating_concat_p
= generating_concat_p
;
330 generating_concat_p
= 0;
331 value
= force_not_mem (value
);
332 generating_concat_p
= old_generating_concat_p
;
335 /* If the target is a register, overwriting the entire object, or storing
336 a full-word or multi-word field can be done with just a SUBREG.
338 If the target is memory, storing any naturally aligned field can be
339 done with a simple store. For targets that support fast unaligned
340 memory, any naturally sized, unit aligned field can be done directly. */
342 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
343 + (offset
* UNITS_PER_WORD
);
346 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
347 && (GET_CODE (op0
) != MEM
348 ? ((GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
349 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
350 && byte_offset
% GET_MODE_SIZE (fieldmode
) == 0)
351 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
352 || (offset
* BITS_PER_UNIT
% bitsize
== 0
353 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
355 if (GET_MODE (op0
) != fieldmode
)
357 if (GET_CODE (op0
) == SUBREG
)
359 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
360 || GET_MODE_CLASS (fieldmode
) == MODE_INT
361 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
362 op0
= SUBREG_REG (op0
);
364 /* Else we've got some float mode source being extracted into
365 a different float mode destination -- this combination of
366 subregs results in Severe Tire Damage. */
369 if (GET_CODE (op0
) == REG
)
370 op0
= gen_rtx_SUBREG (fieldmode
, op0
, byte_offset
);
372 op0
= adjust_address (op0
, fieldmode
, offset
);
374 emit_move_insn (op0
, value
);
378 /* Make sure we are playing with integral modes. Pun with subregs
379 if we aren't. This must come after the entire register case above,
380 since that case is valid for any mode. The following cases are only
381 valid for integral modes. */
383 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
384 if (imode
!= GET_MODE (op0
))
386 if (GET_CODE (op0
) == MEM
)
387 op0
= adjust_address (op0
, imode
, 0);
388 else if (imode
!= BLKmode
)
389 op0
= gen_lowpart (imode
, op0
);
395 /* We may be accessing data outside the field, which means
396 we can alias adjacent data. */
397 if (GET_CODE (op0
) == MEM
)
399 op0
= shallow_copy_rtx (op0
);
400 set_mem_alias_set (op0
, 0);
401 set_mem_expr (op0
, 0);
404 /* If OP0 is a register, BITPOS must count within a word.
405 But as we have it, it counts within whatever size OP0 now has.
406 On a bigendian machine, these are not the same, so convert. */
408 && GET_CODE (op0
) != MEM
409 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
410 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
412 /* Storing an lsb-aligned field in a register
413 can be done with a movestrict instruction. */
415 if (GET_CODE (op0
) != MEM
416 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
417 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
418 && (movstrict_optab
->handlers
[(int) fieldmode
].insn_code
419 != CODE_FOR_nothing
))
421 int icode
= movstrict_optab
->handlers
[(int) fieldmode
].insn_code
;
423 /* Get appropriate low part of the value being stored. */
424 if (GET_CODE (value
) == CONST_INT
|| GET_CODE (value
) == REG
)
425 value
= gen_lowpart (fieldmode
, value
);
426 else if (!(GET_CODE (value
) == SYMBOL_REF
427 || GET_CODE (value
) == LABEL_REF
428 || GET_CODE (value
) == CONST
))
429 value
= convert_to_mode (fieldmode
, value
, 0);
431 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
432 value
= copy_to_mode_reg (fieldmode
, value
);
434 if (GET_CODE (op0
) == SUBREG
)
436 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
437 || GET_MODE_CLASS (fieldmode
) == MODE_INT
438 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
439 op0
= SUBREG_REG (op0
);
441 /* Else we've got some float mode source being extracted into
442 a different float mode destination -- this combination of
443 subregs results in Severe Tire Damage. */
447 emit_insn (GEN_FCN (icode
)
448 (gen_rtx_SUBREG (fieldmode
, op0
,
449 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
450 + (offset
* UNITS_PER_WORD
)),
456 /* Handle fields bigger than a word. */
458 if (bitsize
> BITS_PER_WORD
)
460 /* Here we transfer the words of the field
461 in the order least significant first.
462 This is because the most significant word is the one which may
464 However, only do that if the value is not BLKmode. */
466 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
467 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
470 /* This is the mode we must force value to, so that there will be enough
471 subwords to extract. Note that fieldmode will often (always?) be
472 VOIDmode, because that is what store_field uses to indicate that this
473 is a bit field, but passing VOIDmode to operand_subword_force will
474 result in an abort. */
475 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
477 for (i
= 0; i
< nwords
; i
++)
479 /* If I is 0, use the low-order word in both field and target;
480 if I is 1, use the next to lowest word; and so on. */
481 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
482 unsigned int bit_offset
= (backwards
483 ? MAX ((int) bitsize
- ((int) i
+ 1)
486 : (int) i
* BITS_PER_WORD
);
488 store_bit_field (op0
, MIN (BITS_PER_WORD
,
489 bitsize
- i
* BITS_PER_WORD
),
490 bitnum
+ bit_offset
, word_mode
,
491 operand_subword_force (value
, wordnum
,
492 (GET_MODE (value
) == VOIDmode
494 : GET_MODE (value
))),
500 /* From here on we can assume that the field to be stored in is
501 a full-word (whatever type that is), since it is shorter than a word. */
503 /* OFFSET is the number of words or bytes (UNIT says which)
504 from STR_RTX to the first word or byte containing part of the field. */
506 if (GET_CODE (op0
) != MEM
)
509 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
511 if (GET_CODE (op0
) != REG
)
513 /* Since this is a destination (lvalue), we can't copy it to a
514 pseudo. We can trivially remove a SUBREG that does not
515 change the size of the operand. Such a SUBREG may have been
516 added above. Otherwise, abort. */
517 if (GET_CODE (op0
) == SUBREG
518 && (GET_MODE_SIZE (GET_MODE (op0
))
519 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))))
520 op0
= SUBREG_REG (op0
);
524 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
525 op0
, (offset
* UNITS_PER_WORD
));
530 op0
= protect_from_queue (op0
, 1);
532 /* If VALUE is a floating-point mode, access it as an integer of the
533 corresponding size. This can occur on a machine with 64 bit registers
534 that uses SFmode for float. This can also occur for unaligned float
536 if (GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
537 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
538 value
= gen_lowpart (word_mode
, value
);
540 /* Now OFFSET is nonzero only if OP0 is memory
541 and is therefore always measured in bytes. */
544 && GET_MODE (value
) != BLKmode
545 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
546 /* Ensure insv's size is wide enough for this field. */
547 && (GET_MODE_BITSIZE (op_mode
) >= bitsize
)
548 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
549 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
))))
551 int xbitpos
= bitpos
;
554 rtx last
= get_last_insn ();
556 enum machine_mode maxmode
= mode_for_extraction (EP_insv
, 3);
557 int save_volatile_ok
= volatile_ok
;
561 /* If this machine's insv can only insert into a register, copy OP0
562 into a register and save it back later. */
563 /* This used to check flag_force_mem, but that was a serious
564 de-optimization now that flag_force_mem is enabled by -O2. */
565 if (GET_CODE (op0
) == MEM
566 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
570 enum machine_mode bestmode
;
572 /* Get the mode to use for inserting into this field. If OP0 is
573 BLKmode, get the smallest mode consistent with the alignment. If
574 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
575 mode. Otherwise, use the smallest mode containing the field. */
577 if (GET_MODE (op0
) == BLKmode
578 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
580 = get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
), maxmode
,
581 MEM_VOLATILE_P (op0
));
583 bestmode
= GET_MODE (op0
);
585 if (bestmode
== VOIDmode
586 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
587 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
590 /* Adjust address to point to the containing unit of that mode.
591 Compute offset as multiple of this unit, counting in bytes. */
592 unit
= GET_MODE_BITSIZE (bestmode
);
593 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
594 bitpos
= bitnum
% unit
;
595 op0
= adjust_address (op0
, bestmode
, offset
);
597 /* Fetch that unit, store the bitfield in it, then store
599 tempreg
= copy_to_reg (op0
);
600 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, value
,
602 emit_move_insn (op0
, tempreg
);
605 volatile_ok
= save_volatile_ok
;
607 /* Add OFFSET into OP0's address. */
608 if (GET_CODE (xop0
) == MEM
)
609 xop0
= adjust_address (xop0
, byte_mode
, offset
);
611 /* If xop0 is a register, we need it in MAXMODE
612 to make it acceptable to the format of insv. */
613 if (GET_CODE (xop0
) == SUBREG
)
614 /* We can't just change the mode, because this might clobber op0,
615 and we will need the original value of op0 if insv fails. */
616 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
617 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
618 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
620 /* On big-endian machines, we count bits from the most significant.
621 If the bit field insn does not, we must invert. */
623 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
624 xbitpos
= unit
- bitsize
- xbitpos
;
626 /* We have been counting XBITPOS within UNIT.
627 Count instead within the size of the register. */
628 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
629 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
631 unit
= GET_MODE_BITSIZE (maxmode
);
633 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
635 if (GET_MODE (value
) != maxmode
)
637 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
639 /* Optimization: Don't bother really extending VALUE
640 if it has all the bits we will actually use. However,
641 if we must narrow it, be sure we do it correctly. */
643 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
647 tmp
= simplify_subreg (maxmode
, value1
, GET_MODE (value
), 0);
649 tmp
= simplify_gen_subreg (maxmode
,
650 force_reg (GET_MODE (value
),
652 GET_MODE (value
), 0);
656 value1
= gen_lowpart (maxmode
, value1
);
658 else if (GET_CODE (value
) == CONST_INT
)
659 value1
= gen_int_mode (INTVAL (value
), maxmode
);
660 else if (!CONSTANT_P (value
))
661 /* Parse phase is supposed to make VALUE's data type
662 match that of the component reference, which is a type
663 at least as wide as the field; so VALUE should have
664 a mode that corresponds to that type. */
668 /* If this machine's insv insists on a register,
669 get VALUE1 into a register. */
670 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
672 value1
= force_reg (maxmode
, value1
);
674 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
679 delete_insns_since (last
);
680 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
685 /* Insv is not available; store using shifts and boolean ops. */
686 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
690 /* Use shifts and boolean operations to store VALUE
691 into a bit field of width BITSIZE
692 in a memory location specified by OP0 except offset by OFFSET bytes.
693 (OFFSET must be 0 if OP0 is a register.)
694 The field starts at position BITPOS within the byte.
695 (If OP0 is a register, it may be a full word or a narrower mode,
696 but BITPOS still counts within a full word,
697 which is significant on bigendian machines.)
699 Note that protect_from_queue has already been done on OP0 and VALUE. */
702 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
)
704 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
707 enum machine_mode mode
;
708 unsigned int total_bits
= BITS_PER_WORD
;
713 /* There is a case not handled here:
714 a structure with a known alignment of just a halfword
715 and a field split across two aligned halfwords within the structure.
716 Or likewise a structure with a known alignment of just a byte
717 and a field split across two bytes.
718 Such cases are not supposed to be able to occur. */
720 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
724 /* Special treatment for a bit field split across two registers. */
725 if (bitsize
+ bitpos
> BITS_PER_WORD
)
727 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
733 /* Get the proper mode to use for this field. We want a mode that
734 includes the entire field. If such a mode would be larger than
735 a word, we won't be doing the extraction the normal way.
736 We don't want a mode bigger than the destination. */
738 mode
= GET_MODE (op0
);
739 if (GET_MODE_BITSIZE (mode
) == 0
740 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
742 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
743 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
745 if (mode
== VOIDmode
)
747 /* The only way this should occur is if the field spans word
749 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
754 total_bits
= GET_MODE_BITSIZE (mode
);
756 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
757 be in the range 0 to total_bits-1, and put any excess bytes in
759 if (bitpos
>= total_bits
)
761 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
762 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
766 /* Get ref to an aligned byte, halfword, or word containing the field.
767 Adjust BITPOS to be position within a word,
768 and OFFSET to be the offset of that word.
769 Then alter OP0 to refer to that word. */
770 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
771 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
772 op0
= adjust_address (op0
, mode
, offset
);
775 mode
= GET_MODE (op0
);
777 /* Now MODE is either some integral mode for a MEM as OP0,
778 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
779 The bit field is contained entirely within OP0.
780 BITPOS is the starting bit number within OP0.
781 (OP0's mode may actually be narrower than MODE.) */
783 if (BYTES_BIG_ENDIAN
)
784 /* BITPOS is the distance between our msb
785 and that of the containing datum.
786 Convert it to the distance from the lsb. */
787 bitpos
= total_bits
- bitsize
- bitpos
;
789 /* Now BITPOS is always the distance between our lsb
792 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
793 we must first convert its mode to MODE. */
795 if (GET_CODE (value
) == CONST_INT
)
797 HOST_WIDE_INT v
= INTVAL (value
);
799 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
800 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
804 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
805 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
806 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
809 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
813 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
814 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
816 if (GET_MODE (value
) != mode
)
818 if ((GET_CODE (value
) == REG
|| GET_CODE (value
) == SUBREG
)
819 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
820 value
= gen_lowpart (mode
, value
);
822 value
= convert_to_mode (mode
, value
, 1);
826 value
= expand_binop (mode
, and_optab
, value
,
827 mask_rtx (mode
, 0, bitsize
, 0),
828 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
830 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
831 build_int_2 (bitpos
, 0), NULL_RTX
, 1);
834 /* Now clear the chosen bits in OP0,
835 except that if VALUE is -1 we need not bother. */
837 subtarget
= (GET_CODE (op0
) == REG
|| ! flag_force_mem
) ? op0
: 0;
841 temp
= expand_binop (mode
, and_optab
, op0
,
842 mask_rtx (mode
, bitpos
, bitsize
, 1),
843 subtarget
, 1, OPTAB_LIB_WIDEN
);
849 /* Now logical-or VALUE into OP0, unless it is zero. */
852 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
853 subtarget
, 1, OPTAB_LIB_WIDEN
);
855 emit_move_insn (op0
, temp
);
858 /* Store a bit field that is split across multiple accessible memory objects.
860 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
861 BITSIZE is the field width; BITPOS the position of its first bit
863 VALUE is the value to store.
865 This does not yet handle fields wider than BITS_PER_WORD. */
868 store_split_bit_field (op0
, bitsize
, bitpos
, value
)
870 unsigned HOST_WIDE_INT bitsize
, bitpos
;
874 unsigned int bitsdone
= 0;
876 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
878 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
879 unit
= BITS_PER_WORD
;
881 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
883 /* If VALUE is a constant other than a CONST_INT, get it into a register in
884 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
885 that VALUE might be a floating-point constant. */
886 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
888 rtx word
= gen_lowpart_common (word_mode
, value
);
890 if (word
&& (value
!= word
))
893 value
= gen_lowpart_common (word_mode
,
894 force_reg (GET_MODE (value
) != VOIDmode
896 : word_mode
, value
));
898 else if (GET_CODE (value
) == ADDRESSOF
)
899 value
= copy_to_reg (value
);
901 while (bitsdone
< bitsize
)
903 unsigned HOST_WIDE_INT thissize
;
905 unsigned HOST_WIDE_INT thispos
;
906 unsigned HOST_WIDE_INT offset
;
908 offset
= (bitpos
+ bitsdone
) / unit
;
909 thispos
= (bitpos
+ bitsdone
) % unit
;
911 /* THISSIZE must not overrun a word boundary. Otherwise,
912 store_fixed_bit_field will call us again, and we will mutually
914 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
915 thissize
= MIN (thissize
, unit
- thispos
);
917 if (BYTES_BIG_ENDIAN
)
921 /* We must do an endian conversion exactly the same way as it is
922 done in extract_bit_field, so that the two calls to
923 extract_fixed_bit_field will have comparable arguments. */
924 if (GET_CODE (value
) != MEM
|| GET_MODE (value
) == BLKmode
)
925 total_bits
= BITS_PER_WORD
;
927 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
929 /* Fetch successively less significant portions. */
930 if (GET_CODE (value
) == CONST_INT
)
931 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
932 >> (bitsize
- bitsdone
- thissize
))
933 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
935 /* The args are chosen so that the last part includes the
936 lsb. Give extract_bit_field the value it needs (with
937 endianness compensation) to fetch the piece we want. */
938 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
939 total_bits
- bitsize
+ bitsdone
,
944 /* Fetch successively more significant portions. */
945 if (GET_CODE (value
) == CONST_INT
)
946 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
948 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
950 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
951 bitsdone
, NULL_RTX
, 1);
954 /* If OP0 is a register, then handle OFFSET here.
956 When handling multiword bitfields, extract_bit_field may pass
957 down a word_mode SUBREG of a larger REG for a bitfield that actually
958 crosses a word boundary. Thus, for a SUBREG, we must find
959 the current word starting from the base register. */
960 if (GET_CODE (op0
) == SUBREG
)
962 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
963 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
964 GET_MODE (SUBREG_REG (op0
)));
967 else if (GET_CODE (op0
) == REG
)
969 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
975 /* OFFSET is in UNITs, and UNIT is in bits.
976 store_fixed_bit_field wants offset in bytes. */
977 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
979 bitsdone
+= thissize
;
983 /* Generate code to extract a byte-field from STR_RTX
984 containing BITSIZE bits, starting at BITNUM,
985 and put it in TARGET if possible (if TARGET is nonzero).
986 Regardless of TARGET, we return the rtx for where the value is placed.
989 STR_RTX is the structure containing the byte (a REG or MEM).
990 UNSIGNEDP is nonzero if this is an unsigned bit field.
991 MODE is the natural mode of the field value once extracted.
992 TMODE is the mode the caller would like the value to have;
993 but the value may be returned with type MODE instead.
995 TOTAL_SIZE is the size in bytes of the containing structure,
998 If a TARGET is specified and we can store in it at no extra cost,
999 we do so, and return TARGET.
1000 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1001 if they are equally easy. */
1004 extract_bit_field (str_rtx
, bitsize
, bitnum
, unsignedp
,
1005 target
, mode
, tmode
, total_size
)
1007 unsigned HOST_WIDE_INT bitsize
;
1008 unsigned HOST_WIDE_INT bitnum
;
1011 enum machine_mode mode
, tmode
;
1012 HOST_WIDE_INT total_size
;
1015 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
1016 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
1017 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
1019 rtx spec_target
= target
;
1020 rtx spec_target_subreg
= 0;
1021 enum machine_mode int_mode
;
1022 enum machine_mode extv_mode
= mode_for_extraction (EP_extv
, 0);
1023 enum machine_mode extzv_mode
= mode_for_extraction (EP_extzv
, 0);
1024 enum machine_mode mode1
;
1027 /* Discount the part of the structure before the desired byte.
1028 We need to know how many bytes are safe to reference after it. */
1029 if (total_size
>= 0)
1030 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
1031 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
1033 if (tmode
== VOIDmode
)
1035 while (GET_CODE (op0
) == SUBREG
)
1037 int outer_size
= GET_MODE_BITSIZE (GET_MODE (op0
));
1038 int inner_size
= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)));
1040 offset
+= SUBREG_BYTE (op0
) / UNITS_PER_WORD
;
1042 inner_size
= MIN (inner_size
, BITS_PER_WORD
);
1044 if (BYTES_BIG_ENDIAN
&& (outer_size
< inner_size
))
1046 bitpos
+= inner_size
- outer_size
;
1049 offset
+= (bitpos
/ unit
);
1054 op0
= SUBREG_REG (op0
);
1057 if (GET_CODE (op0
) == REG
1058 && mode
== GET_MODE (op0
)
1060 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1062 /* We're trying to extract a full register from itself. */
1066 /* Make sure we are playing with integral modes. Pun with subregs
1069 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1070 if (imode
!= GET_MODE (op0
))
1072 if (GET_CODE (op0
) == MEM
)
1073 op0
= adjust_address (op0
, imode
, 0);
1074 else if (imode
!= BLKmode
)
1075 op0
= gen_lowpart (imode
, op0
);
1081 /* We may be accessing data outside the field, which means
1082 we can alias adjacent data. */
1083 if (GET_CODE (op0
) == MEM
)
1085 op0
= shallow_copy_rtx (op0
);
1086 set_mem_alias_set (op0
, 0);
1087 set_mem_expr (op0
, 0);
1090 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1091 If that's wrong, the solution is to test for it and set TARGET to 0
1094 /* If OP0 is a register, BITPOS must count within a word.
1095 But as we have it, it counts within whatever size OP0 now has.
1096 On a bigendian machine, these are not the same, so convert. */
1097 if (BYTES_BIG_ENDIAN
1098 && GET_CODE (op0
) != MEM
1099 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1100 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1102 /* Extracting a full-word or multi-word value
1103 from a structure in a register or aligned memory.
1104 This can be done with just SUBREG.
1105 So too extracting a subword value in
1106 the least significant part of the register. */
1108 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
1109 + (offset
* UNITS_PER_WORD
);
1111 mode1
= (VECTOR_MODE_P (tmode
)
1113 : mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0));
1115 if (((GET_CODE (op0
) != MEM
1116 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1117 GET_MODE_BITSIZE (GET_MODE (op0
)))
1118 && GET_MODE_SIZE (mode1
) != 0
1119 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1120 || (GET_CODE (op0
) == MEM
1121 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1122 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1123 && MEM_ALIGN (op0
) % bitsize
== 0))))
1124 && ((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1125 && bitpos
% BITS_PER_WORD
== 0)
1126 || (mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0) != BLKmode
1127 /* ??? The big endian test here is wrong. This is correct
1128 if the value is in a register, and if mode_for_size is not
1129 the same mode as op0. This causes us to get unnecessarily
1130 inefficient code from the Thumb port when -mbig-endian. */
1131 && (BYTES_BIG_ENDIAN
1132 ? bitpos
+ bitsize
== BITS_PER_WORD
1135 if (mode1
!= GET_MODE (op0
))
1137 if (GET_CODE (op0
) == SUBREG
)
1139 if (GET_MODE (SUBREG_REG (op0
)) == mode1
1140 || GET_MODE_CLASS (mode1
) == MODE_INT
1141 || GET_MODE_CLASS (mode1
) == MODE_PARTIAL_INT
)
1142 op0
= SUBREG_REG (op0
);
1144 /* Else we've got some float mode source being extracted into
1145 a different float mode destination -- this combination of
1146 subregs results in Severe Tire Damage. */
1149 if (GET_CODE (op0
) == REG
)
1150 op0
= gen_rtx_SUBREG (mode1
, op0
, byte_offset
);
1152 op0
= adjust_address (op0
, mode1
, offset
);
1155 return convert_to_mode (tmode
, op0
, unsignedp
);
1159 /* Handle fields bigger than a word. */
1161 if (bitsize
> BITS_PER_WORD
)
1163 /* Here we transfer the words of the field
1164 in the order least significant first.
1165 This is because the most significant word is the one which may
1166 be less than full. */
1168 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1171 if (target
== 0 || GET_CODE (target
) != REG
)
1172 target
= gen_reg_rtx (mode
);
1174 /* Indicate for flow that the entire target reg is being set. */
1175 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1177 for (i
= 0; i
< nwords
; i
++)
1179 /* If I is 0, use the low-order word in both field and target;
1180 if I is 1, use the next to lowest word; and so on. */
1181 /* Word number in TARGET to use. */
1182 unsigned int wordnum
1184 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1186 /* Offset from start of field in OP0. */
1187 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1188 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1189 * (int) BITS_PER_WORD
))
1190 : (int) i
* BITS_PER_WORD
);
1191 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1193 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1194 bitsize
- i
* BITS_PER_WORD
),
1195 bitnum
+ bit_offset
, 1, target_part
, mode
,
1196 word_mode
, total_size
);
1198 if (target_part
== 0)
1201 if (result_part
!= target_part
)
1202 emit_move_insn (target_part
, result_part
);
1207 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1208 need to be zero'd out. */
1209 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1211 unsigned int i
, total_words
;
1213 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1214 for (i
= nwords
; i
< total_words
; i
++)
1216 (operand_subword (target
,
1217 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1224 /* Signed bit field: sign-extend with two arithmetic shifts. */
1225 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1226 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1228 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1229 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1233 /* From here on we know the desired field is smaller than a word. */
1235 /* Check if there is a correspondingly-sized integer field, so we can
1236 safely extract it as one size of integer, if necessary; then
1237 truncate or extend to the size that is wanted; then use SUBREGs or
1238 convert_to_mode to get one of the modes we really wanted. */
1240 int_mode
= int_mode_for_mode (tmode
);
1241 if (int_mode
== BLKmode
)
1242 int_mode
= int_mode_for_mode (mode
);
1243 if (int_mode
== BLKmode
)
1244 abort (); /* Should probably push op0 out to memory and then
1247 /* OFFSET is the number of words or bytes (UNIT says which)
1248 from STR_RTX to the first word or byte containing part of the field. */
1250 if (GET_CODE (op0
) != MEM
)
1253 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1255 if (GET_CODE (op0
) != REG
)
1256 op0
= copy_to_reg (op0
);
1257 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1258 op0
, (offset
* UNITS_PER_WORD
));
1263 op0
= protect_from_queue (str_rtx
, 1);
1265 /* Now OFFSET is nonzero only for memory operands. */
1270 && (GET_MODE_BITSIZE (extzv_mode
) >= bitsize
)
1271 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1272 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extzv_mode
))))
1274 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1275 rtx bitsize_rtx
, bitpos_rtx
;
1276 rtx last
= get_last_insn ();
1278 rtx xtarget
= target
;
1279 rtx xspec_target
= spec_target
;
1280 rtx xspec_target_subreg
= spec_target_subreg
;
1282 enum machine_mode maxmode
= mode_for_extraction (EP_extzv
, 0);
1284 if (GET_CODE (xop0
) == MEM
)
1286 int save_volatile_ok
= volatile_ok
;
1289 /* Is the memory operand acceptable? */
1290 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1291 (xop0
, GET_MODE (xop0
))))
1293 /* No, load into a reg and extract from there. */
1294 enum machine_mode bestmode
;
1296 /* Get the mode to use for inserting into this field. If
1297 OP0 is BLKmode, get the smallest mode consistent with the
1298 alignment. If OP0 is a non-BLKmode object that is no
1299 wider than MAXMODE, use its mode. Otherwise, use the
1300 smallest mode containing the field. */
1302 if (GET_MODE (xop0
) == BLKmode
1303 || (GET_MODE_SIZE (GET_MODE (op0
))
1304 > GET_MODE_SIZE (maxmode
)))
1305 bestmode
= get_best_mode (bitsize
, bitnum
,
1306 MEM_ALIGN (xop0
), maxmode
,
1307 MEM_VOLATILE_P (xop0
));
1309 bestmode
= GET_MODE (xop0
);
1311 if (bestmode
== VOIDmode
1312 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1313 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1316 /* Compute offset as multiple of this unit,
1317 counting in bytes. */
1318 unit
= GET_MODE_BITSIZE (bestmode
);
1319 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1320 xbitpos
= bitnum
% unit
;
1321 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1323 /* Fetch it to a register in that size. */
1324 xop0
= force_reg (bestmode
, xop0
);
1326 /* XBITPOS counts within UNIT, which is what is expected. */
1329 /* Get ref to first byte containing part of the field. */
1330 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1332 volatile_ok
= save_volatile_ok
;
1335 /* If op0 is a register, we need it in MAXMODE (which is usually
1336 SImode). to make it acceptable to the format of extzv. */
1337 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1339 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1340 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1342 /* On big-endian machines, we count bits from the most significant.
1343 If the bit field insn does not, we must invert. */
1344 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1345 xbitpos
= unit
- bitsize
- xbitpos
;
1347 /* Now convert from counting within UNIT to counting in MAXMODE. */
1348 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1349 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1351 unit
= GET_MODE_BITSIZE (maxmode
);
1354 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1355 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1357 if (GET_MODE (xtarget
) != maxmode
)
1359 if (GET_CODE (xtarget
) == REG
)
1361 int wider
= (GET_MODE_SIZE (maxmode
)
1362 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1363 xtarget
= gen_lowpart (maxmode
, xtarget
);
1365 xspec_target_subreg
= xtarget
;
1368 xtarget
= gen_reg_rtx (maxmode
);
1371 /* If this machine's extzv insists on a register target,
1372 make sure we have one. */
1373 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1374 (xtarget
, maxmode
)))
1375 xtarget
= gen_reg_rtx (maxmode
);
1377 bitsize_rtx
= GEN_INT (bitsize
);
1378 bitpos_rtx
= GEN_INT (xbitpos
);
1380 pat
= gen_extzv (protect_from_queue (xtarget
, 1),
1381 xop0
, bitsize_rtx
, bitpos_rtx
);
1386 spec_target
= xspec_target
;
1387 spec_target_subreg
= xspec_target_subreg
;
1391 delete_insns_since (last
);
1392 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1398 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1404 && (GET_MODE_BITSIZE (extv_mode
) >= bitsize
)
1405 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1406 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extv_mode
))))
1408 int xbitpos
= bitpos
, xoffset
= offset
;
1409 rtx bitsize_rtx
, bitpos_rtx
;
1410 rtx last
= get_last_insn ();
1411 rtx xop0
= op0
, xtarget
= target
;
1412 rtx xspec_target
= spec_target
;
1413 rtx xspec_target_subreg
= spec_target_subreg
;
1415 enum machine_mode maxmode
= mode_for_extraction (EP_extv
, 0);
1417 if (GET_CODE (xop0
) == MEM
)
1419 /* Is the memory operand acceptable? */
1420 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1421 (xop0
, GET_MODE (xop0
))))
1423 /* No, load into a reg and extract from there. */
1424 enum machine_mode bestmode
;
1426 /* Get the mode to use for inserting into this field. If
1427 OP0 is BLKmode, get the smallest mode consistent with the
1428 alignment. If OP0 is a non-BLKmode object that is no
1429 wider than MAXMODE, use its mode. Otherwise, use the
1430 smallest mode containing the field. */
1432 if (GET_MODE (xop0
) == BLKmode
1433 || (GET_MODE_SIZE (GET_MODE (op0
))
1434 > GET_MODE_SIZE (maxmode
)))
1435 bestmode
= get_best_mode (bitsize
, bitnum
,
1436 MEM_ALIGN (xop0
), maxmode
,
1437 MEM_VOLATILE_P (xop0
));
1439 bestmode
= GET_MODE (xop0
);
1441 if (bestmode
== VOIDmode
1442 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1443 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1446 /* Compute offset as multiple of this unit,
1447 counting in bytes. */
1448 unit
= GET_MODE_BITSIZE (bestmode
);
1449 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1450 xbitpos
= bitnum
% unit
;
1451 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1453 /* Fetch it to a register in that size. */
1454 xop0
= force_reg (bestmode
, xop0
);
1456 /* XBITPOS counts within UNIT, which is what is expected. */
1459 /* Get ref to first byte containing part of the field. */
1460 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1463 /* If op0 is a register, we need it in MAXMODE (which is usually
1464 SImode) to make it acceptable to the format of extv. */
1465 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1467 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1468 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1470 /* On big-endian machines, we count bits from the most significant.
1471 If the bit field insn does not, we must invert. */
1472 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1473 xbitpos
= unit
- bitsize
- xbitpos
;
1475 /* XBITPOS counts within a size of UNIT.
1476 Adjust to count within a size of MAXMODE. */
1477 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1478 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1480 unit
= GET_MODE_BITSIZE (maxmode
);
1483 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1484 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1486 if (GET_MODE (xtarget
) != maxmode
)
1488 if (GET_CODE (xtarget
) == REG
)
1490 int wider
= (GET_MODE_SIZE (maxmode
)
1491 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1492 xtarget
= gen_lowpart (maxmode
, xtarget
);
1494 xspec_target_subreg
= xtarget
;
1497 xtarget
= gen_reg_rtx (maxmode
);
1500 /* If this machine's extv insists on a register target,
1501 make sure we have one. */
1502 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1503 (xtarget
, maxmode
)))
1504 xtarget
= gen_reg_rtx (maxmode
);
1506 bitsize_rtx
= GEN_INT (bitsize
);
1507 bitpos_rtx
= GEN_INT (xbitpos
);
1509 pat
= gen_extv (protect_from_queue (xtarget
, 1),
1510 xop0
, bitsize_rtx
, bitpos_rtx
);
1515 spec_target
= xspec_target
;
1516 spec_target_subreg
= xspec_target_subreg
;
1520 delete_insns_since (last
);
1521 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1527 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1530 if (target
== spec_target
)
1532 if (target
== spec_target_subreg
)
1534 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1536 /* If the target mode is floating-point, first convert to the
1537 integer mode of that size and then access it as a floating-point
1538 value via a SUBREG. */
1539 if (GET_MODE_CLASS (tmode
) != MODE_INT
1540 && GET_MODE_CLASS (tmode
) != MODE_PARTIAL_INT
)
1542 target
= convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode
),
1545 return gen_lowpart (tmode
, target
);
1548 return convert_to_mode (tmode
, target
, unsignedp
);
1553 /* Extract a bit field using shifts and boolean operations
1554 Returns an rtx to represent the value.
1555 OP0 addresses a register (word) or memory (byte).
1556 BITPOS says which bit within the word or byte the bit field starts in.
1557 OFFSET says how many bytes farther the bit field starts;
1558 it is 0 if OP0 is a register.
1559 BITSIZE says how many bits long the bit field is.
1560 (If OP0 is a register, it may be narrower than a full word,
1561 but BITPOS still counts within a full word,
1562 which is significant on bigendian machines.)
1564 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1565 If TARGET is nonzero, attempts to store the value there
1566 and return TARGET, but this is not guaranteed.
1567 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1570 extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1572 enum machine_mode tmode
;
1574 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
1577 unsigned int total_bits
= BITS_PER_WORD
;
1578 enum machine_mode mode
;
1580 if (GET_CODE (op0
) == SUBREG
|| GET_CODE (op0
) == REG
)
1582 /* Special treatment for a bit field split across two registers. */
1583 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1584 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1588 /* Get the proper mode to use for this field. We want a mode that
1589 includes the entire field. If such a mode would be larger than
1590 a word, we won't be doing the extraction the normal way. */
1592 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1593 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1595 if (mode
== VOIDmode
)
1596 /* The only way this should occur is if the field spans word
1598 return extract_split_bit_field (op0
, bitsize
,
1599 bitpos
+ offset
* BITS_PER_UNIT
,
1602 total_bits
= GET_MODE_BITSIZE (mode
);
1604 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1605 be in the range 0 to total_bits-1, and put any excess bytes in
1607 if (bitpos
>= total_bits
)
1609 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1610 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1614 /* Get ref to an aligned byte, halfword, or word containing the field.
1615 Adjust BITPOS to be position within a word,
1616 and OFFSET to be the offset of that word.
1617 Then alter OP0 to refer to that word. */
1618 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1619 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1620 op0
= adjust_address (op0
, mode
, offset
);
1623 mode
= GET_MODE (op0
);
1625 if (BYTES_BIG_ENDIAN
)
1626 /* BITPOS is the distance between our msb and that of OP0.
1627 Convert it to the distance from the lsb. */
1628 bitpos
= total_bits
- bitsize
- bitpos
;
1630 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1631 We have reduced the big-endian case to the little-endian case. */
1637 /* If the field does not already start at the lsb,
1638 shift it so it does. */
1639 tree amount
= build_int_2 (bitpos
, 0);
1640 /* Maybe propagate the target for the shift. */
1641 /* But not if we will return it--could confuse integrate.c. */
1642 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1643 && !REG_FUNCTION_VALUE_P (target
)
1645 if (tmode
!= mode
) subtarget
= 0;
1646 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1648 /* Convert the value to the desired mode. */
1650 op0
= convert_to_mode (tmode
, op0
, 1);
1652 /* Unless the msb of the field used to be the msb when we shifted,
1653 mask out the upper bits. */
1655 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1656 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1657 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1658 target
, 1, OPTAB_LIB_WIDEN
);
1662 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1663 then arithmetic-shift its lsb to the lsb of the word. */
1664 op0
= force_reg (mode
, op0
);
1668 /* Find the narrowest integer mode that contains the field. */
1670 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1671 mode
= GET_MODE_WIDER_MODE (mode
))
1672 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1674 op0
= convert_to_mode (mode
, op0
, 0);
1678 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1681 = build_int_2 (GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
), 0);
1682 /* Maybe propagate the target for the shift. */
1683 /* But not if we will return the result--could confuse integrate.c. */
1684 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1685 && ! REG_FUNCTION_VALUE_P (target
)
1687 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1690 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1691 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1695 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1696 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1697 complement of that if COMPLEMENT. The mask is truncated if
1698 necessary to the width of mode MODE. The mask is zero-extended if
1699 BITSIZE+BITPOS is too small for MODE. */
1702 mask_rtx (mode
, bitpos
, bitsize
, complement
)
1703 enum machine_mode mode
;
1704 int bitpos
, bitsize
, complement
;
1706 HOST_WIDE_INT masklow
, maskhigh
;
1708 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1709 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1713 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1714 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1715 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1717 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1720 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1722 if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1723 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1724 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1730 maskhigh
= ~maskhigh
;
1734 return immed_double_const (masklow
, maskhigh
, mode
);
1737 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1738 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1741 lshift_value (mode
, value
, bitpos
, bitsize
)
1742 enum machine_mode mode
;
1744 int bitpos
, bitsize
;
1746 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1747 HOST_WIDE_INT low
, high
;
1749 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1750 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1752 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1755 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1760 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1763 return immed_double_const (low
, high
, mode
);
1766 /* Extract a bit field that is split across two words
1767 and return an RTX for the result.
1769 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1770 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1771 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1774 extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
)
1776 unsigned HOST_WIDE_INT bitsize
, bitpos
;
1780 unsigned int bitsdone
= 0;
1781 rtx result
= NULL_RTX
;
1784 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1786 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1787 unit
= BITS_PER_WORD
;
1789 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1791 while (bitsdone
< bitsize
)
1793 unsigned HOST_WIDE_INT thissize
;
1795 unsigned HOST_WIDE_INT thispos
;
1796 unsigned HOST_WIDE_INT offset
;
1798 offset
= (bitpos
+ bitsdone
) / unit
;
1799 thispos
= (bitpos
+ bitsdone
) % unit
;
1801 /* THISSIZE must not overrun a word boundary. Otherwise,
1802 extract_fixed_bit_field will call us again, and we will mutually
1804 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1805 thissize
= MIN (thissize
, unit
- thispos
);
1807 /* If OP0 is a register, then handle OFFSET here.
1809 When handling multiword bitfields, extract_bit_field may pass
1810 down a word_mode SUBREG of a larger REG for a bitfield that actually
1811 crosses a word boundary. Thus, for a SUBREG, we must find
1812 the current word starting from the base register. */
1813 if (GET_CODE (op0
) == SUBREG
)
1815 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1816 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1817 GET_MODE (SUBREG_REG (op0
)));
1820 else if (GET_CODE (op0
) == REG
)
1822 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1828 /* Extract the parts in bit-counting order,
1829 whose meaning is determined by BYTES_PER_UNIT.
1830 OFFSET is in UNITs, and UNIT is in bits.
1831 extract_fixed_bit_field wants offset in bytes. */
1832 part
= extract_fixed_bit_field (word_mode
, word
,
1833 offset
* unit
/ BITS_PER_UNIT
,
1834 thissize
, thispos
, 0, 1);
1835 bitsdone
+= thissize
;
1837 /* Shift this part into place for the result. */
1838 if (BYTES_BIG_ENDIAN
)
1840 if (bitsize
!= bitsdone
)
1841 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1842 build_int_2 (bitsize
- bitsdone
, 0), 0, 1);
1846 if (bitsdone
!= thissize
)
1847 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1848 build_int_2 (bitsdone
- thissize
, 0), 0, 1);
1854 /* Combine the parts with bitwise or. This works
1855 because we extracted each part as an unsigned bit field. */
1856 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1862 /* Unsigned bit field: we are done. */
1865 /* Signed bit field: sign-extend with two arithmetic shifts. */
1866 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1867 build_int_2 (BITS_PER_WORD
- bitsize
, 0),
1869 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1870 build_int_2 (BITS_PER_WORD
- bitsize
, 0), NULL_RTX
, 0);
1873 /* Add INC into TARGET. */
1876 expand_inc (target
, inc
)
1879 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
1881 target
, 0, OPTAB_LIB_WIDEN
);
1882 if (value
!= target
)
1883 emit_move_insn (target
, value
);
1886 /* Subtract DEC from TARGET. */
1889 expand_dec (target
, dec
)
1892 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
1894 target
, 0, OPTAB_LIB_WIDEN
);
1895 if (value
!= target
)
1896 emit_move_insn (target
, value
);
1899 /* Output a shift instruction for expression code CODE,
1900 with SHIFTED being the rtx for the value to shift,
1901 and AMOUNT the tree for the amount to shift by.
1902 Store the result in the rtx TARGET, if that is convenient.
1903 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1904 Return the rtx for where the value is. */
1907 expand_shift (code
, mode
, shifted
, amount
, target
, unsignedp
)
1908 enum tree_code code
;
1909 enum machine_mode mode
;
1916 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
1917 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
1920 /* Previously detected shift-counts computed by NEGATE_EXPR
1921 and shifted in the other direction; but that does not work
1924 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
1926 #ifdef SHIFT_COUNT_TRUNCATED
1927 if (SHIFT_COUNT_TRUNCATED
)
1929 if (GET_CODE (op1
) == CONST_INT
1930 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
1931 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
1932 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
1933 % GET_MODE_BITSIZE (mode
));
1934 else if (GET_CODE (op1
) == SUBREG
1935 && subreg_lowpart_p (op1
))
1936 op1
= SUBREG_REG (op1
);
1940 if (op1
== const0_rtx
)
1943 for (try = 0; temp
== 0 && try < 3; try++)
1945 enum optab_methods methods
;
1948 methods
= OPTAB_DIRECT
;
1950 methods
= OPTAB_WIDEN
;
1952 methods
= OPTAB_LIB_WIDEN
;
1956 /* Widening does not work for rotation. */
1957 if (methods
== OPTAB_WIDEN
)
1959 else if (methods
== OPTAB_LIB_WIDEN
)
1961 /* If we have been unable to open-code this by a rotation,
1962 do it as the IOR of two shifts. I.e., to rotate A
1963 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1964 where C is the bitsize of A.
1966 It is theoretically possible that the target machine might
1967 not be able to perform either shift and hence we would
1968 be making two libcalls rather than just the one for the
1969 shift (similarly if IOR could not be done). We will allow
1970 this extremely unlikely lossage to avoid complicating the
1973 rtx subtarget
= target
== shifted
? 0 : target
;
1975 tree type
= TREE_TYPE (amount
);
1976 tree new_amount
= make_tree (type
, op1
);
1978 = fold (build (MINUS_EXPR
, type
,
1980 build_int_2 (GET_MODE_BITSIZE (mode
),
1984 shifted
= force_reg (mode
, shifted
);
1986 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
1987 mode
, shifted
, new_amount
, subtarget
, 1);
1988 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
1989 mode
, shifted
, other_amount
, 0, 1);
1990 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
1991 unsignedp
, methods
);
1994 temp
= expand_binop (mode
,
1995 left
? rotl_optab
: rotr_optab
,
1996 shifted
, op1
, target
, unsignedp
, methods
);
1998 /* If we don't have the rotate, but we are rotating by a constant
1999 that is in range, try a rotate in the opposite direction. */
2001 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
2003 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
2004 temp
= expand_binop (mode
,
2005 left
? rotr_optab
: rotl_optab
,
2007 GEN_INT (GET_MODE_BITSIZE (mode
)
2009 target
, unsignedp
, methods
);
2012 temp
= expand_binop (mode
,
2013 left
? ashl_optab
: lshr_optab
,
2014 shifted
, op1
, target
, unsignedp
, methods
);
2016 /* Do arithmetic shifts.
2017 Also, if we are going to widen the operand, we can just as well
2018 use an arithmetic right-shift instead of a logical one. */
2019 if (temp
== 0 && ! rotate
2020 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2022 enum optab_methods methods1
= methods
;
2024 /* If trying to widen a log shift to an arithmetic shift,
2025 don't accept an arithmetic shift of the same size. */
2027 methods1
= OPTAB_MUST_WIDEN
;
2029 /* Arithmetic shift */
2031 temp
= expand_binop (mode
,
2032 left
? ashl_optab
: ashr_optab
,
2033 shifted
, op1
, target
, unsignedp
, methods1
);
2036 /* We used to try extzv here for logical right shifts, but that was
2037 only useful for one machine, the VAX, and caused poor code
2038 generation there for lshrdi3, so the code was deleted and a
2039 define_expand for lshrsi3 was added to vax.md. */
2047 enum alg_code
{ alg_zero
, alg_m
, alg_shift
,
2048 alg_add_t_m2
, alg_sub_t_m2
,
2049 alg_add_factor
, alg_sub_factor
,
2050 alg_add_t2_m
, alg_sub_t2_m
,
2051 alg_add
, alg_subtract
, alg_factor
, alg_shiftop
};
2053 /* This structure records a sequence of operations.
2054 `ops' is the number of operations recorded.
2055 `cost' is their total cost.
2056 The operations are stored in `op' and the corresponding
2057 logarithms of the integer coefficients in `log'.
2059 These are the operations:
2060 alg_zero total := 0;
2061 alg_m total := multiplicand;
2062 alg_shift total := total * coeff
2063 alg_add_t_m2 total := total + multiplicand * coeff;
2064 alg_sub_t_m2 total := total - multiplicand * coeff;
2065 alg_add_factor total := total * coeff + total;
2066 alg_sub_factor total := total * coeff - total;
2067 alg_add_t2_m total := total * coeff + multiplicand;
2068 alg_sub_t2_m total := total * coeff - multiplicand;
2070 The first operand must be either alg_zero or alg_m. */
2076 /* The size of the OP and LOG fields are not directly related to the
2077 word size, but the worst-case algorithms will be if we have few
2078 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2079 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2080 in total wordsize operations. */
2081 enum alg_code op
[MAX_BITS_PER_WORD
];
2082 char log
[MAX_BITS_PER_WORD
];
2085 static void synth_mult
PARAMS ((struct algorithm
*,
2086 unsigned HOST_WIDE_INT
,
2088 static unsigned HOST_WIDE_INT choose_multiplier
PARAMS ((unsigned HOST_WIDE_INT
,
2090 unsigned HOST_WIDE_INT
*,
2092 static unsigned HOST_WIDE_INT invert_mod2n
PARAMS ((unsigned HOST_WIDE_INT
,
2094 /* Compute and return the best algorithm for multiplying by T.
2095 The algorithm must cost less than cost_limit
2096 If retval.cost >= COST_LIMIT, no algorithm was found and all
2097 other field of the returned struct are undefined. */
2100 synth_mult (alg_out
, t
, cost_limit
)
2101 struct algorithm
*alg_out
;
2102 unsigned HOST_WIDE_INT t
;
2106 struct algorithm
*alg_in
, *best_alg
;
2108 unsigned HOST_WIDE_INT q
;
2110 /* Indicate that no algorithm is yet found. If no algorithm
2111 is found, this value will be returned and indicate failure. */
2112 alg_out
->cost
= cost_limit
;
2114 if (cost_limit
<= 0)
2117 /* t == 1 can be done in zero cost. */
2122 alg_out
->op
[0] = alg_m
;
2126 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2130 if (zero_cost
>= cost_limit
)
2135 alg_out
->cost
= zero_cost
;
2136 alg_out
->op
[0] = alg_zero
;
2141 /* We'll be needing a couple extra algorithm structures now. */
2143 alg_in
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2144 best_alg
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2146 /* If we have a group of zero bits at the low-order part of T, try
2147 multiplying by the remaining bits and then doing a shift. */
2151 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2152 if (m
< BITS_PER_WORD
)
2155 cost
= shift_cost
[m
];
2156 synth_mult (alg_in
, q
, cost_limit
- cost
);
2158 cost
+= alg_in
->cost
;
2159 if (cost
< cost_limit
)
2161 struct algorithm
*x
;
2162 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2163 best_alg
->log
[best_alg
->ops
] = m
;
2164 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2170 /* If we have an odd number, add or subtract one. */
2173 unsigned HOST_WIDE_INT w
;
2175 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2177 /* If T was -1, then W will be zero after the loop. This is another
2178 case where T ends with ...111. Handling this with (T + 1) and
2179 subtract 1 produces slightly better code and results in algorithm
2180 selection much faster than treating it like the ...0111 case
2184 /* Reject the case where t is 3.
2185 Thus we prefer addition in that case. */
2188 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2191 synth_mult (alg_in
, t
+ 1, cost_limit
- cost
);
2193 cost
+= alg_in
->cost
;
2194 if (cost
< cost_limit
)
2196 struct algorithm
*x
;
2197 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2198 best_alg
->log
[best_alg
->ops
] = 0;
2199 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2205 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2208 synth_mult (alg_in
, t
- 1, cost_limit
- cost
);
2210 cost
+= alg_in
->cost
;
2211 if (cost
< cost_limit
)
2213 struct algorithm
*x
;
2214 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2215 best_alg
->log
[best_alg
->ops
] = 0;
2216 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2222 /* Look for factors of t of the form
2223 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2224 If we find such a factor, we can multiply by t using an algorithm that
2225 multiplies by q, shift the result by m and add/subtract it to itself.
2227 We search for large factors first and loop down, even if large factors
2228 are less probable than small; if we find a large factor we will find a
2229 good sequence quickly, and therefore be able to prune (by decreasing
2230 COST_LIMIT) the search. */
2232 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2234 unsigned HOST_WIDE_INT d
;
2236 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2237 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2239 cost
= MIN (shiftadd_cost
[m
], add_cost
+ shift_cost
[m
]);
2240 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2242 cost
+= alg_in
->cost
;
2243 if (cost
< cost_limit
)
2245 struct algorithm
*x
;
2246 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2247 best_alg
->log
[best_alg
->ops
] = m
;
2248 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2251 /* Other factors will have been taken care of in the recursion. */
2255 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2256 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2258 cost
= MIN (shiftsub_cost
[m
], add_cost
+ shift_cost
[m
]);
2259 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2261 cost
+= alg_in
->cost
;
2262 if (cost
< cost_limit
)
2264 struct algorithm
*x
;
2265 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2266 best_alg
->log
[best_alg
->ops
] = m
;
2267 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2274 /* Try shift-and-add (load effective address) instructions,
2275 i.e. do a*3, a*5, a*9. */
2281 if (m
>= 0 && m
< BITS_PER_WORD
)
2283 cost
= shiftadd_cost
[m
];
2284 synth_mult (alg_in
, (t
- 1) >> m
, cost_limit
- cost
);
2286 cost
+= alg_in
->cost
;
2287 if (cost
< cost_limit
)
2289 struct algorithm
*x
;
2290 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2291 best_alg
->log
[best_alg
->ops
] = m
;
2292 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2300 if (m
>= 0 && m
< BITS_PER_WORD
)
2302 cost
= shiftsub_cost
[m
];
2303 synth_mult (alg_in
, (t
+ 1) >> m
, cost_limit
- cost
);
2305 cost
+= alg_in
->cost
;
2306 if (cost
< cost_limit
)
2308 struct algorithm
*x
;
2309 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2310 best_alg
->log
[best_alg
->ops
] = m
;
2311 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2317 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2318 we have not found any algorithm. */
2319 if (cost_limit
== alg_out
->cost
)
2322 /* If we are getting a too long sequence for `struct algorithm'
2323 to record, make this search fail. */
2324 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2327 /* Copy the algorithm from temporary space to the space at alg_out.
2328 We avoid using structure assignment because the majority of
2329 best_alg is normally undefined, and this is a critical function. */
2330 alg_out
->ops
= best_alg
->ops
+ 1;
2331 alg_out
->cost
= cost_limit
;
2332 memcpy (alg_out
->op
, best_alg
->op
,
2333 alg_out
->ops
* sizeof *alg_out
->op
);
2334 memcpy (alg_out
->log
, best_alg
->log
,
2335 alg_out
->ops
* sizeof *alg_out
->log
);
2338 /* Perform a multiplication and return an rtx for the result.
2339 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2340 TARGET is a suggestion for where to store the result (an rtx).
2342 We check specially for a constant integer as OP1.
2343 If you want this check for OP0 as well, then before calling
2344 you should swap the two operands if OP0 would be constant. */
2347 expand_mult (mode
, op0
, op1
, target
, unsignedp
)
2348 enum machine_mode mode
;
2349 rtx op0
, op1
, target
;
2352 rtx const_op1
= op1
;
2354 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2355 less than or equal in size to `unsigned int' this doesn't matter.
2356 If the mode is larger than `unsigned int', then synth_mult works only
2357 if the constant value exactly fits in an `unsigned int' without any
2358 truncation. This means that multiplying by negative values does
2359 not work; results are off by 2^32 on a 32 bit machine. */
2361 /* If we are multiplying in DImode, it may still be a win
2362 to try to work with shifts and adds. */
2363 if (GET_CODE (op1
) == CONST_DOUBLE
2364 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
2365 && HOST_BITS_PER_INT
>= BITS_PER_WORD
2366 && CONST_DOUBLE_HIGH (op1
) == 0)
2367 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2368 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
2369 && GET_CODE (op1
) == CONST_INT
2370 && INTVAL (op1
) < 0)
2373 /* We used to test optimize here, on the grounds that it's better to
2374 produce a smaller program when -O is not used.
2375 But this causes such a terrible slowdown sometimes
2376 that it seems better to use synth_mult always. */
2378 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
2379 && (unsignedp
|| ! flag_trapv
))
2381 struct algorithm alg
;
2382 struct algorithm alg2
;
2383 HOST_WIDE_INT val
= INTVAL (op1
);
2384 HOST_WIDE_INT val_so_far
;
2387 enum {basic_variant
, negate_variant
, add_variant
} variant
= basic_variant
;
2389 /* op0 must be register to make mult_cost match the precomputed
2390 shiftadd_cost array. */
2391 op0
= force_reg (mode
, op0
);
2393 /* Try to do the computation three ways: multiply by the negative of OP1
2394 and then negate, do the multiplication directly, or do multiplication
2397 mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
2398 mult_cost
= MIN (12 * add_cost
, mult_cost
);
2400 synth_mult (&alg
, val
, mult_cost
);
2402 /* This works only if the inverted value actually fits in an
2404 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2406 synth_mult (&alg2
, - val
,
2407 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - negate_cost
);
2408 if (alg2
.cost
+ negate_cost
< alg
.cost
)
2409 alg
= alg2
, variant
= negate_variant
;
2412 /* This proves very useful for division-by-constant. */
2413 synth_mult (&alg2
, val
- 1,
2414 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - add_cost
);
2415 if (alg2
.cost
+ add_cost
< alg
.cost
)
2416 alg
= alg2
, variant
= add_variant
;
2418 if (alg
.cost
< mult_cost
)
2420 /* We found something cheaper than a multiply insn. */
2423 enum machine_mode nmode
;
2425 op0
= protect_from_queue (op0
, 0);
2427 /* Avoid referencing memory over and over.
2428 For speed, but also for correctness when mem is volatile. */
2429 if (GET_CODE (op0
) == MEM
)
2430 op0
= force_reg (mode
, op0
);
2432 /* ACCUM starts out either as OP0 or as a zero, depending on
2433 the first operation. */
2435 if (alg
.op
[0] == alg_zero
)
2437 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2440 else if (alg
.op
[0] == alg_m
)
2442 accum
= copy_to_mode_reg (mode
, op0
);
2448 for (opno
= 1; opno
< alg
.ops
; opno
++)
2450 int log
= alg
.log
[opno
];
2451 int preserve
= preserve_subexpressions_p ();
2452 rtx shift_subtarget
= preserve
? 0 : accum
;
2454 = (opno
== alg
.ops
- 1 && target
!= 0 && variant
!= add_variant
2457 rtx accum_target
= preserve
? 0 : accum
;
2459 switch (alg
.op
[opno
])
2462 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2463 build_int_2 (log
, 0), NULL_RTX
, 0);
2468 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2469 build_int_2 (log
, 0), NULL_RTX
, 0);
2470 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2472 ? add_target
: accum_target
);
2473 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2477 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2478 build_int_2 (log
, 0), NULL_RTX
, 0);
2479 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2481 ? add_target
: accum_target
);
2482 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2486 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2487 build_int_2 (log
, 0), shift_subtarget
,
2489 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2491 ? add_target
: accum_target
);
2492 val_so_far
= (val_so_far
<< log
) + 1;
2496 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2497 build_int_2 (log
, 0), shift_subtarget
,
2499 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2501 ? add_target
: accum_target
);
2502 val_so_far
= (val_so_far
<< log
) - 1;
2505 case alg_add_factor
:
2506 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2507 build_int_2 (log
, 0), NULL_RTX
, 0);
2508 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2510 ? add_target
: accum_target
);
2511 val_so_far
+= val_so_far
<< log
;
2514 case alg_sub_factor
:
2515 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2516 build_int_2 (log
, 0), NULL_RTX
, 0);
2517 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2518 (add_target
? add_target
2519 : preserve
? 0 : tem
));
2520 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2527 /* Write a REG_EQUAL note on the last insn so that we can cse
2528 multiplication sequences. Note that if ACCUM is a SUBREG,
2529 we've set the inner register and must properly indicate
2532 tem
= op0
, nmode
= mode
;
2533 if (GET_CODE (accum
) == SUBREG
)
2535 nmode
= GET_MODE (SUBREG_REG (accum
));
2536 tem
= gen_lowpart (nmode
, op0
);
2539 insn
= get_last_insn ();
2540 set_unique_reg_note (insn
,
2542 gen_rtx_MULT (nmode
, tem
,
2543 GEN_INT (val_so_far
)));
2546 if (variant
== negate_variant
)
2548 val_so_far
= - val_so_far
;
2549 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2551 else if (variant
== add_variant
)
2553 val_so_far
= val_so_far
+ 1;
2554 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2557 if (val
!= val_so_far
)
2564 /* This used to use umul_optab if unsigned, but for non-widening multiply
2565 there is no difference between signed and unsigned. */
2566 op0
= expand_binop (mode
,
2568 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
2569 ? smulv_optab
: smul_optab
,
2570 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2576 /* Return the smallest n such that 2**n >= X. */
2580 unsigned HOST_WIDE_INT x
;
2582 return floor_log2 (x
- 1) + 1;
2585 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2586 replace division by D, and put the least significant N bits of the result
2587 in *MULTIPLIER_PTR and return the most significant bit.
2589 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2590 needed precision is in PRECISION (should be <= N).
2592 PRECISION should be as small as possible so this function can choose
2593 multiplier more freely.
2595 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2596 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2598 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2599 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2602 unsigned HOST_WIDE_INT
2603 choose_multiplier (d
, n
, precision
, multiplier_ptr
, post_shift_ptr
, lgup_ptr
)
2604 unsigned HOST_WIDE_INT d
;
2607 unsigned HOST_WIDE_INT
*multiplier_ptr
;
2608 int *post_shift_ptr
;
2611 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
2612 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
2613 int lgup
, post_shift
;
2615 unsigned HOST_WIDE_INT nl
, dummy1
;
2616 HOST_WIDE_INT nh
, dummy2
;
2618 /* lgup = ceil(log2(divisor)); */
2619 lgup
= ceil_log2 (d
);
2625 pow2
= n
+ lgup
- precision
;
2627 if (pow
== 2 * HOST_BITS_PER_WIDE_INT
)
2629 /* We could handle this with some effort, but this case is much better
2630 handled directly with a scc insn, so rely on caller using that. */
2634 /* mlow = 2^(N + lgup)/d */
2635 if (pow
>= HOST_BITS_PER_WIDE_INT
)
2637 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
2643 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
2645 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2646 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
2648 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2649 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
2650 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
2652 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
2653 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2654 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
2656 if (mhigh_hi
&& nh
- d
>= d
)
2658 if (mhigh_hi
> 1 || mlow_hi
> 1)
2660 /* assert that mlow < mhigh. */
2661 if (! (mlow_hi
< mhigh_hi
|| (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
)))
2664 /* If precision == N, then mlow, mhigh exceed 2^N
2665 (but they do not exceed 2^(N+1)). */
2667 /* Reduce to lowest terms */
2668 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
2670 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
2671 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
2681 *post_shift_ptr
= post_shift
;
2683 if (n
< HOST_BITS_PER_WIDE_INT
)
2685 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
2686 *multiplier_ptr
= mhigh_lo
& mask
;
2687 return mhigh_lo
>= mask
;
2691 *multiplier_ptr
= mhigh_lo
;
2696 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2697 congruent to 1 (mod 2**N). */
2699 static unsigned HOST_WIDE_INT
2701 unsigned HOST_WIDE_INT x
;
2704 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2706 /* The algorithm notes that the choice y = x satisfies
2707 x*y == 1 mod 2^3, since x is assumed odd.
2708 Each iteration doubles the number of bits of significance in y. */
2710 unsigned HOST_WIDE_INT mask
;
2711 unsigned HOST_WIDE_INT y
= x
;
2714 mask
= (n
== HOST_BITS_PER_WIDE_INT
2715 ? ~(unsigned HOST_WIDE_INT
) 0
2716 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
2720 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
2726 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2727 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2728 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2729 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2732 The result is put in TARGET if that is convenient.
2734 MODE is the mode of operation. */
2737 expand_mult_highpart_adjust (mode
, adj_operand
, op0
, op1
, target
, unsignedp
)
2738 enum machine_mode mode
;
2739 rtx adj_operand
, op0
, op1
, target
;
2743 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
2745 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2746 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2748 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
2750 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2753 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
2754 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2756 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
2757 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2763 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2764 in TARGET if that is convenient, and return where the result is. If the
2765 operation can not be performed, 0 is returned.
2767 MODE is the mode of operation and result.
2769 UNSIGNEDP nonzero means unsigned multiply.
2771 MAX_COST is the total allowed cost for the expanded RTL. */
2774 expand_mult_highpart (mode
, op0
, cnst1
, target
, unsignedp
, max_cost
)
2775 enum machine_mode mode
;
2777 unsigned HOST_WIDE_INT cnst1
;
2781 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
2782 optab mul_highpart_optab
;
2785 int size
= GET_MODE_BITSIZE (mode
);
2788 /* We can't support modes wider than HOST_BITS_PER_INT. */
2789 if (size
> HOST_BITS_PER_WIDE_INT
)
2792 op1
= gen_int_mode (cnst1
, mode
);
2795 = immed_double_const (cnst1
,
2798 : -(cnst1
>> (HOST_BITS_PER_WIDE_INT
- 1))),
2801 /* expand_mult handles constant multiplication of word_mode
2802 or narrower. It does a poor job for large modes. */
2803 if (size
< BITS_PER_WORD
2804 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2806 /* We have to do this, since expand_binop doesn't do conversion for
2807 multiply. Maybe change expand_binop to handle widening multiply? */
2808 op0
= convert_to_mode (wider_mode
, op0
, unsignedp
);
2810 /* We know that this can't have signed overflow, so pretend this is
2811 an unsigned multiply. */
2812 tem
= expand_mult (wider_mode
, op0
, wide_op1
, NULL_RTX
, 0);
2813 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2814 build_int_2 (size
, 0), NULL_RTX
, 1);
2815 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2819 target
= gen_reg_rtx (mode
);
2821 /* Firstly, try using a multiplication insn that only generates the needed
2822 high part of the product, and in the sign flavor of unsignedp. */
2823 if (mul_highpart_cost
[(int) mode
] < max_cost
)
2825 mul_highpart_optab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
2826 target
= expand_binop (mode
, mul_highpart_optab
,
2827 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2832 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2833 Need to adjust the result after the multiplication. */
2834 if (size
- 1 < BITS_PER_WORD
2835 && (mul_highpart_cost
[(int) mode
] + 2 * shift_cost
[size
-1] + 4 * add_cost
2838 mul_highpart_optab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
2839 target
= expand_binop (mode
, mul_highpart_optab
,
2840 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2842 /* We used the wrong signedness. Adjust the result. */
2843 return expand_mult_highpart_adjust (mode
, target
, op0
,
2844 op1
, target
, unsignedp
);
2847 /* Try widening multiplication. */
2848 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
2849 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2850 && mul_widen_cost
[(int) wider_mode
] < max_cost
)
2852 op1
= force_reg (mode
, op1
);
2856 /* Try widening the mode and perform a non-widening multiplication. */
2857 moptab
= smul_optab
;
2858 if (smul_optab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2859 && size
- 1 < BITS_PER_WORD
2860 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2866 /* Try widening multiplication of opposite signedness, and adjust. */
2867 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
2868 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2869 && size
- 1 < BITS_PER_WORD
2870 && (mul_widen_cost
[(int) wider_mode
]
2871 + 2 * shift_cost
[size
-1] + 4 * add_cost
< max_cost
))
2873 rtx regop1
= force_reg (mode
, op1
);
2874 tem
= expand_binop (wider_mode
, moptab
, op0
, regop1
,
2875 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
2878 /* Extract the high half of the just generated product. */
2879 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2880 build_int_2 (size
, 0), NULL_RTX
, 1);
2881 tem
= convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2882 /* We used the wrong signedness. Adjust the result. */
2883 return expand_mult_highpart_adjust (mode
, tem
, op0
, op1
,
2891 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2892 tem
= expand_binop (wider_mode
, moptab
, op0
, op1
,
2893 NULL_RTX
, unsignedp
, OPTAB_WIDEN
);
2897 /* Extract the high half of the just generated product. */
2898 if (mode
== word_mode
)
2900 return gen_highpart (mode
, tem
);
2904 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2905 build_int_2 (size
, 0), NULL_RTX
, 1);
2906 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2910 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2911 if that is convenient, and returning where the result is.
2912 You may request either the quotient or the remainder as the result;
2913 specify REM_FLAG nonzero to get the remainder.
2915 CODE is the expression code for which kind of division this is;
2916 it controls how rounding is done. MODE is the machine mode to use.
2917 UNSIGNEDP nonzero means do unsigned division. */
2919 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2920 and then correct it by or'ing in missing high bits
2921 if result of ANDI is nonzero.
2922 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2923 This could optimize to a bfexts instruction.
2924 But C doesn't use these operations, so their optimizations are
2926 /* ??? For modulo, we don't actually need the highpart of the first product,
2927 the low part will do nicely. And for small divisors, the second multiply
2928 can also be a low-part only multiply or even be completely left out.
2929 E.g. to calculate the remainder of a division by 3 with a 32 bit
2930 multiply, multiply with 0x55555556 and extract the upper two bits;
2931 the result is exact for inputs up to 0x1fffffff.
2932 The input range can be reduced by using cross-sum rules.
2933 For odd divisors >= 3, the following table gives right shift counts
2934 so that if an number is shifted by an integer multiple of the given
2935 amount, the remainder stays the same:
2936 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2937 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2938 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2939 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2940 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2942 Cross-sum rules for even numbers can be derived by leaving as many bits
2943 to the right alone as the divisor has zeros to the right.
2944 E.g. if x is an unsigned 32 bit number:
2945 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2948 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2951 expand_divmod (rem_flag
, code
, mode
, op0
, op1
, target
, unsignedp
)
2953 enum tree_code code
;
2954 enum machine_mode mode
;
2955 rtx op0
, op1
, target
;
2958 enum machine_mode compute_mode
;
2960 rtx quotient
= 0, remainder
= 0;
2964 optab optab1
, optab2
;
2965 int op1_is_constant
, op1_is_pow2
;
2966 int max_cost
, extra_cost
;
2967 static HOST_WIDE_INT last_div_const
= 0;
2969 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
2970 op1_is_pow2
= (op1_is_constant
2971 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
2972 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
))))));
2975 This is the structure of expand_divmod:
2977 First comes code to fix up the operands so we can perform the operations
2978 correctly and efficiently.
2980 Second comes a switch statement with code specific for each rounding mode.
2981 For some special operands this code emits all RTL for the desired
2982 operation, for other cases, it generates only a quotient and stores it in
2983 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2984 to indicate that it has not done anything.
2986 Last comes code that finishes the operation. If QUOTIENT is set and
2987 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2988 QUOTIENT is not set, it is computed using trunc rounding.
2990 We try to generate special code for division and remainder when OP1 is a
2991 constant. If |OP1| = 2**n we can use shifts and some other fast
2992 operations. For other values of OP1, we compute a carefully selected
2993 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2996 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2997 half of the product. Different strategies for generating the product are
2998 implemented in expand_mult_highpart.
3000 If what we actually want is the remainder, we generate that by another
3001 by-constant multiplication and a subtraction. */
3003 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3004 code below will malfunction if we are, so check here and handle
3005 the special case if so. */
3006 if (op1
== const1_rtx
)
3007 return rem_flag
? const0_rtx
: op0
;
3009 /* When dividing by -1, we could get an overflow.
3010 negv_optab can handle overflows. */
3011 if (! unsignedp
&& op1
== constm1_rtx
)
3015 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3016 ? negv_optab
: neg_optab
, op0
, target
, 0);
3020 /* Don't use the function value register as a target
3021 since we have to read it as well as write it,
3022 and function-inlining gets confused by this. */
3023 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3024 /* Don't clobber an operand while doing a multi-step calculation. */
3025 || ((rem_flag
|| op1_is_constant
)
3026 && (reg_mentioned_p (target
, op0
)
3027 || (GET_CODE (op0
) == MEM
&& GET_CODE (target
) == MEM
)))
3028 || reg_mentioned_p (target
, op1
)
3029 || (GET_CODE (op1
) == MEM
&& GET_CODE (target
) == MEM
)))
3032 /* Get the mode in which to perform this computation. Normally it will
3033 be MODE, but sometimes we can't do the desired operation in MODE.
3034 If so, pick a wider mode in which we can do the operation. Convert
3035 to that mode at the start to avoid repeated conversions.
3037 First see what operations we need. These depend on the expression
3038 we are evaluating. (We assume that divxx3 insns exist under the
3039 same conditions that modxx3 insns and that these insns don't normally
3040 fail. If these assumptions are not correct, we may generate less
3041 efficient code in some cases.)
3043 Then see if we find a mode in which we can open-code that operation
3044 (either a division, modulus, or shift). Finally, check for the smallest
3045 mode for which we can do the operation with a library call. */
3047 /* We might want to refine this now that we have division-by-constant
3048 optimization. Since expand_mult_highpart tries so many variants, it is
3049 not straightforward to generalize this. Maybe we should make an array
3050 of possible modes in init_expmed? Save this for GCC 2.7. */
3052 optab1
= (op1_is_pow2
? (unsignedp
? lshr_optab
: ashr_optab
)
3053 : (unsignedp
? udiv_optab
: sdiv_optab
));
3054 optab2
= (op1_is_pow2
? optab1
: (unsignedp
? udivmod_optab
: sdivmod_optab
));
3056 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3057 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3058 if (optab1
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
3059 || optab2
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
)
3062 if (compute_mode
== VOIDmode
)
3063 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3064 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3065 if (optab1
->handlers
[(int) compute_mode
].libfunc
3066 || optab2
->handlers
[(int) compute_mode
].libfunc
)
3069 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3071 if (compute_mode
== VOIDmode
)
3072 compute_mode
= mode
;
3074 if (target
&& GET_MODE (target
) == compute_mode
)
3077 tquotient
= gen_reg_rtx (compute_mode
);
3079 size
= GET_MODE_BITSIZE (compute_mode
);
3081 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3082 (mode), and thereby get better code when OP1 is a constant. Do that
3083 later. It will require going over all usages of SIZE below. */
3084 size
= GET_MODE_BITSIZE (mode
);
3087 /* Only deduct something for a REM if the last divide done was
3088 for a different constant. Then set the constant of the last
3090 max_cost
= div_cost
[(int) compute_mode
]
3091 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3092 && INTVAL (op1
) == last_div_const
)
3093 ? mul_cost
[(int) compute_mode
] + add_cost
: 0);
3095 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3097 /* Now convert to the best mode to use. */
3098 if (compute_mode
!= mode
)
3100 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3101 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3103 /* convert_modes may have placed op1 into a register, so we
3104 must recompute the following. */
3105 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3106 op1_is_pow2
= (op1_is_constant
3107 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3109 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3112 /* If one of the operands is a volatile MEM, copy it into a register. */
3114 if (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
))
3115 op0
= force_reg (compute_mode
, op0
);
3116 if (GET_CODE (op1
) == MEM
&& MEM_VOLATILE_P (op1
))
3117 op1
= force_reg (compute_mode
, op1
);
3119 /* If we need the remainder or if OP1 is constant, we need to
3120 put OP0 in a register in case it has any queued subexpressions. */
3121 if (rem_flag
|| op1_is_constant
)
3122 op0
= force_reg (compute_mode
, op0
);
3124 last
= get_last_insn ();
3126 /* Promote floor rounding to trunc rounding for unsigned operations. */
3129 if (code
== FLOOR_DIV_EXPR
)
3130 code
= TRUNC_DIV_EXPR
;
3131 if (code
== FLOOR_MOD_EXPR
)
3132 code
= TRUNC_MOD_EXPR
;
3133 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3134 code
= TRUNC_DIV_EXPR
;
3137 if (op1
!= const0_rtx
)
3140 case TRUNC_MOD_EXPR
:
3141 case TRUNC_DIV_EXPR
:
3142 if (op1_is_constant
)
3146 unsigned HOST_WIDE_INT mh
, ml
;
3147 int pre_shift
, post_shift
;
3149 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3151 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3153 pre_shift
= floor_log2 (d
);
3157 = expand_binop (compute_mode
, and_optab
, op0
,
3158 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3162 return gen_lowpart (mode
, remainder
);
3164 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3165 build_int_2 (pre_shift
, 0),
3168 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3170 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3172 /* Most significant bit of divisor is set; emit an scc
3174 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3175 compute_mode
, 1, 1);
3181 /* Find a suitable multiplier and right shift count
3182 instead of multiplying with D. */
3184 mh
= choose_multiplier (d
, size
, size
,
3185 &ml
, &post_shift
, &dummy
);
3187 /* If the suggested multiplier is more than SIZE bits,
3188 we can do better for even divisors, using an
3189 initial right shift. */
3190 if (mh
!= 0 && (d
& 1) == 0)
3192 pre_shift
= floor_log2 (d
& -d
);
3193 mh
= choose_multiplier (d
>> pre_shift
, size
,
3195 &ml
, &post_shift
, &dummy
);
3206 if (post_shift
- 1 >= BITS_PER_WORD
)
3209 extra_cost
= (shift_cost
[post_shift
- 1]
3210 + shift_cost
[1] + 2 * add_cost
);
3211 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3213 max_cost
- extra_cost
);
3216 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3219 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3220 build_int_2 (1, 0), NULL_RTX
,1);
3221 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3225 = expand_shift (RSHIFT_EXPR
, compute_mode
, t4
,
3226 build_int_2 (post_shift
- 1, 0),
3233 if (pre_shift
>= BITS_PER_WORD
3234 || post_shift
>= BITS_PER_WORD
)
3237 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3238 build_int_2 (pre_shift
, 0),
3240 extra_cost
= (shift_cost
[pre_shift
]
3241 + shift_cost
[post_shift
]);
3242 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
3244 max_cost
- extra_cost
);
3248 = expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3249 build_int_2 (post_shift
, 0),
3254 else /* Too wide mode to use tricky code */
3257 insn
= get_last_insn ();
3259 && (set
= single_set (insn
)) != 0
3260 && SET_DEST (set
) == quotient
)
3261 set_unique_reg_note (insn
,
3263 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3265 else /* TRUNC_DIV, signed */
3267 unsigned HOST_WIDE_INT ml
;
3268 int lgup
, post_shift
;
3269 HOST_WIDE_INT d
= INTVAL (op1
);
3270 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
3272 /* n rem d = n rem -d */
3273 if (rem_flag
&& d
< 0)
3276 op1
= gen_int_mode (abs_d
, compute_mode
);
3282 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
3284 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3286 /* This case is not handled correctly below. */
3287 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
3288 compute_mode
, 1, 1);
3292 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
3293 && (rem_flag
? smod_pow2_cheap
: sdiv_pow2_cheap
)
3294 /* ??? The cheap metric is computed only for
3295 word_mode. If this operation is wider, this may
3296 not be so. Assume true if the optab has an
3297 expander for this mode. */
3298 && (((rem_flag
? smod_optab
: sdiv_optab
)
3299 ->handlers
[(int) compute_mode
].insn_code
3300 != CODE_FOR_nothing
)
3301 || (sdivmod_optab
->handlers
[(int) compute_mode
]
3302 .insn_code
!= CODE_FOR_nothing
)))
3304 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
3306 lgup
= floor_log2 (abs_d
);
3307 if (BRANCH_COST
< 1 || (abs_d
!= 2 && BRANCH_COST
< 3))
3309 rtx label
= gen_label_rtx ();
3312 t1
= copy_to_mode_reg (compute_mode
, op0
);
3313 do_cmp_and_jump (t1
, const0_rtx
, GE
,
3314 compute_mode
, label
);
3315 expand_inc (t1
, gen_int_mode (abs_d
- 1,
3318 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3319 build_int_2 (lgup
, 0),
3325 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3326 build_int_2 (size
- 1, 0),
3328 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3329 build_int_2 (size
- lgup
, 0),
3331 t3
= force_operand (gen_rtx_PLUS (compute_mode
,
3334 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3335 build_int_2 (lgup
, 0),
3339 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3343 insn
= get_last_insn ();
3345 && (set
= single_set (insn
)) != 0
3346 && SET_DEST (set
) == quotient
3347 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
3348 << (HOST_BITS_PER_WIDE_INT
- 1)))
3349 set_unique_reg_note (insn
,
3351 gen_rtx_DIV (compute_mode
,
3358 quotient
= expand_unop (compute_mode
, neg_optab
,
3359 quotient
, quotient
, 0);
3362 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3364 choose_multiplier (abs_d
, size
, size
- 1,
3365 &ml
, &post_shift
, &lgup
);
3366 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3370 if (post_shift
>= BITS_PER_WORD
3371 || size
- 1 >= BITS_PER_WORD
)
3374 extra_cost
= (shift_cost
[post_shift
]
3375 + shift_cost
[size
- 1] + add_cost
);
3376 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3378 max_cost
- extra_cost
);
3381 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3382 build_int_2 (post_shift
, 0), NULL_RTX
, 0);
3383 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3384 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3387 = force_operand (gen_rtx_MINUS (compute_mode
,
3392 = force_operand (gen_rtx_MINUS (compute_mode
,
3400 if (post_shift
>= BITS_PER_WORD
3401 || size
- 1 >= BITS_PER_WORD
)
3404 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
3405 extra_cost
= (shift_cost
[post_shift
]
3406 + shift_cost
[size
- 1] + 2 * add_cost
);
3407 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3409 max_cost
- extra_cost
);
3412 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
3415 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3416 build_int_2 (post_shift
, 0),
3418 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3419 build_int_2 (size
- 1, 0),
3423 = force_operand (gen_rtx_MINUS (compute_mode
,
3428 = force_operand (gen_rtx_MINUS (compute_mode
,
3433 else /* Too wide mode to use tricky code */
3436 insn
= get_last_insn ();
3438 && (set
= single_set (insn
)) != 0
3439 && SET_DEST (set
) == quotient
)
3440 set_unique_reg_note (insn
,
3442 gen_rtx_DIV (compute_mode
, op0
, op1
));
3447 delete_insns_since (last
);
3450 case FLOOR_DIV_EXPR
:
3451 case FLOOR_MOD_EXPR
:
3452 /* We will come here only for signed operations. */
3453 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3455 unsigned HOST_WIDE_INT mh
, ml
;
3456 int pre_shift
, lgup
, post_shift
;
3457 HOST_WIDE_INT d
= INTVAL (op1
);
3461 /* We could just as easily deal with negative constants here,
3462 but it does not seem worth the trouble for GCC 2.6. */
3463 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3465 pre_shift
= floor_log2 (d
);
3468 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
3469 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3470 remainder
, 0, OPTAB_LIB_WIDEN
);
3472 return gen_lowpart (mode
, remainder
);
3474 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3475 build_int_2 (pre_shift
, 0),
3482 mh
= choose_multiplier (d
, size
, size
- 1,
3483 &ml
, &post_shift
, &lgup
);
3487 if (post_shift
< BITS_PER_WORD
3488 && size
- 1 < BITS_PER_WORD
)
3490 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3491 build_int_2 (size
- 1, 0),
3493 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
3494 NULL_RTX
, 0, OPTAB_WIDEN
);
3495 extra_cost
= (shift_cost
[post_shift
]
3496 + shift_cost
[size
- 1] + 2 * add_cost
);
3497 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
3499 max_cost
- extra_cost
);
3502 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3503 build_int_2 (post_shift
, 0),
3505 quotient
= expand_binop (compute_mode
, xor_optab
,
3506 t4
, t1
, tquotient
, 0,
3514 rtx nsign
, t1
, t2
, t3
, t4
;
3515 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
3516 op0
, constm1_rtx
), NULL_RTX
);
3517 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
3519 nsign
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3520 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3521 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
3523 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
3528 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
3530 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3539 delete_insns_since (last
);
3541 /* Try using an instruction that produces both the quotient and
3542 remainder, using truncation. We can easily compensate the quotient
3543 or remainder to get floor rounding, once we have the remainder.
3544 Notice that we compute also the final remainder value here,
3545 and return the result right away. */
3546 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3547 target
= gen_reg_rtx (compute_mode
);
3552 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3553 quotient
= gen_reg_rtx (compute_mode
);
3558 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3559 remainder
= gen_reg_rtx (compute_mode
);
3562 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
3563 quotient
, remainder
, 0))
3565 /* This could be computed with a branch-less sequence.
3566 Save that for later. */
3568 rtx label
= gen_label_rtx ();
3569 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
3570 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3571 NULL_RTX
, 0, OPTAB_WIDEN
);
3572 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
3573 expand_dec (quotient
, const1_rtx
);
3574 expand_inc (remainder
, op1
);
3576 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3579 /* No luck with division elimination or divmod. Have to do it
3580 by conditionally adjusting op0 *and* the result. */
3582 rtx label1
, label2
, label3
, label4
, label5
;
3586 quotient
= gen_reg_rtx (compute_mode
);
3587 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3588 label1
= gen_label_rtx ();
3589 label2
= gen_label_rtx ();
3590 label3
= gen_label_rtx ();
3591 label4
= gen_label_rtx ();
3592 label5
= gen_label_rtx ();
3593 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3594 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
3595 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3596 quotient
, 0, OPTAB_LIB_WIDEN
);
3597 if (tem
!= quotient
)
3598 emit_move_insn (quotient
, tem
);
3599 emit_jump_insn (gen_jump (label5
));
3601 emit_label (label1
);
3602 expand_inc (adjusted_op0
, const1_rtx
);
3603 emit_jump_insn (gen_jump (label4
));
3605 emit_label (label2
);
3606 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
3607 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3608 quotient
, 0, OPTAB_LIB_WIDEN
);
3609 if (tem
!= quotient
)
3610 emit_move_insn (quotient
, tem
);
3611 emit_jump_insn (gen_jump (label5
));
3613 emit_label (label3
);
3614 expand_dec (adjusted_op0
, const1_rtx
);
3615 emit_label (label4
);
3616 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3617 quotient
, 0, OPTAB_LIB_WIDEN
);
3618 if (tem
!= quotient
)
3619 emit_move_insn (quotient
, tem
);
3620 expand_dec (quotient
, const1_rtx
);
3621 emit_label (label5
);
3629 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
3632 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3633 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3634 build_int_2 (floor_log2 (d
), 0),
3636 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3638 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3639 t3
= gen_reg_rtx (compute_mode
);
3640 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3641 compute_mode
, 1, 1);
3645 lab
= gen_label_rtx ();
3646 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3647 expand_inc (t1
, const1_rtx
);
3652 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3658 /* Try using an instruction that produces both the quotient and
3659 remainder, using truncation. We can easily compensate the
3660 quotient or remainder to get ceiling rounding, once we have the
3661 remainder. Notice that we compute also the final remainder
3662 value here, and return the result right away. */
3663 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3664 target
= gen_reg_rtx (compute_mode
);
3668 remainder
= (GET_CODE (target
) == REG
3669 ? target
: gen_reg_rtx (compute_mode
));
3670 quotient
= gen_reg_rtx (compute_mode
);
3674 quotient
= (GET_CODE (target
) == REG
3675 ? target
: gen_reg_rtx (compute_mode
));
3676 remainder
= gen_reg_rtx (compute_mode
);
3679 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
3682 /* This could be computed with a branch-less sequence.
3683 Save that for later. */
3684 rtx label
= gen_label_rtx ();
3685 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3686 compute_mode
, label
);
3687 expand_inc (quotient
, const1_rtx
);
3688 expand_dec (remainder
, op1
);
3690 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3693 /* No luck with division elimination or divmod. Have to do it
3694 by conditionally adjusting op0 *and* the result. */
3697 rtx adjusted_op0
, tem
;
3699 quotient
= gen_reg_rtx (compute_mode
);
3700 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3701 label1
= gen_label_rtx ();
3702 label2
= gen_label_rtx ();
3703 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
3704 compute_mode
, label1
);
3705 emit_move_insn (quotient
, const0_rtx
);
3706 emit_jump_insn (gen_jump (label2
));
3708 emit_label (label1
);
3709 expand_dec (adjusted_op0
, const1_rtx
);
3710 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
3711 quotient
, 1, OPTAB_LIB_WIDEN
);
3712 if (tem
!= quotient
)
3713 emit_move_insn (quotient
, tem
);
3714 expand_inc (quotient
, const1_rtx
);
3715 emit_label (label2
);
3720 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3721 && INTVAL (op1
) >= 0)
3723 /* This is extremely similar to the code for the unsigned case
3724 above. For 2.7 we should merge these variants, but for
3725 2.6.1 I don't want to touch the code for unsigned since that
3726 get used in C. The signed case will only be used by other
3730 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3731 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3732 build_int_2 (floor_log2 (d
), 0),
3734 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3736 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3737 t3
= gen_reg_rtx (compute_mode
);
3738 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3739 compute_mode
, 1, 1);
3743 lab
= gen_label_rtx ();
3744 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3745 expand_inc (t1
, const1_rtx
);
3750 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3756 /* Try using an instruction that produces both the quotient and
3757 remainder, using truncation. We can easily compensate the
3758 quotient or remainder to get ceiling rounding, once we have the
3759 remainder. Notice that we compute also the final remainder
3760 value here, and return the result right away. */
3761 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3762 target
= gen_reg_rtx (compute_mode
);
3765 remainder
= (GET_CODE (target
) == REG
3766 ? target
: gen_reg_rtx (compute_mode
));
3767 quotient
= gen_reg_rtx (compute_mode
);
3771 quotient
= (GET_CODE (target
) == REG
3772 ? target
: gen_reg_rtx (compute_mode
));
3773 remainder
= gen_reg_rtx (compute_mode
);
3776 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
3779 /* This could be computed with a branch-less sequence.
3780 Save that for later. */
3782 rtx label
= gen_label_rtx ();
3783 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3784 compute_mode
, label
);
3785 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3786 NULL_RTX
, 0, OPTAB_WIDEN
);
3787 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
3788 expand_inc (quotient
, const1_rtx
);
3789 expand_dec (remainder
, op1
);
3791 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3794 /* No luck with division elimination or divmod. Have to do it
3795 by conditionally adjusting op0 *and* the result. */
3797 rtx label1
, label2
, label3
, label4
, label5
;
3801 quotient
= gen_reg_rtx (compute_mode
);
3802 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3803 label1
= gen_label_rtx ();
3804 label2
= gen_label_rtx ();
3805 label3
= gen_label_rtx ();
3806 label4
= gen_label_rtx ();
3807 label5
= gen_label_rtx ();
3808 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3809 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
3810 compute_mode
, label1
);
3811 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3812 quotient
, 0, OPTAB_LIB_WIDEN
);
3813 if (tem
!= quotient
)
3814 emit_move_insn (quotient
, tem
);
3815 emit_jump_insn (gen_jump (label5
));
3817 emit_label (label1
);
3818 expand_dec (adjusted_op0
, const1_rtx
);
3819 emit_jump_insn (gen_jump (label4
));
3821 emit_label (label2
);
3822 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
3823 compute_mode
, label3
);
3824 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3825 quotient
, 0, OPTAB_LIB_WIDEN
);
3826 if (tem
!= quotient
)
3827 emit_move_insn (quotient
, tem
);
3828 emit_jump_insn (gen_jump (label5
));
3830 emit_label (label3
);
3831 expand_inc (adjusted_op0
, const1_rtx
);
3832 emit_label (label4
);
3833 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3834 quotient
, 0, OPTAB_LIB_WIDEN
);
3835 if (tem
!= quotient
)
3836 emit_move_insn (quotient
, tem
);
3837 expand_inc (quotient
, const1_rtx
);
3838 emit_label (label5
);
3843 case EXACT_DIV_EXPR
:
3844 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3846 HOST_WIDE_INT d
= INTVAL (op1
);
3847 unsigned HOST_WIDE_INT ml
;
3851 pre_shift
= floor_log2 (d
& -d
);
3852 ml
= invert_mod2n (d
>> pre_shift
, size
);
3853 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3854 build_int_2 (pre_shift
, 0), NULL_RTX
, unsignedp
);
3855 quotient
= expand_mult (compute_mode
, t1
,
3856 gen_int_mode (ml
, compute_mode
),
3859 insn
= get_last_insn ();
3860 set_unique_reg_note (insn
,
3862 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
3868 case ROUND_DIV_EXPR
:
3869 case ROUND_MOD_EXPR
:
3874 label
= gen_label_rtx ();
3875 quotient
= gen_reg_rtx (compute_mode
);
3876 remainder
= gen_reg_rtx (compute_mode
);
3877 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
3880 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
3881 quotient
, 1, OPTAB_LIB_WIDEN
);
3882 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
3883 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3884 remainder
, 1, OPTAB_LIB_WIDEN
);
3886 tem
= plus_constant (op1
, -1);
3887 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3888 build_int_2 (1, 0), NULL_RTX
, 1);
3889 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
3890 expand_inc (quotient
, const1_rtx
);
3891 expand_dec (remainder
, op1
);
3896 rtx abs_rem
, abs_op1
, tem
, mask
;
3898 label
= gen_label_rtx ();
3899 quotient
= gen_reg_rtx (compute_mode
);
3900 remainder
= gen_reg_rtx (compute_mode
);
3901 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
3904 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
3905 quotient
, 0, OPTAB_LIB_WIDEN
);
3906 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
3907 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3908 remainder
, 0, OPTAB_LIB_WIDEN
);
3910 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
3911 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
3912 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
3913 build_int_2 (1, 0), NULL_RTX
, 1);
3914 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
3915 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3916 NULL_RTX
, 0, OPTAB_WIDEN
);
3917 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3918 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3919 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
3920 NULL_RTX
, 0, OPTAB_WIDEN
);
3921 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3922 NULL_RTX
, 0, OPTAB_WIDEN
);
3923 expand_inc (quotient
, tem
);
3924 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
3925 NULL_RTX
, 0, OPTAB_WIDEN
);
3926 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3927 NULL_RTX
, 0, OPTAB_WIDEN
);
3928 expand_dec (remainder
, tem
);
3931 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3939 if (target
&& GET_MODE (target
) != compute_mode
)
3944 /* Try to produce the remainder without producing the quotient.
3945 If we seem to have a divmod pattern that does not require widening,
3946 don't try widening here. We should really have an WIDEN argument
3947 to expand_twoval_binop, since what we'd really like to do here is
3948 1) try a mod insn in compute_mode
3949 2) try a divmod insn in compute_mode
3950 3) try a div insn in compute_mode and multiply-subtract to get
3952 4) try the same things with widening allowed. */
3954 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
3957 ((optab2
->handlers
[(int) compute_mode
].insn_code
3958 != CODE_FOR_nothing
)
3959 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3962 /* No luck there. Can we do remainder and divide at once
3963 without a library call? */
3964 remainder
= gen_reg_rtx (compute_mode
);
3965 if (! expand_twoval_binop ((unsignedp
3969 NULL_RTX
, remainder
, unsignedp
))
3974 return gen_lowpart (mode
, remainder
);
3977 /* Produce the quotient. Try a quotient insn, but not a library call.
3978 If we have a divmod in this mode, use it in preference to widening
3979 the div (for this test we assume it will not fail). Note that optab2
3980 is set to the one of the two optabs that the call below will use. */
3982 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
3983 op0
, op1
, rem_flag
? NULL_RTX
: target
,
3985 ((optab2
->handlers
[(int) compute_mode
].insn_code
3986 != CODE_FOR_nothing
)
3987 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3991 /* No luck there. Try a quotient-and-remainder insn,
3992 keeping the quotient alone. */
3993 quotient
= gen_reg_rtx (compute_mode
);
3994 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
3996 quotient
, NULL_RTX
, unsignedp
))
4000 /* Still no luck. If we are not computing the remainder,
4001 use a library call for the quotient. */
4002 quotient
= sign_expand_binop (compute_mode
,
4003 udiv_optab
, sdiv_optab
,
4005 unsignedp
, OPTAB_LIB_WIDEN
);
4012 if (target
&& GET_MODE (target
) != compute_mode
)
4016 /* No divide instruction either. Use library for remainder. */
4017 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4019 unsignedp
, OPTAB_LIB_WIDEN
);
4022 /* We divided. Now finish doing X - Y * (X / Y). */
4023 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4024 NULL_RTX
, unsignedp
);
4025 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4026 remainder
, target
, unsignedp
,
4031 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4034 /* Return a tree node with data type TYPE, describing the value of X.
4035 Usually this is an RTL_EXPR, if there is no obvious better choice.
4036 X may be an expression, however we only support those expressions
4037 generated by loop.c. */
4046 switch (GET_CODE (x
))
4049 t
= build_int_2 (INTVAL (x
),
4050 (TREE_UNSIGNED (type
)
4051 && (GET_MODE_BITSIZE (TYPE_MODE (type
)) < HOST_BITS_PER_WIDE_INT
))
4052 || INTVAL (x
) >= 0 ? 0 : -1);
4053 TREE_TYPE (t
) = type
;
4057 if (GET_MODE (x
) == VOIDmode
)
4059 t
= build_int_2 (CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4060 TREE_TYPE (t
) = type
;
4066 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4067 t
= build_real (type
, d
);
4078 units
= CONST_VECTOR_NUNITS (x
);
4080 /* Build a tree with vector elements. */
4081 for (i
= units
- 1; i
>= 0; --i
)
4083 elt
= CONST_VECTOR_ELT (x
, i
);
4084 t
= tree_cons (NULL_TREE
, make_tree (type
, elt
), t
);
4087 return build_vector (type
, t
);
4091 return fold (build (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4092 make_tree (type
, XEXP (x
, 1))));
4095 return fold (build (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4096 make_tree (type
, XEXP (x
, 1))));
4099 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4102 return fold (build (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4103 make_tree (type
, XEXP (x
, 1))));
4106 return fold (build (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4107 make_tree (type
, XEXP (x
, 1))));
4110 return fold (convert (type
,
4111 build (RSHIFT_EXPR
, unsigned_type (type
),
4112 make_tree (unsigned_type (type
),
4114 make_tree (type
, XEXP (x
, 1)))));
4117 return fold (convert (type
,
4118 build (RSHIFT_EXPR
, signed_type (type
),
4119 make_tree (signed_type (type
), XEXP (x
, 0)),
4120 make_tree (type
, XEXP (x
, 1)))));
4123 if (TREE_CODE (type
) != REAL_TYPE
)
4124 t
= signed_type (type
);
4128 return fold (convert (type
,
4129 build (TRUNC_DIV_EXPR
, t
,
4130 make_tree (t
, XEXP (x
, 0)),
4131 make_tree (t
, XEXP (x
, 1)))));
4133 t
= unsigned_type (type
);
4134 return fold (convert (type
,
4135 build (TRUNC_DIV_EXPR
, t
,
4136 make_tree (t
, XEXP (x
, 0)),
4137 make_tree (t
, XEXP (x
, 1)))));
4139 t
= make_node (RTL_EXPR
);
4140 TREE_TYPE (t
) = type
;
4142 #ifdef POINTERS_EXTEND_UNSIGNED
4143 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4144 ptr_mode. So convert. */
4145 if (POINTER_TYPE_P (type
) && GET_MODE (x
) != TYPE_MODE (type
))
4146 x
= convert_memory_address (TYPE_MODE (type
), x
);
4149 RTL_EXPR_RTL (t
) = x
;
4150 /* There are no insns to be output
4151 when this rtl_expr is used. */
4152 RTL_EXPR_SEQUENCE (t
) = 0;
4157 /* Return an rtx representing the value of X * MULT + ADD.
4158 TARGET is a suggestion for where to store the result (an rtx).
4159 MODE is the machine mode for the computation.
4160 X and MULT must have mode MODE. ADD may have a different mode.
4161 So can X (defaults to same as MODE).
4162 UNSIGNEDP is non-zero to do unsigned multiplication.
4163 This may emit insns. */
4166 expand_mult_add (x
, target
, mult
, add
, mode
, unsignedp
)
4167 rtx x
, target
, mult
, add
;
4168 enum machine_mode mode
;
4171 tree type
= type_for_mode (mode
, unsignedp
);
4172 tree add_type
= (GET_MODE (add
) == VOIDmode
4173 ? type
: type_for_mode (GET_MODE (add
), unsignedp
));
4174 tree result
= fold (build (PLUS_EXPR
, type
,
4175 fold (build (MULT_EXPR
, type
,
4176 make_tree (type
, x
),
4177 make_tree (type
, mult
))),
4178 make_tree (add_type
, add
)));
4180 return expand_expr (result
, target
, VOIDmode
, 0);
4183 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4184 and returning TARGET.
4186 If TARGET is 0, a pseudo-register or constant is returned. */
4189 expand_and (mode
, op0
, op1
, target
)
4190 enum machine_mode mode
;
4191 rtx op0
, op1
, target
;
4195 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
4196 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
4198 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4202 else if (tem
!= target
)
4203 emit_move_insn (target
, tem
);
4207 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4208 and storing in TARGET. Normally return TARGET.
4209 Return 0 if that cannot be done.
4211 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4212 it is VOIDmode, they cannot both be CONST_INT.
4214 UNSIGNEDP is for the case where we have to widen the operands
4215 to perform the operation. It says to use zero-extension.
4217 NORMALIZEP is 1 if we should convert the result to be either zero
4218 or one. Normalize is -1 if we should convert the result to be
4219 either zero or -1. If NORMALIZEP is zero, the result will be left
4220 "raw" out of the scc insn. */
4223 emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4227 enum machine_mode mode
;
4232 enum insn_code icode
;
4233 enum machine_mode compare_mode
;
4234 enum machine_mode target_mode
= GET_MODE (target
);
4236 rtx last
= get_last_insn ();
4237 rtx pattern
, comparison
;
4239 /* ??? Ok to do this and then fail? */
4240 op0
= protect_from_queue (op0
, 0);
4241 op1
= protect_from_queue (op1
, 0);
4244 code
= unsigned_condition (code
);
4246 /* If one operand is constant, make it the second one. Only do this
4247 if the other operand is not constant as well. */
4249 if (swap_commutative_operands_p (op0
, op1
))
4254 code
= swap_condition (code
);
4257 if (mode
== VOIDmode
)
4258 mode
= GET_MODE (op0
);
4260 /* For some comparisons with 1 and -1, we can convert this to
4261 comparisons with zero. This will often produce more opportunities for
4262 store-flag insns. */
4267 if (op1
== const1_rtx
)
4268 op1
= const0_rtx
, code
= LE
;
4271 if (op1
== constm1_rtx
)
4272 op1
= const0_rtx
, code
= LT
;
4275 if (op1
== const1_rtx
)
4276 op1
= const0_rtx
, code
= GT
;
4279 if (op1
== constm1_rtx
)
4280 op1
= const0_rtx
, code
= GE
;
4283 if (op1
== const1_rtx
)
4284 op1
= const0_rtx
, code
= NE
;
4287 if (op1
== const1_rtx
)
4288 op1
= const0_rtx
, code
= EQ
;
4294 /* If we are comparing a double-word integer with zero, we can convert
4295 the comparison into one involving a single word. */
4296 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
4297 && GET_MODE_CLASS (mode
) == MODE_INT
4298 && op1
== const0_rtx
4299 && (GET_CODE (op0
) != MEM
|| ! MEM_VOLATILE_P (op0
)))
4301 if (code
== EQ
|| code
== NE
)
4303 /* Do a logical OR of the two words and compare the result. */
4304 rtx op0h
= gen_highpart (word_mode
, op0
);
4305 rtx op0l
= gen_lowpart (word_mode
, op0
);
4306 rtx op0both
= expand_binop (word_mode
, ior_optab
, op0h
, op0l
,
4307 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
4309 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
4310 unsignedp
, normalizep
);
4312 else if (code
== LT
|| code
== GE
)
4313 /* If testing the sign bit, can just test on high word. */
4314 return emit_store_flag (target
, code
, gen_highpart (word_mode
, op0
),
4315 op1
, word_mode
, unsignedp
, normalizep
);
4318 /* From now on, we won't change CODE, so set ICODE now. */
4319 icode
= setcc_gen_code
[(int) code
];
4321 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4322 complement of A (for GE) and shifting the sign bit to the low bit. */
4323 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
4324 && GET_MODE_CLASS (mode
) == MODE_INT
4325 && (normalizep
|| STORE_FLAG_VALUE
== 1
4326 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4327 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4328 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
4332 /* If the result is to be wider than OP0, it is best to convert it
4333 first. If it is to be narrower, it is *incorrect* to convert it
4335 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
4337 op0
= protect_from_queue (op0
, 0);
4338 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4342 if (target_mode
!= mode
)
4346 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
4347 ((STORE_FLAG_VALUE
== 1 || normalizep
)
4348 ? 0 : subtarget
), 0);
4350 if (STORE_FLAG_VALUE
== 1 || normalizep
)
4351 /* If we are supposed to produce a 0/1 value, we want to do
4352 a logical shift from the sign bit to the low-order bit; for
4353 a -1/0 value, we do an arithmetic shift. */
4354 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4355 size_int (GET_MODE_BITSIZE (mode
) - 1),
4356 subtarget
, normalizep
!= -1);
4358 if (mode
!= target_mode
)
4359 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4364 if (icode
!= CODE_FOR_nothing
)
4366 insn_operand_predicate_fn pred
;
4368 /* We think we may be able to do this with a scc insn. Emit the
4369 comparison and then the scc insn.
4371 compare_from_rtx may call emit_queue, which would be deleted below
4372 if the scc insn fails. So call it ourselves before setting LAST.
4373 Likewise for do_pending_stack_adjust. */
4376 do_pending_stack_adjust ();
4377 last
= get_last_insn ();
4380 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
);
4381 if (GET_CODE (comparison
) == CONST_INT
)
4382 return (comparison
== const0_rtx
? const0_rtx
4383 : normalizep
== 1 ? const1_rtx
4384 : normalizep
== -1 ? constm1_rtx
4387 /* The code of COMPARISON may not match CODE if compare_from_rtx
4388 decided to swap its operands and reverse the original code.
4390 We know that compare_from_rtx returns either a CONST_INT or
4391 a new comparison code, so it is safe to just extract the
4392 code from COMPARISON. */
4393 code
= GET_CODE (comparison
);
4395 /* Get a reference to the target in the proper mode for this insn. */
4396 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
4398 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
4399 if (preserve_subexpressions_p ()
4400 || ! (*pred
) (subtarget
, compare_mode
))
4401 subtarget
= gen_reg_rtx (compare_mode
);
4403 pattern
= GEN_FCN (icode
) (subtarget
);
4406 emit_insn (pattern
);
4408 /* If we are converting to a wider mode, first convert to
4409 TARGET_MODE, then normalize. This produces better combining
4410 opportunities on machines that have a SIGN_EXTRACT when we are
4411 testing a single bit. This mostly benefits the 68k.
4413 If STORE_FLAG_VALUE does not have the sign bit set when
4414 interpreted in COMPARE_MODE, we can do this conversion as
4415 unsigned, which is usually more efficient. */
4416 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
4418 convert_move (target
, subtarget
,
4419 (GET_MODE_BITSIZE (compare_mode
)
4420 <= HOST_BITS_PER_WIDE_INT
)
4421 && 0 == (STORE_FLAG_VALUE
4422 & ((HOST_WIDE_INT
) 1
4423 << (GET_MODE_BITSIZE (compare_mode
) -1))));
4425 compare_mode
= target_mode
;
4430 /* If we want to keep subexpressions around, don't reuse our
4433 if (preserve_subexpressions_p ())
4436 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4437 we don't have to do anything. */
4438 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
4440 /* STORE_FLAG_VALUE might be the most negative number, so write
4441 the comparison this way to avoid a compiler-time warning. */
4442 else if (- normalizep
== STORE_FLAG_VALUE
)
4443 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
4445 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4446 makes it hard to use a value of just the sign bit due to
4447 ANSI integer constant typing rules. */
4448 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
4449 && (STORE_FLAG_VALUE
4450 & ((HOST_WIDE_INT
) 1
4451 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
4452 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
4453 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
4454 subtarget
, normalizep
== 1);
4455 else if (STORE_FLAG_VALUE
& 1)
4457 op0
= expand_and (compare_mode
, op0
, const1_rtx
, subtarget
);
4458 if (normalizep
== -1)
4459 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
4464 /* If we were converting to a smaller mode, do the
4466 if (target_mode
!= compare_mode
)
4468 convert_move (target
, op0
, 0);
4476 delete_insns_since (last
);
4478 /* If expensive optimizations, use different pseudo registers for each
4479 insn, instead of reusing the same pseudo. This leads to better CSE,
4480 but slows down the compiler, since there are more pseudos */
4481 subtarget
= (!flag_expensive_optimizations
4482 && (target_mode
== mode
)) ? target
: NULL_RTX
;
4484 /* If we reached here, we can't do this with a scc insn. However, there
4485 are some comparisons that can be done directly. For example, if
4486 this is an equality comparison of integers, we can try to exclusive-or
4487 (or subtract) the two operands and use a recursive call to try the
4488 comparison with zero. Don't do any of these cases if branches are
4492 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
4493 && op1
!= const0_rtx
)
4495 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
4499 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
4502 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
4503 mode
, unsignedp
, normalizep
);
4505 delete_insns_since (last
);
4509 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4510 the constant zero. Reject all other comparisons at this point. Only
4511 do LE and GT if branches are expensive since they are expensive on
4512 2-operand machines. */
4514 if (BRANCH_COST
== 0
4515 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
4516 || (code
!= EQ
&& code
!= NE
4517 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
4520 /* See what we need to return. We can only return a 1, -1, or the
4523 if (normalizep
== 0)
4525 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4526 normalizep
= STORE_FLAG_VALUE
;
4528 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4529 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4530 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
4536 /* Try to put the result of the comparison in the sign bit. Assume we can't
4537 do the necessary operation below. */
4541 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4542 the sign bit set. */
4546 /* This is destructive, so SUBTARGET can't be OP0. */
4547 if (rtx_equal_p (subtarget
, op0
))
4550 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
4553 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
4557 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4558 number of bits in the mode of OP0, minus one. */
4562 if (rtx_equal_p (subtarget
, op0
))
4565 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4566 size_int (GET_MODE_BITSIZE (mode
) - 1),
4568 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
4572 if (code
== EQ
|| code
== NE
)
4574 /* For EQ or NE, one way to do the comparison is to apply an operation
4575 that converts the operand into a positive number if it is non-zero
4576 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4577 for NE we negate. This puts the result in the sign bit. Then we
4578 normalize with a shift, if needed.
4580 Two operations that can do the above actions are ABS and FFS, so try
4581 them. If that doesn't work, and MODE is smaller than a full word,
4582 we can use zero-extension to the wider mode (an unsigned conversion)
4583 as the operation. */
4585 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4586 that is compensated by the subsequent overflow when subtracting
4589 if (abs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4590 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
4591 else if (ffs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4592 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
4593 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
4595 op0
= protect_from_queue (op0
, 0);
4596 tem
= convert_modes (word_mode
, mode
, op0
, 1);
4603 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
4606 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
4609 /* If we couldn't do it that way, for NE we can "or" the two's complement
4610 of the value with itself. For EQ, we take the one's complement of
4611 that "or", which is an extra insn, so we only handle EQ if branches
4614 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
4616 if (rtx_equal_p (subtarget
, op0
))
4619 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
4620 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
4623 if (tem
&& code
== EQ
)
4624 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
4628 if (tem
&& normalizep
)
4629 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
4630 size_int (GET_MODE_BITSIZE (mode
) - 1),
4631 subtarget
, normalizep
== 1);
4635 if (GET_MODE (tem
) != target_mode
)
4637 convert_move (target
, tem
, 0);
4640 else if (!subtarget
)
4642 emit_move_insn (target
, tem
);
4647 delete_insns_since (last
);
4652 /* Like emit_store_flag, but always succeeds. */
4655 emit_store_flag_force (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4659 enum machine_mode mode
;
4665 /* First see if emit_store_flag can do the job. */
4666 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
4670 if (normalizep
== 0)
4673 /* If this failed, we have to do this with set/compare/jump/set code. */
4675 if (GET_CODE (target
) != REG
4676 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
4677 target
= gen_reg_rtx (GET_MODE (target
));
4679 emit_move_insn (target
, const1_rtx
);
4680 label
= gen_label_rtx ();
4681 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
4684 emit_move_insn (target
, const0_rtx
);
4690 /* Perform possibly multi-word comparison and conditional jump to LABEL
4691 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4693 The algorithm is based on the code in expr.c:do_jump.
4695 Note that this does not perform a general comparison. Only variants
4696 generated within expmed.c are correctly handled, others abort (but could
4697 be handled if needed). */
4700 do_cmp_and_jump (arg1
, arg2
, op
, mode
, label
)
4701 rtx arg1
, arg2
, label
;
4703 enum machine_mode mode
;
4705 /* If this mode is an integer too wide to compare properly,
4706 compare word by word. Rely on cse to optimize constant cases. */
4708 if (GET_MODE_CLASS (mode
) == MODE_INT
4709 && ! can_compare_p (op
, mode
, ccp_jump
))
4711 rtx label2
= gen_label_rtx ();
4716 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
4720 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
4724 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
4728 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
4732 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
4735 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4736 that's the only equality operations we do */
4738 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4740 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
4744 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4746 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
4753 emit_label (label2
);
4756 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, label
);