BR2975768: Update AMD LWP instructions to match upcoming changes

BR2975768: Update AMD LWP instructions to match upcoming changes

The former changes have been committed to binutils.
From initial message:

|
| 2010-03-22 Quentin Neill <quentin.neill@amd.com>
|           Sebastian Pop  <sebastian.pop@amd.com>
|
|	opcodes/
|	* i386-dis.c (OP_LWP_I): Removed.
|	(reg_table): Do not use OP_LWP_I, use Iq.
|	(OP_LWPCB_E): Remove use of names16.
|	(OP_LWP_E): Same.
|	* i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
|	should not set the Vex.length bit.
|	* i386-tbl.h: Regenerated.
|
|	gas/
|	* testsuite/gas/i386/x86-64-lwp.s: Remove use of 16bit LWP insns.
|	* testsuite/gas/i386/lwp.s: Same.
|	* testsuite/gas/i386/x86-64-lwp.d: Updated.
|	* testsuite/gas/i386/lwp.d: Updated.
|

So there is no 16 bit instructions anymore.
Also xop.l field should be set to 0.

Based on patch from nasm64developer

Reported-by: nasm64developer
Signed-off-by: nasm64developer
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>